1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
203 // are Legal, f80 is custom lowered.
204 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
207 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
209 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
210 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
212 if (X86ScalarSSEf32) {
213 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
214 // f32 and f64 cases are Legal, f80 case is not
215 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
221 // Handle FP_TO_UINT by promoting the destination to a larger signed
223 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
224 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
225 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
227 if (Subtarget->is64Bit()) {
228 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
229 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
230 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
233 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
234 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 } else if (!Subtarget->useSoftFloat()) {
237 // Since AVX is a superset of SSE3, only check for SSE here.
238 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
239 // Expand FP_TO_UINT into a select.
240 // FIXME: We would like to use a Custom expander here eventually to do
241 // the optimal thing for SSE vs. the default expansion in the legalizer.
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
244 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
249 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
252 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
253 if (!X86ScalarSSEf64) {
254 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
255 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
258 // Without SSE, i64->f64 goes through memory.
259 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
263 // Scalar integer divide and remainder are lowered to use operations that
264 // produce two results, to match the available instructions. This exposes
265 // the two-result form to trivial CSE, which is able to combine x/y and x%y
266 // into a single instruction.
268 // Scalar integer multiply-high is also lowered to use two-result
269 // operations, to match the available instructions. However, plain multiply
270 // (low) operations are left as Legal, as there are single-result
271 // instructions for this in x86. Using the two-result multiply instructions
272 // when both high and low results are needed must be arranged by dagcombine.
273 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
275 setOperationAction(ISD::MULHS, VT, Expand);
276 setOperationAction(ISD::MULHU, VT, Expand);
277 setOperationAction(ISD::SDIV, VT, Expand);
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::UREM, VT, Expand);
282 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
283 setOperationAction(ISD::ADDC, VT, Custom);
284 setOperationAction(ISD::ADDE, VT, Custom);
285 setOperationAction(ISD::SUBC, VT, Custom);
286 setOperationAction(ISD::SUBE, VT, Custom);
289 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
290 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
291 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
292 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
293 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
296 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
305 if (Subtarget->is64Bit())
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
308 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
309 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
310 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
312 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
313 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
314 // is. We should promote the value to 64-bits to solve this.
315 // This is what the CRT headers do - `fmodf` is an inline header
316 // function casting to f64 and calling `fmod`.
317 setOperationAction(ISD::FREM , MVT::f32 , Promote);
319 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->isTarget64BitLP64()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit()) {
502 setOperationAction(ISD::VAARG , MVT::Other, Custom);
503 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
505 // TargetInfo::CharPtrBuiltinVaList
506 setOperationAction(ISD::VAARG , MVT::Other, Expand);
507 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
510 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
511 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
513 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
515 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
516 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
517 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
519 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
520 // f32 and f64 use SSE.
521 // Set up the FP register classes.
522 addRegisterClass(MVT::f32, &X86::FR32RegClass);
523 addRegisterClass(MVT::f64, &X86::FR64RegClass);
525 // Use ANDPD to simulate FABS.
526 setOperationAction(ISD::FABS , MVT::f64, Custom);
527 setOperationAction(ISD::FABS , MVT::f32, Custom);
529 // Use XORP to simulate FNEG.
530 setOperationAction(ISD::FNEG , MVT::f64, Custom);
531 setOperationAction(ISD::FNEG , MVT::f32, Custom);
533 // Use ANDPD and ORPD to simulate FCOPYSIGN.
534 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
535 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
537 // Lower this to FGETSIGNx86 plus an AND.
538 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
539 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
541 // We don't support sin/cos/fmod
542 setOperationAction(ISD::FSIN , MVT::f64, Expand);
543 setOperationAction(ISD::FCOS , MVT::f64, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
545 setOperationAction(ISD::FSIN , MVT::f32, Expand);
546 setOperationAction(ISD::FCOS , MVT::f32, Expand);
547 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
549 // Expand FP immediates into loads from the stack, except for the special
551 addLegalFPImmediate(APFloat(+0.0)); // xorpd
552 addLegalFPImmediate(APFloat(+0.0f)); // xorps
553 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
554 // Use SSE for f32, x87 for f64.
555 // Set up the FP register classes.
556 addRegisterClass(MVT::f32, &X86::FR32RegClass);
557 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
559 // Use ANDPS to simulate FABS.
560 setOperationAction(ISD::FABS , MVT::f32, Custom);
562 // Use XORP to simulate FNEG.
563 setOperationAction(ISD::FNEG , MVT::f32, Custom);
565 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
567 // Use ANDPS and ORPS to simulate FCOPYSIGN.
568 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
569 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
571 // We don't support sin/cos/fmod
572 setOperationAction(ISD::FSIN , MVT::f32, Expand);
573 setOperationAction(ISD::FCOS , MVT::f32, Expand);
574 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
576 // Special cases we handle for FP constants.
577 addLegalFPImmediate(APFloat(+0.0f)); // xorps
578 addLegalFPImmediate(APFloat(+0.0)); // FLD0
579 addLegalFPImmediate(APFloat(+1.0)); // FLD1
580 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
581 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
583 if (!TM.Options.UnsafeFPMath) {
584 setOperationAction(ISD::FSIN , MVT::f64, Expand);
585 setOperationAction(ISD::FCOS , MVT::f64, Expand);
586 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
588 } else if (!Subtarget->useSoftFloat()) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
592 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
599 if (!TM.Options.UnsafeFPMath) {
600 setOperationAction(ISD::FSIN , MVT::f64, Expand);
601 setOperationAction(ISD::FSIN , MVT::f32, Expand);
602 setOperationAction(ISD::FCOS , MVT::f64, Expand);
603 setOperationAction(ISD::FCOS , MVT::f32, Expand);
604 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
607 addLegalFPImmediate(APFloat(+0.0)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
611 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
612 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
613 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
614 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
617 // We don't support FMA.
618 setOperationAction(ISD::FMA, MVT::f64, Expand);
619 setOperationAction(ISD::FMA, MVT::f32, Expand);
621 // Long double always uses X87.
622 if (!Subtarget->useSoftFloat()) {
623 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
624 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
625 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
627 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
628 addLegalFPImmediate(TmpFlt); // FLD0
630 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
633 APFloat TmpFlt2(+1.0);
634 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
636 addLegalFPImmediate(TmpFlt2); // FLD1
637 TmpFlt2.changeSign();
638 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
641 if (!TM.Options.UnsafeFPMath) {
642 setOperationAction(ISD::FSIN , MVT::f80, Expand);
643 setOperationAction(ISD::FCOS , MVT::f80, Expand);
644 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
647 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
648 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
649 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
650 setOperationAction(ISD::FRINT, MVT::f80, Expand);
651 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
652 setOperationAction(ISD::FMA, MVT::f80, Expand);
655 // Always use a library call for pow.
656 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
657 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
660 setOperationAction(ISD::FLOG, MVT::f80, Expand);
661 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
663 setOperationAction(ISD::FEXP, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
665 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
666 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
668 // First set operation action for all vector types to either promote
669 // (for widening) or expand (for scalarization). Then we will selectively
670 // turn on ones that can be effectively codegen'd.
671 for (MVT VT : MVT::vector_valuetypes()) {
672 setOperationAction(ISD::ADD , VT, Expand);
673 setOperationAction(ISD::SUB , VT, Expand);
674 setOperationAction(ISD::FADD, VT, Expand);
675 setOperationAction(ISD::FNEG, VT, Expand);
676 setOperationAction(ISD::FSUB, VT, Expand);
677 setOperationAction(ISD::MUL , VT, Expand);
678 setOperationAction(ISD::FMUL, VT, Expand);
679 setOperationAction(ISD::SDIV, VT, Expand);
680 setOperationAction(ISD::UDIV, VT, Expand);
681 setOperationAction(ISD::FDIV, VT, Expand);
682 setOperationAction(ISD::SREM, VT, Expand);
683 setOperationAction(ISD::UREM, VT, Expand);
684 setOperationAction(ISD::LOAD, VT, Expand);
685 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
686 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
687 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
688 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
689 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::FABS, VT, Expand);
691 setOperationAction(ISD::FSIN, VT, Expand);
692 setOperationAction(ISD::FSINCOS, VT, Expand);
693 setOperationAction(ISD::FCOS, VT, Expand);
694 setOperationAction(ISD::FSINCOS, VT, Expand);
695 setOperationAction(ISD::FREM, VT, Expand);
696 setOperationAction(ISD::FMA, VT, Expand);
697 setOperationAction(ISD::FPOWI, VT, Expand);
698 setOperationAction(ISD::FSQRT, VT, Expand);
699 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
700 setOperationAction(ISD::FFLOOR, VT, Expand);
701 setOperationAction(ISD::FCEIL, VT, Expand);
702 setOperationAction(ISD::FTRUNC, VT, Expand);
703 setOperationAction(ISD::FRINT, VT, Expand);
704 setOperationAction(ISD::FNEARBYINT, VT, Expand);
705 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
706 setOperationAction(ISD::MULHS, VT, Expand);
707 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
708 setOperationAction(ISD::MULHU, VT, Expand);
709 setOperationAction(ISD::SDIVREM, VT, Expand);
710 setOperationAction(ISD::UDIVREM, VT, Expand);
711 setOperationAction(ISD::FPOW, VT, Expand);
712 setOperationAction(ISD::CTPOP, VT, Expand);
713 setOperationAction(ISD::CTTZ, VT, Expand);
714 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
715 setOperationAction(ISD::CTLZ, VT, Expand);
716 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
717 setOperationAction(ISD::SHL, VT, Expand);
718 setOperationAction(ISD::SRA, VT, Expand);
719 setOperationAction(ISD::SRL, VT, Expand);
720 setOperationAction(ISD::ROTL, VT, Expand);
721 setOperationAction(ISD::ROTR, VT, Expand);
722 setOperationAction(ISD::BSWAP, VT, Expand);
723 setOperationAction(ISD::SETCC, VT, Expand);
724 setOperationAction(ISD::FLOG, VT, Expand);
725 setOperationAction(ISD::FLOG2, VT, Expand);
726 setOperationAction(ISD::FLOG10, VT, Expand);
727 setOperationAction(ISD::FEXP, VT, Expand);
728 setOperationAction(ISD::FEXP2, VT, Expand);
729 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
730 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
731 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
732 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
734 setOperationAction(ISD::TRUNCATE, VT, Expand);
735 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
736 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
737 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
738 setOperationAction(ISD::VSELECT, VT, Expand);
739 setOperationAction(ISD::SELECT_CC, VT, Expand);
740 for (MVT InnerVT : MVT::vector_valuetypes()) {
741 setTruncStoreAction(InnerVT, VT, Expand);
743 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
744 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
746 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
747 // types, we have to deal with them whether we ask for Expansion or not.
748 // Setting Expand causes its own optimisation problems though, so leave
750 if (VT.getVectorElementType() == MVT::i1)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
753 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
754 // split/scalarized right now.
755 if (VT.getVectorElementType() == MVT::f16)
756 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
760 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
761 // with -msoft-float, disable use of MMX as well.
762 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
763 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
764 // No operations on x86mmx supported, everything uses intrinsics.
767 // MMX-sized vectors (other than x86mmx) are expected to be expanded
768 // into smaller operations.
769 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
770 setOperationAction(ISD::MULHS, MMXTy, Expand);
771 setOperationAction(ISD::AND, MMXTy, Expand);
772 setOperationAction(ISD::OR, MMXTy, Expand);
773 setOperationAction(ISD::XOR, MMXTy, Expand);
774 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
775 setOperationAction(ISD::SELECT, MMXTy, Expand);
776 setOperationAction(ISD::BITCAST, MMXTy, Expand);
778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
780 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
781 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
783 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
785 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
786 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
787 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
788 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
789 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
790 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
791 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
792 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
793 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
794 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
795 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
796 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
799 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
800 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
802 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
803 // registers cannot be used even for integer operations.
804 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
805 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
806 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
807 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
809 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
810 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
811 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
812 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
813 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
814 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
815 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
816 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
817 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
819 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
820 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
821 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
822 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
823 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
824 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
825 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
827 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
828 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
829 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
830 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
831 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
833 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
834 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
835 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
836 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
838 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
839 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
840 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
841 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
843 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
854 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
857 // ISD::CTTZ v2i64 - scalarization is faster.
858 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
861 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
863 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
864 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
865 MVT VT = (MVT::SimpleValueType)i;
866 // Do not attempt to custom lower non-power-of-2 vectors
867 if (!isPowerOf2_32(VT.getVectorNumElements()))
869 // Do not attempt to custom lower non-128-bit vectors
870 if (!VT.is128BitVector())
872 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
873 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
874 setOperationAction(ISD::VSELECT, VT, Custom);
875 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
878 // We support custom legalizing of sext and anyext loads for specific
879 // memory vector types which we can load as a scalar (or sequence of
880 // scalars) and extend in-register to a legal 128-bit vector type. For sext
881 // loads these must work with a single scalar load.
882 for (MVT VT : MVT::integer_vector_valuetypes()) {
883 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
886 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
887 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
888 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
889 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
890 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
891 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
899 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
903 if (Subtarget->is64Bit()) {
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
908 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
909 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
910 MVT VT = (MVT::SimpleValueType)i;
912 // Do not attempt to promote non-128-bit vectors
913 if (!VT.is128BitVector())
916 setOperationAction(ISD::AND, VT, Promote);
917 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
918 setOperationAction(ISD::OR, VT, Promote);
919 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
920 setOperationAction(ISD::XOR, VT, Promote);
921 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
922 setOperationAction(ISD::LOAD, VT, Promote);
923 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
924 setOperationAction(ISD::SELECT, VT, Promote);
925 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
939 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
941 // As there is no 64-bit GPR available, we need build a special custom
942 // sequence to convert from v2i32 to v2f32.
943 if (!Subtarget->is64Bit())
944 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
946 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
949 for (MVT VT : MVT::fp_vector_valuetypes())
950 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
952 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
953 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
957 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
958 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
959 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
960 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
961 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
962 setOperationAction(ISD::FRINT, RoundedTy, Legal);
963 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
966 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
967 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
970 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
971 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
972 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
973 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
975 // FIXME: Do we need to handle scalar-to-vector here?
976 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
978 // We directly match byte blends in the backend as they match the VSELECT
980 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
982 // SSE41 brings specific instructions for doing vector sign extend even in
983 // cases where we don't have SRA.
984 for (MVT VT : MVT::integer_vector_valuetypes()) {
985 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
990 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
991 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
998 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1005 // i8 and i16 vectors are custom because the source register and source
1006 // source memory operand types are not the same width. f32 vectors are
1007 // custom since the immediate controlling the insert encodes additional
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1019 // FIXME: these should be Legal, but that's only for the case where
1020 // the index is constant. For now custom expand to deal with that.
1021 if (Subtarget->is64Bit()) {
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1027 if (Subtarget->hasSSE2()) {
1028 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1032 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1041 // In the customized shift lowering, the legal cases in AVX2 will be
1043 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1049 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1050 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1053 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1054 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1059 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1061 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1063 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1065 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1075 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1076 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1078 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1088 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1089 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1091 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1092 // even though v8i16 is a legal type.
1093 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1095 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1098 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1099 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1102 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1104 for (MVT VT : MVT::fp_vector_valuetypes())
1105 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1110 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1111 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1113 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1114 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1119 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1123 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1127 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1130 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1133 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1136 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1141 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1146 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1150 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1152 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1153 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1155 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1156 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1157 setOperationAction(ISD::FMA, MVT::f32, Legal);
1158 setOperationAction(ISD::FMA, MVT::f64, Legal);
1161 if (Subtarget->hasInt256()) {
1162 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1163 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1164 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1165 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1167 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1168 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1169 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1170 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1172 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1173 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1174 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1175 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1177 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1179 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1180 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1184 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1187 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1190 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1193 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1195 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1196 // when we have a 256bit-wide blend with immediate.
1197 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1199 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1205 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1212 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1214 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1231 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1234 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1240 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1243 // In the customized shift lowering, the legal cases in AVX2 will be
1245 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1246 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1248 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1254 // Custom lower several nodes for 256-bit types.
1255 for (MVT VT : MVT::vector_valuetypes()) {
1256 if (VT.getScalarSizeInBits() >= 32) {
1257 setOperationAction(ISD::MLOAD, VT, Legal);
1258 setOperationAction(ISD::MSTORE, VT, Legal);
1260 // Extract subvector is special because the value type
1261 // (result) is 128-bit but the source is 256-bit wide.
1262 if (VT.is128BitVector()) {
1263 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1265 // Do not attempt to custom lower other non-256-bit vectors
1266 if (!VT.is256BitVector())
1269 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1270 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1271 setOperationAction(ISD::VSELECT, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 if (Subtarget->hasInt256())
1280 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1310 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1311 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1313 for (MVT VT : MVT::fp_vector_valuetypes())
1314 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1316 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1317 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1318 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1319 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1320 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1321 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1322 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1323 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1324 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1325 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1326 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1327 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1329 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1330 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1331 setOperationAction(ISD::XOR, MVT::i1, Legal);
1332 setOperationAction(ISD::OR, MVT::i1, Legal);
1333 setOperationAction(ISD::AND, MVT::i1, Legal);
1334 setOperationAction(ISD::SUB, MVT::i1, Custom);
1335 setOperationAction(ISD::ADD, MVT::i1, Custom);
1336 setOperationAction(ISD::MUL, MVT::i1, Custom);
1337 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1339 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1340 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1341 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1343 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1344 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1345 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1347 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1350 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1352 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1354 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1355 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1356 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1357 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1359 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1360 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1361 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1362 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1363 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1364 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1365 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1366 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1367 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1368 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1369 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1370 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1371 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1372 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1373 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1374 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1376 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1377 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1378 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1379 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1380 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1381 if (Subtarget->hasVLX()){
1382 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1383 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1384 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1385 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1386 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1388 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1389 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1390 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1391 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1392 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1394 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1396 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1397 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1398 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1399 if (Subtarget->hasDQI()) {
1400 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1401 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1403 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1404 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1406 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1407 if (Subtarget->hasVLX()) {
1408 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1418 if (Subtarget->hasVLX()) {
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1422 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1425 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1426 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1428 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1440 if (Subtarget->hasDQI()) {
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1444 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1446 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1448 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1449 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1450 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1451 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1452 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1453 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1461 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1464 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1466 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1468 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1470 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1472 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1476 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1478 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1479 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1480 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1481 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1482 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1483 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1484 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1485 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1487 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1488 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1490 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1491 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1493 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1495 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1498 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1499 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1501 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1502 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1504 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1505 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1506 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1507 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1508 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1509 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1511 if (Subtarget->hasCDI()) {
1512 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1513 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1517 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1518 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1520 if (Subtarget->hasVLX() && Subtarget->hasCDI()) {
1521 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1522 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1523 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1524 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1527 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1531 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1532 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1533 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1535 if (Subtarget->hasDQI()) {
1536 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1537 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1538 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1540 // Custom lower several nodes.
1541 for (MVT VT : MVT::vector_valuetypes()) {
1542 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1544 setOperationAction(ISD::AND, VT, Legal);
1545 setOperationAction(ISD::OR, VT, Legal);
1546 setOperationAction(ISD::XOR, VT, Legal);
1548 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1549 setOperationAction(ISD::MGATHER, VT, Custom);
1550 setOperationAction(ISD::MSCATTER, VT, Custom);
1552 // Extract subvector is special because the value type
1553 // (result) is 256/128-bit but the source is 512-bit wide.
1554 if (VT.is128BitVector() || VT.is256BitVector()) {
1555 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1557 if (VT.getVectorElementType() == MVT::i1)
1558 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1560 // Do not attempt to custom lower other non-512-bit vectors
1561 if (!VT.is512BitVector())
1564 if (EltSize >= 32) {
1565 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1566 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1567 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1568 setOperationAction(ISD::VSELECT, VT, Legal);
1569 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1570 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1571 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1572 setOperationAction(ISD::MLOAD, VT, Legal);
1573 setOperationAction(ISD::MSTORE, VT, Legal);
1576 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1577 MVT VT = (MVT::SimpleValueType)i;
1579 // Do not attempt to promote non-512-bit vectors.
1580 if (!VT.is512BitVector())
1583 setOperationAction(ISD::SELECT, VT, Promote);
1584 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1588 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1589 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1590 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1592 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1593 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1595 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1596 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1597 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1598 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1599 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1600 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1601 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1602 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1603 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1604 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1605 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1606 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1607 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1608 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1609 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1610 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1611 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1612 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1613 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1614 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1615 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1616 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1617 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1618 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1619 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1620 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1621 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1622 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1623 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1624 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1625 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1626 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1627 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1628 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1629 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1630 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1631 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1632 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1633 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1635 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1636 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1637 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1638 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1639 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1640 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1641 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1642 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1644 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1645 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1646 if (Subtarget->hasVLX())
1647 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1649 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1650 const MVT VT = (MVT::SimpleValueType)i;
1652 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1654 // Do not attempt to promote non-512-bit vectors.
1655 if (!VT.is512BitVector())
1659 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1660 setOperationAction(ISD::VSELECT, VT, Legal);
1665 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1666 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1667 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1669 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1670 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1671 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1672 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1673 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1674 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1675 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1676 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1677 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1678 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1679 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1680 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1682 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1683 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1684 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1685 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1686 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1687 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1688 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1689 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1691 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1692 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1693 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1694 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1695 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1696 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1697 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1698 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1701 // We want to custom lower some of our intrinsics.
1702 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1703 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1704 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1705 if (!Subtarget->is64Bit())
1706 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1708 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1709 // handle type legalization for these operations here.
1711 // FIXME: We really should do custom legalization for addition and
1712 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1713 // than generic legalization for 64-bit multiplication-with-overflow, though.
1714 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1715 // Add/Sub/Mul with overflow operations are custom lowered.
1717 setOperationAction(ISD::SADDO, VT, Custom);
1718 setOperationAction(ISD::UADDO, VT, Custom);
1719 setOperationAction(ISD::SSUBO, VT, Custom);
1720 setOperationAction(ISD::USUBO, VT, Custom);
1721 setOperationAction(ISD::SMULO, VT, Custom);
1722 setOperationAction(ISD::UMULO, VT, Custom);
1725 if (!Subtarget->is64Bit()) {
1726 // These libcalls are not available in 32-bit.
1727 setLibcallName(RTLIB::SHL_I128, nullptr);
1728 setLibcallName(RTLIB::SRL_I128, nullptr);
1729 setLibcallName(RTLIB::SRA_I128, nullptr);
1732 // Combine sin / cos into one node or libcall if possible.
1733 if (Subtarget->hasSinCos()) {
1734 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1735 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1736 if (Subtarget->isTargetDarwin()) {
1737 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1738 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1739 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1740 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1744 if (Subtarget->isTargetWin64()) {
1745 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1746 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1747 setOperationAction(ISD::SREM, MVT::i128, Custom);
1748 setOperationAction(ISD::UREM, MVT::i128, Custom);
1749 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1750 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1753 // We have target-specific dag combine patterns for the following nodes:
1754 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1755 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1756 setTargetDAGCombine(ISD::BITCAST);
1757 setTargetDAGCombine(ISD::VSELECT);
1758 setTargetDAGCombine(ISD::SELECT);
1759 setTargetDAGCombine(ISD::SHL);
1760 setTargetDAGCombine(ISD::SRA);
1761 setTargetDAGCombine(ISD::SRL);
1762 setTargetDAGCombine(ISD::OR);
1763 setTargetDAGCombine(ISD::AND);
1764 setTargetDAGCombine(ISD::ADD);
1765 setTargetDAGCombine(ISD::FADD);
1766 setTargetDAGCombine(ISD::FSUB);
1767 setTargetDAGCombine(ISD::FMA);
1768 setTargetDAGCombine(ISD::SUB);
1769 setTargetDAGCombine(ISD::LOAD);
1770 setTargetDAGCombine(ISD::MLOAD);
1771 setTargetDAGCombine(ISD::STORE);
1772 setTargetDAGCombine(ISD::MSTORE);
1773 setTargetDAGCombine(ISD::ZERO_EXTEND);
1774 setTargetDAGCombine(ISD::ANY_EXTEND);
1775 setTargetDAGCombine(ISD::SIGN_EXTEND);
1776 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1777 setTargetDAGCombine(ISD::SINT_TO_FP);
1778 setTargetDAGCombine(ISD::UINT_TO_FP);
1779 setTargetDAGCombine(ISD::SETCC);
1780 setTargetDAGCombine(ISD::BUILD_VECTOR);
1781 setTargetDAGCombine(ISD::MUL);
1782 setTargetDAGCombine(ISD::XOR);
1784 computeRegisterProperties(Subtarget->getRegisterInfo());
1786 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1787 MaxStoresPerMemsetOptSize = 8;
1788 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1789 MaxStoresPerMemcpyOptSize = 4;
1790 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1791 MaxStoresPerMemmoveOptSize = 4;
1792 setPrefLoopAlignment(4); // 2^4 bytes.
1794 // A predictable cmov does not hurt on an in-order CPU.
1795 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1796 PredictableSelectIsExpensive = !Subtarget->isAtom();
1797 EnableExtLdPromotion = true;
1798 setPrefFunctionAlignment(4); // 2^4 bytes.
1800 verifyIntrinsicTables();
1803 // This has so far only been implemented for 64-bit MachO.
1804 bool X86TargetLowering::useLoadStackGuardNode() const {
1805 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1808 TargetLoweringBase::LegalizeTypeAction
1809 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1810 if (ExperimentalVectorWideningLegalization &&
1811 VT.getVectorNumElements() != 1 &&
1812 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1813 return TypeWidenVector;
1815 return TargetLoweringBase::getPreferredVectorAction(VT);
1818 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1821 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1823 const unsigned NumElts = VT.getVectorNumElements();
1824 const EVT EltVT = VT.getVectorElementType();
1825 if (VT.is512BitVector()) {
1826 if (Subtarget->hasAVX512())
1827 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1828 EltVT == MVT::f32 || EltVT == MVT::f64)
1830 case 8: return MVT::v8i1;
1831 case 16: return MVT::v16i1;
1833 if (Subtarget->hasBWI())
1834 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1836 case 32: return MVT::v32i1;
1837 case 64: return MVT::v64i1;
1841 if (VT.is256BitVector() || VT.is128BitVector()) {
1842 if (Subtarget->hasVLX())
1843 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1844 EltVT == MVT::f32 || EltVT == MVT::f64)
1846 case 2: return MVT::v2i1;
1847 case 4: return MVT::v4i1;
1848 case 8: return MVT::v8i1;
1850 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1851 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1853 case 8: return MVT::v8i1;
1854 case 16: return MVT::v16i1;
1855 case 32: return MVT::v32i1;
1859 return VT.changeVectorElementTypeToInteger();
1862 /// Helper for getByValTypeAlignment to determine
1863 /// the desired ByVal argument alignment.
1864 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1867 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1868 if (VTy->getBitWidth() == 128)
1870 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1871 unsigned EltAlign = 0;
1872 getMaxByValAlign(ATy->getElementType(), EltAlign);
1873 if (EltAlign > MaxAlign)
1874 MaxAlign = EltAlign;
1875 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1876 for (auto *EltTy : STy->elements()) {
1877 unsigned EltAlign = 0;
1878 getMaxByValAlign(EltTy, EltAlign);
1879 if (EltAlign > MaxAlign)
1880 MaxAlign = EltAlign;
1887 /// Return the desired alignment for ByVal aggregate
1888 /// function arguments in the caller parameter area. For X86, aggregates
1889 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1890 /// are at 4-byte boundaries.
1891 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1892 const DataLayout &DL) const {
1893 if (Subtarget->is64Bit()) {
1894 // Max of 8 and alignment of type.
1895 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1902 if (Subtarget->hasSSE1())
1903 getMaxByValAlign(Ty, Align);
1907 /// Returns the target specific optimal type for load
1908 /// and store operations as a result of memset, memcpy, and memmove
1909 /// lowering. If DstAlign is zero that means it's safe to destination
1910 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1911 /// means there isn't a need to check it against alignment requirement,
1912 /// probably because the source does not need to be loaded. If 'IsMemset' is
1913 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1914 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1915 /// source is constant so it does not need to be loaded.
1916 /// It returns EVT::Other if the type should be determined using generic
1917 /// target-independent logic.
1919 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1920 unsigned DstAlign, unsigned SrcAlign,
1921 bool IsMemset, bool ZeroMemset,
1923 MachineFunction &MF) const {
1924 const Function *F = MF.getFunction();
1925 if ((!IsMemset || ZeroMemset) &&
1926 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1928 (!Subtarget->isUnalignedMem16Slow() ||
1929 ((DstAlign == 0 || DstAlign >= 16) &&
1930 (SrcAlign == 0 || SrcAlign >= 16)))) {
1932 // FIXME: Check if unaligned 32-byte accesses are slow.
1933 if (Subtarget->hasInt256())
1935 if (Subtarget->hasFp256())
1938 if (Subtarget->hasSSE2())
1940 if (Subtarget->hasSSE1())
1942 } else if (!MemcpyStrSrc && Size >= 8 &&
1943 !Subtarget->is64Bit() &&
1944 Subtarget->hasSSE2()) {
1945 // Do not use f64 to lower memcpy if source is string constant. It's
1946 // better to use i32 to avoid the loads.
1950 // This is a compromise. If we reach here, unaligned accesses may be slow on
1951 // this target. However, creating smaller, aligned accesses could be even
1952 // slower and would certainly be a lot more code.
1953 if (Subtarget->is64Bit() && Size >= 8)
1958 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1960 return X86ScalarSSEf32;
1961 else if (VT == MVT::f64)
1962 return X86ScalarSSEf64;
1967 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1972 switch (VT.getSizeInBits()) {
1974 // 8-byte and under are always assumed to be fast.
1978 *Fast = !Subtarget->isUnalignedMem16Slow();
1981 *Fast = !Subtarget->isUnalignedMem32Slow();
1983 // TODO: What about AVX-512 (512-bit) accesses?
1986 // Misaligned accesses of any size are always allowed.
1990 /// Return the entry encoding for a jump table in the
1991 /// current function. The returned value is a member of the
1992 /// MachineJumpTableInfo::JTEntryKind enum.
1993 unsigned X86TargetLowering::getJumpTableEncoding() const {
1994 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1996 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1997 Subtarget->isPICStyleGOT())
1998 return MachineJumpTableInfo::EK_Custom32;
2000 // Otherwise, use the normal jump table encoding heuristics.
2001 return TargetLowering::getJumpTableEncoding();
2004 bool X86TargetLowering::useSoftFloat() const {
2005 return Subtarget->useSoftFloat();
2009 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2010 const MachineBasicBlock *MBB,
2011 unsigned uid,MCContext &Ctx) const{
2012 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2013 Subtarget->isPICStyleGOT());
2014 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2016 return MCSymbolRefExpr::create(MBB->getSymbol(),
2017 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2020 /// Returns relocation base for the given PIC jumptable.
2021 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2022 SelectionDAG &DAG) const {
2023 if (!Subtarget->is64Bit())
2024 // This doesn't have SDLoc associated with it, but is not really the
2025 // same as a Register.
2026 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2027 getPointerTy(DAG.getDataLayout()));
2031 /// This returns the relocation base for the given PIC jumptable,
2032 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2033 const MCExpr *X86TargetLowering::
2034 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2035 MCContext &Ctx) const {
2036 // X86-64 uses RIP relative addressing based on the jump table label.
2037 if (Subtarget->isPICStyleRIPRel())
2038 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2040 // Otherwise, the reference is relative to the PIC base.
2041 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2044 std::pair<const TargetRegisterClass *, uint8_t>
2045 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2047 const TargetRegisterClass *RRC = nullptr;
2049 switch (VT.SimpleTy) {
2051 return TargetLowering::findRepresentativeClass(TRI, VT);
2052 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2053 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2056 RRC = &X86::VR64RegClass;
2058 case MVT::f32: case MVT::f64:
2059 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2060 case MVT::v4f32: case MVT::v2f64:
2061 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2063 RRC = &X86::VR128RegClass;
2066 return std::make_pair(RRC, Cost);
2069 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2070 unsigned &Offset) const {
2071 if (!Subtarget->isTargetLinux())
2074 if (Subtarget->is64Bit()) {
2075 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2077 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2089 /// Android provides a fixed TLS slot for the SafeStack pointer.
2090 /// See the definition of TLS_SLOT_SAFESTACK in
2091 /// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2092 bool X86TargetLowering::getSafeStackPointerLocation(unsigned &AddressSpace,
2093 unsigned &Offset) const {
2094 if (!Subtarget->isTargetAndroid())
2097 if (Subtarget->is64Bit()) {
2098 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2100 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2112 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2113 unsigned DestAS) const {
2114 assert(SrcAS != DestAS && "Expected different address spaces!");
2116 return SrcAS < 256 && DestAS < 256;
2119 //===----------------------------------------------------------------------===//
2120 // Return Value Calling Convention Implementation
2121 //===----------------------------------------------------------------------===//
2123 #include "X86GenCallingConv.inc"
2125 bool X86TargetLowering::CanLowerReturn(
2126 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2127 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2128 SmallVector<CCValAssign, 16> RVLocs;
2129 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2130 return CCInfo.CheckReturn(Outs, RetCC_X86);
2133 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2134 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2139 X86TargetLowering::LowerReturn(SDValue Chain,
2140 CallingConv::ID CallConv, bool isVarArg,
2141 const SmallVectorImpl<ISD::OutputArg> &Outs,
2142 const SmallVectorImpl<SDValue> &OutVals,
2143 SDLoc dl, SelectionDAG &DAG) const {
2144 MachineFunction &MF = DAG.getMachineFunction();
2145 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2147 SmallVector<CCValAssign, 16> RVLocs;
2148 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2149 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2152 SmallVector<SDValue, 6> RetOps;
2153 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2154 // Operand #1 = Bytes To Pop
2155 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2158 // Copy the result values into the output registers.
2159 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2160 CCValAssign &VA = RVLocs[i];
2161 assert(VA.isRegLoc() && "Can only return in registers!");
2162 SDValue ValToCopy = OutVals[i];
2163 EVT ValVT = ValToCopy.getValueType();
2165 // Promote values to the appropriate types.
2166 if (VA.getLocInfo() == CCValAssign::SExt)
2167 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2168 else if (VA.getLocInfo() == CCValAssign::ZExt)
2169 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2170 else if (VA.getLocInfo() == CCValAssign::AExt) {
2171 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2172 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2174 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2176 else if (VA.getLocInfo() == CCValAssign::BCvt)
2177 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2179 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2180 "Unexpected FP-extend for return value.");
2182 // If this is x86-64, and we disabled SSE, we can't return FP values,
2183 // or SSE or MMX vectors.
2184 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2185 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2186 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2187 report_fatal_error("SSE register return with SSE disabled");
2189 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2190 // llvm-gcc has never done it right and no one has noticed, so this
2191 // should be OK for now.
2192 if (ValVT == MVT::f64 &&
2193 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2194 report_fatal_error("SSE2 register return with SSE2 disabled");
2196 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2197 // the RET instruction and handled by the FP Stackifier.
2198 if (VA.getLocReg() == X86::FP0 ||
2199 VA.getLocReg() == X86::FP1) {
2200 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2201 // change the value to the FP stack register class.
2202 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2203 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2204 RetOps.push_back(ValToCopy);
2205 // Don't emit a copytoreg.
2209 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2210 // which is returned in RAX / RDX.
2211 if (Subtarget->is64Bit()) {
2212 if (ValVT == MVT::x86mmx) {
2213 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2214 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2215 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2217 // If we don't have SSE2 available, convert to v4f32 so the generated
2218 // register is legal.
2219 if (!Subtarget->hasSSE2())
2220 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2225 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2226 Flag = Chain.getValue(1);
2227 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2230 // All x86 ABIs require that for returning structs by value we copy
2231 // the sret argument into %rax/%eax (depending on ABI) for the return.
2232 // We saved the argument into a virtual register in the entry block,
2233 // so now we copy the value out and into %rax/%eax.
2235 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2236 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2237 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2238 // either case FuncInfo->setSRetReturnReg() will have been called.
2239 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2240 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2241 getPointerTy(MF.getDataLayout()));
2244 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2245 X86::RAX : X86::EAX;
2246 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2247 Flag = Chain.getValue(1);
2249 // RAX/EAX now acts like a return value.
2251 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2254 RetOps[0] = Chain; // Update chain.
2256 // Add the flag if we have it.
2258 RetOps.push_back(Flag);
2260 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2263 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2264 if (N->getNumValues() != 1)
2266 if (!N->hasNUsesOfValue(1, 0))
2269 SDValue TCChain = Chain;
2270 SDNode *Copy = *N->use_begin();
2271 if (Copy->getOpcode() == ISD::CopyToReg) {
2272 // If the copy has a glue operand, we conservatively assume it isn't safe to
2273 // perform a tail call.
2274 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2276 TCChain = Copy->getOperand(0);
2277 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2280 bool HasRet = false;
2281 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2283 if (UI->getOpcode() != X86ISD::RET_FLAG)
2285 // If we are returning more than one value, we can definitely
2286 // not make a tail call see PR19530
2287 if (UI->getNumOperands() > 4)
2289 if (UI->getNumOperands() == 4 &&
2290 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2303 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2304 ISD::NodeType ExtendKind) const {
2306 // TODO: Is this also valid on 32-bit?
2307 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2308 ReturnMVT = MVT::i8;
2310 ReturnMVT = MVT::i32;
2312 EVT MinVT = getRegisterType(Context, ReturnMVT);
2313 return VT.bitsLT(MinVT) ? MinVT : VT;
2316 /// Lower the result values of a call into the
2317 /// appropriate copies out of appropriate physical registers.
2320 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2321 CallingConv::ID CallConv, bool isVarArg,
2322 const SmallVectorImpl<ISD::InputArg> &Ins,
2323 SDLoc dl, SelectionDAG &DAG,
2324 SmallVectorImpl<SDValue> &InVals) const {
2326 // Assign locations to each value returned by this call.
2327 SmallVector<CCValAssign, 16> RVLocs;
2328 bool Is64Bit = Subtarget->is64Bit();
2329 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2331 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2333 // Copy all of the result registers out of their specified physreg.
2334 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2335 CCValAssign &VA = RVLocs[i];
2336 EVT CopyVT = VA.getLocVT();
2338 // If this is x86-64, and we disabled SSE, we can't return FP values
2339 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2340 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2341 report_fatal_error("SSE register return with SSE disabled");
2344 // If we prefer to use the value in xmm registers, copy it out as f80 and
2345 // use a truncate to move it from fp stack reg to xmm reg.
2346 bool RoundAfterCopy = false;
2347 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2348 isScalarFPTypeInSSEReg(VA.getValVT())) {
2350 RoundAfterCopy = (CopyVT != VA.getLocVT());
2353 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2354 CopyVT, InFlag).getValue(1);
2355 SDValue Val = Chain.getValue(0);
2358 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2359 // This truncation won't change the value.
2360 DAG.getIntPtrConstant(1, dl));
2362 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2363 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2365 InFlag = Chain.getValue(2);
2366 InVals.push_back(Val);
2372 //===----------------------------------------------------------------------===//
2373 // C & StdCall & Fast Calling Convention implementation
2374 //===----------------------------------------------------------------------===//
2375 // StdCall calling convention seems to be standard for many Windows' API
2376 // routines and around. It differs from C calling convention just a little:
2377 // callee should clean up the stack, not caller. Symbols should be also
2378 // decorated in some fancy way :) It doesn't support any vector arguments.
2379 // For info on fast calling convention see Fast Calling Convention (tail call)
2380 // implementation LowerX86_32FastCCCallTo.
2382 /// CallIsStructReturn - Determines whether a call uses struct return
2384 enum StructReturnType {
2389 static StructReturnType
2390 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2392 return NotStructReturn;
2394 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2395 if (!Flags.isSRet())
2396 return NotStructReturn;
2397 if (Flags.isInReg())
2398 return RegStructReturn;
2399 return StackStructReturn;
2402 /// Determines whether a function uses struct return semantics.
2403 static StructReturnType
2404 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2406 return NotStructReturn;
2408 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2409 if (!Flags.isSRet())
2410 return NotStructReturn;
2411 if (Flags.isInReg())
2412 return RegStructReturn;
2413 return StackStructReturn;
2416 /// Make a copy of an aggregate at address specified by "Src" to address
2417 /// "Dst" with size and alignment information specified by the specific
2418 /// parameter attribute. The copy will be passed as a byval function parameter.
2420 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2421 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2423 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2425 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2426 /*isVolatile*/false, /*AlwaysInline=*/true,
2427 /*isTailCall*/false,
2428 MachinePointerInfo(), MachinePointerInfo());
2431 /// Return true if the calling convention is one that
2432 /// supports tail call optimization.
2433 static bool IsTailCallConvention(CallingConv::ID CC) {
2434 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2435 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2438 /// \brief Return true if the calling convention is a C calling convention.
2439 static bool IsCCallConvention(CallingConv::ID CC) {
2440 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2441 CC == CallingConv::X86_64_SysV);
2444 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2446 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2447 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2451 CallingConv::ID CalleeCC = CS.getCallingConv();
2452 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2458 /// Return true if the function is being made into
2459 /// a tailcall target by changing its ABI.
2460 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2461 bool GuaranteedTailCallOpt) {
2462 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2466 X86TargetLowering::LowerMemArgument(SDValue Chain,
2467 CallingConv::ID CallConv,
2468 const SmallVectorImpl<ISD::InputArg> &Ins,
2469 SDLoc dl, SelectionDAG &DAG,
2470 const CCValAssign &VA,
2471 MachineFrameInfo *MFI,
2473 // Create the nodes corresponding to a load from this parameter slot.
2474 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2475 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2476 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2477 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2480 // If value is passed by pointer we have address passed instead of the value
2482 bool ExtendedInMem = VA.isExtInLoc() &&
2483 VA.getValVT().getScalarType() == MVT::i1;
2485 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2486 ValVT = VA.getLocVT();
2488 ValVT = VA.getValVT();
2490 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2491 // changed with more analysis.
2492 // In case of tail call optimization mark all arguments mutable. Since they
2493 // could be overwritten by lowering of arguments in case of a tail call.
2494 if (Flags.isByVal()) {
2495 unsigned Bytes = Flags.getByValSize();
2496 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2497 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2498 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2500 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2501 VA.getLocMemOffset(), isImmutable);
2502 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2503 SDValue Val = DAG.getLoad(
2504 ValVT, dl, Chain, FIN,
2505 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2507 return ExtendedInMem ?
2508 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2512 // FIXME: Get this from tablegen.
2513 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2514 const X86Subtarget *Subtarget) {
2515 assert(Subtarget->is64Bit());
2517 if (Subtarget->isCallingConvWin64(CallConv)) {
2518 static const MCPhysReg GPR64ArgRegsWin64[] = {
2519 X86::RCX, X86::RDX, X86::R8, X86::R9
2521 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2524 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2525 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2527 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2530 // FIXME: Get this from tablegen.
2531 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2532 CallingConv::ID CallConv,
2533 const X86Subtarget *Subtarget) {
2534 assert(Subtarget->is64Bit());
2535 if (Subtarget->isCallingConvWin64(CallConv)) {
2536 // The XMM registers which might contain var arg parameters are shadowed
2537 // in their paired GPR. So we only need to save the GPR to their home
2539 // TODO: __vectorcall will change this.
2543 const Function *Fn = MF.getFunction();
2544 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2545 bool isSoftFloat = Subtarget->useSoftFloat();
2546 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2547 "SSE register cannot be used when SSE is disabled!");
2548 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2549 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2553 static const MCPhysReg XMMArgRegs64Bit[] = {
2554 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2555 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2557 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2560 SDValue X86TargetLowering::LowerFormalArguments(
2561 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2562 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2563 SmallVectorImpl<SDValue> &InVals) const {
2564 MachineFunction &MF = DAG.getMachineFunction();
2565 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2566 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2568 const Function* Fn = MF.getFunction();
2569 if (Fn->hasExternalLinkage() &&
2570 Subtarget->isTargetCygMing() &&
2571 Fn->getName() == "main")
2572 FuncInfo->setForceFramePointer(true);
2574 MachineFrameInfo *MFI = MF.getFrameInfo();
2575 bool Is64Bit = Subtarget->is64Bit();
2576 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2578 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2579 "Var args not supported with calling convention fastcc, ghc or hipe");
2581 // Assign locations to all of the incoming arguments.
2582 SmallVector<CCValAssign, 16> ArgLocs;
2583 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2585 // Allocate shadow area for Win64
2587 CCInfo.AllocateStack(32, 8);
2589 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2591 unsigned LastVal = ~0U;
2593 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2594 CCValAssign &VA = ArgLocs[i];
2595 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2597 assert(VA.getValNo() != LastVal &&
2598 "Don't support value assigned to multiple locs yet");
2600 LastVal = VA.getValNo();
2602 if (VA.isRegLoc()) {
2603 EVT RegVT = VA.getLocVT();
2604 const TargetRegisterClass *RC;
2605 if (RegVT == MVT::i32)
2606 RC = &X86::GR32RegClass;
2607 else if (Is64Bit && RegVT == MVT::i64)
2608 RC = &X86::GR64RegClass;
2609 else if (RegVT == MVT::f32)
2610 RC = &X86::FR32RegClass;
2611 else if (RegVT == MVT::f64)
2612 RC = &X86::FR64RegClass;
2613 else if (RegVT.is512BitVector())
2614 RC = &X86::VR512RegClass;
2615 else if (RegVT.is256BitVector())
2616 RC = &X86::VR256RegClass;
2617 else if (RegVT.is128BitVector())
2618 RC = &X86::VR128RegClass;
2619 else if (RegVT == MVT::x86mmx)
2620 RC = &X86::VR64RegClass;
2621 else if (RegVT == MVT::i1)
2622 RC = &X86::VK1RegClass;
2623 else if (RegVT == MVT::v8i1)
2624 RC = &X86::VK8RegClass;
2625 else if (RegVT == MVT::v16i1)
2626 RC = &X86::VK16RegClass;
2627 else if (RegVT == MVT::v32i1)
2628 RC = &X86::VK32RegClass;
2629 else if (RegVT == MVT::v64i1)
2630 RC = &X86::VK64RegClass;
2632 llvm_unreachable("Unknown argument type!");
2634 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2635 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2637 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2638 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2640 if (VA.getLocInfo() == CCValAssign::SExt)
2641 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2642 DAG.getValueType(VA.getValVT()));
2643 else if (VA.getLocInfo() == CCValAssign::ZExt)
2644 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2645 DAG.getValueType(VA.getValVT()));
2646 else if (VA.getLocInfo() == CCValAssign::BCvt)
2647 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2649 if (VA.isExtInLoc()) {
2650 // Handle MMX values passed in XMM regs.
2651 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2652 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2654 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2657 assert(VA.isMemLoc());
2658 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2661 // If value is passed via pointer - do a load.
2662 if (VA.getLocInfo() == CCValAssign::Indirect)
2663 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2664 MachinePointerInfo(), false, false, false, 0);
2666 InVals.push_back(ArgValue);
2669 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2670 // All x86 ABIs require that for returning structs by value we copy the
2671 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2672 // the argument into a virtual register so that we can access it from the
2674 if (Ins[i].Flags.isSRet()) {
2675 unsigned Reg = FuncInfo->getSRetReturnReg();
2677 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2678 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2679 FuncInfo->setSRetReturnReg(Reg);
2681 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2682 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2687 unsigned StackSize = CCInfo.getNextStackOffset();
2688 // Align stack specially for tail calls.
2689 if (FuncIsMadeTailCallSafe(CallConv,
2690 MF.getTarget().Options.GuaranteedTailCallOpt))
2691 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2693 // If the function takes variable number of arguments, make a frame index for
2694 // the start of the first vararg value... for expansion of llvm.va_start. We
2695 // can skip this if there are no va_start calls.
2696 if (MFI->hasVAStart() &&
2697 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2698 CallConv != CallingConv::X86_ThisCall))) {
2699 FuncInfo->setVarArgsFrameIndex(
2700 MFI->CreateFixedObject(1, StackSize, true));
2703 MachineModuleInfo &MMI = MF.getMMI();
2705 // Figure out if XMM registers are in use.
2706 assert(!(Subtarget->useSoftFloat() &&
2707 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2708 "SSE register cannot be used when SSE is disabled!");
2710 // 64-bit calling conventions support varargs and register parameters, so we
2711 // have to do extra work to spill them in the prologue.
2712 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2713 // Find the first unallocated argument registers.
2714 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2715 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2716 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2717 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2718 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2719 "SSE register cannot be used when SSE is disabled!");
2721 // Gather all the live in physical registers.
2722 SmallVector<SDValue, 6> LiveGPRs;
2723 SmallVector<SDValue, 8> LiveXMMRegs;
2725 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2726 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2728 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2730 if (!ArgXMMs.empty()) {
2731 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2732 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2733 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2734 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2735 LiveXMMRegs.push_back(
2736 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2741 // Get to the caller-allocated home save location. Add 8 to account
2742 // for the return address.
2743 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2744 FuncInfo->setRegSaveFrameIndex(
2745 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2746 // Fixup to set vararg frame on shadow area (4 x i64).
2748 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2750 // For X86-64, if there are vararg parameters that are passed via
2751 // registers, then we must store them to their spots on the stack so
2752 // they may be loaded by deferencing the result of va_next.
2753 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2754 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2755 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2756 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2759 // Store the integer parameter registers.
2760 SmallVector<SDValue, 8> MemOps;
2761 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2762 getPointerTy(DAG.getDataLayout()));
2763 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2764 for (SDValue Val : LiveGPRs) {
2765 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2766 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2768 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2769 MachinePointerInfo::getFixedStack(
2770 DAG.getMachineFunction(),
2771 FuncInfo->getRegSaveFrameIndex(), Offset),
2773 MemOps.push_back(Store);
2777 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2778 // Now store the XMM (fp + vector) parameter registers.
2779 SmallVector<SDValue, 12> SaveXMMOps;
2780 SaveXMMOps.push_back(Chain);
2781 SaveXMMOps.push_back(ALVal);
2782 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2783 FuncInfo->getRegSaveFrameIndex(), dl));
2784 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2785 FuncInfo->getVarArgsFPOffset(), dl));
2786 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2788 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2789 MVT::Other, SaveXMMOps));
2792 if (!MemOps.empty())
2793 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2796 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2797 // Find the largest legal vector type.
2798 MVT VecVT = MVT::Other;
2799 // FIXME: Only some x86_32 calling conventions support AVX512.
2800 if (Subtarget->hasAVX512() &&
2801 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2802 CallConv == CallingConv::Intel_OCL_BI)))
2803 VecVT = MVT::v16f32;
2804 else if (Subtarget->hasAVX())
2806 else if (Subtarget->hasSSE2())
2809 // We forward some GPRs and some vector types.
2810 SmallVector<MVT, 2> RegParmTypes;
2811 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2812 RegParmTypes.push_back(IntVT);
2813 if (VecVT != MVT::Other)
2814 RegParmTypes.push_back(VecVT);
2816 // Compute the set of forwarded registers. The rest are scratch.
2817 SmallVectorImpl<ForwardedRegister> &Forwards =
2818 FuncInfo->getForwardedMustTailRegParms();
2819 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2821 // Conservatively forward AL on x86_64, since it might be used for varargs.
2822 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2823 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2824 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2827 // Copy all forwards from physical to virtual registers.
2828 for (ForwardedRegister &F : Forwards) {
2829 // FIXME: Can we use a less constrained schedule?
2830 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2831 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2832 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2836 // Some CCs need callee pop.
2837 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2838 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2839 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2841 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2842 // If this is an sret function, the return should pop the hidden pointer.
2843 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2844 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2845 argsAreStructReturn(Ins) == StackStructReturn)
2846 FuncInfo->setBytesToPopOnReturn(4);
2850 // RegSaveFrameIndex is X86-64 only.
2851 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2852 if (CallConv == CallingConv::X86_FastCall ||
2853 CallConv == CallingConv::X86_ThisCall)
2854 // fastcc functions can't have varargs.
2855 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2858 FuncInfo->setArgumentStackSize(StackSize);
2860 if (MMI.hasWinEHFuncInfo(Fn)) {
2862 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2863 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2864 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2865 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2866 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2867 MachinePointerInfo::getFixedStack(
2868 DAG.getMachineFunction(), UnwindHelpFI),
2869 /*isVolatile=*/true,
2870 /*isNonTemporal=*/false, /*Alignment=*/0);
2872 // Functions using Win32 EH are considered to have opaque SP adjustments
2873 // to force local variables to be addressed from the frame or base
2875 MFI->setHasOpaqueSPAdjustment(true);
2883 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2884 SDValue StackPtr, SDValue Arg,
2885 SDLoc dl, SelectionDAG &DAG,
2886 const CCValAssign &VA,
2887 ISD::ArgFlagsTy Flags) const {
2888 unsigned LocMemOffset = VA.getLocMemOffset();
2889 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2890 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2892 if (Flags.isByVal())
2893 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2895 return DAG.getStore(
2896 Chain, dl, Arg, PtrOff,
2897 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2901 /// Emit a load of return address if tail call
2902 /// optimization is performed and it is required.
2904 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2905 SDValue &OutRetAddr, SDValue Chain,
2906 bool IsTailCall, bool Is64Bit,
2907 int FPDiff, SDLoc dl) const {
2908 // Adjust the Return address stack slot.
2909 EVT VT = getPointerTy(DAG.getDataLayout());
2910 OutRetAddr = getReturnAddressFrameIndex(DAG);
2912 // Load the "old" Return address.
2913 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2914 false, false, false, 0);
2915 return SDValue(OutRetAddr.getNode(), 1);
2918 /// Emit a store of the return address if tail call
2919 /// optimization is performed and it is required (FPDiff!=0).
2920 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2921 SDValue Chain, SDValue RetAddrFrIdx,
2922 EVT PtrVT, unsigned SlotSize,
2923 int FPDiff, SDLoc dl) {
2924 // Store the return address to the appropriate stack slot.
2925 if (!FPDiff) return Chain;
2926 // Calculate the new stack slot for the return address.
2927 int NewReturnAddrFI =
2928 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2930 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2931 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2932 MachinePointerInfo::getFixedStack(
2933 DAG.getMachineFunction(), NewReturnAddrFI),
2938 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2939 /// operation of specified width.
2940 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2942 unsigned NumElems = VT.getVectorNumElements();
2943 SmallVector<int, 8> Mask;
2944 Mask.push_back(NumElems);
2945 for (unsigned i = 1; i != NumElems; ++i)
2947 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2951 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2952 SmallVectorImpl<SDValue> &InVals) const {
2953 SelectionDAG &DAG = CLI.DAG;
2955 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2956 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2957 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2958 SDValue Chain = CLI.Chain;
2959 SDValue Callee = CLI.Callee;
2960 CallingConv::ID CallConv = CLI.CallConv;
2961 bool &isTailCall = CLI.IsTailCall;
2962 bool isVarArg = CLI.IsVarArg;
2964 MachineFunction &MF = DAG.getMachineFunction();
2965 bool Is64Bit = Subtarget->is64Bit();
2966 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2967 StructReturnType SR = callIsStructReturn(Outs);
2968 bool IsSibcall = false;
2969 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2970 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2972 if (Attr.getValueAsString() == "true")
2975 if (Subtarget->isPICStyleGOT() &&
2976 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2977 // If we are using a GOT, disable tail calls to external symbols with
2978 // default visibility. Tail calling such a symbol requires using a GOT
2979 // relocation, which forces early binding of the symbol. This breaks code
2980 // that require lazy function symbol resolution. Using musttail or
2981 // GuaranteedTailCallOpt will override this.
2982 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2983 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2984 G->getGlobal()->hasDefaultVisibility()))
2988 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2990 // Force this to be a tail call. The verifier rules are enough to ensure
2991 // that we can lower this successfully without moving the return address
2994 } else if (isTailCall) {
2995 // Check if it's really possible to do a tail call.
2996 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2997 isVarArg, SR != NotStructReturn,
2998 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2999 Outs, OutVals, Ins, DAG);
3001 // Sibcalls are automatically detected tailcalls which do not require
3003 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3010 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
3011 "Var args not supported with calling convention fastcc, ghc or hipe");
3013 // Analyze operands of the call, assigning locations to each operand.
3014 SmallVector<CCValAssign, 16> ArgLocs;
3015 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3017 // Allocate shadow area for Win64
3019 CCInfo.AllocateStack(32, 8);
3021 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3023 // Get a count of how many bytes are to be pushed on the stack.
3024 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3026 // This is a sibcall. The memory operands are available in caller's
3027 // own caller's stack.
3029 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3030 IsTailCallConvention(CallConv))
3031 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3034 if (isTailCall && !IsSibcall && !IsMustTail) {
3035 // Lower arguments at fp - stackoffset + fpdiff.
3036 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3038 FPDiff = NumBytesCallerPushed - NumBytes;
3040 // Set the delta of movement of the returnaddr stackslot.
3041 // But only set if delta is greater than previous delta.
3042 if (FPDiff < X86Info->getTCReturnAddrDelta())
3043 X86Info->setTCReturnAddrDelta(FPDiff);
3046 unsigned NumBytesToPush = NumBytes;
3047 unsigned NumBytesToPop = NumBytes;
3049 // If we have an inalloca argument, all stack space has already been allocated
3050 // for us and be right at the top of the stack. We don't support multiple
3051 // arguments passed in memory when using inalloca.
3052 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3054 if (!ArgLocs.back().isMemLoc())
3055 report_fatal_error("cannot use inalloca attribute on a register "
3057 if (ArgLocs.back().getLocMemOffset() != 0)
3058 report_fatal_error("any parameter with the inalloca attribute must be "
3059 "the only memory argument");
3063 Chain = DAG.getCALLSEQ_START(
3064 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3066 SDValue RetAddrFrIdx;
3067 // Load return address for tail calls.
3068 if (isTailCall && FPDiff)
3069 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3070 Is64Bit, FPDiff, dl);
3072 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3073 SmallVector<SDValue, 8> MemOpChains;
3076 // Walk the register/memloc assignments, inserting copies/loads. In the case
3077 // of tail call optimization arguments are handle later.
3078 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3079 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3080 // Skip inalloca arguments, they have already been written.
3081 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3082 if (Flags.isInAlloca())
3085 CCValAssign &VA = ArgLocs[i];
3086 EVT RegVT = VA.getLocVT();
3087 SDValue Arg = OutVals[i];
3088 bool isByVal = Flags.isByVal();
3090 // Promote the value if needed.
3091 switch (VA.getLocInfo()) {
3092 default: llvm_unreachable("Unknown loc info!");
3093 case CCValAssign::Full: break;
3094 case CCValAssign::SExt:
3095 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3097 case CCValAssign::ZExt:
3098 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3100 case CCValAssign::AExt:
3101 if (Arg.getValueType().isVector() &&
3102 Arg.getValueType().getScalarType() == MVT::i1)
3103 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3104 else if (RegVT.is128BitVector()) {
3105 // Special case: passing MMX values in XMM registers.
3106 Arg = DAG.getBitcast(MVT::i64, Arg);
3107 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3108 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3110 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3112 case CCValAssign::BCvt:
3113 Arg = DAG.getBitcast(RegVT, Arg);
3115 case CCValAssign::Indirect: {
3116 // Store the argument.
3117 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3118 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3119 Chain = DAG.getStore(
3120 Chain, dl, Arg, SpillSlot,
3121 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3128 if (VA.isRegLoc()) {
3129 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3130 if (isVarArg && IsWin64) {
3131 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3132 // shadow reg if callee is a varargs function.
3133 unsigned ShadowReg = 0;
3134 switch (VA.getLocReg()) {
3135 case X86::XMM0: ShadowReg = X86::RCX; break;
3136 case X86::XMM1: ShadowReg = X86::RDX; break;
3137 case X86::XMM2: ShadowReg = X86::R8; break;
3138 case X86::XMM3: ShadowReg = X86::R9; break;
3141 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3143 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3144 assert(VA.isMemLoc());
3145 if (!StackPtr.getNode())
3146 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3147 getPointerTy(DAG.getDataLayout()));
3148 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3149 dl, DAG, VA, Flags));
3153 if (!MemOpChains.empty())
3154 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3156 if (Subtarget->isPICStyleGOT()) {
3157 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3160 RegsToPass.push_back(std::make_pair(
3161 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3162 getPointerTy(DAG.getDataLayout()))));
3164 // If we are tail calling and generating PIC/GOT style code load the
3165 // address of the callee into ECX. The value in ecx is used as target of
3166 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3167 // for tail calls on PIC/GOT architectures. Normally we would just put the
3168 // address of GOT into ebx and then call target@PLT. But for tail calls
3169 // ebx would be restored (since ebx is callee saved) before jumping to the
3172 // Note: The actual moving to ECX is done further down.
3173 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3174 if (G && !G->getGlobal()->hasLocalLinkage() &&
3175 G->getGlobal()->hasDefaultVisibility())
3176 Callee = LowerGlobalAddress(Callee, DAG);
3177 else if (isa<ExternalSymbolSDNode>(Callee))
3178 Callee = LowerExternalSymbol(Callee, DAG);
3182 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3183 // From AMD64 ABI document:
3184 // For calls that may call functions that use varargs or stdargs
3185 // (prototype-less calls or calls to functions containing ellipsis (...) in
3186 // the declaration) %al is used as hidden argument to specify the number
3187 // of SSE registers used. The contents of %al do not need to match exactly
3188 // the number of registers, but must be an ubound on the number of SSE
3189 // registers used and is in the range 0 - 8 inclusive.
3191 // Count the number of XMM registers allocated.
3192 static const MCPhysReg XMMArgRegs[] = {
3193 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3194 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3196 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3197 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3198 && "SSE registers cannot be used when SSE is disabled");
3200 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3201 DAG.getConstant(NumXMMRegs, dl,
3205 if (isVarArg && IsMustTail) {
3206 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3207 for (const auto &F : Forwards) {
3208 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3209 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3213 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3214 // don't need this because the eligibility check rejects calls that require
3215 // shuffling arguments passed in memory.
3216 if (!IsSibcall && isTailCall) {
3217 // Force all the incoming stack arguments to be loaded from the stack
3218 // before any new outgoing arguments are stored to the stack, because the
3219 // outgoing stack slots may alias the incoming argument stack slots, and
3220 // the alias isn't otherwise explicit. This is slightly more conservative
3221 // than necessary, because it means that each store effectively depends
3222 // on every argument instead of just those arguments it would clobber.
3223 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3225 SmallVector<SDValue, 8> MemOpChains2;
3228 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3229 CCValAssign &VA = ArgLocs[i];
3232 assert(VA.isMemLoc());
3233 SDValue Arg = OutVals[i];
3234 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3235 // Skip inalloca arguments. They don't require any work.
3236 if (Flags.isInAlloca())
3238 // Create frame index.
3239 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3240 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3241 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3242 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3244 if (Flags.isByVal()) {
3245 // Copy relative to framepointer.
3246 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3247 if (!StackPtr.getNode())
3248 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3249 getPointerTy(DAG.getDataLayout()));
3250 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3253 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3257 // Store relative to framepointer.
3258 MemOpChains2.push_back(DAG.getStore(
3259 ArgChain, dl, Arg, FIN,
3260 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3265 if (!MemOpChains2.empty())
3266 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3268 // Store the return address to the appropriate stack slot.
3269 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3270 getPointerTy(DAG.getDataLayout()),
3271 RegInfo->getSlotSize(), FPDiff, dl);
3274 // Build a sequence of copy-to-reg nodes chained together with token chain
3275 // and flag operands which copy the outgoing args into registers.
3277 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3278 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3279 RegsToPass[i].second, InFlag);
3280 InFlag = Chain.getValue(1);
3283 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3284 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3285 // In the 64-bit large code model, we have to make all calls
3286 // through a register, since the call instruction's 32-bit
3287 // pc-relative offset may not be large enough to hold the whole
3289 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3290 // If the callee is a GlobalAddress node (quite common, every direct call
3291 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3293 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3295 // We should use extra load for direct calls to dllimported functions in
3297 const GlobalValue *GV = G->getGlobal();
3298 if (!GV->hasDLLImportStorageClass()) {
3299 unsigned char OpFlags = 0;
3300 bool ExtraLoad = false;
3301 unsigned WrapperKind = ISD::DELETED_NODE;
3303 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3304 // external symbols most go through the PLT in PIC mode. If the symbol
3305 // has hidden or protected visibility, or if it is static or local, then
3306 // we don't need to use the PLT - we can directly call it.
3307 if (Subtarget->isTargetELF() &&
3308 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3309 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3310 OpFlags = X86II::MO_PLT;
3311 } else if (Subtarget->isPICStyleStubAny() &&
3312 !GV->isStrongDefinitionForLinker() &&
3313 (!Subtarget->getTargetTriple().isMacOSX() ||
3314 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3315 // PC-relative references to external symbols should go through $stub,
3316 // unless we're building with the leopard linker or later, which
3317 // automatically synthesizes these stubs.
3318 OpFlags = X86II::MO_DARWIN_STUB;
3319 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3320 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3321 // If the function is marked as non-lazy, generate an indirect call
3322 // which loads from the GOT directly. This avoids runtime overhead
3323 // at the cost of eager binding (and one extra byte of encoding).
3324 OpFlags = X86II::MO_GOTPCREL;
3325 WrapperKind = X86ISD::WrapperRIP;
3329 Callee = DAG.getTargetGlobalAddress(
3330 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3332 // Add a wrapper if needed.
3333 if (WrapperKind != ISD::DELETED_NODE)
3334 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3335 getPointerTy(DAG.getDataLayout()), Callee);
3336 // Add extra indirection if needed.
3338 Callee = DAG.getLoad(
3339 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3340 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3343 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3344 unsigned char OpFlags = 0;
3346 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3347 // external symbols should go through the PLT.
3348 if (Subtarget->isTargetELF() &&
3349 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3350 OpFlags = X86II::MO_PLT;
3351 } else if (Subtarget->isPICStyleStubAny() &&
3352 (!Subtarget->getTargetTriple().isMacOSX() ||
3353 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3354 // PC-relative references to external symbols should go through $stub,
3355 // unless we're building with the leopard linker or later, which
3356 // automatically synthesizes these stubs.
3357 OpFlags = X86II::MO_DARWIN_STUB;
3360 Callee = DAG.getTargetExternalSymbol(
3361 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3362 } else if (Subtarget->isTarget64BitILP32() &&
3363 Callee->getValueType(0) == MVT::i32) {
3364 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3365 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3368 // Returns a chain & a flag for retval copy to use.
3369 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3370 SmallVector<SDValue, 8> Ops;
3372 if (!IsSibcall && isTailCall) {
3373 Chain = DAG.getCALLSEQ_END(Chain,
3374 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3375 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3376 InFlag = Chain.getValue(1);
3379 Ops.push_back(Chain);
3380 Ops.push_back(Callee);
3383 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3385 // Add argument registers to the end of the list so that they are known live
3387 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3388 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3389 RegsToPass[i].second.getValueType()));
3391 // Add a register mask operand representing the call-preserved registers.
3392 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3393 assert(Mask && "Missing call preserved mask for calling convention");
3395 // If this is an invoke in a 32-bit function using a funclet-based
3396 // personality, assume the function clobbers all registers. If an exception
3397 // is thrown, the runtime will not restore CSRs.
3398 // FIXME: Model this more precisely so that we can register allocate across
3399 // the normal edge and spill and fill across the exceptional edge.
3400 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3401 const Function *CallerFn = MF.getFunction();
3402 EHPersonality Pers =
3403 CallerFn->hasPersonalityFn()
3404 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3405 : EHPersonality::Unknown;
3406 if (isFuncletEHPersonality(Pers))
3407 Mask = RegInfo->getNoPreservedMask();
3410 Ops.push_back(DAG.getRegisterMask(Mask));
3412 if (InFlag.getNode())
3413 Ops.push_back(InFlag);
3417 //// If this is the first return lowered for this function, add the regs
3418 //// to the liveout set for the function.
3419 // This isn't right, although it's probably harmless on x86; liveouts
3420 // should be computed from returns not tail calls. Consider a void
3421 // function making a tail call to a function returning int.
3422 MF.getFrameInfo()->setHasTailCall();
3423 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3426 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3427 InFlag = Chain.getValue(1);
3429 // Create the CALLSEQ_END node.
3430 unsigned NumBytesForCalleeToPop;
3431 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3432 DAG.getTarget().Options.GuaranteedTailCallOpt))
3433 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3434 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3435 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3436 SR == StackStructReturn)
3437 // If this is a call to a struct-return function, the callee
3438 // pops the hidden struct pointer, so we have to push it back.
3439 // This is common for Darwin/X86, Linux & Mingw32 targets.
3440 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3441 NumBytesForCalleeToPop = 4;
3443 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3445 // Returns a flag for retval copy to use.
3447 Chain = DAG.getCALLSEQ_END(Chain,
3448 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3449 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3452 InFlag = Chain.getValue(1);
3455 // Handle result values, copying them out of physregs into vregs that we
3457 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3458 Ins, dl, DAG, InVals);
3461 //===----------------------------------------------------------------------===//
3462 // Fast Calling Convention (tail call) implementation
3463 //===----------------------------------------------------------------------===//
3465 // Like std call, callee cleans arguments, convention except that ECX is
3466 // reserved for storing the tail called function address. Only 2 registers are
3467 // free for argument passing (inreg). Tail call optimization is performed
3469 // * tailcallopt is enabled
3470 // * caller/callee are fastcc
3471 // On X86_64 architecture with GOT-style position independent code only local
3472 // (within module) calls are supported at the moment.
3473 // To keep the stack aligned according to platform abi the function
3474 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3475 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3476 // If a tail called function callee has more arguments than the caller the
3477 // caller needs to make sure that there is room to move the RETADDR to. This is
3478 // achieved by reserving an area the size of the argument delta right after the
3479 // original RETADDR, but before the saved framepointer or the spilled registers
3480 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3492 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3495 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3496 SelectionDAG& DAG) const {
3497 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3498 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3499 unsigned StackAlignment = TFI.getStackAlignment();
3500 uint64_t AlignMask = StackAlignment - 1;
3501 int64_t Offset = StackSize;
3502 unsigned SlotSize = RegInfo->getSlotSize();
3503 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3504 // Number smaller than 12 so just add the difference.
3505 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3507 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3508 Offset = ((~AlignMask) & Offset) + StackAlignment +
3509 (StackAlignment-SlotSize);
3514 /// Return true if the given stack call argument is already available in the
3515 /// same position (relatively) of the caller's incoming argument stack.
3517 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3518 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3519 const X86InstrInfo *TII) {
3520 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3522 if (Arg.getOpcode() == ISD::CopyFromReg) {
3523 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3524 if (!TargetRegisterInfo::isVirtualRegister(VR))
3526 MachineInstr *Def = MRI->getVRegDef(VR);
3529 if (!Flags.isByVal()) {
3530 if (!TII->isLoadFromStackSlot(Def, FI))
3533 unsigned Opcode = Def->getOpcode();
3534 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3535 Opcode == X86::LEA64_32r) &&
3536 Def->getOperand(1).isFI()) {
3537 FI = Def->getOperand(1).getIndex();
3538 Bytes = Flags.getByValSize();
3542 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3543 if (Flags.isByVal())
3544 // ByVal argument is passed in as a pointer but it's now being
3545 // dereferenced. e.g.
3546 // define @foo(%struct.X* %A) {
3547 // tail call @bar(%struct.X* byval %A)
3550 SDValue Ptr = Ld->getBasePtr();
3551 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3554 FI = FINode->getIndex();
3555 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3556 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3557 FI = FINode->getIndex();
3558 Bytes = Flags.getByValSize();
3562 assert(FI != INT_MAX);
3563 if (!MFI->isFixedObjectIndex(FI))
3565 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3568 /// Check whether the call is eligible for tail call optimization. Targets
3569 /// that want to do tail call optimization should implement this function.
3570 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3571 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3572 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3573 const SmallVectorImpl<ISD::OutputArg> &Outs,
3574 const SmallVectorImpl<SDValue> &OutVals,
3575 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3576 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3579 // If -tailcallopt is specified, make fastcc functions tail-callable.
3580 const MachineFunction &MF = DAG.getMachineFunction();
3581 const Function *CallerF = MF.getFunction();
3583 // If the function return type is x86_fp80 and the callee return type is not,
3584 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3585 // perform a tailcall optimization here.
3586 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3589 CallingConv::ID CallerCC = CallerF->getCallingConv();
3590 bool CCMatch = CallerCC == CalleeCC;
3591 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3592 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3594 // Win64 functions have extra shadow space for argument homing. Don't do the
3595 // sibcall if the caller and callee have mismatched expectations for this
3597 if (IsCalleeWin64 != IsCallerWin64)
3600 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3601 if (IsTailCallConvention(CalleeCC) && CCMatch)
3606 // Look for obvious safe cases to perform tail call optimization that do not
3607 // require ABI changes. This is what gcc calls sibcall.
3609 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3610 // emit a special epilogue.
3611 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3612 if (RegInfo->needsStackRealignment(MF))
3615 // Also avoid sibcall optimization if either caller or callee uses struct
3616 // return semantics.
3617 if (isCalleeStructRet || isCallerStructRet)
3620 // An stdcall/thiscall caller is expected to clean up its arguments; the
3621 // callee isn't going to do that.
3622 // FIXME: this is more restrictive than needed. We could produce a tailcall
3623 // when the stack adjustment matches. For example, with a thiscall that takes
3624 // only one argument.
3625 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3626 CallerCC == CallingConv::X86_ThisCall))
3629 // Do not sibcall optimize vararg calls unless all arguments are passed via
3631 if (isVarArg && !Outs.empty()) {
3633 // Optimizing for varargs on Win64 is unlikely to be safe without
3634 // additional testing.
3635 if (IsCalleeWin64 || IsCallerWin64)
3638 SmallVector<CCValAssign, 16> ArgLocs;
3639 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3642 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3643 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3644 if (!ArgLocs[i].isRegLoc())
3648 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3649 // stack. Therefore, if it's not used by the call it is not safe to optimize
3650 // this into a sibcall.
3651 bool Unused = false;
3652 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3659 SmallVector<CCValAssign, 16> RVLocs;
3660 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3662 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3663 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3664 CCValAssign &VA = RVLocs[i];
3665 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3670 // If the calling conventions do not match, then we'd better make sure the
3671 // results are returned in the same way as what the caller expects.
3673 SmallVector<CCValAssign, 16> RVLocs1;
3674 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3676 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3678 SmallVector<CCValAssign, 16> RVLocs2;
3679 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3681 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3683 if (RVLocs1.size() != RVLocs2.size())
3685 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3686 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3688 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3690 if (RVLocs1[i].isRegLoc()) {
3691 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3694 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3700 // If the callee takes no arguments then go on to check the results of the
3702 if (!Outs.empty()) {
3703 // Check if stack adjustment is needed. For now, do not do this if any
3704 // argument is passed on the stack.
3705 SmallVector<CCValAssign, 16> ArgLocs;
3706 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3709 // Allocate shadow area for Win64
3711 CCInfo.AllocateStack(32, 8);
3713 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3714 if (CCInfo.getNextStackOffset()) {
3715 MachineFunction &MF = DAG.getMachineFunction();
3716 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3719 // Check if the arguments are already laid out in the right way as
3720 // the caller's fixed stack objects.
3721 MachineFrameInfo *MFI = MF.getFrameInfo();
3722 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3723 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3724 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3725 CCValAssign &VA = ArgLocs[i];
3726 SDValue Arg = OutVals[i];
3727 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3728 if (VA.getLocInfo() == CCValAssign::Indirect)
3730 if (!VA.isRegLoc()) {
3731 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3738 // If the tailcall address may be in a register, then make sure it's
3739 // possible to register allocate for it. In 32-bit, the call address can
3740 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3741 // callee-saved registers are restored. These happen to be the same
3742 // registers used to pass 'inreg' arguments so watch out for those.
3743 if (!Subtarget->is64Bit() &&
3744 ((!isa<GlobalAddressSDNode>(Callee) &&
3745 !isa<ExternalSymbolSDNode>(Callee)) ||
3746 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3747 unsigned NumInRegs = 0;
3748 // In PIC we need an extra register to formulate the address computation
3750 unsigned MaxInRegs =
3751 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3753 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3754 CCValAssign &VA = ArgLocs[i];
3757 unsigned Reg = VA.getLocReg();
3760 case X86::EAX: case X86::EDX: case X86::ECX:
3761 if (++NumInRegs == MaxInRegs)
3773 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3774 const TargetLibraryInfo *libInfo) const {
3775 return X86::createFastISel(funcInfo, libInfo);
3778 //===----------------------------------------------------------------------===//
3779 // Other Lowering Hooks
3780 //===----------------------------------------------------------------------===//
3782 static bool MayFoldLoad(SDValue Op) {
3783 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3786 static bool MayFoldIntoStore(SDValue Op) {
3787 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3790 static bool isTargetShuffle(unsigned Opcode) {
3792 default: return false;
3793 case X86ISD::BLENDI:
3794 case X86ISD::PSHUFB:
3795 case X86ISD::PSHUFD:
3796 case X86ISD::PSHUFHW:
3797 case X86ISD::PSHUFLW:
3799 case X86ISD::PALIGNR:
3800 case X86ISD::MOVLHPS:
3801 case X86ISD::MOVLHPD:
3802 case X86ISD::MOVHLPS:
3803 case X86ISD::MOVLPS:
3804 case X86ISD::MOVLPD:
3805 case X86ISD::MOVSHDUP:
3806 case X86ISD::MOVSLDUP:
3807 case X86ISD::MOVDDUP:
3810 case X86ISD::UNPCKL:
3811 case X86ISD::UNPCKH:
3812 case X86ISD::VPERMILPI:
3813 case X86ISD::VPERM2X128:
3814 case X86ISD::VPERMI:
3815 case X86ISD::VPERMV:
3816 case X86ISD::VPERMV3:
3821 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3822 SDValue V1, unsigned TargetMask,
3823 SelectionDAG &DAG) {
3825 default: llvm_unreachable("Unknown x86 shuffle node");
3826 case X86ISD::PSHUFD:
3827 case X86ISD::PSHUFHW:
3828 case X86ISD::PSHUFLW:
3829 case X86ISD::VPERMILPI:
3830 case X86ISD::VPERMI:
3831 return DAG.getNode(Opc, dl, VT, V1,
3832 DAG.getConstant(TargetMask, dl, MVT::i8));
3836 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3837 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3839 default: llvm_unreachable("Unknown x86 shuffle node");
3840 case X86ISD::MOVLHPS:
3841 case X86ISD::MOVLHPD:
3842 case X86ISD::MOVHLPS:
3843 case X86ISD::MOVLPS:
3844 case X86ISD::MOVLPD:
3847 case X86ISD::UNPCKL:
3848 case X86ISD::UNPCKH:
3849 return DAG.getNode(Opc, dl, VT, V1, V2);
3853 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3854 MachineFunction &MF = DAG.getMachineFunction();
3855 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3856 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3857 int ReturnAddrIndex = FuncInfo->getRAIndex();
3859 if (ReturnAddrIndex == 0) {
3860 // Set up a frame object for the return address.
3861 unsigned SlotSize = RegInfo->getSlotSize();
3862 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3865 FuncInfo->setRAIndex(ReturnAddrIndex);
3868 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3871 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3872 bool hasSymbolicDisplacement) {
3873 // Offset should fit into 32 bit immediate field.
3874 if (!isInt<32>(Offset))
3877 // If we don't have a symbolic displacement - we don't have any extra
3879 if (!hasSymbolicDisplacement)
3882 // FIXME: Some tweaks might be needed for medium code model.
3883 if (M != CodeModel::Small && M != CodeModel::Kernel)
3886 // For small code model we assume that latest object is 16MB before end of 31
3887 // bits boundary. We may also accept pretty large negative constants knowing
3888 // that all objects are in the positive half of address space.
3889 if (M == CodeModel::Small && Offset < 16*1024*1024)
3892 // For kernel code model we know that all object resist in the negative half
3893 // of 32bits address space. We may not accept negative offsets, since they may
3894 // be just off and we may accept pretty large positive ones.
3895 if (M == CodeModel::Kernel && Offset >= 0)
3901 /// Determines whether the callee is required to pop its own arguments.
3902 /// Callee pop is necessary to support tail calls.
3903 bool X86::isCalleePop(CallingConv::ID CallingConv,
3904 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3906 if (IsTailCallConvention(CallingConv))
3907 return IsVarArg ? false : TailCallOpt;
3909 switch (CallingConv) {
3912 case CallingConv::X86_StdCall:
3913 case CallingConv::X86_FastCall:
3914 case CallingConv::X86_ThisCall:
3919 /// \brief Return true if the condition is an unsigned comparison operation.
3920 static bool isX86CCUnsigned(unsigned X86CC) {
3922 default: llvm_unreachable("Invalid integer condition!");
3923 case X86::COND_E: return true;
3924 case X86::COND_G: return false;
3925 case X86::COND_GE: return false;
3926 case X86::COND_L: return false;
3927 case X86::COND_LE: return false;
3928 case X86::COND_NE: return true;
3929 case X86::COND_B: return true;
3930 case X86::COND_A: return true;
3931 case X86::COND_BE: return true;
3932 case X86::COND_AE: return true;
3934 llvm_unreachable("covered switch fell through?!");
3937 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3938 /// condition code, returning the condition code and the LHS/RHS of the
3939 /// comparison to make.
3940 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3941 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3943 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3944 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3945 // X > -1 -> X == 0, jump !sign.
3946 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3947 return X86::COND_NS;
3949 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3950 // X < 0 -> X == 0, jump on sign.
3953 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3955 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3956 return X86::COND_LE;
3960 switch (SetCCOpcode) {
3961 default: llvm_unreachable("Invalid integer condition!");
3962 case ISD::SETEQ: return X86::COND_E;
3963 case ISD::SETGT: return X86::COND_G;
3964 case ISD::SETGE: return X86::COND_GE;
3965 case ISD::SETLT: return X86::COND_L;
3966 case ISD::SETLE: return X86::COND_LE;
3967 case ISD::SETNE: return X86::COND_NE;
3968 case ISD::SETULT: return X86::COND_B;
3969 case ISD::SETUGT: return X86::COND_A;
3970 case ISD::SETULE: return X86::COND_BE;
3971 case ISD::SETUGE: return X86::COND_AE;
3975 // First determine if it is required or is profitable to flip the operands.
3977 // If LHS is a foldable load, but RHS is not, flip the condition.
3978 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3979 !ISD::isNON_EXTLoad(RHS.getNode())) {
3980 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3981 std::swap(LHS, RHS);
3984 switch (SetCCOpcode) {
3990 std::swap(LHS, RHS);
3994 // On a floating point condition, the flags are set as follows:
3996 // 0 | 0 | 0 | X > Y
3997 // 0 | 0 | 1 | X < Y
3998 // 1 | 0 | 0 | X == Y
3999 // 1 | 1 | 1 | unordered
4000 switch (SetCCOpcode) {
4001 default: llvm_unreachable("Condcode should be pre-legalized away");
4003 case ISD::SETEQ: return X86::COND_E;
4004 case ISD::SETOLT: // flipped
4006 case ISD::SETGT: return X86::COND_A;
4007 case ISD::SETOLE: // flipped
4009 case ISD::SETGE: return X86::COND_AE;
4010 case ISD::SETUGT: // flipped
4012 case ISD::SETLT: return X86::COND_B;
4013 case ISD::SETUGE: // flipped
4015 case ISD::SETLE: return X86::COND_BE;
4017 case ISD::SETNE: return X86::COND_NE;
4018 case ISD::SETUO: return X86::COND_P;
4019 case ISD::SETO: return X86::COND_NP;
4021 case ISD::SETUNE: return X86::COND_INVALID;
4025 /// Is there a floating point cmov for the specific X86 condition code?
4026 /// Current x86 isa includes the following FP cmov instructions:
4027 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4028 static bool hasFPCMov(unsigned X86CC) {
4044 /// Returns true if the target can instruction select the
4045 /// specified FP immediate natively. If false, the legalizer will
4046 /// materialize the FP immediate as a load from a constant pool.
4047 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4048 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4049 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4055 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4056 ISD::LoadExtType ExtTy,
4058 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4059 // relocation target a movq or addq instruction: don't let the load shrink.
4060 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4061 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4062 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4063 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4067 /// \brief Returns true if it is beneficial to convert a load of a constant
4068 /// to just the constant itself.
4069 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4071 assert(Ty->isIntegerTy());
4073 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4074 if (BitSize == 0 || BitSize > 64)
4079 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4080 unsigned Index) const {
4081 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4084 return (Index == 0 || Index == ResVT.getVectorNumElements());
4087 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4088 // Speculate cttz only if we can directly use TZCNT.
4089 return Subtarget->hasBMI();
4092 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4093 // Speculate ctlz only if we can directly use LZCNT.
4094 return Subtarget->hasLZCNT();
4097 /// Return true if every element in Mask, beginning
4098 /// from position Pos and ending in Pos+Size is undef.
4099 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4100 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4106 /// Return true if Val is undef or if its value falls within the
4107 /// specified range (L, H].
4108 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4109 return (Val < 0) || (Val >= Low && Val < Hi);
4112 /// Val is either less than zero (undef) or equal to the specified value.
4113 static bool isUndefOrEqual(int Val, int CmpVal) {
4114 return (Val < 0 || Val == CmpVal);
4117 /// Return true if every element in Mask, beginning
4118 /// from position Pos and ending in Pos+Size, falls within the specified
4119 /// sequential range (Low, Low+Size]. or is undef.
4120 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4121 unsigned Pos, unsigned Size, int Low) {
4122 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4123 if (!isUndefOrEqual(Mask[i], Low))
4128 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4129 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4130 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4131 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4132 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4135 // The index should be aligned on a vecWidth-bit boundary.
4137 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4139 MVT VT = N->getSimpleValueType(0);
4140 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4141 bool Result = (Index * ElSize) % vecWidth == 0;
4146 /// Return true if the specified INSERT_SUBVECTOR
4147 /// operand specifies a subvector insert that is suitable for input to
4148 /// insertion of 128 or 256-bit subvectors
4149 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4150 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4151 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4153 // The index should be aligned on a vecWidth-bit boundary.
4155 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4157 MVT VT = N->getSimpleValueType(0);
4158 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4159 bool Result = (Index * ElSize) % vecWidth == 0;
4164 bool X86::isVINSERT128Index(SDNode *N) {
4165 return isVINSERTIndex(N, 128);
4168 bool X86::isVINSERT256Index(SDNode *N) {
4169 return isVINSERTIndex(N, 256);
4172 bool X86::isVEXTRACT128Index(SDNode *N) {
4173 return isVEXTRACTIndex(N, 128);
4176 bool X86::isVEXTRACT256Index(SDNode *N) {
4177 return isVEXTRACTIndex(N, 256);
4180 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4181 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4182 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4183 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4186 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4188 MVT VecVT = N->getOperand(0).getSimpleValueType();
4189 MVT ElVT = VecVT.getVectorElementType();
4191 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4192 return Index / NumElemsPerChunk;
4195 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4196 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4197 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4198 llvm_unreachable("Illegal insert subvector for VINSERT");
4201 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4203 MVT VecVT = N->getSimpleValueType(0);
4204 MVT ElVT = VecVT.getVectorElementType();
4206 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4207 return Index / NumElemsPerChunk;
4210 /// Return the appropriate immediate to extract the specified
4211 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4212 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4213 return getExtractVEXTRACTImmediate(N, 128);
4216 /// Return the appropriate immediate to extract the specified
4217 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4218 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4219 return getExtractVEXTRACTImmediate(N, 256);
4222 /// Return the appropriate immediate to insert at the specified
4223 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4224 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4225 return getInsertVINSERTImmediate(N, 128);
4228 /// Return the appropriate immediate to insert at the specified
4229 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4230 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4231 return getInsertVINSERTImmediate(N, 256);
4234 /// Returns true if V is a constant integer zero.
4235 static bool isZero(SDValue V) {
4236 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4237 return C && C->isNullValue();
4240 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4241 bool X86::isZeroNode(SDValue Elt) {
4244 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4245 return CFP->getValueAPF().isPosZero();
4249 /// Returns a vector of specified type with all zero elements.
4250 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4251 SelectionDAG &DAG, SDLoc dl) {
4252 assert(VT.isVector() && "Expected a vector type");
4254 // Always build SSE zero vectors as <4 x i32> bitcasted
4255 // to their dest type. This ensures they get CSE'd.
4257 if (VT.is128BitVector()) { // SSE
4258 if (Subtarget->hasSSE2()) { // SSE2
4259 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4260 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4262 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4263 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4265 } else if (VT.is256BitVector()) { // AVX
4266 if (Subtarget->hasInt256()) { // AVX2
4267 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4268 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4269 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4271 // 256-bit logic and arithmetic instructions in AVX are all
4272 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4273 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4274 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4275 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4277 } else if (VT.is512BitVector()) { // AVX-512
4278 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4279 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4280 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4281 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4282 } else if (VT.getScalarType() == MVT::i1) {
4284 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4285 && "Unexpected vector type");
4286 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4287 && "Unexpected vector type");
4288 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4289 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4290 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4292 llvm_unreachable("Unexpected vector type");
4294 return DAG.getBitcast(VT, Vec);
4297 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4298 SelectionDAG &DAG, SDLoc dl,
4299 unsigned vectorWidth) {
4300 assert((vectorWidth == 128 || vectorWidth == 256) &&
4301 "Unsupported vector width");
4302 EVT VT = Vec.getValueType();
4303 EVT ElVT = VT.getVectorElementType();
4304 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4305 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4306 VT.getVectorNumElements()/Factor);
4308 // Extract from UNDEF is UNDEF.
4309 if (Vec.getOpcode() == ISD::UNDEF)
4310 return DAG.getUNDEF(ResultVT);
4312 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4313 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4315 // This is the index of the first element of the vectorWidth-bit chunk
4317 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4320 // If the input is a buildvector just emit a smaller one.
4321 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4322 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4323 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4326 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4327 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4330 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4331 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4332 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4333 /// instructions or a simple subregister reference. Idx is an index in the
4334 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4335 /// lowering EXTRACT_VECTOR_ELT operations easier.
4336 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4337 SelectionDAG &DAG, SDLoc dl) {
4338 assert((Vec.getValueType().is256BitVector() ||
4339 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4340 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4343 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4344 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4345 SelectionDAG &DAG, SDLoc dl) {
4346 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4347 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4350 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4351 unsigned IdxVal, SelectionDAG &DAG,
4352 SDLoc dl, unsigned vectorWidth) {
4353 assert((vectorWidth == 128 || vectorWidth == 256) &&
4354 "Unsupported vector width");
4355 // Inserting UNDEF is Result
4356 if (Vec.getOpcode() == ISD::UNDEF)
4358 EVT VT = Vec.getValueType();
4359 EVT ElVT = VT.getVectorElementType();
4360 EVT ResultVT = Result.getValueType();
4362 // Insert the relevant vectorWidth bits.
4363 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4365 // This is the index of the first element of the vectorWidth-bit chunk
4367 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4370 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4371 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4374 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4375 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4376 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4377 /// simple superregister reference. Idx is an index in the 128 bits
4378 /// we want. It need not be aligned to a 128-bit boundary. That makes
4379 /// lowering INSERT_VECTOR_ELT operations easier.
4380 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4381 SelectionDAG &DAG, SDLoc dl) {
4382 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4384 // For insertion into the zero index (low half) of a 256-bit vector, it is
4385 // more efficient to generate a blend with immediate instead of an insert*128.
4386 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4387 // extend the subvector to the size of the result vector. Make sure that
4388 // we are not recursing on that node by checking for undef here.
4389 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4390 Result.getOpcode() != ISD::UNDEF) {
4391 EVT ResultVT = Result.getValueType();
4392 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4393 SDValue Undef = DAG.getUNDEF(ResultVT);
4394 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4397 // The blend instruction, and therefore its mask, depend on the data type.
4398 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4399 if (ScalarType.isFloatingPoint()) {
4400 // Choose either vblendps (float) or vblendpd (double).
4401 unsigned ScalarSize = ScalarType.getSizeInBits();
4402 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4403 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4404 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4405 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4408 const X86Subtarget &Subtarget =
4409 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4411 // AVX2 is needed for 256-bit integer blend support.
4412 // Integers must be cast to 32-bit because there is only vpblendd;
4413 // vpblendw can't be used for this because it has a handicapped mask.
4415 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4416 // is still more efficient than using the wrong domain vinsertf128 that
4417 // will be created by InsertSubVector().
4418 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4420 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4421 Vec256 = DAG.getBitcast(CastVT, Vec256);
4422 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4423 return DAG.getBitcast(ResultVT, Vec256);
4426 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4429 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4430 SelectionDAG &DAG, SDLoc dl) {
4431 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4432 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4435 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4436 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4437 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4438 /// large BUILD_VECTORS.
4439 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4440 unsigned NumElems, SelectionDAG &DAG,
4442 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4443 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4446 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4447 unsigned NumElems, SelectionDAG &DAG,
4449 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4450 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4453 /// Returns a vector of specified type with all bits set.
4454 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4455 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4456 /// Then bitcast to their original type, ensuring they get CSE'd.
4457 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4458 SelectionDAG &DAG, SDLoc dl) {
4459 assert(VT.isVector() && "Expected a vector type");
4461 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4463 if (VT.is512BitVector()) {
4464 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4465 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4466 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4467 } else if (VT.is256BitVector()) {
4468 if (Subtarget->hasInt256()) { // AVX2
4469 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4470 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4472 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4473 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4475 } else if (VT.is128BitVector()) {
4476 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4478 llvm_unreachable("Unexpected vector type");
4480 return DAG.getBitcast(VT, Vec);
4483 /// Returns a vector_shuffle node for an unpackl operation.
4484 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4486 unsigned NumElems = VT.getVectorNumElements();
4487 SmallVector<int, 8> Mask;
4488 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4490 Mask.push_back(i + NumElems);
4492 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4495 /// Returns a vector_shuffle node for an unpackh operation.
4496 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4498 unsigned NumElems = VT.getVectorNumElements();
4499 SmallVector<int, 8> Mask;
4500 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4501 Mask.push_back(i + Half);
4502 Mask.push_back(i + NumElems + Half);
4504 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4507 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4508 /// This produces a shuffle where the low element of V2 is swizzled into the
4509 /// zero/undef vector, landing at element Idx.
4510 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4511 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4513 const X86Subtarget *Subtarget,
4514 SelectionDAG &DAG) {
4515 MVT VT = V2.getSimpleValueType();
4517 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4518 unsigned NumElems = VT.getVectorNumElements();
4519 SmallVector<int, 16> MaskVec;
4520 for (unsigned i = 0; i != NumElems; ++i)
4521 // If this is the insertion idx, put the low elt of V2 here.
4522 MaskVec.push_back(i == Idx ? NumElems : i);
4523 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4526 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4527 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4528 /// uses one source. Note that this will set IsUnary for shuffles which use a
4529 /// single input multiple times, and in those cases it will
4530 /// adjust the mask to only have indices within that single input.
4531 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4532 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4533 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4534 unsigned NumElems = VT.getVectorNumElements();
4538 bool IsFakeUnary = false;
4539 switch(N->getOpcode()) {
4540 case X86ISD::BLENDI:
4541 ImmN = N->getOperand(N->getNumOperands()-1);
4542 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4545 ImmN = N->getOperand(N->getNumOperands()-1);
4546 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4547 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4549 case X86ISD::UNPCKH:
4550 DecodeUNPCKHMask(VT, Mask);
4551 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4553 case X86ISD::UNPCKL:
4554 DecodeUNPCKLMask(VT, Mask);
4555 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4557 case X86ISD::MOVHLPS:
4558 DecodeMOVHLPSMask(NumElems, Mask);
4559 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4561 case X86ISD::MOVLHPS:
4562 DecodeMOVLHPSMask(NumElems, Mask);
4563 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4565 case X86ISD::PALIGNR:
4566 ImmN = N->getOperand(N->getNumOperands()-1);
4567 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4569 case X86ISD::PSHUFD:
4570 case X86ISD::VPERMILPI:
4571 ImmN = N->getOperand(N->getNumOperands()-1);
4572 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4575 case X86ISD::PSHUFHW:
4576 ImmN = N->getOperand(N->getNumOperands()-1);
4577 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4580 case X86ISD::PSHUFLW:
4581 ImmN = N->getOperand(N->getNumOperands()-1);
4582 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4585 case X86ISD::PSHUFB: {
4587 SDValue MaskNode = N->getOperand(1);
4588 while (MaskNode->getOpcode() == ISD::BITCAST)
4589 MaskNode = MaskNode->getOperand(0);
4591 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4592 // If we have a build-vector, then things are easy.
4593 EVT VT = MaskNode.getValueType();
4594 assert(VT.isVector() &&
4595 "Can't produce a non-vector with a build_vector!");
4596 if (!VT.isInteger())
4599 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4601 SmallVector<uint64_t, 32> RawMask;
4602 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4603 SDValue Op = MaskNode->getOperand(i);
4604 if (Op->getOpcode() == ISD::UNDEF) {
4605 RawMask.push_back((uint64_t)SM_SentinelUndef);
4608 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4611 APInt MaskElement = CN->getAPIntValue();
4613 // We now have to decode the element which could be any integer size and
4614 // extract each byte of it.
4615 for (int j = 0; j < NumBytesPerElement; ++j) {
4616 // Note that this is x86 and so always little endian: the low byte is
4617 // the first byte of the mask.
4618 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4619 MaskElement = MaskElement.lshr(8);
4622 DecodePSHUFBMask(RawMask, Mask);
4626 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4630 SDValue Ptr = MaskLoad->getBasePtr();
4631 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4632 Ptr->getOpcode() == X86ISD::WrapperRIP)
4633 Ptr = Ptr->getOperand(0);
4635 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4636 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4639 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4640 DecodePSHUFBMask(C, Mask);
4648 case X86ISD::VPERMI:
4649 ImmN = N->getOperand(N->getNumOperands()-1);
4650 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4655 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4657 case X86ISD::VPERM2X128:
4658 ImmN = N->getOperand(N->getNumOperands()-1);
4659 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4660 if (Mask.empty()) return false;
4661 // Mask only contains negative index if an element is zero.
4662 if (std::any_of(Mask.begin(), Mask.end(),
4663 [](int M){ return M == SM_SentinelZero; }))
4666 case X86ISD::MOVSLDUP:
4667 DecodeMOVSLDUPMask(VT, Mask);
4670 case X86ISD::MOVSHDUP:
4671 DecodeMOVSHDUPMask(VT, Mask);
4674 case X86ISD::MOVDDUP:
4675 DecodeMOVDDUPMask(VT, Mask);
4678 case X86ISD::MOVLHPD:
4679 case X86ISD::MOVLPD:
4680 case X86ISD::MOVLPS:
4681 // Not yet implemented
4683 case X86ISD::VPERMV: {
4685 SDValue MaskNode = N->getOperand(0);
4686 while (MaskNode->getOpcode() == ISD::BITCAST)
4687 MaskNode = MaskNode->getOperand(0);
4689 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4690 SmallVector<uint64_t, 32> RawMask;
4691 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4692 // If we have a build-vector, then things are easy.
4693 assert(MaskNode.getValueType().isInteger() &&
4694 MaskNode.getValueType().getVectorNumElements() ==
4695 VT.getVectorNumElements());
4697 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4698 SDValue Op = MaskNode->getOperand(i);
4699 if (Op->getOpcode() == ISD::UNDEF)
4700 RawMask.push_back((uint64_t)SM_SentinelUndef);
4701 else if (isa<ConstantSDNode>(Op)) {
4702 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4703 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4707 DecodeVPERMVMask(RawMask, Mask);
4710 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4711 unsigned NumEltsInMask = MaskNode->getNumOperands();
4712 MaskNode = MaskNode->getOperand(0);
4713 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4715 APInt MaskEltValue = CN->getAPIntValue();
4716 for (unsigned i = 0; i < NumEltsInMask; ++i)
4717 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4718 DecodeVPERMVMask(RawMask, Mask);
4721 // It may be a scalar load
4724 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4728 SDValue Ptr = MaskLoad->getBasePtr();
4729 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4730 Ptr->getOpcode() == X86ISD::WrapperRIP)
4731 Ptr = Ptr->getOperand(0);
4733 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4734 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4737 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4739 DecodeVPERMVMask(C, VT, Mask);
4746 case X86ISD::VPERMV3: {
4748 SDValue MaskNode = N->getOperand(1);
4749 while (MaskNode->getOpcode() == ISD::BITCAST)
4750 MaskNode = MaskNode->getOperand(1);
4752 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4753 // If we have a build-vector, then things are easy.
4754 assert(MaskNode.getValueType().isInteger() &&
4755 MaskNode.getValueType().getVectorNumElements() ==
4756 VT.getVectorNumElements());
4758 SmallVector<uint64_t, 32> RawMask;
4759 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4761 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4762 SDValue Op = MaskNode->getOperand(i);
4763 if (Op->getOpcode() == ISD::UNDEF)
4764 RawMask.push_back((uint64_t)SM_SentinelUndef);
4766 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4769 APInt MaskElement = CN->getAPIntValue();
4770 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4773 DecodeVPERMV3Mask(RawMask, Mask);
4777 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4781 SDValue Ptr = MaskLoad->getBasePtr();
4782 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4783 Ptr->getOpcode() == X86ISD::WrapperRIP)
4784 Ptr = Ptr->getOperand(0);
4786 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4787 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4790 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4792 DecodeVPERMV3Mask(C, VT, Mask);
4799 default: llvm_unreachable("unknown target shuffle node");
4802 // If we have a fake unary shuffle, the shuffle mask is spread across two
4803 // inputs that are actually the same node. Re-map the mask to always point
4804 // into the first input.
4807 if (M >= (int)Mask.size())
4813 /// Returns the scalar element that will make up the ith
4814 /// element of the result of the vector shuffle.
4815 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4818 return SDValue(); // Limit search depth.
4820 SDValue V = SDValue(N, 0);
4821 EVT VT = V.getValueType();
4822 unsigned Opcode = V.getOpcode();
4824 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4825 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4826 int Elt = SV->getMaskElt(Index);
4829 return DAG.getUNDEF(VT.getVectorElementType());
4831 unsigned NumElems = VT.getVectorNumElements();
4832 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4833 : SV->getOperand(1);
4834 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4837 // Recurse into target specific vector shuffles to find scalars.
4838 if (isTargetShuffle(Opcode)) {
4839 MVT ShufVT = V.getSimpleValueType();
4840 unsigned NumElems = ShufVT.getVectorNumElements();
4841 SmallVector<int, 16> ShuffleMask;
4844 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4847 int Elt = ShuffleMask[Index];
4849 return DAG.getUNDEF(ShufVT.getVectorElementType());
4851 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4853 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4857 // Actual nodes that may contain scalar elements
4858 if (Opcode == ISD::BITCAST) {
4859 V = V.getOperand(0);
4860 EVT SrcVT = V.getValueType();
4861 unsigned NumElems = VT.getVectorNumElements();
4863 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4867 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4868 return (Index == 0) ? V.getOperand(0)
4869 : DAG.getUNDEF(VT.getVectorElementType());
4871 if (V.getOpcode() == ISD::BUILD_VECTOR)
4872 return V.getOperand(Index);
4877 /// Custom lower build_vector of v16i8.
4878 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4879 unsigned NumNonZero, unsigned NumZero,
4881 const X86Subtarget* Subtarget,
4882 const TargetLowering &TLI) {
4890 // SSE4.1 - use PINSRB to insert each byte directly.
4891 if (Subtarget->hasSSE41()) {
4892 for (unsigned i = 0; i < 16; ++i) {
4893 bool isNonZero = (NonZeros & (1 << i)) != 0;
4897 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4899 V = DAG.getUNDEF(MVT::v16i8);
4902 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4903 MVT::v16i8, V, Op.getOperand(i),
4904 DAG.getIntPtrConstant(i, dl));
4911 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4912 for (unsigned i = 0; i < 16; ++i) {
4913 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4914 if (ThisIsNonZero && First) {
4916 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4918 V = DAG.getUNDEF(MVT::v8i16);
4923 SDValue ThisElt, LastElt;
4924 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4925 if (LastIsNonZero) {
4926 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4927 MVT::i16, Op.getOperand(i-1));
4929 if (ThisIsNonZero) {
4930 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4931 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4932 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4934 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4938 if (ThisElt.getNode())
4939 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4940 DAG.getIntPtrConstant(i/2, dl));
4944 return DAG.getBitcast(MVT::v16i8, V);
4947 /// Custom lower build_vector of v8i16.
4948 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4949 unsigned NumNonZero, unsigned NumZero,
4951 const X86Subtarget* Subtarget,
4952 const TargetLowering &TLI) {
4959 for (unsigned i = 0; i < 8; ++i) {
4960 bool isNonZero = (NonZeros & (1 << i)) != 0;
4964 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4966 V = DAG.getUNDEF(MVT::v8i16);
4969 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4970 MVT::v8i16, V, Op.getOperand(i),
4971 DAG.getIntPtrConstant(i, dl));
4978 /// Custom lower build_vector of v4i32 or v4f32.
4979 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4980 const X86Subtarget *Subtarget,
4981 const TargetLowering &TLI) {
4982 // Find all zeroable elements.
4983 std::bitset<4> Zeroable;
4984 for (int i=0; i < 4; ++i) {
4985 SDValue Elt = Op->getOperand(i);
4986 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4988 assert(Zeroable.size() - Zeroable.count() > 1 &&
4989 "We expect at least two non-zero elements!");
4991 // We only know how to deal with build_vector nodes where elements are either
4992 // zeroable or extract_vector_elt with constant index.
4993 SDValue FirstNonZero;
4994 unsigned FirstNonZeroIdx;
4995 for (unsigned i=0; i < 4; ++i) {
4998 SDValue Elt = Op->getOperand(i);
4999 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5000 !isa<ConstantSDNode>(Elt.getOperand(1)))
5002 // Make sure that this node is extracting from a 128-bit vector.
5003 MVT VT = Elt.getOperand(0).getSimpleValueType();
5004 if (!VT.is128BitVector())
5006 if (!FirstNonZero.getNode()) {
5008 FirstNonZeroIdx = i;
5012 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5013 SDValue V1 = FirstNonZero.getOperand(0);
5014 MVT VT = V1.getSimpleValueType();
5016 // See if this build_vector can be lowered as a blend with zero.
5018 unsigned EltMaskIdx, EltIdx;
5020 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5021 if (Zeroable[EltIdx]) {
5022 // The zero vector will be on the right hand side.
5023 Mask[EltIdx] = EltIdx+4;
5027 Elt = Op->getOperand(EltIdx);
5028 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5029 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5030 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5032 Mask[EltIdx] = EltIdx;
5036 // Let the shuffle legalizer deal with blend operations.
5037 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5038 if (V1.getSimpleValueType() != VT)
5039 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5040 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5043 // See if we can lower this build_vector to a INSERTPS.
5044 if (!Subtarget->hasSSE41())
5047 SDValue V2 = Elt.getOperand(0);
5048 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5051 bool CanFold = true;
5052 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5056 SDValue Current = Op->getOperand(i);
5057 SDValue SrcVector = Current->getOperand(0);
5060 CanFold = SrcVector == V1 &&
5061 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5067 assert(V1.getNode() && "Expected at least two non-zero elements!");
5068 if (V1.getSimpleValueType() != MVT::v4f32)
5069 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5070 if (V2.getSimpleValueType() != MVT::v4f32)
5071 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5073 // Ok, we can emit an INSERTPS instruction.
5074 unsigned ZMask = Zeroable.to_ulong();
5076 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5077 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5079 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5080 DAG.getIntPtrConstant(InsertPSMask, DL));
5081 return DAG.getBitcast(VT, Result);
5084 /// Return a vector logical shift node.
5085 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5086 unsigned NumBits, SelectionDAG &DAG,
5087 const TargetLowering &TLI, SDLoc dl) {
5088 assert(VT.is128BitVector() && "Unknown type for VShift");
5089 MVT ShVT = MVT::v2i64;
5090 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5091 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5092 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5093 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5094 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5095 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5099 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5101 // Check if the scalar load can be widened into a vector load. And if
5102 // the address is "base + cst" see if the cst can be "absorbed" into
5103 // the shuffle mask.
5104 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5105 SDValue Ptr = LD->getBasePtr();
5106 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5108 EVT PVT = LD->getValueType(0);
5109 if (PVT != MVT::i32 && PVT != MVT::f32)
5114 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5115 FI = FINode->getIndex();
5117 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5118 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5119 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5120 Offset = Ptr.getConstantOperandVal(1);
5121 Ptr = Ptr.getOperand(0);
5126 // FIXME: 256-bit vector instructions don't require a strict alignment,
5127 // improve this code to support it better.
5128 unsigned RequiredAlign = VT.getSizeInBits()/8;
5129 SDValue Chain = LD->getChain();
5130 // Make sure the stack object alignment is at least 16 or 32.
5131 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5132 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5133 if (MFI->isFixedObjectIndex(FI)) {
5134 // Can't change the alignment. FIXME: It's possible to compute
5135 // the exact stack offset and reference FI + adjust offset instead.
5136 // If someone *really* cares about this. That's the way to implement it.
5139 MFI->setObjectAlignment(FI, RequiredAlign);
5143 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5144 // Ptr + (Offset & ~15).
5147 if ((Offset % RequiredAlign) & 3)
5149 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5152 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5153 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5156 int EltNo = (Offset - StartOffset) >> 2;
5157 unsigned NumElems = VT.getVectorNumElements();
5159 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5160 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5161 LD->getPointerInfo().getWithOffset(StartOffset),
5162 false, false, false, 0);
5164 SmallVector<int, 8> Mask(NumElems, EltNo);
5166 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5172 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5173 /// elements can be replaced by a single large load which has the same value as
5174 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5176 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5178 /// FIXME: we'd also like to handle the case where the last elements are zero
5179 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5180 /// There's even a handy isZeroNode for that purpose.
5181 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5182 SDLoc &DL, SelectionDAG &DAG,
5183 bool isAfterLegalize) {
5184 unsigned NumElems = Elts.size();
5186 LoadSDNode *LDBase = nullptr;
5187 unsigned LastLoadedElt = -1U;
5189 // For each element in the initializer, see if we've found a load or an undef.
5190 // If we don't find an initial load element, or later load elements are
5191 // non-consecutive, bail out.
5192 for (unsigned i = 0; i < NumElems; ++i) {
5193 SDValue Elt = Elts[i];
5194 // Look through a bitcast.
5195 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5196 Elt = Elt.getOperand(0);
5197 if (!Elt.getNode() ||
5198 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5201 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5203 LDBase = cast<LoadSDNode>(Elt.getNode());
5207 if (Elt.getOpcode() == ISD::UNDEF)
5210 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5211 EVT LdVT = Elt.getValueType();
5212 // Each loaded element must be the correct fractional portion of the
5213 // requested vector load.
5214 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5216 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5221 // If we have found an entire vector of loads and undefs, then return a large
5222 // load of the entire vector width starting at the base pointer. If we found
5223 // consecutive loads for the low half, generate a vzext_load node.
5224 if (LastLoadedElt == NumElems - 1) {
5225 assert(LDBase && "Did not find base load for merging consecutive loads");
5226 EVT EltVT = LDBase->getValueType(0);
5227 // Ensure that the input vector size for the merged loads matches the
5228 // cumulative size of the input elements.
5229 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5232 if (isAfterLegalize &&
5233 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5236 SDValue NewLd = SDValue();
5238 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5239 LDBase->getPointerInfo(), LDBase->isVolatile(),
5240 LDBase->isNonTemporal(), LDBase->isInvariant(),
5241 LDBase->getAlignment());
5243 if (LDBase->hasAnyUseOfValue(1)) {
5244 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5246 SDValue(NewLd.getNode(), 1));
5247 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5248 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5249 SDValue(NewLd.getNode(), 1));
5255 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5256 //of a v4i32 / v4f32. It's probably worth generalizing.
5257 EVT EltVT = VT.getVectorElementType();
5258 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5259 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5260 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5261 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5263 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5264 LDBase->getPointerInfo(),
5265 LDBase->getAlignment(),
5266 false/*isVolatile*/, true/*ReadMem*/,
5269 // Make sure the newly-created LOAD is in the same position as LDBase in
5270 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5271 // update uses of LDBase's output chain to use the TokenFactor.
5272 if (LDBase->hasAnyUseOfValue(1)) {
5273 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5274 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5275 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5276 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5277 SDValue(ResNode.getNode(), 1));
5280 return DAG.getBitcast(VT, ResNode);
5285 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5286 /// to generate a splat value for the following cases:
5287 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5288 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5289 /// a scalar load, or a constant.
5290 /// The VBROADCAST node is returned when a pattern is found,
5291 /// or SDValue() otherwise.
5292 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5293 SelectionDAG &DAG) {
5294 // VBROADCAST requires AVX.
5295 // TODO: Splats could be generated for non-AVX CPUs using SSE
5296 // instructions, but there's less potential gain for only 128-bit vectors.
5297 if (!Subtarget->hasAVX())
5300 MVT VT = Op.getSimpleValueType();
5303 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5304 "Unsupported vector type for broadcast.");
5309 switch (Op.getOpcode()) {
5311 // Unknown pattern found.
5314 case ISD::BUILD_VECTOR: {
5315 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5316 BitVector UndefElements;
5317 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5319 // We need a splat of a single value to use broadcast, and it doesn't
5320 // make any sense if the value is only in one element of the vector.
5321 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5325 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5326 Ld.getOpcode() == ISD::ConstantFP);
5328 // Make sure that all of the users of a non-constant load are from the
5329 // BUILD_VECTOR node.
5330 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5335 case ISD::VECTOR_SHUFFLE: {
5336 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5338 // Shuffles must have a splat mask where the first element is
5340 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5343 SDValue Sc = Op.getOperand(0);
5344 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5345 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5347 if (!Subtarget->hasInt256())
5350 // Use the register form of the broadcast instruction available on AVX2.
5351 if (VT.getSizeInBits() >= 256)
5352 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5353 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5356 Ld = Sc.getOperand(0);
5357 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5358 Ld.getOpcode() == ISD::ConstantFP);
5360 // The scalar_to_vector node and the suspected
5361 // load node must have exactly one user.
5362 // Constants may have multiple users.
5364 // AVX-512 has register version of the broadcast
5365 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5366 Ld.getValueType().getSizeInBits() >= 32;
5367 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5374 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5375 bool IsGE256 = (VT.getSizeInBits() >= 256);
5377 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5378 // instruction to save 8 or more bytes of constant pool data.
5379 // TODO: If multiple splats are generated to load the same constant,
5380 // it may be detrimental to overall size. There needs to be a way to detect
5381 // that condition to know if this is truly a size win.
5382 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5384 // Handle broadcasting a single constant scalar from the constant pool
5386 // On Sandybridge (no AVX2), it is still better to load a constant vector
5387 // from the constant pool and not to broadcast it from a scalar.
5388 // But override that restriction when optimizing for size.
5389 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5390 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5391 EVT CVT = Ld.getValueType();
5392 assert(!CVT.isVector() && "Must not broadcast a vector type");
5394 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5395 // For size optimization, also splat v2f64 and v2i64, and for size opt
5396 // with AVX2, also splat i8 and i16.
5397 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5398 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5399 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5400 const Constant *C = nullptr;
5401 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5402 C = CI->getConstantIntValue();
5403 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5404 C = CF->getConstantFPValue();
5406 assert(C && "Invalid constant type");
5408 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5410 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5411 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5413 CVT, dl, DAG.getEntryNode(), CP,
5414 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5415 false, false, Alignment);
5417 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5421 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5423 // Handle AVX2 in-register broadcasts.
5424 if (!IsLoad && Subtarget->hasInt256() &&
5425 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5426 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5428 // The scalar source must be a normal load.
5432 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5433 (Subtarget->hasVLX() && ScalarSize == 64))
5434 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5436 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5437 // double since there is no vbroadcastsd xmm
5438 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5439 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5440 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5443 // Unsupported broadcast.
5447 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5448 /// underlying vector and index.
5450 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5452 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5454 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5455 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5458 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5460 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5462 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5463 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5466 // In this case the vector is the extract_subvector expression and the index
5467 // is 2, as specified by the shuffle.
5468 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5469 SDValue ShuffleVec = SVOp->getOperand(0);
5470 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5471 assert(ShuffleVecVT.getVectorElementType() ==
5472 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5474 int ShuffleIdx = SVOp->getMaskElt(Idx);
5475 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5476 ExtractedFromVec = ShuffleVec;
5482 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5483 MVT VT = Op.getSimpleValueType();
5485 // Skip if insert_vec_elt is not supported.
5486 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5487 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5491 unsigned NumElems = Op.getNumOperands();
5495 SmallVector<unsigned, 4> InsertIndices;
5496 SmallVector<int, 8> Mask(NumElems, -1);
5498 for (unsigned i = 0; i != NumElems; ++i) {
5499 unsigned Opc = Op.getOperand(i).getOpcode();
5501 if (Opc == ISD::UNDEF)
5504 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5505 // Quit if more than 1 elements need inserting.
5506 if (InsertIndices.size() > 1)
5509 InsertIndices.push_back(i);
5513 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5514 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5515 // Quit if non-constant index.
5516 if (!isa<ConstantSDNode>(ExtIdx))
5518 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5520 // Quit if extracted from vector of different type.
5521 if (ExtractedFromVec.getValueType() != VT)
5524 if (!VecIn1.getNode())
5525 VecIn1 = ExtractedFromVec;
5526 else if (VecIn1 != ExtractedFromVec) {
5527 if (!VecIn2.getNode())
5528 VecIn2 = ExtractedFromVec;
5529 else if (VecIn2 != ExtractedFromVec)
5530 // Quit if more than 2 vectors to shuffle
5534 if (ExtractedFromVec == VecIn1)
5536 else if (ExtractedFromVec == VecIn2)
5537 Mask[i] = Idx + NumElems;
5540 if (!VecIn1.getNode())
5543 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5544 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5545 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5546 unsigned Idx = InsertIndices[i];
5547 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5548 DAG.getIntPtrConstant(Idx, DL));
5554 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5555 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5556 Op.getScalarValueSizeInBits() == 1 &&
5557 "Can not convert non-constant vector");
5558 uint64_t Immediate = 0;
5559 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5560 SDValue In = Op.getOperand(idx);
5561 if (In.getOpcode() != ISD::UNDEF)
5562 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5566 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5567 return DAG.getConstant(Immediate, dl, VT);
5569 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5571 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5573 MVT VT = Op.getSimpleValueType();
5574 assert((VT.getVectorElementType() == MVT::i1) &&
5575 "Unexpected type in LowerBUILD_VECTORvXi1!");
5578 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5579 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5580 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5581 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5584 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5585 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5586 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5587 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5590 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5591 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5592 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5593 return DAG.getBitcast(VT, Imm);
5594 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5595 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5596 DAG.getIntPtrConstant(0, dl));
5599 // Vector has one or more non-const elements
5600 uint64_t Immediate = 0;
5601 SmallVector<unsigned, 16> NonConstIdx;
5602 bool IsSplat = true;
5603 bool HasConstElts = false;
5605 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5606 SDValue In = Op.getOperand(idx);
5607 if (In.getOpcode() == ISD::UNDEF)
5609 if (!isa<ConstantSDNode>(In))
5610 NonConstIdx.push_back(idx);
5612 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5613 HasConstElts = true;
5617 else if (In != Op.getOperand(SplatIdx))
5621 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5623 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5624 DAG.getConstant(1, dl, VT),
5625 DAG.getConstant(0, dl, VT));
5627 // insert elements one by one
5631 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5632 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5634 else if (HasConstElts)
5635 Imm = DAG.getConstant(0, dl, VT);
5637 Imm = DAG.getUNDEF(VT);
5638 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5639 DstVec = DAG.getBitcast(VT, Imm);
5641 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5642 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5643 DAG.getIntPtrConstant(0, dl));
5646 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5647 unsigned InsertIdx = NonConstIdx[i];
5648 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5649 Op.getOperand(InsertIdx),
5650 DAG.getIntPtrConstant(InsertIdx, dl));
5655 /// \brief Return true if \p N implements a horizontal binop and return the
5656 /// operands for the horizontal binop into V0 and V1.
5658 /// This is a helper function of LowerToHorizontalOp().
5659 /// This function checks that the build_vector \p N in input implements a
5660 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5661 /// operation to match.
5662 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5663 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5664 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5667 /// This function only analyzes elements of \p N whose indices are
5668 /// in range [BaseIdx, LastIdx).
5669 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5671 unsigned BaseIdx, unsigned LastIdx,
5672 SDValue &V0, SDValue &V1) {
5673 EVT VT = N->getValueType(0);
5675 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5676 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5677 "Invalid Vector in input!");
5679 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5680 bool CanFold = true;
5681 unsigned ExpectedVExtractIdx = BaseIdx;
5682 unsigned NumElts = LastIdx - BaseIdx;
5683 V0 = DAG.getUNDEF(VT);
5684 V1 = DAG.getUNDEF(VT);
5686 // Check if N implements a horizontal binop.
5687 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5688 SDValue Op = N->getOperand(i + BaseIdx);
5691 if (Op->getOpcode() == ISD::UNDEF) {
5692 // Update the expected vector extract index.
5693 if (i * 2 == NumElts)
5694 ExpectedVExtractIdx = BaseIdx;
5695 ExpectedVExtractIdx += 2;
5699 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5704 SDValue Op0 = Op.getOperand(0);
5705 SDValue Op1 = Op.getOperand(1);
5707 // Try to match the following pattern:
5708 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5709 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5710 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5711 Op0.getOperand(0) == Op1.getOperand(0) &&
5712 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5713 isa<ConstantSDNode>(Op1.getOperand(1)));
5717 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5718 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5720 if (i * 2 < NumElts) {
5721 if (V0.getOpcode() == ISD::UNDEF) {
5722 V0 = Op0.getOperand(0);
5723 if (V0.getValueType() != VT)
5727 if (V1.getOpcode() == ISD::UNDEF) {
5728 V1 = Op0.getOperand(0);
5729 if (V1.getValueType() != VT)
5732 if (i * 2 == NumElts)
5733 ExpectedVExtractIdx = BaseIdx;
5736 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5737 if (I0 == ExpectedVExtractIdx)
5738 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5739 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5740 // Try to match the following dag sequence:
5741 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5742 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5746 ExpectedVExtractIdx += 2;
5752 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5753 /// a concat_vector.
5755 /// This is a helper function of LowerToHorizontalOp().
5756 /// This function expects two 256-bit vectors called V0 and V1.
5757 /// At first, each vector is split into two separate 128-bit vectors.
5758 /// Then, the resulting 128-bit vectors are used to implement two
5759 /// horizontal binary operations.
5761 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5763 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5764 /// the two new horizontal binop.
5765 /// When Mode is set, the first horizontal binop dag node would take as input
5766 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5767 /// horizontal binop dag node would take as input the lower 128-bit of V1
5768 /// and the upper 128-bit of V1.
5770 /// HADD V0_LO, V0_HI
5771 /// HADD V1_LO, V1_HI
5773 /// Otherwise, the first horizontal binop dag node takes as input the lower
5774 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5775 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5777 /// HADD V0_LO, V1_LO
5778 /// HADD V0_HI, V1_HI
5780 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5781 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5782 /// the upper 128-bits of the result.
5783 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5784 SDLoc DL, SelectionDAG &DAG,
5785 unsigned X86Opcode, bool Mode,
5786 bool isUndefLO, bool isUndefHI) {
5787 EVT VT = V0.getValueType();
5788 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5789 "Invalid nodes in input!");
5791 unsigned NumElts = VT.getVectorNumElements();
5792 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5793 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5794 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5795 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5796 EVT NewVT = V0_LO.getValueType();
5798 SDValue LO = DAG.getUNDEF(NewVT);
5799 SDValue HI = DAG.getUNDEF(NewVT);
5802 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5803 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5804 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5805 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5806 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5808 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5809 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5810 V1_LO->getOpcode() != ISD::UNDEF))
5811 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5813 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5814 V1_HI->getOpcode() != ISD::UNDEF))
5815 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5818 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5821 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5823 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5824 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5825 EVT VT = BV->getValueType(0);
5826 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5827 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5831 unsigned NumElts = VT.getVectorNumElements();
5832 SDValue InVec0 = DAG.getUNDEF(VT);
5833 SDValue InVec1 = DAG.getUNDEF(VT);
5835 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5836 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5838 // Odd-numbered elements in the input build vector are obtained from
5839 // adding two integer/float elements.
5840 // Even-numbered elements in the input build vector are obtained from
5841 // subtracting two integer/float elements.
5842 unsigned ExpectedOpcode = ISD::FSUB;
5843 unsigned NextExpectedOpcode = ISD::FADD;
5844 bool AddFound = false;
5845 bool SubFound = false;
5847 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5848 SDValue Op = BV->getOperand(i);
5850 // Skip 'undef' values.
5851 unsigned Opcode = Op.getOpcode();
5852 if (Opcode == ISD::UNDEF) {
5853 std::swap(ExpectedOpcode, NextExpectedOpcode);
5857 // Early exit if we found an unexpected opcode.
5858 if (Opcode != ExpectedOpcode)
5861 SDValue Op0 = Op.getOperand(0);
5862 SDValue Op1 = Op.getOperand(1);
5864 // Try to match the following pattern:
5865 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5866 // Early exit if we cannot match that sequence.
5867 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5868 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5869 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5870 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5871 Op0.getOperand(1) != Op1.getOperand(1))
5874 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5878 // We found a valid add/sub node. Update the information accordingly.
5884 // Update InVec0 and InVec1.
5885 if (InVec0.getOpcode() == ISD::UNDEF) {
5886 InVec0 = Op0.getOperand(0);
5887 if (InVec0.getValueType() != VT)
5890 if (InVec1.getOpcode() == ISD::UNDEF) {
5891 InVec1 = Op1.getOperand(0);
5892 if (InVec1.getValueType() != VT)
5896 // Make sure that operands in input to each add/sub node always
5897 // come from a same pair of vectors.
5898 if (InVec0 != Op0.getOperand(0)) {
5899 if (ExpectedOpcode == ISD::FSUB)
5902 // FADD is commutable. Try to commute the operands
5903 // and then test again.
5904 std::swap(Op0, Op1);
5905 if (InVec0 != Op0.getOperand(0))
5909 if (InVec1 != Op1.getOperand(0))
5912 // Update the pair of expected opcodes.
5913 std::swap(ExpectedOpcode, NextExpectedOpcode);
5916 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5917 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5918 InVec1.getOpcode() != ISD::UNDEF)
5919 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5924 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5925 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5926 const X86Subtarget *Subtarget,
5927 SelectionDAG &DAG) {
5928 EVT VT = BV->getValueType(0);
5929 unsigned NumElts = VT.getVectorNumElements();
5930 unsigned NumUndefsLO = 0;
5931 unsigned NumUndefsHI = 0;
5932 unsigned Half = NumElts/2;
5934 // Count the number of UNDEF operands in the build_vector in input.
5935 for (unsigned i = 0, e = Half; i != e; ++i)
5936 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5939 for (unsigned i = Half, e = NumElts; i != e; ++i)
5940 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5943 // Early exit if this is either a build_vector of all UNDEFs or all the
5944 // operands but one are UNDEF.
5945 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5949 SDValue InVec0, InVec1;
5950 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5951 // Try to match an SSE3 float HADD/HSUB.
5952 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5953 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5955 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5956 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5957 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5958 // Try to match an SSSE3 integer HADD/HSUB.
5959 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5960 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5962 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5963 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5966 if (!Subtarget->hasAVX())
5969 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5970 // Try to match an AVX horizontal add/sub of packed single/double
5971 // precision floating point values from 256-bit vectors.
5972 SDValue InVec2, InVec3;
5973 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5974 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5975 ((InVec0.getOpcode() == ISD::UNDEF ||
5976 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5977 ((InVec1.getOpcode() == ISD::UNDEF ||
5978 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5979 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5981 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5982 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5983 ((InVec0.getOpcode() == ISD::UNDEF ||
5984 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5985 ((InVec1.getOpcode() == ISD::UNDEF ||
5986 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5987 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5988 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5989 // Try to match an AVX2 horizontal add/sub of signed integers.
5990 SDValue InVec2, InVec3;
5992 bool CanFold = true;
5994 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5995 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5996 ((InVec0.getOpcode() == ISD::UNDEF ||
5997 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5998 ((InVec1.getOpcode() == ISD::UNDEF ||
5999 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6000 X86Opcode = X86ISD::HADD;
6001 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6002 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6003 ((InVec0.getOpcode() == ISD::UNDEF ||
6004 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6005 ((InVec1.getOpcode() == ISD::UNDEF ||
6006 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6007 X86Opcode = X86ISD::HSUB;
6012 // Fold this build_vector into a single horizontal add/sub.
6013 // Do this only if the target has AVX2.
6014 if (Subtarget->hasAVX2())
6015 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6017 // Do not try to expand this build_vector into a pair of horizontal
6018 // add/sub if we can emit a pair of scalar add/sub.
6019 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6022 // Convert this build_vector into a pair of horizontal binop followed by
6024 bool isUndefLO = NumUndefsLO == Half;
6025 bool isUndefHI = NumUndefsHI == Half;
6026 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6027 isUndefLO, isUndefHI);
6031 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6032 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6034 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6035 X86Opcode = X86ISD::HADD;
6036 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6037 X86Opcode = X86ISD::HSUB;
6038 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6039 X86Opcode = X86ISD::FHADD;
6040 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6041 X86Opcode = X86ISD::FHSUB;
6045 // Don't try to expand this build_vector into a pair of horizontal add/sub
6046 // if we can simply emit a pair of scalar add/sub.
6047 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6050 // Convert this build_vector into two horizontal add/sub followed by
6052 bool isUndefLO = NumUndefsLO == Half;
6053 bool isUndefHI = NumUndefsHI == Half;
6054 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6055 isUndefLO, isUndefHI);
6062 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6065 MVT VT = Op.getSimpleValueType();
6066 MVT ExtVT = VT.getVectorElementType();
6067 unsigned NumElems = Op.getNumOperands();
6069 // Generate vectors for predicate vectors.
6070 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6071 return LowerBUILD_VECTORvXi1(Op, DAG);
6073 // Vectors containing all zeros can be matched by pxor and xorps later
6074 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6075 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6076 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6077 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6080 return getZeroVector(VT, Subtarget, DAG, dl);
6083 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6084 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6085 // vpcmpeqd on 256-bit vectors.
6086 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6087 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6090 if (!VT.is512BitVector())
6091 return getOnesVector(VT, Subtarget, DAG, dl);
6094 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6095 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6097 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6098 return HorizontalOp;
6099 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6102 unsigned EVTBits = ExtVT.getSizeInBits();
6104 unsigned NumZero = 0;
6105 unsigned NumNonZero = 0;
6106 unsigned NonZeros = 0;
6107 bool IsAllConstants = true;
6108 SmallSet<SDValue, 8> Values;
6109 for (unsigned i = 0; i < NumElems; ++i) {
6110 SDValue Elt = Op.getOperand(i);
6111 if (Elt.getOpcode() == ISD::UNDEF)
6114 if (Elt.getOpcode() != ISD::Constant &&
6115 Elt.getOpcode() != ISD::ConstantFP)
6116 IsAllConstants = false;
6117 if (X86::isZeroNode(Elt))
6120 NonZeros |= (1 << i);
6125 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6126 if (NumNonZero == 0)
6127 return DAG.getUNDEF(VT);
6129 // Special case for single non-zero, non-undef, element.
6130 if (NumNonZero == 1) {
6131 unsigned Idx = countTrailingZeros(NonZeros);
6132 SDValue Item = Op.getOperand(Idx);
6134 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6135 // the value are obviously zero, truncate the value to i32 and do the
6136 // insertion that way. Only do this if the value is non-constant or if the
6137 // value is a constant being inserted into element 0. It is cheaper to do
6138 // a constant pool load than it is to do a movd + shuffle.
6139 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6140 (!IsAllConstants || Idx == 0)) {
6141 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6143 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6144 EVT VecVT = MVT::v4i32;
6146 // Truncate the value (which may itself be a constant) to i32, and
6147 // convert it to a vector with movd (S2V+shuffle to zero extend).
6148 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6149 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6150 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6151 Item, Idx * 2, true, Subtarget, DAG));
6155 // If we have a constant or non-constant insertion into the low element of
6156 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6157 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6158 // depending on what the source datatype is.
6161 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6163 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6164 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6165 if (VT.is512BitVector()) {
6166 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6167 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6168 Item, DAG.getIntPtrConstant(0, dl));
6170 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6171 "Expected an SSE value type!");
6172 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6173 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6174 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6177 // We can't directly insert an i8 or i16 into a vector, so zero extend
6179 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6180 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6181 if (VT.is256BitVector()) {
6182 if (Subtarget->hasAVX()) {
6183 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6184 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6186 // Without AVX, we need to extend to a 128-bit vector and then
6187 // insert into the 256-bit vector.
6188 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6189 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6190 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6193 assert(VT.is128BitVector() && "Expected an SSE value type!");
6194 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6195 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6197 return DAG.getBitcast(VT, Item);
6201 // Is it a vector logical left shift?
6202 if (NumElems == 2 && Idx == 1 &&
6203 X86::isZeroNode(Op.getOperand(0)) &&
6204 !X86::isZeroNode(Op.getOperand(1))) {
6205 unsigned NumBits = VT.getSizeInBits();
6206 return getVShift(true, VT,
6207 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6208 VT, Op.getOperand(1)),
6209 NumBits/2, DAG, *this, dl);
6212 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6215 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6216 // is a non-constant being inserted into an element other than the low one,
6217 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6218 // movd/movss) to move this into the low element, then shuffle it into
6220 if (EVTBits == 32) {
6221 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6222 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6226 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6227 if (Values.size() == 1) {
6228 if (EVTBits == 32) {
6229 // Instead of a shuffle like this:
6230 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6231 // Check if it's possible to issue this instead.
6232 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6233 unsigned Idx = countTrailingZeros(NonZeros);
6234 SDValue Item = Op.getOperand(Idx);
6235 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6236 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6241 // A vector full of immediates; various special cases are already
6242 // handled, so this is best done with a single constant-pool load.
6246 // For AVX-length vectors, see if we can use a vector load to get all of the
6247 // elements, otherwise build the individual 128-bit pieces and use
6248 // shuffles to put them in place.
6249 if (VT.is256BitVector() || VT.is512BitVector()) {
6250 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6252 // Check for a build vector of consecutive loads.
6253 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6256 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6258 // Build both the lower and upper subvector.
6259 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6260 makeArrayRef(&V[0], NumElems/2));
6261 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6262 makeArrayRef(&V[NumElems / 2], NumElems/2));
6264 // Recreate the wider vector with the lower and upper part.
6265 if (VT.is256BitVector())
6266 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6267 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6270 // Let legalizer expand 2-wide build_vectors.
6271 if (EVTBits == 64) {
6272 if (NumNonZero == 1) {
6273 // One half is zero or undef.
6274 unsigned Idx = countTrailingZeros(NonZeros);
6275 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6276 Op.getOperand(Idx));
6277 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6282 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6283 if (EVTBits == 8 && NumElems == 16)
6284 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6288 if (EVTBits == 16 && NumElems == 8)
6289 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6293 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6294 if (EVTBits == 32 && NumElems == 4)
6295 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6298 // If element VT is == 32 bits, turn it into a number of shuffles.
6299 SmallVector<SDValue, 8> V(NumElems);
6300 if (NumElems == 4 && NumZero > 0) {
6301 for (unsigned i = 0; i < 4; ++i) {
6302 bool isZero = !(NonZeros & (1 << i));
6304 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6306 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6309 for (unsigned i = 0; i < 2; ++i) {
6310 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6313 V[i] = V[i*2]; // Must be a zero vector.
6316 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6319 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6322 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6327 bool Reverse1 = (NonZeros & 0x3) == 2;
6328 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6332 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6333 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6335 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6338 if (Values.size() > 1 && VT.is128BitVector()) {
6339 // Check for a build vector of consecutive loads.
6340 for (unsigned i = 0; i < NumElems; ++i)
6341 V[i] = Op.getOperand(i);
6343 // Check for elements which are consecutive loads.
6344 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6347 // Check for a build vector from mostly shuffle plus few inserting.
6348 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6351 // For SSE 4.1, use insertps to put the high elements into the low element.
6352 if (Subtarget->hasSSE41()) {
6354 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6355 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6357 Result = DAG.getUNDEF(VT);
6359 for (unsigned i = 1; i < NumElems; ++i) {
6360 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6361 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6362 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6367 // Otherwise, expand into a number of unpckl*, start by extending each of
6368 // our (non-undef) elements to the full vector width with the element in the
6369 // bottom slot of the vector (which generates no code for SSE).
6370 for (unsigned i = 0; i < NumElems; ++i) {
6371 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6372 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6374 V[i] = DAG.getUNDEF(VT);
6377 // Next, we iteratively mix elements, e.g. for v4f32:
6378 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6379 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6380 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6381 unsigned EltStride = NumElems >> 1;
6382 while (EltStride != 0) {
6383 for (unsigned i = 0; i < EltStride; ++i) {
6384 // If V[i+EltStride] is undef and this is the first round of mixing,
6385 // then it is safe to just drop this shuffle: V[i] is already in the
6386 // right place, the one element (since it's the first round) being
6387 // inserted as undef can be dropped. This isn't safe for successive
6388 // rounds because they will permute elements within both vectors.
6389 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6390 EltStride == NumElems/2)
6393 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6402 // 256-bit AVX can use the vinsertf128 instruction
6403 // to create 256-bit vectors from two other 128-bit ones.
6404 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6406 MVT ResVT = Op.getSimpleValueType();
6408 assert((ResVT.is256BitVector() ||
6409 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6411 SDValue V1 = Op.getOperand(0);
6412 SDValue V2 = Op.getOperand(1);
6413 unsigned NumElems = ResVT.getVectorNumElements();
6414 if (ResVT.is256BitVector())
6415 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6417 if (Op.getNumOperands() == 4) {
6418 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6419 ResVT.getVectorNumElements()/2);
6420 SDValue V3 = Op.getOperand(2);
6421 SDValue V4 = Op.getOperand(3);
6422 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6423 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6425 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6428 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6429 const X86Subtarget *Subtarget,
6430 SelectionDAG & DAG) {
6432 MVT ResVT = Op.getSimpleValueType();
6433 unsigned NumOfOperands = Op.getNumOperands();
6435 assert(isPowerOf2_32(NumOfOperands) &&
6436 "Unexpected number of operands in CONCAT_VECTORS");
6438 if (NumOfOperands > 2) {
6439 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6440 ResVT.getVectorNumElements()/2);
6441 SmallVector<SDValue, 2> Ops;
6442 for (unsigned i = 0; i < NumOfOperands/2; i++)
6443 Ops.push_back(Op.getOperand(i));
6444 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6446 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6447 Ops.push_back(Op.getOperand(i));
6448 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6449 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6452 SDValue V1 = Op.getOperand(0);
6453 SDValue V2 = Op.getOperand(1);
6454 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6455 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6457 if (IsZeroV1 && IsZeroV2)
6458 return getZeroVector(ResVT, Subtarget, DAG, dl);
6460 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6461 SDValue Undef = DAG.getUNDEF(ResVT);
6462 unsigned NumElems = ResVT.getVectorNumElements();
6463 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6465 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6466 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6470 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6471 // Zero the upper bits of V1
6472 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6473 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6476 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6479 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6480 const X86Subtarget *Subtarget,
6481 SelectionDAG &DAG) {
6482 MVT VT = Op.getSimpleValueType();
6483 if (VT.getVectorElementType() == MVT::i1)
6484 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6486 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6487 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6488 Op.getNumOperands() == 4)));
6490 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6491 // from two other 128-bit ones.
6493 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6494 return LowerAVXCONCAT_VECTORS(Op, DAG);
6497 //===----------------------------------------------------------------------===//
6498 // Vector shuffle lowering
6500 // This is an experimental code path for lowering vector shuffles on x86. It is
6501 // designed to handle arbitrary vector shuffles and blends, gracefully
6502 // degrading performance as necessary. It works hard to recognize idiomatic
6503 // shuffles and lower them to optimal instruction patterns without leaving
6504 // a framework that allows reasonably efficient handling of all vector shuffle
6506 //===----------------------------------------------------------------------===//
6508 /// \brief Tiny helper function to identify a no-op mask.
6510 /// This is a somewhat boring predicate function. It checks whether the mask
6511 /// array input, which is assumed to be a single-input shuffle mask of the kind
6512 /// used by the X86 shuffle instructions (not a fully general
6513 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6514 /// in-place shuffle are 'no-op's.
6515 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6516 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6517 if (Mask[i] != -1 && Mask[i] != i)
6522 /// \brief Helper function to classify a mask as a single-input mask.
6524 /// This isn't a generic single-input test because in the vector shuffle
6525 /// lowering we canonicalize single inputs to be the first input operand. This
6526 /// means we can more quickly test for a single input by only checking whether
6527 /// an input from the second operand exists. We also assume that the size of
6528 /// mask corresponds to the size of the input vectors which isn't true in the
6529 /// fully general case.
6530 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6532 if (M >= (int)Mask.size())
6537 /// \brief Test whether there are elements crossing 128-bit lanes in this
6540 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6541 /// and we routinely test for these.
6542 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6543 int LaneSize = 128 / VT.getScalarSizeInBits();
6544 int Size = Mask.size();
6545 for (int i = 0; i < Size; ++i)
6546 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6551 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6553 /// This checks a shuffle mask to see if it is performing the same
6554 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6555 /// that it is also not lane-crossing. It may however involve a blend from the
6556 /// same lane of a second vector.
6558 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6559 /// non-trivial to compute in the face of undef lanes. The representation is
6560 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6561 /// entries from both V1 and V2 inputs to the wider mask.
6563 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6564 SmallVectorImpl<int> &RepeatedMask) {
6565 int LaneSize = 128 / VT.getScalarSizeInBits();
6566 RepeatedMask.resize(LaneSize, -1);
6567 int Size = Mask.size();
6568 for (int i = 0; i < Size; ++i) {
6571 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6572 // This entry crosses lanes, so there is no way to model this shuffle.
6575 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6576 if (RepeatedMask[i % LaneSize] == -1)
6577 // This is the first non-undef entry in this slot of a 128-bit lane.
6578 RepeatedMask[i % LaneSize] =
6579 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6580 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6581 // Found a mismatch with the repeated mask.
6587 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6590 /// This is a fast way to test a shuffle mask against a fixed pattern:
6592 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6594 /// It returns true if the mask is exactly as wide as the argument list, and
6595 /// each element of the mask is either -1 (signifying undef) or the value given
6596 /// in the argument.
6597 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6598 ArrayRef<int> ExpectedMask) {
6599 if (Mask.size() != ExpectedMask.size())
6602 int Size = Mask.size();
6604 // If the values are build vectors, we can look through them to find
6605 // equivalent inputs that make the shuffles equivalent.
6606 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6607 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6609 for (int i = 0; i < Size; ++i)
6610 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6611 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6612 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6613 if (!MaskBV || !ExpectedBV ||
6614 MaskBV->getOperand(Mask[i] % Size) !=
6615 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6622 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6624 /// This helper function produces an 8-bit shuffle immediate corresponding to
6625 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6626 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6629 /// NB: We rely heavily on "undef" masks preserving the input lane.
6630 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6631 SelectionDAG &DAG) {
6632 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6633 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6634 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6635 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6636 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6639 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6640 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6641 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6642 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6643 return DAG.getConstant(Imm, DL, MVT::i8);
6646 /// \brief Compute whether each element of a shuffle is zeroable.
6648 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6649 /// Either it is an undef element in the shuffle mask, the element of the input
6650 /// referenced is undef, or the element of the input referenced is known to be
6651 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6652 /// as many lanes with this technique as possible to simplify the remaining
6654 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6655 SDValue V1, SDValue V2) {
6656 SmallBitVector Zeroable(Mask.size(), false);
6658 while (V1.getOpcode() == ISD::BITCAST)
6659 V1 = V1->getOperand(0);
6660 while (V2.getOpcode() == ISD::BITCAST)
6661 V2 = V2->getOperand(0);
6663 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6664 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6666 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6668 // Handle the easy cases.
6669 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6674 // If this is an index into a build_vector node (which has the same number
6675 // of elements), dig out the input value and use it.
6676 SDValue V = M < Size ? V1 : V2;
6677 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6680 SDValue Input = V.getOperand(M % Size);
6681 // The UNDEF opcode check really should be dead code here, but not quite
6682 // worth asserting on (it isn't invalid, just unexpected).
6683 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6690 // X86 has dedicated unpack instructions that can handle specific blend
6691 // operations: UNPCKH and UNPCKL.
6692 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6693 SDValue V1, SDValue V2,
6694 SelectionDAG &DAG) {
6695 int NumElts = VT.getVectorNumElements();
6698 bool UnpcklSwapped = true;
6699 bool UnpckhSwapped = true;
6700 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6702 for (int i = 0; i < NumElts; ++i) {
6703 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6705 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6706 int HiPos = LoPos + NumEltsInLane / 2;
6707 int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
6708 int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
6712 if (Mask[i] != LoPos)
6714 if (Mask[i] != HiPos)
6716 if (Mask[i] != LoPosSwapped)
6717 UnpcklSwapped = false;
6718 if (Mask[i] != HiPosSwapped)
6719 UnpckhSwapped = false;
6720 if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
6724 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6726 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6728 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6730 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6732 llvm_unreachable("Unexpected result of UNPCK mask analysis");
6736 /// \brief Try to emit a bitmask instruction for a shuffle.
6738 /// This handles cases where we can model a blend exactly as a bitmask due to
6739 /// one of the inputs being zeroable.
6740 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6741 SDValue V2, ArrayRef<int> Mask,
6742 SelectionDAG &DAG) {
6743 MVT EltVT = VT.getScalarType();
6744 int NumEltBits = EltVT.getSizeInBits();
6745 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6746 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6747 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6749 if (EltVT.isFloatingPoint()) {
6750 Zero = DAG.getBitcast(EltVT, Zero);
6751 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6753 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6754 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6756 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6759 if (Mask[i] % Size != i)
6760 return SDValue(); // Not a blend.
6762 V = Mask[i] < Size ? V1 : V2;
6763 else if (V != (Mask[i] < Size ? V1 : V2))
6764 return SDValue(); // Can only let one input through the mask.
6766 VMaskOps[i] = AllOnes;
6769 return SDValue(); // No non-zeroable elements!
6771 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6772 V = DAG.getNode(VT.isFloatingPoint()
6773 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6778 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6780 /// This is used as a fallback approach when first class blend instructions are
6781 /// unavailable. Currently it is only suitable for integer vectors, but could
6782 /// be generalized for floating point vectors if desirable.
6783 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6784 SDValue V2, ArrayRef<int> Mask,
6785 SelectionDAG &DAG) {
6786 assert(VT.isInteger() && "Only supports integer vector types!");
6787 MVT EltVT = VT.getScalarType();
6788 int NumEltBits = EltVT.getSizeInBits();
6789 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6790 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6792 SmallVector<SDValue, 16> MaskOps;
6793 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6794 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6795 return SDValue(); // Shuffled input!
6796 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6799 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6800 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6801 // We have to cast V2 around.
6802 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6803 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6804 DAG.getBitcast(MaskVT, V1Mask),
6805 DAG.getBitcast(MaskVT, V2)));
6806 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6809 /// \brief Try to emit a blend instruction for a shuffle.
6811 /// This doesn't do any checks for the availability of instructions for blending
6812 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6813 /// be matched in the backend with the type given. What it does check for is
6814 /// that the shuffle mask is in fact a blend.
6815 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6816 SDValue V2, ArrayRef<int> Mask,
6817 const X86Subtarget *Subtarget,
6818 SelectionDAG &DAG) {
6819 unsigned BlendMask = 0;
6820 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6821 if (Mask[i] >= Size) {
6822 if (Mask[i] != i + Size)
6823 return SDValue(); // Shuffled V2 input!
6824 BlendMask |= 1u << i;
6827 if (Mask[i] >= 0 && Mask[i] != i)
6828 return SDValue(); // Shuffled V1 input!
6830 switch (VT.SimpleTy) {
6835 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6836 DAG.getConstant(BlendMask, DL, MVT::i8));
6840 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6844 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6845 // that instruction.
6846 if (Subtarget->hasAVX2()) {
6847 // Scale the blend by the number of 32-bit dwords per element.
6848 int Scale = VT.getScalarSizeInBits() / 32;
6850 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6851 if (Mask[i] >= Size)
6852 for (int j = 0; j < Scale; ++j)
6853 BlendMask |= 1u << (i * Scale + j);
6855 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6856 V1 = DAG.getBitcast(BlendVT, V1);
6857 V2 = DAG.getBitcast(BlendVT, V2);
6858 return DAG.getBitcast(
6859 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6860 DAG.getConstant(BlendMask, DL, MVT::i8)));
6864 // For integer shuffles we need to expand the mask and cast the inputs to
6865 // v8i16s prior to blending.
6866 int Scale = 8 / VT.getVectorNumElements();
6868 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6869 if (Mask[i] >= Size)
6870 for (int j = 0; j < Scale; ++j)
6871 BlendMask |= 1u << (i * Scale + j);
6873 V1 = DAG.getBitcast(MVT::v8i16, V1);
6874 V2 = DAG.getBitcast(MVT::v8i16, V2);
6875 return DAG.getBitcast(VT,
6876 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6877 DAG.getConstant(BlendMask, DL, MVT::i8)));
6881 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6882 SmallVector<int, 8> RepeatedMask;
6883 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6884 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6885 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6887 for (int i = 0; i < 8; ++i)
6888 if (RepeatedMask[i] >= 16)
6889 BlendMask |= 1u << i;
6890 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6891 DAG.getConstant(BlendMask, DL, MVT::i8));
6897 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6898 "256-bit byte-blends require AVX2 support!");
6900 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6901 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6904 // Scale the blend by the number of bytes per element.
6905 int Scale = VT.getScalarSizeInBits() / 8;
6907 // This form of blend is always done on bytes. Compute the byte vector
6909 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6911 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6912 // mix of LLVM's code generator and the x86 backend. We tell the code
6913 // generator that boolean values in the elements of an x86 vector register
6914 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6915 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6916 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6917 // of the element (the remaining are ignored) and 0 in that high bit would
6918 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6919 // the LLVM model for boolean values in vector elements gets the relevant
6920 // bit set, it is set backwards and over constrained relative to x86's
6922 SmallVector<SDValue, 32> VSELECTMask;
6923 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6924 for (int j = 0; j < Scale; ++j)
6925 VSELECTMask.push_back(
6926 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6927 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6930 V1 = DAG.getBitcast(BlendVT, V1);
6931 V2 = DAG.getBitcast(BlendVT, V2);
6932 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6933 DAG.getNode(ISD::BUILD_VECTOR, DL,
6934 BlendVT, VSELECTMask),
6939 llvm_unreachable("Not a supported integer vector type!");
6943 /// \brief Try to lower as a blend of elements from two inputs followed by
6944 /// a single-input permutation.
6946 /// This matches the pattern where we can blend elements from two inputs and
6947 /// then reduce the shuffle to a single-input permutation.
6948 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6951 SelectionDAG &DAG) {
6952 // We build up the blend mask while checking whether a blend is a viable way
6953 // to reduce the shuffle.
6954 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6955 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6957 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6961 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6963 if (BlendMask[Mask[i] % Size] == -1)
6964 BlendMask[Mask[i] % Size] = Mask[i];
6965 else if (BlendMask[Mask[i] % Size] != Mask[i])
6966 return SDValue(); // Can't blend in the needed input!
6968 PermuteMask[i] = Mask[i] % Size;
6971 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6972 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6975 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6976 /// blends and permutes.
6978 /// This matches the extremely common pattern for handling combined
6979 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6980 /// operations. It will try to pick the best arrangement of shuffles and
6982 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6986 SelectionDAG &DAG) {
6987 // Shuffle the input elements into the desired positions in V1 and V2 and
6988 // blend them together.
6989 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6990 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6991 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6992 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6993 if (Mask[i] >= 0 && Mask[i] < Size) {
6994 V1Mask[i] = Mask[i];
6996 } else if (Mask[i] >= Size) {
6997 V2Mask[i] = Mask[i] - Size;
6998 BlendMask[i] = i + Size;
7001 // Try to lower with the simpler initial blend strategy unless one of the
7002 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7003 // shuffle may be able to fold with a load or other benefit. However, when
7004 // we'll have to do 2x as many shuffles in order to achieve this, blending
7005 // first is a better strategy.
7006 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7007 if (SDValue BlendPerm =
7008 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7011 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7012 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7013 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7016 /// \brief Try to lower a vector shuffle as a byte rotation.
7018 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7019 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7020 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7021 /// try to generically lower a vector shuffle through such an pattern. It
7022 /// does not check for the profitability of lowering either as PALIGNR or
7023 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7024 /// This matches shuffle vectors that look like:
7026 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7028 /// Essentially it concatenates V1 and V2, shifts right by some number of
7029 /// elements, and takes the low elements as the result. Note that while this is
7030 /// specified as a *right shift* because x86 is little-endian, it is a *left
7031 /// rotate* of the vector lanes.
7032 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7035 const X86Subtarget *Subtarget,
7036 SelectionDAG &DAG) {
7037 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7039 int NumElts = Mask.size();
7040 int NumLanes = VT.getSizeInBits() / 128;
7041 int NumLaneElts = NumElts / NumLanes;
7043 // We need to detect various ways of spelling a rotation:
7044 // [11, 12, 13, 14, 15, 0, 1, 2]
7045 // [-1, 12, 13, 14, -1, -1, 1, -1]
7046 // [-1, -1, -1, -1, -1, -1, 1, 2]
7047 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7048 // [-1, 4, 5, 6, -1, -1, 9, -1]
7049 // [-1, 4, 5, 6, -1, -1, -1, -1]
7052 for (int l = 0; l < NumElts; l += NumLaneElts) {
7053 for (int i = 0; i < NumLaneElts; ++i) {
7054 if (Mask[l + i] == -1)
7056 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7058 // Get the mod-Size index and lane correct it.
7059 int LaneIdx = (Mask[l + i] % NumElts) - l;
7060 // Make sure it was in this lane.
7061 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7064 // Determine where a rotated vector would have started.
7065 int StartIdx = i - LaneIdx;
7067 // The identity rotation isn't interesting, stop.
7070 // If we found the tail of a vector the rotation must be the missing
7071 // front. If we found the head of a vector, it must be how much of the
7073 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7076 Rotation = CandidateRotation;
7077 else if (Rotation != CandidateRotation)
7078 // The rotations don't match, so we can't match this mask.
7081 // Compute which value this mask is pointing at.
7082 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7084 // Compute which of the two target values this index should be assigned
7085 // to. This reflects whether the high elements are remaining or the low
7086 // elements are remaining.
7087 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7089 // Either set up this value if we've not encountered it before, or check
7090 // that it remains consistent.
7093 else if (TargetV != MaskV)
7094 // This may be a rotation, but it pulls from the inputs in some
7095 // unsupported interleaving.
7100 // Check that we successfully analyzed the mask, and normalize the results.
7101 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7102 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7108 // The actual rotate instruction rotates bytes, so we need to scale the
7109 // rotation based on how many bytes are in the vector lane.
7110 int Scale = 16 / NumLaneElts;
7112 // SSSE3 targets can use the palignr instruction.
7113 if (Subtarget->hasSSSE3()) {
7114 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7115 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7116 Lo = DAG.getBitcast(AlignVT, Lo);
7117 Hi = DAG.getBitcast(AlignVT, Hi);
7119 return DAG.getBitcast(
7120 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7121 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7124 assert(VT.getSizeInBits() == 128 &&
7125 "Rotate-based lowering only supports 128-bit lowering!");
7126 assert(Mask.size() <= 16 &&
7127 "Can shuffle at most 16 bytes in a 128-bit vector!");
7129 // Default SSE2 implementation
7130 int LoByteShift = 16 - Rotation * Scale;
7131 int HiByteShift = Rotation * Scale;
7133 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7134 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7135 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7137 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7138 DAG.getConstant(LoByteShift, DL, MVT::i8));
7139 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7140 DAG.getConstant(HiByteShift, DL, MVT::i8));
7141 return DAG.getBitcast(VT,
7142 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7145 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7147 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7148 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7149 /// matches elements from one of the input vectors shuffled to the left or
7150 /// right with zeroable elements 'shifted in'. It handles both the strictly
7151 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7154 /// PSHL : (little-endian) left bit shift.
7155 /// [ zz, 0, zz, 2 ]
7156 /// [ -1, 4, zz, -1 ]
7157 /// PSRL : (little-endian) right bit shift.
7159 /// [ -1, -1, 7, zz]
7160 /// PSLLDQ : (little-endian) left byte shift
7161 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7162 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7163 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7164 /// PSRLDQ : (little-endian) right byte shift
7165 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7166 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7167 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7168 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7169 SDValue V2, ArrayRef<int> Mask,
7170 SelectionDAG &DAG) {
7171 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7173 int Size = Mask.size();
7174 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7176 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7177 for (int i = 0; i < Size; i += Scale)
7178 for (int j = 0; j < Shift; ++j)
7179 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7185 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7186 for (int i = 0; i != Size; i += Scale) {
7187 unsigned Pos = Left ? i + Shift : i;
7188 unsigned Low = Left ? i : i + Shift;
7189 unsigned Len = Scale - Shift;
7190 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7191 Low + (V == V1 ? 0 : Size)))
7195 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7196 bool ByteShift = ShiftEltBits > 64;
7197 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7198 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7199 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7201 // Normalize the scale for byte shifts to still produce an i64 element
7203 Scale = ByteShift ? Scale / 2 : Scale;
7205 // We need to round trip through the appropriate type for the shift.
7206 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7207 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7208 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7209 "Illegal integer vector type");
7210 V = DAG.getBitcast(ShiftVT, V);
7212 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7213 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7214 return DAG.getBitcast(VT, V);
7217 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7218 // keep doubling the size of the integer elements up to that. We can
7219 // then shift the elements of the integer vector by whole multiples of
7220 // their width within the elements of the larger integer vector. Test each
7221 // multiple to see if we can find a match with the moved element indices
7222 // and that the shifted in elements are all zeroable.
7223 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7224 for (int Shift = 1; Shift != Scale; ++Shift)
7225 for (bool Left : {true, false})
7226 if (CheckZeros(Shift, Scale, Left))
7227 for (SDValue V : {V1, V2})
7228 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7235 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7236 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7237 SDValue V2, ArrayRef<int> Mask,
7238 SelectionDAG &DAG) {
7239 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7240 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7242 int Size = Mask.size();
7243 int HalfSize = Size / 2;
7244 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7246 // Upper half must be undefined.
7247 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7250 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7251 // Remainder of lower half result is zero and upper half is all undef.
7252 auto LowerAsEXTRQ = [&]() {
7253 // Determine the extraction length from the part of the
7254 // lower half that isn't zeroable.
7256 for (; Len >= 0; --Len)
7257 if (!Zeroable[Len - 1])
7259 assert(Len > 0 && "Zeroable shuffle mask");
7261 // Attempt to match first Len sequential elements from the lower half.
7264 for (int i = 0; i != Len; ++i) {
7268 SDValue &V = (M < Size ? V1 : V2);
7271 // All mask elements must be in the lower half.
7275 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7286 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7287 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7288 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7289 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7290 DAG.getConstant(BitLen, DL, MVT::i8),
7291 DAG.getConstant(BitIdx, DL, MVT::i8));
7294 if (SDValue ExtrQ = LowerAsEXTRQ())
7297 // INSERTQ: Extract lowest Len elements from lower half of second source and
7298 // insert over first source, starting at Idx.
7299 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7300 auto LowerAsInsertQ = [&]() {
7301 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7304 // Attempt to match first source from mask before insertion point.
7305 if (isUndefInRange(Mask, 0, Idx)) {
7307 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7309 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7315 // Extend the extraction length looking to match both the insertion of
7316 // the second source and the remaining elements of the first.
7317 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7322 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7324 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7330 // Match the remaining elements of the lower half.
7331 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7333 } else if ((!Base || (Base == V1)) &&
7334 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7336 } else if ((!Base || (Base == V2)) &&
7337 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7344 // We may not have a base (first source) - this can safely be undefined.
7346 Base = DAG.getUNDEF(VT);
7348 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7349 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7350 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7351 DAG.getConstant(BitLen, DL, MVT::i8),
7352 DAG.getConstant(BitIdx, DL, MVT::i8));
7359 if (SDValue InsertQ = LowerAsInsertQ())
7365 /// \brief Lower a vector shuffle as a zero or any extension.
7367 /// Given a specific number of elements, element bit width, and extension
7368 /// stride, produce either a zero or any extension based on the available
7369 /// features of the subtarget. The extended elements are consecutive and
7370 /// begin and can start from an offseted element index in the input; to
7371 /// avoid excess shuffling the offset must either being in the bottom lane
7372 /// or at the start of a higher lane. All extended elements must be from
7374 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7375 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7376 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7377 assert(Scale > 1 && "Need a scale to extend.");
7378 int EltBits = VT.getScalarSizeInBits();
7379 int NumElements = VT.getVectorNumElements();
7380 int NumEltsPerLane = 128 / EltBits;
7381 int OffsetLane = Offset / NumEltsPerLane;
7382 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7383 "Only 8, 16, and 32 bit elements can be extended.");
7384 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7385 assert(0 <= Offset && "Extension offset must be positive.");
7386 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7387 "Extension offset must be in the first lane or start an upper lane.");
7389 // Check that an index is in same lane as the base offset.
7390 auto SafeOffset = [&](int Idx) {
7391 return OffsetLane == (Idx / NumEltsPerLane);
7394 // Shift along an input so that the offset base moves to the first element.
7395 auto ShuffleOffset = [&](SDValue V) {
7399 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7400 for (int i = 0; i * Scale < NumElements; ++i) {
7401 int SrcIdx = i + Offset;
7402 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7404 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7407 // Found a valid zext mask! Try various lowering strategies based on the
7408 // input type and available ISA extensions.
7409 if (Subtarget->hasSSE41()) {
7410 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7411 // PUNPCK will catch this in a later shuffle match.
7412 if (Offset && Scale == 2 && VT.getSizeInBits() == 128)
7414 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7415 NumElements / Scale);
7416 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7417 return DAG.getBitcast(VT, InputV);
7420 assert(VT.getSizeInBits() == 128 && "Only 128-bit vectors can be extended.");
7422 // For any extends we can cheat for larger element sizes and use shuffle
7423 // instructions that can fold with a load and/or copy.
7424 if (AnyExt && EltBits == 32) {
7425 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7427 return DAG.getBitcast(
7428 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7429 DAG.getBitcast(MVT::v4i32, InputV),
7430 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7432 if (AnyExt && EltBits == 16 && Scale > 2) {
7433 int PSHUFDMask[4] = {Offset / 2, -1,
7434 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7435 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7436 DAG.getBitcast(MVT::v4i32, InputV),
7437 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7438 int PSHUFWMask[4] = {1, -1, -1, -1};
7439 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7440 return DAG.getBitcast(
7441 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7442 DAG.getBitcast(MVT::v8i16, InputV),
7443 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7446 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7448 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7449 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7450 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7452 int LoIdx = Offset * EltBits;
7453 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7454 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7455 DAG.getConstant(EltBits, DL, MVT::i8),
7456 DAG.getConstant(LoIdx, DL, MVT::i8)));
7458 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7459 !SafeOffset(Offset + 1))
7460 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7462 int HiIdx = (Offset + 1) * EltBits;
7463 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7464 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7465 DAG.getConstant(EltBits, DL, MVT::i8),
7466 DAG.getConstant(HiIdx, DL, MVT::i8)));
7467 return DAG.getNode(ISD::BITCAST, DL, VT,
7468 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7471 // If this would require more than 2 unpack instructions to expand, use
7472 // pshufb when available. We can only use more than 2 unpack instructions
7473 // when zero extending i8 elements which also makes it easier to use pshufb.
7474 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7475 assert(NumElements == 16 && "Unexpected byte vector width!");
7476 SDValue PSHUFBMask[16];
7477 for (int i = 0; i < 16; ++i) {
7478 int Idx = Offset + (i / Scale);
7479 PSHUFBMask[i] = DAG.getConstant(
7480 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7482 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7483 return DAG.getBitcast(VT,
7484 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7485 DAG.getNode(ISD::BUILD_VECTOR, DL,
7486 MVT::v16i8, PSHUFBMask)));
7489 // If we are extending from an offset, ensure we start on a boundary that
7490 // we can unpack from.
7491 int AlignToUnpack = Offset % (NumElements / Scale);
7492 if (AlignToUnpack) {
7493 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7494 for (int i = AlignToUnpack; i < NumElements; ++i)
7495 ShMask[i - AlignToUnpack] = i;
7496 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7497 Offset -= AlignToUnpack;
7500 // Otherwise emit a sequence of unpacks.
7502 unsigned UnpackLoHi = X86ISD::UNPCKL;
7503 if (Offset >= (NumElements / 2)) {
7504 UnpackLoHi = X86ISD::UNPCKH;
7505 Offset -= (NumElements / 2);
7508 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7509 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7510 : getZeroVector(InputVT, Subtarget, DAG, DL);
7511 InputV = DAG.getBitcast(InputVT, InputV);
7512 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7516 } while (Scale > 1);
7517 return DAG.getBitcast(VT, InputV);
7520 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7522 /// This routine will try to do everything in its power to cleverly lower
7523 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7524 /// check for the profitability of this lowering, it tries to aggressively
7525 /// match this pattern. It will use all of the micro-architectural details it
7526 /// can to emit an efficient lowering. It handles both blends with all-zero
7527 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7528 /// masking out later).
7530 /// The reason we have dedicated lowering for zext-style shuffles is that they
7531 /// are both incredibly common and often quite performance sensitive.
7532 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7533 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7534 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7535 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7537 int Bits = VT.getSizeInBits();
7538 int NumLanes = Bits / 128;
7539 int NumElements = VT.getVectorNumElements();
7540 int NumEltsPerLane = NumElements / NumLanes;
7541 assert(VT.getScalarSizeInBits() <= 32 &&
7542 "Exceeds 32-bit integer zero extension limit");
7543 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7545 // Define a helper function to check a particular ext-scale and lower to it if
7547 auto Lower = [&](int Scale) -> SDValue {
7552 for (int i = 0; i < NumElements; ++i) {
7555 continue; // Valid anywhere but doesn't tell us anything.
7556 if (i % Scale != 0) {
7557 // Each of the extended elements need to be zeroable.
7561 // We no longer are in the anyext case.
7566 // Each of the base elements needs to be consecutive indices into the
7567 // same input vector.
7568 SDValue V = M < NumElements ? V1 : V2;
7569 M = M % NumElements;
7572 Offset = M - (i / Scale);
7573 } else if (InputV != V)
7574 return SDValue(); // Flip-flopping inputs.
7576 // Offset must start in the lowest 128-bit lane or at the start of an
7578 // FIXME: Is it ever worth allowing a negative base offset?
7579 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7580 (Offset % NumEltsPerLane) == 0))
7583 // If we are offsetting, all referenced entries must come from the same
7585 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7588 if ((M % NumElements) != (Offset + (i / Scale)))
7589 return SDValue(); // Non-consecutive strided elements.
7593 // If we fail to find an input, we have a zero-shuffle which should always
7594 // have already been handled.
7595 // FIXME: Maybe handle this here in case during blending we end up with one?
7599 // If we are offsetting, don't extend if we only match a single input, we
7600 // can always do better by using a basic PSHUF or PUNPCK.
7601 if (Offset != 0 && Matches < 2)
7604 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7605 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7608 // The widest scale possible for extending is to a 64-bit integer.
7609 assert(Bits % 64 == 0 &&
7610 "The number of bits in a vector must be divisible by 64 on x86!");
7611 int NumExtElements = Bits / 64;
7613 // Each iteration, try extending the elements half as much, but into twice as
7615 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7616 assert(NumElements % NumExtElements == 0 &&
7617 "The input vector size must be divisible by the extended size.");
7618 if (SDValue V = Lower(NumElements / NumExtElements))
7622 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7626 // Returns one of the source operands if the shuffle can be reduced to a
7627 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7628 auto CanZExtLowHalf = [&]() {
7629 for (int i = NumElements / 2; i != NumElements; ++i)
7632 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7634 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7639 if (SDValue V = CanZExtLowHalf()) {
7640 V = DAG.getBitcast(MVT::v2i64, V);
7641 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7642 return DAG.getBitcast(VT, V);
7645 // No viable ext lowering found.
7649 /// \brief Try to get a scalar value for a specific element of a vector.
7651 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7652 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7653 SelectionDAG &DAG) {
7654 MVT VT = V.getSimpleValueType();
7655 MVT EltVT = VT.getVectorElementType();
7656 while (V.getOpcode() == ISD::BITCAST)
7657 V = V.getOperand(0);
7658 // If the bitcasts shift the element size, we can't extract an equivalent
7660 MVT NewVT = V.getSimpleValueType();
7661 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7664 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7665 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7666 // Ensure the scalar operand is the same size as the destination.
7667 // FIXME: Add support for scalar truncation where possible.
7668 SDValue S = V.getOperand(Idx);
7669 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7670 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7676 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7678 /// This is particularly important because the set of instructions varies
7679 /// significantly based on whether the operand is a load or not.
7680 static bool isShuffleFoldableLoad(SDValue V) {
7681 while (V.getOpcode() == ISD::BITCAST)
7682 V = V.getOperand(0);
7684 return ISD::isNON_EXTLoad(V.getNode());
7687 /// \brief Try to lower insertion of a single element into a zero vector.
7689 /// This is a common pattern that we have especially efficient patterns to lower
7690 /// across all subtarget feature sets.
7691 static SDValue lowerVectorShuffleAsElementInsertion(
7692 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7693 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7694 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7696 MVT EltVT = VT.getVectorElementType();
7698 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7699 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7701 bool IsV1Zeroable = true;
7702 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7703 if (i != V2Index && !Zeroable[i]) {
7704 IsV1Zeroable = false;
7708 // Check for a single input from a SCALAR_TO_VECTOR node.
7709 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7710 // all the smarts here sunk into that routine. However, the current
7711 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7712 // vector shuffle lowering is dead.
7713 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7715 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7716 // We need to zext the scalar if it is smaller than an i32.
7717 V2S = DAG.getBitcast(EltVT, V2S);
7718 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7719 // Using zext to expand a narrow element won't work for non-zero
7724 // Zero-extend directly to i32.
7726 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7728 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7729 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7730 EltVT == MVT::i16) {
7731 // Either not inserting from the low element of the input or the input
7732 // element size is too small to use VZEXT_MOVL to clear the high bits.
7736 if (!IsV1Zeroable) {
7737 // If V1 can't be treated as a zero vector we have fewer options to lower
7738 // this. We can't support integer vectors or non-zero targets cheaply, and
7739 // the V1 elements can't be permuted in any way.
7740 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7741 if (!VT.isFloatingPoint() || V2Index != 0)
7743 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7744 V1Mask[V2Index] = -1;
7745 if (!isNoopShuffleMask(V1Mask))
7747 // This is essentially a special case blend operation, but if we have
7748 // general purpose blend operations, they are always faster. Bail and let
7749 // the rest of the lowering handle these as blends.
7750 if (Subtarget->hasSSE41())
7753 // Otherwise, use MOVSD or MOVSS.
7754 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7755 "Only two types of floating point element types to handle!");
7756 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7760 // This lowering only works for the low element with floating point vectors.
7761 if (VT.isFloatingPoint() && V2Index != 0)
7764 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7766 V2 = DAG.getBitcast(VT, V2);
7769 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7770 // the desired position. Otherwise it is more efficient to do a vector
7771 // shift left. We know that we can do a vector shift left because all
7772 // the inputs are zero.
7773 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7774 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7775 V2Shuffle[V2Index] = 0;
7776 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7778 V2 = DAG.getBitcast(MVT::v2i64, V2);
7780 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7781 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7782 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7783 DAG.getDataLayout(), VT)));
7784 V2 = DAG.getBitcast(VT, V2);
7790 /// \brief Try to lower broadcast of a single element.
7792 /// For convenience, this code also bundles all of the subtarget feature set
7793 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7794 /// a convenient way to factor it out.
7795 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7797 const X86Subtarget *Subtarget,
7798 SelectionDAG &DAG) {
7799 if (!Subtarget->hasAVX())
7801 if (VT.isInteger() && !Subtarget->hasAVX2())
7804 // Check that the mask is a broadcast.
7805 int BroadcastIdx = -1;
7807 if (M >= 0 && BroadcastIdx == -1)
7809 else if (M >= 0 && M != BroadcastIdx)
7812 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7813 "a sorted mask where the broadcast "
7816 // Go up the chain of (vector) values to find a scalar load that we can
7817 // combine with the broadcast.
7819 switch (V.getOpcode()) {
7820 case ISD::CONCAT_VECTORS: {
7821 int OperandSize = Mask.size() / V.getNumOperands();
7822 V = V.getOperand(BroadcastIdx / OperandSize);
7823 BroadcastIdx %= OperandSize;
7827 case ISD::INSERT_SUBVECTOR: {
7828 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7829 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7833 int BeginIdx = (int)ConstantIdx->getZExtValue();
7835 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7836 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7837 BroadcastIdx -= BeginIdx;
7848 // Check if this is a broadcast of a scalar. We special case lowering
7849 // for scalars so that we can more effectively fold with loads.
7850 // First, look through bitcast: if the original value has a larger element
7851 // type than the shuffle, the broadcast element is in essence truncated.
7852 // Make that explicit to ease folding.
7853 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7854 EVT EltVT = VT.getVectorElementType();
7855 SDValue V0 = V.getOperand(0);
7856 EVT V0VT = V0.getValueType();
7858 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7859 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7860 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7861 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7866 // Also check the simpler case, where we can directly reuse the scalar.
7867 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7868 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7869 V = V.getOperand(BroadcastIdx);
7871 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7872 // Only AVX2 has register broadcasts.
7873 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7875 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7876 // We can't broadcast from a vector register without AVX2, and we can only
7877 // broadcast from the zero-element of a vector register.
7881 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7884 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7885 // INSERTPS when the V1 elements are already in the correct locations
7886 // because otherwise we can just always use two SHUFPS instructions which
7887 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7888 // perform INSERTPS if a single V1 element is out of place and all V2
7889 // elements are zeroable.
7890 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7892 SelectionDAG &DAG) {
7893 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7894 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7895 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7896 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7898 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7901 int V1DstIndex = -1;
7902 int V2DstIndex = -1;
7903 bool V1UsedInPlace = false;
7905 for (int i = 0; i < 4; ++i) {
7906 // Synthesize a zero mask from the zeroable elements (includes undefs).
7912 // Flag if we use any V1 inputs in place.
7914 V1UsedInPlace = true;
7918 // We can only insert a single non-zeroable element.
7919 if (V1DstIndex != -1 || V2DstIndex != -1)
7923 // V1 input out of place for insertion.
7926 // V2 input for insertion.
7931 // Don't bother if we have no (non-zeroable) element for insertion.
7932 if (V1DstIndex == -1 && V2DstIndex == -1)
7935 // Determine element insertion src/dst indices. The src index is from the
7936 // start of the inserted vector, not the start of the concatenated vector.
7937 unsigned V2SrcIndex = 0;
7938 if (V1DstIndex != -1) {
7939 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7940 // and don't use the original V2 at all.
7941 V2SrcIndex = Mask[V1DstIndex];
7942 V2DstIndex = V1DstIndex;
7945 V2SrcIndex = Mask[V2DstIndex] - 4;
7948 // If no V1 inputs are used in place, then the result is created only from
7949 // the zero mask and the V2 insertion - so remove V1 dependency.
7951 V1 = DAG.getUNDEF(MVT::v4f32);
7953 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7954 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7956 // Insert the V2 element into the desired position.
7958 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7959 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7962 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7963 /// UNPCK instruction.
7965 /// This specifically targets cases where we end up with alternating between
7966 /// the two inputs, and so can permute them into something that feeds a single
7967 /// UNPCK instruction. Note that this routine only targets integer vectors
7968 /// because for floating point vectors we have a generalized SHUFPS lowering
7969 /// strategy that handles everything that doesn't *exactly* match an unpack,
7970 /// making this clever lowering unnecessary.
7971 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
7972 SDValue V1, SDValue V2,
7974 SelectionDAG &DAG) {
7975 assert(!VT.isFloatingPoint() &&
7976 "This routine only supports integer vectors.");
7977 assert(!isSingleInputShuffleMask(Mask) &&
7978 "This routine should only be used when blending two inputs.");
7979 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7981 int Size = Mask.size();
7983 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7984 return M >= 0 && M % Size < Size / 2;
7986 int NumHiInputs = std::count_if(
7987 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7989 bool UnpackLo = NumLoInputs >= NumHiInputs;
7991 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7992 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7993 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7995 for (int i = 0; i < Size; ++i) {
7999 // Each element of the unpack contains Scale elements from this mask.
8000 int UnpackIdx = i / Scale;
8002 // We only handle the case where V1 feeds the first slots of the unpack.
8003 // We rely on canonicalization to ensure this is the case.
8004 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8007 // Setup the mask for this input. The indexing is tricky as we have to
8008 // handle the unpack stride.
8009 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8010 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8014 // If we will have to shuffle both inputs to use the unpack, check whether
8015 // we can just unpack first and shuffle the result. If so, skip this unpack.
8016 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8017 !isNoopShuffleMask(V2Mask))
8020 // Shuffle the inputs into place.
8021 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8022 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8024 // Cast the inputs to the type we will use to unpack them.
8025 V1 = DAG.getBitcast(UnpackVT, V1);
8026 V2 = DAG.getBitcast(UnpackVT, V2);
8028 // Unpack the inputs and cast the result back to the desired type.
8029 return DAG.getBitcast(
8030 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8034 // We try each unpack from the largest to the smallest to try and find one
8035 // that fits this mask.
8036 int OrigNumElements = VT.getVectorNumElements();
8037 int OrigScalarSize = VT.getScalarSizeInBits();
8038 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8039 int Scale = ScalarSize / OrigScalarSize;
8040 int NumElements = OrigNumElements / Scale;
8041 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8042 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8046 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8048 if (NumLoInputs == 0 || NumHiInputs == 0) {
8049 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8050 "We have to have *some* inputs!");
8051 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8053 // FIXME: We could consider the total complexity of the permute of each
8054 // possible unpacking. Or at the least we should consider how many
8055 // half-crossings are created.
8056 // FIXME: We could consider commuting the unpacks.
8058 SmallVector<int, 32> PermMask;
8059 PermMask.assign(Size, -1);
8060 for (int i = 0; i < Size; ++i) {
8064 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8067 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8069 return DAG.getVectorShuffle(
8070 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8072 DAG.getUNDEF(VT), PermMask);
8078 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8080 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8081 /// support for floating point shuffles but not integer shuffles. These
8082 /// instructions will incur a domain crossing penalty on some chips though so
8083 /// it is better to avoid lowering through this for integer vectors where
8085 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8086 const X86Subtarget *Subtarget,
8087 SelectionDAG &DAG) {
8089 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8090 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8091 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8092 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8093 ArrayRef<int> Mask = SVOp->getMask();
8094 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8096 if (isSingleInputShuffleMask(Mask)) {
8097 // Use low duplicate instructions for masks that match their pattern.
8098 if (Subtarget->hasSSE3())
8099 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8100 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8102 // Straight shuffle of a single input vector. Simulate this by using the
8103 // single input as both of the "inputs" to this instruction..
8104 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8106 if (Subtarget->hasAVX()) {
8107 // If we have AVX, we can use VPERMILPS which will allow folding a load
8108 // into the shuffle.
8109 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8110 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8113 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8114 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8116 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8117 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8119 // If we have a single input, insert that into V1 if we can do so cheaply.
8120 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8121 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8122 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8124 // Try inverting the insertion since for v2 masks it is easy to do and we
8125 // can't reliably sort the mask one way or the other.
8126 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8127 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8128 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8129 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8133 // Try to use one of the special instruction patterns to handle two common
8134 // blend patterns if a zero-blend above didn't work.
8135 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8136 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8137 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8138 // We can either use a special instruction to load over the low double or
8139 // to move just the low double.
8141 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8143 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8145 if (Subtarget->hasSSE41())
8146 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8150 // Use dedicated unpack instructions for masks that match their pattern.
8151 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8152 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8153 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8154 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8156 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8157 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8158 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8161 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8163 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8164 /// the integer unit to minimize domain crossing penalties. However, for blends
8165 /// it falls back to the floating point shuffle operation with appropriate bit
8167 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8168 const X86Subtarget *Subtarget,
8169 SelectionDAG &DAG) {
8171 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8172 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8173 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8174 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8175 ArrayRef<int> Mask = SVOp->getMask();
8176 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8178 if (isSingleInputShuffleMask(Mask)) {
8179 // Check for being able to broadcast a single element.
8180 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8181 Mask, Subtarget, DAG))
8184 // Straight shuffle of a single input vector. For everything from SSE2
8185 // onward this has a single fast instruction with no scary immediates.
8186 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8187 V1 = DAG.getBitcast(MVT::v4i32, V1);
8188 int WidenedMask[4] = {
8189 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8190 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8191 return DAG.getBitcast(
8193 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8194 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8196 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8197 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8198 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8199 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8201 // If we have a blend of two PACKUS operations an the blend aligns with the
8202 // low and half halves, we can just merge the PACKUS operations. This is
8203 // particularly important as it lets us merge shuffles that this routine itself
8205 auto GetPackNode = [](SDValue V) {
8206 while (V.getOpcode() == ISD::BITCAST)
8207 V = V.getOperand(0);
8209 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8211 if (SDValue V1Pack = GetPackNode(V1))
8212 if (SDValue V2Pack = GetPackNode(V2))
8213 return DAG.getBitcast(MVT::v2i64,
8214 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8215 Mask[0] == 0 ? V1Pack.getOperand(0)
8216 : V1Pack.getOperand(1),
8217 Mask[1] == 2 ? V2Pack.getOperand(0)
8218 : V2Pack.getOperand(1)));
8220 // Try to use shift instructions.
8222 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8225 // When loading a scalar and then shuffling it into a vector we can often do
8226 // the insertion cheaply.
8227 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8228 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8230 // Try inverting the insertion since for v2 masks it is easy to do and we
8231 // can't reliably sort the mask one way or the other.
8232 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8233 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8234 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8237 // We have different paths for blend lowering, but they all must use the
8238 // *exact* same predicate.
8239 bool IsBlendSupported = Subtarget->hasSSE41();
8240 if (IsBlendSupported)
8241 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8245 // Use dedicated unpack instructions for masks that match their pattern.
8246 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8247 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8248 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8249 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8251 // Try to use byte rotation instructions.
8252 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8253 if (Subtarget->hasSSSE3())
8254 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8255 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8258 // If we have direct support for blends, we should lower by decomposing into
8259 // a permute. That will be faster than the domain cross.
8260 if (IsBlendSupported)
8261 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8264 // We implement this with SHUFPD which is pretty lame because it will likely
8265 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8266 // However, all the alternatives are still more cycles and newer chips don't
8267 // have this problem. It would be really nice if x86 had better shuffles here.
8268 V1 = DAG.getBitcast(MVT::v2f64, V1);
8269 V2 = DAG.getBitcast(MVT::v2f64, V2);
8270 return DAG.getBitcast(MVT::v2i64,
8271 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8274 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8276 /// This is used to disable more specialized lowerings when the shufps lowering
8277 /// will happen to be efficient.
8278 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8279 // This routine only handles 128-bit shufps.
8280 assert(Mask.size() == 4 && "Unsupported mask size!");
8282 // To lower with a single SHUFPS we need to have the low half and high half
8283 // each requiring a single input.
8284 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8286 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8292 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8294 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8295 /// It makes no assumptions about whether this is the *best* lowering, it simply
8297 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8298 ArrayRef<int> Mask, SDValue V1,
8299 SDValue V2, SelectionDAG &DAG) {
8300 SDValue LowV = V1, HighV = V2;
8301 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8304 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8306 if (NumV2Elements == 1) {
8308 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8311 // Compute the index adjacent to V2Index and in the same half by toggling
8313 int V2AdjIndex = V2Index ^ 1;
8315 if (Mask[V2AdjIndex] == -1) {
8316 // Handles all the cases where we have a single V2 element and an undef.
8317 // This will only ever happen in the high lanes because we commute the
8318 // vector otherwise.
8320 std::swap(LowV, HighV);
8321 NewMask[V2Index] -= 4;
8323 // Handle the case where the V2 element ends up adjacent to a V1 element.
8324 // To make this work, blend them together as the first step.
8325 int V1Index = V2AdjIndex;
8326 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8327 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8328 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8330 // Now proceed to reconstruct the final blend as we have the necessary
8331 // high or low half formed.
8338 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8339 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8341 } else if (NumV2Elements == 2) {
8342 if (Mask[0] < 4 && Mask[1] < 4) {
8343 // Handle the easy case where we have V1 in the low lanes and V2 in the
8347 } else if (Mask[2] < 4 && Mask[3] < 4) {
8348 // We also handle the reversed case because this utility may get called
8349 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8350 // arrange things in the right direction.
8356 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8357 // trying to place elements directly, just blend them and set up the final
8358 // shuffle to place them.
8360 // The first two blend mask elements are for V1, the second two are for
8362 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8363 Mask[2] < 4 ? Mask[2] : Mask[3],
8364 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8365 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8366 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8367 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8369 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8372 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8373 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8374 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8375 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8378 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8379 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8382 /// \brief Lower 4-lane 32-bit floating point shuffles.
8384 /// Uses instructions exclusively from the floating point unit to minimize
8385 /// domain crossing penalties, as these are sufficient to implement all v4f32
8387 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8388 const X86Subtarget *Subtarget,
8389 SelectionDAG &DAG) {
8391 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8392 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8393 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8394 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8395 ArrayRef<int> Mask = SVOp->getMask();
8396 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8399 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8401 if (NumV2Elements == 0) {
8402 // Check for being able to broadcast a single element.
8403 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8404 Mask, Subtarget, DAG))
8407 // Use even/odd duplicate instructions for masks that match their pattern.
8408 if (Subtarget->hasSSE3()) {
8409 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8410 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8411 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8412 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8415 if (Subtarget->hasAVX()) {
8416 // If we have AVX, we can use VPERMILPS which will allow folding a load
8417 // into the shuffle.
8418 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8419 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8422 // Otherwise, use a straight shuffle of a single input vector. We pass the
8423 // input vector to both operands to simulate this with a SHUFPS.
8424 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8425 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8428 // There are special ways we can lower some single-element blends. However, we
8429 // have custom ways we can lower more complex single-element blends below that
8430 // we defer to if both this and BLENDPS fail to match, so restrict this to
8431 // when the V2 input is targeting element 0 of the mask -- that is the fast
8433 if (NumV2Elements == 1 && Mask[0] >= 4)
8434 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8435 Mask, Subtarget, DAG))
8438 if (Subtarget->hasSSE41()) {
8439 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8443 // Use INSERTPS if we can complete the shuffle efficiently.
8444 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8447 if (!isSingleSHUFPSMask(Mask))
8448 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8449 DL, MVT::v4f32, V1, V2, Mask, DAG))
8453 // Use dedicated unpack instructions for masks that match their pattern.
8454 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8455 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8456 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8457 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8458 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8459 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8460 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8461 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8463 // Otherwise fall back to a SHUFPS lowering strategy.
8464 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8467 /// \brief Lower 4-lane i32 vector shuffles.
8469 /// We try to handle these with integer-domain shuffles where we can, but for
8470 /// blends we use the floating point domain blend instructions.
8471 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8472 const X86Subtarget *Subtarget,
8473 SelectionDAG &DAG) {
8475 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8476 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8477 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8478 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8479 ArrayRef<int> Mask = SVOp->getMask();
8480 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8482 // Whenever we can lower this as a zext, that instruction is strictly faster
8483 // than any alternative. It also allows us to fold memory operands into the
8484 // shuffle in many cases.
8485 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8486 Mask, Subtarget, DAG))
8490 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8492 if (NumV2Elements == 0) {
8493 // Check for being able to broadcast a single element.
8494 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8495 Mask, Subtarget, DAG))
8498 // Straight shuffle of a single input vector. For everything from SSE2
8499 // onward this has a single fast instruction with no scary immediates.
8500 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8501 // but we aren't actually going to use the UNPCK instruction because doing
8502 // so prevents folding a load into this instruction or making a copy.
8503 const int UnpackLoMask[] = {0, 0, 1, 1};
8504 const int UnpackHiMask[] = {2, 2, 3, 3};
8505 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8506 Mask = UnpackLoMask;
8507 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8508 Mask = UnpackHiMask;
8510 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8511 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8514 // Try to use shift instructions.
8516 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8519 // There are special ways we can lower some single-element blends.
8520 if (NumV2Elements == 1)
8521 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8522 Mask, Subtarget, DAG))
8525 // We have different paths for blend lowering, but they all must use the
8526 // *exact* same predicate.
8527 bool IsBlendSupported = Subtarget->hasSSE41();
8528 if (IsBlendSupported)
8529 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8533 if (SDValue Masked =
8534 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8537 // Use dedicated unpack instructions for masks that match their pattern.
8538 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8539 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8540 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8541 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8542 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8543 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8544 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8545 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8547 // Try to use byte rotation instructions.
8548 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8549 if (Subtarget->hasSSSE3())
8550 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8551 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8554 // If we have direct support for blends, we should lower by decomposing into
8555 // a permute. That will be faster than the domain cross.
8556 if (IsBlendSupported)
8557 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8560 // Try to lower by permuting the inputs into an unpack instruction.
8561 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8565 // We implement this with SHUFPS because it can blend from two vectors.
8566 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8567 // up the inputs, bypassing domain shift penalties that we would encur if we
8568 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8570 return DAG.getBitcast(
8572 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8573 DAG.getBitcast(MVT::v4f32, V2), Mask));
8576 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8577 /// shuffle lowering, and the most complex part.
8579 /// The lowering strategy is to try to form pairs of input lanes which are
8580 /// targeted at the same half of the final vector, and then use a dword shuffle
8581 /// to place them onto the right half, and finally unpack the paired lanes into
8582 /// their final position.
8584 /// The exact breakdown of how to form these dword pairs and align them on the
8585 /// correct sides is really tricky. See the comments within the function for
8586 /// more of the details.
8588 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8589 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8590 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8591 /// vector, form the analogous 128-bit 8-element Mask.
8592 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8593 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8594 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8595 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8596 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8598 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8599 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8600 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8602 SmallVector<int, 4> LoInputs;
8603 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8604 [](int M) { return M >= 0; });
8605 std::sort(LoInputs.begin(), LoInputs.end());
8606 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8607 SmallVector<int, 4> HiInputs;
8608 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8609 [](int M) { return M >= 0; });
8610 std::sort(HiInputs.begin(), HiInputs.end());
8611 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8613 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8614 int NumHToL = LoInputs.size() - NumLToL;
8616 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8617 int NumHToH = HiInputs.size() - NumLToH;
8618 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8619 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8620 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8621 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8623 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8624 // such inputs we can swap two of the dwords across the half mark and end up
8625 // with <=2 inputs to each half in each half. Once there, we can fall through
8626 // to the generic code below. For example:
8628 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8629 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8631 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8632 // and an existing 2-into-2 on the other half. In this case we may have to
8633 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8634 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8635 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8636 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8637 // half than the one we target for fixing) will be fixed when we re-enter this
8638 // path. We will also combine away any sequence of PSHUFD instructions that
8639 // result into a single instruction. Here is an example of the tricky case:
8641 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8642 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8644 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8646 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8647 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8649 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8650 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8652 // The result is fine to be handled by the generic logic.
8653 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8654 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8655 int AOffset, int BOffset) {
8656 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8657 "Must call this with A having 3 or 1 inputs from the A half.");
8658 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8659 "Must call this with B having 1 or 3 inputs from the B half.");
8660 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8661 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8663 bool ThreeAInputs = AToAInputs.size() == 3;
8665 // Compute the index of dword with only one word among the three inputs in
8666 // a half by taking the sum of the half with three inputs and subtracting
8667 // the sum of the actual three inputs. The difference is the remaining
8670 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8671 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8672 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8673 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8674 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8675 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8676 int TripleNonInputIdx =
8677 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8678 TripleDWord = TripleNonInputIdx / 2;
8680 // We use xor with one to compute the adjacent DWord to whichever one the
8682 OneInputDWord = (OneInput / 2) ^ 1;
8684 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8685 // and BToA inputs. If there is also such a problem with the BToB and AToB
8686 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8687 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8688 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8689 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8690 // Compute how many inputs will be flipped by swapping these DWords. We
8692 // to balance this to ensure we don't form a 3-1 shuffle in the other
8694 int NumFlippedAToBInputs =
8695 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8696 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8697 int NumFlippedBToBInputs =
8698 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8699 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8700 if ((NumFlippedAToBInputs == 1 &&
8701 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8702 (NumFlippedBToBInputs == 1 &&
8703 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8704 // We choose whether to fix the A half or B half based on whether that
8705 // half has zero flipped inputs. At zero, we may not be able to fix it
8706 // with that half. We also bias towards fixing the B half because that
8707 // will more commonly be the high half, and we have to bias one way.
8708 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8709 ArrayRef<int> Inputs) {
8710 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8711 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8712 PinnedIdx ^ 1) != Inputs.end();
8713 // Determine whether the free index is in the flipped dword or the
8714 // unflipped dword based on where the pinned index is. We use this bit
8715 // in an xor to conditionally select the adjacent dword.
8716 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8717 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8718 FixFreeIdx) != Inputs.end();
8719 if (IsFixIdxInput == IsFixFreeIdxInput)
8721 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8722 FixFreeIdx) != Inputs.end();
8723 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8724 "We need to be changing the number of flipped inputs!");
8725 int PSHUFHalfMask[] = {0, 1, 2, 3};
8726 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8727 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8729 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8732 if (M != -1 && M == FixIdx)
8734 else if (M != -1 && M == FixFreeIdx)
8737 if (NumFlippedBToBInputs != 0) {
8739 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8740 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8742 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8743 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8744 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8749 int PSHUFDMask[] = {0, 1, 2, 3};
8750 PSHUFDMask[ADWord] = BDWord;
8751 PSHUFDMask[BDWord] = ADWord;
8754 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8755 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8757 // Adjust the mask to match the new locations of A and B.
8759 if (M != -1 && M/2 == ADWord)
8760 M = 2 * BDWord + M % 2;
8761 else if (M != -1 && M/2 == BDWord)
8762 M = 2 * ADWord + M % 2;
8764 // Recurse back into this routine to re-compute state now that this isn't
8765 // a 3 and 1 problem.
8766 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8769 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8770 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8771 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8772 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8774 // At this point there are at most two inputs to the low and high halves from
8775 // each half. That means the inputs can always be grouped into dwords and
8776 // those dwords can then be moved to the correct half with a dword shuffle.
8777 // We use at most one low and one high word shuffle to collect these paired
8778 // inputs into dwords, and finally a dword shuffle to place them.
8779 int PSHUFLMask[4] = {-1, -1, -1, -1};
8780 int PSHUFHMask[4] = {-1, -1, -1, -1};
8781 int PSHUFDMask[4] = {-1, -1, -1, -1};
8783 // First fix the masks for all the inputs that are staying in their
8784 // original halves. This will then dictate the targets of the cross-half
8786 auto fixInPlaceInputs =
8787 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8788 MutableArrayRef<int> SourceHalfMask,
8789 MutableArrayRef<int> HalfMask, int HalfOffset) {
8790 if (InPlaceInputs.empty())
8792 if (InPlaceInputs.size() == 1) {
8793 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8794 InPlaceInputs[0] - HalfOffset;
8795 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8798 if (IncomingInputs.empty()) {
8799 // Just fix all of the in place inputs.
8800 for (int Input : InPlaceInputs) {
8801 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8802 PSHUFDMask[Input / 2] = Input / 2;
8807 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8808 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8809 InPlaceInputs[0] - HalfOffset;
8810 // Put the second input next to the first so that they are packed into
8811 // a dword. We find the adjacent index by toggling the low bit.
8812 int AdjIndex = InPlaceInputs[0] ^ 1;
8813 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8814 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8815 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8817 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8818 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8820 // Now gather the cross-half inputs and place them into a free dword of
8821 // their target half.
8822 // FIXME: This operation could almost certainly be simplified dramatically to
8823 // look more like the 3-1 fixing operation.
8824 auto moveInputsToRightHalf = [&PSHUFDMask](
8825 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8826 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8827 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8829 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8830 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8832 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8834 int LowWord = Word & ~1;
8835 int HighWord = Word | 1;
8836 return isWordClobbered(SourceHalfMask, LowWord) ||
8837 isWordClobbered(SourceHalfMask, HighWord);
8840 if (IncomingInputs.empty())
8843 if (ExistingInputs.empty()) {
8844 // Map any dwords with inputs from them into the right half.
8845 for (int Input : IncomingInputs) {
8846 // If the source half mask maps over the inputs, turn those into
8847 // swaps and use the swapped lane.
8848 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8849 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8850 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8851 Input - SourceOffset;
8852 // We have to swap the uses in our half mask in one sweep.
8853 for (int &M : HalfMask)
8854 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8856 else if (M == Input)
8857 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8859 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8860 Input - SourceOffset &&
8861 "Previous placement doesn't match!");
8863 // Note that this correctly re-maps both when we do a swap and when
8864 // we observe the other side of the swap above. We rely on that to
8865 // avoid swapping the members of the input list directly.
8866 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8869 // Map the input's dword into the correct half.
8870 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8871 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8873 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8875 "Previous placement doesn't match!");
8878 // And just directly shift any other-half mask elements to be same-half
8879 // as we will have mirrored the dword containing the element into the
8880 // same position within that half.
8881 for (int &M : HalfMask)
8882 if (M >= SourceOffset && M < SourceOffset + 4) {
8883 M = M - SourceOffset + DestOffset;
8884 assert(M >= 0 && "This should never wrap below zero!");
8889 // Ensure we have the input in a viable dword of its current half. This
8890 // is particularly tricky because the original position may be clobbered
8891 // by inputs being moved and *staying* in that half.
8892 if (IncomingInputs.size() == 1) {
8893 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8894 int InputFixed = std::find(std::begin(SourceHalfMask),
8895 std::end(SourceHalfMask), -1) -
8896 std::begin(SourceHalfMask) + SourceOffset;
8897 SourceHalfMask[InputFixed - SourceOffset] =
8898 IncomingInputs[0] - SourceOffset;
8899 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8901 IncomingInputs[0] = InputFixed;
8903 } else if (IncomingInputs.size() == 2) {
8904 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8905 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8906 // We have two non-adjacent or clobbered inputs we need to extract from
8907 // the source half. To do this, we need to map them into some adjacent
8908 // dword slot in the source mask.
8909 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8910 IncomingInputs[1] - SourceOffset};
8912 // If there is a free slot in the source half mask adjacent to one of
8913 // the inputs, place the other input in it. We use (Index XOR 1) to
8914 // compute an adjacent index.
8915 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8916 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8917 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8918 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8919 InputsFixed[1] = InputsFixed[0] ^ 1;
8920 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8921 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8922 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8923 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8924 InputsFixed[0] = InputsFixed[1] ^ 1;
8925 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8926 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8927 // The two inputs are in the same DWord but it is clobbered and the
8928 // adjacent DWord isn't used at all. Move both inputs to the free
8930 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8931 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8932 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8933 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8935 // The only way we hit this point is if there is no clobbering
8936 // (because there are no off-half inputs to this half) and there is no
8937 // free slot adjacent to one of the inputs. In this case, we have to
8938 // swap an input with a non-input.
8939 for (int i = 0; i < 4; ++i)
8940 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8941 "We can't handle any clobbers here!");
8942 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8943 "Cannot have adjacent inputs here!");
8945 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8946 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8948 // We also have to update the final source mask in this case because
8949 // it may need to undo the above swap.
8950 for (int &M : FinalSourceHalfMask)
8951 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8952 M = InputsFixed[1] + SourceOffset;
8953 else if (M == InputsFixed[1] + SourceOffset)
8954 M = (InputsFixed[0] ^ 1) + SourceOffset;
8956 InputsFixed[1] = InputsFixed[0] ^ 1;
8959 // Point everything at the fixed inputs.
8960 for (int &M : HalfMask)
8961 if (M == IncomingInputs[0])
8962 M = InputsFixed[0] + SourceOffset;
8963 else if (M == IncomingInputs[1])
8964 M = InputsFixed[1] + SourceOffset;
8966 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8967 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8970 llvm_unreachable("Unhandled input size!");
8973 // Now hoist the DWord down to the right half.
8974 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8975 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8976 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8977 for (int &M : HalfMask)
8978 for (int Input : IncomingInputs)
8980 M = FreeDWord * 2 + Input % 2;
8982 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8983 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8984 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8985 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8987 // Now enact all the shuffles we've computed to move the inputs into their
8989 if (!isNoopShuffleMask(PSHUFLMask))
8990 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8991 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8992 if (!isNoopShuffleMask(PSHUFHMask))
8993 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8994 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8995 if (!isNoopShuffleMask(PSHUFDMask))
8998 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8999 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9001 // At this point, each half should contain all its inputs, and we can then
9002 // just shuffle them into their final position.
9003 assert(std::count_if(LoMask.begin(), LoMask.end(),
9004 [](int M) { return M >= 4; }) == 0 &&
9005 "Failed to lift all the high half inputs to the low mask!");
9006 assert(std::count_if(HiMask.begin(), HiMask.end(),
9007 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9008 "Failed to lift all the low half inputs to the high mask!");
9010 // Do a half shuffle for the low mask.
9011 if (!isNoopShuffleMask(LoMask))
9012 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9013 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9015 // Do a half shuffle with the high mask after shifting its values down.
9016 for (int &M : HiMask)
9019 if (!isNoopShuffleMask(HiMask))
9020 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9021 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9026 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9027 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9028 SDValue V2, ArrayRef<int> Mask,
9029 SelectionDAG &DAG, bool &V1InUse,
9031 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9037 int Size = Mask.size();
9038 int Scale = 16 / Size;
9039 for (int i = 0; i < 16; ++i) {
9040 if (Mask[i / Scale] == -1) {
9041 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9043 const int ZeroMask = 0x80;
9044 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9046 int V2Idx = Mask[i / Scale] < Size
9048 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9049 if (Zeroable[i / Scale])
9050 V1Idx = V2Idx = ZeroMask;
9051 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9052 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9053 V1InUse |= (ZeroMask != V1Idx);
9054 V2InUse |= (ZeroMask != V2Idx);
9059 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9060 DAG.getBitcast(MVT::v16i8, V1),
9061 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9063 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9064 DAG.getBitcast(MVT::v16i8, V2),
9065 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9067 // If we need shuffled inputs from both, blend the two.
9069 if (V1InUse && V2InUse)
9070 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9072 V = V1InUse ? V1 : V2;
9074 // Cast the result back to the correct type.
9075 return DAG.getBitcast(VT, V);
9078 /// \brief Generic lowering of 8-lane i16 shuffles.
9080 /// This handles both single-input shuffles and combined shuffle/blends with
9081 /// two inputs. The single input shuffles are immediately delegated to
9082 /// a dedicated lowering routine.
9084 /// The blends are lowered in one of three fundamental ways. If there are few
9085 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9086 /// of the input is significantly cheaper when lowered as an interleaving of
9087 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9088 /// halves of the inputs separately (making them have relatively few inputs)
9089 /// and then concatenate them.
9090 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9091 const X86Subtarget *Subtarget,
9092 SelectionDAG &DAG) {
9094 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9095 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9096 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9097 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9098 ArrayRef<int> OrigMask = SVOp->getMask();
9099 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9100 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9101 MutableArrayRef<int> Mask(MaskStorage);
9103 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9105 // Whenever we can lower this as a zext, that instruction is strictly faster
9106 // than any alternative.
9107 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9108 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9111 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9113 auto isV2 = [](int M) { return M >= 8; };
9115 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9117 if (NumV2Inputs == 0) {
9118 // Check for being able to broadcast a single element.
9119 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9120 Mask, Subtarget, DAG))
9123 // Try to use shift instructions.
9125 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9128 // Use dedicated unpack instructions for masks that match their pattern.
9129 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
9130 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
9131 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
9132 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
9134 // Try to use byte rotation instructions.
9135 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9136 Mask, Subtarget, DAG))
9139 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9143 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9144 "All single-input shuffles should be canonicalized to be V1-input "
9147 // Try to use shift instructions.
9149 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9152 // See if we can use SSE4A Extraction / Insertion.
9153 if (Subtarget->hasSSE4A())
9154 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9157 // There are special ways we can lower some single-element blends.
9158 if (NumV2Inputs == 1)
9159 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9160 Mask, Subtarget, DAG))
9163 // We have different paths for blend lowering, but they all must use the
9164 // *exact* same predicate.
9165 bool IsBlendSupported = Subtarget->hasSSE41();
9166 if (IsBlendSupported)
9167 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9171 if (SDValue Masked =
9172 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9175 // Use dedicated unpack instructions for masks that match their pattern.
9176 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
9177 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9178 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
9179 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9181 // Try to use byte rotation instructions.
9182 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9183 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9186 if (SDValue BitBlend =
9187 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9190 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9194 // If we can't directly blend but can use PSHUFB, that will be better as it
9195 // can both shuffle and set up the inefficient blend.
9196 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9197 bool V1InUse, V2InUse;
9198 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9202 // We can always bit-blend if we have to so the fallback strategy is to
9203 // decompose into single-input permutes and blends.
9204 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9208 /// \brief Check whether a compaction lowering can be done by dropping even
9209 /// elements and compute how many times even elements must be dropped.
9211 /// This handles shuffles which take every Nth element where N is a power of
9212 /// two. Example shuffle masks:
9214 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9215 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9216 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9217 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9218 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9219 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9221 /// Any of these lanes can of course be undef.
9223 /// This routine only supports N <= 3.
9224 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9227 /// \returns N above, or the number of times even elements must be dropped if
9228 /// there is such a number. Otherwise returns zero.
9229 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9230 // Figure out whether we're looping over two inputs or just one.
9231 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9233 // The modulus for the shuffle vector entries is based on whether this is
9234 // a single input or not.
9235 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9236 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9237 "We should only be called with masks with a power-of-2 size!");
9239 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9241 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9242 // and 2^3 simultaneously. This is because we may have ambiguity with
9243 // partially undef inputs.
9244 bool ViableForN[3] = {true, true, true};
9246 for (int i = 0, e = Mask.size(); i < e; ++i) {
9247 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9252 bool IsAnyViable = false;
9253 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9254 if (ViableForN[j]) {
9257 // The shuffle mask must be equal to (i * 2^N) % M.
9258 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9261 ViableForN[j] = false;
9263 // Early exit if we exhaust the possible powers of two.
9268 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9272 // Return 0 as there is no viable power of two.
9276 /// \brief Generic lowering of v16i8 shuffles.
9278 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9279 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9280 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9281 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9283 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9284 const X86Subtarget *Subtarget,
9285 SelectionDAG &DAG) {
9287 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9288 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9289 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9290 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9291 ArrayRef<int> Mask = SVOp->getMask();
9292 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9294 // Try to use shift instructions.
9296 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9299 // Try to use byte rotation instructions.
9300 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9301 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9304 // Try to use a zext lowering.
9305 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9306 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9309 // See if we can use SSE4A Extraction / Insertion.
9310 if (Subtarget->hasSSE4A())
9311 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9315 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9317 // For single-input shuffles, there are some nicer lowering tricks we can use.
9318 if (NumV2Elements == 0) {
9319 // Check for being able to broadcast a single element.
9320 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9321 Mask, Subtarget, DAG))
9324 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9325 // Notably, this handles splat and partial-splat shuffles more efficiently.
9326 // However, it only makes sense if the pre-duplication shuffle simplifies
9327 // things significantly. Currently, this means we need to be able to
9328 // express the pre-duplication shuffle as an i16 shuffle.
9330 // FIXME: We should check for other patterns which can be widened into an
9331 // i16 shuffle as well.
9332 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9333 for (int i = 0; i < 16; i += 2)
9334 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9339 auto tryToWidenViaDuplication = [&]() -> SDValue {
9340 if (!canWidenViaDuplication(Mask))
9342 SmallVector<int, 4> LoInputs;
9343 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9344 [](int M) { return M >= 0 && M < 8; });
9345 std::sort(LoInputs.begin(), LoInputs.end());
9346 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9348 SmallVector<int, 4> HiInputs;
9349 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9350 [](int M) { return M >= 8; });
9351 std::sort(HiInputs.begin(), HiInputs.end());
9352 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9355 bool TargetLo = LoInputs.size() >= HiInputs.size();
9356 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9357 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9359 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9360 SmallDenseMap<int, int, 8> LaneMap;
9361 for (int I : InPlaceInputs) {
9362 PreDupI16Shuffle[I/2] = I/2;
9365 int j = TargetLo ? 0 : 4, je = j + 4;
9366 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9367 // Check if j is already a shuffle of this input. This happens when
9368 // there are two adjacent bytes after we move the low one.
9369 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9370 // If we haven't yet mapped the input, search for a slot into which
9372 while (j < je && PreDupI16Shuffle[j] != -1)
9376 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9379 // Map this input with the i16 shuffle.
9380 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9383 // Update the lane map based on the mapping we ended up with.
9384 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9386 V1 = DAG.getBitcast(
9388 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9389 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9391 // Unpack the bytes to form the i16s that will be shuffled into place.
9392 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9393 MVT::v16i8, V1, V1);
9395 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9396 for (int i = 0; i < 16; ++i)
9397 if (Mask[i] != -1) {
9398 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9399 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9400 if (PostDupI16Shuffle[i / 2] == -1)
9401 PostDupI16Shuffle[i / 2] = MappedMask;
9403 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9404 "Conflicting entrties in the original shuffle!");
9406 return DAG.getBitcast(
9408 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9409 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9411 if (SDValue V = tryToWidenViaDuplication())
9415 if (SDValue Masked =
9416 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9419 // Use dedicated unpack instructions for masks that match their pattern.
9420 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9421 0, 16, 1, 17, 2, 18, 3, 19,
9423 4, 20, 5, 21, 6, 22, 7, 23}))
9424 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9425 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9426 8, 24, 9, 25, 10, 26, 11, 27,
9428 12, 28, 13, 29, 14, 30, 15, 31}))
9429 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9431 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9432 // with PSHUFB. It is important to do this before we attempt to generate any
9433 // blends but after all of the single-input lowerings. If the single input
9434 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9435 // want to preserve that and we can DAG combine any longer sequences into
9436 // a PSHUFB in the end. But once we start blending from multiple inputs,
9437 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9438 // and there are *very* few patterns that would actually be faster than the
9439 // PSHUFB approach because of its ability to zero lanes.
9441 // FIXME: The only exceptions to the above are blends which are exact
9442 // interleavings with direct instructions supporting them. We currently don't
9443 // handle those well here.
9444 if (Subtarget->hasSSSE3()) {
9445 bool V1InUse = false;
9446 bool V2InUse = false;
9448 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9449 DAG, V1InUse, V2InUse);
9451 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9452 // do so. This avoids using them to handle blends-with-zero which is
9453 // important as a single pshufb is significantly faster for that.
9454 if (V1InUse && V2InUse) {
9455 if (Subtarget->hasSSE41())
9456 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9457 Mask, Subtarget, DAG))
9460 // We can use an unpack to do the blending rather than an or in some
9461 // cases. Even though the or may be (very minorly) more efficient, we
9462 // preference this lowering because there are common cases where part of
9463 // the complexity of the shuffles goes away when we do the final blend as
9465 // FIXME: It might be worth trying to detect if the unpack-feeding
9466 // shuffles will both be pshufb, in which case we shouldn't bother with
9468 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9469 DL, MVT::v16i8, V1, V2, Mask, DAG))
9476 // There are special ways we can lower some single-element blends.
9477 if (NumV2Elements == 1)
9478 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9479 Mask, Subtarget, DAG))
9482 if (SDValue BitBlend =
9483 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9486 // Check whether a compaction lowering can be done. This handles shuffles
9487 // which take every Nth element for some even N. See the helper function for
9490 // We special case these as they can be particularly efficiently handled with
9491 // the PACKUSB instruction on x86 and they show up in common patterns of
9492 // rearranging bytes to truncate wide elements.
9493 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9494 // NumEvenDrops is the power of two stride of the elements. Another way of
9495 // thinking about it is that we need to drop the even elements this many
9496 // times to get the original input.
9497 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9499 // First we need to zero all the dropped bytes.
9500 assert(NumEvenDrops <= 3 &&
9501 "No support for dropping even elements more than 3 times.");
9502 // We use the mask type to pick which bytes are preserved based on how many
9503 // elements are dropped.
9504 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9505 SDValue ByteClearMask = DAG.getBitcast(
9506 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9507 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9509 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9511 // Now pack things back together.
9512 V1 = DAG.getBitcast(MVT::v8i16, V1);
9513 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9514 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9515 for (int i = 1; i < NumEvenDrops; ++i) {
9516 Result = DAG.getBitcast(MVT::v8i16, Result);
9517 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9523 // Handle multi-input cases by blending single-input shuffles.
9524 if (NumV2Elements > 0)
9525 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9528 // The fallback path for single-input shuffles widens this into two v8i16
9529 // vectors with unpacks, shuffles those, and then pulls them back together
9533 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9534 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9535 for (int i = 0; i < 16; ++i)
9537 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9539 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9541 SDValue VLoHalf, VHiHalf;
9542 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9543 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9545 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9546 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9547 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9548 [](int M) { return M >= 0 && M % 2 == 1; })) {
9549 // Use a mask to drop the high bytes.
9550 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9551 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9552 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9554 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9555 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9557 // Squash the masks to point directly into VLoHalf.
9558 for (int &M : LoBlendMask)
9561 for (int &M : HiBlendMask)
9565 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9566 // VHiHalf so that we can blend them as i16s.
9567 VLoHalf = DAG.getBitcast(
9568 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9569 VHiHalf = DAG.getBitcast(
9570 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9573 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9574 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9576 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9579 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9581 /// This routine breaks down the specific type of 128-bit shuffle and
9582 /// dispatches to the lowering routines accordingly.
9583 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9584 MVT VT, const X86Subtarget *Subtarget,
9585 SelectionDAG &DAG) {
9586 switch (VT.SimpleTy) {
9588 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9590 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9592 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9594 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9596 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9598 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9601 llvm_unreachable("Unimplemented!");
9605 /// \brief Helper function to test whether a shuffle mask could be
9606 /// simplified by widening the elements being shuffled.
9608 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9609 /// leaves it in an unspecified state.
9611 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9612 /// shuffle masks. The latter have the special property of a '-2' representing
9613 /// a zero-ed lane of a vector.
9614 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9615 SmallVectorImpl<int> &WidenedMask) {
9616 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9617 // If both elements are undef, its trivial.
9618 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9619 WidenedMask.push_back(SM_SentinelUndef);
9623 // Check for an undef mask and a mask value properly aligned to fit with
9624 // a pair of values. If we find such a case, use the non-undef mask's value.
9625 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9626 WidenedMask.push_back(Mask[i + 1] / 2);
9629 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9630 WidenedMask.push_back(Mask[i] / 2);
9634 // When zeroing, we need to spread the zeroing across both lanes to widen.
9635 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9636 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9637 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9638 WidenedMask.push_back(SM_SentinelZero);
9644 // Finally check if the two mask values are adjacent and aligned with
9646 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9647 WidenedMask.push_back(Mask[i] / 2);
9651 // Otherwise we can't safely widen the elements used in this shuffle.
9654 assert(WidenedMask.size() == Mask.size() / 2 &&
9655 "Incorrect size of mask after widening the elements!");
9660 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9662 /// This routine just extracts two subvectors, shuffles them independently, and
9663 /// then concatenates them back together. This should work effectively with all
9664 /// AVX vector shuffle types.
9665 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9666 SDValue V2, ArrayRef<int> Mask,
9667 SelectionDAG &DAG) {
9668 assert(VT.getSizeInBits() >= 256 &&
9669 "Only for 256-bit or wider vector shuffles!");
9670 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9671 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9673 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9674 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9676 int NumElements = VT.getVectorNumElements();
9677 int SplitNumElements = NumElements / 2;
9678 MVT ScalarVT = VT.getScalarType();
9679 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9681 // Rather than splitting build-vectors, just build two narrower build
9682 // vectors. This helps shuffling with splats and zeros.
9683 auto SplitVector = [&](SDValue V) {
9684 while (V.getOpcode() == ISD::BITCAST)
9685 V = V->getOperand(0);
9687 MVT OrigVT = V.getSimpleValueType();
9688 int OrigNumElements = OrigVT.getVectorNumElements();
9689 int OrigSplitNumElements = OrigNumElements / 2;
9690 MVT OrigScalarVT = OrigVT.getScalarType();
9691 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9695 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9697 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9698 DAG.getIntPtrConstant(0, DL));
9699 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9700 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9703 SmallVector<SDValue, 16> LoOps, HiOps;
9704 for (int i = 0; i < OrigSplitNumElements; ++i) {
9705 LoOps.push_back(BV->getOperand(i));
9706 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9708 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9709 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9711 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9712 DAG.getBitcast(SplitVT, HiV));
9715 SDValue LoV1, HiV1, LoV2, HiV2;
9716 std::tie(LoV1, HiV1) = SplitVector(V1);
9717 std::tie(LoV2, HiV2) = SplitVector(V2);
9719 // Now create two 4-way blends of these half-width vectors.
9720 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9721 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9722 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9723 for (int i = 0; i < SplitNumElements; ++i) {
9724 int M = HalfMask[i];
9725 if (M >= NumElements) {
9726 if (M >= NumElements + SplitNumElements)
9730 V2BlendMask.push_back(M - NumElements);
9731 V1BlendMask.push_back(-1);
9732 BlendMask.push_back(SplitNumElements + i);
9733 } else if (M >= 0) {
9734 if (M >= SplitNumElements)
9738 V2BlendMask.push_back(-1);
9739 V1BlendMask.push_back(M);
9740 BlendMask.push_back(i);
9742 V2BlendMask.push_back(-1);
9743 V1BlendMask.push_back(-1);
9744 BlendMask.push_back(-1);
9748 // Because the lowering happens after all combining takes place, we need to
9749 // manually combine these blend masks as much as possible so that we create
9750 // a minimal number of high-level vector shuffle nodes.
9752 // First try just blending the halves of V1 or V2.
9753 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9754 return DAG.getUNDEF(SplitVT);
9755 if (!UseLoV2 && !UseHiV2)
9756 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9757 if (!UseLoV1 && !UseHiV1)
9758 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9760 SDValue V1Blend, V2Blend;
9761 if (UseLoV1 && UseHiV1) {
9763 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9765 // We only use half of V1 so map the usage down into the final blend mask.
9766 V1Blend = UseLoV1 ? LoV1 : HiV1;
9767 for (int i = 0; i < SplitNumElements; ++i)
9768 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9769 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9771 if (UseLoV2 && UseHiV2) {
9773 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9775 // We only use half of V2 so map the usage down into the final blend mask.
9776 V2Blend = UseLoV2 ? LoV2 : HiV2;
9777 for (int i = 0; i < SplitNumElements; ++i)
9778 if (BlendMask[i] >= SplitNumElements)
9779 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9781 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9783 SDValue Lo = HalfBlend(LoMask);
9784 SDValue Hi = HalfBlend(HiMask);
9785 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9788 /// \brief Either split a vector in halves or decompose the shuffles and the
9791 /// This is provided as a good fallback for many lowerings of non-single-input
9792 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9793 /// between splitting the shuffle into 128-bit components and stitching those
9794 /// back together vs. extracting the single-input shuffles and blending those
9796 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9797 SDValue V2, ArrayRef<int> Mask,
9798 SelectionDAG &DAG) {
9799 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9800 "lower single-input shuffles as it "
9801 "could then recurse on itself.");
9802 int Size = Mask.size();
9804 // If this can be modeled as a broadcast of two elements followed by a blend,
9805 // prefer that lowering. This is especially important because broadcasts can
9806 // often fold with memory operands.
9807 auto DoBothBroadcast = [&] {
9808 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9811 if (V2BroadcastIdx == -1)
9812 V2BroadcastIdx = M - Size;
9813 else if (M - Size != V2BroadcastIdx)
9815 } else if (M >= 0) {
9816 if (V1BroadcastIdx == -1)
9818 else if (M != V1BroadcastIdx)
9823 if (DoBothBroadcast())
9824 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9827 // If the inputs all stem from a single 128-bit lane of each input, then we
9828 // split them rather than blending because the split will decompose to
9829 // unusually few instructions.
9830 int LaneCount = VT.getSizeInBits() / 128;
9831 int LaneSize = Size / LaneCount;
9832 SmallBitVector LaneInputs[2];
9833 LaneInputs[0].resize(LaneCount, false);
9834 LaneInputs[1].resize(LaneCount, false);
9835 for (int i = 0; i < Size; ++i)
9837 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9838 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9839 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9841 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9842 // that the decomposed single-input shuffles don't end up here.
9843 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9846 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9847 /// a permutation and blend of those lanes.
9849 /// This essentially blends the out-of-lane inputs to each lane into the lane
9850 /// from a permuted copy of the vector. This lowering strategy results in four
9851 /// instructions in the worst case for a single-input cross lane shuffle which
9852 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9853 /// of. Special cases for each particular shuffle pattern should be handled
9854 /// prior to trying this lowering.
9855 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9856 SDValue V1, SDValue V2,
9858 SelectionDAG &DAG) {
9859 // FIXME: This should probably be generalized for 512-bit vectors as well.
9860 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9861 int LaneSize = Mask.size() / 2;
9863 // If there are only inputs from one 128-bit lane, splitting will in fact be
9864 // less expensive. The flags track whether the given lane contains an element
9865 // that crosses to another lane.
9866 bool LaneCrossing[2] = {false, false};
9867 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9868 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9869 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9870 if (!LaneCrossing[0] || !LaneCrossing[1])
9871 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9873 if (isSingleInputShuffleMask(Mask)) {
9874 SmallVector<int, 32> FlippedBlendMask;
9875 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9876 FlippedBlendMask.push_back(
9877 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9879 : Mask[i] % LaneSize +
9880 (i / LaneSize) * LaneSize + Size));
9882 // Flip the vector, and blend the results which should now be in-lane. The
9883 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9884 // 5 for the high source. The value 3 selects the high half of source 2 and
9885 // the value 2 selects the low half of source 2. We only use source 2 to
9886 // allow folding it into a memory operand.
9887 unsigned PERMMask = 3 | 2 << 4;
9888 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9889 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9890 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9893 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9894 // will be handled by the above logic and a blend of the results, much like
9895 // other patterns in AVX.
9896 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9899 /// \brief Handle lowering 2-lane 128-bit shuffles.
9900 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9901 SDValue V2, ArrayRef<int> Mask,
9902 const X86Subtarget *Subtarget,
9903 SelectionDAG &DAG) {
9904 // TODO: If minimizing size and one of the inputs is a zero vector and the
9905 // the zero vector has only one use, we could use a VPERM2X128 to save the
9906 // instruction bytes needed to explicitly generate the zero vector.
9908 // Blends are faster and handle all the non-lane-crossing cases.
9909 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9913 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9914 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9916 // If either input operand is a zero vector, use VPERM2X128 because its mask
9917 // allows us to replace the zero input with an implicit zero.
9918 if (!IsV1Zero && !IsV2Zero) {
9919 // Check for patterns which can be matched with a single insert of a 128-bit
9921 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9922 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9923 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9924 VT.getVectorNumElements() / 2);
9925 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9926 DAG.getIntPtrConstant(0, DL));
9927 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9928 OnlyUsesV1 ? V1 : V2,
9929 DAG.getIntPtrConstant(0, DL));
9930 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9934 // Otherwise form a 128-bit permutation. After accounting for undefs,
9935 // convert the 64-bit shuffle mask selection values into 128-bit
9936 // selection bits by dividing the indexes by 2 and shifting into positions
9937 // defined by a vperm2*128 instruction's immediate control byte.
9939 // The immediate permute control byte looks like this:
9940 // [1:0] - select 128 bits from sources for low half of destination
9942 // [3] - zero low half of destination
9943 // [5:4] - select 128 bits from sources for high half of destination
9945 // [7] - zero high half of destination
9947 int MaskLO = Mask[0];
9948 if (MaskLO == SM_SentinelUndef)
9949 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9951 int MaskHI = Mask[2];
9952 if (MaskHI == SM_SentinelUndef)
9953 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9955 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9957 // If either input is a zero vector, replace it with an undef input.
9958 // Shuffle mask values < 4 are selecting elements of V1.
9959 // Shuffle mask values >= 4 are selecting elements of V2.
9960 // Adjust each half of the permute mask by clearing the half that was
9961 // selecting the zero vector and setting the zero mask bit.
9963 V1 = DAG.getUNDEF(VT);
9965 PermMask = (PermMask & 0xf0) | 0x08;
9967 PermMask = (PermMask & 0x0f) | 0x80;
9970 V2 = DAG.getUNDEF(VT);
9972 PermMask = (PermMask & 0xf0) | 0x08;
9974 PermMask = (PermMask & 0x0f) | 0x80;
9977 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9978 DAG.getConstant(PermMask, DL, MVT::i8));
9981 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9982 /// shuffling each lane.
9984 /// This will only succeed when the result of fixing the 128-bit lanes results
9985 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9986 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9987 /// the lane crosses early and then use simpler shuffles within each lane.
9989 /// FIXME: It might be worthwhile at some point to support this without
9990 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9991 /// in x86 only floating point has interesting non-repeating shuffles, and even
9992 /// those are still *marginally* more expensive.
9993 static SDValue lowerVectorShuffleByMerging128BitLanes(
9994 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9995 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9996 assert(!isSingleInputShuffleMask(Mask) &&
9997 "This is only useful with multiple inputs.");
9999 int Size = Mask.size();
10000 int LaneSize = 128 / VT.getScalarSizeInBits();
10001 int NumLanes = Size / LaneSize;
10002 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10004 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10005 // check whether the in-128-bit lane shuffles share a repeating pattern.
10006 SmallVector<int, 4> Lanes;
10007 Lanes.resize(NumLanes, -1);
10008 SmallVector<int, 4> InLaneMask;
10009 InLaneMask.resize(LaneSize, -1);
10010 for (int i = 0; i < Size; ++i) {
10014 int j = i / LaneSize;
10016 if (Lanes[j] < 0) {
10017 // First entry we've seen for this lane.
10018 Lanes[j] = Mask[i] / LaneSize;
10019 } else if (Lanes[j] != Mask[i] / LaneSize) {
10020 // This doesn't match the lane selected previously!
10024 // Check that within each lane we have a consistent shuffle mask.
10025 int k = i % LaneSize;
10026 if (InLaneMask[k] < 0) {
10027 InLaneMask[k] = Mask[i] % LaneSize;
10028 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10029 // This doesn't fit a repeating in-lane mask.
10034 // First shuffle the lanes into place.
10035 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10036 VT.getSizeInBits() / 64);
10037 SmallVector<int, 8> LaneMask;
10038 LaneMask.resize(NumLanes * 2, -1);
10039 for (int i = 0; i < NumLanes; ++i)
10040 if (Lanes[i] >= 0) {
10041 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10042 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10045 V1 = DAG.getBitcast(LaneVT, V1);
10046 V2 = DAG.getBitcast(LaneVT, V2);
10047 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10049 // Cast it back to the type we actually want.
10050 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10052 // Now do a simple shuffle that isn't lane crossing.
10053 SmallVector<int, 8> NewMask;
10054 NewMask.resize(Size, -1);
10055 for (int i = 0; i < Size; ++i)
10057 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10058 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10059 "Must not introduce lane crosses at this point!");
10061 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10064 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10067 /// This returns true if the elements from a particular input are already in the
10068 /// slot required by the given mask and require no permutation.
10069 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10070 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10071 int Size = Mask.size();
10072 for (int i = 0; i < Size; ++i)
10073 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10079 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10080 ArrayRef<int> Mask, SDValue V1,
10081 SDValue V2, SelectionDAG &DAG) {
10083 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10084 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10085 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10086 int NumElts = VT.getVectorNumElements();
10087 bool ShufpdMask = true;
10088 bool CommutableMask = true;
10089 unsigned Immediate = 0;
10090 for (int i = 0; i < NumElts; ++i) {
10093 int Val = (i & 6) + NumElts * (i & 1);
10094 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10095 if (Mask[i] < Val || Mask[i] > Val + 1)
10096 ShufpdMask = false;
10097 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10098 CommutableMask = false;
10099 Immediate |= (Mask[i] % 2) << i;
10102 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10103 DAG.getConstant(Immediate, DL, MVT::i8));
10104 if (CommutableMask)
10105 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10106 DAG.getConstant(Immediate, DL, MVT::i8));
10110 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10112 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10113 /// isn't available.
10114 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10115 const X86Subtarget *Subtarget,
10116 SelectionDAG &DAG) {
10118 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10119 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10120 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10121 ArrayRef<int> Mask = SVOp->getMask();
10122 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10124 SmallVector<int, 4> WidenedMask;
10125 if (canWidenShuffleElements(Mask, WidenedMask))
10126 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10129 if (isSingleInputShuffleMask(Mask)) {
10130 // Check for being able to broadcast a single element.
10131 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10132 Mask, Subtarget, DAG))
10135 // Use low duplicate instructions for masks that match their pattern.
10136 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10137 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10139 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10140 // Non-half-crossing single input shuffles can be lowerid with an
10141 // interleaved permutation.
10142 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10143 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10144 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10145 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10148 // With AVX2 we have direct support for this permutation.
10149 if (Subtarget->hasAVX2())
10150 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10151 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10153 // Otherwise, fall back.
10154 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10158 // X86 has dedicated unpack instructions that can handle specific blend
10159 // operations: UNPCKH and UNPCKL.
10160 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10161 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10162 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10163 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10164 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10165 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
10166 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10167 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
10169 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10173 // Check if the blend happens to exactly fit that of SHUFPD.
10175 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10178 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10179 // shuffle. However, if we have AVX2 and either inputs are already in place,
10180 // we will be able to shuffle even across lanes the other input in a single
10181 // instruction so skip this pattern.
10182 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10183 isShuffleMaskInputInPlace(1, Mask))))
10184 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10185 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10188 // If we have AVX2 then we always want to lower with a blend because an v4 we
10189 // can fully permute the elements.
10190 if (Subtarget->hasAVX2())
10191 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10194 // Otherwise fall back on generic lowering.
10195 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10198 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10200 /// This routine is only called when we have AVX2 and thus a reasonable
10201 /// instruction set for v4i64 shuffling..
10202 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10203 const X86Subtarget *Subtarget,
10204 SelectionDAG &DAG) {
10206 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10207 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10208 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10209 ArrayRef<int> Mask = SVOp->getMask();
10210 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10211 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10213 SmallVector<int, 4> WidenedMask;
10214 if (canWidenShuffleElements(Mask, WidenedMask))
10215 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10218 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10222 // Check for being able to broadcast a single element.
10223 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10224 Mask, Subtarget, DAG))
10227 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10228 // use lower latency instructions that will operate on both 128-bit lanes.
10229 SmallVector<int, 2> RepeatedMask;
10230 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10231 if (isSingleInputShuffleMask(Mask)) {
10232 int PSHUFDMask[] = {-1, -1, -1, -1};
10233 for (int i = 0; i < 2; ++i)
10234 if (RepeatedMask[i] >= 0) {
10235 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10236 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10238 return DAG.getBitcast(
10240 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10241 DAG.getBitcast(MVT::v8i32, V1),
10242 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10246 // AVX2 provides a direct instruction for permuting a single input across
10248 if (isSingleInputShuffleMask(Mask))
10249 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10250 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10252 // Try to use shift instructions.
10253 if (SDValue Shift =
10254 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10257 // Use dedicated unpack instructions for masks that match their pattern.
10258 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10259 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10260 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10261 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10262 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10263 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
10264 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10265 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
10267 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10268 // shuffle. However, if we have AVX2 and either inputs are already in place,
10269 // we will be able to shuffle even across lanes the other input in a single
10270 // instruction so skip this pattern.
10271 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10272 isShuffleMaskInputInPlace(1, Mask))))
10273 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10274 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10277 // Otherwise fall back on generic blend lowering.
10278 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10282 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10284 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10285 /// isn't available.
10286 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10287 const X86Subtarget *Subtarget,
10288 SelectionDAG &DAG) {
10290 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10291 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10292 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10293 ArrayRef<int> Mask = SVOp->getMask();
10294 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10296 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10300 // Check for being able to broadcast a single element.
10301 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10302 Mask, Subtarget, DAG))
10305 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10306 // options to efficiently lower the shuffle.
10307 SmallVector<int, 4> RepeatedMask;
10308 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10309 assert(RepeatedMask.size() == 4 &&
10310 "Repeated masks must be half the mask width!");
10312 // Use even/odd duplicate instructions for masks that match their pattern.
10313 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10314 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10315 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10316 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10318 if (isSingleInputShuffleMask(Mask))
10319 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10320 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10322 // Use dedicated unpack instructions for masks that match their pattern.
10323 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10324 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10325 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10326 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10327 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10328 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10329 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10330 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10332 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10333 // have already handled any direct blends. We also need to squash the
10334 // repeated mask into a simulated v4f32 mask.
10335 for (int i = 0; i < 4; ++i)
10336 if (RepeatedMask[i] >= 8)
10337 RepeatedMask[i] -= 4;
10338 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10341 // If we have a single input shuffle with different shuffle patterns in the
10342 // two 128-bit lanes use the variable mask to VPERMILPS.
10343 if (isSingleInputShuffleMask(Mask)) {
10344 SDValue VPermMask[8];
10345 for (int i = 0; i < 8; ++i)
10346 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10347 : DAG.getConstant(Mask[i], DL, MVT::i32);
10348 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10349 return DAG.getNode(
10350 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10351 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10353 if (Subtarget->hasAVX2())
10354 return DAG.getNode(
10355 X86ISD::VPERMV, DL, MVT::v8f32,
10356 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10357 MVT::v8i32, VPermMask)),
10360 // Otherwise, fall back.
10361 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10365 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10367 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10368 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10371 // If we have AVX2 then we always want to lower with a blend because at v8 we
10372 // can fully permute the elements.
10373 if (Subtarget->hasAVX2())
10374 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10377 // Otherwise fall back on generic lowering.
10378 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10381 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10383 /// This routine is only called when we have AVX2 and thus a reasonable
10384 /// instruction set for v8i32 shuffling..
10385 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10386 const X86Subtarget *Subtarget,
10387 SelectionDAG &DAG) {
10389 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10390 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10391 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10392 ArrayRef<int> Mask = SVOp->getMask();
10393 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10394 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10396 // Whenever we can lower this as a zext, that instruction is strictly faster
10397 // than any alternative. It also allows us to fold memory operands into the
10398 // shuffle in many cases.
10399 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10400 Mask, Subtarget, DAG))
10403 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10407 // Check for being able to broadcast a single element.
10408 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10409 Mask, Subtarget, DAG))
10412 // If the shuffle mask is repeated in each 128-bit lane we can use more
10413 // efficient instructions that mirror the shuffles across the two 128-bit
10415 SmallVector<int, 4> RepeatedMask;
10416 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10417 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10418 if (isSingleInputShuffleMask(Mask))
10419 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10420 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10422 // Use dedicated unpack instructions for masks that match their pattern.
10423 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10424 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10425 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10426 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10427 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10428 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10429 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10430 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10433 // Try to use shift instructions.
10434 if (SDValue Shift =
10435 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10438 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10439 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10442 // If the shuffle patterns aren't repeated but it is a single input, directly
10443 // generate a cross-lane VPERMD instruction.
10444 if (isSingleInputShuffleMask(Mask)) {
10445 SDValue VPermMask[8];
10446 for (int i = 0; i < 8; ++i)
10447 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10448 : DAG.getConstant(Mask[i], DL, MVT::i32);
10449 return DAG.getNode(
10450 X86ISD::VPERMV, DL, MVT::v8i32,
10451 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10454 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10456 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10457 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10460 // Otherwise fall back on generic blend lowering.
10461 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10465 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10467 /// This routine is only called when we have AVX2 and thus a reasonable
10468 /// instruction set for v16i16 shuffling..
10469 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10470 const X86Subtarget *Subtarget,
10471 SelectionDAG &DAG) {
10473 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10474 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10475 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10476 ArrayRef<int> Mask = SVOp->getMask();
10477 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10478 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10480 // Whenever we can lower this as a zext, that instruction is strictly faster
10481 // than any alternative. It also allows us to fold memory operands into the
10482 // shuffle in many cases.
10483 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10484 Mask, Subtarget, DAG))
10487 // Check for being able to broadcast a single element.
10488 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10489 Mask, Subtarget, DAG))
10492 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10496 // Use dedicated unpack instructions for masks that match their pattern.
10497 if (isShuffleEquivalent(V1, V2, Mask,
10498 {// First 128-bit lane:
10499 0, 16, 1, 17, 2, 18, 3, 19,
10500 // Second 128-bit lane:
10501 8, 24, 9, 25, 10, 26, 11, 27}))
10502 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10503 if (isShuffleEquivalent(V1, V2, Mask,
10504 {// First 128-bit lane:
10505 4, 20, 5, 21, 6, 22, 7, 23,
10506 // Second 128-bit lane:
10507 12, 28, 13, 29, 14, 30, 15, 31}))
10508 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10510 // Try to use shift instructions.
10511 if (SDValue Shift =
10512 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10515 // Try to use byte rotation instructions.
10516 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10517 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10520 if (isSingleInputShuffleMask(Mask)) {
10521 // There are no generalized cross-lane shuffle operations available on i16
10523 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10524 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10527 SmallVector<int, 8> RepeatedMask;
10528 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10529 // As this is a single-input shuffle, the repeated mask should be
10530 // a strictly valid v8i16 mask that we can pass through to the v8i16
10531 // lowering to handle even the v16 case.
10532 return lowerV8I16GeneralSingleInputVectorShuffle(
10533 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10536 SDValue PSHUFBMask[32];
10537 for (int i = 0; i < 16; ++i) {
10538 if (Mask[i] == -1) {
10539 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10543 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10544 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10545 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10546 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10548 return DAG.getBitcast(MVT::v16i16,
10549 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10550 DAG.getBitcast(MVT::v32i8, V1),
10551 DAG.getNode(ISD::BUILD_VECTOR, DL,
10552 MVT::v32i8, PSHUFBMask)));
10555 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10557 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10558 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10561 // Otherwise fall back on generic lowering.
10562 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10565 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10567 /// This routine is only called when we have AVX2 and thus a reasonable
10568 /// instruction set for v32i8 shuffling..
10569 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10570 const X86Subtarget *Subtarget,
10571 SelectionDAG &DAG) {
10573 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10574 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10575 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10576 ArrayRef<int> Mask = SVOp->getMask();
10577 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10578 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10580 // Whenever we can lower this as a zext, that instruction is strictly faster
10581 // than any alternative. It also allows us to fold memory operands into the
10582 // shuffle in many cases.
10583 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10584 Mask, Subtarget, DAG))
10587 // Check for being able to broadcast a single element.
10588 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10589 Mask, Subtarget, DAG))
10592 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10596 // Use dedicated unpack instructions for masks that match their pattern.
10597 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10599 if (isShuffleEquivalent(
10601 {// First 128-bit lane:
10602 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10603 // Second 128-bit lane:
10604 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10605 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10606 if (isShuffleEquivalent(
10608 {// First 128-bit lane:
10609 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10610 // Second 128-bit lane:
10611 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10612 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10614 // Try to use shift instructions.
10615 if (SDValue Shift =
10616 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10619 // Try to use byte rotation instructions.
10620 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10621 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10624 if (isSingleInputShuffleMask(Mask)) {
10625 // There are no generalized cross-lane shuffle operations available on i8
10627 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10628 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10631 SDValue PSHUFBMask[32];
10632 for (int i = 0; i < 32; ++i)
10635 ? DAG.getUNDEF(MVT::i8)
10636 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10639 return DAG.getNode(
10640 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10641 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10644 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10646 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10647 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10650 // Otherwise fall back on generic lowering.
10651 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10654 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10656 /// This routine either breaks down the specific type of a 256-bit x86 vector
10657 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10658 /// together based on the available instructions.
10659 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10660 MVT VT, const X86Subtarget *Subtarget,
10661 SelectionDAG &DAG) {
10663 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10664 ArrayRef<int> Mask = SVOp->getMask();
10666 // If we have a single input to the zero element, insert that into V1 if we
10667 // can do so cheaply.
10668 int NumElts = VT.getVectorNumElements();
10669 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10670 return M >= NumElts;
10673 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10674 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10675 DL, VT, V1, V2, Mask, Subtarget, DAG))
10678 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10679 // can check for those subtargets here and avoid much of the subtarget
10680 // querying in the per-vector-type lowering routines. With AVX1 we have
10681 // essentially *zero* ability to manipulate a 256-bit vector with integer
10682 // types. Since we'll use floating point types there eventually, just
10683 // immediately cast everything to a float and operate entirely in that domain.
10684 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10685 int ElementBits = VT.getScalarSizeInBits();
10686 if (ElementBits < 32)
10687 // No floating point type available, decompose into 128-bit vectors.
10688 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10690 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10691 VT.getVectorNumElements());
10692 V1 = DAG.getBitcast(FpVT, V1);
10693 V2 = DAG.getBitcast(FpVT, V2);
10694 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10697 switch (VT.SimpleTy) {
10699 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10701 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10703 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10705 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10707 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10709 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10712 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10716 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10717 ArrayRef<int> Mask, SDValue V1,
10718 SDValue V2, SelectionDAG &DAG) {
10720 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10722 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10723 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10725 SmallVector<SDValue, 32> VPermMask;
10726 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i)
10727 VPermMask.push_back(Mask[i] < 0 ? DAG.getUNDEF(MaskEltVT) :
10728 DAG.getConstant(Mask[i], DL, MaskEltVT));
10729 SDValue MaskNode = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecVT,
10731 if (isSingleInputShuffleMask(Mask))
10732 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10734 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10737 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10738 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10739 const X86Subtarget *Subtarget,
10740 SelectionDAG &DAG) {
10742 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10743 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10744 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10745 ArrayRef<int> Mask = SVOp->getMask();
10746 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10748 if (SDValue Unpck =
10749 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10752 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10755 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10756 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10757 const X86Subtarget *Subtarget,
10758 SelectionDAG &DAG) {
10760 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10761 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10762 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10763 ArrayRef<int> Mask = SVOp->getMask();
10764 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10766 if (SDValue Unpck =
10767 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10770 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10773 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10774 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10775 const X86Subtarget *Subtarget,
10776 SelectionDAG &DAG) {
10778 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10779 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10780 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10781 ArrayRef<int> Mask = SVOp->getMask();
10782 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10784 if (SDValue Unpck =
10785 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10788 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10791 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10792 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10793 const X86Subtarget *Subtarget,
10794 SelectionDAG &DAG) {
10796 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10797 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10798 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10799 ArrayRef<int> Mask = SVOp->getMask();
10800 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10802 if (SDValue Unpck =
10803 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10806 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10809 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10810 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10811 const X86Subtarget *Subtarget,
10812 SelectionDAG &DAG) {
10814 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10815 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10816 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10817 ArrayRef<int> Mask = SVOp->getMask();
10818 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10819 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10821 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10824 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10825 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10826 const X86Subtarget *Subtarget,
10827 SelectionDAG &DAG) {
10829 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10830 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10831 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10832 ArrayRef<int> Mask = SVOp->getMask();
10833 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10834 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10836 // FIXME: Implement direct support for this type!
10837 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10840 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10842 /// This routine either breaks down the specific type of a 512-bit x86 vector
10843 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10844 /// together based on the available instructions.
10845 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10846 MVT VT, const X86Subtarget *Subtarget,
10847 SelectionDAG &DAG) {
10849 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10850 ArrayRef<int> Mask = SVOp->getMask();
10851 assert(Subtarget->hasAVX512() &&
10852 "Cannot lower 512-bit vectors w/ basic ISA!");
10854 // Check for being able to broadcast a single element.
10855 if (SDValue Broadcast =
10856 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10859 // Dispatch to each element type for lowering. If we don't have supprot for
10860 // specific element type shuffles at 512 bits, immediately split them and
10861 // lower them. Each lowering routine of a given type is allowed to assume that
10862 // the requisite ISA extensions for that element type are available.
10863 switch (VT.SimpleTy) {
10865 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10867 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10869 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10871 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10873 if (Subtarget->hasBWI())
10874 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10877 if (Subtarget->hasBWI())
10878 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10882 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10885 // Otherwise fall back on splitting.
10886 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10889 // Lower vXi1 vector shuffles.
10890 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10891 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10892 // vector, shuffle and then truncate it back.
10893 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10894 MVT VT, const X86Subtarget *Subtarget,
10895 SelectionDAG &DAG) {
10897 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10898 ArrayRef<int> Mask = SVOp->getMask();
10899 assert(Subtarget->hasAVX512() &&
10900 "Cannot lower 512-bit vectors w/o basic ISA!");
10902 switch (VT.SimpleTy) {
10904 assert(false && "Expected a vector of i1 elements");
10907 ExtVT = MVT::v2i64;
10910 ExtVT = MVT::v4i32;
10913 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
10916 ExtVT = MVT::v16i32;
10919 ExtVT = MVT::v32i16;
10922 ExtVT = MVT::v64i8;
10926 if (ISD::isBuildVectorAllZeros(V1.getNode()))
10927 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10928 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
10929 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10931 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
10934 V2 = DAG.getUNDEF(ExtVT);
10935 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
10936 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
10937 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
10938 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
10940 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
10941 return DAG.getNode(ISD::TRUNCATE, DL, VT,
10942 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
10944 /// \brief Top-level lowering for x86 vector shuffles.
10946 /// This handles decomposition, canonicalization, and lowering of all x86
10947 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10948 /// above in helper routines. The canonicalization attempts to widen shuffles
10949 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10950 /// s.t. only one of the two inputs needs to be tested, etc.
10951 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10952 SelectionDAG &DAG) {
10953 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10954 ArrayRef<int> Mask = SVOp->getMask();
10955 SDValue V1 = Op.getOperand(0);
10956 SDValue V2 = Op.getOperand(1);
10957 MVT VT = Op.getSimpleValueType();
10958 int NumElements = VT.getVectorNumElements();
10960 bool Is1BitVector = (VT.getScalarType() == MVT::i1);
10962 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
10963 "Can't lower MMX shuffles");
10965 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10966 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10967 if (V1IsUndef && V2IsUndef)
10968 return DAG.getUNDEF(VT);
10970 // When we create a shuffle node we put the UNDEF node to second operand,
10971 // but in some cases the first operand may be transformed to UNDEF.
10972 // In this case we should just commute the node.
10974 return DAG.getCommutedVectorShuffle(*SVOp);
10976 // Check for non-undef masks pointing at an undef vector and make the masks
10977 // undef as well. This makes it easier to match the shuffle based solely on
10981 if (M >= NumElements) {
10982 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10983 for (int &M : NewMask)
10984 if (M >= NumElements)
10986 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10989 // We actually see shuffles that are entirely re-arrangements of a set of
10990 // zero inputs. This mostly happens while decomposing complex shuffles into
10991 // simple ones. Directly lower these as a buildvector of zeros.
10992 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10993 if (Zeroable.all())
10994 return getZeroVector(VT, Subtarget, DAG, dl);
10996 // Try to collapse shuffles into using a vector type with fewer elements but
10997 // wider element types. We cap this to not form integers or floating point
10998 // elements wider than 64 bits, but it might be interesting to form i128
10999 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11000 SmallVector<int, 16> WidenedMask;
11001 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11002 canWidenShuffleElements(Mask, WidenedMask)) {
11003 MVT NewEltVT = VT.isFloatingPoint()
11004 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11005 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11006 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11007 // Make sure that the new vector type is legal. For example, v2f64 isn't
11009 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11010 V1 = DAG.getBitcast(NewVT, V1);
11011 V2 = DAG.getBitcast(NewVT, V2);
11012 return DAG.getBitcast(
11013 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11017 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11018 for (int M : SVOp->getMask())
11020 ++NumUndefElements;
11021 else if (M < NumElements)
11026 // Commute the shuffle as needed such that more elements come from V1 than
11027 // V2. This allows us to match the shuffle pattern strictly on how many
11028 // elements come from V1 without handling the symmetric cases.
11029 if (NumV2Elements > NumV1Elements)
11030 return DAG.getCommutedVectorShuffle(*SVOp);
11032 // When the number of V1 and V2 elements are the same, try to minimize the
11033 // number of uses of V2 in the low half of the vector. When that is tied,
11034 // ensure that the sum of indices for V1 is equal to or lower than the sum
11035 // indices for V2. When those are equal, try to ensure that the number of odd
11036 // indices for V1 is lower than the number of odd indices for V2.
11037 if (NumV1Elements == NumV2Elements) {
11038 int LowV1Elements = 0, LowV2Elements = 0;
11039 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11040 if (M >= NumElements)
11044 if (LowV2Elements > LowV1Elements) {
11045 return DAG.getCommutedVectorShuffle(*SVOp);
11046 } else if (LowV2Elements == LowV1Elements) {
11047 int SumV1Indices = 0, SumV2Indices = 0;
11048 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11049 if (SVOp->getMask()[i] >= NumElements)
11051 else if (SVOp->getMask()[i] >= 0)
11053 if (SumV2Indices < SumV1Indices) {
11054 return DAG.getCommutedVectorShuffle(*SVOp);
11055 } else if (SumV2Indices == SumV1Indices) {
11056 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11057 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11058 if (SVOp->getMask()[i] >= NumElements)
11059 NumV2OddIndices += i % 2;
11060 else if (SVOp->getMask()[i] >= 0)
11061 NumV1OddIndices += i % 2;
11062 if (NumV2OddIndices < NumV1OddIndices)
11063 return DAG.getCommutedVectorShuffle(*SVOp);
11068 // For each vector width, delegate to a specialized lowering routine.
11069 if (VT.getSizeInBits() == 128)
11070 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11072 if (VT.getSizeInBits() == 256)
11073 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11075 if (VT.getSizeInBits() == 512)
11076 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11079 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11080 llvm_unreachable("Unimplemented!");
11083 // This function assumes its argument is a BUILD_VECTOR of constants or
11084 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11086 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11087 unsigned &MaskValue) {
11089 unsigned NumElems = BuildVector->getNumOperands();
11091 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11092 // We don't handle the >2 lanes case right now.
11093 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11097 unsigned NumElemsInLane = NumElems / NumLanes;
11099 // Blend for v16i16 should be symmetric for the both lanes.
11100 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11101 SDValue EltCond = BuildVector->getOperand(i);
11102 SDValue SndLaneEltCond =
11103 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11105 int Lane1Cond = -1, Lane2Cond = -1;
11106 if (isa<ConstantSDNode>(EltCond))
11107 Lane1Cond = !isZero(EltCond);
11108 if (isa<ConstantSDNode>(SndLaneEltCond))
11109 Lane2Cond = !isZero(SndLaneEltCond);
11111 unsigned LaneMask = 0;
11112 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11113 // Lane1Cond != 0, means we want the first argument.
11114 // Lane1Cond == 0, means we want the second argument.
11115 // The encoding of this argument is 0 for the first argument, 1
11116 // for the second. Therefore, invert the condition.
11117 LaneMask = !Lane1Cond << i;
11118 else if (Lane1Cond < 0)
11119 LaneMask = !Lane2Cond << i;
11123 MaskValue |= LaneMask;
11125 MaskValue |= LaneMask << NumElemsInLane;
11130 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11131 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11132 const X86Subtarget *Subtarget,
11133 SelectionDAG &DAG) {
11134 SDValue Cond = Op.getOperand(0);
11135 SDValue LHS = Op.getOperand(1);
11136 SDValue RHS = Op.getOperand(2);
11138 MVT VT = Op.getSimpleValueType();
11140 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11142 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11144 // Only non-legal VSELECTs reach this lowering, convert those into generic
11145 // shuffles and re-use the shuffle lowering path for blends.
11146 SmallVector<int, 32> Mask;
11147 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11148 SDValue CondElt = CondBV->getOperand(i);
11150 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11152 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11155 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11156 // A vselect where all conditions and data are constants can be optimized into
11157 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11158 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11159 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11160 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11163 // Try to lower this to a blend-style vector shuffle. This can handle all
11164 // constant condition cases.
11165 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11168 // Variable blends are only legal from SSE4.1 onward.
11169 if (!Subtarget->hasSSE41())
11172 // Only some types will be legal on some subtargets. If we can emit a legal
11173 // VSELECT-matching blend, return Op, and but if we need to expand, return
11175 switch (Op.getSimpleValueType().SimpleTy) {
11177 // Most of the vector types have blends past SSE4.1.
11181 // The byte blends for AVX vectors were introduced only in AVX2.
11182 if (Subtarget->hasAVX2())
11189 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11190 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11193 // FIXME: We should custom lower this by fixing the condition and using i8
11199 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11200 MVT VT = Op.getSimpleValueType();
11203 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11206 if (VT.getSizeInBits() == 8) {
11207 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11208 Op.getOperand(0), Op.getOperand(1));
11209 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11210 DAG.getValueType(VT));
11211 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11214 if (VT.getSizeInBits() == 16) {
11215 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11216 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11218 return DAG.getNode(
11219 ISD::TRUNCATE, dl, MVT::i16,
11220 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11221 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11222 Op.getOperand(1)));
11223 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11224 Op.getOperand(0), Op.getOperand(1));
11225 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11226 DAG.getValueType(VT));
11227 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11230 if (VT == MVT::f32) {
11231 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11232 // the result back to FR32 register. It's only worth matching if the
11233 // result has a single use which is a store or a bitcast to i32. And in
11234 // the case of a store, it's not worth it if the index is a constant 0,
11235 // because a MOVSSmr can be used instead, which is smaller and faster.
11236 if (!Op.hasOneUse())
11238 SDNode *User = *Op.getNode()->use_begin();
11239 if ((User->getOpcode() != ISD::STORE ||
11240 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11241 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11242 (User->getOpcode() != ISD::BITCAST ||
11243 User->getValueType(0) != MVT::i32))
11245 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11246 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11248 return DAG.getBitcast(MVT::f32, Extract);
11251 if (VT == MVT::i32 || VT == MVT::i64) {
11252 // ExtractPS/pextrq works with constant index.
11253 if (isa<ConstantSDNode>(Op.getOperand(1)))
11259 /// Extract one bit from mask vector, like v16i1 or v8i1.
11260 /// AVX-512 feature.
11262 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11263 SDValue Vec = Op.getOperand(0);
11265 MVT VecVT = Vec.getSimpleValueType();
11266 SDValue Idx = Op.getOperand(1);
11267 MVT EltVT = Op.getSimpleValueType();
11269 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11270 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11271 "Unexpected vector type in ExtractBitFromMaskVector");
11273 // variable index can't be handled in mask registers,
11274 // extend vector to VR512
11275 if (!isa<ConstantSDNode>(Idx)) {
11276 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11277 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11278 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11279 ExtVT.getVectorElementType(), Ext, Idx);
11280 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11283 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11284 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11285 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11286 rc = getRegClassFor(MVT::v16i1);
11287 unsigned MaxSift = rc->getSize()*8 - 1;
11288 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11289 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11290 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11291 DAG.getConstant(MaxSift, dl, MVT::i8));
11292 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11293 DAG.getIntPtrConstant(0, dl));
11297 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11298 SelectionDAG &DAG) const {
11300 SDValue Vec = Op.getOperand(0);
11301 MVT VecVT = Vec.getSimpleValueType();
11302 SDValue Idx = Op.getOperand(1);
11304 if (Op.getSimpleValueType() == MVT::i1)
11305 return ExtractBitFromMaskVector(Op, DAG);
11307 if (!isa<ConstantSDNode>(Idx)) {
11308 if (VecVT.is512BitVector() ||
11309 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11310 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11313 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11314 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11315 MaskEltVT.getSizeInBits());
11317 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11318 auto PtrVT = getPointerTy(DAG.getDataLayout());
11319 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11320 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11321 DAG.getConstant(0, dl, PtrVT));
11322 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11323 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11324 DAG.getConstant(0, dl, PtrVT));
11329 // If this is a 256-bit vector result, first extract the 128-bit vector and
11330 // then extract the element from the 128-bit vector.
11331 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11333 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11334 // Get the 128-bit vector.
11335 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11336 MVT EltVT = VecVT.getVectorElementType();
11338 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11340 //if (IdxVal >= NumElems/2)
11341 // IdxVal -= NumElems/2;
11342 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11343 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11344 DAG.getConstant(IdxVal, dl, MVT::i32));
11347 assert(VecVT.is128BitVector() && "Unexpected vector length");
11349 if (Subtarget->hasSSE41())
11350 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11353 MVT VT = Op.getSimpleValueType();
11354 // TODO: handle v16i8.
11355 if (VT.getSizeInBits() == 16) {
11356 SDValue Vec = Op.getOperand(0);
11357 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11359 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11360 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11361 DAG.getBitcast(MVT::v4i32, Vec),
11362 Op.getOperand(1)));
11363 // Transform it so it match pextrw which produces a 32-bit result.
11364 MVT EltVT = MVT::i32;
11365 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11366 Op.getOperand(0), Op.getOperand(1));
11367 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11368 DAG.getValueType(VT));
11369 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11372 if (VT.getSizeInBits() == 32) {
11373 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11377 // SHUFPS the element to the lowest double word, then movss.
11378 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11379 MVT VVT = Op.getOperand(0).getSimpleValueType();
11380 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11381 DAG.getUNDEF(VVT), Mask);
11382 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11383 DAG.getIntPtrConstant(0, dl));
11386 if (VT.getSizeInBits() == 64) {
11387 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11388 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11389 // to match extract_elt for f64.
11390 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11394 // UNPCKHPD the element to the lowest double word, then movsd.
11395 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11396 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11397 int Mask[2] = { 1, -1 };
11398 MVT VVT = Op.getOperand(0).getSimpleValueType();
11399 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11400 DAG.getUNDEF(VVT), Mask);
11401 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11402 DAG.getIntPtrConstant(0, dl));
11408 /// Insert one bit to mask vector, like v16i1 or v8i1.
11409 /// AVX-512 feature.
11411 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11413 SDValue Vec = Op.getOperand(0);
11414 SDValue Elt = Op.getOperand(1);
11415 SDValue Idx = Op.getOperand(2);
11416 MVT VecVT = Vec.getSimpleValueType();
11418 if (!isa<ConstantSDNode>(Idx)) {
11419 // Non constant index. Extend source and destination,
11420 // insert element and then truncate the result.
11421 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11422 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11423 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11424 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11425 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11426 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11429 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11430 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11432 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11433 DAG.getConstant(IdxVal, dl, MVT::i8));
11434 if (Vec.getOpcode() == ISD::UNDEF)
11436 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11439 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11440 SelectionDAG &DAG) const {
11441 MVT VT = Op.getSimpleValueType();
11442 MVT EltVT = VT.getVectorElementType();
11444 if (EltVT == MVT::i1)
11445 return InsertBitToMaskVector(Op, DAG);
11448 SDValue N0 = Op.getOperand(0);
11449 SDValue N1 = Op.getOperand(1);
11450 SDValue N2 = Op.getOperand(2);
11451 if (!isa<ConstantSDNode>(N2))
11453 auto *N2C = cast<ConstantSDNode>(N2);
11454 unsigned IdxVal = N2C->getZExtValue();
11456 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11457 // into that, and then insert the subvector back into the result.
11458 if (VT.is256BitVector() || VT.is512BitVector()) {
11459 // With a 256-bit vector, we can insert into the zero element efficiently
11460 // using a blend if we have AVX or AVX2 and the right data type.
11461 if (VT.is256BitVector() && IdxVal == 0) {
11462 // TODO: It is worthwhile to cast integer to floating point and back
11463 // and incur a domain crossing penalty if that's what we'll end up
11464 // doing anyway after extracting to a 128-bit vector.
11465 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11466 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11467 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11468 N2 = DAG.getIntPtrConstant(1, dl);
11469 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11473 // Get the desired 128-bit vector chunk.
11474 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11476 // Insert the element into the desired chunk.
11477 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11478 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11480 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11481 DAG.getConstant(IdxIn128, dl, MVT::i32));
11483 // Insert the changed part back into the bigger vector
11484 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11486 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11488 if (Subtarget->hasSSE41()) {
11489 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11491 if (VT == MVT::v8i16) {
11492 Opc = X86ISD::PINSRW;
11494 assert(VT == MVT::v16i8);
11495 Opc = X86ISD::PINSRB;
11498 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11500 if (N1.getValueType() != MVT::i32)
11501 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11502 if (N2.getValueType() != MVT::i32)
11503 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11504 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11507 if (EltVT == MVT::f32) {
11508 // Bits [7:6] of the constant are the source select. This will always be
11509 // zero here. The DAG Combiner may combine an extract_elt index into
11510 // these bits. For example (insert (extract, 3), 2) could be matched by
11511 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11512 // Bits [5:4] of the constant are the destination select. This is the
11513 // value of the incoming immediate.
11514 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11515 // combine either bitwise AND or insert of float 0.0 to set these bits.
11517 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11518 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11519 // If this is an insertion of 32-bits into the low 32-bits of
11520 // a vector, we prefer to generate a blend with immediate rather
11521 // than an insertps. Blends are simpler operations in hardware and so
11522 // will always have equal or better performance than insertps.
11523 // But if optimizing for size and there's a load folding opportunity,
11524 // generate insertps because blendps does not have a 32-bit memory
11526 N2 = DAG.getIntPtrConstant(1, dl);
11527 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11528 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11530 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11531 // Create this as a scalar to vector..
11532 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11533 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11536 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11537 // PINSR* works with constant index.
11542 if (EltVT == MVT::i8)
11545 if (EltVT.getSizeInBits() == 16) {
11546 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11547 // as its second argument.
11548 if (N1.getValueType() != MVT::i32)
11549 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11550 if (N2.getValueType() != MVT::i32)
11551 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11552 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11557 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11559 MVT OpVT = Op.getSimpleValueType();
11561 // If this is a 256-bit vector result, first insert into a 128-bit
11562 // vector and then insert into the 256-bit vector.
11563 if (!OpVT.is128BitVector()) {
11564 // Insert into a 128-bit vector.
11565 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11566 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11567 OpVT.getVectorNumElements() / SizeFactor);
11569 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11571 // Insert the 128-bit vector.
11572 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11575 if (OpVT == MVT::v1i64 &&
11576 Op.getOperand(0).getValueType() == MVT::i64)
11577 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11579 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11580 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11581 return DAG.getBitcast(
11582 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11585 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11586 // a simple subregister reference or explicit instructions to grab
11587 // upper bits of a vector.
11588 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11589 SelectionDAG &DAG) {
11591 SDValue In = Op.getOperand(0);
11592 SDValue Idx = Op.getOperand(1);
11593 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11594 MVT ResVT = Op.getSimpleValueType();
11595 MVT InVT = In.getSimpleValueType();
11597 if (Subtarget->hasFp256()) {
11598 if (ResVT.is128BitVector() &&
11599 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11600 isa<ConstantSDNode>(Idx)) {
11601 return Extract128BitVector(In, IdxVal, DAG, dl);
11603 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11604 isa<ConstantSDNode>(Idx)) {
11605 return Extract256BitVector(In, IdxVal, DAG, dl);
11611 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11612 // simple superregister reference or explicit instructions to insert
11613 // the upper bits of a vector.
11614 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11615 SelectionDAG &DAG) {
11616 if (!Subtarget->hasAVX())
11620 SDValue Vec = Op.getOperand(0);
11621 SDValue SubVec = Op.getOperand(1);
11622 SDValue Idx = Op.getOperand(2);
11624 if (!isa<ConstantSDNode>(Idx))
11627 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11628 MVT OpVT = Op.getSimpleValueType();
11629 MVT SubVecVT = SubVec.getSimpleValueType();
11631 // Fold two 16-byte subvector loads into one 32-byte load:
11632 // (insert_subvector (insert_subvector undef, (load addr), 0),
11633 // (load addr + 16), Elts/2)
11635 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11636 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11637 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11638 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11639 if (Idx2 && Idx2->getZExtValue() == 0) {
11640 SDValue SubVec2 = Vec.getOperand(1);
11641 // If needed, look through a bitcast to get to the load.
11642 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11643 SubVec2 = SubVec2.getOperand(0);
11645 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11647 unsigned Alignment = FirstLd->getAlignment();
11648 unsigned AS = FirstLd->getAddressSpace();
11649 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11650 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11651 OpVT, AS, Alignment, &Fast) && Fast) {
11652 SDValue Ops[] = { SubVec2, SubVec };
11653 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11660 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11661 SubVecVT.is128BitVector())
11662 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11664 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11665 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11667 if (OpVT.getVectorElementType() == MVT::i1) {
11668 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11670 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11671 SDValue Undef = DAG.getUNDEF(OpVT);
11672 unsigned NumElems = OpVT.getVectorNumElements();
11673 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11675 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11676 // Zero upper bits of the Vec
11677 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11678 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11680 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11682 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11683 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11686 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11688 // Zero upper bits of the Vec2
11689 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11690 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11691 // Zero lower bits of the Vec
11692 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11693 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11694 // Merge them together
11695 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11701 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11702 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11703 // one of the above mentioned nodes. It has to be wrapped because otherwise
11704 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11705 // be used to form addressing mode. These wrapped nodes will be selected
11708 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11709 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11711 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11712 // global base reg.
11713 unsigned char OpFlag = 0;
11714 unsigned WrapperKind = X86ISD::Wrapper;
11715 CodeModel::Model M = DAG.getTarget().getCodeModel();
11717 if (Subtarget->isPICStyleRIPRel() &&
11718 (M == CodeModel::Small || M == CodeModel::Kernel))
11719 WrapperKind = X86ISD::WrapperRIP;
11720 else if (Subtarget->isPICStyleGOT())
11721 OpFlag = X86II::MO_GOTOFF;
11722 else if (Subtarget->isPICStyleStubPIC())
11723 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11725 auto PtrVT = getPointerTy(DAG.getDataLayout());
11726 SDValue Result = DAG.getTargetConstantPool(
11727 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11729 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11730 // With PIC, the address is actually $g + Offset.
11733 DAG.getNode(ISD::ADD, DL, PtrVT,
11734 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11740 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11741 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11743 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11744 // global base reg.
11745 unsigned char OpFlag = 0;
11746 unsigned WrapperKind = X86ISD::Wrapper;
11747 CodeModel::Model M = DAG.getTarget().getCodeModel();
11749 if (Subtarget->isPICStyleRIPRel() &&
11750 (M == CodeModel::Small || M == CodeModel::Kernel))
11751 WrapperKind = X86ISD::WrapperRIP;
11752 else if (Subtarget->isPICStyleGOT())
11753 OpFlag = X86II::MO_GOTOFF;
11754 else if (Subtarget->isPICStyleStubPIC())
11755 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11757 auto PtrVT = getPointerTy(DAG.getDataLayout());
11758 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11760 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11762 // With PIC, the address is actually $g + Offset.
11765 DAG.getNode(ISD::ADD, DL, PtrVT,
11766 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11772 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11773 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11775 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11776 // global base reg.
11777 unsigned char OpFlag = 0;
11778 unsigned WrapperKind = X86ISD::Wrapper;
11779 CodeModel::Model M = DAG.getTarget().getCodeModel();
11781 if (Subtarget->isPICStyleRIPRel() &&
11782 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11783 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11784 OpFlag = X86II::MO_GOTPCREL;
11785 WrapperKind = X86ISD::WrapperRIP;
11786 } else if (Subtarget->isPICStyleGOT()) {
11787 OpFlag = X86II::MO_GOT;
11788 } else if (Subtarget->isPICStyleStubPIC()) {
11789 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11790 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11791 OpFlag = X86II::MO_DARWIN_NONLAZY;
11794 auto PtrVT = getPointerTy(DAG.getDataLayout());
11795 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11798 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11800 // With PIC, the address is actually $g + Offset.
11801 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11802 !Subtarget->is64Bit()) {
11804 DAG.getNode(ISD::ADD, DL, PtrVT,
11805 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11808 // For symbols that require a load from a stub to get the address, emit the
11810 if (isGlobalStubReference(OpFlag))
11811 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11812 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11813 false, false, false, 0);
11819 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11820 // Create the TargetBlockAddressAddress node.
11821 unsigned char OpFlags =
11822 Subtarget->ClassifyBlockAddressReference();
11823 CodeModel::Model M = DAG.getTarget().getCodeModel();
11824 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11825 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11827 auto PtrVT = getPointerTy(DAG.getDataLayout());
11828 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11830 if (Subtarget->isPICStyleRIPRel() &&
11831 (M == CodeModel::Small || M == CodeModel::Kernel))
11832 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11834 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11836 // With PIC, the address is actually $g + Offset.
11837 if (isGlobalRelativeToPICBase(OpFlags)) {
11838 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11839 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11846 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11847 int64_t Offset, SelectionDAG &DAG) const {
11848 // Create the TargetGlobalAddress node, folding in the constant
11849 // offset if it is legal.
11850 unsigned char OpFlags =
11851 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11852 CodeModel::Model M = DAG.getTarget().getCodeModel();
11853 auto PtrVT = getPointerTy(DAG.getDataLayout());
11855 if (OpFlags == X86II::MO_NO_FLAG &&
11856 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11857 // A direct static reference to a global.
11858 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11861 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11864 if (Subtarget->isPICStyleRIPRel() &&
11865 (M == CodeModel::Small || M == CodeModel::Kernel))
11866 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11868 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11870 // With PIC, the address is actually $g + Offset.
11871 if (isGlobalRelativeToPICBase(OpFlags)) {
11872 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11873 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11876 // For globals that require a load from a stub to get the address, emit the
11878 if (isGlobalStubReference(OpFlags))
11879 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11880 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11881 false, false, false, 0);
11883 // If there was a non-zero offset that we didn't fold, create an explicit
11884 // addition for it.
11886 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11887 DAG.getConstant(Offset, dl, PtrVT));
11893 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11894 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11895 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11896 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11900 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11901 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11902 unsigned char OperandFlags, bool LocalDynamic = false) {
11903 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11904 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11906 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11907 GA->getValueType(0),
11911 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11915 SDValue Ops[] = { Chain, TGA, *InFlag };
11916 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11918 SDValue Ops[] = { Chain, TGA };
11919 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11922 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11923 MFI->setAdjustsStack(true);
11924 MFI->setHasCalls(true);
11926 SDValue Flag = Chain.getValue(1);
11927 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11930 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11932 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11935 SDLoc dl(GA); // ? function entry point might be better
11936 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11937 DAG.getNode(X86ISD::GlobalBaseReg,
11938 SDLoc(), PtrVT), InFlag);
11939 InFlag = Chain.getValue(1);
11941 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11944 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11946 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11948 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11949 X86::RAX, X86II::MO_TLSGD);
11952 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11958 // Get the start address of the TLS block for this module.
11959 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11960 .getInfo<X86MachineFunctionInfo>();
11961 MFI->incNumLocalDynamicTLSAccesses();
11965 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11966 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11969 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11970 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11971 InFlag = Chain.getValue(1);
11972 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11973 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11976 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11980 unsigned char OperandFlags = X86II::MO_DTPOFF;
11981 unsigned WrapperKind = X86ISD::Wrapper;
11982 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11983 GA->getValueType(0),
11984 GA->getOffset(), OperandFlags);
11985 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11987 // Add x@dtpoff with the base.
11988 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11991 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11992 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11993 const EVT PtrVT, TLSModel::Model model,
11994 bool is64Bit, bool isPIC) {
11997 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11998 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11999 is64Bit ? 257 : 256));
12001 SDValue ThreadPointer =
12002 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12003 MachinePointerInfo(Ptr), false, false, false, 0);
12005 unsigned char OperandFlags = 0;
12006 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12008 unsigned WrapperKind = X86ISD::Wrapper;
12009 if (model == TLSModel::LocalExec) {
12010 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12011 } else if (model == TLSModel::InitialExec) {
12013 OperandFlags = X86II::MO_GOTTPOFF;
12014 WrapperKind = X86ISD::WrapperRIP;
12016 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12019 llvm_unreachable("Unexpected model");
12022 // emit "addl x@ntpoff,%eax" (local exec)
12023 // or "addl x@indntpoff,%eax" (initial exec)
12024 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12026 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12027 GA->getOffset(), OperandFlags);
12028 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12030 if (model == TLSModel::InitialExec) {
12031 if (isPIC && !is64Bit) {
12032 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12033 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12037 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12038 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12039 false, false, false, 0);
12042 // The address of the thread local variable is the add of the thread
12043 // pointer with the offset of the variable.
12044 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12048 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12050 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12051 const GlobalValue *GV = GA->getGlobal();
12052 auto PtrVT = getPointerTy(DAG.getDataLayout());
12054 if (Subtarget->isTargetELF()) {
12055 if (DAG.getTarget().Options.EmulatedTLS)
12056 return LowerToTLSEmulatedModel(GA, DAG);
12057 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12059 case TLSModel::GeneralDynamic:
12060 if (Subtarget->is64Bit())
12061 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12062 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12063 case TLSModel::LocalDynamic:
12064 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12065 Subtarget->is64Bit());
12066 case TLSModel::InitialExec:
12067 case TLSModel::LocalExec:
12068 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12069 DAG.getTarget().getRelocationModel() ==
12072 llvm_unreachable("Unknown TLS model.");
12075 if (Subtarget->isTargetDarwin()) {
12076 // Darwin only has one model of TLS. Lower to that.
12077 unsigned char OpFlag = 0;
12078 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12079 X86ISD::WrapperRIP : X86ISD::Wrapper;
12081 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12082 // global base reg.
12083 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12084 !Subtarget->is64Bit();
12086 OpFlag = X86II::MO_TLVP_PIC_BASE;
12088 OpFlag = X86II::MO_TLVP;
12090 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12091 GA->getValueType(0),
12092 GA->getOffset(), OpFlag);
12093 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12095 // With PIC32, the address is actually $g + Offset.
12097 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12098 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12101 // Lowering the machine isd will make sure everything is in the right
12103 SDValue Chain = DAG.getEntryNode();
12104 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12105 SDValue Args[] = { Chain, Offset };
12106 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12108 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12109 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12110 MFI->setAdjustsStack(true);
12112 // And our return value (tls address) is in the standard call return value
12114 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12115 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12118 if (Subtarget->isTargetKnownWindowsMSVC() ||
12119 Subtarget->isTargetWindowsGNU()) {
12120 // Just use the implicit TLS architecture
12121 // Need to generate someting similar to:
12122 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12124 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12125 // mov rcx, qword [rdx+rcx*8]
12126 // mov eax, .tls$:tlsvar
12127 // [rax+rcx] contains the address
12128 // Windows 64bit: gs:0x58
12129 // Windows 32bit: fs:__tls_array
12132 SDValue Chain = DAG.getEntryNode();
12134 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12135 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12136 // use its literal value of 0x2C.
12137 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12138 ? Type::getInt8PtrTy(*DAG.getContext(),
12140 : Type::getInt32PtrTy(*DAG.getContext(),
12143 SDValue TlsArray = Subtarget->is64Bit()
12144 ? DAG.getIntPtrConstant(0x58, dl)
12145 : (Subtarget->isTargetWindowsGNU()
12146 ? DAG.getIntPtrConstant(0x2C, dl)
12147 : DAG.getExternalSymbol("_tls_array", PtrVT));
12149 SDValue ThreadPointer =
12150 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12154 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12155 res = ThreadPointer;
12157 // Load the _tls_index variable
12158 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12159 if (Subtarget->is64Bit())
12160 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12161 MachinePointerInfo(), MVT::i32, false, false,
12164 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12167 auto &DL = DAG.getDataLayout();
12169 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12170 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12172 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12175 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12178 // Get the offset of start of .tls section
12179 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12180 GA->getValueType(0),
12181 GA->getOffset(), X86II::MO_SECREL);
12182 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12184 // The address of the thread local variable is the add of the thread
12185 // pointer with the offset of the variable.
12186 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12189 llvm_unreachable("TLS not implemented for this target.");
12192 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12193 /// and take a 2 x i32 value to shift plus a shift amount.
12194 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12195 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12196 MVT VT = Op.getSimpleValueType();
12197 unsigned VTBits = VT.getSizeInBits();
12199 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12200 SDValue ShOpLo = Op.getOperand(0);
12201 SDValue ShOpHi = Op.getOperand(1);
12202 SDValue ShAmt = Op.getOperand(2);
12203 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12204 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12206 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12207 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12208 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12209 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12210 : DAG.getConstant(0, dl, VT);
12212 SDValue Tmp2, Tmp3;
12213 if (Op.getOpcode() == ISD::SHL_PARTS) {
12214 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12215 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12217 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12218 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12221 // If the shift amount is larger or equal than the width of a part we can't
12222 // rely on the results of shld/shrd. Insert a test and select the appropriate
12223 // values for large shift amounts.
12224 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12225 DAG.getConstant(VTBits, dl, MVT::i8));
12226 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12227 AndNode, DAG.getConstant(0, dl, MVT::i8));
12230 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12231 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12232 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12234 if (Op.getOpcode() == ISD::SHL_PARTS) {
12235 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12236 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12238 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12239 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12242 SDValue Ops[2] = { Lo, Hi };
12243 return DAG.getMergeValues(Ops, dl);
12246 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12247 SelectionDAG &DAG) const {
12248 SDValue Src = Op.getOperand(0);
12249 MVT SrcVT = Src.getSimpleValueType();
12250 MVT VT = Op.getSimpleValueType();
12253 if (SrcVT.isVector()) {
12254 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12255 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12256 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12257 DAG.getUNDEF(SrcVT)));
12259 if (SrcVT.getVectorElementType() == MVT::i1) {
12260 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12261 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12262 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12267 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12268 "Unknown SINT_TO_FP to lower!");
12270 // These are really Legal; return the operand so the caller accepts it as
12272 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12274 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12275 Subtarget->is64Bit()) {
12279 unsigned Size = SrcVT.getSizeInBits()/8;
12280 MachineFunction &MF = DAG.getMachineFunction();
12281 auto PtrVT = getPointerTy(MF.getDataLayout());
12282 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12283 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12284 SDValue Chain = DAG.getStore(
12285 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12286 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12288 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12291 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12293 SelectionDAG &DAG) const {
12297 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12299 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12301 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12303 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12305 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12306 MachineMemOperand *MMO;
12308 int SSFI = FI->getIndex();
12309 MMO = DAG.getMachineFunction().getMachineMemOperand(
12310 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12311 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12313 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12314 StackSlot = StackSlot.getOperand(1);
12316 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12317 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12319 Tys, Ops, SrcVT, MMO);
12322 Chain = Result.getValue(1);
12323 SDValue InFlag = Result.getValue(2);
12325 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12326 // shouldn't be necessary except that RFP cannot be live across
12327 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12328 MachineFunction &MF = DAG.getMachineFunction();
12329 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12330 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12331 auto PtrVT = getPointerTy(MF.getDataLayout());
12332 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12333 Tys = DAG.getVTList(MVT::Other);
12335 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12337 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12338 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12339 MachineMemOperand::MOStore, SSFISize, SSFISize);
12341 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12342 Ops, Op.getValueType(), MMO);
12343 Result = DAG.getLoad(
12344 Op.getValueType(), DL, Chain, StackSlot,
12345 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12346 false, false, false, 0);
12352 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12353 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12354 SelectionDAG &DAG) const {
12355 // This algorithm is not obvious. Here it is what we're trying to output:
12358 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12359 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12361 haddpd %xmm0, %xmm0
12363 pshufd $0x4e, %xmm0, %xmm1
12369 LLVMContext *Context = DAG.getContext();
12371 // Build some magic constants.
12372 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12373 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12374 auto PtrVT = getPointerTy(DAG.getDataLayout());
12375 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12377 SmallVector<Constant*,2> CV1;
12379 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12380 APInt(64, 0x4330000000000000ULL))));
12382 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12383 APInt(64, 0x4530000000000000ULL))));
12384 Constant *C1 = ConstantVector::get(CV1);
12385 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12387 // Load the 64-bit value into an XMM register.
12388 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12391 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12392 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12393 false, false, false, 16);
12395 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12398 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12399 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12400 false, false, false, 16);
12401 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12402 // TODO: Are there any fast-math-flags to propagate here?
12403 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12406 if (Subtarget->hasSSE3()) {
12407 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12408 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12410 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12411 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12413 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12414 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12417 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12418 DAG.getIntPtrConstant(0, dl));
12421 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12422 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12423 SelectionDAG &DAG) const {
12425 // FP constant to bias correct the final result.
12426 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12429 // Load the 32-bit value into an XMM register.
12430 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12433 // Zero out the upper parts of the register.
12434 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12436 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12437 DAG.getBitcast(MVT::v2f64, Load),
12438 DAG.getIntPtrConstant(0, dl));
12440 // Or the load with the bias.
12441 SDValue Or = DAG.getNode(
12442 ISD::OR, dl, MVT::v2i64,
12443 DAG.getBitcast(MVT::v2i64,
12444 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12445 DAG.getBitcast(MVT::v2i64,
12446 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12448 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12449 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12451 // Subtract the bias.
12452 // TODO: Are there any fast-math-flags to propagate here?
12453 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12455 // Handle final rounding.
12456 EVT DestVT = Op.getValueType();
12458 if (DestVT.bitsLT(MVT::f64))
12459 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12460 DAG.getIntPtrConstant(0, dl));
12461 if (DestVT.bitsGT(MVT::f64))
12462 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12464 // Handle final rounding.
12468 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12469 const X86Subtarget &Subtarget) {
12470 // The algorithm is the following:
12471 // #ifdef __SSE4_1__
12472 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12473 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12474 // (uint4) 0x53000000, 0xaa);
12476 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12477 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12479 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12480 // return (float4) lo + fhi;
12482 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12483 // reassociate the two FADDs, and if we do that, the algorithm fails
12484 // spectacularly (PR24512).
12485 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12486 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12487 // there's also the MachineCombiner reassociations happening on Machine IR.
12488 if (DAG.getTarget().Options.UnsafeFPMath)
12492 SDValue V = Op->getOperand(0);
12493 EVT VecIntVT = V.getValueType();
12494 bool Is128 = VecIntVT == MVT::v4i32;
12495 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12496 // If we convert to something else than the supported type, e.g., to v4f64,
12498 if (VecFloatVT != Op->getValueType(0))
12501 unsigned NumElts = VecIntVT.getVectorNumElements();
12502 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12503 "Unsupported custom type");
12504 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12506 // In the #idef/#else code, we have in common:
12507 // - The vector of constants:
12513 // Create the splat vector for 0x4b000000.
12514 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12515 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12516 CstLow, CstLow, CstLow, CstLow};
12517 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12518 makeArrayRef(&CstLowArray[0], NumElts));
12519 // Create the splat vector for 0x53000000.
12520 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12521 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12522 CstHigh, CstHigh, CstHigh, CstHigh};
12523 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12524 makeArrayRef(&CstHighArray[0], NumElts));
12526 // Create the right shift.
12527 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12528 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12529 CstShift, CstShift, CstShift, CstShift};
12530 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12531 makeArrayRef(&CstShiftArray[0], NumElts));
12532 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12535 if (Subtarget.hasSSE41()) {
12536 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12537 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12538 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12539 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12540 // Low will be bitcasted right away, so do not bother bitcasting back to its
12542 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12543 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12544 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12545 // (uint4) 0x53000000, 0xaa);
12546 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12547 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12548 // High will be bitcasted right away, so do not bother bitcasting back to
12549 // its original type.
12550 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12551 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12553 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12554 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12555 CstMask, CstMask, CstMask);
12556 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12557 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12558 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12560 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12561 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12564 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12565 SDValue CstFAdd = DAG.getConstantFP(
12566 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12567 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12568 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12569 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12570 makeArrayRef(&CstFAddArray[0], NumElts));
12572 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12573 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12574 // TODO: Are there any fast-math-flags to propagate here?
12576 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12577 // return (float4) lo + fhi;
12578 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12579 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12582 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12583 SelectionDAG &DAG) const {
12584 SDValue N0 = Op.getOperand(0);
12585 MVT SVT = N0.getSimpleValueType();
12588 switch (SVT.SimpleTy) {
12590 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12595 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12596 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12597 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12601 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12604 if (Subtarget->hasAVX512())
12605 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12606 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12608 llvm_unreachable(nullptr);
12611 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12612 SelectionDAG &DAG) const {
12613 SDValue N0 = Op.getOperand(0);
12615 auto PtrVT = getPointerTy(DAG.getDataLayout());
12617 if (Op.getValueType().isVector())
12618 return lowerUINT_TO_FP_vec(Op, DAG);
12620 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12621 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12622 // the optimization here.
12623 if (DAG.SignBitIsZero(N0))
12624 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12626 MVT SrcVT = N0.getSimpleValueType();
12627 MVT DstVT = Op.getSimpleValueType();
12629 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12630 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12631 // Conversions from unsigned i32 to f32/f64 are legal,
12632 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12636 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12637 return LowerUINT_TO_FP_i64(Op, DAG);
12638 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12639 return LowerUINT_TO_FP_i32(Op, DAG);
12640 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12643 // Make a 64-bit buffer, and use it to build an FILD.
12644 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12645 if (SrcVT == MVT::i32) {
12646 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12647 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12648 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12649 StackSlot, MachinePointerInfo(),
12651 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12652 OffsetSlot, MachinePointerInfo(),
12654 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12658 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12659 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12660 StackSlot, MachinePointerInfo(),
12662 // For i64 source, we need to add the appropriate power of 2 if the input
12663 // was negative. This is the same as the optimization in
12664 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12665 // we must be careful to do the computation in x87 extended precision, not
12666 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12667 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12668 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12669 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12670 MachineMemOperand::MOLoad, 8, 8);
12672 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12673 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12674 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12677 APInt FF(32, 0x5F800000ULL);
12679 // Check whether the sign bit is set.
12680 SDValue SignSet = DAG.getSetCC(
12681 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12682 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12684 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12685 SDValue FudgePtr = DAG.getConstantPool(
12686 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12688 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12689 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12690 SDValue Four = DAG.getIntPtrConstant(4, dl);
12691 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12693 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12695 // Load the value out, extending it from f32 to f80.
12696 // FIXME: Avoid the extend by constructing the right constant pool?
12697 SDValue Fudge = DAG.getExtLoad(
12698 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12699 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12700 false, false, false, 4);
12701 // Extend everything to 80 bits to force it to be done on x87.
12702 // TODO: Are there any fast-math-flags to propagate here?
12703 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12704 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12705 DAG.getIntPtrConstant(0, dl));
12708 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12709 // is legal, or has an f16 source (which needs to be promoted to f32),
12710 // just return an <SDValue(), SDValue()> pair.
12711 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12712 // to i16, i32 or i64, and we lower it to a legal sequence.
12713 // If lowered to the final integer result we return a <result, SDValue()> pair.
12714 // Otherwise we lower it to a sequence ending with a FIST, return a
12715 // <FIST, StackSlot> pair, and the caller is responsible for loading
12716 // the final integer result from StackSlot.
12717 std::pair<SDValue,SDValue>
12718 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12719 bool IsSigned, bool IsReplace) const {
12722 EVT DstTy = Op.getValueType();
12723 EVT TheVT = Op.getOperand(0).getValueType();
12724 auto PtrVT = getPointerTy(DAG.getDataLayout());
12726 if (TheVT == MVT::f16)
12727 // We need to promote the f16 to f32 before using the lowering
12728 // in this routine.
12729 return std::make_pair(SDValue(), SDValue());
12731 assert((TheVT == MVT::f32 ||
12732 TheVT == MVT::f64 ||
12733 TheVT == MVT::f80) &&
12734 "Unexpected FP operand type in FP_TO_INTHelper");
12736 // If using FIST to compute an unsigned i64, we'll need some fixup
12737 // to handle values above the maximum signed i64. A FIST is always
12738 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12739 bool UnsignedFixup = !IsSigned &&
12740 DstTy == MVT::i64 &&
12741 (!Subtarget->is64Bit() ||
12742 !isScalarFPTypeInSSEReg(TheVT));
12744 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12745 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12746 // The low 32 bits of the fist result will have the correct uint32 result.
12747 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12751 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12752 DstTy.getSimpleVT() >= MVT::i16 &&
12753 "Unknown FP_TO_INT to lower!");
12755 // These are really Legal.
12756 if (DstTy == MVT::i32 &&
12757 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12758 return std::make_pair(SDValue(), SDValue());
12759 if (Subtarget->is64Bit() &&
12760 DstTy == MVT::i64 &&
12761 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12762 return std::make_pair(SDValue(), SDValue());
12764 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12766 MachineFunction &MF = DAG.getMachineFunction();
12767 unsigned MemSize = DstTy.getSizeInBits()/8;
12768 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12769 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12772 switch (DstTy.getSimpleVT().SimpleTy) {
12773 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12774 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12775 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12776 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12779 SDValue Chain = DAG.getEntryNode();
12780 SDValue Value = Op.getOperand(0);
12781 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12783 if (UnsignedFixup) {
12785 // Conversion to unsigned i64 is implemented with a select,
12786 // depending on whether the source value fits in the range
12787 // of a signed i64. Let Thresh be the FP equivalent of
12788 // 0x8000000000000000ULL.
12790 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12791 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12792 // Fist-to-mem64 FistSrc
12793 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12794 // to XOR'ing the high 32 bits with Adjust.
12796 // Being a power of 2, Thresh is exactly representable in all FP formats.
12797 // For X87 we'd like to use the smallest FP type for this constant, but
12798 // for DAG type consistency we have to match the FP operand type.
12800 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12801 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12802 bool LosesInfo = false;
12803 if (TheVT == MVT::f64)
12804 // The rounding mode is irrelevant as the conversion should be exact.
12805 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12807 else if (TheVT == MVT::f80)
12808 Status = Thresh.convert(APFloat::x87DoubleExtended,
12809 APFloat::rmNearestTiesToEven, &LosesInfo);
12811 assert(Status == APFloat::opOK && !LosesInfo &&
12812 "FP conversion should have been exact");
12814 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12816 SDValue Cmp = DAG.getSetCC(DL,
12817 getSetCCResultType(DAG.getDataLayout(),
12818 *DAG.getContext(), TheVT),
12819 Value, ThreshVal, ISD::SETLT);
12820 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12821 DAG.getConstant(0, DL, MVT::i32),
12822 DAG.getConstant(0x80000000, DL, MVT::i32));
12823 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12824 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12825 *DAG.getContext(), TheVT),
12826 Value, ThreshVal, ISD::SETLT);
12827 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12830 // FIXME This causes a redundant load/store if the SSE-class value is already
12831 // in memory, such as if it is on the callstack.
12832 if (isScalarFPTypeInSSEReg(TheVT)) {
12833 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12834 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12835 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12837 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12839 Chain, StackSlot, DAG.getValueType(TheVT)
12842 MachineMemOperand *MMO =
12843 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12844 MachineMemOperand::MOLoad, MemSize, MemSize);
12845 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12846 Chain = Value.getValue(1);
12847 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12848 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12851 MachineMemOperand *MMO =
12852 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12853 MachineMemOperand::MOStore, MemSize, MemSize);
12855 if (UnsignedFixup) {
12857 // Insert the FIST, load its result as two i32's,
12858 // and XOR the high i32 with Adjust.
12860 SDValue FistOps[] = { Chain, Value, StackSlot };
12861 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12862 FistOps, DstTy, MMO);
12864 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12865 MachinePointerInfo(),
12866 false, false, false, 0);
12867 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12868 DAG.getConstant(4, DL, PtrVT));
12870 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12871 MachinePointerInfo(),
12872 false, false, false, 0);
12873 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12875 if (Subtarget->is64Bit()) {
12876 // Join High32 and Low32 into a 64-bit result.
12877 // (High32 << 32) | Low32
12878 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12879 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12880 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12881 DAG.getConstant(32, DL, MVT::i8));
12882 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12883 return std::make_pair(Result, SDValue());
12886 SDValue ResultOps[] = { Low32, High32 };
12888 SDValue pair = IsReplace
12889 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12890 : DAG.getMergeValues(ResultOps, DL);
12891 return std::make_pair(pair, SDValue());
12893 // Build the FP_TO_INT*_IN_MEM
12894 SDValue Ops[] = { Chain, Value, StackSlot };
12895 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12897 return std::make_pair(FIST, StackSlot);
12901 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12902 const X86Subtarget *Subtarget) {
12903 MVT VT = Op->getSimpleValueType(0);
12904 SDValue In = Op->getOperand(0);
12905 MVT InVT = In.getSimpleValueType();
12908 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12909 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12911 // Optimize vectors in AVX mode:
12914 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12915 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12916 // Concat upper and lower parts.
12919 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12920 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12921 // Concat upper and lower parts.
12924 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12925 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12926 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12929 if (Subtarget->hasInt256())
12930 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12932 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12933 SDValue Undef = DAG.getUNDEF(InVT);
12934 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12935 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12936 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12938 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12939 VT.getVectorNumElements()/2);
12941 OpLo = DAG.getBitcast(HVT, OpLo);
12942 OpHi = DAG.getBitcast(HVT, OpHi);
12944 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12947 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12948 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12949 MVT VT = Op->getSimpleValueType(0);
12950 SDValue In = Op->getOperand(0);
12951 MVT InVT = In.getSimpleValueType();
12953 unsigned int NumElts = VT.getVectorNumElements();
12954 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12957 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12958 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12960 assert(InVT.getVectorElementType() == MVT::i1);
12961 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12963 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12965 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12967 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12968 if (VT.is512BitVector())
12970 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12973 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12974 SelectionDAG &DAG) {
12975 if (Subtarget->hasFp256())
12976 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12982 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12983 SelectionDAG &DAG) {
12985 MVT VT = Op.getSimpleValueType();
12986 SDValue In = Op.getOperand(0);
12987 MVT SVT = In.getSimpleValueType();
12989 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12990 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12992 if (Subtarget->hasFp256())
12993 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12996 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12997 VT.getVectorNumElements() != SVT.getVectorNumElements());
13001 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13003 MVT VT = Op.getSimpleValueType();
13004 SDValue In = Op.getOperand(0);
13005 MVT InVT = In.getSimpleValueType();
13007 if (VT == MVT::i1) {
13008 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13009 "Invalid scalar TRUNCATE operation");
13010 if (InVT.getSizeInBits() >= 32)
13012 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13013 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13015 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13016 "Invalid TRUNCATE operation");
13018 // move vector to mask - truncate solution for SKX
13019 if (VT.getVectorElementType() == MVT::i1) {
13020 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13021 Subtarget->hasBWI())
13022 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13023 if ((InVT.is256BitVector() || InVT.is128BitVector())
13024 && InVT.getScalarSizeInBits() <= 16 &&
13025 Subtarget->hasBWI() && Subtarget->hasVLX())
13026 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13027 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13028 Subtarget->hasDQI())
13029 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13030 if ((InVT.is256BitVector() || InVT.is128BitVector())
13031 && InVT.getScalarSizeInBits() >= 32 &&
13032 Subtarget->hasDQI() && Subtarget->hasVLX())
13033 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13036 if (VT.getVectorElementType() == MVT::i1) {
13037 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13038 unsigned NumElts = InVT.getVectorNumElements();
13039 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13040 if (InVT.getSizeInBits() < 512) {
13041 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13042 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13047 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13048 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13049 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13052 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13053 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
13054 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
13055 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13057 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13058 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13059 if (Subtarget->hasInt256()) {
13060 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13061 In = DAG.getBitcast(MVT::v8i32, In);
13062 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13064 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13065 DAG.getIntPtrConstant(0, DL));
13068 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13069 DAG.getIntPtrConstant(0, DL));
13070 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13071 DAG.getIntPtrConstant(2, DL));
13072 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13073 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13074 static const int ShufMask[] = {0, 2, 4, 6};
13075 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13078 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13079 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13080 if (Subtarget->hasInt256()) {
13081 In = DAG.getBitcast(MVT::v32i8, In);
13083 SmallVector<SDValue,32> pshufbMask;
13084 for (unsigned i = 0; i < 2; ++i) {
13085 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13086 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13087 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13088 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13089 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13090 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13091 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13092 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13093 for (unsigned j = 0; j < 8; ++j)
13094 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13096 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13097 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13098 In = DAG.getBitcast(MVT::v4i64, In);
13100 static const int ShufMask[] = {0, 2, -1, -1};
13101 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13103 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13104 DAG.getIntPtrConstant(0, DL));
13105 return DAG.getBitcast(VT, In);
13108 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13109 DAG.getIntPtrConstant(0, DL));
13111 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13112 DAG.getIntPtrConstant(4, DL));
13114 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13115 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13117 // The PSHUFB mask:
13118 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13119 -1, -1, -1, -1, -1, -1, -1, -1};
13121 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13122 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13123 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13125 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13126 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13128 // The MOVLHPS Mask:
13129 static const int ShufMask2[] = {0, 1, 4, 5};
13130 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13131 return DAG.getBitcast(MVT::v8i16, res);
13134 // Handle truncation of V256 to V128 using shuffles.
13135 if (!VT.is128BitVector() || !InVT.is256BitVector())
13138 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13140 unsigned NumElems = VT.getVectorNumElements();
13141 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13143 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13144 // Prepare truncation shuffle mask
13145 for (unsigned i = 0; i != NumElems; ++i)
13146 MaskVec[i] = i * 2;
13147 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13148 DAG.getUNDEF(NVT), &MaskVec[0]);
13149 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13150 DAG.getIntPtrConstant(0, DL));
13153 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13154 SelectionDAG &DAG) const {
13155 assert(!Op.getSimpleValueType().isVector());
13157 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13158 /*IsSigned=*/ true, /*IsReplace=*/ false);
13159 SDValue FIST = Vals.first, StackSlot = Vals.second;
13160 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13161 if (!FIST.getNode())
13164 if (StackSlot.getNode())
13165 // Load the result.
13166 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13167 FIST, StackSlot, MachinePointerInfo(),
13168 false, false, false, 0);
13170 // The node is the result.
13174 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13175 SelectionDAG &DAG) const {
13176 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13177 /*IsSigned=*/ false, /*IsReplace=*/ false);
13178 SDValue FIST = Vals.first, StackSlot = Vals.second;
13179 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13180 if (!FIST.getNode())
13183 if (StackSlot.getNode())
13184 // Load the result.
13185 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13186 FIST, StackSlot, MachinePointerInfo(),
13187 false, false, false, 0);
13189 // The node is the result.
13193 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13195 MVT VT = Op.getSimpleValueType();
13196 SDValue In = Op.getOperand(0);
13197 MVT SVT = In.getSimpleValueType();
13199 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13201 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13202 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13203 In, DAG.getUNDEF(SVT)));
13206 /// The only differences between FABS and FNEG are the mask and the logic op.
13207 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13208 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13209 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13210 "Wrong opcode for lowering FABS or FNEG.");
13212 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13214 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13215 // into an FNABS. We'll lower the FABS after that if it is still in use.
13217 for (SDNode *User : Op->uses())
13218 if (User->getOpcode() == ISD::FNEG)
13222 MVT VT = Op.getSimpleValueType();
13224 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13225 // decide if we should generate a 16-byte constant mask when we only need 4 or
13226 // 8 bytes for the scalar case.
13232 if (VT.isVector()) {
13234 EltVT = VT.getVectorElementType();
13235 NumElts = VT.getVectorNumElements();
13237 // There are no scalar bitwise logical SSE/AVX instructions, so we
13238 // generate a 16-byte vector constant and logic op even for the scalar case.
13239 // Using a 16-byte mask allows folding the load of the mask with
13240 // the logic op, so it can save (~4 bytes) on code size.
13241 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13243 NumElts = (VT == MVT::f64) ? 2 : 4;
13246 unsigned EltBits = EltVT.getSizeInBits();
13247 LLVMContext *Context = DAG.getContext();
13248 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13250 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13251 Constant *C = ConstantInt::get(*Context, MaskElt);
13252 C = ConstantVector::getSplat(NumElts, C);
13253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13254 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13255 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13257 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13258 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13259 false, false, false, Alignment);
13261 SDValue Op0 = Op.getOperand(0);
13262 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13264 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13265 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13268 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13270 // For the scalar case extend to a 128-bit vector, perform the logic op,
13271 // and extract the scalar result back out.
13272 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13273 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13274 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13275 DAG.getIntPtrConstant(0, dl));
13278 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13279 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13280 LLVMContext *Context = DAG.getContext();
13281 SDValue Op0 = Op.getOperand(0);
13282 SDValue Op1 = Op.getOperand(1);
13284 MVT VT = Op.getSimpleValueType();
13285 MVT SrcVT = Op1.getSimpleValueType();
13287 // If second operand is smaller, extend it first.
13288 if (SrcVT.bitsLT(VT)) {
13289 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13292 // And if it is bigger, shrink it first.
13293 if (SrcVT.bitsGT(VT)) {
13294 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13298 // At this point the operands and the result should have the same
13299 // type, and that won't be f80 since that is not custom lowered.
13301 const fltSemantics &Sem =
13302 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13303 const unsigned SizeInBits = VT.getSizeInBits();
13305 SmallVector<Constant *, 4> CV(
13306 VT == MVT::f64 ? 2 : 4,
13307 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13309 // First, clear all bits but the sign bit from the second operand (sign).
13310 CV[0] = ConstantFP::get(*Context,
13311 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13312 Constant *C = ConstantVector::get(CV);
13313 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13314 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13316 // Perform all logic operations as 16-byte vectors because there are no
13317 // scalar FP logic instructions in SSE. This allows load folding of the
13318 // constants into the logic instructions.
13319 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13321 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13322 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13323 false, false, false, 16);
13324 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13325 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13327 // Next, clear the sign bit from the first operand (magnitude).
13328 // If it's a constant, we can clear it here.
13329 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13330 APFloat APF = Op0CN->getValueAPF();
13331 // If the magnitude is a positive zero, the sign bit alone is enough.
13332 if (APF.isPosZero())
13333 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13334 DAG.getIntPtrConstant(0, dl));
13336 CV[0] = ConstantFP::get(*Context, APF);
13338 CV[0] = ConstantFP::get(
13340 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13342 C = ConstantVector::get(CV);
13343 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13345 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13346 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13347 false, false, false, 16);
13348 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13349 if (!isa<ConstantFPSDNode>(Op0)) {
13350 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13351 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13353 // OR the magnitude value with the sign bit.
13354 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13355 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13356 DAG.getIntPtrConstant(0, dl));
13359 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13360 SDValue N0 = Op.getOperand(0);
13362 MVT VT = Op.getSimpleValueType();
13364 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13365 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13366 DAG.getConstant(1, dl, VT));
13367 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13370 // Check whether an OR'd tree is PTEST-able.
13371 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13372 SelectionDAG &DAG) {
13373 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13375 if (!Subtarget->hasSSE41())
13378 if (!Op->hasOneUse())
13381 SDNode *N = Op.getNode();
13384 SmallVector<SDValue, 8> Opnds;
13385 DenseMap<SDValue, unsigned> VecInMap;
13386 SmallVector<SDValue, 8> VecIns;
13387 EVT VT = MVT::Other;
13389 // Recognize a special case where a vector is casted into wide integer to
13391 Opnds.push_back(N->getOperand(0));
13392 Opnds.push_back(N->getOperand(1));
13394 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13395 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13396 // BFS traverse all OR'd operands.
13397 if (I->getOpcode() == ISD::OR) {
13398 Opnds.push_back(I->getOperand(0));
13399 Opnds.push_back(I->getOperand(1));
13400 // Re-evaluate the number of nodes to be traversed.
13401 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13405 // Quit if a non-EXTRACT_VECTOR_ELT
13406 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13409 // Quit if without a constant index.
13410 SDValue Idx = I->getOperand(1);
13411 if (!isa<ConstantSDNode>(Idx))
13414 SDValue ExtractedFromVec = I->getOperand(0);
13415 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13416 if (M == VecInMap.end()) {
13417 VT = ExtractedFromVec.getValueType();
13418 // Quit if not 128/256-bit vector.
13419 if (!VT.is128BitVector() && !VT.is256BitVector())
13421 // Quit if not the same type.
13422 if (VecInMap.begin() != VecInMap.end() &&
13423 VT != VecInMap.begin()->first.getValueType())
13425 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13426 VecIns.push_back(ExtractedFromVec);
13428 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13431 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13432 "Not extracted from 128-/256-bit vector.");
13434 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13436 for (DenseMap<SDValue, unsigned>::const_iterator
13437 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13438 // Quit if not all elements are used.
13439 if (I->second != FullMask)
13443 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13445 // Cast all vectors into TestVT for PTEST.
13446 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13447 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13449 // If more than one full vectors are evaluated, OR them first before PTEST.
13450 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13451 // Each iteration will OR 2 nodes and append the result until there is only
13452 // 1 node left, i.e. the final OR'd value of all vectors.
13453 SDValue LHS = VecIns[Slot];
13454 SDValue RHS = VecIns[Slot + 1];
13455 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13458 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13459 VecIns.back(), VecIns.back());
13462 /// \brief return true if \c Op has a use that doesn't just read flags.
13463 static bool hasNonFlagsUse(SDValue Op) {
13464 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13466 SDNode *User = *UI;
13467 unsigned UOpNo = UI.getOperandNo();
13468 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13469 // Look pass truncate.
13470 UOpNo = User->use_begin().getOperandNo();
13471 User = *User->use_begin();
13474 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13475 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13481 /// Emit nodes that will be selected as "test Op0,Op0", or something
13483 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13484 SelectionDAG &DAG) const {
13485 if (Op.getValueType() == MVT::i1) {
13486 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13487 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13488 DAG.getConstant(0, dl, MVT::i8));
13490 // CF and OF aren't always set the way we want. Determine which
13491 // of these we need.
13492 bool NeedCF = false;
13493 bool NeedOF = false;
13496 case X86::COND_A: case X86::COND_AE:
13497 case X86::COND_B: case X86::COND_BE:
13500 case X86::COND_G: case X86::COND_GE:
13501 case X86::COND_L: case X86::COND_LE:
13502 case X86::COND_O: case X86::COND_NO: {
13503 // Check if we really need to set the
13504 // Overflow flag. If NoSignedWrap is present
13505 // that is not actually needed.
13506 switch (Op->getOpcode()) {
13511 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13512 if (BinNode->Flags.hasNoSignedWrap())
13522 // See if we can use the EFLAGS value from the operand instead of
13523 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13524 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13525 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13526 // Emit a CMP with 0, which is the TEST pattern.
13527 //if (Op.getValueType() == MVT::i1)
13528 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13529 // DAG.getConstant(0, MVT::i1));
13530 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13531 DAG.getConstant(0, dl, Op.getValueType()));
13533 unsigned Opcode = 0;
13534 unsigned NumOperands = 0;
13536 // Truncate operations may prevent the merge of the SETCC instruction
13537 // and the arithmetic instruction before it. Attempt to truncate the operands
13538 // of the arithmetic instruction and use a reduced bit-width instruction.
13539 bool NeedTruncation = false;
13540 SDValue ArithOp = Op;
13541 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13542 SDValue Arith = Op->getOperand(0);
13543 // Both the trunc and the arithmetic op need to have one user each.
13544 if (Arith->hasOneUse())
13545 switch (Arith.getOpcode()) {
13552 NeedTruncation = true;
13558 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13559 // which may be the result of a CAST. We use the variable 'Op', which is the
13560 // non-casted variable when we check for possible users.
13561 switch (ArithOp.getOpcode()) {
13563 // Due to an isel shortcoming, be conservative if this add is likely to be
13564 // selected as part of a load-modify-store instruction. When the root node
13565 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13566 // uses of other nodes in the match, such as the ADD in this case. This
13567 // leads to the ADD being left around and reselected, with the result being
13568 // two adds in the output. Alas, even if none our users are stores, that
13569 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13570 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13571 // climbing the DAG back to the root, and it doesn't seem to be worth the
13573 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13574 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13575 if (UI->getOpcode() != ISD::CopyToReg &&
13576 UI->getOpcode() != ISD::SETCC &&
13577 UI->getOpcode() != ISD::STORE)
13580 if (ConstantSDNode *C =
13581 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13582 // An add of one will be selected as an INC.
13583 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13584 Opcode = X86ISD::INC;
13589 // An add of negative one (subtract of one) will be selected as a DEC.
13590 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13591 Opcode = X86ISD::DEC;
13597 // Otherwise use a regular EFLAGS-setting add.
13598 Opcode = X86ISD::ADD;
13603 // If we have a constant logical shift that's only used in a comparison
13604 // against zero turn it into an equivalent AND. This allows turning it into
13605 // a TEST instruction later.
13606 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13607 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13608 EVT VT = Op.getValueType();
13609 unsigned BitWidth = VT.getSizeInBits();
13610 unsigned ShAmt = Op->getConstantOperandVal(1);
13611 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13613 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13614 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13615 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13616 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13618 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13619 DAG.getConstant(Mask, dl, VT));
13620 DAG.ReplaceAllUsesWith(Op, New);
13626 // If the primary and result isn't used, don't bother using X86ISD::AND,
13627 // because a TEST instruction will be better.
13628 if (!hasNonFlagsUse(Op))
13634 // Due to the ISEL shortcoming noted above, be conservative if this op is
13635 // likely to be selected as part of a load-modify-store instruction.
13636 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13637 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13638 if (UI->getOpcode() == ISD::STORE)
13641 // Otherwise use a regular EFLAGS-setting instruction.
13642 switch (ArithOp.getOpcode()) {
13643 default: llvm_unreachable("unexpected operator!");
13644 case ISD::SUB: Opcode = X86ISD::SUB; break;
13645 case ISD::XOR: Opcode = X86ISD::XOR; break;
13646 case ISD::AND: Opcode = X86ISD::AND; break;
13648 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13649 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13650 if (EFLAGS.getNode())
13653 Opcode = X86ISD::OR;
13667 return SDValue(Op.getNode(), 1);
13673 // If we found that truncation is beneficial, perform the truncation and
13675 if (NeedTruncation) {
13676 EVT VT = Op.getValueType();
13677 SDValue WideVal = Op->getOperand(0);
13678 EVT WideVT = WideVal.getValueType();
13679 unsigned ConvertedOp = 0;
13680 // Use a target machine opcode to prevent further DAGCombine
13681 // optimizations that may separate the arithmetic operations
13682 // from the setcc node.
13683 switch (WideVal.getOpcode()) {
13685 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13686 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13687 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13688 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13689 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13693 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13694 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13695 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13696 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13697 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13703 // Emit a CMP with 0, which is the TEST pattern.
13704 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13705 DAG.getConstant(0, dl, Op.getValueType()));
13707 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13708 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13710 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13711 DAG.ReplaceAllUsesWith(Op, New);
13712 return SDValue(New.getNode(), 1);
13715 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13717 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13718 SDLoc dl, SelectionDAG &DAG) const {
13719 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13720 if (C->getAPIntValue() == 0)
13721 return EmitTest(Op0, X86CC, dl, DAG);
13723 if (Op0.getValueType() == MVT::i1)
13724 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13727 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13728 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13729 // Do the comparison at i32 if it's smaller, besides the Atom case.
13730 // This avoids subregister aliasing issues. Keep the smaller reference
13731 // if we're optimizing for size, however, as that'll allow better folding
13732 // of memory operations.
13733 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13734 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13735 !Subtarget->isAtom()) {
13736 unsigned ExtendOp =
13737 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13738 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13739 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13741 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13742 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13743 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13745 return SDValue(Sub.getNode(), 1);
13747 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13750 /// Convert a comparison if required by the subtarget.
13751 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13752 SelectionDAG &DAG) const {
13753 // If the subtarget does not support the FUCOMI instruction, floating-point
13754 // comparisons have to be converted.
13755 if (Subtarget->hasCMov() ||
13756 Cmp.getOpcode() != X86ISD::CMP ||
13757 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13758 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13761 // The instruction selector will select an FUCOM instruction instead of
13762 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13763 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13764 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13766 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13767 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13768 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13769 DAG.getConstant(8, dl, MVT::i8));
13770 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13771 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13774 /// The minimum architected relative accuracy is 2^-12. We need one
13775 /// Newton-Raphson step to have a good float result (24 bits of precision).
13776 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13777 DAGCombinerInfo &DCI,
13778 unsigned &RefinementSteps,
13779 bool &UseOneConstNR) const {
13780 EVT VT = Op.getValueType();
13781 const char *RecipOp;
13783 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13784 // TODO: Add support for AVX512 (v16f32).
13785 // It is likely not profitable to do this for f64 because a double-precision
13786 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13787 // instructions: convert to single, rsqrtss, convert back to double, refine
13788 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13789 // along with FMA, this could be a throughput win.
13790 if (VT == MVT::f32 && Subtarget->hasSSE1())
13792 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13793 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13794 RecipOp = "vec-sqrtf";
13798 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13799 if (!Recips.isEnabled(RecipOp))
13802 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13803 UseOneConstNR = false;
13804 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13807 /// The minimum architected relative accuracy is 2^-12. We need one
13808 /// Newton-Raphson step to have a good float result (24 bits of precision).
13809 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13810 DAGCombinerInfo &DCI,
13811 unsigned &RefinementSteps) const {
13812 EVT VT = Op.getValueType();
13813 const char *RecipOp;
13815 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13816 // TODO: Add support for AVX512 (v16f32).
13817 // It is likely not profitable to do this for f64 because a double-precision
13818 // reciprocal estimate with refinement on x86 prior to FMA requires
13819 // 15 instructions: convert to single, rcpss, convert back to double, refine
13820 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13821 // along with FMA, this could be a throughput win.
13822 if (VT == MVT::f32 && Subtarget->hasSSE1())
13824 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13825 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13826 RecipOp = "vec-divf";
13830 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13831 if (!Recips.isEnabled(RecipOp))
13834 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13835 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13838 /// If we have at least two divisions that use the same divisor, convert to
13839 /// multplication by a reciprocal. This may need to be adjusted for a given
13840 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13841 /// This is because we still need one division to calculate the reciprocal and
13842 /// then we need two multiplies by that reciprocal as replacements for the
13843 /// original divisions.
13844 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13848 static bool isAllOnes(SDValue V) {
13849 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13850 return C && C->isAllOnesValue();
13853 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13854 /// if it's possible.
13855 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13856 SDLoc dl, SelectionDAG &DAG) const {
13857 SDValue Op0 = And.getOperand(0);
13858 SDValue Op1 = And.getOperand(1);
13859 if (Op0.getOpcode() == ISD::TRUNCATE)
13860 Op0 = Op0.getOperand(0);
13861 if (Op1.getOpcode() == ISD::TRUNCATE)
13862 Op1 = Op1.getOperand(0);
13865 if (Op1.getOpcode() == ISD::SHL)
13866 std::swap(Op0, Op1);
13867 if (Op0.getOpcode() == ISD::SHL) {
13868 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13869 if (And00C->getZExtValue() == 1) {
13870 // If we looked past a truncate, check that it's only truncating away
13872 unsigned BitWidth = Op0.getValueSizeInBits();
13873 unsigned AndBitWidth = And.getValueSizeInBits();
13874 if (BitWidth > AndBitWidth) {
13876 DAG.computeKnownBits(Op0, Zeros, Ones);
13877 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13881 RHS = Op0.getOperand(1);
13883 } else if (Op1.getOpcode() == ISD::Constant) {
13884 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13885 uint64_t AndRHSVal = AndRHS->getZExtValue();
13886 SDValue AndLHS = Op0;
13888 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13889 LHS = AndLHS.getOperand(0);
13890 RHS = AndLHS.getOperand(1);
13893 // Use BT if the immediate can't be encoded in a TEST instruction.
13894 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13896 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13900 if (LHS.getNode()) {
13901 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13902 // instruction. Since the shift amount is in-range-or-undefined, we know
13903 // that doing a bittest on the i32 value is ok. We extend to i32 because
13904 // the encoding for the i16 version is larger than the i32 version.
13905 // Also promote i16 to i32 for performance / code size reason.
13906 if (LHS.getValueType() == MVT::i8 ||
13907 LHS.getValueType() == MVT::i16)
13908 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13910 // If the operand types disagree, extend the shift amount to match. Since
13911 // BT ignores high bits (like shifts) we can use anyextend.
13912 if (LHS.getValueType() != RHS.getValueType())
13913 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13915 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13916 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13917 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13918 DAG.getConstant(Cond, dl, MVT::i8), BT);
13924 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13926 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13931 // SSE Condition code mapping:
13940 switch (SetCCOpcode) {
13941 default: llvm_unreachable("Unexpected SETCC condition");
13943 case ISD::SETEQ: SSECC = 0; break;
13945 case ISD::SETGT: Swap = true; // Fallthrough
13947 case ISD::SETOLT: SSECC = 1; break;
13949 case ISD::SETGE: Swap = true; // Fallthrough
13951 case ISD::SETOLE: SSECC = 2; break;
13952 case ISD::SETUO: SSECC = 3; break;
13954 case ISD::SETNE: SSECC = 4; break;
13955 case ISD::SETULE: Swap = true; // Fallthrough
13956 case ISD::SETUGE: SSECC = 5; break;
13957 case ISD::SETULT: Swap = true; // Fallthrough
13958 case ISD::SETUGT: SSECC = 6; break;
13959 case ISD::SETO: SSECC = 7; break;
13961 case ISD::SETONE: SSECC = 8; break;
13964 std::swap(Op0, Op1);
13969 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13970 // ones, and then concatenate the result back.
13971 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13972 MVT VT = Op.getSimpleValueType();
13974 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13975 "Unsupported value type for operation");
13977 unsigned NumElems = VT.getVectorNumElements();
13979 SDValue CC = Op.getOperand(2);
13981 // Extract the LHS vectors
13982 SDValue LHS = Op.getOperand(0);
13983 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13984 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13986 // Extract the RHS vectors
13987 SDValue RHS = Op.getOperand(1);
13988 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13989 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13991 // Issue the operation on the smaller types and concatenate the result back
13992 MVT EltVT = VT.getVectorElementType();
13993 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13994 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13995 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13996 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13999 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14000 SDValue Op0 = Op.getOperand(0);
14001 SDValue Op1 = Op.getOperand(1);
14002 SDValue CC = Op.getOperand(2);
14003 MVT VT = Op.getSimpleValueType();
14006 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
14007 "Unexpected type for boolean compare operation");
14008 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14009 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14010 DAG.getConstant(-1, dl, VT));
14011 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14012 DAG.getConstant(-1, dl, VT));
14013 switch (SetCCOpcode) {
14014 default: llvm_unreachable("Unexpected SETCC condition");
14016 // (x == y) -> ~(x ^ y)
14017 return DAG.getNode(ISD::XOR, dl, VT,
14018 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14019 DAG.getConstant(-1, dl, VT));
14021 // (x != y) -> (x ^ y)
14022 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14025 // (x > y) -> (x & ~y)
14026 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14029 // (x < y) -> (~x & y)
14030 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14033 // (x <= y) -> (~x | y)
14034 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14037 // (x >=y) -> (x | ~y)
14038 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14042 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14043 const X86Subtarget *Subtarget) {
14044 SDValue Op0 = Op.getOperand(0);
14045 SDValue Op1 = Op.getOperand(1);
14046 SDValue CC = Op.getOperand(2);
14047 MVT VT = Op.getSimpleValueType();
14050 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14051 Op.getValueType().getScalarType() == MVT::i1 &&
14052 "Cannot set masked compare for this operation");
14054 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14056 bool Unsigned = false;
14059 switch (SetCCOpcode) {
14060 default: llvm_unreachable("Unexpected SETCC condition");
14061 case ISD::SETNE: SSECC = 4; break;
14062 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14063 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14064 case ISD::SETLT: Swap = true; //fall-through
14065 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14066 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14067 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14068 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14069 case ISD::SETULE: Unsigned = true; //fall-through
14070 case ISD::SETLE: SSECC = 2; break;
14074 std::swap(Op0, Op1);
14076 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14077 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14078 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14079 DAG.getConstant(SSECC, dl, MVT::i8));
14082 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14083 /// operand \p Op1. If non-trivial (for example because it's not constant)
14084 /// return an empty value.
14085 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14087 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14091 MVT VT = Op1.getSimpleValueType();
14092 MVT EVT = VT.getVectorElementType();
14093 unsigned n = VT.getVectorNumElements();
14094 SmallVector<SDValue, 8> ULTOp1;
14096 for (unsigned i = 0; i < n; ++i) {
14097 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14098 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14101 // Avoid underflow.
14102 APInt Val = Elt->getAPIntValue();
14106 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14109 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14112 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14113 SelectionDAG &DAG) {
14114 SDValue Op0 = Op.getOperand(0);
14115 SDValue Op1 = Op.getOperand(1);
14116 SDValue CC = Op.getOperand(2);
14117 MVT VT = Op.getSimpleValueType();
14118 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14119 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14124 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14125 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14128 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14129 unsigned Opc = X86ISD::CMPP;
14130 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14131 assert(VT.getVectorNumElements() <= 16);
14132 Opc = X86ISD::CMPM;
14134 // In the two special cases we can't handle, emit two comparisons.
14137 unsigned CombineOpc;
14138 if (SetCCOpcode == ISD::SETUEQ) {
14139 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14141 assert(SetCCOpcode == ISD::SETONE);
14142 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14145 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14146 DAG.getConstant(CC0, dl, MVT::i8));
14147 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14148 DAG.getConstant(CC1, dl, MVT::i8));
14149 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14151 // Handle all other FP comparisons here.
14152 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14153 DAG.getConstant(SSECC, dl, MVT::i8));
14156 MVT VTOp0 = Op0.getSimpleValueType();
14157 assert(VTOp0 == Op1.getSimpleValueType() &&
14158 "Expected operands with same type!");
14159 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14160 "Invalid number of packed elements for source and destination!");
14162 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14163 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14164 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14165 // legalizer firstly checks if the first operand in input to the setcc has
14166 // a legal type. If so, then it promotes the return type to that same type.
14167 // Otherwise, the return type is promoted to the 'next legal type' which,
14168 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14170 // We reach this code only if the following two conditions are met:
14171 // 1. Both return type and operand type have been promoted to wider types
14172 // by the type legalizer.
14173 // 2. The original operand type has been promoted to a 256-bit vector.
14175 // Note that condition 2. only applies for AVX targets.
14176 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14177 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14180 // The non-AVX512 code below works under the assumption that source and
14181 // destination types are the same.
14182 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14183 "Value types for source and destination must be the same!");
14185 // Break 256-bit integer vector compare into smaller ones.
14186 if (VT.is256BitVector() && !Subtarget->hasInt256())
14187 return Lower256IntVSETCC(Op, DAG);
14189 EVT OpVT = Op1.getValueType();
14190 if (OpVT.getVectorElementType() == MVT::i1)
14191 return LowerBoolVSETCC_AVX512(Op, DAG);
14193 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14194 if (Subtarget->hasAVX512()) {
14195 if (Op1.getValueType().is512BitVector() ||
14196 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14197 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14198 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14200 // In AVX-512 architecture setcc returns mask with i1 elements,
14201 // But there is no compare instruction for i8 and i16 elements in KNL.
14202 // We are not talking about 512-bit operands in this case, these
14203 // types are illegal.
14205 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14206 OpVT.getVectorElementType().getSizeInBits() >= 8))
14207 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14208 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14211 // Lower using XOP integer comparisons.
14212 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14213 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14214 // Translate compare code to XOP PCOM compare mode.
14215 unsigned CmpMode = 0;
14216 switch (SetCCOpcode) {
14217 default: llvm_unreachable("Unexpected SETCC condition");
14219 case ISD::SETLT: CmpMode = 0x00; break;
14221 case ISD::SETLE: CmpMode = 0x01; break;
14223 case ISD::SETGT: CmpMode = 0x02; break;
14225 case ISD::SETGE: CmpMode = 0x03; break;
14226 case ISD::SETEQ: CmpMode = 0x04; break;
14227 case ISD::SETNE: CmpMode = 0x05; break;
14230 // Are we comparing unsigned or signed integers?
14231 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14232 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14234 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14235 DAG.getConstant(CmpMode, dl, MVT::i8));
14238 // We are handling one of the integer comparisons here. Since SSE only has
14239 // GT and EQ comparisons for integer, swapping operands and multiple
14240 // operations may be required for some comparisons.
14242 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14243 bool Subus = false;
14245 switch (SetCCOpcode) {
14246 default: llvm_unreachable("Unexpected SETCC condition");
14247 case ISD::SETNE: Invert = true;
14248 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14249 case ISD::SETLT: Swap = true;
14250 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14251 case ISD::SETGE: Swap = true;
14252 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14253 Invert = true; break;
14254 case ISD::SETULT: Swap = true;
14255 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14256 FlipSigns = true; break;
14257 case ISD::SETUGE: Swap = true;
14258 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14259 FlipSigns = true; Invert = true; break;
14262 // Special case: Use min/max operations for SETULE/SETUGE
14263 MVT VET = VT.getVectorElementType();
14265 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14266 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14269 switch (SetCCOpcode) {
14271 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14272 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14275 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14278 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14279 if (!MinMax && hasSubus) {
14280 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14282 // t = psubus Op0, Op1
14283 // pcmpeq t, <0..0>
14284 switch (SetCCOpcode) {
14286 case ISD::SETULT: {
14287 // If the comparison is against a constant we can turn this into a
14288 // setule. With psubus, setule does not require a swap. This is
14289 // beneficial because the constant in the register is no longer
14290 // destructed as the destination so it can be hoisted out of a loop.
14291 // Only do this pre-AVX since vpcmp* is no longer destructive.
14292 if (Subtarget->hasAVX())
14294 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14295 if (ULEOp1.getNode()) {
14297 Subus = true; Invert = false; Swap = false;
14301 // Psubus is better than flip-sign because it requires no inversion.
14302 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14303 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14307 Opc = X86ISD::SUBUS;
14313 std::swap(Op0, Op1);
14315 // Check that the operation in question is available (most are plain SSE2,
14316 // but PCMPGTQ and PCMPEQQ have different requirements).
14317 if (VT == MVT::v2i64) {
14318 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14319 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14321 // First cast everything to the right type.
14322 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14323 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14325 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14326 // bits of the inputs before performing those operations. The lower
14327 // compare is always unsigned.
14330 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14332 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14333 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14334 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14335 Sign, Zero, Sign, Zero);
14337 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14338 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14340 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14341 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14342 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14344 // Create masks for only the low parts/high parts of the 64 bit integers.
14345 static const int MaskHi[] = { 1, 1, 3, 3 };
14346 static const int MaskLo[] = { 0, 0, 2, 2 };
14347 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14348 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14349 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14351 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14352 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14355 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14357 return DAG.getBitcast(VT, Result);
14360 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14361 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14362 // pcmpeqd + pshufd + pand.
14363 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14365 // First cast everything to the right type.
14366 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14367 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14370 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14372 // Make sure the lower and upper halves are both all-ones.
14373 static const int Mask[] = { 1, 0, 3, 2 };
14374 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14375 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14378 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14380 return DAG.getBitcast(VT, Result);
14384 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14385 // bits of the inputs before performing those operations.
14387 EVT EltVT = VT.getVectorElementType();
14388 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14390 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14391 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14394 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14396 // If the logical-not of the result is required, perform that now.
14398 Result = DAG.getNOT(dl, Result, VT);
14401 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14404 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14405 getZeroVector(VT, Subtarget, DAG, dl));
14410 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14412 MVT VT = Op.getSimpleValueType();
14414 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14416 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14417 && "SetCC type must be 8-bit or 1-bit integer");
14418 SDValue Op0 = Op.getOperand(0);
14419 SDValue Op1 = Op.getOperand(1);
14421 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14423 // Optimize to BT if possible.
14424 // Lower (X & (1 << N)) == 0 to BT(X, N).
14425 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14426 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14427 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14428 Op1.getOpcode() == ISD::Constant &&
14429 cast<ConstantSDNode>(Op1)->isNullValue() &&
14430 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14431 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14432 if (NewSetCC.getNode()) {
14434 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14439 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14441 if (Op1.getOpcode() == ISD::Constant &&
14442 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14443 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14444 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14446 // If the input is a setcc, then reuse the input setcc or use a new one with
14447 // the inverted condition.
14448 if (Op0.getOpcode() == X86ISD::SETCC) {
14449 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14450 bool Invert = (CC == ISD::SETNE) ^
14451 cast<ConstantSDNode>(Op1)->isNullValue();
14455 CCode = X86::GetOppositeBranchCondition(CCode);
14456 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14457 DAG.getConstant(CCode, dl, MVT::i8),
14458 Op0.getOperand(1));
14460 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14464 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14465 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14466 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14468 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14469 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14472 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14473 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14474 if (X86CC == X86::COND_INVALID)
14477 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14478 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14479 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14480 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14482 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14486 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14487 static bool isX86LogicalCmp(SDValue Op) {
14488 unsigned Opc = Op.getNode()->getOpcode();
14489 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14490 Opc == X86ISD::SAHF)
14492 if (Op.getResNo() == 1 &&
14493 (Opc == X86ISD::ADD ||
14494 Opc == X86ISD::SUB ||
14495 Opc == X86ISD::ADC ||
14496 Opc == X86ISD::SBB ||
14497 Opc == X86ISD::SMUL ||
14498 Opc == X86ISD::UMUL ||
14499 Opc == X86ISD::INC ||
14500 Opc == X86ISD::DEC ||
14501 Opc == X86ISD::OR ||
14502 Opc == X86ISD::XOR ||
14503 Opc == X86ISD::AND))
14506 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14512 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14513 if (V.getOpcode() != ISD::TRUNCATE)
14516 SDValue VOp0 = V.getOperand(0);
14517 unsigned InBits = VOp0.getValueSizeInBits();
14518 unsigned Bits = V.getValueSizeInBits();
14519 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14522 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14523 bool addTest = true;
14524 SDValue Cond = Op.getOperand(0);
14525 SDValue Op1 = Op.getOperand(1);
14526 SDValue Op2 = Op.getOperand(2);
14528 EVT VT = Op1.getValueType();
14531 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14532 // are available or VBLENDV if AVX is available.
14533 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14534 if (Cond.getOpcode() == ISD::SETCC &&
14535 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14536 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14537 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14538 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14539 int SSECC = translateX86FSETCC(
14540 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14543 if (Subtarget->hasAVX512()) {
14544 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14545 DAG.getConstant(SSECC, DL, MVT::i8));
14546 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14549 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14550 DAG.getConstant(SSECC, DL, MVT::i8));
14552 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14553 // of 3 logic instructions for size savings and potentially speed.
14554 // Unfortunately, there is no scalar form of VBLENDV.
14556 // If either operand is a constant, don't try this. We can expect to
14557 // optimize away at least one of the logic instructions later in that
14558 // case, so that sequence would be faster than a variable blend.
14560 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14561 // uses XMM0 as the selection register. That may need just as many
14562 // instructions as the AND/ANDN/OR sequence due to register moves, so
14565 if (Subtarget->hasAVX() &&
14566 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14568 // Convert to vectors, do a VSELECT, and convert back to scalar.
14569 // All of the conversions should be optimized away.
14571 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14572 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14573 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14574 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14576 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14577 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14579 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14581 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14582 VSel, DAG.getIntPtrConstant(0, DL));
14584 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14585 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14586 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14590 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14592 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14593 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14594 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14595 Op1Scalar = Op1.getOperand(0);
14597 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14598 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14599 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14600 Op2Scalar = Op2.getOperand(0);
14601 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14602 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14603 Op1Scalar.getValueType(),
14604 Cond, Op1Scalar, Op2Scalar);
14605 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14606 return DAG.getBitcast(VT, newSelect);
14607 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14608 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14609 DAG.getIntPtrConstant(0, DL));
14613 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14614 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14615 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14616 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14617 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14618 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14619 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14621 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14624 if (Cond.getOpcode() == ISD::SETCC) {
14625 SDValue NewCond = LowerSETCC(Cond, DAG);
14626 if (NewCond.getNode())
14630 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14631 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14632 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14633 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14634 if (Cond.getOpcode() == X86ISD::SETCC &&
14635 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14636 isZero(Cond.getOperand(1).getOperand(1))) {
14637 SDValue Cmp = Cond.getOperand(1);
14639 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14641 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14642 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14643 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14645 SDValue CmpOp0 = Cmp.getOperand(0);
14646 // Apply further optimizations for special cases
14647 // (select (x != 0), -1, 0) -> neg & sbb
14648 // (select (x == 0), 0, -1) -> neg & sbb
14649 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14650 if (YC->isNullValue() &&
14651 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14652 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14653 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14654 DAG.getConstant(0, DL,
14655 CmpOp0.getValueType()),
14657 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14658 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14659 SDValue(Neg.getNode(), 1));
14663 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14664 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14665 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14667 SDValue Res = // Res = 0 or -1.
14668 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14669 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14671 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14672 Res = DAG.getNOT(DL, Res, Res.getValueType());
14674 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14675 if (!N2C || !N2C->isNullValue())
14676 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14681 // Look past (and (setcc_carry (cmp ...)), 1).
14682 if (Cond.getOpcode() == ISD::AND &&
14683 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14684 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14685 if (C && C->getAPIntValue() == 1)
14686 Cond = Cond.getOperand(0);
14689 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14690 // setting operand in place of the X86ISD::SETCC.
14691 unsigned CondOpcode = Cond.getOpcode();
14692 if (CondOpcode == X86ISD::SETCC ||
14693 CondOpcode == X86ISD::SETCC_CARRY) {
14694 CC = Cond.getOperand(0);
14696 SDValue Cmp = Cond.getOperand(1);
14697 unsigned Opc = Cmp.getOpcode();
14698 MVT VT = Op.getSimpleValueType();
14700 bool IllegalFPCMov = false;
14701 if (VT.isFloatingPoint() && !VT.isVector() &&
14702 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14703 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14705 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14706 Opc == X86ISD::BT) { // FIXME
14710 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14711 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14712 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14713 Cond.getOperand(0).getValueType() != MVT::i8)) {
14714 SDValue LHS = Cond.getOperand(0);
14715 SDValue RHS = Cond.getOperand(1);
14716 unsigned X86Opcode;
14719 switch (CondOpcode) {
14720 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14721 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14722 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14723 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14724 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14725 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14726 default: llvm_unreachable("unexpected overflowing operator");
14728 if (CondOpcode == ISD::UMULO)
14729 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14732 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14734 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14736 if (CondOpcode == ISD::UMULO)
14737 Cond = X86Op.getValue(2);
14739 Cond = X86Op.getValue(1);
14741 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14746 // Look past the truncate if the high bits are known zero.
14747 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14748 Cond = Cond.getOperand(0);
14750 // We know the result of AND is compared against zero. Try to match
14752 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14753 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14754 if (NewSetCC.getNode()) {
14755 CC = NewSetCC.getOperand(0);
14756 Cond = NewSetCC.getOperand(1);
14763 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14764 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14767 // a < b ? -1 : 0 -> RES = ~setcc_carry
14768 // a < b ? 0 : -1 -> RES = setcc_carry
14769 // a >= b ? -1 : 0 -> RES = setcc_carry
14770 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14771 if (Cond.getOpcode() == X86ISD::SUB) {
14772 Cond = ConvertCmpIfNecessary(Cond, DAG);
14773 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14775 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14776 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14777 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14778 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14780 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14781 return DAG.getNOT(DL, Res, Res.getValueType());
14786 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14787 // widen the cmov and push the truncate through. This avoids introducing a new
14788 // branch during isel and doesn't add any extensions.
14789 if (Op.getValueType() == MVT::i8 &&
14790 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14791 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14792 if (T1.getValueType() == T2.getValueType() &&
14793 // Blacklist CopyFromReg to avoid partial register stalls.
14794 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14795 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14796 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14797 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14801 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14802 // condition is true.
14803 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14804 SDValue Ops[] = { Op2, Op1, CC, Cond };
14805 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14808 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14809 const X86Subtarget *Subtarget,
14810 SelectionDAG &DAG) {
14811 MVT VT = Op->getSimpleValueType(0);
14812 SDValue In = Op->getOperand(0);
14813 MVT InVT = In.getSimpleValueType();
14814 MVT VTElt = VT.getVectorElementType();
14815 MVT InVTElt = InVT.getVectorElementType();
14819 if ((InVTElt == MVT::i1) &&
14820 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14821 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14823 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14824 VTElt.getSizeInBits() <= 16)) ||
14826 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14827 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14829 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14830 VTElt.getSizeInBits() >= 32))))
14831 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14833 unsigned int NumElts = VT.getVectorNumElements();
14835 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14838 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14839 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14840 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14841 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14844 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14845 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14847 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14850 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14852 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14853 if (VT.is512BitVector())
14855 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14858 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14859 const X86Subtarget *Subtarget,
14860 SelectionDAG &DAG) {
14861 SDValue In = Op->getOperand(0);
14862 MVT VT = Op->getSimpleValueType(0);
14863 MVT InVT = In.getSimpleValueType();
14864 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14866 MVT InSVT = InVT.getScalarType();
14867 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14869 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14871 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14876 // SSE41 targets can use the pmovsx* instructions directly.
14877 if (Subtarget->hasSSE41())
14878 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14880 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14884 // As SRAI is only available on i16/i32 types, we expand only up to i32
14885 // and handle i64 separately.
14886 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14887 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14888 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14889 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14890 Curr = DAG.getBitcast(CurrVT, Curr);
14893 SDValue SignExt = Curr;
14894 if (CurrVT != InVT) {
14895 unsigned SignExtShift =
14896 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14897 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14898 DAG.getConstant(SignExtShift, dl, MVT::i8));
14904 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14905 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14906 DAG.getConstant(31, dl, MVT::i8));
14907 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14908 return DAG.getBitcast(VT, Ext);
14914 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14915 SelectionDAG &DAG) {
14916 MVT VT = Op->getSimpleValueType(0);
14917 SDValue In = Op->getOperand(0);
14918 MVT InVT = In.getSimpleValueType();
14921 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14922 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14924 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14925 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14926 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14929 if (Subtarget->hasInt256())
14930 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14932 // Optimize vectors in AVX mode
14933 // Sign extend v8i16 to v8i32 and
14936 // Divide input vector into two parts
14937 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14938 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14939 // concat the vectors to original VT
14941 unsigned NumElems = InVT.getVectorNumElements();
14942 SDValue Undef = DAG.getUNDEF(InVT);
14944 SmallVector<int,8> ShufMask1(NumElems, -1);
14945 for (unsigned i = 0; i != NumElems/2; ++i)
14948 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14950 SmallVector<int,8> ShufMask2(NumElems, -1);
14951 for (unsigned i = 0; i != NumElems/2; ++i)
14952 ShufMask2[i] = i + NumElems/2;
14954 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14956 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14957 VT.getVectorNumElements()/2);
14959 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14960 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14962 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14965 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14966 // may emit an illegal shuffle but the expansion is still better than scalar
14967 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14968 // we'll emit a shuffle and a arithmetic shift.
14969 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14970 // TODO: It is possible to support ZExt by zeroing the undef values during
14971 // the shuffle phase or after the shuffle.
14972 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14973 SelectionDAG &DAG) {
14974 MVT RegVT = Op.getSimpleValueType();
14975 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14976 assert(RegVT.isInteger() &&
14977 "We only custom lower integer vector sext loads.");
14979 // Nothing useful we can do without SSE2 shuffles.
14980 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14982 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14984 EVT MemVT = Ld->getMemoryVT();
14985 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14986 unsigned RegSz = RegVT.getSizeInBits();
14988 ISD::LoadExtType Ext = Ld->getExtensionType();
14990 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14991 && "Only anyext and sext are currently implemented.");
14992 assert(MemVT != RegVT && "Cannot extend to the same type");
14993 assert(MemVT.isVector() && "Must load a vector from memory");
14995 unsigned NumElems = RegVT.getVectorNumElements();
14996 unsigned MemSz = MemVT.getSizeInBits();
14997 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14999 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15000 // The only way in which we have a legal 256-bit vector result but not the
15001 // integer 256-bit operations needed to directly lower a sextload is if we
15002 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15003 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15004 // correctly legalized. We do this late to allow the canonical form of
15005 // sextload to persist throughout the rest of the DAG combiner -- it wants
15006 // to fold together any extensions it can, and so will fuse a sign_extend
15007 // of an sextload into a sextload targeting a wider value.
15009 if (MemSz == 128) {
15010 // Just switch this to a normal load.
15011 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15012 "it must be a legal 128-bit vector "
15014 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15015 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15016 Ld->isInvariant(), Ld->getAlignment());
15018 assert(MemSz < 128 &&
15019 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15020 // Do an sext load to a 128-bit vector type. We want to use the same
15021 // number of elements, but elements half as wide. This will end up being
15022 // recursively lowered by this routine, but will succeed as we definitely
15023 // have all the necessary features if we're using AVX1.
15025 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15026 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15028 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15029 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15030 Ld->isNonTemporal(), Ld->isInvariant(),
15031 Ld->getAlignment());
15034 // Replace chain users with the new chain.
15035 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15036 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15038 // Finally, do a normal sign-extend to the desired register.
15039 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15042 // All sizes must be a power of two.
15043 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15044 "Non-power-of-two elements are not custom lowered!");
15046 // Attempt to load the original value using scalar loads.
15047 // Find the largest scalar type that divides the total loaded size.
15048 MVT SclrLoadTy = MVT::i8;
15049 for (MVT Tp : MVT::integer_valuetypes()) {
15050 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15055 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15056 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15058 SclrLoadTy = MVT::f64;
15060 // Calculate the number of scalar loads that we need to perform
15061 // in order to load our vector from memory.
15062 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15064 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15065 "Can only lower sext loads with a single scalar load!");
15067 unsigned loadRegZize = RegSz;
15068 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15071 // Represent our vector as a sequence of elements which are the
15072 // largest scalar that we can load.
15073 EVT LoadUnitVecVT = EVT::getVectorVT(
15074 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15076 // Represent the data using the same element type that is stored in
15077 // memory. In practice, we ''widen'' MemVT.
15079 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15080 loadRegZize / MemVT.getScalarType().getSizeInBits());
15082 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15083 "Invalid vector type");
15085 // We can't shuffle using an illegal type.
15086 assert(TLI.isTypeLegal(WideVecVT) &&
15087 "We only lower types that form legal widened vector types");
15089 SmallVector<SDValue, 8> Chains;
15090 SDValue Ptr = Ld->getBasePtr();
15091 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15092 TLI.getPointerTy(DAG.getDataLayout()));
15093 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15095 for (unsigned i = 0; i < NumLoads; ++i) {
15096 // Perform a single load.
15097 SDValue ScalarLoad =
15098 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15099 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15100 Ld->getAlignment());
15101 Chains.push_back(ScalarLoad.getValue(1));
15102 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15103 // another round of DAGCombining.
15105 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15107 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15108 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15110 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15113 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15115 // Bitcast the loaded value to a vector of the original element type, in
15116 // the size of the target vector type.
15117 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15118 unsigned SizeRatio = RegSz / MemSz;
15120 if (Ext == ISD::SEXTLOAD) {
15121 // If we have SSE4.1, we can directly emit a VSEXT node.
15122 if (Subtarget->hasSSE41()) {
15123 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15124 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15128 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15130 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15131 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15133 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15134 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15138 // Redistribute the loaded elements into the different locations.
15139 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15140 for (unsigned i = 0; i != NumElems; ++i)
15141 ShuffleVec[i * SizeRatio] = i;
15143 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15144 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15146 // Bitcast to the requested type.
15147 Shuff = DAG.getBitcast(RegVT, Shuff);
15148 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15152 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15153 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15154 // from the AND / OR.
15155 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15156 Opc = Op.getOpcode();
15157 if (Opc != ISD::OR && Opc != ISD::AND)
15159 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15160 Op.getOperand(0).hasOneUse() &&
15161 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15162 Op.getOperand(1).hasOneUse());
15165 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15166 // 1 and that the SETCC node has a single use.
15167 static bool isXor1OfSetCC(SDValue Op) {
15168 if (Op.getOpcode() != ISD::XOR)
15170 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15171 if (N1C && N1C->getAPIntValue() == 1) {
15172 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15173 Op.getOperand(0).hasOneUse();
15178 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15179 bool addTest = true;
15180 SDValue Chain = Op.getOperand(0);
15181 SDValue Cond = Op.getOperand(1);
15182 SDValue Dest = Op.getOperand(2);
15185 bool Inverted = false;
15187 if (Cond.getOpcode() == ISD::SETCC) {
15188 // Check for setcc([su]{add,sub,mul}o == 0).
15189 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15190 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15191 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15192 Cond.getOperand(0).getResNo() == 1 &&
15193 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15194 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15195 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15196 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15197 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15198 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15200 Cond = Cond.getOperand(0);
15202 SDValue NewCond = LowerSETCC(Cond, DAG);
15203 if (NewCond.getNode())
15208 // FIXME: LowerXALUO doesn't handle these!!
15209 else if (Cond.getOpcode() == X86ISD::ADD ||
15210 Cond.getOpcode() == X86ISD::SUB ||
15211 Cond.getOpcode() == X86ISD::SMUL ||
15212 Cond.getOpcode() == X86ISD::UMUL)
15213 Cond = LowerXALUO(Cond, DAG);
15216 // Look pass (and (setcc_carry (cmp ...)), 1).
15217 if (Cond.getOpcode() == ISD::AND &&
15218 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15219 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15220 if (C && C->getAPIntValue() == 1)
15221 Cond = Cond.getOperand(0);
15224 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15225 // setting operand in place of the X86ISD::SETCC.
15226 unsigned CondOpcode = Cond.getOpcode();
15227 if (CondOpcode == X86ISD::SETCC ||
15228 CondOpcode == X86ISD::SETCC_CARRY) {
15229 CC = Cond.getOperand(0);
15231 SDValue Cmp = Cond.getOperand(1);
15232 unsigned Opc = Cmp.getOpcode();
15233 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15234 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15238 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15242 // These can only come from an arithmetic instruction with overflow,
15243 // e.g. SADDO, UADDO.
15244 Cond = Cond.getNode()->getOperand(1);
15250 CondOpcode = Cond.getOpcode();
15251 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15252 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15253 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15254 Cond.getOperand(0).getValueType() != MVT::i8)) {
15255 SDValue LHS = Cond.getOperand(0);
15256 SDValue RHS = Cond.getOperand(1);
15257 unsigned X86Opcode;
15260 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15261 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15263 switch (CondOpcode) {
15264 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15266 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15268 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15271 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15272 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15274 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15276 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15279 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15280 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15281 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15282 default: llvm_unreachable("unexpected overflowing operator");
15285 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15286 if (CondOpcode == ISD::UMULO)
15287 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15290 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15292 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15294 if (CondOpcode == ISD::UMULO)
15295 Cond = X86Op.getValue(2);
15297 Cond = X86Op.getValue(1);
15299 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15303 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15304 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15305 if (CondOpc == ISD::OR) {
15306 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15307 // two branches instead of an explicit OR instruction with a
15309 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15310 isX86LogicalCmp(Cmp)) {
15311 CC = Cond.getOperand(0).getOperand(0);
15312 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15313 Chain, Dest, CC, Cmp);
15314 CC = Cond.getOperand(1).getOperand(0);
15318 } else { // ISD::AND
15319 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15320 // two branches instead of an explicit AND instruction with a
15321 // separate test. However, we only do this if this block doesn't
15322 // have a fall-through edge, because this requires an explicit
15323 // jmp when the condition is false.
15324 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15325 isX86LogicalCmp(Cmp) &&
15326 Op.getNode()->hasOneUse()) {
15327 X86::CondCode CCode =
15328 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15329 CCode = X86::GetOppositeBranchCondition(CCode);
15330 CC = DAG.getConstant(CCode, dl, MVT::i8);
15331 SDNode *User = *Op.getNode()->use_begin();
15332 // Look for an unconditional branch following this conditional branch.
15333 // We need this because we need to reverse the successors in order
15334 // to implement FCMP_OEQ.
15335 if (User->getOpcode() == ISD::BR) {
15336 SDValue FalseBB = User->getOperand(1);
15338 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15339 assert(NewBR == User);
15343 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15344 Chain, Dest, CC, Cmp);
15345 X86::CondCode CCode =
15346 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15347 CCode = X86::GetOppositeBranchCondition(CCode);
15348 CC = DAG.getConstant(CCode, dl, MVT::i8);
15354 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15355 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15356 // It should be transformed during dag combiner except when the condition
15357 // is set by a arithmetics with overflow node.
15358 X86::CondCode CCode =
15359 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15360 CCode = X86::GetOppositeBranchCondition(CCode);
15361 CC = DAG.getConstant(CCode, dl, MVT::i8);
15362 Cond = Cond.getOperand(0).getOperand(1);
15364 } else if (Cond.getOpcode() == ISD::SETCC &&
15365 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15366 // For FCMP_OEQ, we can emit
15367 // two branches instead of an explicit AND instruction with a
15368 // separate test. However, we only do this if this block doesn't
15369 // have a fall-through edge, because this requires an explicit
15370 // jmp when the condition is false.
15371 if (Op.getNode()->hasOneUse()) {
15372 SDNode *User = *Op.getNode()->use_begin();
15373 // Look for an unconditional branch following this conditional branch.
15374 // We need this because we need to reverse the successors in order
15375 // to implement FCMP_OEQ.
15376 if (User->getOpcode() == ISD::BR) {
15377 SDValue FalseBB = User->getOperand(1);
15379 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15380 assert(NewBR == User);
15384 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15385 Cond.getOperand(0), Cond.getOperand(1));
15386 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15387 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15388 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15389 Chain, Dest, CC, Cmp);
15390 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15395 } else if (Cond.getOpcode() == ISD::SETCC &&
15396 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15397 // For FCMP_UNE, we can emit
15398 // two branches instead of an explicit AND instruction with a
15399 // separate test. However, we only do this if this block doesn't
15400 // have a fall-through edge, because this requires an explicit
15401 // jmp when the condition is false.
15402 if (Op.getNode()->hasOneUse()) {
15403 SDNode *User = *Op.getNode()->use_begin();
15404 // Look for an unconditional branch following this conditional branch.
15405 // We need this because we need to reverse the successors in order
15406 // to implement FCMP_UNE.
15407 if (User->getOpcode() == ISD::BR) {
15408 SDValue FalseBB = User->getOperand(1);
15410 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15411 assert(NewBR == User);
15414 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15415 Cond.getOperand(0), Cond.getOperand(1));
15416 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15417 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15418 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15419 Chain, Dest, CC, Cmp);
15420 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15430 // Look pass the truncate if the high bits are known zero.
15431 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15432 Cond = Cond.getOperand(0);
15434 // We know the result of AND is compared against zero. Try to match
15436 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15437 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15438 if (NewSetCC.getNode()) {
15439 CC = NewSetCC.getOperand(0);
15440 Cond = NewSetCC.getOperand(1);
15447 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15448 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15449 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15451 Cond = ConvertCmpIfNecessary(Cond, DAG);
15452 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15453 Chain, Dest, CC, Cond);
15456 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15457 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15458 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15459 // that the guard pages used by the OS virtual memory manager are allocated in
15460 // correct sequence.
15462 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15463 SelectionDAG &DAG) const {
15464 MachineFunction &MF = DAG.getMachineFunction();
15465 bool SplitStack = MF.shouldSplitStack();
15466 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15471 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15472 SDNode* Node = Op.getNode();
15474 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15475 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15476 " not tell us which reg is the stack pointer!");
15477 EVT VT = Node->getValueType(0);
15478 SDValue Tmp1 = SDValue(Node, 0);
15479 SDValue Tmp2 = SDValue(Node, 1);
15480 SDValue Tmp3 = Node->getOperand(2);
15481 SDValue Chain = Tmp1.getOperand(0);
15483 // Chain the dynamic stack allocation so that it doesn't modify the stack
15484 // pointer when other instructions are using the stack.
15485 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15488 SDValue Size = Tmp2.getOperand(1);
15489 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15490 Chain = SP.getValue(1);
15491 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15492 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15493 unsigned StackAlign = TFI.getStackAlignment();
15494 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15495 if (Align > StackAlign)
15496 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15497 DAG.getConstant(-(uint64_t)Align, dl, VT));
15498 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15500 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15501 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15504 SDValue Ops[2] = { Tmp1, Tmp2 };
15505 return DAG.getMergeValues(Ops, dl);
15509 SDValue Chain = Op.getOperand(0);
15510 SDValue Size = Op.getOperand(1);
15511 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15512 EVT VT = Op.getNode()->getValueType(0);
15514 bool Is64Bit = Subtarget->is64Bit();
15515 MVT SPTy = getPointerTy(DAG.getDataLayout());
15518 MachineRegisterInfo &MRI = MF.getRegInfo();
15521 // The 64 bit implementation of segmented stacks needs to clobber both r10
15522 // r11. This makes it impossible to use it along with nested parameters.
15523 const Function *F = MF.getFunction();
15525 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15527 if (I->hasNestAttr())
15528 report_fatal_error("Cannot use segmented stacks with functions that "
15529 "have nested arguments.");
15532 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15533 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15534 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15535 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15536 DAG.getRegister(Vreg, SPTy));
15537 SDValue Ops1[2] = { Value, Chain };
15538 return DAG.getMergeValues(Ops1, dl);
15541 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15543 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15544 Flag = Chain.getValue(1);
15545 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15547 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15549 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15550 unsigned SPReg = RegInfo->getStackRegister();
15551 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15552 Chain = SP.getValue(1);
15555 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15556 DAG.getConstant(-(uint64_t)Align, dl, VT));
15557 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15560 SDValue Ops1[2] = { SP, Chain };
15561 return DAG.getMergeValues(Ops1, dl);
15565 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15566 MachineFunction &MF = DAG.getMachineFunction();
15567 auto PtrVT = getPointerTy(MF.getDataLayout());
15568 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15570 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15573 if (!Subtarget->is64Bit() ||
15574 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15575 // vastart just stores the address of the VarArgsFrameIndex slot into the
15576 // memory location argument.
15577 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15578 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15579 MachinePointerInfo(SV), false, false, 0);
15583 // gp_offset (0 - 6 * 8)
15584 // fp_offset (48 - 48 + 8 * 16)
15585 // overflow_arg_area (point to parameters coming in memory).
15587 SmallVector<SDValue, 8> MemOps;
15588 SDValue FIN = Op.getOperand(1);
15590 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15591 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15593 FIN, MachinePointerInfo(SV), false, false, 0);
15594 MemOps.push_back(Store);
15597 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15598 Store = DAG.getStore(Op.getOperand(0), DL,
15599 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15601 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15602 MemOps.push_back(Store);
15604 // Store ptr to overflow_arg_area
15605 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15606 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15607 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15608 MachinePointerInfo(SV, 8),
15610 MemOps.push_back(Store);
15612 // Store ptr to reg_save_area.
15613 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15614 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15615 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15616 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15617 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15618 MemOps.push_back(Store);
15619 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15622 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15623 assert(Subtarget->is64Bit() &&
15624 "LowerVAARG only handles 64-bit va_arg!");
15625 assert(Op.getNode()->getNumOperands() == 4);
15627 MachineFunction &MF = DAG.getMachineFunction();
15628 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15629 // The Win64 ABI uses char* instead of a structure.
15630 return DAG.expandVAArg(Op.getNode());
15632 SDValue Chain = Op.getOperand(0);
15633 SDValue SrcPtr = Op.getOperand(1);
15634 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15635 unsigned Align = Op.getConstantOperandVal(3);
15638 EVT ArgVT = Op.getNode()->getValueType(0);
15639 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15640 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15643 // Decide which area this value should be read from.
15644 // TODO: Implement the AMD64 ABI in its entirety. This simple
15645 // selection mechanism works only for the basic types.
15646 if (ArgVT == MVT::f80) {
15647 llvm_unreachable("va_arg for f80 not yet implemented");
15648 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15649 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15650 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15651 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15653 llvm_unreachable("Unhandled argument type in LowerVAARG");
15656 if (ArgMode == 2) {
15657 // Sanity Check: Make sure using fp_offset makes sense.
15658 assert(!Subtarget->useSoftFloat() &&
15659 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15660 Subtarget->hasSSE1());
15663 // Insert VAARG_64 node into the DAG
15664 // VAARG_64 returns two values: Variable Argument Address, Chain
15665 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15666 DAG.getConstant(ArgMode, dl, MVT::i8),
15667 DAG.getConstant(Align, dl, MVT::i32)};
15668 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15669 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15670 VTs, InstOps, MVT::i64,
15671 MachinePointerInfo(SV),
15673 /*Volatile=*/false,
15675 /*WriteMem=*/true);
15676 Chain = VAARG.getValue(1);
15678 // Load the next argument and return it
15679 return DAG.getLoad(ArgVT, dl,
15682 MachinePointerInfo(),
15683 false, false, false, 0);
15686 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15687 SelectionDAG &DAG) {
15688 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15689 // where a va_list is still an i8*.
15690 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15691 if (Subtarget->isCallingConvWin64(
15692 DAG.getMachineFunction().getFunction()->getCallingConv()))
15693 // Probably a Win64 va_copy.
15694 return DAG.expandVACopy(Op.getNode());
15696 SDValue Chain = Op.getOperand(0);
15697 SDValue DstPtr = Op.getOperand(1);
15698 SDValue SrcPtr = Op.getOperand(2);
15699 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15700 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15703 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15704 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15706 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15709 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15710 // amount is a constant. Takes immediate version of shift as input.
15711 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15712 SDValue SrcOp, uint64_t ShiftAmt,
15713 SelectionDAG &DAG) {
15714 MVT ElementType = VT.getVectorElementType();
15716 // Fold this packed shift into its first operand if ShiftAmt is 0.
15720 // Check for ShiftAmt >= element width
15721 if (ShiftAmt >= ElementType.getSizeInBits()) {
15722 if (Opc == X86ISD::VSRAI)
15723 ShiftAmt = ElementType.getSizeInBits() - 1;
15725 return DAG.getConstant(0, dl, VT);
15728 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15729 && "Unknown target vector shift-by-constant node");
15731 // Fold this packed vector shift into a build vector if SrcOp is a
15732 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15733 if (VT == SrcOp.getSimpleValueType() &&
15734 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15735 SmallVector<SDValue, 8> Elts;
15736 unsigned NumElts = SrcOp->getNumOperands();
15737 ConstantSDNode *ND;
15740 default: llvm_unreachable(nullptr);
15741 case X86ISD::VSHLI:
15742 for (unsigned i=0; i!=NumElts; ++i) {
15743 SDValue CurrentOp = SrcOp->getOperand(i);
15744 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15745 Elts.push_back(CurrentOp);
15748 ND = cast<ConstantSDNode>(CurrentOp);
15749 const APInt &C = ND->getAPIntValue();
15750 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15753 case X86ISD::VSRLI:
15754 for (unsigned i=0; i!=NumElts; ++i) {
15755 SDValue CurrentOp = SrcOp->getOperand(i);
15756 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15757 Elts.push_back(CurrentOp);
15760 ND = cast<ConstantSDNode>(CurrentOp);
15761 const APInt &C = ND->getAPIntValue();
15762 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15765 case X86ISD::VSRAI:
15766 for (unsigned i=0; i!=NumElts; ++i) {
15767 SDValue CurrentOp = SrcOp->getOperand(i);
15768 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15769 Elts.push_back(CurrentOp);
15772 ND = cast<ConstantSDNode>(CurrentOp);
15773 const APInt &C = ND->getAPIntValue();
15774 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15779 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15782 return DAG.getNode(Opc, dl, VT, SrcOp,
15783 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15786 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15787 // may or may not be a constant. Takes immediate version of shift as input.
15788 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15789 SDValue SrcOp, SDValue ShAmt,
15790 SelectionDAG &DAG) {
15791 MVT SVT = ShAmt.getSimpleValueType();
15792 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15794 // Catch shift-by-constant.
15795 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15796 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15797 CShAmt->getZExtValue(), DAG);
15799 // Change opcode to non-immediate version
15801 default: llvm_unreachable("Unknown target vector shift node");
15802 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15803 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15804 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15807 const X86Subtarget &Subtarget =
15808 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15809 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15810 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15811 // Let the shuffle legalizer expand this shift amount node.
15812 SDValue Op0 = ShAmt.getOperand(0);
15813 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15814 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15816 // Need to build a vector containing shift amount.
15817 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15818 SmallVector<SDValue, 4> ShOps;
15819 ShOps.push_back(ShAmt);
15820 if (SVT == MVT::i32) {
15821 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15822 ShOps.push_back(DAG.getUNDEF(SVT));
15824 ShOps.push_back(DAG.getUNDEF(SVT));
15826 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15827 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15830 // The return type has to be a 128-bit type with the same element
15831 // type as the input type.
15832 MVT EltVT = VT.getVectorElementType();
15833 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15835 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15836 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15839 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15840 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15841 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15842 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15843 SDValue PreservedSrc,
15844 const X86Subtarget *Subtarget,
15845 SelectionDAG &DAG) {
15846 EVT VT = Op.getValueType();
15847 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15848 MVT::i1, VT.getVectorNumElements());
15849 SDValue VMask = SDValue();
15850 unsigned OpcodeSelect = ISD::VSELECT;
15853 assert(MaskVT.isSimple() && "invalid mask type");
15855 if (isAllOnes(Mask))
15858 if (MaskVT.bitsGT(Mask.getValueType())) {
15859 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15860 MaskVT.getSizeInBits());
15861 VMask = DAG.getBitcast(MaskVT,
15862 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15864 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15865 Mask.getValueType().getSizeInBits());
15866 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15867 // are extracted by EXTRACT_SUBVECTOR.
15868 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15869 DAG.getBitcast(BitcastVT, Mask),
15870 DAG.getIntPtrConstant(0, dl));
15873 switch (Op.getOpcode()) {
15875 case X86ISD::PCMPEQM:
15876 case X86ISD::PCMPGTM:
15878 case X86ISD::CMPMU:
15879 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15880 case X86ISD::VFPCLASS:
15881 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15882 case X86ISD::VTRUNC:
15883 case X86ISD::VTRUNCS:
15884 case X86ISD::VTRUNCUS:
15885 // We can't use ISD::VSELECT here because it is not always "Legal"
15886 // for the destination type. For example vpmovqb require only AVX512
15887 // and vselect that can operate on byte element type require BWI
15888 OpcodeSelect = X86ISD::SELECT;
15891 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15892 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15893 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15896 /// \brief Creates an SDNode for a predicated scalar operation.
15897 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15898 /// The mask is coming as MVT::i8 and it should be truncated
15899 /// to MVT::i1 while lowering masking intrinsics.
15900 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15901 /// "X86select" instead of "vselect". We just can't create the "vselect" node
15902 /// for a scalar instruction.
15903 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15904 SDValue PreservedSrc,
15905 const X86Subtarget *Subtarget,
15906 SelectionDAG &DAG) {
15907 if (isAllOnes(Mask))
15910 EVT VT = Op.getValueType();
15912 // The mask should be of type MVT::i1
15913 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15915 if (Op.getOpcode() == X86ISD::FSETCC)
15916 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
15918 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15919 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15920 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15923 static int getSEHRegistrationNodeSize(const Function *Fn) {
15924 if (!Fn->hasPersonalityFn())
15925 report_fatal_error(
15926 "querying registration node size for function without personality");
15927 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15928 // WinEHStatePass for the full struct definition.
15929 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15930 case EHPersonality::MSVC_X86SEH: return 24;
15931 case EHPersonality::MSVC_CXX: return 16;
15934 report_fatal_error("can only recover FP for MSVC EH personality functions");
15937 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15938 /// function or when returning to a parent frame after catching an exception, we
15939 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15940 /// Here's the math:
15941 /// RegNodeBase = EntryEBP - RegNodeSize
15942 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15943 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15944 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15945 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15946 SDValue EntryEBP) {
15947 MachineFunction &MF = DAG.getMachineFunction();
15950 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15951 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
15953 // It's possible that the parent function no longer has a personality function
15954 // if the exceptional code was optimized away, in which case we just return
15955 // the incoming EBP.
15956 if (!Fn->hasPersonalityFn())
15959 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
15961 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15963 MCSymbol *OffsetSym =
15964 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15965 GlobalValue::getRealLinkageName(Fn->getName()));
15966 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15967 SDValue RegNodeFrameOffset =
15968 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
15970 // RegNodeBase = EntryEBP - RegNodeSize
15971 // ParentFP = RegNodeBase - RegNodeFrameOffset
15972 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15973 DAG.getConstant(RegNodeSize, dl, PtrVT));
15974 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15977 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15978 SelectionDAG &DAG) {
15980 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15981 EVT VT = Op.getValueType();
15982 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15984 switch(IntrData->Type) {
15985 case INTR_TYPE_1OP:
15986 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15987 case INTR_TYPE_2OP:
15988 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15990 case INTR_TYPE_2OP_IMM8:
15991 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15992 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
15993 case INTR_TYPE_3OP:
15994 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15995 Op.getOperand(2), Op.getOperand(3));
15996 case INTR_TYPE_4OP:
15997 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15998 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
15999 case INTR_TYPE_1OP_MASK_RM: {
16000 SDValue Src = Op.getOperand(1);
16001 SDValue PassThru = Op.getOperand(2);
16002 SDValue Mask = Op.getOperand(3);
16003 SDValue RoundingMode;
16004 // We allways add rounding mode to the Node.
16005 // If the rounding mode is not specified, we add the
16006 // "current direction" mode.
16007 if (Op.getNumOperands() == 4)
16009 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16011 RoundingMode = Op.getOperand(4);
16012 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16013 if (IntrWithRoundingModeOpcode != 0)
16014 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16015 X86::STATIC_ROUNDING::CUR_DIRECTION)
16016 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16017 dl, Op.getValueType(), Src, RoundingMode),
16018 Mask, PassThru, Subtarget, DAG);
16019 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16021 Mask, PassThru, Subtarget, DAG);
16023 case INTR_TYPE_1OP_MASK: {
16024 SDValue Src = Op.getOperand(1);
16025 SDValue PassThru = Op.getOperand(2);
16026 SDValue Mask = Op.getOperand(3);
16027 // We add rounding mode to the Node when
16028 // - RM Opcode is specified and
16029 // - RM is not "current direction".
16030 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16031 if (IntrWithRoundingModeOpcode != 0) {
16032 SDValue Rnd = Op.getOperand(4);
16033 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16034 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16035 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16036 dl, Op.getValueType(),
16038 Mask, PassThru, Subtarget, DAG);
16041 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16042 Mask, PassThru, Subtarget, DAG);
16044 case INTR_TYPE_SCALAR_MASK: {
16045 SDValue Src1 = Op.getOperand(1);
16046 SDValue Src2 = Op.getOperand(2);
16047 SDValue passThru = Op.getOperand(3);
16048 SDValue Mask = Op.getOperand(4);
16049 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16050 Mask, passThru, Subtarget, DAG);
16052 case INTR_TYPE_SCALAR_MASK_RM: {
16053 SDValue Src1 = Op.getOperand(1);
16054 SDValue Src2 = Op.getOperand(2);
16055 SDValue Src0 = Op.getOperand(3);
16056 SDValue Mask = Op.getOperand(4);
16057 // There are 2 kinds of intrinsics in this group:
16058 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16059 // (2) With rounding mode and sae - 7 operands.
16060 if (Op.getNumOperands() == 6) {
16061 SDValue Sae = Op.getOperand(5);
16062 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16063 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16065 Mask, Src0, Subtarget, DAG);
16067 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16068 SDValue RoundingMode = Op.getOperand(5);
16069 SDValue Sae = Op.getOperand(6);
16070 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16071 RoundingMode, Sae),
16072 Mask, Src0, Subtarget, DAG);
16074 case INTR_TYPE_2OP_MASK:
16075 case INTR_TYPE_2OP_IMM8_MASK: {
16076 SDValue Src1 = Op.getOperand(1);
16077 SDValue Src2 = Op.getOperand(2);
16078 SDValue PassThru = Op.getOperand(3);
16079 SDValue Mask = Op.getOperand(4);
16081 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16082 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16084 // We specify 2 possible opcodes for intrinsics with rounding modes.
16085 // First, we check if the intrinsic may have non-default rounding mode,
16086 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16087 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16088 if (IntrWithRoundingModeOpcode != 0) {
16089 SDValue Rnd = Op.getOperand(5);
16090 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16091 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16092 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16093 dl, Op.getValueType(),
16095 Mask, PassThru, Subtarget, DAG);
16098 // TODO: Intrinsics should have fast-math-flags to propagate.
16099 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16100 Mask, PassThru, Subtarget, DAG);
16102 case INTR_TYPE_2OP_MASK_RM: {
16103 SDValue Src1 = Op.getOperand(1);
16104 SDValue Src2 = Op.getOperand(2);
16105 SDValue PassThru = Op.getOperand(3);
16106 SDValue Mask = Op.getOperand(4);
16107 // We specify 2 possible modes for intrinsics, with/without rounding
16109 // First, we check if the intrinsic have rounding mode (6 operands),
16110 // if not, we set rounding mode to "current".
16112 if (Op.getNumOperands() == 6)
16113 Rnd = Op.getOperand(5);
16115 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16116 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16118 Mask, PassThru, Subtarget, DAG);
16120 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16121 SDValue Src1 = Op.getOperand(1);
16122 SDValue Src2 = Op.getOperand(2);
16123 SDValue Src3 = Op.getOperand(3);
16124 SDValue PassThru = Op.getOperand(4);
16125 SDValue Mask = Op.getOperand(5);
16126 SDValue Sae = Op.getOperand(6);
16128 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16130 Mask, PassThru, Subtarget, DAG);
16132 case INTR_TYPE_3OP_MASK_RM: {
16133 SDValue Src1 = Op.getOperand(1);
16134 SDValue Src2 = Op.getOperand(2);
16135 SDValue Imm = Op.getOperand(3);
16136 SDValue PassThru = Op.getOperand(4);
16137 SDValue Mask = Op.getOperand(5);
16138 // We specify 2 possible modes for intrinsics, with/without rounding
16140 // First, we check if the intrinsic have rounding mode (7 operands),
16141 // if not, we set rounding mode to "current".
16143 if (Op.getNumOperands() == 7)
16144 Rnd = Op.getOperand(6);
16146 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16147 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16148 Src1, Src2, Imm, Rnd),
16149 Mask, PassThru, Subtarget, DAG);
16151 case INTR_TYPE_3OP_IMM8_MASK:
16152 case INTR_TYPE_3OP_MASK:
16153 case INSERT_SUBVEC: {
16154 SDValue Src1 = Op.getOperand(1);
16155 SDValue Src2 = Op.getOperand(2);
16156 SDValue Src3 = Op.getOperand(3);
16157 SDValue PassThru = Op.getOperand(4);
16158 SDValue Mask = Op.getOperand(5);
16160 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16161 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16162 else if (IntrData->Type == INSERT_SUBVEC) {
16163 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16164 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16165 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16166 Imm *= Src2.getValueType().getVectorNumElements();
16167 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16170 // We specify 2 possible opcodes for intrinsics with rounding modes.
16171 // First, we check if the intrinsic may have non-default rounding mode,
16172 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16173 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16174 if (IntrWithRoundingModeOpcode != 0) {
16175 SDValue Rnd = Op.getOperand(6);
16176 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16177 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16178 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16179 dl, Op.getValueType(),
16180 Src1, Src2, Src3, Rnd),
16181 Mask, PassThru, Subtarget, DAG);
16184 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16186 Mask, PassThru, Subtarget, DAG);
16188 case VPERM_3OP_MASKZ:
16189 case VPERM_3OP_MASK:
16192 case FMA_OP_MASK: {
16193 SDValue Src1 = Op.getOperand(1);
16194 SDValue Src2 = Op.getOperand(2);
16195 SDValue Src3 = Op.getOperand(3);
16196 SDValue Mask = Op.getOperand(4);
16197 EVT VT = Op.getValueType();
16198 SDValue PassThru = SDValue();
16200 // set PassThru element
16201 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16202 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16203 else if (IntrData->Type == FMA_OP_MASK3)
16208 // We specify 2 possible opcodes for intrinsics with rounding modes.
16209 // First, we check if the intrinsic may have non-default rounding mode,
16210 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16211 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16212 if (IntrWithRoundingModeOpcode != 0) {
16213 SDValue Rnd = Op.getOperand(5);
16214 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16215 X86::STATIC_ROUNDING::CUR_DIRECTION)
16216 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16217 dl, Op.getValueType(),
16218 Src1, Src2, Src3, Rnd),
16219 Mask, PassThru, Subtarget, DAG);
16221 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16222 dl, Op.getValueType(),
16224 Mask, PassThru, Subtarget, DAG);
16227 // FPclass intrinsics with mask
16228 SDValue Src1 = Op.getOperand(1);
16229 EVT VT = Src1.getValueType();
16230 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16231 VT.getVectorNumElements());
16232 SDValue Imm = Op.getOperand(2);
16233 SDValue Mask = Op.getOperand(3);
16234 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16235 Mask.getValueType().getSizeInBits());
16236 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16237 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16238 DAG.getTargetConstant(0, dl, MaskVT),
16240 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16241 DAG.getUNDEF(BitcastVT), FPclassMask,
16242 DAG.getIntPtrConstant(0, dl));
16243 return DAG.getBitcast(Op.getValueType(), Res);
16246 case CMP_MASK_CC: {
16247 // Comparison intrinsics with masks.
16248 // Example of transformation:
16249 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16250 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16252 // (v8i1 (insert_subvector undef,
16253 // (v2i1 (and (PCMPEQM %a, %b),
16254 // (extract_subvector
16255 // (v8i1 (bitcast %mask)), 0))), 0))))
16256 EVT VT = Op.getOperand(1).getValueType();
16257 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16258 VT.getVectorNumElements());
16259 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16260 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16261 Mask.getValueType().getSizeInBits());
16263 if (IntrData->Type == CMP_MASK_CC) {
16264 SDValue CC = Op.getOperand(3);
16265 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16266 // We specify 2 possible opcodes for intrinsics with rounding modes.
16267 // First, we check if the intrinsic may have non-default rounding mode,
16268 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16269 if (IntrData->Opc1 != 0) {
16270 SDValue Rnd = Op.getOperand(5);
16271 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16272 X86::STATIC_ROUNDING::CUR_DIRECTION)
16273 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16274 Op.getOperand(2), CC, Rnd);
16276 //default rounding mode
16278 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16279 Op.getOperand(2), CC);
16282 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16283 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16286 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16287 DAG.getTargetConstant(0, dl,
16290 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16291 DAG.getUNDEF(BitcastVT), CmpMask,
16292 DAG.getIntPtrConstant(0, dl));
16293 return DAG.getBitcast(Op.getValueType(), Res);
16295 case CMP_MASK_SCALAR_CC: {
16296 SDValue Src1 = Op.getOperand(1);
16297 SDValue Src2 = Op.getOperand(2);
16298 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16299 SDValue Mask = Op.getOperand(4);
16302 if (IntrData->Opc1 != 0) {
16303 SDValue Rnd = Op.getOperand(5);
16304 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16305 X86::STATIC_ROUNDING::CUR_DIRECTION)
16306 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16308 //default rounding mode
16310 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16312 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16313 DAG.getTargetConstant(0, dl,
16317 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16318 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16319 DAG.getValueType(MVT::i1));
16321 case COMI: { // Comparison intrinsics
16322 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16323 SDValue LHS = Op.getOperand(1);
16324 SDValue RHS = Op.getOperand(2);
16325 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16326 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16327 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16328 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16329 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16330 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16333 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16334 Op.getOperand(1), Op.getOperand(2), DAG);
16336 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16337 Op.getSimpleValueType(),
16339 Op.getOperand(2), DAG),
16340 Op.getOperand(4), Op.getOperand(3), Subtarget,
16342 case COMPRESS_EXPAND_IN_REG: {
16343 SDValue Mask = Op.getOperand(3);
16344 SDValue DataToCompress = Op.getOperand(1);
16345 SDValue PassThru = Op.getOperand(2);
16346 if (isAllOnes(Mask)) // return data as is
16347 return Op.getOperand(1);
16349 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16351 Mask, PassThru, Subtarget, DAG);
16354 SDValue Mask = Op.getOperand(3);
16355 EVT VT = Op.getValueType();
16356 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16357 VT.getVectorNumElements());
16358 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16359 Mask.getValueType().getSizeInBits());
16361 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16362 DAG.getBitcast(BitcastVT, Mask),
16363 DAG.getIntPtrConstant(0, dl));
16364 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16373 default: return SDValue(); // Don't custom lower most intrinsics.
16375 case Intrinsic::x86_avx2_permd:
16376 case Intrinsic::x86_avx2_permps:
16377 // Operands intentionally swapped. Mask is last operand to intrinsic,
16378 // but second operand for node/instruction.
16379 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16380 Op.getOperand(2), Op.getOperand(1));
16382 // ptest and testp intrinsics. The intrinsic these come from are designed to
16383 // return an integer value, not just an instruction so lower it to the ptest
16384 // or testp pattern and a setcc for the result.
16385 case Intrinsic::x86_sse41_ptestz:
16386 case Intrinsic::x86_sse41_ptestc:
16387 case Intrinsic::x86_sse41_ptestnzc:
16388 case Intrinsic::x86_avx_ptestz_256:
16389 case Intrinsic::x86_avx_ptestc_256:
16390 case Intrinsic::x86_avx_ptestnzc_256:
16391 case Intrinsic::x86_avx_vtestz_ps:
16392 case Intrinsic::x86_avx_vtestc_ps:
16393 case Intrinsic::x86_avx_vtestnzc_ps:
16394 case Intrinsic::x86_avx_vtestz_pd:
16395 case Intrinsic::x86_avx_vtestc_pd:
16396 case Intrinsic::x86_avx_vtestnzc_pd:
16397 case Intrinsic::x86_avx_vtestz_ps_256:
16398 case Intrinsic::x86_avx_vtestc_ps_256:
16399 case Intrinsic::x86_avx_vtestnzc_ps_256:
16400 case Intrinsic::x86_avx_vtestz_pd_256:
16401 case Intrinsic::x86_avx_vtestc_pd_256:
16402 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16403 bool IsTestPacked = false;
16406 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16407 case Intrinsic::x86_avx_vtestz_ps:
16408 case Intrinsic::x86_avx_vtestz_pd:
16409 case Intrinsic::x86_avx_vtestz_ps_256:
16410 case Intrinsic::x86_avx_vtestz_pd_256:
16411 IsTestPacked = true; // Fallthrough
16412 case Intrinsic::x86_sse41_ptestz:
16413 case Intrinsic::x86_avx_ptestz_256:
16415 X86CC = X86::COND_E;
16417 case Intrinsic::x86_avx_vtestc_ps:
16418 case Intrinsic::x86_avx_vtestc_pd:
16419 case Intrinsic::x86_avx_vtestc_ps_256:
16420 case Intrinsic::x86_avx_vtestc_pd_256:
16421 IsTestPacked = true; // Fallthrough
16422 case Intrinsic::x86_sse41_ptestc:
16423 case Intrinsic::x86_avx_ptestc_256:
16425 X86CC = X86::COND_B;
16427 case Intrinsic::x86_avx_vtestnzc_ps:
16428 case Intrinsic::x86_avx_vtestnzc_pd:
16429 case Intrinsic::x86_avx_vtestnzc_ps_256:
16430 case Intrinsic::x86_avx_vtestnzc_pd_256:
16431 IsTestPacked = true; // Fallthrough
16432 case Intrinsic::x86_sse41_ptestnzc:
16433 case Intrinsic::x86_avx_ptestnzc_256:
16435 X86CC = X86::COND_A;
16439 SDValue LHS = Op.getOperand(1);
16440 SDValue RHS = Op.getOperand(2);
16441 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16442 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16443 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16444 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16445 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16447 case Intrinsic::x86_avx512_kortestz_w:
16448 case Intrinsic::x86_avx512_kortestc_w: {
16449 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16450 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16451 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16452 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16453 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16454 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16455 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16458 case Intrinsic::x86_sse42_pcmpistria128:
16459 case Intrinsic::x86_sse42_pcmpestria128:
16460 case Intrinsic::x86_sse42_pcmpistric128:
16461 case Intrinsic::x86_sse42_pcmpestric128:
16462 case Intrinsic::x86_sse42_pcmpistrio128:
16463 case Intrinsic::x86_sse42_pcmpestrio128:
16464 case Intrinsic::x86_sse42_pcmpistris128:
16465 case Intrinsic::x86_sse42_pcmpestris128:
16466 case Intrinsic::x86_sse42_pcmpistriz128:
16467 case Intrinsic::x86_sse42_pcmpestriz128: {
16471 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16472 case Intrinsic::x86_sse42_pcmpistria128:
16473 Opcode = X86ISD::PCMPISTRI;
16474 X86CC = X86::COND_A;
16476 case Intrinsic::x86_sse42_pcmpestria128:
16477 Opcode = X86ISD::PCMPESTRI;
16478 X86CC = X86::COND_A;
16480 case Intrinsic::x86_sse42_pcmpistric128:
16481 Opcode = X86ISD::PCMPISTRI;
16482 X86CC = X86::COND_B;
16484 case Intrinsic::x86_sse42_pcmpestric128:
16485 Opcode = X86ISD::PCMPESTRI;
16486 X86CC = X86::COND_B;
16488 case Intrinsic::x86_sse42_pcmpistrio128:
16489 Opcode = X86ISD::PCMPISTRI;
16490 X86CC = X86::COND_O;
16492 case Intrinsic::x86_sse42_pcmpestrio128:
16493 Opcode = X86ISD::PCMPESTRI;
16494 X86CC = X86::COND_O;
16496 case Intrinsic::x86_sse42_pcmpistris128:
16497 Opcode = X86ISD::PCMPISTRI;
16498 X86CC = X86::COND_S;
16500 case Intrinsic::x86_sse42_pcmpestris128:
16501 Opcode = X86ISD::PCMPESTRI;
16502 X86CC = X86::COND_S;
16504 case Intrinsic::x86_sse42_pcmpistriz128:
16505 Opcode = X86ISD::PCMPISTRI;
16506 X86CC = X86::COND_E;
16508 case Intrinsic::x86_sse42_pcmpestriz128:
16509 Opcode = X86ISD::PCMPESTRI;
16510 X86CC = X86::COND_E;
16513 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16514 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16515 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16516 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16517 DAG.getConstant(X86CC, dl, MVT::i8),
16518 SDValue(PCMP.getNode(), 1));
16519 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16522 case Intrinsic::x86_sse42_pcmpistri128:
16523 case Intrinsic::x86_sse42_pcmpestri128: {
16525 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16526 Opcode = X86ISD::PCMPISTRI;
16528 Opcode = X86ISD::PCMPESTRI;
16530 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16531 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16532 return DAG.getNode(Opcode, dl, VTs, NewOps);
16535 case Intrinsic::x86_seh_lsda: {
16536 // Compute the symbol for the LSDA. We know it'll get emitted later.
16537 MachineFunction &MF = DAG.getMachineFunction();
16538 SDValue Op1 = Op.getOperand(1);
16539 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16540 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16541 GlobalValue::getRealLinkageName(Fn->getName()));
16543 // Generate a simple absolute symbol reference. This intrinsic is only
16544 // supported on 32-bit Windows, which isn't PIC.
16545 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16546 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16549 case Intrinsic::x86_seh_recoverfp: {
16550 SDValue FnOp = Op.getOperand(1);
16551 SDValue IncomingFPOp = Op.getOperand(2);
16552 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16553 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16555 report_fatal_error(
16556 "llvm.x86.seh.recoverfp must take a function as the first argument");
16557 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16560 case Intrinsic::localaddress: {
16561 // Returns one of the stack, base, or frame pointer registers, depending on
16562 // which is used to reference local variables.
16563 MachineFunction &MF = DAG.getMachineFunction();
16564 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16566 if (RegInfo->hasBasePointer(MF))
16567 Reg = RegInfo->getBaseRegister();
16568 else // This function handles the SP or FP case.
16569 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16570 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16575 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16576 SDValue Src, SDValue Mask, SDValue Base,
16577 SDValue Index, SDValue ScaleOp, SDValue Chain,
16578 const X86Subtarget * Subtarget) {
16580 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16582 llvm_unreachable("Invalid scale type");
16583 unsigned ScaleVal = C->getZExtValue();
16584 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16585 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16587 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16588 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16589 Index.getSimpleValueType().getVectorNumElements());
16591 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16593 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16595 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16596 Mask.getValueType().getSizeInBits());
16598 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16599 // are extracted by EXTRACT_SUBVECTOR.
16600 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16601 DAG.getBitcast(BitcastVT, Mask),
16602 DAG.getIntPtrConstant(0, dl));
16604 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16605 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16606 SDValue Segment = DAG.getRegister(0, MVT::i32);
16607 if (Src.getOpcode() == ISD::UNDEF)
16608 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16609 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16610 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16611 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16612 return DAG.getMergeValues(RetOps, dl);
16615 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16616 SDValue Src, SDValue Mask, SDValue Base,
16617 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16619 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16621 llvm_unreachable("Invalid scale type");
16622 unsigned ScaleVal = C->getZExtValue();
16623 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16624 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16626 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16627 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16628 SDValue Segment = DAG.getRegister(0, MVT::i32);
16629 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16630 Index.getSimpleValueType().getVectorNumElements());
16632 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16634 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16636 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16637 Mask.getValueType().getSizeInBits());
16639 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16640 // are extracted by EXTRACT_SUBVECTOR.
16641 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16642 DAG.getBitcast(BitcastVT, Mask),
16643 DAG.getIntPtrConstant(0, dl));
16645 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16646 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16647 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16648 return SDValue(Res, 1);
16651 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16652 SDValue Mask, SDValue Base, SDValue Index,
16653 SDValue ScaleOp, SDValue Chain) {
16655 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16656 assert(C && "Invalid scale type");
16657 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16658 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16659 SDValue Segment = DAG.getRegister(0, MVT::i32);
16661 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16663 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16665 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16667 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16668 //SDVTList VTs = DAG.getVTList(MVT::Other);
16669 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16670 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16671 return SDValue(Res, 0);
16674 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16675 // read performance monitor counters (x86_rdpmc).
16676 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16677 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16678 SmallVectorImpl<SDValue> &Results) {
16679 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16680 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16683 // The ECX register is used to select the index of the performance counter
16685 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16687 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16689 // Reads the content of a 64-bit performance counter and returns it in the
16690 // registers EDX:EAX.
16691 if (Subtarget->is64Bit()) {
16692 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16693 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16696 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16697 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16700 Chain = HI.getValue(1);
16702 if (Subtarget->is64Bit()) {
16703 // The EAX register is loaded with the low-order 32 bits. The EDX register
16704 // is loaded with the supported high-order bits of the counter.
16705 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16706 DAG.getConstant(32, DL, MVT::i8));
16707 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16708 Results.push_back(Chain);
16712 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16713 SDValue Ops[] = { LO, HI };
16714 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16715 Results.push_back(Pair);
16716 Results.push_back(Chain);
16719 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16720 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16721 // also used to custom lower READCYCLECOUNTER nodes.
16722 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16723 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16724 SmallVectorImpl<SDValue> &Results) {
16725 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16726 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16729 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16730 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16731 // and the EAX register is loaded with the low-order 32 bits.
16732 if (Subtarget->is64Bit()) {
16733 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16734 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16737 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16738 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16741 SDValue Chain = HI.getValue(1);
16743 if (Opcode == X86ISD::RDTSCP_DAG) {
16744 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16746 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16747 // the ECX register. Add 'ecx' explicitly to the chain.
16748 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16750 // Explicitly store the content of ECX at the location passed in input
16751 // to the 'rdtscp' intrinsic.
16752 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16753 MachinePointerInfo(), false, false, 0);
16756 if (Subtarget->is64Bit()) {
16757 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16758 // the EAX register is loaded with the low-order 32 bits.
16759 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16760 DAG.getConstant(32, DL, MVT::i8));
16761 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16762 Results.push_back(Chain);
16766 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16767 SDValue Ops[] = { LO, HI };
16768 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16769 Results.push_back(Pair);
16770 Results.push_back(Chain);
16773 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16774 SelectionDAG &DAG) {
16775 SmallVector<SDValue, 2> Results;
16777 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16779 return DAG.getMergeValues(Results, DL);
16782 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16783 SelectionDAG &DAG) {
16784 MachineFunction &MF = DAG.getMachineFunction();
16785 const Function *Fn = MF.getFunction();
16787 SDValue Chain = Op.getOperand(0);
16789 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16790 "using llvm.x86.seh.restoreframe requires a frame pointer");
16792 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16793 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16795 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16796 unsigned FrameReg =
16797 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16798 unsigned SPReg = RegInfo->getStackRegister();
16799 unsigned SlotSize = RegInfo->getSlotSize();
16801 // Get incoming EBP.
16802 SDValue IncomingEBP =
16803 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16805 // SP is saved in the first field of every registration node, so load
16806 // [EBP-RegNodeSize] into SP.
16807 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16808 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16809 DAG.getConstant(-RegNodeSize, dl, VT));
16811 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16812 false, VT.getScalarSizeInBits() / 8);
16813 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16815 if (!RegInfo->needsStackRealignment(MF)) {
16816 // Adjust EBP to point back to the original frame position.
16817 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16818 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16820 assert(RegInfo->hasBasePointer(MF) &&
16821 "functions with Win32 EH must use frame or base pointer register");
16823 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16824 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16825 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16827 // Reload the spilled EBP value, now that the stack and base pointers are
16829 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16830 X86FI->setHasSEHFramePtrSave(true);
16831 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16832 X86FI->setSEHFramePtrSaveIndex(FI);
16833 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16834 MachinePointerInfo(), false, false, false,
16835 VT.getScalarSizeInBits() / 8);
16836 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16842 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16843 /// return truncate Store/MaskedStore Node
16844 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16848 SDValue Mask = Op.getOperand(4);
16849 SDValue DataToTruncate = Op.getOperand(3);
16850 SDValue Addr = Op.getOperand(2);
16851 SDValue Chain = Op.getOperand(0);
16853 EVT VT = DataToTruncate.getValueType();
16854 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16855 ElementType, VT.getVectorNumElements());
16857 if (isAllOnes(Mask)) // return just a truncate store
16858 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16859 MachinePointerInfo(), SVT, false, false,
16860 SVT.getScalarSizeInBits()/8);
16862 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16863 MVT::i1, VT.getVectorNumElements());
16864 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16865 Mask.getValueType().getSizeInBits());
16866 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16867 // are extracted by EXTRACT_SUBVECTOR.
16868 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16869 DAG.getBitcast(BitcastVT, Mask),
16870 DAG.getIntPtrConstant(0, dl));
16872 MachineMemOperand *MMO = DAG.getMachineFunction().
16873 getMachineMemOperand(MachinePointerInfo(),
16874 MachineMemOperand::MOStore, SVT.getStoreSize(),
16875 SVT.getScalarSizeInBits()/8);
16877 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
16878 VMask, SVT, MMO, true);
16881 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16882 SelectionDAG &DAG) {
16883 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16885 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16887 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16888 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16893 switch(IntrData->Type) {
16895 llvm_unreachable("Unknown Intrinsic Type");
16899 // Emit the node with the right value type.
16900 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16901 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16903 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16904 // Otherwise return the value from Rand, which is always 0, casted to i32.
16905 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16906 DAG.getConstant(1, dl, Op->getValueType(1)),
16907 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16908 SDValue(Result.getNode(), 1) };
16909 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16910 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16913 // Return { result, isValid, chain }.
16914 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16915 SDValue(Result.getNode(), 2));
16918 //gather(v1, mask, index, base, scale);
16919 SDValue Chain = Op.getOperand(0);
16920 SDValue Src = Op.getOperand(2);
16921 SDValue Base = Op.getOperand(3);
16922 SDValue Index = Op.getOperand(4);
16923 SDValue Mask = Op.getOperand(5);
16924 SDValue Scale = Op.getOperand(6);
16925 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16929 //scatter(base, mask, index, v1, scale);
16930 SDValue Chain = Op.getOperand(0);
16931 SDValue Base = Op.getOperand(2);
16932 SDValue Mask = Op.getOperand(3);
16933 SDValue Index = Op.getOperand(4);
16934 SDValue Src = Op.getOperand(5);
16935 SDValue Scale = Op.getOperand(6);
16936 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16940 SDValue Hint = Op.getOperand(6);
16941 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16942 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16943 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16944 SDValue Chain = Op.getOperand(0);
16945 SDValue Mask = Op.getOperand(2);
16946 SDValue Index = Op.getOperand(3);
16947 SDValue Base = Op.getOperand(4);
16948 SDValue Scale = Op.getOperand(5);
16949 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16951 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16953 SmallVector<SDValue, 2> Results;
16954 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
16956 return DAG.getMergeValues(Results, dl);
16958 // Read Performance Monitoring Counters.
16960 SmallVector<SDValue, 2> Results;
16961 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16962 return DAG.getMergeValues(Results, dl);
16964 // XTEST intrinsics.
16966 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16967 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16968 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16969 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
16971 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16972 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16973 Ret, SDValue(InTrans.getNode(), 1));
16977 SmallVector<SDValue, 2> Results;
16978 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16979 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16980 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16981 DAG.getConstant(-1, dl, MVT::i8));
16982 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16983 Op.getOperand(4), GenCF.getValue(1));
16984 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16985 Op.getOperand(5), MachinePointerInfo(),
16987 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16988 DAG.getConstant(X86::COND_B, dl, MVT::i8),
16990 Results.push_back(SetCC);
16991 Results.push_back(Store);
16992 return DAG.getMergeValues(Results, dl);
16994 case COMPRESS_TO_MEM: {
16996 SDValue Mask = Op.getOperand(4);
16997 SDValue DataToCompress = Op.getOperand(3);
16998 SDValue Addr = Op.getOperand(2);
16999 SDValue Chain = Op.getOperand(0);
17001 EVT VT = DataToCompress.getValueType();
17002 if (isAllOnes(Mask)) // return just a store
17003 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17004 MachinePointerInfo(), false, false,
17005 VT.getScalarSizeInBits()/8);
17007 SDValue Compressed =
17008 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17009 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17010 return DAG.getStore(Chain, dl, Compressed, Addr,
17011 MachinePointerInfo(), false, false,
17012 VT.getScalarSizeInBits()/8);
17014 case TRUNCATE_TO_MEM_VI8:
17015 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17016 case TRUNCATE_TO_MEM_VI16:
17017 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17018 case TRUNCATE_TO_MEM_VI32:
17019 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17020 case EXPAND_FROM_MEM: {
17022 SDValue Mask = Op.getOperand(4);
17023 SDValue PassThru = Op.getOperand(3);
17024 SDValue Addr = Op.getOperand(2);
17025 SDValue Chain = Op.getOperand(0);
17026 EVT VT = Op.getValueType();
17028 if (isAllOnes(Mask)) // return just a load
17029 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17030 false, VT.getScalarSizeInBits()/8);
17032 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17033 false, false, false,
17034 VT.getScalarSizeInBits()/8);
17036 SDValue Results[] = {
17037 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17038 Mask, PassThru, Subtarget, DAG), Chain};
17039 return DAG.getMergeValues(Results, dl);
17044 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17045 SelectionDAG &DAG) const {
17046 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17047 MFI->setReturnAddressIsTaken(true);
17049 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17052 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17054 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17057 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17058 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17059 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17060 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17061 DAG.getNode(ISD::ADD, dl, PtrVT,
17062 FrameAddr, Offset),
17063 MachinePointerInfo(), false, false, false, 0);
17066 // Just load the return address.
17067 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17068 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17069 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17072 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17073 MachineFunction &MF = DAG.getMachineFunction();
17074 MachineFrameInfo *MFI = MF.getFrameInfo();
17075 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17076 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17077 EVT VT = Op.getValueType();
17079 MFI->setFrameAddressIsTaken(true);
17081 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17082 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17083 // is not possible to crawl up the stack without looking at the unwind codes
17085 int FrameAddrIndex = FuncInfo->getFAIndex();
17086 if (!FrameAddrIndex) {
17087 // Set up a frame object for the return address.
17088 unsigned SlotSize = RegInfo->getSlotSize();
17089 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17090 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17091 FuncInfo->setFAIndex(FrameAddrIndex);
17093 return DAG.getFrameIndex(FrameAddrIndex, VT);
17096 unsigned FrameReg =
17097 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17098 SDLoc dl(Op); // FIXME probably not meaningful
17099 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17100 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17101 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17102 "Invalid Frame Register!");
17103 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17105 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17106 MachinePointerInfo(),
17107 false, false, false, 0);
17111 // FIXME? Maybe this could be a TableGen attribute on some registers and
17112 // this table could be generated automatically from RegInfo.
17113 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17114 SelectionDAG &DAG) const {
17115 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17116 const MachineFunction &MF = DAG.getMachineFunction();
17118 unsigned Reg = StringSwitch<unsigned>(RegName)
17119 .Case("esp", X86::ESP)
17120 .Case("rsp", X86::RSP)
17121 .Case("ebp", X86::EBP)
17122 .Case("rbp", X86::RBP)
17125 if (Reg == X86::EBP || Reg == X86::RBP) {
17126 if (!TFI.hasFP(MF))
17127 report_fatal_error("register " + StringRef(RegName) +
17128 " is allocatable: function has no frame pointer");
17131 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17132 unsigned FrameReg =
17133 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17134 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17135 "Invalid Frame Register!");
17143 report_fatal_error("Invalid register name global variable");
17146 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17147 SelectionDAG &DAG) const {
17148 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17149 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17152 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17153 SDValue Chain = Op.getOperand(0);
17154 SDValue Offset = Op.getOperand(1);
17155 SDValue Handler = Op.getOperand(2);
17158 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17159 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17160 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17161 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17162 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17163 "Invalid Frame Register!");
17164 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17165 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17167 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17168 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17170 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17171 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17173 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17175 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17176 DAG.getRegister(StoreAddrReg, PtrVT));
17179 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17180 SelectionDAG &DAG) const {
17182 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17183 DAG.getVTList(MVT::i32, MVT::Other),
17184 Op.getOperand(0), Op.getOperand(1));
17187 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17188 SelectionDAG &DAG) const {
17190 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17191 Op.getOperand(0), Op.getOperand(1));
17194 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17195 return Op.getOperand(0);
17198 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17199 SelectionDAG &DAG) const {
17200 SDValue Root = Op.getOperand(0);
17201 SDValue Trmp = Op.getOperand(1); // trampoline
17202 SDValue FPtr = Op.getOperand(2); // nested function
17203 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17206 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17207 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17209 if (Subtarget->is64Bit()) {
17210 SDValue OutChains[6];
17212 // Large code-model.
17213 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17214 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17216 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17217 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17219 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17221 // Load the pointer to the nested function into R11.
17222 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17223 SDValue Addr = Trmp;
17224 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17225 Addr, MachinePointerInfo(TrmpAddr),
17228 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17229 DAG.getConstant(2, dl, MVT::i64));
17230 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17231 MachinePointerInfo(TrmpAddr, 2),
17234 // Load the 'nest' parameter value into R10.
17235 // R10 is specified in X86CallingConv.td
17236 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17237 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17238 DAG.getConstant(10, dl, MVT::i64));
17239 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17240 Addr, MachinePointerInfo(TrmpAddr, 10),
17243 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17244 DAG.getConstant(12, dl, MVT::i64));
17245 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17246 MachinePointerInfo(TrmpAddr, 12),
17249 // Jump to the nested function.
17250 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17251 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17252 DAG.getConstant(20, dl, MVT::i64));
17253 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17254 Addr, MachinePointerInfo(TrmpAddr, 20),
17257 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17258 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17259 DAG.getConstant(22, dl, MVT::i64));
17260 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17261 Addr, MachinePointerInfo(TrmpAddr, 22),
17264 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17266 const Function *Func =
17267 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17268 CallingConv::ID CC = Func->getCallingConv();
17273 llvm_unreachable("Unsupported calling convention");
17274 case CallingConv::C:
17275 case CallingConv::X86_StdCall: {
17276 // Pass 'nest' parameter in ECX.
17277 // Must be kept in sync with X86CallingConv.td
17278 NestReg = X86::ECX;
17280 // Check that ECX wasn't needed by an 'inreg' parameter.
17281 FunctionType *FTy = Func->getFunctionType();
17282 const AttributeSet &Attrs = Func->getAttributes();
17284 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17285 unsigned InRegCount = 0;
17288 for (FunctionType::param_iterator I = FTy->param_begin(),
17289 E = FTy->param_end(); I != E; ++I, ++Idx)
17290 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17291 auto &DL = DAG.getDataLayout();
17292 // FIXME: should only count parameters that are lowered to integers.
17293 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17296 if (InRegCount > 2) {
17297 report_fatal_error("Nest register in use - reduce number of inreg"
17303 case CallingConv::X86_FastCall:
17304 case CallingConv::X86_ThisCall:
17305 case CallingConv::Fast:
17306 // Pass 'nest' parameter in EAX.
17307 // Must be kept in sync with X86CallingConv.td
17308 NestReg = X86::EAX;
17312 SDValue OutChains[4];
17313 SDValue Addr, Disp;
17315 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17316 DAG.getConstant(10, dl, MVT::i32));
17317 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17319 // This is storing the opcode for MOV32ri.
17320 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17321 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17322 OutChains[0] = DAG.getStore(Root, dl,
17323 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17324 Trmp, MachinePointerInfo(TrmpAddr),
17327 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17328 DAG.getConstant(1, dl, MVT::i32));
17329 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17330 MachinePointerInfo(TrmpAddr, 1),
17333 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17334 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17335 DAG.getConstant(5, dl, MVT::i32));
17336 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17337 Addr, MachinePointerInfo(TrmpAddr, 5),
17340 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17341 DAG.getConstant(6, dl, MVT::i32));
17342 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17343 MachinePointerInfo(TrmpAddr, 6),
17346 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17350 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17351 SelectionDAG &DAG) const {
17353 The rounding mode is in bits 11:10 of FPSR, and has the following
17355 00 Round to nearest
17360 FLT_ROUNDS, on the other hand, expects the following:
17367 To perform the conversion, we do:
17368 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17371 MachineFunction &MF = DAG.getMachineFunction();
17372 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17373 unsigned StackAlignment = TFI.getStackAlignment();
17374 MVT VT = Op.getSimpleValueType();
17377 // Save FP Control Word to stack slot
17378 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17379 SDValue StackSlot =
17380 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17382 MachineMemOperand *MMO =
17383 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17384 MachineMemOperand::MOStore, 2, 2);
17386 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17387 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17388 DAG.getVTList(MVT::Other),
17389 Ops, MVT::i16, MMO);
17391 // Load FP Control Word from stack slot
17392 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17393 MachinePointerInfo(), false, false, false, 0);
17395 // Transform as necessary
17397 DAG.getNode(ISD::SRL, DL, MVT::i16,
17398 DAG.getNode(ISD::AND, DL, MVT::i16,
17399 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17400 DAG.getConstant(11, DL, MVT::i8));
17402 DAG.getNode(ISD::SRL, DL, MVT::i16,
17403 DAG.getNode(ISD::AND, DL, MVT::i16,
17404 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17405 DAG.getConstant(9, DL, MVT::i8));
17408 DAG.getNode(ISD::AND, DL, MVT::i16,
17409 DAG.getNode(ISD::ADD, DL, MVT::i16,
17410 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17411 DAG.getConstant(1, DL, MVT::i16)),
17412 DAG.getConstant(3, DL, MVT::i16));
17414 return DAG.getNode((VT.getSizeInBits() < 16 ?
17415 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17418 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17419 MVT VT = Op.getSimpleValueType();
17421 unsigned NumBits = VT.getSizeInBits();
17424 Op = Op.getOperand(0);
17425 if (VT == MVT::i8) {
17426 // Zero extend to i32 since there is not an i8 bsr.
17428 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17431 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17432 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17433 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17435 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17438 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17439 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17442 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17444 // Finally xor with NumBits-1.
17445 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17446 DAG.getConstant(NumBits - 1, dl, OpVT));
17449 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17453 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17454 MVT VT = Op.getSimpleValueType();
17456 unsigned NumBits = VT.getSizeInBits();
17459 Op = Op.getOperand(0);
17460 if (VT == MVT::i8) {
17461 // Zero extend to i32 since there is not an i8 bsr.
17463 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17466 // Issue a bsr (scan bits in reverse).
17467 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17468 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17470 // And xor with NumBits-1.
17471 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17472 DAG.getConstant(NumBits - 1, dl, OpVT));
17475 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17479 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17480 MVT VT = Op.getSimpleValueType();
17481 unsigned NumBits = VT.getScalarSizeInBits();
17484 if (VT.isVector()) {
17485 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17487 SDValue N0 = Op.getOperand(0);
17488 SDValue Zero = DAG.getConstant(0, dl, VT);
17490 // lsb(x) = (x & -x)
17491 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17492 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17494 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17495 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17496 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17497 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17498 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17499 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17502 // cttz(x) = ctpop(lsb - 1)
17503 SDValue One = DAG.getConstant(1, dl, VT);
17504 return DAG.getNode(ISD::CTPOP, dl, VT,
17505 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17508 assert(Op.getOpcode() == ISD::CTTZ &&
17509 "Only scalar CTTZ requires custom lowering");
17511 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17512 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17513 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17515 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17518 DAG.getConstant(NumBits, dl, VT),
17519 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17522 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17525 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17526 // ones, and then concatenate the result back.
17527 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17528 MVT VT = Op.getSimpleValueType();
17530 assert(VT.is256BitVector() && VT.isInteger() &&
17531 "Unsupported value type for operation");
17533 unsigned NumElems = VT.getVectorNumElements();
17536 // Extract the LHS vectors
17537 SDValue LHS = Op.getOperand(0);
17538 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17539 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17541 // Extract the RHS vectors
17542 SDValue RHS = Op.getOperand(1);
17543 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17544 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17546 MVT EltVT = VT.getVectorElementType();
17547 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17549 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17550 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17551 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17554 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17555 if (Op.getValueType() == MVT::i1)
17556 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17557 Op.getOperand(0), Op.getOperand(1));
17558 assert(Op.getSimpleValueType().is256BitVector() &&
17559 Op.getSimpleValueType().isInteger() &&
17560 "Only handle AVX 256-bit vector integer operation");
17561 return Lower256IntArith(Op, DAG);
17564 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17565 if (Op.getValueType() == MVT::i1)
17566 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17567 Op.getOperand(0), Op.getOperand(1));
17568 assert(Op.getSimpleValueType().is256BitVector() &&
17569 Op.getSimpleValueType().isInteger() &&
17570 "Only handle AVX 256-bit vector integer operation");
17571 return Lower256IntArith(Op, DAG);
17574 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17575 assert(Op.getSimpleValueType().is256BitVector() &&
17576 Op.getSimpleValueType().isInteger() &&
17577 "Only handle AVX 256-bit vector integer operation");
17578 return Lower256IntArith(Op, DAG);
17581 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17582 SelectionDAG &DAG) {
17584 MVT VT = Op.getSimpleValueType();
17587 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17589 // Decompose 256-bit ops into smaller 128-bit ops.
17590 if (VT.is256BitVector() && !Subtarget->hasInt256())
17591 return Lower256IntArith(Op, DAG);
17593 SDValue A = Op.getOperand(0);
17594 SDValue B = Op.getOperand(1);
17596 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17597 // pairs, multiply and truncate.
17598 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17599 if (Subtarget->hasInt256()) {
17600 if (VT == MVT::v32i8) {
17601 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17602 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17603 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17604 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17605 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17606 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17607 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17608 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17609 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17610 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17613 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17614 return DAG.getNode(
17615 ISD::TRUNCATE, dl, VT,
17616 DAG.getNode(ISD::MUL, dl, ExVT,
17617 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17618 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17621 assert(VT == MVT::v16i8 &&
17622 "Pre-AVX2 support only supports v16i8 multiplication");
17623 MVT ExVT = MVT::v8i16;
17625 // Extract the lo parts and sign extend to i16
17627 if (Subtarget->hasSSE41()) {
17628 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17629 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17631 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17632 -1, 4, -1, 5, -1, 6, -1, 7};
17633 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17634 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17635 ALo = DAG.getBitcast(ExVT, ALo);
17636 BLo = DAG.getBitcast(ExVT, BLo);
17637 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17638 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17641 // Extract the hi parts and sign extend to i16
17643 if (Subtarget->hasSSE41()) {
17644 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17645 -1, -1, -1, -1, -1, -1, -1, -1};
17646 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17647 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17648 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17649 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17651 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17652 -1, 12, -1, 13, -1, 14, -1, 15};
17653 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17654 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17655 AHi = DAG.getBitcast(ExVT, AHi);
17656 BHi = DAG.getBitcast(ExVT, BHi);
17657 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17658 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17661 // Multiply, mask the lower 8bits of the lo/hi results and pack
17662 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17663 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17664 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17665 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17666 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17669 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17670 if (VT == MVT::v4i32) {
17671 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17672 "Should not custom lower when pmuldq is available!");
17674 // Extract the odd parts.
17675 static const int UnpackMask[] = { 1, -1, 3, -1 };
17676 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17677 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17679 // Multiply the even parts.
17680 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17681 // Now multiply odd parts.
17682 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17684 Evens = DAG.getBitcast(VT, Evens);
17685 Odds = DAG.getBitcast(VT, Odds);
17687 // Merge the two vectors back together with a shuffle. This expands into 2
17689 static const int ShufMask[] = { 0, 4, 2, 6 };
17690 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17693 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17694 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17696 // Ahi = psrlqi(a, 32);
17697 // Bhi = psrlqi(b, 32);
17699 // AloBlo = pmuludq(a, b);
17700 // AloBhi = pmuludq(a, Bhi);
17701 // AhiBlo = pmuludq(Ahi, b);
17703 // AloBhi = psllqi(AloBhi, 32);
17704 // AhiBlo = psllqi(AhiBlo, 32);
17705 // return AloBlo + AloBhi + AhiBlo;
17707 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17708 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17710 SDValue AhiBlo = Ahi;
17711 SDValue AloBhi = Bhi;
17712 // Bit cast to 32-bit vectors for MULUDQ
17713 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17714 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17715 A = DAG.getBitcast(MulVT, A);
17716 B = DAG.getBitcast(MulVT, B);
17717 Ahi = DAG.getBitcast(MulVT, Ahi);
17718 Bhi = DAG.getBitcast(MulVT, Bhi);
17720 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17721 // After shifting right const values the result may be all-zero.
17722 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17723 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17724 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17726 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17727 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17728 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17731 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17732 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17735 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17736 assert(Subtarget->isTargetWin64() && "Unexpected target");
17737 EVT VT = Op.getValueType();
17738 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17739 "Unexpected return type for lowering");
17743 switch (Op->getOpcode()) {
17744 default: llvm_unreachable("Unexpected request for libcall!");
17745 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17746 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17747 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17748 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17749 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17750 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17754 SDValue InChain = DAG.getEntryNode();
17756 TargetLowering::ArgListTy Args;
17757 TargetLowering::ArgListEntry Entry;
17758 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17759 EVT ArgVT = Op->getOperand(i).getValueType();
17760 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17761 "Unexpected argument type for lowering");
17762 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17763 Entry.Node = StackPtr;
17764 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17766 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17767 Entry.Ty = PointerType::get(ArgTy,0);
17768 Entry.isSExt = false;
17769 Entry.isZExt = false;
17770 Args.push_back(Entry);
17773 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17774 getPointerTy(DAG.getDataLayout()));
17776 TargetLowering::CallLoweringInfo CLI(DAG);
17777 CLI.setDebugLoc(dl).setChain(InChain)
17778 .setCallee(getLibcallCallingConv(LC),
17779 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17780 Callee, std::move(Args), 0)
17781 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17783 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17784 return DAG.getBitcast(VT, CallInfo.first);
17787 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17788 SelectionDAG &DAG) {
17789 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17790 EVT VT = Op0.getValueType();
17793 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17794 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17796 // PMULxD operations multiply each even value (starting at 0) of LHS with
17797 // the related value of RHS and produce a widen result.
17798 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17799 // => <2 x i64> <ae|cg>
17801 // In other word, to have all the results, we need to perform two PMULxD:
17802 // 1. one with the even values.
17803 // 2. one with the odd values.
17804 // To achieve #2, with need to place the odd values at an even position.
17806 // Place the odd value at an even position (basically, shift all values 1
17807 // step to the left):
17808 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17809 // <a|b|c|d> => <b|undef|d|undef>
17810 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17811 // <e|f|g|h> => <f|undef|h|undef>
17812 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17814 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17816 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17817 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17819 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17820 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17821 // => <2 x i64> <ae|cg>
17822 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17823 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17824 // => <2 x i64> <bf|dh>
17825 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17827 // Shuffle it back into the right order.
17828 SDValue Highs, Lows;
17829 if (VT == MVT::v8i32) {
17830 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17831 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17832 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17833 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17835 const int HighMask[] = {1, 5, 3, 7};
17836 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17837 const int LowMask[] = {0, 4, 2, 6};
17838 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17841 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17842 // unsigned multiply.
17843 if (IsSigned && !Subtarget->hasSSE41()) {
17844 SDValue ShAmt = DAG.getConstant(
17846 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
17847 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17848 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17849 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17850 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17852 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17853 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17856 // The first result of MUL_LOHI is actually the low value, followed by the
17858 SDValue Ops[] = {Lows, Highs};
17859 return DAG.getMergeValues(Ops, dl);
17862 // Return true if the required (according to Opcode) shift-imm form is natively
17863 // supported by the Subtarget
17864 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
17866 if (VT.getScalarSizeInBits() < 16)
17869 if (VT.is512BitVector() &&
17870 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
17873 bool LShift = VT.is128BitVector() ||
17874 (VT.is256BitVector() && Subtarget->hasInt256());
17876 bool AShift = LShift && (Subtarget->hasVLX() ||
17877 (VT != MVT::v2i64 && VT != MVT::v4i64));
17878 return (Opcode == ISD::SRA) ? AShift : LShift;
17881 // The shift amount is a variable, but it is the same for all vector lanes.
17882 // These instructions are defined together with shift-immediate.
17884 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
17886 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
17889 // Return true if the required (according to Opcode) variable-shift form is
17890 // natively supported by the Subtarget
17891 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
17894 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
17897 // vXi16 supported only on AVX-512, BWI
17898 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
17901 if (VT.is512BitVector() || Subtarget->hasVLX())
17904 bool LShift = VT.is128BitVector() || VT.is256BitVector();
17905 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
17906 return (Opcode == ISD::SRA) ? AShift : LShift;
17909 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17910 const X86Subtarget *Subtarget) {
17911 MVT VT = Op.getSimpleValueType();
17913 SDValue R = Op.getOperand(0);
17914 SDValue Amt = Op.getOperand(1);
17916 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17917 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17919 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
17920 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
17921 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
17922 SDValue Ex = DAG.getBitcast(ExVT, R);
17924 if (ShiftAmt >= 32) {
17925 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
17927 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
17928 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17929 ShiftAmt - 32, DAG);
17930 if (VT == MVT::v2i64)
17931 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
17932 if (VT == MVT::v4i64)
17933 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17934 {9, 1, 11, 3, 13, 5, 15, 7});
17936 // SRA upper i32, SHL whole i64 and select lower i32.
17937 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17940 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
17941 Lower = DAG.getBitcast(ExVT, Lower);
17942 if (VT == MVT::v2i64)
17943 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
17944 if (VT == MVT::v4i64)
17945 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17946 {8, 1, 10, 3, 12, 5, 14, 7});
17948 return DAG.getBitcast(VT, Ex);
17951 // Optimize shl/srl/sra with constant shift amount.
17952 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17953 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17954 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17956 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17957 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17959 // i64 SRA needs to be performed as partial shifts.
17960 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17961 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
17962 return ArithmeticShiftRight64(ShiftAmt);
17964 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
17965 unsigned NumElts = VT.getVectorNumElements();
17966 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
17968 // Simple i8 add case
17969 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
17970 return DAG.getNode(ISD::ADD, dl, VT, R, R);
17972 // ashr(R, 7) === cmp_slt(R, 0)
17973 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
17974 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17975 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17978 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
17979 if (VT == MVT::v16i8 && Subtarget->hasXOP())
17982 if (Op.getOpcode() == ISD::SHL) {
17983 // Make a large shift.
17984 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
17986 SHL = DAG.getBitcast(VT, SHL);
17987 // Zero out the rightmost bits.
17988 SmallVector<SDValue, 32> V(
17989 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
17990 return DAG.getNode(ISD::AND, dl, VT, SHL,
17991 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17993 if (Op.getOpcode() == ISD::SRL) {
17994 // Make a large shift.
17995 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
17997 SRL = DAG.getBitcast(VT, SRL);
17998 // Zero out the leftmost bits.
17999 SmallVector<SDValue, 32> V(
18000 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18001 return DAG.getNode(ISD::AND, dl, VT, SRL,
18002 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18004 if (Op.getOpcode() == ISD::SRA) {
18005 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18006 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18007 SmallVector<SDValue, 32> V(NumElts,
18008 DAG.getConstant(128 >> ShiftAmt, dl,
18010 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18011 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18012 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18015 llvm_unreachable("Unknown shift opcode.");
18020 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18021 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18022 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18024 // Peek through any splat that was introduced for i64 shift vectorization.
18025 int SplatIndex = -1;
18026 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18027 if (SVN->isSplat()) {
18028 SplatIndex = SVN->getSplatIndex();
18029 Amt = Amt.getOperand(0);
18030 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18031 "Splat shuffle referencing second operand");
18034 if (Amt.getOpcode() != ISD::BITCAST ||
18035 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18038 Amt = Amt.getOperand(0);
18039 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18040 VT.getVectorNumElements();
18041 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18042 uint64_t ShiftAmt = 0;
18043 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18044 for (unsigned i = 0; i != Ratio; ++i) {
18045 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18049 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18052 // Check remaining shift amounts (if not a splat).
18053 if (SplatIndex < 0) {
18054 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18055 uint64_t ShAmt = 0;
18056 for (unsigned j = 0; j != Ratio; ++j) {
18057 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18061 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18063 if (ShAmt != ShiftAmt)
18068 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18069 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18071 if (Op.getOpcode() == ISD::SRA)
18072 return ArithmeticShiftRight64(ShiftAmt);
18078 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18079 const X86Subtarget* Subtarget) {
18080 MVT VT = Op.getSimpleValueType();
18082 SDValue R = Op.getOperand(0);
18083 SDValue Amt = Op.getOperand(1);
18085 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18086 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18088 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18089 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18091 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18093 EVT EltVT = VT.getVectorElementType();
18095 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18096 // Check if this build_vector node is doing a splat.
18097 // If so, then set BaseShAmt equal to the splat value.
18098 BaseShAmt = BV->getSplatValue();
18099 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18100 BaseShAmt = SDValue();
18102 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18103 Amt = Amt.getOperand(0);
18105 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18106 if (SVN && SVN->isSplat()) {
18107 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18108 SDValue InVec = Amt.getOperand(0);
18109 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18110 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18111 "Unexpected shuffle index found!");
18112 BaseShAmt = InVec.getOperand(SplatIdx);
18113 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18114 if (ConstantSDNode *C =
18115 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18116 if (C->getZExtValue() == SplatIdx)
18117 BaseShAmt = InVec.getOperand(1);
18122 // Avoid introducing an extract element from a shuffle.
18123 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18124 DAG.getIntPtrConstant(SplatIdx, dl));
18128 if (BaseShAmt.getNode()) {
18129 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18130 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18131 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18132 else if (EltVT.bitsLT(MVT::i32))
18133 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18135 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18139 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18140 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18141 Amt.getOpcode() == ISD::BITCAST &&
18142 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18143 Amt = Amt.getOperand(0);
18144 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18145 VT.getVectorNumElements();
18146 std::vector<SDValue> Vals(Ratio);
18147 for (unsigned i = 0; i != Ratio; ++i)
18148 Vals[i] = Amt.getOperand(i);
18149 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18150 for (unsigned j = 0; j != Ratio; ++j)
18151 if (Vals[j] != Amt.getOperand(i + j))
18155 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18156 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18161 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18162 SelectionDAG &DAG) {
18163 MVT VT = Op.getSimpleValueType();
18165 SDValue R = Op.getOperand(0);
18166 SDValue Amt = Op.getOperand(1);
18168 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18169 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18171 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18174 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18177 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18180 // XOP has 128-bit variable logical/arithmetic shifts.
18181 // +ve/-ve Amt = shift left/right.
18182 if (Subtarget->hasXOP() &&
18183 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18184 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18185 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18186 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18187 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18189 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18190 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18191 if (Op.getOpcode() == ISD::SRA)
18192 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18195 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18196 // shifts per-lane and then shuffle the partial results back together.
18197 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18198 // Splat the shift amounts so the scalar shifts above will catch it.
18199 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18200 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18201 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18202 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18203 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18206 // i64 vector arithmetic shift can be emulated with the transform:
18207 // M = lshr(SIGN_BIT, Amt)
18208 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18209 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18210 Op.getOpcode() == ISD::SRA) {
18211 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18212 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18213 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18214 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18215 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18219 // If possible, lower this packed shift into a vector multiply instead of
18220 // expanding it into a sequence of scalar shifts.
18221 // Do this only if the vector shift count is a constant build_vector.
18222 if (Op.getOpcode() == ISD::SHL &&
18223 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18224 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18225 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18226 SmallVector<SDValue, 8> Elts;
18227 EVT SVT = VT.getScalarType();
18228 unsigned SVTBits = SVT.getSizeInBits();
18229 const APInt &One = APInt(SVTBits, 1);
18230 unsigned NumElems = VT.getVectorNumElements();
18232 for (unsigned i=0; i !=NumElems; ++i) {
18233 SDValue Op = Amt->getOperand(i);
18234 if (Op->getOpcode() == ISD::UNDEF) {
18235 Elts.push_back(Op);
18239 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18240 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18241 uint64_t ShAmt = C.getZExtValue();
18242 if (ShAmt >= SVTBits) {
18243 Elts.push_back(DAG.getUNDEF(SVT));
18246 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18248 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18249 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18252 // Lower SHL with variable shift amount.
18253 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18254 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18256 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18257 DAG.getConstant(0x3f800000U, dl, VT));
18258 Op = DAG.getBitcast(MVT::v4f32, Op);
18259 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18260 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18263 // If possible, lower this shift as a sequence of two shifts by
18264 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18266 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18268 // Could be rewritten as:
18269 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18271 // The advantage is that the two shifts from the example would be
18272 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18273 // the vector shift into four scalar shifts plus four pairs of vector
18275 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18276 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18277 unsigned TargetOpcode = X86ISD::MOVSS;
18278 bool CanBeSimplified;
18279 // The splat value for the first packed shift (the 'X' from the example).
18280 SDValue Amt1 = Amt->getOperand(0);
18281 // The splat value for the second packed shift (the 'Y' from the example).
18282 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18283 Amt->getOperand(2);
18285 // See if it is possible to replace this node with a sequence of
18286 // two shifts followed by a MOVSS/MOVSD
18287 if (VT == MVT::v4i32) {
18288 // Check if it is legal to use a MOVSS.
18289 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18290 Amt2 == Amt->getOperand(3);
18291 if (!CanBeSimplified) {
18292 // Otherwise, check if we can still simplify this node using a MOVSD.
18293 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18294 Amt->getOperand(2) == Amt->getOperand(3);
18295 TargetOpcode = X86ISD::MOVSD;
18296 Amt2 = Amt->getOperand(2);
18299 // Do similar checks for the case where the machine value type
18301 CanBeSimplified = Amt1 == Amt->getOperand(1);
18302 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18303 CanBeSimplified = Amt2 == Amt->getOperand(i);
18305 if (!CanBeSimplified) {
18306 TargetOpcode = X86ISD::MOVSD;
18307 CanBeSimplified = true;
18308 Amt2 = Amt->getOperand(4);
18309 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18310 CanBeSimplified = Amt1 == Amt->getOperand(i);
18311 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18312 CanBeSimplified = Amt2 == Amt->getOperand(j);
18316 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18317 isa<ConstantSDNode>(Amt2)) {
18318 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18319 EVT CastVT = MVT::v4i32;
18321 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18322 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18324 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18325 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18326 if (TargetOpcode == X86ISD::MOVSD)
18327 CastVT = MVT::v2i64;
18328 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18329 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18330 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18332 return DAG.getBitcast(VT, Result);
18336 // v4i32 Non Uniform Shifts.
18337 // If the shift amount is constant we can shift each lane using the SSE2
18338 // immediate shifts, else we need to zero-extend each lane to the lower i64
18339 // and shift using the SSE2 variable shifts.
18340 // The separate results can then be blended together.
18341 if (VT == MVT::v4i32) {
18342 unsigned Opc = Op.getOpcode();
18343 SDValue Amt0, Amt1, Amt2, Amt3;
18344 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18345 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18346 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18347 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18348 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18350 // ISD::SHL is handled above but we include it here for completeness.
18353 llvm_unreachable("Unknown target vector shift node");
18355 Opc = X86ISD::VSHL;
18358 Opc = X86ISD::VSRL;
18361 Opc = X86ISD::VSRA;
18364 // The SSE2 shifts use the lower i64 as the same shift amount for
18365 // all lanes and the upper i64 is ignored. These shuffle masks
18366 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18367 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18368 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18369 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18370 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18371 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18374 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18375 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18376 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18377 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18378 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18379 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18380 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18383 if (VT == MVT::v16i8 ||
18384 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18385 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18386 unsigned ShiftOpcode = Op->getOpcode();
18388 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18389 // On SSE41 targets we make use of the fact that VSELECT lowers
18390 // to PBLENDVB which selects bytes based just on the sign bit.
18391 if (Subtarget->hasSSE41()) {
18392 V0 = DAG.getBitcast(VT, V0);
18393 V1 = DAG.getBitcast(VT, V1);
18394 Sel = DAG.getBitcast(VT, Sel);
18395 return DAG.getBitcast(SelVT,
18396 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18398 // On pre-SSE41 targets we test for the sign bit by comparing to
18399 // zero - a negative value will set all bits of the lanes to true
18400 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18401 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18402 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18403 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18406 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18407 // We can safely do this using i16 shifts as we're only interested in
18408 // the 3 lower bits of each byte.
18409 Amt = DAG.getBitcast(ExtVT, Amt);
18410 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18411 Amt = DAG.getBitcast(VT, Amt);
18413 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18414 // r = VSELECT(r, shift(r, 4), a);
18416 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18417 R = SignBitSelect(VT, Amt, M, R);
18420 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18422 // r = VSELECT(r, shift(r, 2), a);
18423 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18424 R = SignBitSelect(VT, Amt, M, R);
18427 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18429 // return VSELECT(r, shift(r, 1), a);
18430 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18431 R = SignBitSelect(VT, Amt, M, R);
18435 if (Op->getOpcode() == ISD::SRA) {
18436 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18437 // so we can correctly sign extend. We don't care what happens to the
18439 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18440 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18441 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18442 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18443 ALo = DAG.getBitcast(ExtVT, ALo);
18444 AHi = DAG.getBitcast(ExtVT, AHi);
18445 RLo = DAG.getBitcast(ExtVT, RLo);
18446 RHi = DAG.getBitcast(ExtVT, RHi);
18448 // r = VSELECT(r, shift(r, 4), a);
18449 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18450 DAG.getConstant(4, dl, ExtVT));
18451 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18452 DAG.getConstant(4, dl, ExtVT));
18453 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18454 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18457 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18458 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18460 // r = VSELECT(r, shift(r, 2), a);
18461 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18462 DAG.getConstant(2, dl, ExtVT));
18463 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18464 DAG.getConstant(2, dl, ExtVT));
18465 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18466 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18469 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18470 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18472 // r = VSELECT(r, shift(r, 1), a);
18473 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18474 DAG.getConstant(1, dl, ExtVT));
18475 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18476 DAG.getConstant(1, dl, ExtVT));
18477 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18478 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18480 // Logical shift the result back to the lower byte, leaving a zero upper
18482 // meaning that we can safely pack with PACKUSWB.
18484 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18486 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18487 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18491 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18492 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18493 // solution better.
18494 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18495 MVT ExtVT = MVT::v8i32;
18497 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18498 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18499 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18500 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18501 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18504 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18505 MVT ExtVT = MVT::v8i32;
18506 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18507 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18508 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18509 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18510 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18511 ALo = DAG.getBitcast(ExtVT, ALo);
18512 AHi = DAG.getBitcast(ExtVT, AHi);
18513 RLo = DAG.getBitcast(ExtVT, RLo);
18514 RHi = DAG.getBitcast(ExtVT, RHi);
18515 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18516 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18517 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18518 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18519 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18522 if (VT == MVT::v8i16) {
18523 unsigned ShiftOpcode = Op->getOpcode();
18525 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18526 // On SSE41 targets we make use of the fact that VSELECT lowers
18527 // to PBLENDVB which selects bytes based just on the sign bit.
18528 if (Subtarget->hasSSE41()) {
18529 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18530 V0 = DAG.getBitcast(ExtVT, V0);
18531 V1 = DAG.getBitcast(ExtVT, V1);
18532 Sel = DAG.getBitcast(ExtVT, Sel);
18533 return DAG.getBitcast(
18534 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18536 // On pre-SSE41 targets we splat the sign bit - a negative value will
18537 // set all bits of the lanes to true and VSELECT uses that in
18538 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18540 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18541 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18544 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18545 if (Subtarget->hasSSE41()) {
18546 // On SSE41 targets we need to replicate the shift mask in both
18547 // bytes for PBLENDVB.
18550 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18551 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18553 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18556 // r = VSELECT(r, shift(r, 8), a);
18557 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18558 R = SignBitSelect(Amt, M, R);
18561 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18563 // r = VSELECT(r, shift(r, 4), a);
18564 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18565 R = SignBitSelect(Amt, M, R);
18568 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18570 // r = VSELECT(r, shift(r, 2), a);
18571 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18572 R = SignBitSelect(Amt, M, R);
18575 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18577 // return VSELECT(r, shift(r, 1), a);
18578 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18579 R = SignBitSelect(Amt, M, R);
18583 // Decompose 256-bit shifts into smaller 128-bit shifts.
18584 if (VT.is256BitVector()) {
18585 unsigned NumElems = VT.getVectorNumElements();
18586 MVT EltVT = VT.getVectorElementType();
18587 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18589 // Extract the two vectors
18590 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18591 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18593 // Recreate the shift amount vectors
18594 SDValue Amt1, Amt2;
18595 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18596 // Constant shift amount
18597 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18598 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18599 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18601 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18602 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18604 // Variable shift amount
18605 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18606 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18609 // Issue new vector shifts for the smaller types
18610 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18611 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18613 // Concatenate the result back
18614 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18620 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18621 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18622 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18623 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18624 // has only one use.
18625 SDNode *N = Op.getNode();
18626 SDValue LHS = N->getOperand(0);
18627 SDValue RHS = N->getOperand(1);
18628 unsigned BaseOp = 0;
18631 switch (Op.getOpcode()) {
18632 default: llvm_unreachable("Unknown ovf instruction!");
18634 // A subtract of one will be selected as a INC. Note that INC doesn't
18635 // set CF, so we can't do this for UADDO.
18636 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18638 BaseOp = X86ISD::INC;
18639 Cond = X86::COND_O;
18642 BaseOp = X86ISD::ADD;
18643 Cond = X86::COND_O;
18646 BaseOp = X86ISD::ADD;
18647 Cond = X86::COND_B;
18650 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18651 // set CF, so we can't do this for USUBO.
18652 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18654 BaseOp = X86ISD::DEC;
18655 Cond = X86::COND_O;
18658 BaseOp = X86ISD::SUB;
18659 Cond = X86::COND_O;
18662 BaseOp = X86ISD::SUB;
18663 Cond = X86::COND_B;
18666 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18667 Cond = X86::COND_O;
18669 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18670 if (N->getValueType(0) == MVT::i8) {
18671 BaseOp = X86ISD::UMUL8;
18672 Cond = X86::COND_O;
18675 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18677 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18680 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18681 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18682 SDValue(Sum.getNode(), 2));
18684 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18688 // Also sets EFLAGS.
18689 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18690 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18693 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18694 DAG.getConstant(Cond, DL, MVT::i32),
18695 SDValue(Sum.getNode(), 1));
18697 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18700 /// Returns true if the operand type is exactly twice the native width, and
18701 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18702 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18703 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18704 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18705 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18708 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18709 else if (OpWidth == 128)
18710 return Subtarget->hasCmpxchg16b();
18715 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18716 return needsCmpXchgNb(SI->getValueOperand()->getType());
18719 // Note: this turns large loads into lock cmpxchg8b/16b.
18720 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18721 TargetLowering::AtomicExpansionKind
18722 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18723 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18724 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18725 : AtomicExpansionKind::None;
18728 TargetLowering::AtomicExpansionKind
18729 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18730 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18731 Type *MemType = AI->getType();
18733 // If the operand is too big, we must see if cmpxchg8/16b is available
18734 // and default to library calls otherwise.
18735 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18736 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18737 : AtomicExpansionKind::None;
18740 AtomicRMWInst::BinOp Op = AI->getOperation();
18743 llvm_unreachable("Unknown atomic operation");
18744 case AtomicRMWInst::Xchg:
18745 case AtomicRMWInst::Add:
18746 case AtomicRMWInst::Sub:
18747 // It's better to use xadd, xsub or xchg for these in all cases.
18748 return AtomicExpansionKind::None;
18749 case AtomicRMWInst::Or:
18750 case AtomicRMWInst::And:
18751 case AtomicRMWInst::Xor:
18752 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18753 // prefix to a normal instruction for these operations.
18754 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18755 : AtomicExpansionKind::None;
18756 case AtomicRMWInst::Nand:
18757 case AtomicRMWInst::Max:
18758 case AtomicRMWInst::Min:
18759 case AtomicRMWInst::UMax:
18760 case AtomicRMWInst::UMin:
18761 // These always require a non-trivial set of data operations on x86. We must
18762 // use a cmpxchg loop.
18763 return AtomicExpansionKind::CmpXChg;
18767 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18768 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18769 // no-sse2). There isn't any reason to disable it if the target processor
18771 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18775 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18776 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18777 Type *MemType = AI->getType();
18778 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18779 // there is no benefit in turning such RMWs into loads, and it is actually
18780 // harmful as it introduces a mfence.
18781 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18784 auto Builder = IRBuilder<>(AI);
18785 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18786 auto SynchScope = AI->getSynchScope();
18787 // We must restrict the ordering to avoid generating loads with Release or
18788 // ReleaseAcquire orderings.
18789 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18790 auto Ptr = AI->getPointerOperand();
18792 // Before the load we need a fence. Here is an example lifted from
18793 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18796 // x.store(1, relaxed);
18797 // r1 = y.fetch_add(0, release);
18799 // y.fetch_add(42, acquire);
18800 // r2 = x.load(relaxed);
18801 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18802 // lowered to just a load without a fence. A mfence flushes the store buffer,
18803 // making the optimization clearly correct.
18804 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18805 // otherwise, we might be able to be more aggressive on relaxed idempotent
18806 // rmw. In practice, they do not look useful, so we don't try to be
18807 // especially clever.
18808 if (SynchScope == SingleThread)
18809 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18810 // the IR level, so we must wrap it in an intrinsic.
18813 if (!hasMFENCE(*Subtarget))
18814 // FIXME: it might make sense to use a locked operation here but on a
18815 // different cache-line to prevent cache-line bouncing. In practice it
18816 // is probably a small win, and x86 processors without mfence are rare
18817 // enough that we do not bother.
18821 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
18822 Builder.CreateCall(MFence, {});
18824 // Finally we can emit the atomic load.
18825 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18826 AI->getType()->getPrimitiveSizeInBits());
18827 Loaded->setAtomic(Order, SynchScope);
18828 AI->replaceAllUsesWith(Loaded);
18829 AI->eraseFromParent();
18833 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18834 SelectionDAG &DAG) {
18836 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18837 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18838 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18839 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18841 // The only fence that needs an instruction is a sequentially-consistent
18842 // cross-thread fence.
18843 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18844 if (hasMFENCE(*Subtarget))
18845 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18847 SDValue Chain = Op.getOperand(0);
18848 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
18850 DAG.getRegister(X86::ESP, MVT::i32), // Base
18851 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
18852 DAG.getRegister(0, MVT::i32), // Index
18853 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
18854 DAG.getRegister(0, MVT::i32), // Segment.
18858 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18859 return SDValue(Res, 0);
18862 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18863 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18866 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18867 SelectionDAG &DAG) {
18868 MVT T = Op.getSimpleValueType();
18872 switch(T.SimpleTy) {
18873 default: llvm_unreachable("Invalid value type!");
18874 case MVT::i8: Reg = X86::AL; size = 1; break;
18875 case MVT::i16: Reg = X86::AX; size = 2; break;
18876 case MVT::i32: Reg = X86::EAX; size = 4; break;
18878 assert(Subtarget->is64Bit() && "Node not type legal!");
18879 Reg = X86::RAX; size = 8;
18882 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18883 Op.getOperand(2), SDValue());
18884 SDValue Ops[] = { cpIn.getValue(0),
18887 DAG.getTargetConstant(size, DL, MVT::i8),
18888 cpIn.getValue(1) };
18889 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18890 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18891 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18895 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18896 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18897 MVT::i32, cpOut.getValue(2));
18898 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18899 DAG.getConstant(X86::COND_E, DL, MVT::i8),
18902 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18903 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18904 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18908 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18909 SelectionDAG &DAG) {
18910 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18911 MVT DstVT = Op.getSimpleValueType();
18913 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18914 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18915 if (DstVT != MVT::f64)
18916 // This conversion needs to be expanded.
18919 SDValue InVec = Op->getOperand(0);
18921 unsigned NumElts = SrcVT.getVectorNumElements();
18922 EVT SVT = SrcVT.getVectorElementType();
18924 // Widen the vector in input in the case of MVT::v2i32.
18925 // Example: from MVT::v2i32 to MVT::v4i32.
18926 SmallVector<SDValue, 16> Elts;
18927 for (unsigned i = 0, e = NumElts; i != e; ++i)
18928 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18929 DAG.getIntPtrConstant(i, dl)));
18931 // Explicitly mark the extra elements as Undef.
18932 Elts.append(NumElts, DAG.getUNDEF(SVT));
18934 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18935 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18936 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
18937 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18938 DAG.getIntPtrConstant(0, dl));
18941 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18942 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18943 assert((DstVT == MVT::i64 ||
18944 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18945 "Unexpected custom BITCAST");
18946 // i64 <=> MMX conversions are Legal.
18947 if (SrcVT==MVT::i64 && DstVT.isVector())
18949 if (DstVT==MVT::i64 && SrcVT.isVector())
18951 // MMX <=> MMX conversions are Legal.
18952 if (SrcVT.isVector() && DstVT.isVector())
18954 // All other conversions need to be expanded.
18958 /// Compute the horizontal sum of bytes in V for the elements of VT.
18960 /// Requires V to be a byte vector and VT to be an integer vector type with
18961 /// wider elements than V's type. The width of the elements of VT determines
18962 /// how many bytes of V are summed horizontally to produce each element of the
18964 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
18965 const X86Subtarget *Subtarget,
18966 SelectionDAG &DAG) {
18968 MVT ByteVecVT = V.getSimpleValueType();
18969 MVT EltVT = VT.getVectorElementType();
18970 int NumElts = VT.getVectorNumElements();
18971 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
18972 "Expected value to have byte element type.");
18973 assert(EltVT != MVT::i8 &&
18974 "Horizontal byte sum only makes sense for wider elements!");
18975 unsigned VecSize = VT.getSizeInBits();
18976 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
18978 // PSADBW instruction horizontally add all bytes and leave the result in i64
18979 // chunks, thus directly computes the pop count for v2i64 and v4i64.
18980 if (EltVT == MVT::i64) {
18981 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18982 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
18983 return DAG.getBitcast(VT, V);
18986 if (EltVT == MVT::i32) {
18987 // We unpack the low half and high half into i32s interleaved with zeros so
18988 // that we can use PSADBW to horizontally sum them. The most useful part of
18989 // this is that it lines up the results of two PSADBW instructions to be
18990 // two v2i64 vectors which concatenated are the 4 population counts. We can
18991 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
18992 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
18993 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
18994 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
18996 // Do the horizontal sums into two v2i64s.
18997 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
18998 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
18999 DAG.getBitcast(ByteVecVT, Low), Zeros);
19000 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19001 DAG.getBitcast(ByteVecVT, High), Zeros);
19003 // Merge them together.
19004 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19005 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19006 DAG.getBitcast(ShortVecVT, Low),
19007 DAG.getBitcast(ShortVecVT, High));
19009 return DAG.getBitcast(VT, V);
19012 // The only element type left is i16.
19013 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19015 // To obtain pop count for each i16 element starting from the pop count for
19016 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19017 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19018 // directly supported.
19019 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19020 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19021 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19022 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19023 DAG.getBitcast(ByteVecVT, V));
19024 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19027 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19028 const X86Subtarget *Subtarget,
19029 SelectionDAG &DAG) {
19030 MVT VT = Op.getSimpleValueType();
19031 MVT EltVT = VT.getVectorElementType();
19032 unsigned VecSize = VT.getSizeInBits();
19034 // Implement a lookup table in register by using an algorithm based on:
19035 // http://wm.ite.pl/articles/sse-popcount.html
19037 // The general idea is that every lower byte nibble in the input vector is an
19038 // index into a in-register pre-computed pop count table. We then split up the
19039 // input vector in two new ones: (1) a vector with only the shifted-right
19040 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19041 // masked out higher ones) for each byte. PSHUB is used separately with both
19042 // to index the in-register table. Next, both are added and the result is a
19043 // i8 vector where each element contains the pop count for input byte.
19045 // To obtain the pop count for elements != i8, we follow up with the same
19046 // approach and use additional tricks as described below.
19048 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19049 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19050 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19051 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19053 int NumByteElts = VecSize / 8;
19054 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19055 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19056 SmallVector<SDValue, 16> LUTVec;
19057 for (int i = 0; i < NumByteElts; ++i)
19058 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19059 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19060 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19061 DAG.getConstant(0x0F, DL, MVT::i8));
19062 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19065 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19066 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19067 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19070 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19072 // The input vector is used as the shuffle mask that index elements into the
19073 // LUT. After counting low and high nibbles, add the vector to obtain the
19074 // final pop count per i8 element.
19075 SDValue HighPopCnt =
19076 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19077 SDValue LowPopCnt =
19078 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19079 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19081 if (EltVT == MVT::i8)
19084 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19087 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19088 const X86Subtarget *Subtarget,
19089 SelectionDAG &DAG) {
19090 MVT VT = Op.getSimpleValueType();
19091 assert(VT.is128BitVector() &&
19092 "Only 128-bit vector bitmath lowering supported.");
19094 int VecSize = VT.getSizeInBits();
19095 MVT EltVT = VT.getVectorElementType();
19096 int Len = EltVT.getSizeInBits();
19098 // This is the vectorized version of the "best" algorithm from
19099 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19100 // with a minor tweak to use a series of adds + shifts instead of vector
19101 // multiplications. Implemented for all integer vector types. We only use
19102 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19103 // much faster, even faster than using native popcnt instructions.
19105 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19106 MVT VT = V.getSimpleValueType();
19107 SmallVector<SDValue, 32> Shifters(
19108 VT.getVectorNumElements(),
19109 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19110 return DAG.getNode(OpCode, DL, VT, V,
19111 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19113 auto GetMask = [&](SDValue V, APInt Mask) {
19114 MVT VT = V.getSimpleValueType();
19115 SmallVector<SDValue, 32> Masks(
19116 VT.getVectorNumElements(),
19117 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19118 return DAG.getNode(ISD::AND, DL, VT, V,
19119 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19122 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19123 // x86, so set the SRL type to have elements at least i16 wide. This is
19124 // correct because all of our SRLs are followed immediately by a mask anyways
19125 // that handles any bits that sneak into the high bits of the byte elements.
19126 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19130 // v = v - ((v >> 1) & 0x55555555...)
19132 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19133 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19134 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19136 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19137 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19138 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19139 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19140 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19142 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19143 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19144 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19145 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19147 // At this point, V contains the byte-wise population count, and we are
19148 // merely doing a horizontal sum if necessary to get the wider element
19150 if (EltVT == MVT::i8)
19153 return LowerHorizontalByteSum(
19154 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19158 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19159 SelectionDAG &DAG) {
19160 MVT VT = Op.getSimpleValueType();
19161 // FIXME: Need to add AVX-512 support here!
19162 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19163 "Unknown CTPOP type to handle");
19164 SDLoc DL(Op.getNode());
19165 SDValue Op0 = Op.getOperand(0);
19167 if (!Subtarget->hasSSSE3()) {
19168 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19169 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19170 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19173 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19174 unsigned NumElems = VT.getVectorNumElements();
19176 // Extract each 128-bit vector, compute pop count and concat the result.
19177 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19178 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19180 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19181 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19182 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19185 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19188 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19189 SelectionDAG &DAG) {
19190 assert(Op.getValueType().isVector() &&
19191 "We only do custom lowering for vector population count.");
19192 return LowerVectorCTPOP(Op, Subtarget, DAG);
19195 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19196 SDNode *Node = Op.getNode();
19198 EVT T = Node->getValueType(0);
19199 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19200 DAG.getConstant(0, dl, T), Node->getOperand(2));
19201 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19202 cast<AtomicSDNode>(Node)->getMemoryVT(),
19203 Node->getOperand(0),
19204 Node->getOperand(1), negOp,
19205 cast<AtomicSDNode>(Node)->getMemOperand(),
19206 cast<AtomicSDNode>(Node)->getOrdering(),
19207 cast<AtomicSDNode>(Node)->getSynchScope());
19210 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19211 SDNode *Node = Op.getNode();
19213 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19215 // Convert seq_cst store -> xchg
19216 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19217 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19218 // (The only way to get a 16-byte store is cmpxchg16b)
19219 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19220 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19221 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19222 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19223 cast<AtomicSDNode>(Node)->getMemoryVT(),
19224 Node->getOperand(0),
19225 Node->getOperand(1), Node->getOperand(2),
19226 cast<AtomicSDNode>(Node)->getMemOperand(),
19227 cast<AtomicSDNode>(Node)->getOrdering(),
19228 cast<AtomicSDNode>(Node)->getSynchScope());
19229 return Swap.getValue(1);
19231 // Other atomic stores have a simple pattern.
19235 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19236 EVT VT = Op.getNode()->getSimpleValueType(0);
19238 // Let legalize expand this if it isn't a legal type yet.
19239 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19242 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19245 bool ExtraOp = false;
19246 switch (Op.getOpcode()) {
19247 default: llvm_unreachable("Invalid code");
19248 case ISD::ADDC: Opc = X86ISD::ADD; break;
19249 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19250 case ISD::SUBC: Opc = X86ISD::SUB; break;
19251 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19255 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19257 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19258 Op.getOperand(1), Op.getOperand(2));
19261 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19262 SelectionDAG &DAG) {
19263 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19265 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19266 // which returns the values as { float, float } (in XMM0) or
19267 // { double, double } (which is returned in XMM0, XMM1).
19269 SDValue Arg = Op.getOperand(0);
19270 EVT ArgVT = Arg.getValueType();
19271 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19273 TargetLowering::ArgListTy Args;
19274 TargetLowering::ArgListEntry Entry;
19278 Entry.isSExt = false;
19279 Entry.isZExt = false;
19280 Args.push_back(Entry);
19282 bool isF64 = ArgVT == MVT::f64;
19283 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19284 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19285 // the results are returned via SRet in memory.
19286 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19287 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19289 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19291 Type *RetTy = isF64
19292 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19293 : (Type*)VectorType::get(ArgTy, 4);
19295 TargetLowering::CallLoweringInfo CLI(DAG);
19296 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19297 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19299 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19302 // Returned in xmm0 and xmm1.
19303 return CallResult.first;
19305 // Returned in bits 0:31 and 32:64 xmm0.
19306 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19307 CallResult.first, DAG.getIntPtrConstant(0, dl));
19308 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19309 CallResult.first, DAG.getIntPtrConstant(1, dl));
19310 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19311 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19314 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19315 SelectionDAG &DAG) {
19316 assert(Subtarget->hasAVX512() &&
19317 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19319 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19320 EVT VT = N->getValue().getValueType();
19321 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19324 // X86 scatter kills mask register, so its type should be added to
19325 // the list of return values
19326 if (N->getNumValues() == 1) {
19327 SDValue Index = N->getIndex();
19328 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19329 !Index.getValueType().is512BitVector())
19330 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19332 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19333 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19334 N->getOperand(3), Index };
19336 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19337 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19338 return SDValue(NewScatter.getNode(), 0);
19343 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19344 SelectionDAG &DAG) {
19345 assert(Subtarget->hasAVX512() &&
19346 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19348 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19349 EVT VT = Op.getValueType();
19350 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19353 SDValue Index = N->getIndex();
19354 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19355 !Index.getValueType().is512BitVector()) {
19356 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19357 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19358 N->getOperand(3), Index };
19359 DAG.UpdateNodeOperands(N, Ops);
19364 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19365 SelectionDAG &DAG) const {
19366 // TODO: Eventually, the lowering of these nodes should be informed by or
19367 // deferred to the GC strategy for the function in which they appear. For
19368 // now, however, they must be lowered to something. Since they are logically
19369 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19370 // require special handling for these nodes), lower them as literal NOOPs for
19372 SmallVector<SDValue, 2> Ops;
19374 Ops.push_back(Op.getOperand(0));
19375 if (Op->getGluedNode())
19376 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19379 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19380 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19385 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19386 SelectionDAG &DAG) const {
19387 // TODO: Eventually, the lowering of these nodes should be informed by or
19388 // deferred to the GC strategy for the function in which they appear. For
19389 // now, however, they must be lowered to something. Since they are logically
19390 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19391 // require special handling for these nodes), lower them as literal NOOPs for
19393 SmallVector<SDValue, 2> Ops;
19395 Ops.push_back(Op.getOperand(0));
19396 if (Op->getGluedNode())
19397 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19400 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19401 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19406 /// LowerOperation - Provide custom lowering hooks for some operations.
19408 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19409 switch (Op.getOpcode()) {
19410 default: llvm_unreachable("Should not custom lower this!");
19411 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19412 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19413 return LowerCMP_SWAP(Op, Subtarget, DAG);
19414 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19415 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19416 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19417 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19418 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19419 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19420 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19421 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19422 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19423 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19424 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19425 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19426 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19427 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19428 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19429 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19430 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19431 case ISD::SHL_PARTS:
19432 case ISD::SRA_PARTS:
19433 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19434 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19435 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19436 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19437 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19438 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19439 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19440 case ISD::SIGN_EXTEND_VECTOR_INREG:
19441 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19442 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19443 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19444 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19445 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19447 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19448 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19449 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19450 case ISD::SETCC: return LowerSETCC(Op, DAG);
19451 case ISD::SELECT: return LowerSELECT(Op, DAG);
19452 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19453 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19454 case ISD::VASTART: return LowerVASTART(Op, DAG);
19455 case ISD::VAARG: return LowerVAARG(Op, DAG);
19456 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19457 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19458 case ISD::INTRINSIC_VOID:
19459 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19460 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19461 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19462 case ISD::FRAME_TO_ARGS_OFFSET:
19463 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19464 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19465 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19466 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19467 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19468 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19469 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19470 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19471 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19472 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19474 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19475 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19476 case ISD::UMUL_LOHI:
19477 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19480 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19486 case ISD::UMULO: return LowerXALUO(Op, DAG);
19487 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19488 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19492 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19493 case ISD::ADD: return LowerADD(Op, DAG);
19494 case ISD::SUB: return LowerSUB(Op, DAG);
19498 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19499 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19500 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19501 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19502 case ISD::GC_TRANSITION_START:
19503 return LowerGC_TRANSITION_START(Op, DAG);
19504 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19508 /// ReplaceNodeResults - Replace a node with an illegal result type
19509 /// with a new node built out of custom code.
19510 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19511 SmallVectorImpl<SDValue>&Results,
19512 SelectionDAG &DAG) const {
19514 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19515 switch (N->getOpcode()) {
19517 llvm_unreachable("Do not know how to custom type legalize this operation!");
19518 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19519 case X86ISD::FMINC:
19521 case X86ISD::FMAXC:
19522 case X86ISD::FMAX: {
19523 EVT VT = N->getValueType(0);
19524 if (VT != MVT::v2f32)
19525 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19526 SDValue UNDEF = DAG.getUNDEF(VT);
19527 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19528 N->getOperand(0), UNDEF);
19529 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19530 N->getOperand(1), UNDEF);
19531 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19534 case ISD::SIGN_EXTEND_INREG:
19539 // We don't want to expand or promote these.
19546 case ISD::UDIVREM: {
19547 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19548 Results.push_back(V);
19551 case ISD::FP_TO_SINT:
19552 case ISD::FP_TO_UINT: {
19553 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19555 std::pair<SDValue,SDValue> Vals =
19556 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19557 SDValue FIST = Vals.first, StackSlot = Vals.second;
19558 if (FIST.getNode()) {
19559 EVT VT = N->getValueType(0);
19560 // Return a load from the stack slot.
19561 if (StackSlot.getNode())
19562 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19563 MachinePointerInfo(),
19564 false, false, false, 0));
19566 Results.push_back(FIST);
19570 case ISD::UINT_TO_FP: {
19571 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19572 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19573 N->getValueType(0) != MVT::v2f32)
19575 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19577 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19579 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19580 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19581 DAG.getBitcast(MVT::v2i64, VBias));
19582 Or = DAG.getBitcast(MVT::v2f64, Or);
19583 // TODO: Are there any fast-math-flags to propagate here?
19584 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19585 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19588 case ISD::FP_ROUND: {
19589 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19591 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19592 Results.push_back(V);
19595 case ISD::FP_EXTEND: {
19596 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19597 // No other ValueType for FP_EXTEND should reach this point.
19598 assert(N->getValueType(0) == MVT::v2f32 &&
19599 "Do not know how to legalize this Node");
19602 case ISD::INTRINSIC_W_CHAIN: {
19603 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19605 default : llvm_unreachable("Do not know how to custom type "
19606 "legalize this intrinsic operation!");
19607 case Intrinsic::x86_rdtsc:
19608 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19610 case Intrinsic::x86_rdtscp:
19611 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19613 case Intrinsic::x86_rdpmc:
19614 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19617 case ISD::READCYCLECOUNTER: {
19618 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19621 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19622 EVT T = N->getValueType(0);
19623 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19624 bool Regs64bit = T == MVT::i128;
19625 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19626 SDValue cpInL, cpInH;
19627 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19628 DAG.getConstant(0, dl, HalfT));
19629 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19630 DAG.getConstant(1, dl, HalfT));
19631 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19632 Regs64bit ? X86::RAX : X86::EAX,
19634 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19635 Regs64bit ? X86::RDX : X86::EDX,
19636 cpInH, cpInL.getValue(1));
19637 SDValue swapInL, swapInH;
19638 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19639 DAG.getConstant(0, dl, HalfT));
19640 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19641 DAG.getConstant(1, dl, HalfT));
19642 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19643 Regs64bit ? X86::RBX : X86::EBX,
19644 swapInL, cpInH.getValue(1));
19645 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19646 Regs64bit ? X86::RCX : X86::ECX,
19647 swapInH, swapInL.getValue(1));
19648 SDValue Ops[] = { swapInH.getValue(0),
19650 swapInH.getValue(1) };
19651 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19652 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19653 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19654 X86ISD::LCMPXCHG8_DAG;
19655 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19656 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19657 Regs64bit ? X86::RAX : X86::EAX,
19658 HalfT, Result.getValue(1));
19659 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19660 Regs64bit ? X86::RDX : X86::EDX,
19661 HalfT, cpOutL.getValue(2));
19662 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19664 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19665 MVT::i32, cpOutH.getValue(2));
19667 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19668 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19669 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19671 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19672 Results.push_back(Success);
19673 Results.push_back(EFLAGS.getValue(1));
19676 case ISD::ATOMIC_SWAP:
19677 case ISD::ATOMIC_LOAD_ADD:
19678 case ISD::ATOMIC_LOAD_SUB:
19679 case ISD::ATOMIC_LOAD_AND:
19680 case ISD::ATOMIC_LOAD_OR:
19681 case ISD::ATOMIC_LOAD_XOR:
19682 case ISD::ATOMIC_LOAD_NAND:
19683 case ISD::ATOMIC_LOAD_MIN:
19684 case ISD::ATOMIC_LOAD_MAX:
19685 case ISD::ATOMIC_LOAD_UMIN:
19686 case ISD::ATOMIC_LOAD_UMAX:
19687 case ISD::ATOMIC_LOAD: {
19688 // Delegate to generic TypeLegalization. Situations we can really handle
19689 // should have already been dealt with by AtomicExpandPass.cpp.
19692 case ISD::BITCAST: {
19693 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19694 EVT DstVT = N->getValueType(0);
19695 EVT SrcVT = N->getOperand(0)->getValueType(0);
19697 if (SrcVT != MVT::f64 ||
19698 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19701 unsigned NumElts = DstVT.getVectorNumElements();
19702 EVT SVT = DstVT.getVectorElementType();
19703 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19704 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19705 MVT::v2f64, N->getOperand(0));
19706 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19708 if (ExperimentalVectorWideningLegalization) {
19709 // If we are legalizing vectors by widening, we already have the desired
19710 // legal vector type, just return it.
19711 Results.push_back(ToVecInt);
19715 SmallVector<SDValue, 8> Elts;
19716 for (unsigned i = 0, e = NumElts; i != e; ++i)
19717 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19718 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19720 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19725 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19726 switch ((X86ISD::NodeType)Opcode) {
19727 case X86ISD::FIRST_NUMBER: break;
19728 case X86ISD::BSF: return "X86ISD::BSF";
19729 case X86ISD::BSR: return "X86ISD::BSR";
19730 case X86ISD::SHLD: return "X86ISD::SHLD";
19731 case X86ISD::SHRD: return "X86ISD::SHRD";
19732 case X86ISD::FAND: return "X86ISD::FAND";
19733 case X86ISD::FANDN: return "X86ISD::FANDN";
19734 case X86ISD::FOR: return "X86ISD::FOR";
19735 case X86ISD::FXOR: return "X86ISD::FXOR";
19736 case X86ISD::FILD: return "X86ISD::FILD";
19737 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19738 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19739 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19740 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19741 case X86ISD::FLD: return "X86ISD::FLD";
19742 case X86ISD::FST: return "X86ISD::FST";
19743 case X86ISD::CALL: return "X86ISD::CALL";
19744 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19745 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19746 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19747 case X86ISD::BT: return "X86ISD::BT";
19748 case X86ISD::CMP: return "X86ISD::CMP";
19749 case X86ISD::COMI: return "X86ISD::COMI";
19750 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19751 case X86ISD::CMPM: return "X86ISD::CMPM";
19752 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19753 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19754 case X86ISD::SETCC: return "X86ISD::SETCC";
19755 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19756 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19757 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19758 case X86ISD::CMOV: return "X86ISD::CMOV";
19759 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19760 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19761 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19762 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19763 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19764 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19765 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19766 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19767 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19768 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19769 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19770 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19771 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19772 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19773 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19774 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19775 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19776 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19777 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19778 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19779 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19780 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19781 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19782 case X86ISD::HADD: return "X86ISD::HADD";
19783 case X86ISD::HSUB: return "X86ISD::HSUB";
19784 case X86ISD::FHADD: return "X86ISD::FHADD";
19785 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19786 case X86ISD::ABS: return "X86ISD::ABS";
19787 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19788 case X86ISD::FMAX: return "X86ISD::FMAX";
19789 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19790 case X86ISD::FMIN: return "X86ISD::FMIN";
19791 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19792 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19793 case X86ISD::FMINC: return "X86ISD::FMINC";
19794 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19795 case X86ISD::FRCP: return "X86ISD::FRCP";
19796 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19797 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19798 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19799 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19800 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19801 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19802 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19803 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19804 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19805 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19806 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19807 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19808 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19809 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19810 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19811 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19812 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19813 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19814 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19815 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
19816 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
19817 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19818 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19819 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19820 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
19821 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
19822 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19823 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19824 case X86ISD::VSHL: return "X86ISD::VSHL";
19825 case X86ISD::VSRL: return "X86ISD::VSRL";
19826 case X86ISD::VSRA: return "X86ISD::VSRA";
19827 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19828 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19829 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19830 case X86ISD::CMPP: return "X86ISD::CMPP";
19831 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19832 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19833 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19834 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19835 case X86ISD::ADD: return "X86ISD::ADD";
19836 case X86ISD::SUB: return "X86ISD::SUB";
19837 case X86ISD::ADC: return "X86ISD::ADC";
19838 case X86ISD::SBB: return "X86ISD::SBB";
19839 case X86ISD::SMUL: return "X86ISD::SMUL";
19840 case X86ISD::UMUL: return "X86ISD::UMUL";
19841 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19842 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19843 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19844 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19845 case X86ISD::INC: return "X86ISD::INC";
19846 case X86ISD::DEC: return "X86ISD::DEC";
19847 case X86ISD::OR: return "X86ISD::OR";
19848 case X86ISD::XOR: return "X86ISD::XOR";
19849 case X86ISD::AND: return "X86ISD::AND";
19850 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19851 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19852 case X86ISD::PTEST: return "X86ISD::PTEST";
19853 case X86ISD::TESTP: return "X86ISD::TESTP";
19854 case X86ISD::TESTM: return "X86ISD::TESTM";
19855 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19856 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19857 case X86ISD::KTEST: return "X86ISD::KTEST";
19858 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19859 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19860 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19861 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19862 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19863 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19864 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19865 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19866 case X86ISD::SHUF128: return "X86ISD::SHUF128";
19867 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19868 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19869 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19870 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19871 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19872 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19873 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19874 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19875 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19876 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19877 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19878 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19879 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19880 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
19881 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19882 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
19883 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19884 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19885 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19886 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19887 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19888 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19889 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
19890 case X86ISD::VRANGE: return "X86ISD::VRANGE";
19891 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19892 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19893 case X86ISD::PSADBW: return "X86ISD::PSADBW";
19894 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
19895 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19896 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19897 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19898 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19899 case X86ISD::MFENCE: return "X86ISD::MFENCE";
19900 case X86ISD::SFENCE: return "X86ISD::SFENCE";
19901 case X86ISD::LFENCE: return "X86ISD::LFENCE";
19902 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19903 case X86ISD::SAHF: return "X86ISD::SAHF";
19904 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19905 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19906 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
19907 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
19908 case X86ISD::VPSHA: return "X86ISD::VPSHA";
19909 case X86ISD::VPSHL: return "X86ISD::VPSHL";
19910 case X86ISD::VPCOM: return "X86ISD::VPCOM";
19911 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
19912 case X86ISD::FMADD: return "X86ISD::FMADD";
19913 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19914 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19915 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19916 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19917 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19918 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
19919 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
19920 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
19921 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
19922 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
19923 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
19924 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
19925 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
19926 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
19927 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19928 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19929 case X86ISD::XTEST: return "X86ISD::XTEST";
19930 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19931 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19932 case X86ISD::SELECT: return "X86ISD::SELECT";
19933 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
19934 case X86ISD::RCP28: return "X86ISD::RCP28";
19935 case X86ISD::EXP2: return "X86ISD::EXP2";
19936 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
19937 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
19938 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
19939 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
19940 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
19941 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
19942 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
19943 case X86ISD::SCALEF: return "X86ISD::SCALEF";
19944 case X86ISD::ADDS: return "X86ISD::ADDS";
19945 case X86ISD::SUBS: return "X86ISD::SUBS";
19946 case X86ISD::AVG: return "X86ISD::AVG";
19947 case X86ISD::MULHRS: return "X86ISD::MULHRS";
19948 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
19949 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
19950 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
19951 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
19952 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
19957 // isLegalAddressingMode - Return true if the addressing mode represented
19958 // by AM is legal for this target, for a load/store of the specified type.
19959 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
19960 const AddrMode &AM, Type *Ty,
19961 unsigned AS) const {
19962 // X86 supports extremely general addressing modes.
19963 CodeModel::Model M = getTargetMachine().getCodeModel();
19964 Reloc::Model R = getTargetMachine().getRelocationModel();
19966 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19967 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19972 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19974 // If a reference to this global requires an extra load, we can't fold it.
19975 if (isGlobalStubReference(GVFlags))
19978 // If BaseGV requires a register for the PIC base, we cannot also have a
19979 // BaseReg specified.
19980 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19983 // If lower 4G is not available, then we must use rip-relative addressing.
19984 if ((M != CodeModel::Small || R != Reloc::Static) &&
19985 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19989 switch (AM.Scale) {
19995 // These scales always work.
20000 // These scales are formed with basereg+scalereg. Only accept if there is
20005 default: // Other stuff never works.
20012 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20013 unsigned Bits = Ty->getScalarSizeInBits();
20015 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20016 // particularly cheaper than those without.
20020 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20021 // variable shifts just as cheap as scalar ones.
20022 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20025 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20026 // fully general vector.
20030 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20031 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20033 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20034 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20035 return NumBits1 > NumBits2;
20038 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20039 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20042 if (!isTypeLegal(EVT::getEVT(Ty1)))
20045 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20047 // Assuming the caller doesn't have a zeroext or signext return parameter,
20048 // truncation all the way down to i1 is valid.
20052 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20053 return isInt<32>(Imm);
20056 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20057 // Can also use sub to handle negated immediates.
20058 return isInt<32>(Imm);
20061 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20062 if (!VT1.isInteger() || !VT2.isInteger())
20064 unsigned NumBits1 = VT1.getSizeInBits();
20065 unsigned NumBits2 = VT2.getSizeInBits();
20066 return NumBits1 > NumBits2;
20069 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20070 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20071 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20074 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20075 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20076 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20079 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20080 EVT VT1 = Val.getValueType();
20081 if (isZExtFree(VT1, VT2))
20084 if (Val.getOpcode() != ISD::LOAD)
20087 if (!VT1.isSimple() || !VT1.isInteger() ||
20088 !VT2.isSimple() || !VT2.isInteger())
20091 switch (VT1.getSimpleVT().SimpleTy) {
20096 // X86 has 8, 16, and 32-bit zero-extending loads.
20103 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20106 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20107 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20110 VT = VT.getScalarType();
20112 if (!VT.isSimple())
20115 switch (VT.getSimpleVT().SimpleTy) {
20126 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20127 // i16 instructions are longer (0x66 prefix) and potentially slower.
20128 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20131 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20132 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20133 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20134 /// are assumed to be legal.
20136 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20138 if (!VT.isSimple())
20141 // Not for i1 vectors
20142 if (VT.getScalarType() == MVT::i1)
20145 // Very little shuffling can be done for 64-bit vectors right now.
20146 if (VT.getSizeInBits() == 64)
20149 // We only care that the types being shuffled are legal. The lowering can
20150 // handle any possible shuffle mask that results.
20151 return isTypeLegal(VT.getSimpleVT());
20155 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20157 // Just delegate to the generic legality, clear masks aren't special.
20158 return isShuffleMaskLegal(Mask, VT);
20161 //===----------------------------------------------------------------------===//
20162 // X86 Scheduler Hooks
20163 //===----------------------------------------------------------------------===//
20165 /// Utility function to emit xbegin specifying the start of an RTM region.
20166 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20167 const TargetInstrInfo *TII) {
20168 DebugLoc DL = MI->getDebugLoc();
20170 const BasicBlock *BB = MBB->getBasicBlock();
20171 MachineFunction::iterator I = MBB;
20174 // For the v = xbegin(), we generate
20185 MachineBasicBlock *thisMBB = MBB;
20186 MachineFunction *MF = MBB->getParent();
20187 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20188 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20189 MF->insert(I, mainMBB);
20190 MF->insert(I, sinkMBB);
20192 // Transfer the remainder of BB and its successor edges to sinkMBB.
20193 sinkMBB->splice(sinkMBB->begin(), MBB,
20194 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20195 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20199 // # fallthrough to mainMBB
20200 // # abortion to sinkMBB
20201 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20202 thisMBB->addSuccessor(mainMBB);
20203 thisMBB->addSuccessor(sinkMBB);
20207 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20208 mainMBB->addSuccessor(sinkMBB);
20211 // EAX is live into the sinkMBB
20212 sinkMBB->addLiveIn(X86::EAX);
20213 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20214 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20217 MI->eraseFromParent();
20221 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20222 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20223 // in the .td file.
20224 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20225 const TargetInstrInfo *TII) {
20227 switch (MI->getOpcode()) {
20228 default: llvm_unreachable("illegal opcode!");
20229 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20230 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20231 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20232 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20233 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20234 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20235 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20236 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20239 DebugLoc dl = MI->getDebugLoc();
20240 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20242 unsigned NumArgs = MI->getNumOperands();
20243 for (unsigned i = 1; i < NumArgs; ++i) {
20244 MachineOperand &Op = MI->getOperand(i);
20245 if (!(Op.isReg() && Op.isImplicit()))
20246 MIB.addOperand(Op);
20248 if (MI->hasOneMemOperand())
20249 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20251 BuildMI(*BB, MI, dl,
20252 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20253 .addReg(X86::XMM0);
20255 MI->eraseFromParent();
20259 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20260 // defs in an instruction pattern
20261 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20262 const TargetInstrInfo *TII) {
20264 switch (MI->getOpcode()) {
20265 default: llvm_unreachable("illegal opcode!");
20266 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20267 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20268 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20269 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20270 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20271 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20272 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20273 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20276 DebugLoc dl = MI->getDebugLoc();
20277 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20279 unsigned NumArgs = MI->getNumOperands(); // remove the results
20280 for (unsigned i = 1; i < NumArgs; ++i) {
20281 MachineOperand &Op = MI->getOperand(i);
20282 if (!(Op.isReg() && Op.isImplicit()))
20283 MIB.addOperand(Op);
20285 if (MI->hasOneMemOperand())
20286 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20288 BuildMI(*BB, MI, dl,
20289 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20292 MI->eraseFromParent();
20296 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20297 const X86Subtarget *Subtarget) {
20298 DebugLoc dl = MI->getDebugLoc();
20299 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20300 // Address into RAX/EAX, other two args into ECX, EDX.
20301 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20302 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20303 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20304 for (int i = 0; i < X86::AddrNumOperands; ++i)
20305 MIB.addOperand(MI->getOperand(i));
20307 unsigned ValOps = X86::AddrNumOperands;
20308 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20309 .addReg(MI->getOperand(ValOps).getReg());
20310 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20311 .addReg(MI->getOperand(ValOps+1).getReg());
20313 // The instruction doesn't actually take any operands though.
20314 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20316 MI->eraseFromParent(); // The pseudo is gone now.
20320 MachineBasicBlock *
20321 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20322 MachineBasicBlock *MBB) const {
20323 // Emit va_arg instruction on X86-64.
20325 // Operands to this pseudo-instruction:
20326 // 0 ) Output : destination address (reg)
20327 // 1-5) Input : va_list address (addr, i64mem)
20328 // 6 ) ArgSize : Size (in bytes) of vararg type
20329 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20330 // 8 ) Align : Alignment of type
20331 // 9 ) EFLAGS (implicit-def)
20333 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20334 static_assert(X86::AddrNumOperands == 5,
20335 "VAARG_64 assumes 5 address operands");
20337 unsigned DestReg = MI->getOperand(0).getReg();
20338 MachineOperand &Base = MI->getOperand(1);
20339 MachineOperand &Scale = MI->getOperand(2);
20340 MachineOperand &Index = MI->getOperand(3);
20341 MachineOperand &Disp = MI->getOperand(4);
20342 MachineOperand &Segment = MI->getOperand(5);
20343 unsigned ArgSize = MI->getOperand(6).getImm();
20344 unsigned ArgMode = MI->getOperand(7).getImm();
20345 unsigned Align = MI->getOperand(8).getImm();
20347 // Memory Reference
20348 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20349 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20350 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20352 // Machine Information
20353 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20354 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20355 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20356 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20357 DebugLoc DL = MI->getDebugLoc();
20359 // struct va_list {
20362 // i64 overflow_area (address)
20363 // i64 reg_save_area (address)
20365 // sizeof(va_list) = 24
20366 // alignment(va_list) = 8
20368 unsigned TotalNumIntRegs = 6;
20369 unsigned TotalNumXMMRegs = 8;
20370 bool UseGPOffset = (ArgMode == 1);
20371 bool UseFPOffset = (ArgMode == 2);
20372 unsigned MaxOffset = TotalNumIntRegs * 8 +
20373 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20375 /* Align ArgSize to a multiple of 8 */
20376 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20377 bool NeedsAlign = (Align > 8);
20379 MachineBasicBlock *thisMBB = MBB;
20380 MachineBasicBlock *overflowMBB;
20381 MachineBasicBlock *offsetMBB;
20382 MachineBasicBlock *endMBB;
20384 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20385 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20386 unsigned OffsetReg = 0;
20388 if (!UseGPOffset && !UseFPOffset) {
20389 // If we only pull from the overflow region, we don't create a branch.
20390 // We don't need to alter control flow.
20391 OffsetDestReg = 0; // unused
20392 OverflowDestReg = DestReg;
20394 offsetMBB = nullptr;
20395 overflowMBB = thisMBB;
20398 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20399 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20400 // If not, pull from overflow_area. (branch to overflowMBB)
20405 // offsetMBB overflowMBB
20410 // Registers for the PHI in endMBB
20411 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20412 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20414 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20415 MachineFunction *MF = MBB->getParent();
20416 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20417 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20418 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20420 MachineFunction::iterator MBBIter = MBB;
20423 // Insert the new basic blocks
20424 MF->insert(MBBIter, offsetMBB);
20425 MF->insert(MBBIter, overflowMBB);
20426 MF->insert(MBBIter, endMBB);
20428 // Transfer the remainder of MBB and its successor edges to endMBB.
20429 endMBB->splice(endMBB->begin(), thisMBB,
20430 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20431 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20433 // Make offsetMBB and overflowMBB successors of thisMBB
20434 thisMBB->addSuccessor(offsetMBB);
20435 thisMBB->addSuccessor(overflowMBB);
20437 // endMBB is a successor of both offsetMBB and overflowMBB
20438 offsetMBB->addSuccessor(endMBB);
20439 overflowMBB->addSuccessor(endMBB);
20441 // Load the offset value into a register
20442 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20443 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20447 .addDisp(Disp, UseFPOffset ? 4 : 0)
20448 .addOperand(Segment)
20449 .setMemRefs(MMOBegin, MMOEnd);
20451 // Check if there is enough room left to pull this argument.
20452 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20454 .addImm(MaxOffset + 8 - ArgSizeA8);
20456 // Branch to "overflowMBB" if offset >= max
20457 // Fall through to "offsetMBB" otherwise
20458 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20459 .addMBB(overflowMBB);
20462 // In offsetMBB, emit code to use the reg_save_area.
20464 assert(OffsetReg != 0);
20466 // Read the reg_save_area address.
20467 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20468 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20473 .addOperand(Segment)
20474 .setMemRefs(MMOBegin, MMOEnd);
20476 // Zero-extend the offset
20477 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20478 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20481 .addImm(X86::sub_32bit);
20483 // Add the offset to the reg_save_area to get the final address.
20484 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20485 .addReg(OffsetReg64)
20486 .addReg(RegSaveReg);
20488 // Compute the offset for the next argument
20489 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20490 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20492 .addImm(UseFPOffset ? 16 : 8);
20494 // Store it back into the va_list.
20495 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20499 .addDisp(Disp, UseFPOffset ? 4 : 0)
20500 .addOperand(Segment)
20501 .addReg(NextOffsetReg)
20502 .setMemRefs(MMOBegin, MMOEnd);
20505 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20510 // Emit code to use overflow area
20513 // Load the overflow_area address into a register.
20514 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20515 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20520 .addOperand(Segment)
20521 .setMemRefs(MMOBegin, MMOEnd);
20523 // If we need to align it, do so. Otherwise, just copy the address
20524 // to OverflowDestReg.
20526 // Align the overflow address
20527 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20528 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20530 // aligned_addr = (addr + (align-1)) & ~(align-1)
20531 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20532 .addReg(OverflowAddrReg)
20535 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20537 .addImm(~(uint64_t)(Align-1));
20539 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20540 .addReg(OverflowAddrReg);
20543 // Compute the next overflow address after this argument.
20544 // (the overflow address should be kept 8-byte aligned)
20545 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20546 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20547 .addReg(OverflowDestReg)
20548 .addImm(ArgSizeA8);
20550 // Store the new overflow address.
20551 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20556 .addOperand(Segment)
20557 .addReg(NextAddrReg)
20558 .setMemRefs(MMOBegin, MMOEnd);
20560 // If we branched, emit the PHI to the front of endMBB.
20562 BuildMI(*endMBB, endMBB->begin(), DL,
20563 TII->get(X86::PHI), DestReg)
20564 .addReg(OffsetDestReg).addMBB(offsetMBB)
20565 .addReg(OverflowDestReg).addMBB(overflowMBB);
20568 // Erase the pseudo instruction
20569 MI->eraseFromParent();
20574 MachineBasicBlock *
20575 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20577 MachineBasicBlock *MBB) const {
20578 // Emit code to save XMM registers to the stack. The ABI says that the
20579 // number of registers to save is given in %al, so it's theoretically
20580 // possible to do an indirect jump trick to avoid saving all of them,
20581 // however this code takes a simpler approach and just executes all
20582 // of the stores if %al is non-zero. It's less code, and it's probably
20583 // easier on the hardware branch predictor, and stores aren't all that
20584 // expensive anyway.
20586 // Create the new basic blocks. One block contains all the XMM stores,
20587 // and one block is the final destination regardless of whether any
20588 // stores were performed.
20589 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20590 MachineFunction *F = MBB->getParent();
20591 MachineFunction::iterator MBBIter = MBB;
20593 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20594 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20595 F->insert(MBBIter, XMMSaveMBB);
20596 F->insert(MBBIter, EndMBB);
20598 // Transfer the remainder of MBB and its successor edges to EndMBB.
20599 EndMBB->splice(EndMBB->begin(), MBB,
20600 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20601 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20603 // The original block will now fall through to the XMM save block.
20604 MBB->addSuccessor(XMMSaveMBB);
20605 // The XMMSaveMBB will fall through to the end block.
20606 XMMSaveMBB->addSuccessor(EndMBB);
20608 // Now add the instructions.
20609 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20610 DebugLoc DL = MI->getDebugLoc();
20612 unsigned CountReg = MI->getOperand(0).getReg();
20613 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20614 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20616 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20617 // If %al is 0, branch around the XMM save block.
20618 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20619 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20620 MBB->addSuccessor(EndMBB);
20623 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20624 // that was just emitted, but clearly shouldn't be "saved".
20625 assert((MI->getNumOperands() <= 3 ||
20626 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20627 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20628 && "Expected last argument to be EFLAGS");
20629 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20630 // In the XMM save block, save all the XMM argument registers.
20631 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20632 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20633 MachineMemOperand *MMO = F->getMachineMemOperand(
20634 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20635 MachineMemOperand::MOStore,
20636 /*Size=*/16, /*Align=*/16);
20637 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20638 .addFrameIndex(RegSaveFrameIndex)
20639 .addImm(/*Scale=*/1)
20640 .addReg(/*IndexReg=*/0)
20641 .addImm(/*Disp=*/Offset)
20642 .addReg(/*Segment=*/0)
20643 .addReg(MI->getOperand(i).getReg())
20644 .addMemOperand(MMO);
20647 MI->eraseFromParent(); // The pseudo instruction is gone now.
20652 // The EFLAGS operand of SelectItr might be missing a kill marker
20653 // because there were multiple uses of EFLAGS, and ISel didn't know
20654 // which to mark. Figure out whether SelectItr should have had a
20655 // kill marker, and set it if it should. Returns the correct kill
20657 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20658 MachineBasicBlock* BB,
20659 const TargetRegisterInfo* TRI) {
20660 // Scan forward through BB for a use/def of EFLAGS.
20661 MachineBasicBlock::iterator miI(std::next(SelectItr));
20662 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20663 const MachineInstr& mi = *miI;
20664 if (mi.readsRegister(X86::EFLAGS))
20666 if (mi.definesRegister(X86::EFLAGS))
20667 break; // Should have kill-flag - update below.
20670 // If we hit the end of the block, check whether EFLAGS is live into a
20672 if (miI == BB->end()) {
20673 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20674 sEnd = BB->succ_end();
20675 sItr != sEnd; ++sItr) {
20676 MachineBasicBlock* succ = *sItr;
20677 if (succ->isLiveIn(X86::EFLAGS))
20682 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20683 // out. SelectMI should have a kill flag on EFLAGS.
20684 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20688 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20689 // together with other CMOV pseudo-opcodes into a single basic-block with
20690 // conditional jump around it.
20691 static bool isCMOVPseudo(MachineInstr *MI) {
20692 switch (MI->getOpcode()) {
20693 case X86::CMOV_FR32:
20694 case X86::CMOV_FR64:
20695 case X86::CMOV_GR8:
20696 case X86::CMOV_GR16:
20697 case X86::CMOV_GR32:
20698 case X86::CMOV_RFP32:
20699 case X86::CMOV_RFP64:
20700 case X86::CMOV_RFP80:
20701 case X86::CMOV_V2F64:
20702 case X86::CMOV_V2I64:
20703 case X86::CMOV_V4F32:
20704 case X86::CMOV_V4F64:
20705 case X86::CMOV_V4I64:
20706 case X86::CMOV_V16F32:
20707 case X86::CMOV_V8F32:
20708 case X86::CMOV_V8F64:
20709 case X86::CMOV_V8I64:
20710 case X86::CMOV_V8I1:
20711 case X86::CMOV_V16I1:
20712 case X86::CMOV_V32I1:
20713 case X86::CMOV_V64I1:
20721 MachineBasicBlock *
20722 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20723 MachineBasicBlock *BB) const {
20724 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20725 DebugLoc DL = MI->getDebugLoc();
20727 // To "insert" a SELECT_CC instruction, we actually have to insert the
20728 // diamond control-flow pattern. The incoming instruction knows the
20729 // destination vreg to set, the condition code register to branch on, the
20730 // true/false values to select between, and a branch opcode to use.
20731 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20732 MachineFunction::iterator It = BB;
20738 // cmpTY ccX, r1, r2
20740 // fallthrough --> copy0MBB
20741 MachineBasicBlock *thisMBB = BB;
20742 MachineFunction *F = BB->getParent();
20744 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20745 // as described above, by inserting a BB, and then making a PHI at the join
20746 // point to select the true and false operands of the CMOV in the PHI.
20748 // The code also handles two different cases of multiple CMOV opcodes
20752 // In this case, there are multiple CMOVs in a row, all which are based on
20753 // the same condition setting (or the exact opposite condition setting).
20754 // In this case we can lower all the CMOVs using a single inserted BB, and
20755 // then make a number of PHIs at the join point to model the CMOVs. The only
20756 // trickiness here, is that in a case like:
20758 // t2 = CMOV cond1 t1, f1
20759 // t3 = CMOV cond1 t2, f2
20761 // when rewriting this into PHIs, we have to perform some renaming on the
20762 // temps since you cannot have a PHI operand refer to a PHI result earlier
20763 // in the same block. The "simple" but wrong lowering would be:
20765 // t2 = PHI t1(BB1), f1(BB2)
20766 // t3 = PHI t2(BB1), f2(BB2)
20768 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20769 // renaming is to note that on the path through BB1, t2 is really just a
20770 // copy of t1, and do that renaming, properly generating:
20772 // t2 = PHI t1(BB1), f1(BB2)
20773 // t3 = PHI t1(BB1), f2(BB2)
20775 // Case 2, we lower cascaded CMOVs such as
20777 // (CMOV (CMOV F, T, cc1), T, cc2)
20779 // to two successives branches. For that, we look for another CMOV as the
20780 // following instruction.
20782 // Without this, we would add a PHI between the two jumps, which ends up
20783 // creating a few copies all around. For instance, for
20785 // (sitofp (zext (fcmp une)))
20787 // we would generate:
20789 // ucomiss %xmm1, %xmm0
20790 // movss <1.0f>, %xmm0
20791 // movaps %xmm0, %xmm1
20793 // xorps %xmm1, %xmm1
20796 // movaps %xmm1, %xmm0
20800 // because this custom-inserter would have generated:
20812 // A: X = ...; Y = ...
20814 // C: Z = PHI [X, A], [Y, B]
20816 // E: PHI [X, C], [Z, D]
20818 // If we lower both CMOVs in a single step, we can instead generate:
20830 // A: X = ...; Y = ...
20832 // E: PHI [X, A], [X, C], [Y, D]
20834 // Which, in our sitofp/fcmp example, gives us something like:
20836 // ucomiss %xmm1, %xmm0
20837 // movss <1.0f>, %xmm0
20840 // xorps %xmm0, %xmm0
20844 MachineInstr *CascadedCMOV = nullptr;
20845 MachineInstr *LastCMOV = MI;
20846 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
20847 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
20848 MachineBasicBlock::iterator NextMIIt =
20849 std::next(MachineBasicBlock::iterator(MI));
20851 // Check for case 1, where there are multiple CMOVs with the same condition
20852 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
20853 // number of jumps the most.
20855 if (isCMOVPseudo(MI)) {
20856 // See if we have a string of CMOVS with the same condition.
20857 while (NextMIIt != BB->end() &&
20858 isCMOVPseudo(NextMIIt) &&
20859 (NextMIIt->getOperand(3).getImm() == CC ||
20860 NextMIIt->getOperand(3).getImm() == OppCC)) {
20861 LastCMOV = &*NextMIIt;
20866 // This checks for case 2, but only do this if we didn't already find
20867 // case 1, as indicated by LastCMOV == MI.
20868 if (LastCMOV == MI &&
20869 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
20870 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
20871 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
20872 CascadedCMOV = &*NextMIIt;
20875 MachineBasicBlock *jcc1MBB = nullptr;
20877 // If we have a cascaded CMOV, we lower it to two successive branches to
20878 // the same block. EFLAGS is used by both, so mark it as live in the second.
20879 if (CascadedCMOV) {
20880 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
20881 F->insert(It, jcc1MBB);
20882 jcc1MBB->addLiveIn(X86::EFLAGS);
20885 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20886 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20887 F->insert(It, copy0MBB);
20888 F->insert(It, sinkMBB);
20890 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20891 // live into the sink and copy blocks.
20892 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
20894 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
20895 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
20896 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
20897 copy0MBB->addLiveIn(X86::EFLAGS);
20898 sinkMBB->addLiveIn(X86::EFLAGS);
20901 // Transfer the remainder of BB and its successor edges to sinkMBB.
20902 sinkMBB->splice(sinkMBB->begin(), BB,
20903 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
20904 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20906 // Add the true and fallthrough blocks as its successors.
20907 if (CascadedCMOV) {
20908 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
20909 BB->addSuccessor(jcc1MBB);
20911 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
20912 // jump to the sinkMBB.
20913 jcc1MBB->addSuccessor(copy0MBB);
20914 jcc1MBB->addSuccessor(sinkMBB);
20916 BB->addSuccessor(copy0MBB);
20919 // The true block target of the first (or only) branch is always sinkMBB.
20920 BB->addSuccessor(sinkMBB);
20922 // Create the conditional branch instruction.
20923 unsigned Opc = X86::GetCondBranchFromCond(CC);
20924 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20926 if (CascadedCMOV) {
20927 unsigned Opc2 = X86::GetCondBranchFromCond(
20928 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
20929 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
20933 // %FalseValue = ...
20934 // # fallthrough to sinkMBB
20935 copy0MBB->addSuccessor(sinkMBB);
20938 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20940 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
20941 MachineBasicBlock::iterator MIItEnd =
20942 std::next(MachineBasicBlock::iterator(LastCMOV));
20943 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
20944 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
20945 MachineInstrBuilder MIB;
20947 // As we are creating the PHIs, we have to be careful if there is more than
20948 // one. Later CMOVs may reference the results of earlier CMOVs, but later
20949 // PHIs have to reference the individual true/false inputs from earlier PHIs.
20950 // That also means that PHI construction must work forward from earlier to
20951 // later, and that the code must maintain a mapping from earlier PHI's
20952 // destination registers, and the registers that went into the PHI.
20954 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
20955 unsigned DestReg = MIIt->getOperand(0).getReg();
20956 unsigned Op1Reg = MIIt->getOperand(1).getReg();
20957 unsigned Op2Reg = MIIt->getOperand(2).getReg();
20959 // If this CMOV we are generating is the opposite condition from
20960 // the jump we generated, then we have to swap the operands for the
20961 // PHI that is going to be generated.
20962 if (MIIt->getOperand(3).getImm() == OppCC)
20963 std::swap(Op1Reg, Op2Reg);
20965 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
20966 Op1Reg = RegRewriteTable[Op1Reg].first;
20968 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
20969 Op2Reg = RegRewriteTable[Op2Reg].second;
20971 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
20972 TII->get(X86::PHI), DestReg)
20973 .addReg(Op1Reg).addMBB(copy0MBB)
20974 .addReg(Op2Reg).addMBB(thisMBB);
20976 // Add this PHI to the rewrite table.
20977 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
20980 // If we have a cascaded CMOV, the second Jcc provides the same incoming
20981 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
20982 if (CascadedCMOV) {
20983 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
20984 // Copy the PHI result to the register defined by the second CMOV.
20985 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
20986 DL, TII->get(TargetOpcode::COPY),
20987 CascadedCMOV->getOperand(0).getReg())
20988 .addReg(MI->getOperand(0).getReg());
20989 CascadedCMOV->eraseFromParent();
20992 // Now remove the CMOV(s).
20993 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
20994 (MIIt++)->eraseFromParent();
20999 MachineBasicBlock *
21000 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21001 MachineBasicBlock *BB) const {
21002 // Combine the following atomic floating-point modification pattern:
21003 // a.store(reg OP a.load(acquire), release)
21004 // Transform them into:
21005 // OPss (%gpr), %xmm
21006 // movss %xmm, (%gpr)
21007 // Or sd equivalent for 64-bit operations.
21009 switch (MI->getOpcode()) {
21010 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21011 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21012 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21014 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21015 DebugLoc DL = MI->getDebugLoc();
21016 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21017 unsigned MSrc = MI->getOperand(0).getReg();
21018 unsigned VSrc = MI->getOperand(5).getReg();
21019 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21020 .addReg(/*Base=*/MSrc)
21021 .addImm(/*Scale=*/1)
21022 .addReg(/*Index=*/0)
21025 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21026 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21028 .addReg(/*Base=*/MSrc)
21029 .addImm(/*Scale=*/1)
21030 .addReg(/*Index=*/0)
21031 .addImm(/*Disp=*/0)
21032 .addReg(/*Segment=*/0);
21033 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21034 MI->eraseFromParent(); // The pseudo instruction is gone now.
21038 MachineBasicBlock *
21039 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21040 MachineBasicBlock *BB) const {
21041 MachineFunction *MF = BB->getParent();
21042 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21043 DebugLoc DL = MI->getDebugLoc();
21044 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21046 assert(MF->shouldSplitStack());
21048 const bool Is64Bit = Subtarget->is64Bit();
21049 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21051 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21052 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21055 // ... [Till the alloca]
21056 // If stacklet is not large enough, jump to mallocMBB
21059 // Allocate by subtracting from RSP
21060 // Jump to continueMBB
21063 // Allocate by call to runtime
21067 // [rest of original BB]
21070 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21071 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21072 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21074 MachineRegisterInfo &MRI = MF->getRegInfo();
21075 const TargetRegisterClass *AddrRegClass =
21076 getRegClassFor(getPointerTy(MF->getDataLayout()));
21078 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21079 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21080 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21081 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21082 sizeVReg = MI->getOperand(1).getReg(),
21083 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21085 MachineFunction::iterator MBBIter = BB;
21088 MF->insert(MBBIter, bumpMBB);
21089 MF->insert(MBBIter, mallocMBB);
21090 MF->insert(MBBIter, continueMBB);
21092 continueMBB->splice(continueMBB->begin(), BB,
21093 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21094 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21096 // Add code to the main basic block to check if the stack limit has been hit,
21097 // and if so, jump to mallocMBB otherwise to bumpMBB.
21098 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21099 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21100 .addReg(tmpSPVReg).addReg(sizeVReg);
21101 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21102 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21103 .addReg(SPLimitVReg);
21104 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21106 // bumpMBB simply decreases the stack pointer, since we know the current
21107 // stacklet has enough space.
21108 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21109 .addReg(SPLimitVReg);
21110 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21111 .addReg(SPLimitVReg);
21112 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21114 // Calls into a routine in libgcc to allocate more space from the heap.
21115 const uint32_t *RegMask =
21116 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21118 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21120 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21121 .addExternalSymbol("__morestack_allocate_stack_space")
21122 .addRegMask(RegMask)
21123 .addReg(X86::RDI, RegState::Implicit)
21124 .addReg(X86::RAX, RegState::ImplicitDefine);
21125 } else if (Is64Bit) {
21126 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21128 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21129 .addExternalSymbol("__morestack_allocate_stack_space")
21130 .addRegMask(RegMask)
21131 .addReg(X86::EDI, RegState::Implicit)
21132 .addReg(X86::EAX, RegState::ImplicitDefine);
21134 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21136 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21137 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21138 .addExternalSymbol("__morestack_allocate_stack_space")
21139 .addRegMask(RegMask)
21140 .addReg(X86::EAX, RegState::ImplicitDefine);
21144 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21147 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21148 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21149 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21151 // Set up the CFG correctly.
21152 BB->addSuccessor(bumpMBB);
21153 BB->addSuccessor(mallocMBB);
21154 mallocMBB->addSuccessor(continueMBB);
21155 bumpMBB->addSuccessor(continueMBB);
21157 // Take care of the PHI nodes.
21158 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21159 MI->getOperand(0).getReg())
21160 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21161 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21163 // Delete the original pseudo instruction.
21164 MI->eraseFromParent();
21167 return continueMBB;
21170 MachineBasicBlock *
21171 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21172 MachineBasicBlock *BB) const {
21173 DebugLoc DL = MI->getDebugLoc();
21175 assert(!Subtarget->isTargetMachO());
21177 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
21180 MI->eraseFromParent(); // The pseudo instruction is gone now.
21184 MachineBasicBlock *
21185 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21186 MachineBasicBlock *BB) const {
21187 // This is pretty easy. We're taking the value that we received from
21188 // our load from the relocation, sticking it in either RDI (x86-64)
21189 // or EAX and doing an indirect call. The return value will then
21190 // be in the normal return register.
21191 MachineFunction *F = BB->getParent();
21192 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21193 DebugLoc DL = MI->getDebugLoc();
21195 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21196 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21198 // Get a register mask for the lowered call.
21199 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21200 // proper register mask.
21201 const uint32_t *RegMask =
21202 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21203 if (Subtarget->is64Bit()) {
21204 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21205 TII->get(X86::MOV64rm), X86::RDI)
21207 .addImm(0).addReg(0)
21208 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21209 MI->getOperand(3).getTargetFlags())
21211 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21212 addDirectMem(MIB, X86::RDI);
21213 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21214 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21215 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21216 TII->get(X86::MOV32rm), X86::EAX)
21218 .addImm(0).addReg(0)
21219 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21220 MI->getOperand(3).getTargetFlags())
21222 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21223 addDirectMem(MIB, X86::EAX);
21224 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21226 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21227 TII->get(X86::MOV32rm), X86::EAX)
21228 .addReg(TII->getGlobalBaseReg(F))
21229 .addImm(0).addReg(0)
21230 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21231 MI->getOperand(3).getTargetFlags())
21233 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21234 addDirectMem(MIB, X86::EAX);
21235 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21238 MI->eraseFromParent(); // The pseudo instruction is gone now.
21242 MachineBasicBlock *
21243 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21244 MachineBasicBlock *MBB) const {
21245 DebugLoc DL = MI->getDebugLoc();
21246 MachineFunction *MF = MBB->getParent();
21247 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21248 MachineRegisterInfo &MRI = MF->getRegInfo();
21250 const BasicBlock *BB = MBB->getBasicBlock();
21251 MachineFunction::iterator I = MBB;
21254 // Memory Reference
21255 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21256 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21259 unsigned MemOpndSlot = 0;
21261 unsigned CurOp = 0;
21263 DstReg = MI->getOperand(CurOp++).getReg();
21264 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21265 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21266 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21267 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21269 MemOpndSlot = CurOp;
21271 MVT PVT = getPointerTy(MF->getDataLayout());
21272 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21273 "Invalid Pointer Size!");
21275 // For v = setjmp(buf), we generate
21278 // buf[LabelOffset] = restoreMBB
21279 // SjLjSetup restoreMBB
21285 // v = phi(main, restore)
21288 // if base pointer being used, load it from frame
21291 MachineBasicBlock *thisMBB = MBB;
21292 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21293 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21294 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21295 MF->insert(I, mainMBB);
21296 MF->insert(I, sinkMBB);
21297 MF->push_back(restoreMBB);
21299 MachineInstrBuilder MIB;
21301 // Transfer the remainder of BB and its successor edges to sinkMBB.
21302 sinkMBB->splice(sinkMBB->begin(), MBB,
21303 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21304 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21307 unsigned PtrStoreOpc = 0;
21308 unsigned LabelReg = 0;
21309 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21310 Reloc::Model RM = MF->getTarget().getRelocationModel();
21311 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21312 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21314 // Prepare IP either in reg or imm.
21315 if (!UseImmLabel) {
21316 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21317 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21318 LabelReg = MRI.createVirtualRegister(PtrRC);
21319 if (Subtarget->is64Bit()) {
21320 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21324 .addMBB(restoreMBB)
21327 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21328 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21329 .addReg(XII->getGlobalBaseReg(MF))
21332 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21336 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21338 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21339 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21340 if (i == X86::AddrDisp)
21341 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21343 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21346 MIB.addReg(LabelReg);
21348 MIB.addMBB(restoreMBB);
21349 MIB.setMemRefs(MMOBegin, MMOEnd);
21351 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21352 .addMBB(restoreMBB);
21354 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21355 MIB.addRegMask(RegInfo->getNoPreservedMask());
21356 thisMBB->addSuccessor(mainMBB);
21357 thisMBB->addSuccessor(restoreMBB);
21361 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21362 mainMBB->addSuccessor(sinkMBB);
21365 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21366 TII->get(X86::PHI), DstReg)
21367 .addReg(mainDstReg).addMBB(mainMBB)
21368 .addReg(restoreDstReg).addMBB(restoreMBB);
21371 if (RegInfo->hasBasePointer(*MF)) {
21372 const bool Uses64BitFramePtr =
21373 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21374 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21375 X86FI->setRestoreBasePointer(MF);
21376 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21377 unsigned BasePtr = RegInfo->getBaseRegister();
21378 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21379 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21380 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21381 .setMIFlag(MachineInstr::FrameSetup);
21383 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21384 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21385 restoreMBB->addSuccessor(sinkMBB);
21387 MI->eraseFromParent();
21391 MachineBasicBlock *
21392 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21393 MachineBasicBlock *MBB) const {
21394 DebugLoc DL = MI->getDebugLoc();
21395 MachineFunction *MF = MBB->getParent();
21396 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21397 MachineRegisterInfo &MRI = MF->getRegInfo();
21399 // Memory Reference
21400 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21401 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21403 MVT PVT = getPointerTy(MF->getDataLayout());
21404 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21405 "Invalid Pointer Size!");
21407 const TargetRegisterClass *RC =
21408 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21409 unsigned Tmp = MRI.createVirtualRegister(RC);
21410 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21411 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21412 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21413 unsigned SP = RegInfo->getStackRegister();
21415 MachineInstrBuilder MIB;
21417 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21418 const int64_t SPOffset = 2 * PVT.getStoreSize();
21420 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21421 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21424 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21425 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21426 MIB.addOperand(MI->getOperand(i));
21427 MIB.setMemRefs(MMOBegin, MMOEnd);
21429 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21430 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21431 if (i == X86::AddrDisp)
21432 MIB.addDisp(MI->getOperand(i), LabelOffset);
21434 MIB.addOperand(MI->getOperand(i));
21436 MIB.setMemRefs(MMOBegin, MMOEnd);
21438 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21439 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21440 if (i == X86::AddrDisp)
21441 MIB.addDisp(MI->getOperand(i), SPOffset);
21443 MIB.addOperand(MI->getOperand(i));
21445 MIB.setMemRefs(MMOBegin, MMOEnd);
21447 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21449 MI->eraseFromParent();
21453 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21454 // accumulator loops. Writing back to the accumulator allows the coalescer
21455 // to remove extra copies in the loop.
21456 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21457 MachineBasicBlock *
21458 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21459 MachineBasicBlock *MBB) const {
21460 MachineOperand &AddendOp = MI->getOperand(3);
21462 // Bail out early if the addend isn't a register - we can't switch these.
21463 if (!AddendOp.isReg())
21466 MachineFunction &MF = *MBB->getParent();
21467 MachineRegisterInfo &MRI = MF.getRegInfo();
21469 // Check whether the addend is defined by a PHI:
21470 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21471 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21472 if (!AddendDef.isPHI())
21475 // Look for the following pattern:
21477 // %addend = phi [%entry, 0], [%loop, %result]
21479 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21483 // %addend = phi [%entry, 0], [%loop, %result]
21485 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21487 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21488 assert(AddendDef.getOperand(i).isReg());
21489 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21490 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21491 if (&PHISrcInst == MI) {
21492 // Found a matching instruction.
21493 unsigned NewFMAOpc = 0;
21494 switch (MI->getOpcode()) {
21495 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21496 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21497 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21498 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21499 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21500 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21501 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21502 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21503 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21504 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21505 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21506 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21507 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21508 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21509 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21510 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21511 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21512 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21513 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21514 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21516 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21517 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21518 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21519 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21520 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21521 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21522 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21523 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21524 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21525 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21526 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21527 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21528 default: llvm_unreachable("Unrecognized FMA variant.");
21531 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21532 MachineInstrBuilder MIB =
21533 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21534 .addOperand(MI->getOperand(0))
21535 .addOperand(MI->getOperand(3))
21536 .addOperand(MI->getOperand(2))
21537 .addOperand(MI->getOperand(1));
21538 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21539 MI->eraseFromParent();
21546 MachineBasicBlock *
21547 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21548 MachineBasicBlock *BB) const {
21549 switch (MI->getOpcode()) {
21550 default: llvm_unreachable("Unexpected instr type to insert");
21551 case X86::TAILJMPd64:
21552 case X86::TAILJMPr64:
21553 case X86::TAILJMPm64:
21554 case X86::TAILJMPd64_REX:
21555 case X86::TAILJMPr64_REX:
21556 case X86::TAILJMPm64_REX:
21557 llvm_unreachable("TAILJMP64 would not be touched here.");
21558 case X86::TCRETURNdi64:
21559 case X86::TCRETURNri64:
21560 case X86::TCRETURNmi64:
21562 case X86::WIN_ALLOCA:
21563 return EmitLoweredWinAlloca(MI, BB);
21564 case X86::SEG_ALLOCA_32:
21565 case X86::SEG_ALLOCA_64:
21566 return EmitLoweredSegAlloca(MI, BB);
21567 case X86::TLSCall_32:
21568 case X86::TLSCall_64:
21569 return EmitLoweredTLSCall(MI, BB);
21570 case X86::CMOV_FR32:
21571 case X86::CMOV_FR64:
21572 case X86::CMOV_GR8:
21573 case X86::CMOV_GR16:
21574 case X86::CMOV_GR32:
21575 case X86::CMOV_RFP32:
21576 case X86::CMOV_RFP64:
21577 case X86::CMOV_RFP80:
21578 case X86::CMOV_V2F64:
21579 case X86::CMOV_V2I64:
21580 case X86::CMOV_V4F32:
21581 case X86::CMOV_V4F64:
21582 case X86::CMOV_V4I64:
21583 case X86::CMOV_V16F32:
21584 case X86::CMOV_V8F32:
21585 case X86::CMOV_V8F64:
21586 case X86::CMOV_V8I64:
21587 case X86::CMOV_V8I1:
21588 case X86::CMOV_V16I1:
21589 case X86::CMOV_V32I1:
21590 case X86::CMOV_V64I1:
21591 return EmitLoweredSelect(MI, BB);
21593 case X86::RELEASE_FADD32mr:
21594 case X86::RELEASE_FADD64mr:
21595 return EmitLoweredAtomicFP(MI, BB);
21597 case X86::FP32_TO_INT16_IN_MEM:
21598 case X86::FP32_TO_INT32_IN_MEM:
21599 case X86::FP32_TO_INT64_IN_MEM:
21600 case X86::FP64_TO_INT16_IN_MEM:
21601 case X86::FP64_TO_INT32_IN_MEM:
21602 case X86::FP64_TO_INT64_IN_MEM:
21603 case X86::FP80_TO_INT16_IN_MEM:
21604 case X86::FP80_TO_INT32_IN_MEM:
21605 case X86::FP80_TO_INT64_IN_MEM: {
21606 MachineFunction *F = BB->getParent();
21607 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21608 DebugLoc DL = MI->getDebugLoc();
21610 // Change the floating point control register to use "round towards zero"
21611 // mode when truncating to an integer value.
21612 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21613 addFrameReference(BuildMI(*BB, MI, DL,
21614 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21616 // Load the old value of the high byte of the control word...
21618 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21619 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21622 // Set the high part to be round to zero...
21623 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21626 // Reload the modified control word now...
21627 addFrameReference(BuildMI(*BB, MI, DL,
21628 TII->get(X86::FLDCW16m)), CWFrameIdx);
21630 // Restore the memory image of control word to original value
21631 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21634 // Get the X86 opcode to use.
21636 switch (MI->getOpcode()) {
21637 default: llvm_unreachable("illegal opcode!");
21638 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21639 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21640 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21641 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21642 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21643 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21644 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21645 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21646 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21650 MachineOperand &Op = MI->getOperand(0);
21652 AM.BaseType = X86AddressMode::RegBase;
21653 AM.Base.Reg = Op.getReg();
21655 AM.BaseType = X86AddressMode::FrameIndexBase;
21656 AM.Base.FrameIndex = Op.getIndex();
21658 Op = MI->getOperand(1);
21660 AM.Scale = Op.getImm();
21661 Op = MI->getOperand(2);
21663 AM.IndexReg = Op.getImm();
21664 Op = MI->getOperand(3);
21665 if (Op.isGlobal()) {
21666 AM.GV = Op.getGlobal();
21668 AM.Disp = Op.getImm();
21670 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21671 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21673 // Reload the original control word now.
21674 addFrameReference(BuildMI(*BB, MI, DL,
21675 TII->get(X86::FLDCW16m)), CWFrameIdx);
21677 MI->eraseFromParent(); // The pseudo instruction is gone now.
21680 // String/text processing lowering.
21681 case X86::PCMPISTRM128REG:
21682 case X86::VPCMPISTRM128REG:
21683 case X86::PCMPISTRM128MEM:
21684 case X86::VPCMPISTRM128MEM:
21685 case X86::PCMPESTRM128REG:
21686 case X86::VPCMPESTRM128REG:
21687 case X86::PCMPESTRM128MEM:
21688 case X86::VPCMPESTRM128MEM:
21689 assert(Subtarget->hasSSE42() &&
21690 "Target must have SSE4.2 or AVX features enabled");
21691 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21693 // String/text processing lowering.
21694 case X86::PCMPISTRIREG:
21695 case X86::VPCMPISTRIREG:
21696 case X86::PCMPISTRIMEM:
21697 case X86::VPCMPISTRIMEM:
21698 case X86::PCMPESTRIREG:
21699 case X86::VPCMPESTRIREG:
21700 case X86::PCMPESTRIMEM:
21701 case X86::VPCMPESTRIMEM:
21702 assert(Subtarget->hasSSE42() &&
21703 "Target must have SSE4.2 or AVX features enabled");
21704 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21706 // Thread synchronization.
21708 return EmitMonitor(MI, BB, Subtarget);
21712 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21714 case X86::VASTART_SAVE_XMM_REGS:
21715 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21717 case X86::VAARG_64:
21718 return EmitVAARG64WithCustomInserter(MI, BB);
21720 case X86::EH_SjLj_SetJmp32:
21721 case X86::EH_SjLj_SetJmp64:
21722 return emitEHSjLjSetJmp(MI, BB);
21724 case X86::EH_SjLj_LongJmp32:
21725 case X86::EH_SjLj_LongJmp64:
21726 return emitEHSjLjLongJmp(MI, BB);
21728 case TargetOpcode::STATEPOINT:
21729 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21730 // this point in the process. We diverge later.
21731 return emitPatchPoint(MI, BB);
21733 case TargetOpcode::STACKMAP:
21734 case TargetOpcode::PATCHPOINT:
21735 return emitPatchPoint(MI, BB);
21737 case X86::VFMADDPDr213r:
21738 case X86::VFMADDPSr213r:
21739 case X86::VFMADDSDr213r:
21740 case X86::VFMADDSSr213r:
21741 case X86::VFMSUBPDr213r:
21742 case X86::VFMSUBPSr213r:
21743 case X86::VFMSUBSDr213r:
21744 case X86::VFMSUBSSr213r:
21745 case X86::VFNMADDPDr213r:
21746 case X86::VFNMADDPSr213r:
21747 case X86::VFNMADDSDr213r:
21748 case X86::VFNMADDSSr213r:
21749 case X86::VFNMSUBPDr213r:
21750 case X86::VFNMSUBPSr213r:
21751 case X86::VFNMSUBSDr213r:
21752 case X86::VFNMSUBSSr213r:
21753 case X86::VFMADDSUBPDr213r:
21754 case X86::VFMADDSUBPSr213r:
21755 case X86::VFMSUBADDPDr213r:
21756 case X86::VFMSUBADDPSr213r:
21757 case X86::VFMADDPDr213rY:
21758 case X86::VFMADDPSr213rY:
21759 case X86::VFMSUBPDr213rY:
21760 case X86::VFMSUBPSr213rY:
21761 case X86::VFNMADDPDr213rY:
21762 case X86::VFNMADDPSr213rY:
21763 case X86::VFNMSUBPDr213rY:
21764 case X86::VFNMSUBPSr213rY:
21765 case X86::VFMADDSUBPDr213rY:
21766 case X86::VFMADDSUBPSr213rY:
21767 case X86::VFMSUBADDPDr213rY:
21768 case X86::VFMSUBADDPSr213rY:
21769 return emitFMA3Instr(MI, BB);
21773 //===----------------------------------------------------------------------===//
21774 // X86 Optimization Hooks
21775 //===----------------------------------------------------------------------===//
21777 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21780 const SelectionDAG &DAG,
21781 unsigned Depth) const {
21782 unsigned BitWidth = KnownZero.getBitWidth();
21783 unsigned Opc = Op.getOpcode();
21784 assert((Opc >= ISD::BUILTIN_OP_END ||
21785 Opc == ISD::INTRINSIC_WO_CHAIN ||
21786 Opc == ISD::INTRINSIC_W_CHAIN ||
21787 Opc == ISD::INTRINSIC_VOID) &&
21788 "Should use MaskedValueIsZero if you don't know whether Op"
21789 " is a target node!");
21791 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21805 // These nodes' second result is a boolean.
21806 if (Op.getResNo() == 0)
21809 case X86ISD::SETCC:
21810 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21812 case ISD::INTRINSIC_WO_CHAIN: {
21813 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21814 unsigned NumLoBits = 0;
21817 case Intrinsic::x86_sse_movmsk_ps:
21818 case Intrinsic::x86_avx_movmsk_ps_256:
21819 case Intrinsic::x86_sse2_movmsk_pd:
21820 case Intrinsic::x86_avx_movmsk_pd_256:
21821 case Intrinsic::x86_mmx_pmovmskb:
21822 case Intrinsic::x86_sse2_pmovmskb_128:
21823 case Intrinsic::x86_avx2_pmovmskb: {
21824 // High bits of movmskp{s|d}, pmovmskb are known zero.
21826 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21827 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21828 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21829 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21830 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21831 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21832 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21833 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21835 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21844 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21846 const SelectionDAG &,
21847 unsigned Depth) const {
21848 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21849 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21850 return Op.getValueType().getScalarType().getSizeInBits();
21856 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21857 /// node is a GlobalAddress + offset.
21858 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21859 const GlobalValue* &GA,
21860 int64_t &Offset) const {
21861 if (N->getOpcode() == X86ISD::Wrapper) {
21862 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21863 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21864 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21868 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21871 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21872 /// same as extracting the high 128-bit part of 256-bit vector and then
21873 /// inserting the result into the low part of a new 256-bit vector
21874 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21875 EVT VT = SVOp->getValueType(0);
21876 unsigned NumElems = VT.getVectorNumElements();
21878 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21879 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21880 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21881 SVOp->getMaskElt(j) >= 0)
21887 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21888 /// same as extracting the low 128-bit part of 256-bit vector and then
21889 /// inserting the result into the high part of a new 256-bit vector
21890 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21891 EVT VT = SVOp->getValueType(0);
21892 unsigned NumElems = VT.getVectorNumElements();
21894 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21895 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21896 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21897 SVOp->getMaskElt(j) >= 0)
21903 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21904 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21905 TargetLowering::DAGCombinerInfo &DCI,
21906 const X86Subtarget* Subtarget) {
21908 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21909 SDValue V1 = SVOp->getOperand(0);
21910 SDValue V2 = SVOp->getOperand(1);
21911 EVT VT = SVOp->getValueType(0);
21912 unsigned NumElems = VT.getVectorNumElements();
21914 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21915 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21919 // V UNDEF BUILD_VECTOR UNDEF
21921 // CONCAT_VECTOR CONCAT_VECTOR
21924 // RESULT: V + zero extended
21926 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21927 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21928 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21931 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21934 // To match the shuffle mask, the first half of the mask should
21935 // be exactly the first vector, and all the rest a splat with the
21936 // first element of the second one.
21937 for (unsigned i = 0; i != NumElems/2; ++i)
21938 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21939 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21942 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21943 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21944 if (Ld->hasNUsesOfValue(1, 0)) {
21945 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21946 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21948 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21950 Ld->getPointerInfo(),
21951 Ld->getAlignment(),
21952 false/*isVolatile*/, true/*ReadMem*/,
21953 false/*WriteMem*/);
21955 // Make sure the newly-created LOAD is in the same position as Ld in
21956 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21957 // and update uses of Ld's output chain to use the TokenFactor.
21958 if (Ld->hasAnyUseOfValue(1)) {
21959 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21960 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21961 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21962 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21963 SDValue(ResNode.getNode(), 1));
21966 return DAG.getBitcast(VT, ResNode);
21970 // Emit a zeroed vector and insert the desired subvector on its
21972 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21973 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21974 return DCI.CombineTo(N, InsV);
21977 //===--------------------------------------------------------------------===//
21978 // Combine some shuffles into subvector extracts and inserts:
21981 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21982 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21983 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21984 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21985 return DCI.CombineTo(N, InsV);
21988 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21989 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21990 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21991 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21992 return DCI.CombineTo(N, InsV);
21998 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22001 /// This is the leaf of the recursive combinine below. When we have found some
22002 /// chain of single-use x86 shuffle instructions and accumulated the combined
22003 /// shuffle mask represented by them, this will try to pattern match that mask
22004 /// into either a single instruction if there is a special purpose instruction
22005 /// for this operation, or into a PSHUFB instruction which is a fully general
22006 /// instruction but should only be used to replace chains over a certain depth.
22007 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22008 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22009 TargetLowering::DAGCombinerInfo &DCI,
22010 const X86Subtarget *Subtarget) {
22011 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22013 // Find the operand that enters the chain. Note that multiple uses are OK
22014 // here, we're not going to remove the operand we find.
22015 SDValue Input = Op.getOperand(0);
22016 while (Input.getOpcode() == ISD::BITCAST)
22017 Input = Input.getOperand(0);
22019 MVT VT = Input.getSimpleValueType();
22020 MVT RootVT = Root.getSimpleValueType();
22023 if (Mask.size() == 1) {
22024 int Index = Mask[0];
22025 assert((Index >= 0 || Index == SM_SentinelUndef ||
22026 Index == SM_SentinelZero) &&
22027 "Invalid shuffle index found!");
22029 // We may end up with an accumulated mask of size 1 as a result of
22030 // widening of shuffle operands (see function canWidenShuffleElements).
22031 // If the only shuffle index is equal to SM_SentinelZero then propagate
22032 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22033 // mask, and therefore the entire chain of shuffles can be folded away.
22034 if (Index == SM_SentinelZero)
22035 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22037 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22042 // Use the float domain if the operand type is a floating point type.
22043 bool FloatDomain = VT.isFloatingPoint();
22045 // For floating point shuffles, we don't have free copies in the shuffle
22046 // instructions or the ability to load as part of the instruction, so
22047 // canonicalize their shuffles to UNPCK or MOV variants.
22049 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22050 // vectors because it can have a load folded into it that UNPCK cannot. This
22051 // doesn't preclude something switching to the shorter encoding post-RA.
22053 // FIXME: Should teach these routines about AVX vector widths.
22054 if (FloatDomain && VT.getSizeInBits() == 128) {
22055 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22056 bool Lo = Mask.equals({0, 0});
22059 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22060 // is no slower than UNPCKLPD but has the option to fold the input operand
22061 // into even an unaligned memory load.
22062 if (Lo && Subtarget->hasSSE3()) {
22063 Shuffle = X86ISD::MOVDDUP;
22064 ShuffleVT = MVT::v2f64;
22066 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22067 // than the UNPCK variants.
22068 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22069 ShuffleVT = MVT::v4f32;
22071 if (Depth == 1 && Root->getOpcode() == Shuffle)
22072 return false; // Nothing to do!
22073 Op = DAG.getBitcast(ShuffleVT, Input);
22074 DCI.AddToWorklist(Op.getNode());
22075 if (Shuffle == X86ISD::MOVDDUP)
22076 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22078 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22079 DCI.AddToWorklist(Op.getNode());
22080 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22084 if (Subtarget->hasSSE3() &&
22085 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22086 bool Lo = Mask.equals({0, 0, 2, 2});
22087 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22088 MVT ShuffleVT = MVT::v4f32;
22089 if (Depth == 1 && Root->getOpcode() == Shuffle)
22090 return false; // Nothing to do!
22091 Op = DAG.getBitcast(ShuffleVT, Input);
22092 DCI.AddToWorklist(Op.getNode());
22093 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22094 DCI.AddToWorklist(Op.getNode());
22095 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22099 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22100 bool Lo = Mask.equals({0, 0, 1, 1});
22101 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22102 MVT ShuffleVT = MVT::v4f32;
22103 if (Depth == 1 && Root->getOpcode() == Shuffle)
22104 return false; // Nothing to do!
22105 Op = DAG.getBitcast(ShuffleVT, Input);
22106 DCI.AddToWorklist(Op.getNode());
22107 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22108 DCI.AddToWorklist(Op.getNode());
22109 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22115 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22116 // variants as none of these have single-instruction variants that are
22117 // superior to the UNPCK formulation.
22118 if (!FloatDomain && VT.getSizeInBits() == 128 &&
22119 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22120 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22121 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22123 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22124 bool Lo = Mask[0] == 0;
22125 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22126 if (Depth == 1 && Root->getOpcode() == Shuffle)
22127 return false; // Nothing to do!
22129 switch (Mask.size()) {
22131 ShuffleVT = MVT::v8i16;
22134 ShuffleVT = MVT::v16i8;
22137 llvm_unreachable("Impossible mask size!");
22139 Op = DAG.getBitcast(ShuffleVT, Input);
22140 DCI.AddToWorklist(Op.getNode());
22141 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22142 DCI.AddToWorklist(Op.getNode());
22143 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22148 // Don't try to re-form single instruction chains under any circumstances now
22149 // that we've done encoding canonicalization for them.
22153 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22154 // can replace them with a single PSHUFB instruction profitably. Intel's
22155 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22156 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22157 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22158 SmallVector<SDValue, 16> PSHUFBMask;
22159 int NumBytes = VT.getSizeInBits() / 8;
22160 int Ratio = NumBytes / Mask.size();
22161 for (int i = 0; i < NumBytes; ++i) {
22162 if (Mask[i / Ratio] == SM_SentinelUndef) {
22163 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22166 int M = Mask[i / Ratio] != SM_SentinelZero
22167 ? Ratio * Mask[i / Ratio] + i % Ratio
22169 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22171 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22172 Op = DAG.getBitcast(ByteVT, Input);
22173 DCI.AddToWorklist(Op.getNode());
22174 SDValue PSHUFBMaskOp =
22175 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22176 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22177 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22178 DCI.AddToWorklist(Op.getNode());
22179 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22184 // Failed to find any combines.
22188 /// \brief Fully generic combining of x86 shuffle instructions.
22190 /// This should be the last combine run over the x86 shuffle instructions. Once
22191 /// they have been fully optimized, this will recursively consider all chains
22192 /// of single-use shuffle instructions, build a generic model of the cumulative
22193 /// shuffle operation, and check for simpler instructions which implement this
22194 /// operation. We use this primarily for two purposes:
22196 /// 1) Collapse generic shuffles to specialized single instructions when
22197 /// equivalent. In most cases, this is just an encoding size win, but
22198 /// sometimes we will collapse multiple generic shuffles into a single
22199 /// special-purpose shuffle.
22200 /// 2) Look for sequences of shuffle instructions with 3 or more total
22201 /// instructions, and replace them with the slightly more expensive SSSE3
22202 /// PSHUFB instruction if available. We do this as the last combining step
22203 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22204 /// a suitable short sequence of other instructions. The PHUFB will either
22205 /// use a register or have to read from memory and so is slightly (but only
22206 /// slightly) more expensive than the other shuffle instructions.
22208 /// Because this is inherently a quadratic operation (for each shuffle in
22209 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22210 /// This should never be an issue in practice as the shuffle lowering doesn't
22211 /// produce sequences of more than 8 instructions.
22213 /// FIXME: We will currently miss some cases where the redundant shuffling
22214 /// would simplify under the threshold for PSHUFB formation because of
22215 /// combine-ordering. To fix this, we should do the redundant instruction
22216 /// combining in this recursive walk.
22217 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22218 ArrayRef<int> RootMask,
22219 int Depth, bool HasPSHUFB,
22221 TargetLowering::DAGCombinerInfo &DCI,
22222 const X86Subtarget *Subtarget) {
22223 // Bound the depth of our recursive combine because this is ultimately
22224 // quadratic in nature.
22228 // Directly rip through bitcasts to find the underlying operand.
22229 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22230 Op = Op.getOperand(0);
22232 MVT VT = Op.getSimpleValueType();
22233 if (!VT.isVector())
22234 return false; // Bail if we hit a non-vector.
22236 assert(Root.getSimpleValueType().isVector() &&
22237 "Shuffles operate on vector types!");
22238 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22239 "Can only combine shuffles of the same vector register size.");
22241 if (!isTargetShuffle(Op.getOpcode()))
22243 SmallVector<int, 16> OpMask;
22245 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22246 // We only can combine unary shuffles which we can decode the mask for.
22247 if (!HaveMask || !IsUnary)
22250 assert(VT.getVectorNumElements() == OpMask.size() &&
22251 "Different mask size from vector size!");
22252 assert(((RootMask.size() > OpMask.size() &&
22253 RootMask.size() % OpMask.size() == 0) ||
22254 (OpMask.size() > RootMask.size() &&
22255 OpMask.size() % RootMask.size() == 0) ||
22256 OpMask.size() == RootMask.size()) &&
22257 "The smaller number of elements must divide the larger.");
22258 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22259 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22260 assert(((RootRatio == 1 && OpRatio == 1) ||
22261 (RootRatio == 1) != (OpRatio == 1)) &&
22262 "Must not have a ratio for both incoming and op masks!");
22264 SmallVector<int, 16> Mask;
22265 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22267 // Merge this shuffle operation's mask into our accumulated mask. Note that
22268 // this shuffle's mask will be the first applied to the input, followed by the
22269 // root mask to get us all the way to the root value arrangement. The reason
22270 // for this order is that we are recursing up the operation chain.
22271 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22272 int RootIdx = i / RootRatio;
22273 if (RootMask[RootIdx] < 0) {
22274 // This is a zero or undef lane, we're done.
22275 Mask.push_back(RootMask[RootIdx]);
22279 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22280 int OpIdx = RootMaskedIdx / OpRatio;
22281 if (OpMask[OpIdx] < 0) {
22282 // The incoming lanes are zero or undef, it doesn't matter which ones we
22284 Mask.push_back(OpMask[OpIdx]);
22288 // Ok, we have non-zero lanes, map them through.
22289 Mask.push_back(OpMask[OpIdx] * OpRatio +
22290 RootMaskedIdx % OpRatio);
22293 // See if we can recurse into the operand to combine more things.
22294 switch (Op.getOpcode()) {
22295 case X86ISD::PSHUFB:
22297 case X86ISD::PSHUFD:
22298 case X86ISD::PSHUFHW:
22299 case X86ISD::PSHUFLW:
22300 if (Op.getOperand(0).hasOneUse() &&
22301 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22302 HasPSHUFB, DAG, DCI, Subtarget))
22306 case X86ISD::UNPCKL:
22307 case X86ISD::UNPCKH:
22308 assert(Op.getOperand(0) == Op.getOperand(1) &&
22309 "We only combine unary shuffles!");
22310 // We can't check for single use, we have to check that this shuffle is the
22312 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22313 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22314 HasPSHUFB, DAG, DCI, Subtarget))
22319 // Minor canonicalization of the accumulated shuffle mask to make it easier
22320 // to match below. All this does is detect masks with squential pairs of
22321 // elements, and shrink them to the half-width mask. It does this in a loop
22322 // so it will reduce the size of the mask to the minimal width mask which
22323 // performs an equivalent shuffle.
22324 SmallVector<int, 16> WidenedMask;
22325 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22326 Mask = std::move(WidenedMask);
22327 WidenedMask.clear();
22330 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22334 /// \brief Get the PSHUF-style mask from PSHUF node.
22336 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22337 /// PSHUF-style masks that can be reused with such instructions.
22338 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22339 MVT VT = N.getSimpleValueType();
22340 SmallVector<int, 4> Mask;
22342 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22346 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22347 // matter. Check that the upper masks are repeats and remove them.
22348 if (VT.getSizeInBits() > 128) {
22349 int LaneElts = 128 / VT.getScalarSizeInBits();
22351 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22352 for (int j = 0; j < LaneElts; ++j)
22353 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22354 "Mask doesn't repeat in high 128-bit lanes!");
22356 Mask.resize(LaneElts);
22359 switch (N.getOpcode()) {
22360 case X86ISD::PSHUFD:
22362 case X86ISD::PSHUFLW:
22365 case X86ISD::PSHUFHW:
22366 Mask.erase(Mask.begin(), Mask.begin() + 4);
22367 for (int &M : Mask)
22371 llvm_unreachable("No valid shuffle instruction found!");
22375 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22377 /// We walk up the chain and look for a combinable shuffle, skipping over
22378 /// shuffles that we could hoist this shuffle's transformation past without
22379 /// altering anything.
22381 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22383 TargetLowering::DAGCombinerInfo &DCI) {
22384 assert(N.getOpcode() == X86ISD::PSHUFD &&
22385 "Called with something other than an x86 128-bit half shuffle!");
22388 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22389 // of the shuffles in the chain so that we can form a fresh chain to replace
22391 SmallVector<SDValue, 8> Chain;
22392 SDValue V = N.getOperand(0);
22393 for (; V.hasOneUse(); V = V.getOperand(0)) {
22394 switch (V.getOpcode()) {
22396 return SDValue(); // Nothing combined!
22399 // Skip bitcasts as we always know the type for the target specific
22403 case X86ISD::PSHUFD:
22404 // Found another dword shuffle.
22407 case X86ISD::PSHUFLW:
22408 // Check that the low words (being shuffled) are the identity in the
22409 // dword shuffle, and the high words are self-contained.
22410 if (Mask[0] != 0 || Mask[1] != 1 ||
22411 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22414 Chain.push_back(V);
22417 case X86ISD::PSHUFHW:
22418 // Check that the high words (being shuffled) are the identity in the
22419 // dword shuffle, and the low words are self-contained.
22420 if (Mask[2] != 2 || Mask[3] != 3 ||
22421 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22424 Chain.push_back(V);
22427 case X86ISD::UNPCKL:
22428 case X86ISD::UNPCKH:
22429 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22430 // shuffle into a preceding word shuffle.
22431 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22432 V.getSimpleValueType().getScalarType() != MVT::i16)
22435 // Search for a half-shuffle which we can combine with.
22436 unsigned CombineOp =
22437 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22438 if (V.getOperand(0) != V.getOperand(1) ||
22439 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22441 Chain.push_back(V);
22442 V = V.getOperand(0);
22444 switch (V.getOpcode()) {
22446 return SDValue(); // Nothing to combine.
22448 case X86ISD::PSHUFLW:
22449 case X86ISD::PSHUFHW:
22450 if (V.getOpcode() == CombineOp)
22453 Chain.push_back(V);
22457 V = V.getOperand(0);
22461 } while (V.hasOneUse());
22464 // Break out of the loop if we break out of the switch.
22468 if (!V.hasOneUse())
22469 // We fell out of the loop without finding a viable combining instruction.
22472 // Merge this node's mask and our incoming mask.
22473 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22474 for (int &M : Mask)
22476 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22477 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22479 // Rebuild the chain around this new shuffle.
22480 while (!Chain.empty()) {
22481 SDValue W = Chain.pop_back_val();
22483 if (V.getValueType() != W.getOperand(0).getValueType())
22484 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22486 switch (W.getOpcode()) {
22488 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22490 case X86ISD::UNPCKL:
22491 case X86ISD::UNPCKH:
22492 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22495 case X86ISD::PSHUFD:
22496 case X86ISD::PSHUFLW:
22497 case X86ISD::PSHUFHW:
22498 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22502 if (V.getValueType() != N.getValueType())
22503 V = DAG.getBitcast(N.getValueType(), V);
22505 // Return the new chain to replace N.
22509 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22512 /// We walk up the chain, skipping shuffles of the other half and looking
22513 /// through shuffles which switch halves trying to find a shuffle of the same
22514 /// pair of dwords.
22515 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22517 TargetLowering::DAGCombinerInfo &DCI) {
22519 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22520 "Called with something other than an x86 128-bit half shuffle!");
22522 unsigned CombineOpcode = N.getOpcode();
22524 // Walk up a single-use chain looking for a combinable shuffle.
22525 SDValue V = N.getOperand(0);
22526 for (; V.hasOneUse(); V = V.getOperand(0)) {
22527 switch (V.getOpcode()) {
22529 return false; // Nothing combined!
22532 // Skip bitcasts as we always know the type for the target specific
22536 case X86ISD::PSHUFLW:
22537 case X86ISD::PSHUFHW:
22538 if (V.getOpcode() == CombineOpcode)
22541 // Other-half shuffles are no-ops.
22544 // Break out of the loop if we break out of the switch.
22548 if (!V.hasOneUse())
22549 // We fell out of the loop without finding a viable combining instruction.
22552 // Combine away the bottom node as its shuffle will be accumulated into
22553 // a preceding shuffle.
22554 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22556 // Record the old value.
22559 // Merge this node's mask and our incoming mask (adjusted to account for all
22560 // the pshufd instructions encountered).
22561 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22562 for (int &M : Mask)
22564 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22565 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22567 // Check that the shuffles didn't cancel each other out. If not, we need to
22568 // combine to the new one.
22570 // Replace the combinable shuffle with the combined one, updating all users
22571 // so that we re-evaluate the chain here.
22572 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22577 /// \brief Try to combine x86 target specific shuffles.
22578 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22579 TargetLowering::DAGCombinerInfo &DCI,
22580 const X86Subtarget *Subtarget) {
22582 MVT VT = N.getSimpleValueType();
22583 SmallVector<int, 4> Mask;
22585 switch (N.getOpcode()) {
22586 case X86ISD::PSHUFD:
22587 case X86ISD::PSHUFLW:
22588 case X86ISD::PSHUFHW:
22589 Mask = getPSHUFShuffleMask(N);
22590 assert(Mask.size() == 4);
22596 // Nuke no-op shuffles that show up after combining.
22597 if (isNoopShuffleMask(Mask))
22598 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22600 // Look for simplifications involving one or two shuffle instructions.
22601 SDValue V = N.getOperand(0);
22602 switch (N.getOpcode()) {
22605 case X86ISD::PSHUFLW:
22606 case X86ISD::PSHUFHW:
22607 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22609 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22610 return SDValue(); // We combined away this shuffle, so we're done.
22612 // See if this reduces to a PSHUFD which is no more expensive and can
22613 // combine with more operations. Note that it has to at least flip the
22614 // dwords as otherwise it would have been removed as a no-op.
22615 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22616 int DMask[] = {0, 1, 2, 3};
22617 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22618 DMask[DOffset + 0] = DOffset + 1;
22619 DMask[DOffset + 1] = DOffset + 0;
22620 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22621 V = DAG.getBitcast(DVT, V);
22622 DCI.AddToWorklist(V.getNode());
22623 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22624 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22625 DCI.AddToWorklist(V.getNode());
22626 return DAG.getBitcast(VT, V);
22629 // Look for shuffle patterns which can be implemented as a single unpack.
22630 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22631 // only works when we have a PSHUFD followed by two half-shuffles.
22632 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22633 (V.getOpcode() == X86ISD::PSHUFLW ||
22634 V.getOpcode() == X86ISD::PSHUFHW) &&
22635 V.getOpcode() != N.getOpcode() &&
22637 SDValue D = V.getOperand(0);
22638 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22639 D = D.getOperand(0);
22640 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22641 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22642 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22643 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22644 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22646 for (int i = 0; i < 4; ++i) {
22647 WordMask[i + NOffset] = Mask[i] + NOffset;
22648 WordMask[i + VOffset] = VMask[i] + VOffset;
22650 // Map the word mask through the DWord mask.
22652 for (int i = 0; i < 8; ++i)
22653 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22654 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22655 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22656 // We can replace all three shuffles with an unpack.
22657 V = DAG.getBitcast(VT, D.getOperand(0));
22658 DCI.AddToWorklist(V.getNode());
22659 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22668 case X86ISD::PSHUFD:
22669 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22678 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22680 /// We combine this directly on the abstract vector shuffle nodes so it is
22681 /// easier to generically match. We also insert dummy vector shuffle nodes for
22682 /// the operands which explicitly discard the lanes which are unused by this
22683 /// operation to try to flow through the rest of the combiner the fact that
22684 /// they're unused.
22685 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22687 EVT VT = N->getValueType(0);
22689 // We only handle target-independent shuffles.
22690 // FIXME: It would be easy and harmless to use the target shuffle mask
22691 // extraction tool to support more.
22692 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22695 auto *SVN = cast<ShuffleVectorSDNode>(N);
22696 ArrayRef<int> Mask = SVN->getMask();
22697 SDValue V1 = N->getOperand(0);
22698 SDValue V2 = N->getOperand(1);
22700 // We require the first shuffle operand to be the SUB node, and the second to
22701 // be the ADD node.
22702 // FIXME: We should support the commuted patterns.
22703 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22706 // If there are other uses of these operations we can't fold them.
22707 if (!V1->hasOneUse() || !V2->hasOneUse())
22710 // Ensure that both operations have the same operands. Note that we can
22711 // commute the FADD operands.
22712 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22713 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22714 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22717 // We're looking for blends between FADD and FSUB nodes. We insist on these
22718 // nodes being lined up in a specific expected pattern.
22719 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22720 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22721 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22724 // Only specific types are legal at this point, assert so we notice if and
22725 // when these change.
22726 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22727 VT == MVT::v4f64) &&
22728 "Unknown vector type encountered!");
22730 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22733 /// PerformShuffleCombine - Performs several different shuffle combines.
22734 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22735 TargetLowering::DAGCombinerInfo &DCI,
22736 const X86Subtarget *Subtarget) {
22738 SDValue N0 = N->getOperand(0);
22739 SDValue N1 = N->getOperand(1);
22740 EVT VT = N->getValueType(0);
22742 // Don't create instructions with illegal types after legalize types has run.
22743 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22744 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22747 // If we have legalized the vector types, look for blends of FADD and FSUB
22748 // nodes that we can fuse into an ADDSUB node.
22749 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22750 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22753 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22754 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22755 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22756 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22758 // During Type Legalization, when promoting illegal vector types,
22759 // the backend might introduce new shuffle dag nodes and bitcasts.
22761 // This code performs the following transformation:
22762 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22763 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22765 // We do this only if both the bitcast and the BINOP dag nodes have
22766 // one use. Also, perform this transformation only if the new binary
22767 // operation is legal. This is to avoid introducing dag nodes that
22768 // potentially need to be further expanded (or custom lowered) into a
22769 // less optimal sequence of dag nodes.
22770 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22771 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22772 N0.getOpcode() == ISD::BITCAST) {
22773 SDValue BC0 = N0.getOperand(0);
22774 EVT SVT = BC0.getValueType();
22775 unsigned Opcode = BC0.getOpcode();
22776 unsigned NumElts = VT.getVectorNumElements();
22778 if (BC0.hasOneUse() && SVT.isVector() &&
22779 SVT.getVectorNumElements() * 2 == NumElts &&
22780 TLI.isOperationLegal(Opcode, VT)) {
22781 bool CanFold = false;
22793 unsigned SVTNumElts = SVT.getVectorNumElements();
22794 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22795 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22796 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22797 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22798 CanFold = SVOp->getMaskElt(i) < 0;
22801 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22802 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
22803 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22804 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22809 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22810 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22811 // consecutive, non-overlapping, and in the right order.
22812 SmallVector<SDValue, 16> Elts;
22813 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22814 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22816 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
22819 if (isTargetShuffle(N->getOpcode())) {
22821 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22822 if (Shuffle.getNode())
22825 // Try recursively combining arbitrary sequences of x86 shuffle
22826 // instructions into higher-order shuffles. We do this after combining
22827 // specific PSHUF instruction sequences into their minimal form so that we
22828 // can evaluate how many specialized shuffle instructions are involved in
22829 // a particular chain.
22830 SmallVector<int, 1> NonceMask; // Just a placeholder.
22831 NonceMask.push_back(0);
22832 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22833 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22835 return SDValue(); // This routine will use CombineTo to replace N.
22841 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22842 /// specific shuffle of a load can be folded into a single element load.
22843 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22844 /// shuffles have been custom lowered so we need to handle those here.
22845 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22846 TargetLowering::DAGCombinerInfo &DCI) {
22847 if (DCI.isBeforeLegalizeOps())
22850 SDValue InVec = N->getOperand(0);
22851 SDValue EltNo = N->getOperand(1);
22853 if (!isa<ConstantSDNode>(EltNo))
22856 EVT OriginalVT = InVec.getValueType();
22858 if (InVec.getOpcode() == ISD::BITCAST) {
22859 // Don't duplicate a load with other uses.
22860 if (!InVec.hasOneUse())
22862 EVT BCVT = InVec.getOperand(0).getValueType();
22863 if (!BCVT.isVector() ||
22864 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22866 InVec = InVec.getOperand(0);
22869 EVT CurrentVT = InVec.getValueType();
22871 if (!isTargetShuffle(InVec.getOpcode()))
22874 // Don't duplicate a load with other uses.
22875 if (!InVec.hasOneUse())
22878 SmallVector<int, 16> ShuffleMask;
22880 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22881 ShuffleMask, UnaryShuffle))
22884 // Select the input vector, guarding against out of range extract vector.
22885 unsigned NumElems = CurrentVT.getVectorNumElements();
22886 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22887 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22888 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22889 : InVec.getOperand(1);
22891 // If inputs to shuffle are the same for both ops, then allow 2 uses
22892 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
22893 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22895 if (LdNode.getOpcode() == ISD::BITCAST) {
22896 // Don't duplicate a load with other uses.
22897 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22900 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22901 LdNode = LdNode.getOperand(0);
22904 if (!ISD::isNormalLoad(LdNode.getNode()))
22907 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22909 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22912 EVT EltVT = N->getValueType(0);
22913 // If there's a bitcast before the shuffle, check if the load type and
22914 // alignment is valid.
22915 unsigned Align = LN0->getAlignment();
22916 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22917 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
22918 EltVT.getTypeForEVT(*DAG.getContext()));
22920 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22923 // All checks match so transform back to vector_shuffle so that DAG combiner
22924 // can finish the job
22927 // Create shuffle node taking into account the case that its a unary shuffle
22928 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22929 : InVec.getOperand(1);
22930 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22931 InVec.getOperand(0), Shuffle,
22933 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
22934 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22938 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
22939 /// special and don't usually play with other vector types, it's better to
22940 /// handle them early to be sure we emit efficient code by avoiding
22941 /// store-load conversions.
22942 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
22943 if (N->getValueType(0) != MVT::x86mmx ||
22944 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
22945 N->getOperand(0)->getValueType(0) != MVT::v2i32)
22948 SDValue V = N->getOperand(0);
22949 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
22950 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
22951 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
22952 N->getValueType(0), V.getOperand(0));
22957 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22958 /// generation and convert it from being a bunch of shuffles and extracts
22959 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22960 /// storing the value and loading scalars back, while for x64 we should
22961 /// use 64-bit extracts and shifts.
22962 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22963 TargetLowering::DAGCombinerInfo &DCI) {
22964 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
22967 SDValue InputVector = N->getOperand(0);
22968 SDLoc dl(InputVector);
22969 // Detect mmx to i32 conversion through a v2i32 elt extract.
22970 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
22971 N->getValueType(0) == MVT::i32 &&
22972 InputVector.getValueType() == MVT::v2i32) {
22974 // The bitcast source is a direct mmx result.
22975 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
22976 if (MMXSrc.getValueType() == MVT::x86mmx)
22977 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22978 N->getValueType(0),
22979 InputVector.getNode()->getOperand(0));
22981 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
22982 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
22983 MMXSrc.getValueType() == MVT::i64) {
22984 SDValue MMXSrcOp = MMXSrc.getOperand(0);
22985 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
22986 MMXSrcOp.getValueType() == MVT::v1i64 &&
22987 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
22988 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22989 N->getValueType(0), MMXSrcOp.getOperand(0));
22993 EVT VT = N->getValueType(0);
22995 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
22996 InputVector.getOpcode() == ISD::BITCAST &&
22997 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
22998 uint64_t ExtractedElt =
22999 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23000 uint64_t InputValue =
23001 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23002 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23003 return DAG.getConstant(Res, dl, MVT::i1);
23005 // Only operate on vectors of 4 elements, where the alternative shuffling
23006 // gets to be more expensive.
23007 if (InputVector.getValueType() != MVT::v4i32)
23010 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23011 // single use which is a sign-extend or zero-extend, and all elements are
23013 SmallVector<SDNode *, 4> Uses;
23014 unsigned ExtractedElements = 0;
23015 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23016 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23017 if (UI.getUse().getResNo() != InputVector.getResNo())
23020 SDNode *Extract = *UI;
23021 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23024 if (Extract->getValueType(0) != MVT::i32)
23026 if (!Extract->hasOneUse())
23028 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23029 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23031 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23034 // Record which element was extracted.
23035 ExtractedElements |=
23036 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23038 Uses.push_back(Extract);
23041 // If not all the elements were used, this may not be worthwhile.
23042 if (ExtractedElements != 15)
23045 // Ok, we've now decided to do the transformation.
23046 // If 64-bit shifts are legal, use the extract-shift sequence,
23047 // otherwise bounce the vector off the cache.
23048 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23051 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23052 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23053 auto &DL = DAG.getDataLayout();
23054 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23055 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23056 DAG.getConstant(0, dl, VecIdxTy));
23057 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23058 DAG.getConstant(1, dl, VecIdxTy));
23060 SDValue ShAmt = DAG.getConstant(
23061 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23062 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23063 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23064 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23065 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23066 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23067 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23069 // Store the value to a temporary stack slot.
23070 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23071 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23072 MachinePointerInfo(), false, false, 0);
23074 EVT ElementType = InputVector.getValueType().getVectorElementType();
23075 unsigned EltSize = ElementType.getSizeInBits() / 8;
23077 // Replace each use (extract) with a load of the appropriate element.
23078 for (unsigned i = 0; i < 4; ++i) {
23079 uint64_t Offset = EltSize * i;
23080 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23081 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23083 SDValue ScalarAddr =
23084 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23086 // Load the scalar.
23087 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23088 ScalarAddr, MachinePointerInfo(),
23089 false, false, false, 0);
23094 // Replace the extracts
23095 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23096 UE = Uses.end(); UI != UE; ++UI) {
23097 SDNode *Extract = *UI;
23099 SDValue Idx = Extract->getOperand(1);
23100 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23101 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23104 // The replacement was made in place; don't return anything.
23109 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23110 const X86Subtarget *Subtarget) {
23112 SDValue Cond = N->getOperand(0);
23113 SDValue LHS = N->getOperand(1);
23114 SDValue RHS = N->getOperand(2);
23116 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23117 SDValue CondSrc = Cond->getOperand(0);
23118 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23119 Cond = CondSrc->getOperand(0);
23122 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23125 // A vselect where all conditions and data are constants can be optimized into
23126 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23127 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23128 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23131 unsigned MaskValue = 0;
23132 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23135 MVT VT = N->getSimpleValueType(0);
23136 unsigned NumElems = VT.getVectorNumElements();
23137 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23138 for (unsigned i = 0; i < NumElems; ++i) {
23139 // Be sure we emit undef where we can.
23140 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23141 ShuffleMask[i] = -1;
23143 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23146 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23147 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23149 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23152 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23154 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23155 TargetLowering::DAGCombinerInfo &DCI,
23156 const X86Subtarget *Subtarget) {
23158 SDValue Cond = N->getOperand(0);
23159 // Get the LHS/RHS of the select.
23160 SDValue LHS = N->getOperand(1);
23161 SDValue RHS = N->getOperand(2);
23162 EVT VT = LHS.getValueType();
23163 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23165 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23166 // instructions match the semantics of the common C idiom x<y?x:y but not
23167 // x<=y?x:y, because of how they handle negative zero (which can be
23168 // ignored in unsafe-math mode).
23169 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23170 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23171 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23172 (Subtarget->hasSSE2() ||
23173 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23174 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23176 unsigned Opcode = 0;
23177 // Check for x CC y ? x : y.
23178 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23179 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23183 // Converting this to a min would handle NaNs incorrectly, and swapping
23184 // the operands would cause it to handle comparisons between positive
23185 // and negative zero incorrectly.
23186 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23187 if (!DAG.getTarget().Options.UnsafeFPMath &&
23188 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23190 std::swap(LHS, RHS);
23192 Opcode = X86ISD::FMIN;
23195 // Converting this to a min would handle comparisons between positive
23196 // and negative zero incorrectly.
23197 if (!DAG.getTarget().Options.UnsafeFPMath &&
23198 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23200 Opcode = X86ISD::FMIN;
23203 // Converting this to a min would handle both negative zeros and NaNs
23204 // incorrectly, but we can swap the operands to fix both.
23205 std::swap(LHS, RHS);
23209 Opcode = X86ISD::FMIN;
23213 // Converting this to a max would handle comparisons between positive
23214 // and negative zero incorrectly.
23215 if (!DAG.getTarget().Options.UnsafeFPMath &&
23216 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23218 Opcode = X86ISD::FMAX;
23221 // Converting this to a max would handle NaNs incorrectly, and swapping
23222 // the operands would cause it to handle comparisons between positive
23223 // and negative zero incorrectly.
23224 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23225 if (!DAG.getTarget().Options.UnsafeFPMath &&
23226 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23228 std::swap(LHS, RHS);
23230 Opcode = X86ISD::FMAX;
23233 // Converting this to a max would handle both negative zeros and NaNs
23234 // incorrectly, but we can swap the operands to fix both.
23235 std::swap(LHS, RHS);
23239 Opcode = X86ISD::FMAX;
23242 // Check for x CC y ? y : x -- a min/max with reversed arms.
23243 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23244 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23248 // Converting this to a min would handle comparisons between positive
23249 // and negative zero incorrectly, and swapping the operands would
23250 // cause it to handle NaNs incorrectly.
23251 if (!DAG.getTarget().Options.UnsafeFPMath &&
23252 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23253 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23255 std::swap(LHS, RHS);
23257 Opcode = X86ISD::FMIN;
23260 // Converting this to a min would handle NaNs incorrectly.
23261 if (!DAG.getTarget().Options.UnsafeFPMath &&
23262 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23264 Opcode = X86ISD::FMIN;
23267 // Converting this to a min would handle both negative zeros and NaNs
23268 // incorrectly, but we can swap the operands to fix both.
23269 std::swap(LHS, RHS);
23273 Opcode = X86ISD::FMIN;
23277 // Converting this to a max would handle NaNs incorrectly.
23278 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23280 Opcode = X86ISD::FMAX;
23283 // Converting this to a max would handle comparisons between positive
23284 // and negative zero incorrectly, and swapping the operands would
23285 // cause it to handle NaNs incorrectly.
23286 if (!DAG.getTarget().Options.UnsafeFPMath &&
23287 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23288 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23290 std::swap(LHS, RHS);
23292 Opcode = X86ISD::FMAX;
23295 // Converting this to a max would handle both negative zeros and NaNs
23296 // incorrectly, but we can swap the operands to fix both.
23297 std::swap(LHS, RHS);
23301 Opcode = X86ISD::FMAX;
23307 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23310 EVT CondVT = Cond.getValueType();
23311 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23312 CondVT.getVectorElementType() == MVT::i1) {
23313 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23314 // lowering on KNL. In this case we convert it to
23315 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23316 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23317 // Since SKX these selects have a proper lowering.
23318 EVT OpVT = LHS.getValueType();
23319 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23320 (OpVT.getVectorElementType() == MVT::i8 ||
23321 OpVT.getVectorElementType() == MVT::i16) &&
23322 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23323 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23324 DCI.AddToWorklist(Cond.getNode());
23325 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23328 // If this is a select between two integer constants, try to do some
23330 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23331 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23332 // Don't do this for crazy integer types.
23333 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23334 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23335 // so that TrueC (the true value) is larger than FalseC.
23336 bool NeedsCondInvert = false;
23338 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23339 // Efficiently invertible.
23340 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23341 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23342 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23343 NeedsCondInvert = true;
23344 std::swap(TrueC, FalseC);
23347 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23348 if (FalseC->getAPIntValue() == 0 &&
23349 TrueC->getAPIntValue().isPowerOf2()) {
23350 if (NeedsCondInvert) // Invert the condition if needed.
23351 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23352 DAG.getConstant(1, DL, Cond.getValueType()));
23354 // Zero extend the condition if needed.
23355 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23357 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23358 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23359 DAG.getConstant(ShAmt, DL, MVT::i8));
23362 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23363 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23364 if (NeedsCondInvert) // Invert the condition if needed.
23365 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23366 DAG.getConstant(1, DL, Cond.getValueType()));
23368 // Zero extend the condition if needed.
23369 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23370 FalseC->getValueType(0), Cond);
23371 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23372 SDValue(FalseC, 0));
23375 // Optimize cases that will turn into an LEA instruction. This requires
23376 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23377 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23378 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23379 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23381 bool isFastMultiplier = false;
23383 switch ((unsigned char)Diff) {
23385 case 1: // result = add base, cond
23386 case 2: // result = lea base( , cond*2)
23387 case 3: // result = lea base(cond, cond*2)
23388 case 4: // result = lea base( , cond*4)
23389 case 5: // result = lea base(cond, cond*4)
23390 case 8: // result = lea base( , cond*8)
23391 case 9: // result = lea base(cond, cond*8)
23392 isFastMultiplier = true;
23397 if (isFastMultiplier) {
23398 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23399 if (NeedsCondInvert) // Invert the condition if needed.
23400 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23401 DAG.getConstant(1, DL, Cond.getValueType()));
23403 // Zero extend the condition if needed.
23404 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23406 // Scale the condition by the difference.
23408 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23409 DAG.getConstant(Diff, DL,
23410 Cond.getValueType()));
23412 // Add the base if non-zero.
23413 if (FalseC->getAPIntValue() != 0)
23414 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23415 SDValue(FalseC, 0));
23422 // Canonicalize max and min:
23423 // (x > y) ? x : y -> (x >= y) ? x : y
23424 // (x < y) ? x : y -> (x <= y) ? x : y
23425 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23426 // the need for an extra compare
23427 // against zero. e.g.
23428 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23430 // testl %edi, %edi
23432 // cmovgl %edi, %eax
23436 // cmovsl %eax, %edi
23437 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23438 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23439 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23440 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23445 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23446 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23447 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23448 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23453 // Early exit check
23454 if (!TLI.isTypeLegal(VT))
23457 // Match VSELECTs into subs with unsigned saturation.
23458 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23459 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23460 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23461 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23462 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23464 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23465 // left side invert the predicate to simplify logic below.
23467 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23469 CC = ISD::getSetCCInverse(CC, true);
23470 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23474 if (Other.getNode() && Other->getNumOperands() == 2 &&
23475 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23476 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23477 SDValue CondRHS = Cond->getOperand(1);
23479 // Look for a general sub with unsigned saturation first.
23480 // x >= y ? x-y : 0 --> subus x, y
23481 // x > y ? x-y : 0 --> subus x, y
23482 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23483 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23484 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23486 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23487 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23488 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23489 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23490 // If the RHS is a constant we have to reverse the const
23491 // canonicalization.
23492 // x > C-1 ? x+-C : 0 --> subus x, C
23493 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23494 CondRHSConst->getAPIntValue() ==
23495 (-OpRHSConst->getAPIntValue() - 1))
23496 return DAG.getNode(
23497 X86ISD::SUBUS, DL, VT, OpLHS,
23498 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23500 // Another special case: If C was a sign bit, the sub has been
23501 // canonicalized into a xor.
23502 // FIXME: Would it be better to use computeKnownBits to determine
23503 // whether it's safe to decanonicalize the xor?
23504 // x s< 0 ? x^C : 0 --> subus x, C
23505 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23506 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23507 OpRHSConst->getAPIntValue().isSignBit())
23508 // Note that we have to rebuild the RHS constant here to ensure we
23509 // don't rely on particular values of undef lanes.
23510 return DAG.getNode(
23511 X86ISD::SUBUS, DL, VT, OpLHS,
23512 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23517 // Simplify vector selection if condition value type matches vselect
23519 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23520 assert(Cond.getValueType().isVector() &&
23521 "vector select expects a vector selector!");
23523 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23524 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23526 // Try invert the condition if true value is not all 1s and false value
23528 if (!TValIsAllOnes && !FValIsAllZeros &&
23529 // Check if the selector will be produced by CMPP*/PCMP*
23530 Cond.getOpcode() == ISD::SETCC &&
23531 // Check if SETCC has already been promoted
23532 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23534 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23535 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23537 if (TValIsAllZeros || FValIsAllOnes) {
23538 SDValue CC = Cond.getOperand(2);
23539 ISD::CondCode NewCC =
23540 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23541 Cond.getOperand(0).getValueType().isInteger());
23542 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23543 std::swap(LHS, RHS);
23544 TValIsAllOnes = FValIsAllOnes;
23545 FValIsAllZeros = TValIsAllZeros;
23549 if (TValIsAllOnes || FValIsAllZeros) {
23552 if (TValIsAllOnes && FValIsAllZeros)
23554 else if (TValIsAllOnes)
23556 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23557 else if (FValIsAllZeros)
23558 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23559 DAG.getBitcast(CondVT, LHS));
23561 return DAG.getBitcast(VT, Ret);
23565 // We should generate an X86ISD::BLENDI from a vselect if its argument
23566 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23567 // constants. This specific pattern gets generated when we split a
23568 // selector for a 512 bit vector in a machine without AVX512 (but with
23569 // 256-bit vectors), during legalization:
23571 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23573 // Iff we find this pattern and the build_vectors are built from
23574 // constants, we translate the vselect into a shuffle_vector that we
23575 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23576 if ((N->getOpcode() == ISD::VSELECT ||
23577 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23578 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23579 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23580 if (Shuffle.getNode())
23584 // If this is a *dynamic* select (non-constant condition) and we can match
23585 // this node with one of the variable blend instructions, restructure the
23586 // condition so that the blends can use the high bit of each element and use
23587 // SimplifyDemandedBits to simplify the condition operand.
23588 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23589 !DCI.isBeforeLegalize() &&
23590 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23591 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23593 // Don't optimize vector selects that map to mask-registers.
23597 // We can only handle the cases where VSELECT is directly legal on the
23598 // subtarget. We custom lower VSELECT nodes with constant conditions and
23599 // this makes it hard to see whether a dynamic VSELECT will correctly
23600 // lower, so we both check the operation's status and explicitly handle the
23601 // cases where a *dynamic* blend will fail even though a constant-condition
23602 // blend could be custom lowered.
23603 // FIXME: We should find a better way to handle this class of problems.
23604 // Potentially, we should combine constant-condition vselect nodes
23605 // pre-legalization into shuffles and not mark as many types as custom
23607 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23609 // FIXME: We don't support i16-element blends currently. We could and
23610 // should support them by making *all* the bits in the condition be set
23611 // rather than just the high bit and using an i8-element blend.
23612 if (VT.getScalarType() == MVT::i16)
23614 // Dynamic blending was only available from SSE4.1 onward.
23615 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23617 // Byte blends are only available in AVX2
23618 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23619 !Subtarget->hasAVX2())
23622 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23623 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23625 APInt KnownZero, KnownOne;
23626 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23627 DCI.isBeforeLegalizeOps());
23628 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23629 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23631 // If we changed the computation somewhere in the DAG, this change
23632 // will affect all users of Cond.
23633 // Make sure it is fine and update all the nodes so that we do not
23634 // use the generic VSELECT anymore. Otherwise, we may perform
23635 // wrong optimizations as we messed up with the actual expectation
23636 // for the vector boolean values.
23637 if (Cond != TLO.Old) {
23638 // Check all uses of that condition operand to check whether it will be
23639 // consumed by non-BLEND instructions, which may depend on all bits are
23641 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23643 if (I->getOpcode() != ISD::VSELECT)
23644 // TODO: Add other opcodes eventually lowered into BLEND.
23647 // Update all the users of the condition, before committing the change,
23648 // so that the VSELECT optimizations that expect the correct vector
23649 // boolean value will not be triggered.
23650 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23652 DAG.ReplaceAllUsesOfValueWith(
23654 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23655 Cond, I->getOperand(1), I->getOperand(2)));
23656 DCI.CommitTargetLoweringOpt(TLO);
23659 // At this point, only Cond is changed. Change the condition
23660 // just for N to keep the opportunity to optimize all other
23661 // users their own way.
23662 DAG.ReplaceAllUsesOfValueWith(
23664 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23665 TLO.New, N->getOperand(1), N->getOperand(2)));
23673 // Check whether a boolean test is testing a boolean value generated by
23674 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23677 // Simplify the following patterns:
23678 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23679 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23680 // to (Op EFLAGS Cond)
23682 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23683 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23684 // to (Op EFLAGS !Cond)
23686 // where Op could be BRCOND or CMOV.
23688 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23689 // Quit if not CMP and SUB with its value result used.
23690 if (Cmp.getOpcode() != X86ISD::CMP &&
23691 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23694 // Quit if not used as a boolean value.
23695 if (CC != X86::COND_E && CC != X86::COND_NE)
23698 // Check CMP operands. One of them should be 0 or 1 and the other should be
23699 // an SetCC or extended from it.
23700 SDValue Op1 = Cmp.getOperand(0);
23701 SDValue Op2 = Cmp.getOperand(1);
23704 const ConstantSDNode* C = nullptr;
23705 bool needOppositeCond = (CC == X86::COND_E);
23706 bool checkAgainstTrue = false; // Is it a comparison against 1?
23708 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23710 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23712 else // Quit if all operands are not constants.
23715 if (C->getZExtValue() == 1) {
23716 needOppositeCond = !needOppositeCond;
23717 checkAgainstTrue = true;
23718 } else if (C->getZExtValue() != 0)
23719 // Quit if the constant is neither 0 or 1.
23722 bool truncatedToBoolWithAnd = false;
23723 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23724 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23725 SetCC.getOpcode() == ISD::TRUNCATE ||
23726 SetCC.getOpcode() == ISD::AND) {
23727 if (SetCC.getOpcode() == ISD::AND) {
23729 ConstantSDNode *CS;
23730 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23731 CS->getZExtValue() == 1)
23733 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23734 CS->getZExtValue() == 1)
23738 SetCC = SetCC.getOperand(OpIdx);
23739 truncatedToBoolWithAnd = true;
23741 SetCC = SetCC.getOperand(0);
23744 switch (SetCC.getOpcode()) {
23745 case X86ISD::SETCC_CARRY:
23746 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23747 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23748 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23749 // truncated to i1 using 'and'.
23750 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23752 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23753 "Invalid use of SETCC_CARRY!");
23755 case X86ISD::SETCC:
23756 // Set the condition code or opposite one if necessary.
23757 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23758 if (needOppositeCond)
23759 CC = X86::GetOppositeBranchCondition(CC);
23760 return SetCC.getOperand(1);
23761 case X86ISD::CMOV: {
23762 // Check whether false/true value has canonical one, i.e. 0 or 1.
23763 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23764 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23765 // Quit if true value is not a constant.
23768 // Quit if false value is not a constant.
23770 SDValue Op = SetCC.getOperand(0);
23771 // Skip 'zext' or 'trunc' node.
23772 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23773 Op.getOpcode() == ISD::TRUNCATE)
23774 Op = Op.getOperand(0);
23775 // A special case for rdrand/rdseed, where 0 is set if false cond is
23777 if ((Op.getOpcode() != X86ISD::RDRAND &&
23778 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23781 // Quit if false value is not the constant 0 or 1.
23782 bool FValIsFalse = true;
23783 if (FVal && FVal->getZExtValue() != 0) {
23784 if (FVal->getZExtValue() != 1)
23786 // If FVal is 1, opposite cond is needed.
23787 needOppositeCond = !needOppositeCond;
23788 FValIsFalse = false;
23790 // Quit if TVal is not the constant opposite of FVal.
23791 if (FValIsFalse && TVal->getZExtValue() != 1)
23793 if (!FValIsFalse && TVal->getZExtValue() != 0)
23795 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23796 if (needOppositeCond)
23797 CC = X86::GetOppositeBranchCondition(CC);
23798 return SetCC.getOperand(3);
23805 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
23807 /// (X86or (X86setcc) (X86setcc))
23808 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
23809 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
23810 X86::CondCode &CC1, SDValue &Flags,
23812 if (Cond->getOpcode() == X86ISD::CMP) {
23813 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
23814 if (!CondOp1C || !CondOp1C->isNullValue())
23817 Cond = Cond->getOperand(0);
23822 SDValue SetCC0, SetCC1;
23823 switch (Cond->getOpcode()) {
23824 default: return false;
23831 SetCC0 = Cond->getOperand(0);
23832 SetCC1 = Cond->getOperand(1);
23836 // Make sure we have SETCC nodes, using the same flags value.
23837 if (SetCC0.getOpcode() != X86ISD::SETCC ||
23838 SetCC1.getOpcode() != X86ISD::SETCC ||
23839 SetCC0->getOperand(1) != SetCC1->getOperand(1))
23842 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
23843 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
23844 Flags = SetCC0->getOperand(1);
23848 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23849 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23850 TargetLowering::DAGCombinerInfo &DCI,
23851 const X86Subtarget *Subtarget) {
23854 // If the flag operand isn't dead, don't touch this CMOV.
23855 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23858 SDValue FalseOp = N->getOperand(0);
23859 SDValue TrueOp = N->getOperand(1);
23860 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23861 SDValue Cond = N->getOperand(3);
23863 if (CC == X86::COND_E || CC == X86::COND_NE) {
23864 switch (Cond.getOpcode()) {
23868 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23869 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23870 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23876 Flags = checkBoolTestSetCCCombine(Cond, CC);
23877 if (Flags.getNode() &&
23878 // Extra check as FCMOV only supports a subset of X86 cond.
23879 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23880 SDValue Ops[] = { FalseOp, TrueOp,
23881 DAG.getConstant(CC, DL, MVT::i8), Flags };
23882 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23885 // If this is a select between two integer constants, try to do some
23886 // optimizations. Note that the operands are ordered the opposite of SELECT
23888 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23889 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23890 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23891 // larger than FalseC (the false value).
23892 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23893 CC = X86::GetOppositeBranchCondition(CC);
23894 std::swap(TrueC, FalseC);
23895 std::swap(TrueOp, FalseOp);
23898 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23899 // This is efficient for any integer data type (including i8/i16) and
23901 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23902 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23903 DAG.getConstant(CC, DL, MVT::i8), Cond);
23905 // Zero extend the condition if needed.
23906 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23908 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23909 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23910 DAG.getConstant(ShAmt, DL, MVT::i8));
23911 if (N->getNumValues() == 2) // Dead flag value?
23912 return DCI.CombineTo(N, Cond, SDValue());
23916 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23917 // for any integer data type, including i8/i16.
23918 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23919 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23920 DAG.getConstant(CC, DL, MVT::i8), Cond);
23922 // Zero extend the condition if needed.
23923 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23924 FalseC->getValueType(0), Cond);
23925 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23926 SDValue(FalseC, 0));
23928 if (N->getNumValues() == 2) // Dead flag value?
23929 return DCI.CombineTo(N, Cond, SDValue());
23933 // Optimize cases that will turn into an LEA instruction. This requires
23934 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23935 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23936 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23937 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23939 bool isFastMultiplier = false;
23941 switch ((unsigned char)Diff) {
23943 case 1: // result = add base, cond
23944 case 2: // result = lea base( , cond*2)
23945 case 3: // result = lea base(cond, cond*2)
23946 case 4: // result = lea base( , cond*4)
23947 case 5: // result = lea base(cond, cond*4)
23948 case 8: // result = lea base( , cond*8)
23949 case 9: // result = lea base(cond, cond*8)
23950 isFastMultiplier = true;
23955 if (isFastMultiplier) {
23956 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23957 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23958 DAG.getConstant(CC, DL, MVT::i8), Cond);
23959 // Zero extend the condition if needed.
23960 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23962 // Scale the condition by the difference.
23964 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23965 DAG.getConstant(Diff, DL, Cond.getValueType()));
23967 // Add the base if non-zero.
23968 if (FalseC->getAPIntValue() != 0)
23969 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23970 SDValue(FalseC, 0));
23971 if (N->getNumValues() == 2) // Dead flag value?
23972 return DCI.CombineTo(N, Cond, SDValue());
23979 // Handle these cases:
23980 // (select (x != c), e, c) -> select (x != c), e, x),
23981 // (select (x == c), c, e) -> select (x == c), x, e)
23982 // where the c is an integer constant, and the "select" is the combination
23983 // of CMOV and CMP.
23985 // The rationale for this change is that the conditional-move from a constant
23986 // needs two instructions, however, conditional-move from a register needs
23987 // only one instruction.
23989 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23990 // some instruction-combining opportunities. This opt needs to be
23991 // postponed as late as possible.
23993 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23994 // the DCI.xxxx conditions are provided to postpone the optimization as
23995 // late as possible.
23997 ConstantSDNode *CmpAgainst = nullptr;
23998 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23999 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24000 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24002 if (CC == X86::COND_NE &&
24003 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24004 CC = X86::GetOppositeBranchCondition(CC);
24005 std::swap(TrueOp, FalseOp);
24008 if (CC == X86::COND_E &&
24009 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24010 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24011 DAG.getConstant(CC, DL, MVT::i8), Cond };
24012 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24017 // Fold and/or of setcc's to double CMOV:
24018 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24019 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24021 // This combine lets us generate:
24022 // cmovcc1 (jcc1 if we don't have CMOV)
24028 // cmovne (jne if we don't have CMOV)
24029 // When we can't use the CMOV instruction, it might increase branch
24031 // When we can use CMOV, or when there is no mispredict, this improves
24032 // throughput and reduces register pressure.
24034 if (CC == X86::COND_NE) {
24036 X86::CondCode CC0, CC1;
24038 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24040 std::swap(FalseOp, TrueOp);
24041 CC0 = X86::GetOppositeBranchCondition(CC0);
24042 CC1 = X86::GetOppositeBranchCondition(CC1);
24045 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24047 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24048 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24049 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24050 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24058 /// PerformMulCombine - Optimize a single multiply with constant into two
24059 /// in order to implement it with two cheaper instructions, e.g.
24060 /// LEA + SHL, LEA + LEA.
24061 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24062 TargetLowering::DAGCombinerInfo &DCI) {
24063 // An imul is usually smaller than the alternative sequence.
24064 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24067 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24070 EVT VT = N->getValueType(0);
24071 if (VT != MVT::i64 && VT != MVT::i32)
24074 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24077 uint64_t MulAmt = C->getZExtValue();
24078 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24081 uint64_t MulAmt1 = 0;
24082 uint64_t MulAmt2 = 0;
24083 if ((MulAmt % 9) == 0) {
24085 MulAmt2 = MulAmt / 9;
24086 } else if ((MulAmt % 5) == 0) {
24088 MulAmt2 = MulAmt / 5;
24089 } else if ((MulAmt % 3) == 0) {
24091 MulAmt2 = MulAmt / 3;
24094 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24097 if (isPowerOf2_64(MulAmt2) &&
24098 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24099 // If second multiplifer is pow2, issue it first. We want the multiply by
24100 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24102 std::swap(MulAmt1, MulAmt2);
24105 if (isPowerOf2_64(MulAmt1))
24106 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24107 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24109 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24110 DAG.getConstant(MulAmt1, DL, VT));
24112 if (isPowerOf2_64(MulAmt2))
24113 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24114 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24116 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24117 DAG.getConstant(MulAmt2, DL, VT));
24119 // Do not add new nodes to DAG combiner worklist.
24120 DCI.CombineTo(N, NewMul, false);
24125 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24126 SDValue N0 = N->getOperand(0);
24127 SDValue N1 = N->getOperand(1);
24128 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24129 EVT VT = N0.getValueType();
24131 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24132 // since the result of setcc_c is all zero's or all ones.
24133 if (VT.isInteger() && !VT.isVector() &&
24134 N1C && N0.getOpcode() == ISD::AND &&
24135 N0.getOperand(1).getOpcode() == ISD::Constant) {
24136 SDValue N00 = N0.getOperand(0);
24137 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24138 APInt ShAmt = N1C->getAPIntValue();
24139 Mask = Mask.shl(ShAmt);
24140 bool MaskOK = false;
24141 // We can handle cases concerning bit-widening nodes containing setcc_c if
24142 // we carefully interrogate the mask to make sure we are semantics
24144 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24145 // of the underlying setcc_c operation if the setcc_c was zero extended.
24146 // Consider the following example:
24147 // zext(setcc_c) -> i32 0x0000FFFF
24148 // c1 -> i32 0x0000FFFF
24149 // c2 -> i32 0x00000001
24150 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24151 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24152 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24154 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24155 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24157 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24158 N00.getOpcode() == ISD::ANY_EXTEND) &&
24159 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24160 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24162 if (MaskOK && Mask != 0) {
24164 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24168 // Hardware support for vector shifts is sparse which makes us scalarize the
24169 // vector operations in many cases. Also, on sandybridge ADD is faster than
24171 // (shl V, 1) -> add V,V
24172 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24173 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24174 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24175 // We shift all of the values by one. In many cases we do not have
24176 // hardware support for this operation. This is better expressed as an ADD
24178 if (N1SplatC->getAPIntValue() == 1)
24179 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24185 /// \brief Returns a vector of 0s if the node in input is a vector logical
24186 /// shift by a constant amount which is known to be bigger than or equal
24187 /// to the vector element size in bits.
24188 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24189 const X86Subtarget *Subtarget) {
24190 EVT VT = N->getValueType(0);
24192 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24193 (!Subtarget->hasInt256() ||
24194 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24197 SDValue Amt = N->getOperand(1);
24199 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24200 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24201 APInt ShiftAmt = AmtSplat->getAPIntValue();
24202 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24204 // SSE2/AVX2 logical shifts always return a vector of 0s
24205 // if the shift amount is bigger than or equal to
24206 // the element size. The constant shift amount will be
24207 // encoded as a 8-bit immediate.
24208 if (ShiftAmt.trunc(8).uge(MaxAmount))
24209 return getZeroVector(VT, Subtarget, DAG, DL);
24215 /// PerformShiftCombine - Combine shifts.
24216 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24217 TargetLowering::DAGCombinerInfo &DCI,
24218 const X86Subtarget *Subtarget) {
24219 if (N->getOpcode() == ISD::SHL)
24220 if (SDValue V = PerformSHLCombine(N, DAG))
24223 // Try to fold this logical shift into a zero vector.
24224 if (N->getOpcode() != ISD::SRA)
24225 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24231 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24232 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24233 // and friends. Likewise for OR -> CMPNEQSS.
24234 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24235 TargetLowering::DAGCombinerInfo &DCI,
24236 const X86Subtarget *Subtarget) {
24239 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24240 // we're requiring SSE2 for both.
24241 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24242 SDValue N0 = N->getOperand(0);
24243 SDValue N1 = N->getOperand(1);
24244 SDValue CMP0 = N0->getOperand(1);
24245 SDValue CMP1 = N1->getOperand(1);
24248 // The SETCCs should both refer to the same CMP.
24249 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24252 SDValue CMP00 = CMP0->getOperand(0);
24253 SDValue CMP01 = CMP0->getOperand(1);
24254 EVT VT = CMP00.getValueType();
24256 if (VT == MVT::f32 || VT == MVT::f64) {
24257 bool ExpectingFlags = false;
24258 // Check for any users that want flags:
24259 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24260 !ExpectingFlags && UI != UE; ++UI)
24261 switch (UI->getOpcode()) {
24266 ExpectingFlags = true;
24268 case ISD::CopyToReg:
24269 case ISD::SIGN_EXTEND:
24270 case ISD::ZERO_EXTEND:
24271 case ISD::ANY_EXTEND:
24275 if (!ExpectingFlags) {
24276 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24277 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24279 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24280 X86::CondCode tmp = cc0;
24285 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24286 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24287 // FIXME: need symbolic constants for these magic numbers.
24288 // See X86ATTInstPrinter.cpp:printSSECC().
24289 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24290 if (Subtarget->hasAVX512()) {
24291 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24293 DAG.getConstant(x86cc, DL, MVT::i8));
24294 if (N->getValueType(0) != MVT::i1)
24295 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24299 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24300 CMP00.getValueType(), CMP00, CMP01,
24301 DAG.getConstant(x86cc, DL,
24304 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24305 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24307 if (is64BitFP && !Subtarget->is64Bit()) {
24308 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24309 // 64-bit integer, since that's not a legal type. Since
24310 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24311 // bits, but can do this little dance to extract the lowest 32 bits
24312 // and work with those going forward.
24313 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24315 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24316 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24317 Vector32, DAG.getIntPtrConstant(0, DL));
24321 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24322 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24323 DAG.getConstant(1, DL, IntVT));
24324 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24326 return OneBitOfTruth;
24334 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24335 /// so it can be folded inside ANDNP.
24336 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24337 EVT VT = N->getValueType(0);
24339 // Match direct AllOnes for 128 and 256-bit vectors
24340 if (ISD::isBuildVectorAllOnes(N))
24343 // Look through a bit convert.
24344 if (N->getOpcode() == ISD::BITCAST)
24345 N = N->getOperand(0).getNode();
24347 // Sometimes the operand may come from a insert_subvector building a 256-bit
24349 if (VT.is256BitVector() &&
24350 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24351 SDValue V1 = N->getOperand(0);
24352 SDValue V2 = N->getOperand(1);
24354 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24355 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24356 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24357 ISD::isBuildVectorAllOnes(V2.getNode()))
24364 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24365 // register. In most cases we actually compare or select YMM-sized registers
24366 // and mixing the two types creates horrible code. This method optimizes
24367 // some of the transition sequences.
24368 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24369 TargetLowering::DAGCombinerInfo &DCI,
24370 const X86Subtarget *Subtarget) {
24371 EVT VT = N->getValueType(0);
24372 if (!VT.is256BitVector())
24375 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24376 N->getOpcode() == ISD::ZERO_EXTEND ||
24377 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24379 SDValue Narrow = N->getOperand(0);
24380 EVT NarrowVT = Narrow->getValueType(0);
24381 if (!NarrowVT.is128BitVector())
24384 if (Narrow->getOpcode() != ISD::XOR &&
24385 Narrow->getOpcode() != ISD::AND &&
24386 Narrow->getOpcode() != ISD::OR)
24389 SDValue N0 = Narrow->getOperand(0);
24390 SDValue N1 = Narrow->getOperand(1);
24393 // The Left side has to be a trunc.
24394 if (N0.getOpcode() != ISD::TRUNCATE)
24397 // The type of the truncated inputs.
24398 EVT WideVT = N0->getOperand(0)->getValueType(0);
24402 // The right side has to be a 'trunc' or a constant vector.
24403 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24404 ConstantSDNode *RHSConstSplat = nullptr;
24405 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24406 RHSConstSplat = RHSBV->getConstantSplatNode();
24407 if (!RHSTrunc && !RHSConstSplat)
24410 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24412 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24415 // Set N0 and N1 to hold the inputs to the new wide operation.
24416 N0 = N0->getOperand(0);
24417 if (RHSConstSplat) {
24418 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24419 SDValue(RHSConstSplat, 0));
24420 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24421 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24422 } else if (RHSTrunc) {
24423 N1 = N1->getOperand(0);
24426 // Generate the wide operation.
24427 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24428 unsigned Opcode = N->getOpcode();
24430 case ISD::ANY_EXTEND:
24432 case ISD::ZERO_EXTEND: {
24433 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24434 APInt Mask = APInt::getAllOnesValue(InBits);
24435 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24436 return DAG.getNode(ISD::AND, DL, VT,
24437 Op, DAG.getConstant(Mask, DL, VT));
24439 case ISD::SIGN_EXTEND:
24440 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24441 Op, DAG.getValueType(NarrowVT));
24443 llvm_unreachable("Unexpected opcode");
24447 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24448 TargetLowering::DAGCombinerInfo &DCI,
24449 const X86Subtarget *Subtarget) {
24450 SDValue N0 = N->getOperand(0);
24451 SDValue N1 = N->getOperand(1);
24454 // A vector zext_in_reg may be represented as a shuffle,
24455 // feeding into a bitcast (this represents anyext) feeding into
24456 // an and with a mask.
24457 // We'd like to try to combine that into a shuffle with zero
24458 // plus a bitcast, removing the and.
24459 if (N0.getOpcode() != ISD::BITCAST ||
24460 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24463 // The other side of the AND should be a splat of 2^C, where C
24464 // is the number of bits in the source type.
24465 if (N1.getOpcode() == ISD::BITCAST)
24466 N1 = N1.getOperand(0);
24467 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24469 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24471 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24472 EVT SrcType = Shuffle->getValueType(0);
24474 // We expect a single-source shuffle
24475 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24478 unsigned SrcSize = SrcType.getScalarSizeInBits();
24480 APInt SplatValue, SplatUndef;
24481 unsigned SplatBitSize;
24483 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24484 SplatBitSize, HasAnyUndefs))
24487 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24488 // Make sure the splat matches the mask we expect
24489 if (SplatBitSize > ResSize ||
24490 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24493 // Make sure the input and output size make sense
24494 if (SrcSize >= ResSize || ResSize % SrcSize)
24497 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24498 // The number of u's between each two values depends on the ratio between
24499 // the source and dest type.
24500 unsigned ZextRatio = ResSize / SrcSize;
24501 bool IsZext = true;
24502 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24503 if (i % ZextRatio) {
24504 if (Shuffle->getMaskElt(i) > 0) {
24510 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24511 // Expected element number
24521 // Ok, perform the transformation - replace the shuffle with
24522 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24523 // (instead of undef) where the k elements come from the zero vector.
24524 SmallVector<int, 8> Mask;
24525 unsigned NumElems = SrcType.getVectorNumElements();
24526 for (unsigned i = 0; i < NumElems; ++i)
24528 Mask.push_back(NumElems);
24530 Mask.push_back(i / ZextRatio);
24532 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24533 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24534 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24537 /// If both input operands of a logic op are being cast from floating point
24538 /// types, try to convert this into a floating point logic node to avoid
24539 /// unnecessary moves from SSE to integer registers.
24540 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24541 const X86Subtarget *Subtarget) {
24542 unsigned FPOpcode = ISD::DELETED_NODE;
24543 if (N->getOpcode() == ISD::AND)
24544 FPOpcode = X86ISD::FAND;
24545 else if (N->getOpcode() == ISD::OR)
24546 FPOpcode = X86ISD::FOR;
24547 else if (N->getOpcode() == ISD::XOR)
24548 FPOpcode = X86ISD::FXOR;
24550 assert(FPOpcode != ISD::DELETED_NODE &&
24551 "Unexpected input node for FP logic conversion");
24553 EVT VT = N->getValueType(0);
24554 SDValue N0 = N->getOperand(0);
24555 SDValue N1 = N->getOperand(1);
24557 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
24558 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
24559 (Subtarget->hasSSE2() && VT == MVT::i64))) {
24560 SDValue N00 = N0.getOperand(0);
24561 SDValue N10 = N1.getOperand(0);
24562 EVT N00Type = N00.getValueType();
24563 EVT N10Type = N10.getValueType();
24564 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
24565 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
24566 return DAG.getBitcast(VT, FPLogic);
24572 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24573 TargetLowering::DAGCombinerInfo &DCI,
24574 const X86Subtarget *Subtarget) {
24575 if (DCI.isBeforeLegalizeOps())
24578 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24581 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24584 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24587 EVT VT = N->getValueType(0);
24588 SDValue N0 = N->getOperand(0);
24589 SDValue N1 = N->getOperand(1);
24592 // Create BEXTR instructions
24593 // BEXTR is ((X >> imm) & (2**size-1))
24594 if (VT == MVT::i32 || VT == MVT::i64) {
24595 // Check for BEXTR.
24596 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24597 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24598 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24599 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24600 if (MaskNode && ShiftNode) {
24601 uint64_t Mask = MaskNode->getZExtValue();
24602 uint64_t Shift = ShiftNode->getZExtValue();
24603 if (isMask_64(Mask)) {
24604 uint64_t MaskSize = countPopulation(Mask);
24605 if (Shift + MaskSize <= VT.getSizeInBits())
24606 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24607 DAG.getConstant(Shift | (MaskSize << 8), DL,
24616 // Want to form ANDNP nodes:
24617 // 1) In the hopes of then easily combining them with OR and AND nodes
24618 // to form PBLEND/PSIGN.
24619 // 2) To match ANDN packed intrinsics
24620 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24623 // Check LHS for vnot
24624 if (N0.getOpcode() == ISD::XOR &&
24625 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24626 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24627 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24629 // Check RHS for vnot
24630 if (N1.getOpcode() == ISD::XOR &&
24631 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24632 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24633 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24638 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24639 TargetLowering::DAGCombinerInfo &DCI,
24640 const X86Subtarget *Subtarget) {
24641 if (DCI.isBeforeLegalizeOps())
24644 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24647 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24650 SDValue N0 = N->getOperand(0);
24651 SDValue N1 = N->getOperand(1);
24652 EVT VT = N->getValueType(0);
24654 // look for psign/blend
24655 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24656 if (!Subtarget->hasSSSE3() ||
24657 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24660 // Canonicalize pandn to RHS
24661 if (N0.getOpcode() == X86ISD::ANDNP)
24663 // or (and (m, y), (pandn m, x))
24664 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24665 SDValue Mask = N1.getOperand(0);
24666 SDValue X = N1.getOperand(1);
24668 if (N0.getOperand(0) == Mask)
24669 Y = N0.getOperand(1);
24670 if (N0.getOperand(1) == Mask)
24671 Y = N0.getOperand(0);
24673 // Check to see if the mask appeared in both the AND and ANDNP and
24677 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24678 // Look through mask bitcast.
24679 if (Mask.getOpcode() == ISD::BITCAST)
24680 Mask = Mask.getOperand(0);
24681 if (X.getOpcode() == ISD::BITCAST)
24682 X = X.getOperand(0);
24683 if (Y.getOpcode() == ISD::BITCAST)
24684 Y = Y.getOperand(0);
24686 EVT MaskVT = Mask.getValueType();
24688 // Validate that the Mask operand is a vector sra node.
24689 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24690 // there is no psrai.b
24691 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24692 unsigned SraAmt = ~0;
24693 if (Mask.getOpcode() == ISD::SRA) {
24694 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24695 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24696 SraAmt = AmtConst->getZExtValue();
24697 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24698 SDValue SraC = Mask.getOperand(1);
24699 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24701 if ((SraAmt + 1) != EltBits)
24706 // Now we know we at least have a plendvb with the mask val. See if
24707 // we can form a psignb/w/d.
24708 // psign = x.type == y.type == mask.type && y = sub(0, x);
24709 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24710 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24711 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24712 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24713 "Unsupported VT for PSIGN");
24714 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24715 return DAG.getBitcast(VT, Mask);
24717 // PBLENDVB only available on SSE 4.1
24718 if (!Subtarget->hasSSE41())
24721 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24723 X = DAG.getBitcast(BlendVT, X);
24724 Y = DAG.getBitcast(BlendVT, Y);
24725 Mask = DAG.getBitcast(BlendVT, Mask);
24726 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24727 return DAG.getBitcast(VT, Mask);
24731 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24734 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24735 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24737 // SHLD/SHRD instructions have lower register pressure, but on some
24738 // platforms they have higher latency than the equivalent
24739 // series of shifts/or that would otherwise be generated.
24740 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24741 // have higher latencies and we are not optimizing for size.
24742 if (!OptForSize && Subtarget->isSHLDSlow())
24745 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24747 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24749 if (!N0.hasOneUse() || !N1.hasOneUse())
24752 SDValue ShAmt0 = N0.getOperand(1);
24753 if (ShAmt0.getValueType() != MVT::i8)
24755 SDValue ShAmt1 = N1.getOperand(1);
24756 if (ShAmt1.getValueType() != MVT::i8)
24758 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24759 ShAmt0 = ShAmt0.getOperand(0);
24760 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24761 ShAmt1 = ShAmt1.getOperand(0);
24764 unsigned Opc = X86ISD::SHLD;
24765 SDValue Op0 = N0.getOperand(0);
24766 SDValue Op1 = N1.getOperand(0);
24767 if (ShAmt0.getOpcode() == ISD::SUB) {
24768 Opc = X86ISD::SHRD;
24769 std::swap(Op0, Op1);
24770 std::swap(ShAmt0, ShAmt1);
24773 unsigned Bits = VT.getSizeInBits();
24774 if (ShAmt1.getOpcode() == ISD::SUB) {
24775 SDValue Sum = ShAmt1.getOperand(0);
24776 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24777 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24778 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24779 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24780 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24781 return DAG.getNode(Opc, DL, VT,
24783 DAG.getNode(ISD::TRUNCATE, DL,
24786 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24787 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24789 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24790 return DAG.getNode(Opc, DL, VT,
24791 N0.getOperand(0), N1.getOperand(0),
24792 DAG.getNode(ISD::TRUNCATE, DL,
24799 // Generate NEG and CMOV for integer abs.
24800 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24801 EVT VT = N->getValueType(0);
24803 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24804 // 8-bit integer abs to NEG and CMOV.
24805 if (VT.isInteger() && VT.getSizeInBits() == 8)
24808 SDValue N0 = N->getOperand(0);
24809 SDValue N1 = N->getOperand(1);
24812 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24813 // and change it to SUB and CMOV.
24814 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24815 N0.getOpcode() == ISD::ADD &&
24816 N0.getOperand(1) == N1 &&
24817 N1.getOpcode() == ISD::SRA &&
24818 N1.getOperand(0) == N0.getOperand(0))
24819 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24820 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24821 // Generate SUB & CMOV.
24822 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24823 DAG.getConstant(0, DL, VT), N0.getOperand(0));
24825 SDValue Ops[] = { N0.getOperand(0), Neg,
24826 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
24827 SDValue(Neg.getNode(), 1) };
24828 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24833 // Try to turn tests against the signbit in the form of:
24834 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
24837 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
24838 // This is only worth doing if the output type is i8.
24839 if (N->getValueType(0) != MVT::i8)
24842 SDValue N0 = N->getOperand(0);
24843 SDValue N1 = N->getOperand(1);
24845 // We should be performing an xor against a truncated shift.
24846 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
24849 // Make sure we are performing an xor against one.
24850 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
24853 // SetCC on x86 zero extends so only act on this if it's a logical shift.
24854 SDValue Shift = N0.getOperand(0);
24855 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
24858 // Make sure we are truncating from one of i16, i32 or i64.
24859 EVT ShiftTy = Shift.getValueType();
24860 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
24863 // Make sure the shift amount extracts the sign bit.
24864 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
24865 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
24868 // Create a greater-than comparison against -1.
24869 // N.B. Using SETGE against 0 works but we want a canonical looking
24870 // comparison, using SETGT matches up with what TranslateX86CC.
24872 SDValue ShiftOp = Shift.getOperand(0);
24873 EVT ShiftOpTy = ShiftOp.getValueType();
24874 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
24875 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
24879 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24880 TargetLowering::DAGCombinerInfo &DCI,
24881 const X86Subtarget *Subtarget) {
24882 if (DCI.isBeforeLegalizeOps())
24885 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
24888 if (Subtarget->hasCMov())
24889 if (SDValue RV = performIntegerAbsCombine(N, DAG))
24892 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24898 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24899 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24900 TargetLowering::DAGCombinerInfo &DCI,
24901 const X86Subtarget *Subtarget) {
24902 LoadSDNode *Ld = cast<LoadSDNode>(N);
24903 EVT RegVT = Ld->getValueType(0);
24904 EVT MemVT = Ld->getMemoryVT();
24906 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24908 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24909 // into two 16-byte operations.
24910 ISD::LoadExtType Ext = Ld->getExtensionType();
24912 unsigned AddressSpace = Ld->getAddressSpace();
24913 unsigned Alignment = Ld->getAlignment();
24914 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
24915 Ext == ISD::NON_EXTLOAD &&
24916 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
24917 AddressSpace, Alignment, &Fast) && !Fast) {
24918 unsigned NumElems = RegVT.getVectorNumElements();
24922 SDValue Ptr = Ld->getBasePtr();
24923 SDValue Increment =
24924 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24926 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24928 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24929 Ld->getPointerInfo(), Ld->isVolatile(),
24930 Ld->isNonTemporal(), Ld->isInvariant(),
24932 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24933 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24934 Ld->getPointerInfo(), Ld->isVolatile(),
24935 Ld->isNonTemporal(), Ld->isInvariant(),
24936 std::min(16U, Alignment));
24937 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24939 Load2.getValue(1));
24941 SDValue NewVec = DAG.getUNDEF(RegVT);
24942 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24943 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24944 return DCI.CombineTo(N, NewVec, TF, true);
24950 /// PerformMLOADCombine - Resolve extending loads
24951 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
24952 TargetLowering::DAGCombinerInfo &DCI,
24953 const X86Subtarget *Subtarget) {
24954 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
24955 if (Mld->getExtensionType() != ISD::SEXTLOAD)
24958 EVT VT = Mld->getValueType(0);
24959 unsigned NumElems = VT.getVectorNumElements();
24960 EVT LdVT = Mld->getMemoryVT();
24963 assert(LdVT != VT && "Cannot extend to the same type");
24964 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
24965 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
24966 // From, To sizes and ElemCount must be pow of two
24967 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
24968 "Unexpected size for extending masked load");
24970 unsigned SizeRatio = ToSz / FromSz;
24971 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
24973 // Create a type on which we perform the shuffle
24974 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24975 LdVT.getScalarType(), NumElems*SizeRatio);
24976 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24978 // Convert Src0 value
24979 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
24980 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
24981 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24982 for (unsigned i = 0; i != NumElems; ++i)
24983 ShuffleVec[i] = i * SizeRatio;
24985 // Can't shuffle using an illegal type.
24986 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
24987 "WideVecVT should be legal");
24988 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
24989 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
24991 // Prepare the new mask
24993 SDValue Mask = Mld->getMask();
24994 if (Mask.getValueType() == VT) {
24995 // Mask and original value have the same type
24996 NewMask = DAG.getBitcast(WideVecVT, Mask);
24997 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
24998 for (unsigned i = 0; i != NumElems; ++i)
24999 ShuffleVec[i] = i * SizeRatio;
25000 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25001 ShuffleVec[i] = NumElems*SizeRatio;
25002 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25003 DAG.getConstant(0, dl, WideVecVT),
25007 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25008 unsigned WidenNumElts = NumElems*SizeRatio;
25009 unsigned MaskNumElts = VT.getVectorNumElements();
25010 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25013 unsigned NumConcat = WidenNumElts / MaskNumElts;
25014 SmallVector<SDValue, 16> Ops(NumConcat);
25015 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25017 for (unsigned i = 1; i != NumConcat; ++i)
25020 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25023 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25024 Mld->getBasePtr(), NewMask, WideSrc0,
25025 Mld->getMemoryVT(), Mld->getMemOperand(),
25027 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25028 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25030 /// PerformMSTORECombine - Resolve truncating stores
25031 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25032 const X86Subtarget *Subtarget) {
25033 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25034 if (!Mst->isTruncatingStore())
25037 EVT VT = Mst->getValue().getValueType();
25038 unsigned NumElems = VT.getVectorNumElements();
25039 EVT StVT = Mst->getMemoryVT();
25042 assert(StVT != VT && "Cannot truncate to the same type");
25043 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25044 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25046 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25048 // The truncating store is legal in some cases. For example
25049 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25050 // are designated for truncate store.
25051 // In this case we don't need any further transformations.
25052 if (TLI.isTruncStoreLegal(VT, StVT))
25055 // From, To sizes and ElemCount must be pow of two
25056 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25057 "Unexpected size for truncating masked store");
25058 // We are going to use the original vector elt for storing.
25059 // Accumulated smaller vector elements must be a multiple of the store size.
25060 assert (((NumElems * FromSz) % ToSz) == 0 &&
25061 "Unexpected ratio for truncating masked store");
25063 unsigned SizeRatio = FromSz / ToSz;
25064 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25066 // Create a type on which we perform the shuffle
25067 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25068 StVT.getScalarType(), NumElems*SizeRatio);
25070 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25072 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25073 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25074 for (unsigned i = 0; i != NumElems; ++i)
25075 ShuffleVec[i] = i * SizeRatio;
25077 // Can't shuffle using an illegal type.
25078 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25079 "WideVecVT should be legal");
25081 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25082 DAG.getUNDEF(WideVecVT),
25086 SDValue Mask = Mst->getMask();
25087 if (Mask.getValueType() == VT) {
25088 // Mask and original value have the same type
25089 NewMask = DAG.getBitcast(WideVecVT, Mask);
25090 for (unsigned i = 0; i != NumElems; ++i)
25091 ShuffleVec[i] = i * SizeRatio;
25092 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25093 ShuffleVec[i] = NumElems*SizeRatio;
25094 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25095 DAG.getConstant(0, dl, WideVecVT),
25099 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25100 unsigned WidenNumElts = NumElems*SizeRatio;
25101 unsigned MaskNumElts = VT.getVectorNumElements();
25102 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25105 unsigned NumConcat = WidenNumElts / MaskNumElts;
25106 SmallVector<SDValue, 16> Ops(NumConcat);
25107 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25109 for (unsigned i = 1; i != NumConcat; ++i)
25112 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25115 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25116 NewMask, StVT, Mst->getMemOperand(), false);
25118 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25119 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25120 const X86Subtarget *Subtarget) {
25121 StoreSDNode *St = cast<StoreSDNode>(N);
25122 EVT VT = St->getValue().getValueType();
25123 EVT StVT = St->getMemoryVT();
25125 SDValue StoredVal = St->getOperand(1);
25126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25128 // If we are saving a concatenation of two XMM registers and 32-byte stores
25129 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25131 unsigned AddressSpace = St->getAddressSpace();
25132 unsigned Alignment = St->getAlignment();
25133 if (VT.is256BitVector() && StVT == VT &&
25134 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25135 AddressSpace, Alignment, &Fast) && !Fast) {
25136 unsigned NumElems = VT.getVectorNumElements();
25140 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25141 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25144 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25145 SDValue Ptr0 = St->getBasePtr();
25146 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25148 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25149 St->getPointerInfo(), St->isVolatile(),
25150 St->isNonTemporal(), Alignment);
25151 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25152 St->getPointerInfo(), St->isVolatile(),
25153 St->isNonTemporal(),
25154 std::min(16U, Alignment));
25155 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25158 // Optimize trunc store (of multiple scalars) to shuffle and store.
25159 // First, pack all of the elements in one place. Next, store to memory
25160 // in fewer chunks.
25161 if (St->isTruncatingStore() && VT.isVector()) {
25162 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25163 unsigned NumElems = VT.getVectorNumElements();
25164 assert(StVT != VT && "Cannot truncate to the same type");
25165 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25166 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25168 // The truncating store is legal in some cases. For example
25169 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25170 // are designated for truncate store.
25171 // In this case we don't need any further transformations.
25172 if (TLI.isTruncStoreLegal(VT, StVT))
25175 // From, To sizes and ElemCount must be pow of two
25176 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25177 // We are going to use the original vector elt for storing.
25178 // Accumulated smaller vector elements must be a multiple of the store size.
25179 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25181 unsigned SizeRatio = FromSz / ToSz;
25183 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25185 // Create a type on which we perform the shuffle
25186 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25187 StVT.getScalarType(), NumElems*SizeRatio);
25189 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25191 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25192 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25193 for (unsigned i = 0; i != NumElems; ++i)
25194 ShuffleVec[i] = i * SizeRatio;
25196 // Can't shuffle using an illegal type.
25197 if (!TLI.isTypeLegal(WideVecVT))
25200 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25201 DAG.getUNDEF(WideVecVT),
25203 // At this point all of the data is stored at the bottom of the
25204 // register. We now need to save it to mem.
25206 // Find the largest store unit
25207 MVT StoreType = MVT::i8;
25208 for (MVT Tp : MVT::integer_valuetypes()) {
25209 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25213 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25214 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25215 (64 <= NumElems * ToSz))
25216 StoreType = MVT::f64;
25218 // Bitcast the original vector into a vector of store-size units
25219 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25220 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25221 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25222 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25223 SmallVector<SDValue, 8> Chains;
25224 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25225 TLI.getPointerTy(DAG.getDataLayout()));
25226 SDValue Ptr = St->getBasePtr();
25228 // Perform one or more big stores into memory.
25229 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25230 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25231 StoreType, ShuffWide,
25232 DAG.getIntPtrConstant(i, dl));
25233 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25234 St->getPointerInfo(), St->isVolatile(),
25235 St->isNonTemporal(), St->getAlignment());
25236 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25237 Chains.push_back(Ch);
25240 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25243 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25244 // the FP state in cases where an emms may be missing.
25245 // A preferable solution to the general problem is to figure out the right
25246 // places to insert EMMS. This qualifies as a quick hack.
25248 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25249 if (VT.getSizeInBits() != 64)
25252 const Function *F = DAG.getMachineFunction().getFunction();
25253 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25255 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25256 if ((VT.isVector() ||
25257 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25258 isa<LoadSDNode>(St->getValue()) &&
25259 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25260 St->getChain().hasOneUse() && !St->isVolatile()) {
25261 SDNode* LdVal = St->getValue().getNode();
25262 LoadSDNode *Ld = nullptr;
25263 int TokenFactorIndex = -1;
25264 SmallVector<SDValue, 8> Ops;
25265 SDNode* ChainVal = St->getChain().getNode();
25266 // Must be a store of a load. We currently handle two cases: the load
25267 // is a direct child, and it's under an intervening TokenFactor. It is
25268 // possible to dig deeper under nested TokenFactors.
25269 if (ChainVal == LdVal)
25270 Ld = cast<LoadSDNode>(St->getChain());
25271 else if (St->getValue().hasOneUse() &&
25272 ChainVal->getOpcode() == ISD::TokenFactor) {
25273 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25274 if (ChainVal->getOperand(i).getNode() == LdVal) {
25275 TokenFactorIndex = i;
25276 Ld = cast<LoadSDNode>(St->getValue());
25278 Ops.push_back(ChainVal->getOperand(i));
25282 if (!Ld || !ISD::isNormalLoad(Ld))
25285 // If this is not the MMX case, i.e. we are just turning i64 load/store
25286 // into f64 load/store, avoid the transformation if there are multiple
25287 // uses of the loaded value.
25288 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25293 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25294 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25296 if (Subtarget->is64Bit() || F64IsLegal) {
25297 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25298 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25299 Ld->getPointerInfo(), Ld->isVolatile(),
25300 Ld->isNonTemporal(), Ld->isInvariant(),
25301 Ld->getAlignment());
25302 SDValue NewChain = NewLd.getValue(1);
25303 if (TokenFactorIndex != -1) {
25304 Ops.push_back(NewChain);
25305 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25307 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25308 St->getPointerInfo(),
25309 St->isVolatile(), St->isNonTemporal(),
25310 St->getAlignment());
25313 // Otherwise, lower to two pairs of 32-bit loads / stores.
25314 SDValue LoAddr = Ld->getBasePtr();
25315 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25316 DAG.getConstant(4, LdDL, MVT::i32));
25318 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25319 Ld->getPointerInfo(),
25320 Ld->isVolatile(), Ld->isNonTemporal(),
25321 Ld->isInvariant(), Ld->getAlignment());
25322 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25323 Ld->getPointerInfo().getWithOffset(4),
25324 Ld->isVolatile(), Ld->isNonTemporal(),
25326 MinAlign(Ld->getAlignment(), 4));
25328 SDValue NewChain = LoLd.getValue(1);
25329 if (TokenFactorIndex != -1) {
25330 Ops.push_back(LoLd);
25331 Ops.push_back(HiLd);
25332 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25335 LoAddr = St->getBasePtr();
25336 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25337 DAG.getConstant(4, StDL, MVT::i32));
25339 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25340 St->getPointerInfo(),
25341 St->isVolatile(), St->isNonTemporal(),
25342 St->getAlignment());
25343 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25344 St->getPointerInfo().getWithOffset(4),
25346 St->isNonTemporal(),
25347 MinAlign(St->getAlignment(), 4));
25348 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25351 // This is similar to the above case, but here we handle a scalar 64-bit
25352 // integer store that is extracted from a vector on a 32-bit target.
25353 // If we have SSE2, then we can treat it like a floating-point double
25354 // to get past legalization. The execution dependencies fixup pass will
25355 // choose the optimal machine instruction for the store if this really is
25356 // an integer or v2f32 rather than an f64.
25357 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25358 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25359 SDValue OldExtract = St->getOperand(1);
25360 SDValue ExtOp0 = OldExtract.getOperand(0);
25361 unsigned VecSize = ExtOp0.getValueSizeInBits();
25362 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25363 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25364 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25365 BitCast, OldExtract.getOperand(1));
25366 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25367 St->getPointerInfo(), St->isVolatile(),
25368 St->isNonTemporal(), St->getAlignment());
25374 /// Return 'true' if this vector operation is "horizontal"
25375 /// and return the operands for the horizontal operation in LHS and RHS. A
25376 /// horizontal operation performs the binary operation on successive elements
25377 /// of its first operand, then on successive elements of its second operand,
25378 /// returning the resulting values in a vector. For example, if
25379 /// A = < float a0, float a1, float a2, float a3 >
25381 /// B = < float b0, float b1, float b2, float b3 >
25382 /// then the result of doing a horizontal operation on A and B is
25383 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25384 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25385 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25386 /// set to A, RHS to B, and the routine returns 'true'.
25387 /// Note that the binary operation should have the property that if one of the
25388 /// operands is UNDEF then the result is UNDEF.
25389 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25390 // Look for the following pattern: if
25391 // A = < float a0, float a1, float a2, float a3 >
25392 // B = < float b0, float b1, float b2, float b3 >
25394 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25395 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25396 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25397 // which is A horizontal-op B.
25399 // At least one of the operands should be a vector shuffle.
25400 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25401 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25404 MVT VT = LHS.getSimpleValueType();
25406 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25407 "Unsupported vector type for horizontal add/sub");
25409 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25410 // operate independently on 128-bit lanes.
25411 unsigned NumElts = VT.getVectorNumElements();
25412 unsigned NumLanes = VT.getSizeInBits()/128;
25413 unsigned NumLaneElts = NumElts / NumLanes;
25414 assert((NumLaneElts % 2 == 0) &&
25415 "Vector type should have an even number of elements in each lane");
25416 unsigned HalfLaneElts = NumLaneElts/2;
25418 // View LHS in the form
25419 // LHS = VECTOR_SHUFFLE A, B, LMask
25420 // If LHS is not a shuffle then pretend it is the shuffle
25421 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25422 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25425 SmallVector<int, 16> LMask(NumElts);
25426 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25427 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25428 A = LHS.getOperand(0);
25429 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25430 B = LHS.getOperand(1);
25431 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25432 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25434 if (LHS.getOpcode() != ISD::UNDEF)
25436 for (unsigned i = 0; i != NumElts; ++i)
25440 // Likewise, view RHS in the form
25441 // RHS = VECTOR_SHUFFLE C, D, RMask
25443 SmallVector<int, 16> RMask(NumElts);
25444 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25445 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25446 C = RHS.getOperand(0);
25447 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25448 D = RHS.getOperand(1);
25449 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25450 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25452 if (RHS.getOpcode() != ISD::UNDEF)
25454 for (unsigned i = 0; i != NumElts; ++i)
25458 // Check that the shuffles are both shuffling the same vectors.
25459 if (!(A == C && B == D) && !(A == D && B == C))
25462 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25463 if (!A.getNode() && !B.getNode())
25466 // If A and B occur in reverse order in RHS, then "swap" them (which means
25467 // rewriting the mask).
25469 ShuffleVectorSDNode::commuteMask(RMask);
25471 // At this point LHS and RHS are equivalent to
25472 // LHS = VECTOR_SHUFFLE A, B, LMask
25473 // RHS = VECTOR_SHUFFLE A, B, RMask
25474 // Check that the masks correspond to performing a horizontal operation.
25475 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25476 for (unsigned i = 0; i != NumLaneElts; ++i) {
25477 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25479 // Ignore any UNDEF components.
25480 if (LIdx < 0 || RIdx < 0 ||
25481 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25482 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25485 // Check that successive elements are being operated on. If not, this is
25486 // not a horizontal operation.
25487 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25488 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25489 if (!(LIdx == Index && RIdx == Index + 1) &&
25490 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25495 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25496 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25500 /// Do target-specific dag combines on floating point adds.
25501 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25502 const X86Subtarget *Subtarget) {
25503 EVT VT = N->getValueType(0);
25504 SDValue LHS = N->getOperand(0);
25505 SDValue RHS = N->getOperand(1);
25507 // Try to synthesize horizontal adds from adds of shuffles.
25508 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25509 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25510 isHorizontalBinOp(LHS, RHS, true))
25511 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25515 /// Do target-specific dag combines on floating point subs.
25516 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25517 const X86Subtarget *Subtarget) {
25518 EVT VT = N->getValueType(0);
25519 SDValue LHS = N->getOperand(0);
25520 SDValue RHS = N->getOperand(1);
25522 // Try to synthesize horizontal subs from subs of shuffles.
25523 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25524 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25525 isHorizontalBinOp(LHS, RHS, false))
25526 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25530 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25531 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25532 const X86Subtarget *Subtarget) {
25533 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25535 // F[X]OR(0.0, x) -> x
25536 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25537 if (C->getValueAPF().isPosZero())
25538 return N->getOperand(1);
25540 // F[X]OR(x, 0.0) -> x
25541 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25542 if (C->getValueAPF().isPosZero())
25543 return N->getOperand(0);
25545 EVT VT = N->getValueType(0);
25546 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25548 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25549 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25551 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25552 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25553 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25554 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25555 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25560 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25561 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25562 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25564 // Only perform optimizations if UnsafeMath is used.
25565 if (!DAG.getTarget().Options.UnsafeFPMath)
25568 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25569 // into FMINC and FMAXC, which are Commutative operations.
25570 unsigned NewOp = 0;
25571 switch (N->getOpcode()) {
25572 default: llvm_unreachable("unknown opcode");
25573 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25574 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25577 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25578 N->getOperand(0), N->getOperand(1));
25581 /// Do target-specific dag combines on X86ISD::FAND nodes.
25582 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25583 // FAND(0.0, x) -> 0.0
25584 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25585 if (C->getValueAPF().isPosZero())
25586 return N->getOperand(0);
25588 // FAND(x, 0.0) -> 0.0
25589 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25590 if (C->getValueAPF().isPosZero())
25591 return N->getOperand(1);
25596 /// Do target-specific dag combines on X86ISD::FANDN nodes
25597 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25598 // FANDN(0.0, x) -> x
25599 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25600 if (C->getValueAPF().isPosZero())
25601 return N->getOperand(1);
25603 // FANDN(x, 0.0) -> 0.0
25604 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25605 if (C->getValueAPF().isPosZero())
25606 return N->getOperand(1);
25611 static SDValue PerformBTCombine(SDNode *N,
25613 TargetLowering::DAGCombinerInfo &DCI) {
25614 // BT ignores high bits in the bit index operand.
25615 SDValue Op1 = N->getOperand(1);
25616 if (Op1.hasOneUse()) {
25617 unsigned BitWidth = Op1.getValueSizeInBits();
25618 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25619 APInt KnownZero, KnownOne;
25620 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25621 !DCI.isBeforeLegalizeOps());
25622 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25623 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25624 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25625 DCI.CommitTargetLoweringOpt(TLO);
25630 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25631 SDValue Op = N->getOperand(0);
25632 if (Op.getOpcode() == ISD::BITCAST)
25633 Op = Op.getOperand(0);
25634 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25635 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25636 VT.getVectorElementType().getSizeInBits() ==
25637 OpVT.getVectorElementType().getSizeInBits()) {
25638 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25643 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25644 const X86Subtarget *Subtarget) {
25645 EVT VT = N->getValueType(0);
25646 if (!VT.isVector())
25649 SDValue N0 = N->getOperand(0);
25650 SDValue N1 = N->getOperand(1);
25651 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25654 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25655 // both SSE and AVX2 since there is no sign-extended shift right
25656 // operation on a vector with 64-bit elements.
25657 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25658 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25659 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25660 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25661 SDValue N00 = N0.getOperand(0);
25663 // EXTLOAD has a better solution on AVX2,
25664 // it may be replaced with X86ISD::VSEXT node.
25665 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25666 if (!ISD::isNormalLoad(N00.getNode()))
25669 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25670 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25672 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25678 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25679 TargetLowering::DAGCombinerInfo &DCI,
25680 const X86Subtarget *Subtarget) {
25681 SDValue N0 = N->getOperand(0);
25682 EVT VT = N->getValueType(0);
25683 EVT SVT = VT.getScalarType();
25684 EVT InVT = N0.getValueType();
25685 EVT InSVT = InVT.getScalarType();
25688 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25689 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25690 // This exposes the sext to the sdivrem lowering, so that it directly extends
25691 // from AH (which we otherwise need to do contortions to access).
25692 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25693 InVT == MVT::i8 && VT == MVT::i32) {
25694 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25695 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25696 N0.getOperand(0), N0.getOperand(1));
25697 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25698 return R.getValue(1);
25701 if (!DCI.isBeforeLegalizeOps()) {
25702 if (InVT == MVT::i1) {
25703 SDValue Zero = DAG.getConstant(0, DL, VT);
25705 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25706 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25711 if (VT.isVector() && Subtarget->hasSSE2()) {
25712 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25713 EVT InVT = N.getValueType();
25714 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25715 Size / InVT.getScalarSizeInBits());
25716 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25717 DAG.getUNDEF(InVT));
25719 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25722 // If target-size is less than 128-bits, extend to a type that would extend
25723 // to 128 bits, extend that and extract the original target vector.
25724 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25725 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25726 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25727 unsigned Scale = 128 / VT.getSizeInBits();
25729 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25730 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25731 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25732 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25733 DAG.getIntPtrConstant(0, DL));
25736 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25737 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25738 if (VT.getSizeInBits() == 128 &&
25739 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25740 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25741 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25742 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25745 // On pre-AVX2 targets, split into 128-bit nodes of
25746 // ISD::SIGN_EXTEND_VECTOR_INREG.
25747 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25748 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25749 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25750 unsigned NumVecs = VT.getSizeInBits() / 128;
25751 unsigned NumSubElts = 128 / SVT.getSizeInBits();
25752 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
25753 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
25755 SmallVector<SDValue, 8> Opnds;
25756 for (unsigned i = 0, Offset = 0; i != NumVecs;
25757 ++i, Offset += NumSubElts) {
25758 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
25759 DAG.getIntPtrConstant(Offset, DL));
25760 SrcVec = ExtendVecSize(DL, SrcVec, 128);
25761 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
25762 Opnds.push_back(SrcVec);
25764 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
25768 if (Subtarget->hasAVX() && VT.isVector() && VT.getSizeInBits() == 256)
25769 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25775 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
25776 const X86Subtarget* Subtarget) {
25778 EVT VT = N->getValueType(0);
25780 // Let legalize expand this if it isn't a legal type yet.
25781 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
25784 EVT ScalarVT = VT.getScalarType();
25785 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
25786 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
25787 !Subtarget->hasAVX512()))
25790 SDValue A = N->getOperand(0);
25791 SDValue B = N->getOperand(1);
25792 SDValue C = N->getOperand(2);
25794 bool NegA = (A.getOpcode() == ISD::FNEG);
25795 bool NegB = (B.getOpcode() == ISD::FNEG);
25796 bool NegC = (C.getOpcode() == ISD::FNEG);
25798 // Negative multiplication when NegA xor NegB
25799 bool NegMul = (NegA != NegB);
25801 A = A.getOperand(0);
25803 B = B.getOperand(0);
25805 C = C.getOperand(0);
25809 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25811 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25813 return DAG.getNode(Opcode, dl, VT, A, B, C);
25816 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25817 TargetLowering::DAGCombinerInfo &DCI,
25818 const X86Subtarget *Subtarget) {
25819 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25820 // (and (i32 x86isd::setcc_carry), 1)
25821 // This eliminates the zext. This transformation is necessary because
25822 // ISD::SETCC is always legalized to i8.
25824 SDValue N0 = N->getOperand(0);
25825 EVT VT = N->getValueType(0);
25827 if (N0.getOpcode() == ISD::AND &&
25829 N0.getOperand(0).hasOneUse()) {
25830 SDValue N00 = N0.getOperand(0);
25831 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25832 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25833 if (!C || C->getZExtValue() != 1)
25835 return DAG.getNode(ISD::AND, dl, VT,
25836 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25837 N00.getOperand(0), N00.getOperand(1)),
25838 DAG.getConstant(1, dl, VT));
25842 if (N0.getOpcode() == ISD::TRUNCATE &&
25844 N0.getOperand(0).hasOneUse()) {
25845 SDValue N00 = N0.getOperand(0);
25846 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25847 return DAG.getNode(ISD::AND, dl, VT,
25848 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25849 N00.getOperand(0), N00.getOperand(1)),
25850 DAG.getConstant(1, dl, VT));
25854 if (VT.is256BitVector())
25855 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
25858 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25859 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25860 // This exposes the zext to the udivrem lowering, so that it directly extends
25861 // from AH (which we otherwise need to do contortions to access).
25862 if (N0.getOpcode() == ISD::UDIVREM &&
25863 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25864 (VT == MVT::i32 || VT == MVT::i64)) {
25865 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25866 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25867 N0.getOperand(0), N0.getOperand(1));
25868 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25869 return R.getValue(1);
25875 // Optimize x == -y --> x+y == 0
25876 // x != -y --> x+y != 0
25877 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25878 const X86Subtarget* Subtarget) {
25879 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25880 SDValue LHS = N->getOperand(0);
25881 SDValue RHS = N->getOperand(1);
25882 EVT VT = N->getValueType(0);
25885 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25886 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25887 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25888 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
25889 LHS.getOperand(1));
25890 return DAG.getSetCC(DL, N->getValueType(0), addV,
25891 DAG.getConstant(0, DL, addV.getValueType()), CC);
25893 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25894 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25895 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25896 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
25897 RHS.getOperand(1));
25898 return DAG.getSetCC(DL, N->getValueType(0), addV,
25899 DAG.getConstant(0, DL, addV.getValueType()), CC);
25902 if (VT.getScalarType() == MVT::i1 &&
25903 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
25905 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25906 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25907 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25909 if (!IsSEXT0 || !IsVZero1) {
25910 // Swap the operands and update the condition code.
25911 std::swap(LHS, RHS);
25912 CC = ISD::getSetCCSwappedOperands(CC);
25914 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25915 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25916 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25919 if (IsSEXT0 && IsVZero1) {
25920 assert(VT == LHS.getOperand(0).getValueType() &&
25921 "Uexpected operand type");
25922 if (CC == ISD::SETGT)
25923 return DAG.getConstant(0, DL, VT);
25924 if (CC == ISD::SETLE)
25925 return DAG.getConstant(1, DL, VT);
25926 if (CC == ISD::SETEQ || CC == ISD::SETGE)
25927 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25929 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
25930 "Unexpected condition code!");
25931 return LHS.getOperand(0);
25938 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
25939 SelectionDAG &DAG) {
25941 MVT VT = Load->getSimpleValueType(0);
25942 MVT EVT = VT.getVectorElementType();
25943 SDValue Addr = Load->getOperand(1);
25944 SDValue NewAddr = DAG.getNode(
25945 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
25946 DAG.getConstant(Index * EVT.getStoreSize(), dl,
25947 Addr.getSimpleValueType()));
25950 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
25951 DAG.getMachineFunction().getMachineMemOperand(
25952 Load->getMemOperand(), 0, EVT.getStoreSize()));
25956 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25957 const X86Subtarget *Subtarget) {
25959 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25960 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25961 "X86insertps is only defined for v4x32");
25963 SDValue Ld = N->getOperand(1);
25964 if (MayFoldLoad(Ld)) {
25965 // Extract the countS bits from the immediate so we can get the proper
25966 // address when narrowing the vector load to a specific element.
25967 // When the second source op is a memory address, insertps doesn't use
25968 // countS and just gets an f32 from that address.
25969 unsigned DestIndex =
25970 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25972 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25974 // Create this as a scalar to vector to match the instruction pattern.
25975 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25976 // countS bits are ignored when loading from memory on insertps, which
25977 // means we don't need to explicitly set them to 0.
25978 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25979 LoadScalarToVector, N->getOperand(2));
25984 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
25985 SDValue V0 = N->getOperand(0);
25986 SDValue V1 = N->getOperand(1);
25988 EVT VT = N->getValueType(0);
25990 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
25991 // operands and changing the mask to 1. This saves us a bunch of
25992 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
25993 // x86InstrInfo knows how to commute this back after instruction selection
25994 // if it would help register allocation.
25996 // TODO: If optimizing for size or a processor that doesn't suffer from
25997 // partial register update stalls, this should be transformed into a MOVSD
25998 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26000 if (VT == MVT::v2f64)
26001 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26002 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26003 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26004 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26010 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26011 // as "sbb reg,reg", since it can be extended without zext and produces
26012 // an all-ones bit which is more useful than 0/1 in some cases.
26013 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26016 return DAG.getNode(ISD::AND, DL, VT,
26017 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26018 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26020 DAG.getConstant(1, DL, VT));
26021 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26022 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26023 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26024 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26028 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26029 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26030 TargetLowering::DAGCombinerInfo &DCI,
26031 const X86Subtarget *Subtarget) {
26033 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26034 SDValue EFLAGS = N->getOperand(1);
26036 if (CC == X86::COND_A) {
26037 // Try to convert COND_A into COND_B in an attempt to facilitate
26038 // materializing "setb reg".
26040 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26041 // cannot take an immediate as its first operand.
26043 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26044 EFLAGS.getValueType().isInteger() &&
26045 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26046 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26047 EFLAGS.getNode()->getVTList(),
26048 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26049 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26050 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26054 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26055 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26057 if (CC == X86::COND_B)
26058 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26060 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26061 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26062 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26068 // Optimize branch condition evaluation.
26070 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26071 TargetLowering::DAGCombinerInfo &DCI,
26072 const X86Subtarget *Subtarget) {
26074 SDValue Chain = N->getOperand(0);
26075 SDValue Dest = N->getOperand(1);
26076 SDValue EFLAGS = N->getOperand(3);
26077 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26079 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26080 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26081 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26088 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26089 SelectionDAG &DAG) {
26090 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26091 // optimize away operation when it's from a constant.
26093 // The general transformation is:
26094 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26095 // AND(VECTOR_CMP(x,y), constant2)
26096 // constant2 = UNARYOP(constant)
26098 // Early exit if this isn't a vector operation, the operand of the
26099 // unary operation isn't a bitwise AND, or if the sizes of the operations
26100 // aren't the same.
26101 EVT VT = N->getValueType(0);
26102 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26103 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26104 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26107 // Now check that the other operand of the AND is a constant. We could
26108 // make the transformation for non-constant splats as well, but it's unclear
26109 // that would be a benefit as it would not eliminate any operations, just
26110 // perform one more step in scalar code before moving to the vector unit.
26111 if (BuildVectorSDNode *BV =
26112 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26113 // Bail out if the vector isn't a constant.
26114 if (!BV->isConstant())
26117 // Everything checks out. Build up the new and improved node.
26119 EVT IntVT = BV->getValueType(0);
26120 // Create a new constant of the appropriate type for the transformed
26122 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26123 // The AND node needs bitcasts to/from an integer vector type around it.
26124 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26125 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26126 N->getOperand(0)->getOperand(0), MaskConst);
26127 SDValue Res = DAG.getBitcast(VT, NewAnd);
26134 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26135 const X86Subtarget *Subtarget) {
26136 SDValue Op0 = N->getOperand(0);
26137 EVT VT = N->getValueType(0);
26138 EVT InVT = Op0.getValueType();
26139 EVT InSVT = InVT.getScalarType();
26140 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26142 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26143 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26144 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26146 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26147 InVT.getVectorNumElements());
26148 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26150 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26151 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26153 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26159 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26160 const X86Subtarget *Subtarget) {
26161 // First try to optimize away the conversion entirely when it's
26162 // conditionally from a constant. Vectors only.
26163 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26166 // Now move on to more general possibilities.
26167 SDValue Op0 = N->getOperand(0);
26168 EVT VT = N->getValueType(0);
26169 EVT InVT = Op0.getValueType();
26170 EVT InSVT = InVT.getScalarType();
26172 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26173 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26174 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26176 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26177 InVT.getVectorNumElements());
26178 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26179 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26182 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26183 // a 32-bit target where SSE doesn't support i64->FP operations.
26184 if (Op0.getOpcode() == ISD::LOAD) {
26185 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26186 EVT LdVT = Ld->getValueType(0);
26188 // This transformation is not supported if the result type is f16
26189 if (VT == MVT::f16)
26192 if (!Ld->isVolatile() && !VT.isVector() &&
26193 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26194 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26195 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26196 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26197 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26204 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26205 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26206 X86TargetLowering::DAGCombinerInfo &DCI) {
26207 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26208 // the result is either zero or one (depending on the input carry bit).
26209 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26210 if (X86::isZeroNode(N->getOperand(0)) &&
26211 X86::isZeroNode(N->getOperand(1)) &&
26212 // We don't have a good way to replace an EFLAGS use, so only do this when
26214 SDValue(N, 1).use_empty()) {
26216 EVT VT = N->getValueType(0);
26217 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26218 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26219 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26220 DAG.getConstant(X86::COND_B, DL,
26223 DAG.getConstant(1, DL, VT));
26224 return DCI.CombineTo(N, Res1, CarryOut);
26230 // fold (add Y, (sete X, 0)) -> adc 0, Y
26231 // (add Y, (setne X, 0)) -> sbb -1, Y
26232 // (sub (sete X, 0), Y) -> sbb 0, Y
26233 // (sub (setne X, 0), Y) -> adc -1, Y
26234 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26237 // Look through ZExts.
26238 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26239 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26242 SDValue SetCC = Ext.getOperand(0);
26243 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26246 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26247 if (CC != X86::COND_E && CC != X86::COND_NE)
26250 SDValue Cmp = SetCC.getOperand(1);
26251 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26252 !X86::isZeroNode(Cmp.getOperand(1)) ||
26253 !Cmp.getOperand(0).getValueType().isInteger())
26256 SDValue CmpOp0 = Cmp.getOperand(0);
26257 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26258 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26260 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26261 if (CC == X86::COND_NE)
26262 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26263 DL, OtherVal.getValueType(), OtherVal,
26264 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26266 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26267 DL, OtherVal.getValueType(), OtherVal,
26268 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26271 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26272 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26273 const X86Subtarget *Subtarget) {
26274 EVT VT = N->getValueType(0);
26275 SDValue Op0 = N->getOperand(0);
26276 SDValue Op1 = N->getOperand(1);
26278 // Try to synthesize horizontal adds from adds of shuffles.
26279 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26280 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26281 isHorizontalBinOp(Op0, Op1, true))
26282 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26284 return OptimizeConditionalInDecrement(N, DAG);
26287 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26288 const X86Subtarget *Subtarget) {
26289 SDValue Op0 = N->getOperand(0);
26290 SDValue Op1 = N->getOperand(1);
26292 // X86 can't encode an immediate LHS of a sub. See if we can push the
26293 // negation into a preceding instruction.
26294 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26295 // If the RHS of the sub is a XOR with one use and a constant, invert the
26296 // immediate. Then add one to the LHS of the sub so we can turn
26297 // X-Y -> X+~Y+1, saving one register.
26298 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26299 isa<ConstantSDNode>(Op1.getOperand(1))) {
26300 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26301 EVT VT = Op0.getValueType();
26302 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26304 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26305 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26306 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26310 // Try to synthesize horizontal adds from adds of shuffles.
26311 EVT VT = N->getValueType(0);
26312 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26313 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26314 isHorizontalBinOp(Op0, Op1, true))
26315 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26317 return OptimizeConditionalInDecrement(N, DAG);
26320 /// performVZEXTCombine - Performs build vector combines
26321 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26322 TargetLowering::DAGCombinerInfo &DCI,
26323 const X86Subtarget *Subtarget) {
26325 MVT VT = N->getSimpleValueType(0);
26326 SDValue Op = N->getOperand(0);
26327 MVT OpVT = Op.getSimpleValueType();
26328 MVT OpEltVT = OpVT.getVectorElementType();
26329 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26331 // (vzext (bitcast (vzext (x)) -> (vzext x)
26333 while (V.getOpcode() == ISD::BITCAST)
26334 V = V.getOperand(0);
26336 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26337 MVT InnerVT = V.getSimpleValueType();
26338 MVT InnerEltVT = InnerVT.getVectorElementType();
26340 // If the element sizes match exactly, we can just do one larger vzext. This
26341 // is always an exact type match as vzext operates on integer types.
26342 if (OpEltVT == InnerEltVT) {
26343 assert(OpVT == InnerVT && "Types must match for vzext!");
26344 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26347 // The only other way we can combine them is if only a single element of the
26348 // inner vzext is used in the input to the outer vzext.
26349 if (InnerEltVT.getSizeInBits() < InputBits)
26352 // In this case, the inner vzext is completely dead because we're going to
26353 // only look at bits inside of the low element. Just do the outer vzext on
26354 // a bitcast of the input to the inner.
26355 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26358 // Check if we can bypass extracting and re-inserting an element of an input
26359 // vector. Essentially:
26360 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26361 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26362 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26363 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26364 SDValue ExtractedV = V.getOperand(0);
26365 SDValue OrigV = ExtractedV.getOperand(0);
26366 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26367 if (ExtractIdx->getZExtValue() == 0) {
26368 MVT OrigVT = OrigV.getSimpleValueType();
26369 // Extract a subvector if necessary...
26370 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26371 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26372 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26373 OrigVT.getVectorNumElements() / Ratio);
26374 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26375 DAG.getIntPtrConstant(0, DL));
26377 Op = DAG.getBitcast(OpVT, OrigV);
26378 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26385 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26386 DAGCombinerInfo &DCI) const {
26387 SelectionDAG &DAG = DCI.DAG;
26388 switch (N->getOpcode()) {
26390 case ISD::EXTRACT_VECTOR_ELT:
26391 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26394 case X86ISD::SHRUNKBLEND:
26395 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26396 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
26397 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26398 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26399 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26400 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26401 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26404 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26405 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26406 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26407 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26408 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26409 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26410 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26411 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26412 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26413 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26414 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26415 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26417 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26419 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26420 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26421 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26422 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26423 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26424 case ISD::ANY_EXTEND:
26425 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26426 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26427 case ISD::SIGN_EXTEND_INREG:
26428 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26429 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26430 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26431 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26432 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26433 case X86ISD::SHUFP: // Handle all target specific shuffles
26434 case X86ISD::PALIGNR:
26435 case X86ISD::UNPCKH:
26436 case X86ISD::UNPCKL:
26437 case X86ISD::MOVHLPS:
26438 case X86ISD::MOVLHPS:
26439 case X86ISD::PSHUFB:
26440 case X86ISD::PSHUFD:
26441 case X86ISD::PSHUFHW:
26442 case X86ISD::PSHUFLW:
26443 case X86ISD::MOVSS:
26444 case X86ISD::MOVSD:
26445 case X86ISD::VPERMILPI:
26446 case X86ISD::VPERM2X128:
26447 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26448 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26449 case X86ISD::INSERTPS: {
26450 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26451 return PerformINSERTPSCombine(N, DAG, Subtarget);
26454 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26460 /// isTypeDesirableForOp - Return true if the target has native support for
26461 /// the specified value type and it is 'desirable' to use the type for the
26462 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26463 /// instruction encodings are longer and some i16 instructions are slow.
26464 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26465 if (!isTypeLegal(VT))
26467 if (VT != MVT::i16)
26474 case ISD::SIGN_EXTEND:
26475 case ISD::ZERO_EXTEND:
26476 case ISD::ANY_EXTEND:
26489 /// IsDesirableToPromoteOp - This method query the target whether it is
26490 /// beneficial for dag combiner to promote the specified node. If true, it
26491 /// should return the desired promotion type by reference.
26492 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26493 EVT VT = Op.getValueType();
26494 if (VT != MVT::i16)
26497 bool Promote = false;
26498 bool Commute = false;
26499 switch (Op.getOpcode()) {
26502 LoadSDNode *LD = cast<LoadSDNode>(Op);
26503 // If the non-extending load has a single use and it's not live out, then it
26504 // might be folded.
26505 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26506 Op.hasOneUse()*/) {
26507 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26508 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26509 // The only case where we'd want to promote LOAD (rather then it being
26510 // promoted as an operand is when it's only use is liveout.
26511 if (UI->getOpcode() != ISD::CopyToReg)
26518 case ISD::SIGN_EXTEND:
26519 case ISD::ZERO_EXTEND:
26520 case ISD::ANY_EXTEND:
26525 SDValue N0 = Op.getOperand(0);
26526 // Look out for (store (shl (load), x)).
26527 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26540 SDValue N0 = Op.getOperand(0);
26541 SDValue N1 = Op.getOperand(1);
26542 if (!Commute && MayFoldLoad(N1))
26544 // Avoid disabling potential load folding opportunities.
26545 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26547 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26557 //===----------------------------------------------------------------------===//
26558 // X86 Inline Assembly Support
26559 //===----------------------------------------------------------------------===//
26561 // Helper to match a string separated by whitespace.
26562 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26563 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26565 for (StringRef Piece : Pieces) {
26566 if (!S.startswith(Piece)) // Check if the piece matches.
26569 S = S.substr(Piece.size());
26570 StringRef::size_type Pos = S.find_first_not_of(" \t");
26571 if (Pos == 0) // We matched a prefix.
26580 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26582 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26583 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26584 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26585 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26587 if (AsmPieces.size() == 3)
26589 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26596 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26597 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26599 std::string AsmStr = IA->getAsmString();
26601 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26602 if (!Ty || Ty->getBitWidth() % 16 != 0)
26605 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26606 SmallVector<StringRef, 4> AsmPieces;
26607 SplitString(AsmStr, AsmPieces, ";\n");
26609 switch (AsmPieces.size()) {
26610 default: return false;
26612 // FIXME: this should verify that we are targeting a 486 or better. If not,
26613 // we will turn this bswap into something that will be lowered to logical
26614 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26615 // lower so don't worry about this.
26617 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26618 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26619 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26620 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26621 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26622 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26623 // No need to check constraints, nothing other than the equivalent of
26624 // "=r,0" would be valid here.
26625 return IntrinsicLowering::LowerToByteSwap(CI);
26628 // rorw $$8, ${0:w} --> llvm.bswap.i16
26629 if (CI->getType()->isIntegerTy(16) &&
26630 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26631 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26632 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26634 StringRef ConstraintsStr = IA->getConstraintString();
26635 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26636 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26637 if (clobbersFlagRegisters(AsmPieces))
26638 return IntrinsicLowering::LowerToByteSwap(CI);
26642 if (CI->getType()->isIntegerTy(32) &&
26643 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26644 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26645 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26646 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26648 StringRef ConstraintsStr = IA->getConstraintString();
26649 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26650 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26651 if (clobbersFlagRegisters(AsmPieces))
26652 return IntrinsicLowering::LowerToByteSwap(CI);
26655 if (CI->getType()->isIntegerTy(64)) {
26656 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26657 if (Constraints.size() >= 2 &&
26658 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26659 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26660 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26661 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26662 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26663 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26664 return IntrinsicLowering::LowerToByteSwap(CI);
26672 /// getConstraintType - Given a constraint letter, return the type of
26673 /// constraint it is for this target.
26674 X86TargetLowering::ConstraintType
26675 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26676 if (Constraint.size() == 1) {
26677 switch (Constraint[0]) {
26688 return C_RegisterClass;
26712 return TargetLowering::getConstraintType(Constraint);
26715 /// Examine constraint type and operand type and determine a weight value.
26716 /// This object must already have been set up with the operand type
26717 /// and the current alternative constraint selected.
26718 TargetLowering::ConstraintWeight
26719 X86TargetLowering::getSingleConstraintMatchWeight(
26720 AsmOperandInfo &info, const char *constraint) const {
26721 ConstraintWeight weight = CW_Invalid;
26722 Value *CallOperandVal = info.CallOperandVal;
26723 // If we don't have a value, we can't do a match,
26724 // but allow it at the lowest weight.
26725 if (!CallOperandVal)
26727 Type *type = CallOperandVal->getType();
26728 // Look at the constraint type.
26729 switch (*constraint) {
26731 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26742 if (CallOperandVal->getType()->isIntegerTy())
26743 weight = CW_SpecificReg;
26748 if (type->isFloatingPointTy())
26749 weight = CW_SpecificReg;
26752 if (type->isX86_MMXTy() && Subtarget->hasMMX())
26753 weight = CW_SpecificReg;
26757 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
26758 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
26759 weight = CW_Register;
26762 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
26763 if (C->getZExtValue() <= 31)
26764 weight = CW_Constant;
26768 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26769 if (C->getZExtValue() <= 63)
26770 weight = CW_Constant;
26774 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26775 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
26776 weight = CW_Constant;
26780 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26781 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
26782 weight = CW_Constant;
26786 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26787 if (C->getZExtValue() <= 3)
26788 weight = CW_Constant;
26792 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26793 if (C->getZExtValue() <= 0xff)
26794 weight = CW_Constant;
26799 if (isa<ConstantFP>(CallOperandVal)) {
26800 weight = CW_Constant;
26804 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26805 if ((C->getSExtValue() >= -0x80000000LL) &&
26806 (C->getSExtValue() <= 0x7fffffffLL))
26807 weight = CW_Constant;
26811 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
26812 if (C->getZExtValue() <= 0xffffffff)
26813 weight = CW_Constant;
26820 /// LowerXConstraint - try to replace an X constraint, which matches anything,
26821 /// with another that has more specific requirements based on the type of the
26822 /// corresponding operand.
26823 const char *X86TargetLowering::
26824 LowerXConstraint(EVT ConstraintVT) const {
26825 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
26826 // 'f' like normal targets.
26827 if (ConstraintVT.isFloatingPoint()) {
26828 if (Subtarget->hasSSE2())
26830 if (Subtarget->hasSSE1())
26834 return TargetLowering::LowerXConstraint(ConstraintVT);
26837 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
26838 /// vector. If it is invalid, don't add anything to Ops.
26839 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
26840 std::string &Constraint,
26841 std::vector<SDValue>&Ops,
26842 SelectionDAG &DAG) const {
26845 // Only support length 1 constraints for now.
26846 if (Constraint.length() > 1) return;
26848 char ConstraintLetter = Constraint[0];
26849 switch (ConstraintLetter) {
26852 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26853 if (C->getZExtValue() <= 31) {
26854 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26855 Op.getValueType());
26861 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26862 if (C->getZExtValue() <= 63) {
26863 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26864 Op.getValueType());
26870 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26871 if (isInt<8>(C->getSExtValue())) {
26872 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26873 Op.getValueType());
26879 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26880 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
26881 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
26882 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
26883 Op.getValueType());
26889 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26890 if (C->getZExtValue() <= 3) {
26891 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26892 Op.getValueType());
26898 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26899 if (C->getZExtValue() <= 255) {
26900 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26901 Op.getValueType());
26907 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26908 if (C->getZExtValue() <= 127) {
26909 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26910 Op.getValueType());
26916 // 32-bit signed value
26917 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26918 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26919 C->getSExtValue())) {
26920 // Widen to 64 bits here to get it sign extended.
26921 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
26924 // FIXME gcc accepts some relocatable values here too, but only in certain
26925 // memory models; it's complicated.
26930 // 32-bit unsigned value
26931 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26932 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26933 C->getZExtValue())) {
26934 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
26935 Op.getValueType());
26939 // FIXME gcc accepts some relocatable values here too, but only in certain
26940 // memory models; it's complicated.
26944 // Literal immediates are always ok.
26945 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26946 // Widen to 64 bits here to get it sign extended.
26947 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
26951 // In any sort of PIC mode addresses need to be computed at runtime by
26952 // adding in a register or some sort of table lookup. These can't
26953 // be used as immediates.
26954 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26957 // If we are in non-pic codegen mode, we allow the address of a global (with
26958 // an optional displacement) to be used with 'i'.
26959 GlobalAddressSDNode *GA = nullptr;
26960 int64_t Offset = 0;
26962 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26964 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26965 Offset += GA->getOffset();
26967 } else if (Op.getOpcode() == ISD::ADD) {
26968 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26969 Offset += C->getZExtValue();
26970 Op = Op.getOperand(0);
26973 } else if (Op.getOpcode() == ISD::SUB) {
26974 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26975 Offset += -C->getZExtValue();
26976 Op = Op.getOperand(0);
26981 // Otherwise, this isn't something we can handle, reject it.
26985 const GlobalValue *GV = GA->getGlobal();
26986 // If we require an extra load to get this address, as in PIC mode, we
26987 // can't accept it.
26988 if (isGlobalStubReference(
26989 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26992 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26993 GA->getValueType(0), Offset);
26998 if (Result.getNode()) {
26999 Ops.push_back(Result);
27002 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27005 std::pair<unsigned, const TargetRegisterClass *>
27006 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27007 StringRef Constraint,
27009 // First, see if this is a constraint that directly corresponds to an LLVM
27011 if (Constraint.size() == 1) {
27012 // GCC Constraint Letters
27013 switch (Constraint[0]) {
27015 // TODO: Slight differences here in allocation order and leaving
27016 // RIP in the class. Do they matter any more here than they do
27017 // in the normal allocation?
27018 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27019 if (Subtarget->is64Bit()) {
27020 if (VT == MVT::i32 || VT == MVT::f32)
27021 return std::make_pair(0U, &X86::GR32RegClass);
27022 if (VT == MVT::i16)
27023 return std::make_pair(0U, &X86::GR16RegClass);
27024 if (VT == MVT::i8 || VT == MVT::i1)
27025 return std::make_pair(0U, &X86::GR8RegClass);
27026 if (VT == MVT::i64 || VT == MVT::f64)
27027 return std::make_pair(0U, &X86::GR64RegClass);
27030 // 32-bit fallthrough
27031 case 'Q': // Q_REGS
27032 if (VT == MVT::i32 || VT == MVT::f32)
27033 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27034 if (VT == MVT::i16)
27035 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27036 if (VT == MVT::i8 || VT == MVT::i1)
27037 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27038 if (VT == MVT::i64)
27039 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27041 case 'r': // GENERAL_REGS
27042 case 'l': // INDEX_REGS
27043 if (VT == MVT::i8 || VT == MVT::i1)
27044 return std::make_pair(0U, &X86::GR8RegClass);
27045 if (VT == MVT::i16)
27046 return std::make_pair(0U, &X86::GR16RegClass);
27047 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27048 return std::make_pair(0U, &X86::GR32RegClass);
27049 return std::make_pair(0U, &X86::GR64RegClass);
27050 case 'R': // LEGACY_REGS
27051 if (VT == MVT::i8 || VT == MVT::i1)
27052 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27053 if (VT == MVT::i16)
27054 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27055 if (VT == MVT::i32 || !Subtarget->is64Bit())
27056 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27057 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27058 case 'f': // FP Stack registers.
27059 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27060 // value to the correct fpstack register class.
27061 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27062 return std::make_pair(0U, &X86::RFP32RegClass);
27063 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27064 return std::make_pair(0U, &X86::RFP64RegClass);
27065 return std::make_pair(0U, &X86::RFP80RegClass);
27066 case 'y': // MMX_REGS if MMX allowed.
27067 if (!Subtarget->hasMMX()) break;
27068 return std::make_pair(0U, &X86::VR64RegClass);
27069 case 'Y': // SSE_REGS if SSE2 allowed
27070 if (!Subtarget->hasSSE2()) break;
27072 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27073 if (!Subtarget->hasSSE1()) break;
27075 switch (VT.SimpleTy) {
27077 // Scalar SSE types.
27080 return std::make_pair(0U, &X86::FR32RegClass);
27083 return std::make_pair(0U, &X86::FR64RegClass);
27091 return std::make_pair(0U, &X86::VR128RegClass);
27099 return std::make_pair(0U, &X86::VR256RegClass);
27104 return std::make_pair(0U, &X86::VR512RegClass);
27110 // Use the default implementation in TargetLowering to convert the register
27111 // constraint into a member of a register class.
27112 std::pair<unsigned, const TargetRegisterClass*> Res;
27113 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27115 // Not found as a standard register?
27117 // Map st(0) -> st(7) -> ST0
27118 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27119 tolower(Constraint[1]) == 's' &&
27120 tolower(Constraint[2]) == 't' &&
27121 Constraint[3] == '(' &&
27122 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27123 Constraint[5] == ')' &&
27124 Constraint[6] == '}') {
27126 Res.first = X86::FP0+Constraint[4]-'0';
27127 Res.second = &X86::RFP80RegClass;
27131 // GCC allows "st(0)" to be called just plain "st".
27132 if (StringRef("{st}").equals_lower(Constraint)) {
27133 Res.first = X86::FP0;
27134 Res.second = &X86::RFP80RegClass;
27139 if (StringRef("{flags}").equals_lower(Constraint)) {
27140 Res.first = X86::EFLAGS;
27141 Res.second = &X86::CCRRegClass;
27145 // 'A' means EAX + EDX.
27146 if (Constraint == "A") {
27147 Res.first = X86::EAX;
27148 Res.second = &X86::GR32_ADRegClass;
27154 // Otherwise, check to see if this is a register class of the wrong value
27155 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27156 // turn into {ax},{dx}.
27157 // MVT::Other is used to specify clobber names.
27158 if (Res.second->hasType(VT) || VT == MVT::Other)
27159 return Res; // Correct type already, nothing to do.
27161 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27162 // return "eax". This should even work for things like getting 64bit integer
27163 // registers when given an f64 type.
27164 const TargetRegisterClass *Class = Res.second;
27165 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27166 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27167 unsigned Size = VT.getSizeInBits();
27168 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27169 : Size == 16 ? MVT::i16
27170 : Size == 32 ? MVT::i32
27171 : Size == 64 ? MVT::i64
27173 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27175 Res.first = DestReg;
27176 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27177 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27178 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27179 : &X86::GR64RegClass;
27180 assert(Res.second->contains(Res.first) && "Register in register class");
27182 // No register found/type mismatch.
27184 Res.second = nullptr;
27186 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27187 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27188 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27189 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27190 Class == &X86::VR512RegClass) {
27191 // Handle references to XMM physical registers that got mapped into the
27192 // wrong class. This can happen with constraints like {xmm0} where the
27193 // target independent register mapper will just pick the first match it can
27194 // find, ignoring the required type.
27196 if (VT == MVT::f32 || VT == MVT::i32)
27197 Res.second = &X86::FR32RegClass;
27198 else if (VT == MVT::f64 || VT == MVT::i64)
27199 Res.second = &X86::FR64RegClass;
27200 else if (X86::VR128RegClass.hasType(VT))
27201 Res.second = &X86::VR128RegClass;
27202 else if (X86::VR256RegClass.hasType(VT))
27203 Res.second = &X86::VR256RegClass;
27204 else if (X86::VR512RegClass.hasType(VT))
27205 Res.second = &X86::VR512RegClass;
27207 // Type mismatch and not a clobber: Return an error;
27209 Res.second = nullptr;
27216 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27217 const AddrMode &AM, Type *Ty,
27218 unsigned AS) const {
27219 // Scaling factors are not free at all.
27220 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27221 // will take 2 allocations in the out of order engine instead of 1
27222 // for plain addressing mode, i.e. inst (reg1).
27224 // vaddps (%rsi,%drx), %ymm0, %ymm1
27225 // Requires two allocations (one for the load, one for the computation)
27227 // vaddps (%rsi), %ymm0, %ymm1
27228 // Requires just 1 allocation, i.e., freeing allocations for other operations
27229 // and having less micro operations to execute.
27231 // For some X86 architectures, this is even worse because for instance for
27232 // stores, the complex addressing mode forces the instruction to use the
27233 // "load" ports instead of the dedicated "store" port.
27234 // E.g., on Haswell:
27235 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27236 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27237 if (isLegalAddressingMode(DL, AM, Ty, AS))
27238 // Scale represents reg2 * scale, thus account for 1
27239 // as soon as we use a second register.
27240 return AM.Scale != 0;
27244 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27245 // Integer division on x86 is expensive. However, when aggressively optimizing
27246 // for code size, we prefer to use a div instruction, as it is usually smaller
27247 // than the alternative sequence.
27248 // The exception to this is vector division. Since x86 doesn't have vector
27249 // integer division, leaving the division as-is is a loss even in terms of
27250 // size, because it will have to be scalarized, while the alternative code
27251 // sequence can be performed in vector form.
27252 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27253 Attribute::MinSize);
27254 return OptSize && !VT.isVector();