1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit bounday. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
171 unsigned IdxVal, SelectionDAG &DAG,
173 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
174 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
177 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
178 unsigned IdxVal, SelectionDAG &DAG,
180 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
181 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
184 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
185 /// instructions. This is used because creating CONCAT_VECTOR nodes of
186 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
187 /// large BUILD_VECTORS.
188 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
189 unsigned NumElems, SelectionDAG &DAG,
191 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
192 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
195 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
196 unsigned NumElems, SelectionDAG &DAG,
198 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
199 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
202 // FIXME: This should stop caching the target machine as soon as
203 // we can remove resetOperationActions et al.
204 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
205 : TargetLowering(TM) {
206 Subtarget = &TM.getSubtarget<X86Subtarget>();
207 X86ScalarSSEf64 = Subtarget->hasSSE2();
208 X86ScalarSSEf32 = Subtarget->hasSSE1();
209 TD = getDataLayout();
211 resetOperationActions();
214 void X86TargetLowering::resetOperationActions() {
215 const TargetMachine &TM = getTargetMachine();
216 static bool FirstTimeThrough = true;
218 // If none of the target options have changed, then we don't need to reset the
219 // operation actions.
220 if (!FirstTimeThrough && TO == TM.Options) return;
222 if (!FirstTimeThrough) {
223 // Reinitialize the actions.
225 FirstTimeThrough = false;
230 // Set up the TargetLowering object.
231 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
233 // X86 is weird, it always uses i8 for shift amounts and setcc results.
234 setBooleanContents(ZeroOrOneBooleanContent);
235 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
236 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
238 // For 64-bit since we have so many registers use the ILP scheduler, for
239 // 32-bit code use the register pressure specific scheduling.
240 // For Atom, always use ILP scheduling.
241 if (Subtarget->isAtom())
242 setSchedulingPreference(Sched::ILP);
243 else if (Subtarget->is64Bit())
244 setSchedulingPreference(Sched::ILP);
246 setSchedulingPreference(Sched::RegPressure);
247 const X86RegisterInfo *RegInfo =
248 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
249 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
251 // Bypass expensive divides on Atom when compiling with O2
252 if (TM.getOptLevel() >= CodeGenOpt::Default) {
253 if (Subtarget->hasSlowDivide32())
254 addBypassSlowDiv(32, 8);
255 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
256 addBypassSlowDiv(64, 16);
259 if (Subtarget->isTargetKnownWindowsMSVC()) {
260 // Setup Windows compiler runtime calls.
261 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
262 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
263 setLibcallName(RTLIB::SREM_I64, "_allrem");
264 setLibcallName(RTLIB::UREM_I64, "_aullrem");
265 setLibcallName(RTLIB::MUL_I64, "_allmul");
266 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
268 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
269 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
270 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
272 // The _ftol2 runtime function has an unusual calling conv, which
273 // is modeled by a special pseudo-instruction.
274 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
275 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
276 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
277 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
280 if (Subtarget->isTargetDarwin()) {
281 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
282 setUseUnderscoreSetJmp(false);
283 setUseUnderscoreLongJmp(false);
284 } else if (Subtarget->isTargetWindowsGNU()) {
285 // MS runtime is weird: it exports _setjmp, but longjmp!
286 setUseUnderscoreSetJmp(true);
287 setUseUnderscoreLongJmp(false);
289 setUseUnderscoreSetJmp(true);
290 setUseUnderscoreLongJmp(true);
293 // Set up the register classes.
294 addRegisterClass(MVT::i8, &X86::GR8RegClass);
295 addRegisterClass(MVT::i16, &X86::GR16RegClass);
296 addRegisterClass(MVT::i32, &X86::GR32RegClass);
297 if (Subtarget->is64Bit())
298 addRegisterClass(MVT::i64, &X86::GR64RegClass);
300 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
302 // We don't accept any truncstore of integer registers.
303 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
304 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
305 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
306 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
307 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
308 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
310 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
312 // SETOEQ and SETUNE require checking two conditions.
313 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
314 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
315 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
316 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
317 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
318 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
320 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
322 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
324 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
326 if (Subtarget->is64Bit()) {
327 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
328 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
329 } else if (!TM.Options.UseSoftFloat) {
330 // We have an algorithm for SSE2->double, and we turn this into a
331 // 64-bit FILD followed by conditional FADD for other targets.
332 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
333 // We have an algorithm for SSE2, and we turn this into a 64-bit
334 // FILD for other targets.
335 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
338 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
340 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
343 if (!TM.Options.UseSoftFloat) {
344 // SSE has no i16 to fp conversion, only i32
345 if (X86ScalarSSEf32) {
346 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
347 // f32 and f64 cases are Legal, f80 case is not
348 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
354 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
358 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
359 // are Legal, f80 is custom lowered.
360 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
363 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
365 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
366 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
368 if (X86ScalarSSEf32) {
369 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
370 // f32 and f64 cases are Legal, f80 case is not
371 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
374 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
377 // Handle FP_TO_UINT by promoting the destination to a larger signed
379 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
381 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
383 if (Subtarget->is64Bit()) {
384 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
385 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
386 } else if (!TM.Options.UseSoftFloat) {
387 // Since AVX is a superset of SSE3, only check for SSE here.
388 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
389 // Expand FP_TO_UINT into a select.
390 // FIXME: We would like to use a Custom expander here eventually to do
391 // the optimal thing for SSE vs. the default expansion in the legalizer.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
394 // With SSE3 we can use fisttpll to convert to a signed i64; without
395 // SSE, we're stuck with a fistpll.
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
399 if (isTargetFTOL()) {
400 // Use the _ftol2 runtime function, which has a pseudo-instruction
401 // to handle its weird calling convention.
402 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
405 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
406 if (!X86ScalarSSEf64) {
407 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
408 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
409 if (Subtarget->is64Bit()) {
410 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
411 // Without SSE, i64->f64 goes through memory.
412 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
416 // Scalar integer divide and remainder are lowered to use operations that
417 // produce two results, to match the available instructions. This exposes
418 // the two-result form to trivial CSE, which is able to combine x/y and x%y
419 // into a single instruction.
421 // Scalar integer multiply-high is also lowered to use two-result
422 // operations, to match the available instructions. However, plain multiply
423 // (low) operations are left as Legal, as there are single-result
424 // instructions for this in x86. Using the two-result multiply instructions
425 // when both high and low results are needed must be arranged by dagcombine.
426 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
428 setOperationAction(ISD::MULHS, VT, Expand);
429 setOperationAction(ISD::MULHU, VT, Expand);
430 setOperationAction(ISD::SDIV, VT, Expand);
431 setOperationAction(ISD::UDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UREM, VT, Expand);
435 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
436 setOperationAction(ISD::ADDC, VT, Custom);
437 setOperationAction(ISD::ADDE, VT, Custom);
438 setOperationAction(ISD::SUBC, VT, Custom);
439 setOperationAction(ISD::SUBE, VT, Custom);
442 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
443 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
444 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
446 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
447 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
448 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
449 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
450 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
456 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
457 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
458 if (Subtarget->is64Bit())
459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
461 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
462 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
463 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
464 setOperationAction(ISD::FREM , MVT::f32 , Expand);
465 setOperationAction(ISD::FREM , MVT::f64 , Expand);
466 setOperationAction(ISD::FREM , MVT::f80 , Expand);
467 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
469 // Promote the i8 variants and force them on up to i32 which has a shorter
471 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
472 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
473 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
474 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
475 if (Subtarget->hasBMI()) {
476 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
478 if (Subtarget->is64Bit())
479 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
481 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
482 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
483 if (Subtarget->is64Bit())
484 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
487 if (Subtarget->hasLZCNT()) {
488 // When promoting the i8 variants, force them to i32 for a shorter
490 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
491 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
493 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
494 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
495 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
496 if (Subtarget->is64Bit())
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
499 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
500 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
501 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
505 if (Subtarget->is64Bit()) {
506 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
507 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
511 // Special handling for half-precision floating point conversions.
512 // If we don't have F16C support, then lower half float conversions
513 // into library calls.
514 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
515 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
516 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
519 // There's never any support for operations beyond MVT::f32.
520 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
521 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
522 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
523 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
525 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
527 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
528 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
530 if (Subtarget->hasPOPCNT()) {
531 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
533 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
534 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
535 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
536 if (Subtarget->is64Bit())
537 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
540 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
542 if (!Subtarget->hasMOVBE())
543 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
545 // These should be promoted to a larger select which is supported.
546 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
547 // X86 wants to expand cmov itself.
548 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
549 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
550 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
552 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
553 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
555 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
556 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
558 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
559 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
560 if (Subtarget->is64Bit()) {
561 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
564 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
565 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
566 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
567 // support continuation, user-level threading, and etc.. As a result, no
568 // other SjLj exception interfaces are implemented and please don't build
569 // your own exception handling based on them.
570 // LLVM/Clang supports zero-cost DWARF exception handling.
571 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
572 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
575 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
576 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
577 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
578 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
579 if (Subtarget->is64Bit())
580 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
581 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
582 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
583 if (Subtarget->is64Bit()) {
584 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
585 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
586 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
587 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
588 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
590 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
591 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
592 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
593 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
596 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
597 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
600 if (Subtarget->hasSSE1())
601 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
603 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
605 // Expand certain atomics
606 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
608 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
609 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
610 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
613 if (Subtarget->hasCmpxchg16b()) {
614 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
617 // FIXME - use subtarget debug flags
618 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
619 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
620 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
623 if (Subtarget->is64Bit()) {
624 setExceptionPointerRegister(X86::RAX);
625 setExceptionSelectorRegister(X86::RDX);
627 setExceptionPointerRegister(X86::EAX);
628 setExceptionSelectorRegister(X86::EDX);
630 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
631 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
633 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
634 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
636 setOperationAction(ISD::TRAP, MVT::Other, Legal);
637 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
639 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
640 setOperationAction(ISD::VASTART , MVT::Other, Custom);
641 setOperationAction(ISD::VAEND , MVT::Other, Expand);
642 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
643 // TargetInfo::X86_64ABIBuiltinVaList
644 setOperationAction(ISD::VAARG , MVT::Other, Custom);
645 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
647 // TargetInfo::CharPtrBuiltinVaList
648 setOperationAction(ISD::VAARG , MVT::Other, Expand);
649 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
652 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
653 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
655 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
657 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
658 // f32 and f64 use SSE.
659 // Set up the FP register classes.
660 addRegisterClass(MVT::f32, &X86::FR32RegClass);
661 addRegisterClass(MVT::f64, &X86::FR64RegClass);
663 // Use ANDPD to simulate FABS.
664 setOperationAction(ISD::FABS , MVT::f64, Custom);
665 setOperationAction(ISD::FABS , MVT::f32, Custom);
667 // Use XORP to simulate FNEG.
668 setOperationAction(ISD::FNEG , MVT::f64, Custom);
669 setOperationAction(ISD::FNEG , MVT::f32, Custom);
671 // Use ANDPD and ORPD to simulate FCOPYSIGN.
672 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
673 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
675 // Lower this to FGETSIGNx86 plus an AND.
676 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
677 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
679 // We don't support sin/cos/fmod
680 setOperationAction(ISD::FSIN , MVT::f64, Expand);
681 setOperationAction(ISD::FCOS , MVT::f64, Expand);
682 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
683 setOperationAction(ISD::FSIN , MVT::f32, Expand);
684 setOperationAction(ISD::FCOS , MVT::f32, Expand);
685 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
687 // Expand FP immediates into loads from the stack, except for the special
689 addLegalFPImmediate(APFloat(+0.0)); // xorpd
690 addLegalFPImmediate(APFloat(+0.0f)); // xorps
691 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
692 // Use SSE for f32, x87 for f64.
693 // Set up the FP register classes.
694 addRegisterClass(MVT::f32, &X86::FR32RegClass);
695 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
697 // Use ANDPS to simulate FABS.
698 setOperationAction(ISD::FABS , MVT::f32, Custom);
700 // Use XORP to simulate FNEG.
701 setOperationAction(ISD::FNEG , MVT::f32, Custom);
703 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
705 // Use ANDPS and ORPS to simulate FCOPYSIGN.
706 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
707 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
709 // We don't support sin/cos/fmod
710 setOperationAction(ISD::FSIN , MVT::f32, Expand);
711 setOperationAction(ISD::FCOS , MVT::f32, Expand);
712 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
714 // Special cases we handle for FP constants.
715 addLegalFPImmediate(APFloat(+0.0f)); // xorps
716 addLegalFPImmediate(APFloat(+0.0)); // FLD0
717 addLegalFPImmediate(APFloat(+1.0)); // FLD1
718 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
719 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
721 if (!TM.Options.UnsafeFPMath) {
722 setOperationAction(ISD::FSIN , MVT::f64, Expand);
723 setOperationAction(ISD::FCOS , MVT::f64, Expand);
724 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
726 } else if (!TM.Options.UseSoftFloat) {
727 // f32 and f64 in x87.
728 // Set up the FP register classes.
729 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
730 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
732 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
733 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
734 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
735 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
737 if (!TM.Options.UnsafeFPMath) {
738 setOperationAction(ISD::FSIN , MVT::f64, Expand);
739 setOperationAction(ISD::FSIN , MVT::f32, Expand);
740 setOperationAction(ISD::FCOS , MVT::f64, Expand);
741 setOperationAction(ISD::FCOS , MVT::f32, Expand);
742 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
743 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
745 addLegalFPImmediate(APFloat(+0.0)); // FLD0
746 addLegalFPImmediate(APFloat(+1.0)); // FLD1
747 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
748 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
749 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
750 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
751 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
752 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
755 // We don't support FMA.
756 setOperationAction(ISD::FMA, MVT::f64, Expand);
757 setOperationAction(ISD::FMA, MVT::f32, Expand);
759 // Long double always uses X87.
760 if (!TM.Options.UseSoftFloat) {
761 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
762 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
763 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
765 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
766 addLegalFPImmediate(TmpFlt); // FLD0
768 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
771 APFloat TmpFlt2(+1.0);
772 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
774 addLegalFPImmediate(TmpFlt2); // FLD1
775 TmpFlt2.changeSign();
776 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
779 if (!TM.Options.UnsafeFPMath) {
780 setOperationAction(ISD::FSIN , MVT::f80, Expand);
781 setOperationAction(ISD::FCOS , MVT::f80, Expand);
782 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
785 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
786 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
787 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
788 setOperationAction(ISD::FRINT, MVT::f80, Expand);
789 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
790 setOperationAction(ISD::FMA, MVT::f80, Expand);
793 // Always use a library call for pow.
794 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
795 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
796 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
798 setOperationAction(ISD::FLOG, MVT::f80, Expand);
799 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
800 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
801 setOperationAction(ISD::FEXP, MVT::f80, Expand);
802 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
803 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
804 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
806 // First set operation action for all vector types to either promote
807 // (for widening) or expand (for scalarization). Then we will selectively
808 // turn on ones that can be effectively codegen'd.
809 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
810 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
811 MVT VT = (MVT::SimpleValueType)i;
812 setOperationAction(ISD::ADD , VT, Expand);
813 setOperationAction(ISD::SUB , VT, Expand);
814 setOperationAction(ISD::FADD, VT, Expand);
815 setOperationAction(ISD::FNEG, VT, Expand);
816 setOperationAction(ISD::FSUB, VT, Expand);
817 setOperationAction(ISD::MUL , VT, Expand);
818 setOperationAction(ISD::FMUL, VT, Expand);
819 setOperationAction(ISD::SDIV, VT, Expand);
820 setOperationAction(ISD::UDIV, VT, Expand);
821 setOperationAction(ISD::FDIV, VT, Expand);
822 setOperationAction(ISD::SREM, VT, Expand);
823 setOperationAction(ISD::UREM, VT, Expand);
824 setOperationAction(ISD::LOAD, VT, Expand);
825 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
826 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
827 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
828 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
829 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
830 setOperationAction(ISD::FABS, VT, Expand);
831 setOperationAction(ISD::FSIN, VT, Expand);
832 setOperationAction(ISD::FSINCOS, VT, Expand);
833 setOperationAction(ISD::FCOS, VT, Expand);
834 setOperationAction(ISD::FSINCOS, VT, Expand);
835 setOperationAction(ISD::FREM, VT, Expand);
836 setOperationAction(ISD::FMA, VT, Expand);
837 setOperationAction(ISD::FPOWI, VT, Expand);
838 setOperationAction(ISD::FSQRT, VT, Expand);
839 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
840 setOperationAction(ISD::FFLOOR, VT, Expand);
841 setOperationAction(ISD::FCEIL, VT, Expand);
842 setOperationAction(ISD::FTRUNC, VT, Expand);
843 setOperationAction(ISD::FRINT, VT, Expand);
844 setOperationAction(ISD::FNEARBYINT, VT, Expand);
845 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
846 setOperationAction(ISD::MULHS, VT, Expand);
847 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
848 setOperationAction(ISD::MULHU, VT, Expand);
849 setOperationAction(ISD::SDIVREM, VT, Expand);
850 setOperationAction(ISD::UDIVREM, VT, Expand);
851 setOperationAction(ISD::FPOW, VT, Expand);
852 setOperationAction(ISD::CTPOP, VT, Expand);
853 setOperationAction(ISD::CTTZ, VT, Expand);
854 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
855 setOperationAction(ISD::CTLZ, VT, Expand);
856 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
857 setOperationAction(ISD::SHL, VT, Expand);
858 setOperationAction(ISD::SRA, VT, Expand);
859 setOperationAction(ISD::SRL, VT, Expand);
860 setOperationAction(ISD::ROTL, VT, Expand);
861 setOperationAction(ISD::ROTR, VT, Expand);
862 setOperationAction(ISD::BSWAP, VT, Expand);
863 setOperationAction(ISD::SETCC, VT, Expand);
864 setOperationAction(ISD::FLOG, VT, Expand);
865 setOperationAction(ISD::FLOG2, VT, Expand);
866 setOperationAction(ISD::FLOG10, VT, Expand);
867 setOperationAction(ISD::FEXP, VT, Expand);
868 setOperationAction(ISD::FEXP2, VT, Expand);
869 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
870 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
871 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
872 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
873 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
874 setOperationAction(ISD::TRUNCATE, VT, Expand);
875 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
876 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
877 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
878 setOperationAction(ISD::VSELECT, VT, Expand);
879 setOperationAction(ISD::SELECT_CC, VT, Expand);
880 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
881 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
882 setTruncStoreAction(VT,
883 (MVT::SimpleValueType)InnerVT, Expand);
884 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
885 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
887 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
888 // we have to deal with them whether we ask for Expansion or not. Setting
889 // Expand causes its own optimisation problems though, so leave them legal.
890 if (VT.getVectorElementType() == MVT::i1)
891 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
894 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
895 // with -msoft-float, disable use of MMX as well.
896 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
897 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
898 // No operations on x86mmx supported, everything uses intrinsics.
901 // MMX-sized vectors (other than x86mmx) are expected to be expanded
902 // into smaller operations.
903 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
904 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
905 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
906 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
907 setOperationAction(ISD::AND, MVT::v8i8, Expand);
908 setOperationAction(ISD::AND, MVT::v4i16, Expand);
909 setOperationAction(ISD::AND, MVT::v2i32, Expand);
910 setOperationAction(ISD::AND, MVT::v1i64, Expand);
911 setOperationAction(ISD::OR, MVT::v8i8, Expand);
912 setOperationAction(ISD::OR, MVT::v4i16, Expand);
913 setOperationAction(ISD::OR, MVT::v2i32, Expand);
914 setOperationAction(ISD::OR, MVT::v1i64, Expand);
915 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
916 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
917 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
918 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
921 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
922 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
923 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
924 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
925 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
926 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
927 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
928 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
929 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
930 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
931 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
933 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
934 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
936 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
937 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
938 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
939 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
940 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
941 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
942 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
943 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
944 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
945 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
946 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
947 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
948 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
951 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
952 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
954 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
955 // registers cannot be used even for integer operations.
956 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
957 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
958 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
959 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
961 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
962 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
963 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
964 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
965 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
966 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
967 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
968 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
969 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
970 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
971 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
972 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
973 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
974 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
975 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
976 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
977 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
978 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
979 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
980 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
981 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
982 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
984 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
985 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
986 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
987 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
989 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
990 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
993 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
995 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
996 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
997 MVT VT = (MVT::SimpleValueType)i;
998 // Do not attempt to custom lower non-power-of-2 vectors
999 if (!isPowerOf2_32(VT.getVectorNumElements()))
1001 // Do not attempt to custom lower non-128-bit vectors
1002 if (!VT.is128BitVector())
1004 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1005 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1006 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1009 // We support custom legalizing of sext and anyext loads for specific
1010 // memory vector types which we can load as a scalar (or sequence of
1011 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1012 // loads these must work with a single scalar load.
1013 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1014 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1015 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1017 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1018 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1021 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1023 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1024 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1025 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1026 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1027 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1028 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1030 if (Subtarget->is64Bit()) {
1031 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1032 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1035 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1036 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1037 MVT VT = (MVT::SimpleValueType)i;
1039 // Do not attempt to promote non-128-bit vectors
1040 if (!VT.is128BitVector())
1043 setOperationAction(ISD::AND, VT, Promote);
1044 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1045 setOperationAction(ISD::OR, VT, Promote);
1046 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1047 setOperationAction(ISD::XOR, VT, Promote);
1048 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1049 setOperationAction(ISD::LOAD, VT, Promote);
1050 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1051 setOperationAction(ISD::SELECT, VT, Promote);
1052 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1055 // Custom lower v2i64 and v2f64 selects.
1056 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1057 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1058 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1059 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1061 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1062 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1064 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1065 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1066 // As there is no 64-bit GPR available, we need build a special custom
1067 // sequence to convert from v2i32 to v2f32.
1068 if (!Subtarget->is64Bit())
1069 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1071 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1072 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1074 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1076 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1077 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1078 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1081 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1082 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1085 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1087 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1088 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1089 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1090 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1091 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1093 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1094 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1095 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1098 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1099 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1100 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1101 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1102 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1104 // FIXME: Do we need to handle scalar-to-vector here?
1105 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1107 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1108 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1109 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1110 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1111 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1112 // There is no BLENDI for byte vectors. We don't need to custom lower
1113 // some vselects for now.
1114 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1116 // SSE41 brings specific instructions for doing vector sign extend even in
1117 // cases where we don't have SRA.
1118 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1119 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1120 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1122 // i8 and i16 vectors are custom because the source register and source
1123 // source memory operand types are not the same width. f32 vectors are
1124 // custom since the immediate controlling the insert encodes additional
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1128 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1129 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1133 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1134 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1136 // FIXME: these should be Legal, but that's only for the case where
1137 // the index is constant. For now custom expand to deal with that.
1138 if (Subtarget->is64Bit()) {
1139 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1144 if (Subtarget->hasSSE2()) {
1145 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1146 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1148 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1149 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1151 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1152 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1154 // In the customized shift lowering, the legal cases in AVX2 will be
1156 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1157 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1159 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1160 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1162 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1165 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1166 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1171 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1173 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1174 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1175 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1177 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1188 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1190 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1201 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1203 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1204 // even though v8i16 is a legal type.
1205 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1206 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1207 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1209 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1210 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1211 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1213 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1214 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1216 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1218 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1219 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1221 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1224 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1225 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1229 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1230 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1233 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1234 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1236 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1237 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1238 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1239 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1241 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1243 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1244 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1245 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1246 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1247 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1248 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1249 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1250 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1251 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1252 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1254 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1255 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1256 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1257 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1258 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1259 setOperationAction(ISD::FMA, MVT::f32, Legal);
1260 setOperationAction(ISD::FMA, MVT::f64, Legal);
1263 if (Subtarget->hasInt256()) {
1264 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1265 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1266 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1267 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1269 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1270 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1271 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1272 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1274 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1275 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1276 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1277 // Don't lower v32i8 because there is no 128-bit byte mul
1279 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1280 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1281 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1282 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1284 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1285 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1287 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1288 // when we have a 256bit-wide blend with immediate.
1289 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1291 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1292 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1293 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1294 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1296 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1297 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1298 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1299 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1301 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1302 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1303 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1304 // Don't lower v32i8 because there is no 128-bit byte mul
1307 // In the customized shift lowering, the legal cases in AVX2 will be
1309 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1310 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1312 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1313 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1315 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1317 // Custom lower several nodes for 256-bit types.
1318 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1319 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1320 MVT VT = (MVT::SimpleValueType)i;
1322 // Extract subvector is special because the value type
1323 // (result) is 128-bit but the source is 256-bit wide.
1324 if (VT.is128BitVector())
1325 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1327 // Do not attempt to custom lower other non-256-bit vectors
1328 if (!VT.is256BitVector())
1331 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1332 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1333 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1334 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1335 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1336 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1337 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1340 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1341 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1342 MVT VT = (MVT::SimpleValueType)i;
1344 // Do not attempt to promote non-256-bit vectors
1345 if (!VT.is256BitVector())
1348 setOperationAction(ISD::AND, VT, Promote);
1349 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1350 setOperationAction(ISD::OR, VT, Promote);
1351 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1352 setOperationAction(ISD::XOR, VT, Promote);
1353 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1354 setOperationAction(ISD::LOAD, VT, Promote);
1355 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1356 setOperationAction(ISD::SELECT, VT, Promote);
1357 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1361 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1362 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1363 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1364 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1365 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1367 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1368 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1369 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1371 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1372 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1373 setOperationAction(ISD::XOR, MVT::i1, Legal);
1374 setOperationAction(ISD::OR, MVT::i1, Legal);
1375 setOperationAction(ISD::AND, MVT::i1, Legal);
1376 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1377 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1378 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1379 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1380 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1383 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1384 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1385 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1386 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1387 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1390 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1391 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1392 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1393 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1394 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1396 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1399 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1400 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1401 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1402 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1403 if (Subtarget->is64Bit()) {
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1405 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1406 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1407 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1410 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1411 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1412 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1414 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1415 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1563 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1566 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1567 // of this type with custom code.
1568 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1569 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1570 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1574 // We want to custom lower some of our intrinsics.
1575 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1577 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1578 if (!Subtarget->is64Bit())
1579 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1581 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1582 // handle type legalization for these operations here.
1584 // FIXME: We really should do custom legalization for addition and
1585 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1586 // than generic legalization for 64-bit multiplication-with-overflow, though.
1587 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1588 // Add/Sub/Mul with overflow operations are custom lowered.
1590 setOperationAction(ISD::SADDO, VT, Custom);
1591 setOperationAction(ISD::UADDO, VT, Custom);
1592 setOperationAction(ISD::SSUBO, VT, Custom);
1593 setOperationAction(ISD::USUBO, VT, Custom);
1594 setOperationAction(ISD::SMULO, VT, Custom);
1595 setOperationAction(ISD::UMULO, VT, Custom);
1599 if (!Subtarget->is64Bit()) {
1600 // These libcalls are not available in 32-bit.
1601 setLibcallName(RTLIB::SHL_I128, nullptr);
1602 setLibcallName(RTLIB::SRL_I128, nullptr);
1603 setLibcallName(RTLIB::SRA_I128, nullptr);
1606 // Combine sin / cos into one node or libcall if possible.
1607 if (Subtarget->hasSinCos()) {
1608 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1609 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1610 if (Subtarget->isTargetDarwin()) {
1611 // For MacOSX, we don't want to the normal expansion of a libcall to
1612 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1614 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1615 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1619 if (Subtarget->isTargetWin64()) {
1620 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1621 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1622 setOperationAction(ISD::SREM, MVT::i128, Custom);
1623 setOperationAction(ISD::UREM, MVT::i128, Custom);
1624 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1625 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1628 // We have target-specific dag combine patterns for the following nodes:
1629 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1630 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1631 setTargetDAGCombine(ISD::VSELECT);
1632 setTargetDAGCombine(ISD::SELECT);
1633 setTargetDAGCombine(ISD::SHL);
1634 setTargetDAGCombine(ISD::SRA);
1635 setTargetDAGCombine(ISD::SRL);
1636 setTargetDAGCombine(ISD::OR);
1637 setTargetDAGCombine(ISD::AND);
1638 setTargetDAGCombine(ISD::ADD);
1639 setTargetDAGCombine(ISD::FADD);
1640 setTargetDAGCombine(ISD::FSUB);
1641 setTargetDAGCombine(ISD::FMA);
1642 setTargetDAGCombine(ISD::SUB);
1643 setTargetDAGCombine(ISD::LOAD);
1644 setTargetDAGCombine(ISD::STORE);
1645 setTargetDAGCombine(ISD::ZERO_EXTEND);
1646 setTargetDAGCombine(ISD::ANY_EXTEND);
1647 setTargetDAGCombine(ISD::SIGN_EXTEND);
1648 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1649 setTargetDAGCombine(ISD::TRUNCATE);
1650 setTargetDAGCombine(ISD::SINT_TO_FP);
1651 setTargetDAGCombine(ISD::SETCC);
1652 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1653 setTargetDAGCombine(ISD::BUILD_VECTOR);
1654 if (Subtarget->is64Bit())
1655 setTargetDAGCombine(ISD::MUL);
1656 setTargetDAGCombine(ISD::XOR);
1658 computeRegisterProperties();
1660 // On Darwin, -Os means optimize for size without hurting performance,
1661 // do not reduce the limit.
1662 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1663 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1664 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1665 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1666 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1667 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1668 setPrefLoopAlignment(4); // 2^4 bytes.
1670 // Predictable cmov don't hurt on atom because it's in-order.
1671 PredictableSelectIsExpensive = !Subtarget->isAtom();
1673 setPrefFunctionAlignment(4); // 2^4 bytes.
1675 verifyIntrinsicTables();
1678 // This has so far only been implemented for 64-bit MachO.
1679 bool X86TargetLowering::useLoadStackGuardNode() const {
1680 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1681 Subtarget->is64Bit();
1684 TargetLoweringBase::LegalizeTypeAction
1685 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1686 if (ExperimentalVectorWideningLegalization &&
1687 VT.getVectorNumElements() != 1 &&
1688 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1689 return TypeWidenVector;
1691 return TargetLoweringBase::getPreferredVectorAction(VT);
1694 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1696 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1698 const unsigned NumElts = VT.getVectorNumElements();
1699 const EVT EltVT = VT.getVectorElementType();
1700 if (VT.is512BitVector()) {
1701 if (Subtarget->hasAVX512())
1702 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1703 EltVT == MVT::f32 || EltVT == MVT::f64)
1705 case 8: return MVT::v8i1;
1706 case 16: return MVT::v16i1;
1708 if (Subtarget->hasBWI())
1709 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1711 case 32: return MVT::v32i1;
1712 case 64: return MVT::v64i1;
1716 if (VT.is256BitVector() || VT.is128BitVector()) {
1717 if (Subtarget->hasVLX())
1718 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1719 EltVT == MVT::f32 || EltVT == MVT::f64)
1721 case 2: return MVT::v2i1;
1722 case 4: return MVT::v4i1;
1723 case 8: return MVT::v8i1;
1725 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1726 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1728 case 8: return MVT::v8i1;
1729 case 16: return MVT::v16i1;
1730 case 32: return MVT::v32i1;
1734 return VT.changeVectorElementTypeToInteger();
1737 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1738 /// the desired ByVal argument alignment.
1739 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1742 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1743 if (VTy->getBitWidth() == 128)
1745 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1746 unsigned EltAlign = 0;
1747 getMaxByValAlign(ATy->getElementType(), EltAlign);
1748 if (EltAlign > MaxAlign)
1749 MaxAlign = EltAlign;
1750 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1751 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1752 unsigned EltAlign = 0;
1753 getMaxByValAlign(STy->getElementType(i), EltAlign);
1754 if (EltAlign > MaxAlign)
1755 MaxAlign = EltAlign;
1762 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1763 /// function arguments in the caller parameter area. For X86, aggregates
1764 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1765 /// are at 4-byte boundaries.
1766 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1767 if (Subtarget->is64Bit()) {
1768 // Max of 8 and alignment of type.
1769 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1776 if (Subtarget->hasSSE1())
1777 getMaxByValAlign(Ty, Align);
1781 /// getOptimalMemOpType - Returns the target specific optimal type for load
1782 /// and store operations as a result of memset, memcpy, and memmove
1783 /// lowering. If DstAlign is zero that means it's safe to destination
1784 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1785 /// means there isn't a need to check it against alignment requirement,
1786 /// probably because the source does not need to be loaded. If 'IsMemset' is
1787 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1788 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1789 /// source is constant so it does not need to be loaded.
1790 /// It returns EVT::Other if the type should be determined using generic
1791 /// target-independent logic.
1793 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1794 unsigned DstAlign, unsigned SrcAlign,
1795 bool IsMemset, bool ZeroMemset,
1797 MachineFunction &MF) const {
1798 const Function *F = MF.getFunction();
1799 if ((!IsMemset || ZeroMemset) &&
1800 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1801 Attribute::NoImplicitFloat)) {
1803 (Subtarget->isUnalignedMemAccessFast() ||
1804 ((DstAlign == 0 || DstAlign >= 16) &&
1805 (SrcAlign == 0 || SrcAlign >= 16)))) {
1807 if (Subtarget->hasInt256())
1809 if (Subtarget->hasFp256())
1812 if (Subtarget->hasSSE2())
1814 if (Subtarget->hasSSE1())
1816 } else if (!MemcpyStrSrc && Size >= 8 &&
1817 !Subtarget->is64Bit() &&
1818 Subtarget->hasSSE2()) {
1819 // Do not use f64 to lower memcpy if source is string constant. It's
1820 // better to use i32 to avoid the loads.
1824 if (Subtarget->is64Bit() && Size >= 8)
1829 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1831 return X86ScalarSSEf32;
1832 else if (VT == MVT::f64)
1833 return X86ScalarSSEf64;
1838 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1843 *Fast = Subtarget->isUnalignedMemAccessFast();
1847 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1848 /// current function. The returned value is a member of the
1849 /// MachineJumpTableInfo::JTEntryKind enum.
1850 unsigned X86TargetLowering::getJumpTableEncoding() const {
1851 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1853 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1854 Subtarget->isPICStyleGOT())
1855 return MachineJumpTableInfo::EK_Custom32;
1857 // Otherwise, use the normal jump table encoding heuristics.
1858 return TargetLowering::getJumpTableEncoding();
1862 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1863 const MachineBasicBlock *MBB,
1864 unsigned uid,MCContext &Ctx) const{
1865 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1866 Subtarget->isPICStyleGOT());
1867 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1869 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1870 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1873 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1875 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1876 SelectionDAG &DAG) const {
1877 if (!Subtarget->is64Bit())
1878 // This doesn't have SDLoc associated with it, but is not really the
1879 // same as a Register.
1880 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1884 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1885 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1887 const MCExpr *X86TargetLowering::
1888 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1889 MCContext &Ctx) const {
1890 // X86-64 uses RIP relative addressing based on the jump table label.
1891 if (Subtarget->isPICStyleRIPRel())
1892 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1894 // Otherwise, the reference is relative to the PIC base.
1895 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1898 // FIXME: Why this routine is here? Move to RegInfo!
1899 std::pair<const TargetRegisterClass*, uint8_t>
1900 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1901 const TargetRegisterClass *RRC = nullptr;
1903 switch (VT.SimpleTy) {
1905 return TargetLowering::findRepresentativeClass(VT);
1906 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1907 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1910 RRC = &X86::VR64RegClass;
1912 case MVT::f32: case MVT::f64:
1913 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1914 case MVT::v4f32: case MVT::v2f64:
1915 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1917 RRC = &X86::VR128RegClass;
1920 return std::make_pair(RRC, Cost);
1923 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1924 unsigned &Offset) const {
1925 if (!Subtarget->isTargetLinux())
1928 if (Subtarget->is64Bit()) {
1929 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1931 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1943 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1944 unsigned DestAS) const {
1945 assert(SrcAS != DestAS && "Expected different address spaces!");
1947 return SrcAS < 256 && DestAS < 256;
1950 //===----------------------------------------------------------------------===//
1951 // Return Value Calling Convention Implementation
1952 //===----------------------------------------------------------------------===//
1954 #include "X86GenCallingConv.inc"
1957 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1958 MachineFunction &MF, bool isVarArg,
1959 const SmallVectorImpl<ISD::OutputArg> &Outs,
1960 LLVMContext &Context) const {
1961 SmallVector<CCValAssign, 16> RVLocs;
1962 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1963 return CCInfo.CheckReturn(Outs, RetCC_X86);
1966 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1967 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1972 X86TargetLowering::LowerReturn(SDValue Chain,
1973 CallingConv::ID CallConv, bool isVarArg,
1974 const SmallVectorImpl<ISD::OutputArg> &Outs,
1975 const SmallVectorImpl<SDValue> &OutVals,
1976 SDLoc dl, SelectionDAG &DAG) const {
1977 MachineFunction &MF = DAG.getMachineFunction();
1978 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1980 SmallVector<CCValAssign, 16> RVLocs;
1981 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1982 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1985 SmallVector<SDValue, 6> RetOps;
1986 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1987 // Operand #1 = Bytes To Pop
1988 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1991 // Copy the result values into the output registers.
1992 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1993 CCValAssign &VA = RVLocs[i];
1994 assert(VA.isRegLoc() && "Can only return in registers!");
1995 SDValue ValToCopy = OutVals[i];
1996 EVT ValVT = ValToCopy.getValueType();
1998 // Promote values to the appropriate types
1999 if (VA.getLocInfo() == CCValAssign::SExt)
2000 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2001 else if (VA.getLocInfo() == CCValAssign::ZExt)
2002 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2003 else if (VA.getLocInfo() == CCValAssign::AExt)
2004 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2005 else if (VA.getLocInfo() == CCValAssign::BCvt)
2006 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2008 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2009 "Unexpected FP-extend for return value.");
2011 // If this is x86-64, and we disabled SSE, we can't return FP values,
2012 // or SSE or MMX vectors.
2013 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2014 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2015 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2016 report_fatal_error("SSE register return with SSE disabled");
2018 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2019 // llvm-gcc has never done it right and no one has noticed, so this
2020 // should be OK for now.
2021 if (ValVT == MVT::f64 &&
2022 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2023 report_fatal_error("SSE2 register return with SSE2 disabled");
2025 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2026 // the RET instruction and handled by the FP Stackifier.
2027 if (VA.getLocReg() == X86::FP0 ||
2028 VA.getLocReg() == X86::FP1) {
2029 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2030 // change the value to the FP stack register class.
2031 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2032 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2033 RetOps.push_back(ValToCopy);
2034 // Don't emit a copytoreg.
2038 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2039 // which is returned in RAX / RDX.
2040 if (Subtarget->is64Bit()) {
2041 if (ValVT == MVT::x86mmx) {
2042 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2043 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2044 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2046 // If we don't have SSE2 available, convert to v4f32 so the generated
2047 // register is legal.
2048 if (!Subtarget->hasSSE2())
2049 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2054 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2055 Flag = Chain.getValue(1);
2056 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2059 // The x86-64 ABIs require that for returning structs by value we copy
2060 // the sret argument into %rax/%eax (depending on ABI) for the return.
2061 // Win32 requires us to put the sret argument to %eax as well.
2062 // We saved the argument into a virtual register in the entry block,
2063 // so now we copy the value out and into %rax/%eax.
2064 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2065 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2066 MachineFunction &MF = DAG.getMachineFunction();
2067 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2068 unsigned Reg = FuncInfo->getSRetReturnReg();
2070 "SRetReturnReg should have been set in LowerFormalArguments().");
2071 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2074 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2075 X86::RAX : X86::EAX;
2076 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2077 Flag = Chain.getValue(1);
2079 // RAX/EAX now acts like a return value.
2080 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2083 RetOps[0] = Chain; // Update chain.
2085 // Add the flag if we have it.
2087 RetOps.push_back(Flag);
2089 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2092 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2093 if (N->getNumValues() != 1)
2095 if (!N->hasNUsesOfValue(1, 0))
2098 SDValue TCChain = Chain;
2099 SDNode *Copy = *N->use_begin();
2100 if (Copy->getOpcode() == ISD::CopyToReg) {
2101 // If the copy has a glue operand, we conservatively assume it isn't safe to
2102 // perform a tail call.
2103 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2105 TCChain = Copy->getOperand(0);
2106 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2109 bool HasRet = false;
2110 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2112 if (UI->getOpcode() != X86ISD::RET_FLAG)
2114 // If we are returning more than one value, we can definitely
2115 // not make a tail call see PR19530
2116 if (UI->getNumOperands() > 4)
2118 if (UI->getNumOperands() == 4 &&
2119 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2132 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2133 ISD::NodeType ExtendKind) const {
2135 // TODO: Is this also valid on 32-bit?
2136 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2137 ReturnMVT = MVT::i8;
2139 ReturnMVT = MVT::i32;
2141 EVT MinVT = getRegisterType(Context, ReturnMVT);
2142 return VT.bitsLT(MinVT) ? MinVT : VT;
2145 /// LowerCallResult - Lower the result values of a call into the
2146 /// appropriate copies out of appropriate physical registers.
2149 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2150 CallingConv::ID CallConv, bool isVarArg,
2151 const SmallVectorImpl<ISD::InputArg> &Ins,
2152 SDLoc dl, SelectionDAG &DAG,
2153 SmallVectorImpl<SDValue> &InVals) const {
2155 // Assign locations to each value returned by this call.
2156 SmallVector<CCValAssign, 16> RVLocs;
2157 bool Is64Bit = Subtarget->is64Bit();
2158 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2160 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2162 // Copy all of the result registers out of their specified physreg.
2163 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2164 CCValAssign &VA = RVLocs[i];
2165 EVT CopyVT = VA.getValVT();
2167 // If this is x86-64, and we disabled SSE, we can't return FP values
2168 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2169 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2170 report_fatal_error("SSE register return with SSE disabled");
2173 // If we prefer to use the value in xmm registers, copy it out as f80 and
2174 // use a truncate to move it from fp stack reg to xmm reg.
2175 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2176 isScalarFPTypeInSSEReg(VA.getValVT()))
2179 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2180 CopyVT, InFlag).getValue(1);
2181 SDValue Val = Chain.getValue(0);
2183 if (CopyVT != VA.getValVT())
2184 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2185 // This truncation won't change the value.
2186 DAG.getIntPtrConstant(1));
2188 InFlag = Chain.getValue(2);
2189 InVals.push_back(Val);
2195 //===----------------------------------------------------------------------===//
2196 // C & StdCall & Fast Calling Convention implementation
2197 //===----------------------------------------------------------------------===//
2198 // StdCall calling convention seems to be standard for many Windows' API
2199 // routines and around. It differs from C calling convention just a little:
2200 // callee should clean up the stack, not caller. Symbols should be also
2201 // decorated in some fancy way :) It doesn't support any vector arguments.
2202 // For info on fast calling convention see Fast Calling Convention (tail call)
2203 // implementation LowerX86_32FastCCCallTo.
2205 /// CallIsStructReturn - Determines whether a call uses struct return
2207 enum StructReturnType {
2212 static StructReturnType
2213 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2215 return NotStructReturn;
2217 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2218 if (!Flags.isSRet())
2219 return NotStructReturn;
2220 if (Flags.isInReg())
2221 return RegStructReturn;
2222 return StackStructReturn;
2225 /// ArgsAreStructReturn - Determines whether a function uses struct
2226 /// return semantics.
2227 static StructReturnType
2228 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2230 return NotStructReturn;
2232 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2233 if (!Flags.isSRet())
2234 return NotStructReturn;
2235 if (Flags.isInReg())
2236 return RegStructReturn;
2237 return StackStructReturn;
2240 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2241 /// by "Src" to address "Dst" with size and alignment information specified by
2242 /// the specific parameter attribute. The copy will be passed as a byval
2243 /// function parameter.
2245 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2246 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2248 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2250 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2251 /*isVolatile*/false, /*AlwaysInline=*/true,
2252 MachinePointerInfo(), MachinePointerInfo());
2255 /// IsTailCallConvention - Return true if the calling convention is one that
2256 /// supports tail call optimization.
2257 static bool IsTailCallConvention(CallingConv::ID CC) {
2258 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2259 CC == CallingConv::HiPE);
2262 /// \brief Return true if the calling convention is a C calling convention.
2263 static bool IsCCallConvention(CallingConv::ID CC) {
2264 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2265 CC == CallingConv::X86_64_SysV);
2268 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2269 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2273 CallingConv::ID CalleeCC = CS.getCallingConv();
2274 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2280 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2281 /// a tailcall target by changing its ABI.
2282 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2283 bool GuaranteedTailCallOpt) {
2284 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2288 X86TargetLowering::LowerMemArgument(SDValue Chain,
2289 CallingConv::ID CallConv,
2290 const SmallVectorImpl<ISD::InputArg> &Ins,
2291 SDLoc dl, SelectionDAG &DAG,
2292 const CCValAssign &VA,
2293 MachineFrameInfo *MFI,
2295 // Create the nodes corresponding to a load from this parameter slot.
2296 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2297 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2298 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2299 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2302 // If value is passed by pointer we have address passed instead of the value
2304 if (VA.getLocInfo() == CCValAssign::Indirect)
2305 ValVT = VA.getLocVT();
2307 ValVT = VA.getValVT();
2309 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2310 // changed with more analysis.
2311 // In case of tail call optimization mark all arguments mutable. Since they
2312 // could be overwritten by lowering of arguments in case of a tail call.
2313 if (Flags.isByVal()) {
2314 unsigned Bytes = Flags.getByValSize();
2315 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2316 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2317 return DAG.getFrameIndex(FI, getPointerTy());
2319 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2320 VA.getLocMemOffset(), isImmutable);
2321 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2322 return DAG.getLoad(ValVT, dl, Chain, FIN,
2323 MachinePointerInfo::getFixedStack(FI),
2324 false, false, false, 0);
2328 // FIXME: Get this from tablegen.
2329 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2330 const X86Subtarget *Subtarget) {
2331 assert(Subtarget->is64Bit());
2333 if (Subtarget->isCallingConvWin64(CallConv)) {
2334 static const MCPhysReg GPR64ArgRegsWin64[] = {
2335 X86::RCX, X86::RDX, X86::R8, X86::R9
2337 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2340 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2341 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2343 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2346 // FIXME: Get this from tablegen.
2347 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2348 CallingConv::ID CallConv,
2349 const X86Subtarget *Subtarget) {
2350 assert(Subtarget->is64Bit());
2351 if (Subtarget->isCallingConvWin64(CallConv)) {
2352 // The XMM registers which might contain var arg parameters are shadowed
2353 // in their paired GPR. So we only need to save the GPR to their home
2355 // TODO: __vectorcall will change this.
2359 const Function *Fn = MF.getFunction();
2360 bool NoImplicitFloatOps = Fn->getAttributes().
2361 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2362 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2363 "SSE register cannot be used when SSE is disabled!");
2364 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2365 !Subtarget->hasSSE1())
2366 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2370 static const MCPhysReg XMMArgRegs64Bit[] = {
2371 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2372 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2374 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2378 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2379 CallingConv::ID CallConv,
2381 const SmallVectorImpl<ISD::InputArg> &Ins,
2384 SmallVectorImpl<SDValue> &InVals)
2386 MachineFunction &MF = DAG.getMachineFunction();
2387 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2389 const Function* Fn = MF.getFunction();
2390 if (Fn->hasExternalLinkage() &&
2391 Subtarget->isTargetCygMing() &&
2392 Fn->getName() == "main")
2393 FuncInfo->setForceFramePointer(true);
2395 MachineFrameInfo *MFI = MF.getFrameInfo();
2396 bool Is64Bit = Subtarget->is64Bit();
2397 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2399 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2400 "Var args not supported with calling convention fastcc, ghc or hipe");
2402 // Assign locations to all of the incoming arguments.
2403 SmallVector<CCValAssign, 16> ArgLocs;
2404 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2406 // Allocate shadow area for Win64
2408 CCInfo.AllocateStack(32, 8);
2410 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2412 unsigned LastVal = ~0U;
2414 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2415 CCValAssign &VA = ArgLocs[i];
2416 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2418 assert(VA.getValNo() != LastVal &&
2419 "Don't support value assigned to multiple locs yet");
2421 LastVal = VA.getValNo();
2423 if (VA.isRegLoc()) {
2424 EVT RegVT = VA.getLocVT();
2425 const TargetRegisterClass *RC;
2426 if (RegVT == MVT::i32)
2427 RC = &X86::GR32RegClass;
2428 else if (Is64Bit && RegVT == MVT::i64)
2429 RC = &X86::GR64RegClass;
2430 else if (RegVT == MVT::f32)
2431 RC = &X86::FR32RegClass;
2432 else if (RegVT == MVT::f64)
2433 RC = &X86::FR64RegClass;
2434 else if (RegVT.is512BitVector())
2435 RC = &X86::VR512RegClass;
2436 else if (RegVT.is256BitVector())
2437 RC = &X86::VR256RegClass;
2438 else if (RegVT.is128BitVector())
2439 RC = &X86::VR128RegClass;
2440 else if (RegVT == MVT::x86mmx)
2441 RC = &X86::VR64RegClass;
2442 else if (RegVT == MVT::i1)
2443 RC = &X86::VK1RegClass;
2444 else if (RegVT == MVT::v8i1)
2445 RC = &X86::VK8RegClass;
2446 else if (RegVT == MVT::v16i1)
2447 RC = &X86::VK16RegClass;
2448 else if (RegVT == MVT::v32i1)
2449 RC = &X86::VK32RegClass;
2450 else if (RegVT == MVT::v64i1)
2451 RC = &X86::VK64RegClass;
2453 llvm_unreachable("Unknown argument type!");
2455 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2456 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2458 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2459 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2461 if (VA.getLocInfo() == CCValAssign::SExt)
2462 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2463 DAG.getValueType(VA.getValVT()));
2464 else if (VA.getLocInfo() == CCValAssign::ZExt)
2465 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2466 DAG.getValueType(VA.getValVT()));
2467 else if (VA.getLocInfo() == CCValAssign::BCvt)
2468 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2470 if (VA.isExtInLoc()) {
2471 // Handle MMX values passed in XMM regs.
2472 if (RegVT.isVector())
2473 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2475 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2478 assert(VA.isMemLoc());
2479 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2482 // If value is passed via pointer - do a load.
2483 if (VA.getLocInfo() == CCValAssign::Indirect)
2484 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2485 MachinePointerInfo(), false, false, false, 0);
2487 InVals.push_back(ArgValue);
2490 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2491 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2492 // The x86-64 ABIs require that for returning structs by value we copy
2493 // the sret argument into %rax/%eax (depending on ABI) for the return.
2494 // Win32 requires us to put the sret argument to %eax as well.
2495 // Save the argument into a virtual register so that we can access it
2496 // from the return points.
2497 if (Ins[i].Flags.isSRet()) {
2498 unsigned Reg = FuncInfo->getSRetReturnReg();
2500 MVT PtrTy = getPointerTy();
2501 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2502 FuncInfo->setSRetReturnReg(Reg);
2504 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2505 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2511 unsigned StackSize = CCInfo.getNextStackOffset();
2512 // Align stack specially for tail calls.
2513 if (FuncIsMadeTailCallSafe(CallConv,
2514 MF.getTarget().Options.GuaranteedTailCallOpt))
2515 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2517 // If the function takes variable number of arguments, make a frame index for
2518 // the start of the first vararg value... for expansion of llvm.va_start. We
2519 // can skip this if there are no va_start calls.
2520 if (MFI->hasVAStart() &&
2521 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2522 CallConv != CallingConv::X86_ThisCall))) {
2523 FuncInfo->setVarArgsFrameIndex(
2524 MFI->CreateFixedObject(1, StackSize, true));
2527 // 64-bit calling conventions support varargs and register parameters, so we
2528 // have to do extra work to spill them in the prologue or forward them to
2530 if (Is64Bit && isVarArg &&
2531 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2532 // Find the first unallocated argument registers.
2533 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2534 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2535 unsigned NumIntRegs =
2536 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2537 unsigned NumXMMRegs =
2538 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2539 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2540 "SSE register cannot be used when SSE is disabled!");
2542 // Gather all the live in physical registers.
2543 SmallVector<SDValue, 6> LiveGPRs;
2544 SmallVector<SDValue, 8> LiveXMMRegs;
2546 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2547 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2549 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2551 if (!ArgXMMs.empty()) {
2552 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2553 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2554 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2555 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2556 LiveXMMRegs.push_back(
2557 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2561 // Store them to the va_list returned by va_start.
2562 if (MFI->hasVAStart()) {
2564 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2565 // Get to the caller-allocated home save location. Add 8 to account
2566 // for the return address.
2567 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2568 FuncInfo->setRegSaveFrameIndex(
2569 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2570 // Fixup to set vararg frame on shadow area (4 x i64).
2572 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2574 // For X86-64, if there are vararg parameters that are passed via
2575 // registers, then we must store them to their spots on the stack so
2576 // they may be loaded by deferencing the result of va_next.
2577 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2578 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2579 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2580 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2583 // Store the integer parameter registers.
2584 SmallVector<SDValue, 8> MemOps;
2585 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2587 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2588 for (SDValue Val : LiveGPRs) {
2589 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2590 DAG.getIntPtrConstant(Offset));
2592 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2593 MachinePointerInfo::getFixedStack(
2594 FuncInfo->getRegSaveFrameIndex(), Offset),
2596 MemOps.push_back(Store);
2600 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2601 // Now store the XMM (fp + vector) parameter registers.
2602 SmallVector<SDValue, 12> SaveXMMOps;
2603 SaveXMMOps.push_back(Chain);
2604 SaveXMMOps.push_back(ALVal);
2605 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2606 FuncInfo->getRegSaveFrameIndex()));
2607 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2608 FuncInfo->getVarArgsFPOffset()));
2609 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2611 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2612 MVT::Other, SaveXMMOps));
2615 if (!MemOps.empty())
2616 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2618 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2619 // to the liveout set on a musttail call.
2620 assert(MFI->hasMustTailInVarArgFunc());
2621 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2622 typedef X86MachineFunctionInfo::Forward Forward;
2624 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2626 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2627 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2628 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2631 if (!ArgXMMs.empty()) {
2633 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2634 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2635 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2637 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2639 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2640 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2642 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2648 // Some CCs need callee pop.
2649 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2650 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2651 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2653 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2654 // If this is an sret function, the return should pop the hidden pointer.
2655 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2656 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2657 argsAreStructReturn(Ins) == StackStructReturn)
2658 FuncInfo->setBytesToPopOnReturn(4);
2662 // RegSaveFrameIndex is X86-64 only.
2663 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2664 if (CallConv == CallingConv::X86_FastCall ||
2665 CallConv == CallingConv::X86_ThisCall)
2666 // fastcc functions can't have varargs.
2667 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2670 FuncInfo->setArgumentStackSize(StackSize);
2676 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2677 SDValue StackPtr, SDValue Arg,
2678 SDLoc dl, SelectionDAG &DAG,
2679 const CCValAssign &VA,
2680 ISD::ArgFlagsTy Flags) const {
2681 unsigned LocMemOffset = VA.getLocMemOffset();
2682 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2683 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2684 if (Flags.isByVal())
2685 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2687 return DAG.getStore(Chain, dl, Arg, PtrOff,
2688 MachinePointerInfo::getStack(LocMemOffset),
2692 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2693 /// optimization is performed and it is required.
2695 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2696 SDValue &OutRetAddr, SDValue Chain,
2697 bool IsTailCall, bool Is64Bit,
2698 int FPDiff, SDLoc dl) const {
2699 // Adjust the Return address stack slot.
2700 EVT VT = getPointerTy();
2701 OutRetAddr = getReturnAddressFrameIndex(DAG);
2703 // Load the "old" Return address.
2704 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2705 false, false, false, 0);
2706 return SDValue(OutRetAddr.getNode(), 1);
2709 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2710 /// optimization is performed and it is required (FPDiff!=0).
2711 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2712 SDValue Chain, SDValue RetAddrFrIdx,
2713 EVT PtrVT, unsigned SlotSize,
2714 int FPDiff, SDLoc dl) {
2715 // Store the return address to the appropriate stack slot.
2716 if (!FPDiff) return Chain;
2717 // Calculate the new stack slot for the return address.
2718 int NewReturnAddrFI =
2719 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2721 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2722 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2723 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2729 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2730 SmallVectorImpl<SDValue> &InVals) const {
2731 SelectionDAG &DAG = CLI.DAG;
2733 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2734 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2735 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2736 SDValue Chain = CLI.Chain;
2737 SDValue Callee = CLI.Callee;
2738 CallingConv::ID CallConv = CLI.CallConv;
2739 bool &isTailCall = CLI.IsTailCall;
2740 bool isVarArg = CLI.IsVarArg;
2742 MachineFunction &MF = DAG.getMachineFunction();
2743 bool Is64Bit = Subtarget->is64Bit();
2744 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2745 StructReturnType SR = callIsStructReturn(Outs);
2746 bool IsSibcall = false;
2747 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2749 if (MF.getTarget().Options.DisableTailCalls)
2752 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2754 // Force this to be a tail call. The verifier rules are enough to ensure
2755 // that we can lower this successfully without moving the return address
2758 } else if (isTailCall) {
2759 // Check if it's really possible to do a tail call.
2760 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2761 isVarArg, SR != NotStructReturn,
2762 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2763 Outs, OutVals, Ins, DAG);
2765 // Sibcalls are automatically detected tailcalls which do not require
2767 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2774 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2775 "Var args not supported with calling convention fastcc, ghc or hipe");
2777 // Analyze operands of the call, assigning locations to each operand.
2778 SmallVector<CCValAssign, 16> ArgLocs;
2779 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2781 // Allocate shadow area for Win64
2783 CCInfo.AllocateStack(32, 8);
2785 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2787 // Get a count of how many bytes are to be pushed on the stack.
2788 unsigned NumBytes = CCInfo.getNextStackOffset();
2790 // This is a sibcall. The memory operands are available in caller's
2791 // own caller's stack.
2793 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2794 IsTailCallConvention(CallConv))
2795 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2798 if (isTailCall && !IsSibcall && !IsMustTail) {
2799 // Lower arguments at fp - stackoffset + fpdiff.
2800 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2802 FPDiff = NumBytesCallerPushed - NumBytes;
2804 // Set the delta of movement of the returnaddr stackslot.
2805 // But only set if delta is greater than previous delta.
2806 if (FPDiff < X86Info->getTCReturnAddrDelta())
2807 X86Info->setTCReturnAddrDelta(FPDiff);
2810 unsigned NumBytesToPush = NumBytes;
2811 unsigned NumBytesToPop = NumBytes;
2813 // If we have an inalloca argument, all stack space has already been allocated
2814 // for us and be right at the top of the stack. We don't support multiple
2815 // arguments passed in memory when using inalloca.
2816 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2818 if (!ArgLocs.back().isMemLoc())
2819 report_fatal_error("cannot use inalloca attribute on a register "
2821 if (ArgLocs.back().getLocMemOffset() != 0)
2822 report_fatal_error("any parameter with the inalloca attribute must be "
2823 "the only memory argument");
2827 Chain = DAG.getCALLSEQ_START(
2828 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2830 SDValue RetAddrFrIdx;
2831 // Load return address for tail calls.
2832 if (isTailCall && FPDiff)
2833 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2834 Is64Bit, FPDiff, dl);
2836 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2837 SmallVector<SDValue, 8> MemOpChains;
2840 // Walk the register/memloc assignments, inserting copies/loads. In the case
2841 // of tail call optimization arguments are handle later.
2842 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2843 DAG.getSubtarget().getRegisterInfo());
2844 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2845 // Skip inalloca arguments, they have already been written.
2846 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2847 if (Flags.isInAlloca())
2850 CCValAssign &VA = ArgLocs[i];
2851 EVT RegVT = VA.getLocVT();
2852 SDValue Arg = OutVals[i];
2853 bool isByVal = Flags.isByVal();
2855 // Promote the value if needed.
2856 switch (VA.getLocInfo()) {
2857 default: llvm_unreachable("Unknown loc info!");
2858 case CCValAssign::Full: break;
2859 case CCValAssign::SExt:
2860 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2862 case CCValAssign::ZExt:
2863 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2865 case CCValAssign::AExt:
2866 if (RegVT.is128BitVector()) {
2867 // Special case: passing MMX values in XMM registers.
2868 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2869 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2870 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2872 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2874 case CCValAssign::BCvt:
2875 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2877 case CCValAssign::Indirect: {
2878 // Store the argument.
2879 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2880 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2881 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2882 MachinePointerInfo::getFixedStack(FI),
2889 if (VA.isRegLoc()) {
2890 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2891 if (isVarArg && IsWin64) {
2892 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2893 // shadow reg if callee is a varargs function.
2894 unsigned ShadowReg = 0;
2895 switch (VA.getLocReg()) {
2896 case X86::XMM0: ShadowReg = X86::RCX; break;
2897 case X86::XMM1: ShadowReg = X86::RDX; break;
2898 case X86::XMM2: ShadowReg = X86::R8; break;
2899 case X86::XMM3: ShadowReg = X86::R9; break;
2902 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2904 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2905 assert(VA.isMemLoc());
2906 if (!StackPtr.getNode())
2907 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2909 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2910 dl, DAG, VA, Flags));
2914 if (!MemOpChains.empty())
2915 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2917 if (Subtarget->isPICStyleGOT()) {
2918 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2921 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2922 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2924 // If we are tail calling and generating PIC/GOT style code load the
2925 // address of the callee into ECX. The value in ecx is used as target of
2926 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2927 // for tail calls on PIC/GOT architectures. Normally we would just put the
2928 // address of GOT into ebx and then call target@PLT. But for tail calls
2929 // ebx would be restored (since ebx is callee saved) before jumping to the
2932 // Note: The actual moving to ECX is done further down.
2933 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2934 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2935 !G->getGlobal()->hasProtectedVisibility())
2936 Callee = LowerGlobalAddress(Callee, DAG);
2937 else if (isa<ExternalSymbolSDNode>(Callee))
2938 Callee = LowerExternalSymbol(Callee, DAG);
2942 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2943 // From AMD64 ABI document:
2944 // For calls that may call functions that use varargs or stdargs
2945 // (prototype-less calls or calls to functions containing ellipsis (...) in
2946 // the declaration) %al is used as hidden argument to specify the number
2947 // of SSE registers used. The contents of %al do not need to match exactly
2948 // the number of registers, but must be an ubound on the number of SSE
2949 // registers used and is in the range 0 - 8 inclusive.
2951 // Count the number of XMM registers allocated.
2952 static const MCPhysReg XMMArgRegs[] = {
2953 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2954 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2956 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2957 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2958 && "SSE registers cannot be used when SSE is disabled");
2960 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2961 DAG.getConstant(NumXMMRegs, MVT::i8)));
2964 if (Is64Bit && isVarArg && IsMustTail) {
2965 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2966 for (const auto &F : Forwards) {
2967 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2968 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2972 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2973 // don't need this because the eligibility check rejects calls that require
2974 // shuffling arguments passed in memory.
2975 if (!IsSibcall && isTailCall) {
2976 // Force all the incoming stack arguments to be loaded from the stack
2977 // before any new outgoing arguments are stored to the stack, because the
2978 // outgoing stack slots may alias the incoming argument stack slots, and
2979 // the alias isn't otherwise explicit. This is slightly more conservative
2980 // than necessary, because it means that each store effectively depends
2981 // on every argument instead of just those arguments it would clobber.
2982 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2984 SmallVector<SDValue, 8> MemOpChains2;
2987 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2988 CCValAssign &VA = ArgLocs[i];
2991 assert(VA.isMemLoc());
2992 SDValue Arg = OutVals[i];
2993 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2994 // Skip inalloca arguments. They don't require any work.
2995 if (Flags.isInAlloca())
2997 // Create frame index.
2998 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2999 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3000 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3001 FIN = DAG.getFrameIndex(FI, getPointerTy());
3003 if (Flags.isByVal()) {
3004 // Copy relative to framepointer.
3005 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3006 if (!StackPtr.getNode())
3007 StackPtr = DAG.getCopyFromReg(Chain, dl,
3008 RegInfo->getStackRegister(),
3010 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3012 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3016 // Store relative to framepointer.
3017 MemOpChains2.push_back(
3018 DAG.getStore(ArgChain, dl, Arg, FIN,
3019 MachinePointerInfo::getFixedStack(FI),
3024 if (!MemOpChains2.empty())
3025 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3027 // Store the return address to the appropriate stack slot.
3028 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3029 getPointerTy(), RegInfo->getSlotSize(),
3033 // Build a sequence of copy-to-reg nodes chained together with token chain
3034 // and flag operands which copy the outgoing args into registers.
3036 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3037 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3038 RegsToPass[i].second, InFlag);
3039 InFlag = Chain.getValue(1);
3042 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3043 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3044 // In the 64-bit large code model, we have to make all calls
3045 // through a register, since the call instruction's 32-bit
3046 // pc-relative offset may not be large enough to hold the whole
3048 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3049 // If the callee is a GlobalAddress node (quite common, every direct call
3050 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3053 // We should use extra load for direct calls to dllimported functions in
3055 const GlobalValue *GV = G->getGlobal();
3056 if (!GV->hasDLLImportStorageClass()) {
3057 unsigned char OpFlags = 0;
3058 bool ExtraLoad = false;
3059 unsigned WrapperKind = ISD::DELETED_NODE;
3061 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3062 // external symbols most go through the PLT in PIC mode. If the symbol
3063 // has hidden or protected visibility, or if it is static or local, then
3064 // we don't need to use the PLT - we can directly call it.
3065 if (Subtarget->isTargetELF() &&
3066 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3067 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3068 OpFlags = X86II::MO_PLT;
3069 } else if (Subtarget->isPICStyleStubAny() &&
3070 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3071 (!Subtarget->getTargetTriple().isMacOSX() ||
3072 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3073 // PC-relative references to external symbols should go through $stub,
3074 // unless we're building with the leopard linker or later, which
3075 // automatically synthesizes these stubs.
3076 OpFlags = X86II::MO_DARWIN_STUB;
3077 } else if (Subtarget->isPICStyleRIPRel() &&
3078 isa<Function>(GV) &&
3079 cast<Function>(GV)->getAttributes().
3080 hasAttribute(AttributeSet::FunctionIndex,
3081 Attribute::NonLazyBind)) {
3082 // If the function is marked as non-lazy, generate an indirect call
3083 // which loads from the GOT directly. This avoids runtime overhead
3084 // at the cost of eager binding (and one extra byte of encoding).
3085 OpFlags = X86II::MO_GOTPCREL;
3086 WrapperKind = X86ISD::WrapperRIP;
3090 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3091 G->getOffset(), OpFlags);
3093 // Add a wrapper if needed.
3094 if (WrapperKind != ISD::DELETED_NODE)
3095 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3096 // Add extra indirection if needed.
3098 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3099 MachinePointerInfo::getGOT(),
3100 false, false, false, 0);
3102 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3103 unsigned char OpFlags = 0;
3105 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3106 // external symbols should go through the PLT.
3107 if (Subtarget->isTargetELF() &&
3108 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3109 OpFlags = X86II::MO_PLT;
3110 } else if (Subtarget->isPICStyleStubAny() &&
3111 (!Subtarget->getTargetTriple().isMacOSX() ||
3112 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3113 // PC-relative references to external symbols should go through $stub,
3114 // unless we're building with the leopard linker or later, which
3115 // automatically synthesizes these stubs.
3116 OpFlags = X86II::MO_DARWIN_STUB;
3119 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3121 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3122 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3123 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3126 // Returns a chain & a flag for retval copy to use.
3127 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3128 SmallVector<SDValue, 8> Ops;
3130 if (!IsSibcall && isTailCall) {
3131 Chain = DAG.getCALLSEQ_END(Chain,
3132 DAG.getIntPtrConstant(NumBytesToPop, true),
3133 DAG.getIntPtrConstant(0, true), InFlag, dl);
3134 InFlag = Chain.getValue(1);
3137 Ops.push_back(Chain);
3138 Ops.push_back(Callee);
3141 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3143 // Add argument registers to the end of the list so that they are known live
3145 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3146 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3147 RegsToPass[i].second.getValueType()));
3149 // Add a register mask operand representing the call-preserved registers.
3150 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3151 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3152 assert(Mask && "Missing call preserved mask for calling convention");
3153 Ops.push_back(DAG.getRegisterMask(Mask));
3155 if (InFlag.getNode())
3156 Ops.push_back(InFlag);
3160 //// If this is the first return lowered for this function, add the regs
3161 //// to the liveout set for the function.
3162 // This isn't right, although it's probably harmless on x86; liveouts
3163 // should be computed from returns not tail calls. Consider a void
3164 // function making a tail call to a function returning int.
3165 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3168 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3169 InFlag = Chain.getValue(1);
3171 // Create the CALLSEQ_END node.
3172 unsigned NumBytesForCalleeToPop;
3173 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3174 DAG.getTarget().Options.GuaranteedTailCallOpt))
3175 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3176 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3177 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3178 SR == StackStructReturn)
3179 // If this is a call to a struct-return function, the callee
3180 // pops the hidden struct pointer, so we have to push it back.
3181 // This is common for Darwin/X86, Linux & Mingw32 targets.
3182 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3183 NumBytesForCalleeToPop = 4;
3185 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3187 // Returns a flag for retval copy to use.
3189 Chain = DAG.getCALLSEQ_END(Chain,
3190 DAG.getIntPtrConstant(NumBytesToPop, true),
3191 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3194 InFlag = Chain.getValue(1);
3197 // Handle result values, copying them out of physregs into vregs that we
3199 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3200 Ins, dl, DAG, InVals);
3203 //===----------------------------------------------------------------------===//
3204 // Fast Calling Convention (tail call) implementation
3205 //===----------------------------------------------------------------------===//
3207 // Like std call, callee cleans arguments, convention except that ECX is
3208 // reserved for storing the tail called function address. Only 2 registers are
3209 // free for argument passing (inreg). Tail call optimization is performed
3211 // * tailcallopt is enabled
3212 // * caller/callee are fastcc
3213 // On X86_64 architecture with GOT-style position independent code only local
3214 // (within module) calls are supported at the moment.
3215 // To keep the stack aligned according to platform abi the function
3216 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3217 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3218 // If a tail called function callee has more arguments than the caller the
3219 // caller needs to make sure that there is room to move the RETADDR to. This is
3220 // achieved by reserving an area the size of the argument delta right after the
3221 // original RETADDR, but before the saved framepointer or the spilled registers
3222 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3234 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3235 /// for a 16 byte align requirement.
3237 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3238 SelectionDAG& DAG) const {
3239 MachineFunction &MF = DAG.getMachineFunction();
3240 const TargetMachine &TM = MF.getTarget();
3241 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3242 TM.getSubtargetImpl()->getRegisterInfo());
3243 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3244 unsigned StackAlignment = TFI.getStackAlignment();
3245 uint64_t AlignMask = StackAlignment - 1;
3246 int64_t Offset = StackSize;
3247 unsigned SlotSize = RegInfo->getSlotSize();
3248 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3249 // Number smaller than 12 so just add the difference.
3250 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3252 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3253 Offset = ((~AlignMask) & Offset) + StackAlignment +
3254 (StackAlignment-SlotSize);
3259 /// MatchingStackOffset - Return true if the given stack call argument is
3260 /// already available in the same position (relatively) of the caller's
3261 /// incoming argument stack.
3263 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3264 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3265 const X86InstrInfo *TII) {
3266 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3268 if (Arg.getOpcode() == ISD::CopyFromReg) {
3269 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3270 if (!TargetRegisterInfo::isVirtualRegister(VR))
3272 MachineInstr *Def = MRI->getVRegDef(VR);
3275 if (!Flags.isByVal()) {
3276 if (!TII->isLoadFromStackSlot(Def, FI))
3279 unsigned Opcode = Def->getOpcode();
3280 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3281 Def->getOperand(1).isFI()) {
3282 FI = Def->getOperand(1).getIndex();
3283 Bytes = Flags.getByValSize();
3287 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3288 if (Flags.isByVal())
3289 // ByVal argument is passed in as a pointer but it's now being
3290 // dereferenced. e.g.
3291 // define @foo(%struct.X* %A) {
3292 // tail call @bar(%struct.X* byval %A)
3295 SDValue Ptr = Ld->getBasePtr();
3296 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3299 FI = FINode->getIndex();
3300 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3301 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3302 FI = FINode->getIndex();
3303 Bytes = Flags.getByValSize();
3307 assert(FI != INT_MAX);
3308 if (!MFI->isFixedObjectIndex(FI))
3310 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3313 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3314 /// for tail call optimization. Targets which want to do tail call
3315 /// optimization should implement this function.
3317 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3318 CallingConv::ID CalleeCC,
3320 bool isCalleeStructRet,
3321 bool isCallerStructRet,
3323 const SmallVectorImpl<ISD::OutputArg> &Outs,
3324 const SmallVectorImpl<SDValue> &OutVals,
3325 const SmallVectorImpl<ISD::InputArg> &Ins,
3326 SelectionDAG &DAG) const {
3327 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3330 // If -tailcallopt is specified, make fastcc functions tail-callable.
3331 const MachineFunction &MF = DAG.getMachineFunction();
3332 const Function *CallerF = MF.getFunction();
3334 // If the function return type is x86_fp80 and the callee return type is not,
3335 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3336 // perform a tailcall optimization here.
3337 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3340 CallingConv::ID CallerCC = CallerF->getCallingConv();
3341 bool CCMatch = CallerCC == CalleeCC;
3342 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3343 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3345 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3346 if (IsTailCallConvention(CalleeCC) && CCMatch)
3351 // Look for obvious safe cases to perform tail call optimization that do not
3352 // require ABI changes. This is what gcc calls sibcall.
3354 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3355 // emit a special epilogue.
3356 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3357 DAG.getSubtarget().getRegisterInfo());
3358 if (RegInfo->needsStackRealignment(MF))
3361 // Also avoid sibcall optimization if either caller or callee uses struct
3362 // return semantics.
3363 if (isCalleeStructRet || isCallerStructRet)
3366 // An stdcall/thiscall caller is expected to clean up its arguments; the
3367 // callee isn't going to do that.
3368 // FIXME: this is more restrictive than needed. We could produce a tailcall
3369 // when the stack adjustment matches. For example, with a thiscall that takes
3370 // only one argument.
3371 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3372 CallerCC == CallingConv::X86_ThisCall))
3375 // Do not sibcall optimize vararg calls unless all arguments are passed via
3377 if (isVarArg && !Outs.empty()) {
3379 // Optimizing for varargs on Win64 is unlikely to be safe without
3380 // additional testing.
3381 if (IsCalleeWin64 || IsCallerWin64)
3384 SmallVector<CCValAssign, 16> ArgLocs;
3385 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3388 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3389 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3390 if (!ArgLocs[i].isRegLoc())
3394 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3395 // stack. Therefore, if it's not used by the call it is not safe to optimize
3396 // this into a sibcall.
3397 bool Unused = false;
3398 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3405 SmallVector<CCValAssign, 16> RVLocs;
3406 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3408 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3409 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3410 CCValAssign &VA = RVLocs[i];
3411 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3416 // If the calling conventions do not match, then we'd better make sure the
3417 // results are returned in the same way as what the caller expects.
3419 SmallVector<CCValAssign, 16> RVLocs1;
3420 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3422 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3424 SmallVector<CCValAssign, 16> RVLocs2;
3425 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3427 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3429 if (RVLocs1.size() != RVLocs2.size())
3431 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3432 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3434 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3436 if (RVLocs1[i].isRegLoc()) {
3437 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3440 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3446 // If the callee takes no arguments then go on to check the results of the
3448 if (!Outs.empty()) {
3449 // Check if stack adjustment is needed. For now, do not do this if any
3450 // argument is passed on the stack.
3451 SmallVector<CCValAssign, 16> ArgLocs;
3452 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3455 // Allocate shadow area for Win64
3457 CCInfo.AllocateStack(32, 8);
3459 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3460 if (CCInfo.getNextStackOffset()) {
3461 MachineFunction &MF = DAG.getMachineFunction();
3462 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3465 // Check if the arguments are already laid out in the right way as
3466 // the caller's fixed stack objects.
3467 MachineFrameInfo *MFI = MF.getFrameInfo();
3468 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3469 const X86InstrInfo *TII =
3470 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3471 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3472 CCValAssign &VA = ArgLocs[i];
3473 SDValue Arg = OutVals[i];
3474 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3475 if (VA.getLocInfo() == CCValAssign::Indirect)
3477 if (!VA.isRegLoc()) {
3478 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3485 // If the tailcall address may be in a register, then make sure it's
3486 // possible to register allocate for it. In 32-bit, the call address can
3487 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3488 // callee-saved registers are restored. These happen to be the same
3489 // registers used to pass 'inreg' arguments so watch out for those.
3490 if (!Subtarget->is64Bit() &&
3491 ((!isa<GlobalAddressSDNode>(Callee) &&
3492 !isa<ExternalSymbolSDNode>(Callee)) ||
3493 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3494 unsigned NumInRegs = 0;
3495 // In PIC we need an extra register to formulate the address computation
3497 unsigned MaxInRegs =
3498 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3500 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3501 CCValAssign &VA = ArgLocs[i];
3504 unsigned Reg = VA.getLocReg();
3507 case X86::EAX: case X86::EDX: case X86::ECX:
3508 if (++NumInRegs == MaxInRegs)
3520 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3521 const TargetLibraryInfo *libInfo) const {
3522 return X86::createFastISel(funcInfo, libInfo);
3525 //===----------------------------------------------------------------------===//
3526 // Other Lowering Hooks
3527 //===----------------------------------------------------------------------===//
3529 static bool MayFoldLoad(SDValue Op) {
3530 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3533 static bool MayFoldIntoStore(SDValue Op) {
3534 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3537 static bool isTargetShuffle(unsigned Opcode) {
3539 default: return false;
3540 case X86ISD::BLENDI:
3541 case X86ISD::PSHUFB:
3542 case X86ISD::PSHUFD:
3543 case X86ISD::PSHUFHW:
3544 case X86ISD::PSHUFLW:
3546 case X86ISD::PALIGNR:
3547 case X86ISD::MOVLHPS:
3548 case X86ISD::MOVLHPD:
3549 case X86ISD::MOVHLPS:
3550 case X86ISD::MOVLPS:
3551 case X86ISD::MOVLPD:
3552 case X86ISD::MOVSHDUP:
3553 case X86ISD::MOVSLDUP:
3554 case X86ISD::MOVDDUP:
3557 case X86ISD::UNPCKL:
3558 case X86ISD::UNPCKH:
3559 case X86ISD::VPERMILPI:
3560 case X86ISD::VPERM2X128:
3561 case X86ISD::VPERMI:
3566 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3567 SDValue V1, SelectionDAG &DAG) {
3569 default: llvm_unreachable("Unknown x86 shuffle node");
3570 case X86ISD::MOVSHDUP:
3571 case X86ISD::MOVSLDUP:
3572 case X86ISD::MOVDDUP:
3573 return DAG.getNode(Opc, dl, VT, V1);
3577 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3578 SDValue V1, unsigned TargetMask,
3579 SelectionDAG &DAG) {
3581 default: llvm_unreachable("Unknown x86 shuffle node");
3582 case X86ISD::PSHUFD:
3583 case X86ISD::PSHUFHW:
3584 case X86ISD::PSHUFLW:
3585 case X86ISD::VPERMILPI:
3586 case X86ISD::VPERMI:
3587 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3591 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3592 SDValue V1, SDValue V2, unsigned TargetMask,
3593 SelectionDAG &DAG) {
3595 default: llvm_unreachable("Unknown x86 shuffle node");
3596 case X86ISD::PALIGNR:
3597 case X86ISD::VALIGN:
3599 case X86ISD::VPERM2X128:
3600 return DAG.getNode(Opc, dl, VT, V1, V2,
3601 DAG.getConstant(TargetMask, MVT::i8));
3605 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3606 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3608 default: llvm_unreachable("Unknown x86 shuffle node");
3609 case X86ISD::MOVLHPS:
3610 case X86ISD::MOVLHPD:
3611 case X86ISD::MOVHLPS:
3612 case X86ISD::MOVLPS:
3613 case X86ISD::MOVLPD:
3616 case X86ISD::UNPCKL:
3617 case X86ISD::UNPCKH:
3618 return DAG.getNode(Opc, dl, VT, V1, V2);
3622 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3623 MachineFunction &MF = DAG.getMachineFunction();
3624 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3625 DAG.getSubtarget().getRegisterInfo());
3626 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3627 int ReturnAddrIndex = FuncInfo->getRAIndex();
3629 if (ReturnAddrIndex == 0) {
3630 // Set up a frame object for the return address.
3631 unsigned SlotSize = RegInfo->getSlotSize();
3632 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3635 FuncInfo->setRAIndex(ReturnAddrIndex);
3638 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3641 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3642 bool hasSymbolicDisplacement) {
3643 // Offset should fit into 32 bit immediate field.
3644 if (!isInt<32>(Offset))
3647 // If we don't have a symbolic displacement - we don't have any extra
3649 if (!hasSymbolicDisplacement)
3652 // FIXME: Some tweaks might be needed for medium code model.
3653 if (M != CodeModel::Small && M != CodeModel::Kernel)
3656 // For small code model we assume that latest object is 16MB before end of 31
3657 // bits boundary. We may also accept pretty large negative constants knowing
3658 // that all objects are in the positive half of address space.
3659 if (M == CodeModel::Small && Offset < 16*1024*1024)
3662 // For kernel code model we know that all object resist in the negative half
3663 // of 32bits address space. We may not accept negative offsets, since they may
3664 // be just off and we may accept pretty large positive ones.
3665 if (M == CodeModel::Kernel && Offset > 0)
3671 /// isCalleePop - Determines whether the callee is required to pop its
3672 /// own arguments. Callee pop is necessary to support tail calls.
3673 bool X86::isCalleePop(CallingConv::ID CallingConv,
3674 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3675 switch (CallingConv) {
3678 case CallingConv::X86_StdCall:
3679 case CallingConv::X86_FastCall:
3680 case CallingConv::X86_ThisCall:
3682 case CallingConv::Fast:
3683 case CallingConv::GHC:
3684 case CallingConv::HiPE:
3691 /// \brief Return true if the condition is an unsigned comparison operation.
3692 static bool isX86CCUnsigned(unsigned X86CC) {
3694 default: llvm_unreachable("Invalid integer condition!");
3695 case X86::COND_E: return true;
3696 case X86::COND_G: return false;
3697 case X86::COND_GE: return false;
3698 case X86::COND_L: return false;
3699 case X86::COND_LE: return false;
3700 case X86::COND_NE: return true;
3701 case X86::COND_B: return true;
3702 case X86::COND_A: return true;
3703 case X86::COND_BE: return true;
3704 case X86::COND_AE: return true;
3706 llvm_unreachable("covered switch fell through?!");
3709 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3710 /// specific condition code, returning the condition code and the LHS/RHS of the
3711 /// comparison to make.
3712 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3713 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3715 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3716 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3717 // X > -1 -> X == 0, jump !sign.
3718 RHS = DAG.getConstant(0, RHS.getValueType());
3719 return X86::COND_NS;
3721 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3722 // X < 0 -> X == 0, jump on sign.
3725 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3727 RHS = DAG.getConstant(0, RHS.getValueType());
3728 return X86::COND_LE;
3732 switch (SetCCOpcode) {
3733 default: llvm_unreachable("Invalid integer condition!");
3734 case ISD::SETEQ: return X86::COND_E;
3735 case ISD::SETGT: return X86::COND_G;
3736 case ISD::SETGE: return X86::COND_GE;
3737 case ISD::SETLT: return X86::COND_L;
3738 case ISD::SETLE: return X86::COND_LE;
3739 case ISD::SETNE: return X86::COND_NE;
3740 case ISD::SETULT: return X86::COND_B;
3741 case ISD::SETUGT: return X86::COND_A;
3742 case ISD::SETULE: return X86::COND_BE;
3743 case ISD::SETUGE: return X86::COND_AE;
3747 // First determine if it is required or is profitable to flip the operands.
3749 // If LHS is a foldable load, but RHS is not, flip the condition.
3750 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3751 !ISD::isNON_EXTLoad(RHS.getNode())) {
3752 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3753 std::swap(LHS, RHS);
3756 switch (SetCCOpcode) {
3762 std::swap(LHS, RHS);
3766 // On a floating point condition, the flags are set as follows:
3768 // 0 | 0 | 0 | X > Y
3769 // 0 | 0 | 1 | X < Y
3770 // 1 | 0 | 0 | X == Y
3771 // 1 | 1 | 1 | unordered
3772 switch (SetCCOpcode) {
3773 default: llvm_unreachable("Condcode should be pre-legalized away");
3775 case ISD::SETEQ: return X86::COND_E;
3776 case ISD::SETOLT: // flipped
3778 case ISD::SETGT: return X86::COND_A;
3779 case ISD::SETOLE: // flipped
3781 case ISD::SETGE: return X86::COND_AE;
3782 case ISD::SETUGT: // flipped
3784 case ISD::SETLT: return X86::COND_B;
3785 case ISD::SETUGE: // flipped
3787 case ISD::SETLE: return X86::COND_BE;
3789 case ISD::SETNE: return X86::COND_NE;
3790 case ISD::SETUO: return X86::COND_P;
3791 case ISD::SETO: return X86::COND_NP;
3793 case ISD::SETUNE: return X86::COND_INVALID;
3797 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3798 /// code. Current x86 isa includes the following FP cmov instructions:
3799 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3800 static bool hasFPCMov(unsigned X86CC) {
3816 /// isFPImmLegal - Returns true if the target can instruction select the
3817 /// specified FP immediate natively. If false, the legalizer will
3818 /// materialize the FP immediate as a load from a constant pool.
3819 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3820 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3821 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3827 /// \brief Returns true if it is beneficial to convert a load of a constant
3828 /// to just the constant itself.
3829 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3831 assert(Ty->isIntegerTy());
3833 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3834 if (BitSize == 0 || BitSize > 64)
3839 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3840 /// the specified range (L, H].
3841 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3842 return (Val < 0) || (Val >= Low && Val < Hi);
3845 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3846 /// specified value.
3847 static bool isUndefOrEqual(int Val, int CmpVal) {
3848 return (Val < 0 || Val == CmpVal);
3851 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3852 /// from position Pos and ending in Pos+Size, falls within the specified
3853 /// sequential range (L, L+Pos]. or is undef.
3854 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3855 unsigned Pos, unsigned Size, int Low) {
3856 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3857 if (!isUndefOrEqual(Mask[i], Low))
3862 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3863 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3864 /// operand - by default will match for first operand.
3865 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3866 bool TestSecondOperand = false) {
3867 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3868 VT != MVT::v2f64 && VT != MVT::v2i64)
3871 unsigned NumElems = VT.getVectorNumElements();
3872 unsigned Lo = TestSecondOperand ? NumElems : 0;
3873 unsigned Hi = Lo + NumElems;
3875 for (unsigned i = 0; i < NumElems; ++i)
3876 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3882 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3883 /// is suitable for input to PSHUFHW.
3884 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3885 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3888 // Lower quadword copied in order or undef.
3889 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3892 // Upper quadword shuffled.
3893 for (unsigned i = 4; i != 8; ++i)
3894 if (!isUndefOrInRange(Mask[i], 4, 8))
3897 if (VT == MVT::v16i16) {
3898 // Lower quadword copied in order or undef.
3899 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3902 // Upper quadword shuffled.
3903 for (unsigned i = 12; i != 16; ++i)
3904 if (!isUndefOrInRange(Mask[i], 12, 16))
3911 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3912 /// is suitable for input to PSHUFLW.
3913 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3914 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3917 // Upper quadword copied in order.
3918 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3921 // Lower quadword shuffled.
3922 for (unsigned i = 0; i != 4; ++i)
3923 if (!isUndefOrInRange(Mask[i], 0, 4))
3926 if (VT == MVT::v16i16) {
3927 // Upper quadword copied in order.
3928 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3931 // Lower quadword shuffled.
3932 for (unsigned i = 8; i != 12; ++i)
3933 if (!isUndefOrInRange(Mask[i], 8, 12))
3940 /// \brief Return true if the mask specifies a shuffle of elements that is
3941 /// suitable for input to intralane (palignr) or interlane (valign) vector
3943 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3944 unsigned NumElts = VT.getVectorNumElements();
3945 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3946 unsigned NumLaneElts = NumElts/NumLanes;
3948 // Do not handle 64-bit element shuffles with palignr.
3949 if (NumLaneElts == 2)
3952 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3954 for (i = 0; i != NumLaneElts; ++i) {
3959 // Lane is all undef, go to next lane
3960 if (i == NumLaneElts)
3963 int Start = Mask[i+l];
3965 // Make sure its in this lane in one of the sources
3966 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3967 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3970 // If not lane 0, then we must match lane 0
3971 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3974 // Correct second source to be contiguous with first source
3975 if (Start >= (int)NumElts)
3976 Start -= NumElts - NumLaneElts;
3978 // Make sure we're shifting in the right direction.
3979 if (Start <= (int)(i+l))
3984 // Check the rest of the elements to see if they are consecutive.
3985 for (++i; i != NumLaneElts; ++i) {
3986 int Idx = Mask[i+l];
3988 // Make sure its in this lane
3989 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3990 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3993 // If not lane 0, then we must match lane 0
3994 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3997 if (Idx >= (int)NumElts)
3998 Idx -= NumElts - NumLaneElts;
4000 if (!isUndefOrEqual(Idx, Start+i))
4009 /// \brief Return true if the node specifies a shuffle of elements that is
4010 /// suitable for input to PALIGNR.
4011 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4012 const X86Subtarget *Subtarget) {
4013 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4014 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4015 VT.is512BitVector())
4016 // FIXME: Add AVX512BW.
4019 return isAlignrMask(Mask, VT, false);
4022 /// \brief Return true if the node specifies a shuffle of elements that is
4023 /// suitable for input to VALIGN.
4024 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4025 const X86Subtarget *Subtarget) {
4026 // FIXME: Add AVX512VL.
4027 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4029 return isAlignrMask(Mask, VT, true);
4032 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4033 /// the two vector operands have swapped position.
4034 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4035 unsigned NumElems) {
4036 for (unsigned i = 0; i != NumElems; ++i) {
4040 else if (idx < (int)NumElems)
4041 Mask[i] = idx + NumElems;
4043 Mask[i] = idx - NumElems;
4047 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4048 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4049 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4050 /// reverse of what x86 shuffles want.
4051 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4053 unsigned NumElems = VT.getVectorNumElements();
4054 unsigned NumLanes = VT.getSizeInBits()/128;
4055 unsigned NumLaneElems = NumElems/NumLanes;
4057 if (NumLaneElems != 2 && NumLaneElems != 4)
4060 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4061 bool symetricMaskRequired =
4062 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4064 // VSHUFPSY divides the resulting vector into 4 chunks.
4065 // The sources are also splitted into 4 chunks, and each destination
4066 // chunk must come from a different source chunk.
4068 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4069 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4071 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4072 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4074 // VSHUFPDY divides the resulting vector into 4 chunks.
4075 // The sources are also splitted into 4 chunks, and each destination
4076 // chunk must come from a different source chunk.
4078 // SRC1 => X3 X2 X1 X0
4079 // SRC2 => Y3 Y2 Y1 Y0
4081 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4083 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4084 unsigned HalfLaneElems = NumLaneElems/2;
4085 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4086 for (unsigned i = 0; i != NumLaneElems; ++i) {
4087 int Idx = Mask[i+l];
4088 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4089 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4091 // For VSHUFPSY, the mask of the second half must be the same as the
4092 // first but with the appropriate offsets. This works in the same way as
4093 // VPERMILPS works with masks.
4094 if (!symetricMaskRequired || Idx < 0)
4096 if (MaskVal[i] < 0) {
4097 MaskVal[i] = Idx - l;
4100 if ((signed)(Idx - l) != MaskVal[i])
4108 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4109 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4110 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4111 if (!VT.is128BitVector())
4114 unsigned NumElems = VT.getVectorNumElements();
4119 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4120 return isUndefOrEqual(Mask[0], 6) &&
4121 isUndefOrEqual(Mask[1], 7) &&
4122 isUndefOrEqual(Mask[2], 2) &&
4123 isUndefOrEqual(Mask[3], 3);
4126 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4127 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4129 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4130 if (!VT.is128BitVector())
4133 unsigned NumElems = VT.getVectorNumElements();
4138 return isUndefOrEqual(Mask[0], 2) &&
4139 isUndefOrEqual(Mask[1], 3) &&
4140 isUndefOrEqual(Mask[2], 2) &&
4141 isUndefOrEqual(Mask[3], 3);
4144 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4145 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4146 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4147 if (!VT.is128BitVector())
4150 unsigned NumElems = VT.getVectorNumElements();
4152 if (NumElems != 2 && NumElems != 4)
4155 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4156 if (!isUndefOrEqual(Mask[i], i + NumElems))
4159 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4160 if (!isUndefOrEqual(Mask[i], i))
4166 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4167 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4168 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4169 if (!VT.is128BitVector())
4172 unsigned NumElems = VT.getVectorNumElements();
4174 if (NumElems != 2 && NumElems != 4)
4177 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4178 if (!isUndefOrEqual(Mask[i], i))
4181 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4182 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4188 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4189 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4190 /// i. e: If all but one element come from the same vector.
4191 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4192 // TODO: Deal with AVX's VINSERTPS
4193 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4196 unsigned CorrectPosV1 = 0;
4197 unsigned CorrectPosV2 = 0;
4198 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4199 if (Mask[i] == -1) {
4207 else if (Mask[i] == i + 4)
4211 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4212 // We have 3 elements (undefs count as elements from any vector) from one
4213 // vector, and one from another.
4220 // Some special combinations that can be optimized.
4223 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4224 SelectionDAG &DAG) {
4225 MVT VT = SVOp->getSimpleValueType(0);
4228 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4231 ArrayRef<int> Mask = SVOp->getMask();
4233 // These are the special masks that may be optimized.
4234 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4235 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4236 bool MatchEvenMask = true;
4237 bool MatchOddMask = true;
4238 for (int i=0; i<8; ++i) {
4239 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4240 MatchEvenMask = false;
4241 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4242 MatchOddMask = false;
4245 if (!MatchEvenMask && !MatchOddMask)
4248 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4250 SDValue Op0 = SVOp->getOperand(0);
4251 SDValue Op1 = SVOp->getOperand(1);
4253 if (MatchEvenMask) {
4254 // Shift the second operand right to 32 bits.
4255 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4256 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4258 // Shift the first operand left to 32 bits.
4259 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4260 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4262 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4263 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4266 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4267 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4268 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4269 bool HasInt256, bool V2IsSplat = false) {
4271 assert(VT.getSizeInBits() >= 128 &&
4272 "Unsupported vector type for unpckl");
4274 unsigned NumElts = VT.getVectorNumElements();
4275 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4276 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4279 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4280 "Unsupported vector type for unpckh");
4282 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4283 unsigned NumLanes = VT.getSizeInBits()/128;
4284 unsigned NumLaneElts = NumElts/NumLanes;
4286 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4287 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4288 int BitI = Mask[l+i];
4289 int BitI1 = Mask[l+i+1];
4290 if (!isUndefOrEqual(BitI, j))
4293 if (!isUndefOrEqual(BitI1, NumElts))
4296 if (!isUndefOrEqual(BitI1, j + NumElts))
4305 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4306 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4307 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4308 bool HasInt256, bool V2IsSplat = false) {
4309 assert(VT.getSizeInBits() >= 128 &&
4310 "Unsupported vector type for unpckh");
4312 unsigned NumElts = VT.getVectorNumElements();
4313 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4314 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4317 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4318 "Unsupported vector type for unpckh");
4320 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4321 unsigned NumLanes = VT.getSizeInBits()/128;
4322 unsigned NumLaneElts = NumElts/NumLanes;
4324 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4325 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4326 int BitI = Mask[l+i];
4327 int BitI1 = Mask[l+i+1];
4328 if (!isUndefOrEqual(BitI, j))
4331 if (isUndefOrEqual(BitI1, NumElts))
4334 if (!isUndefOrEqual(BitI1, j+NumElts))
4342 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4343 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4345 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4346 unsigned NumElts = VT.getVectorNumElements();
4347 bool Is256BitVec = VT.is256BitVector();
4349 if (VT.is512BitVector())
4351 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4352 "Unsupported vector type for unpckh");
4354 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4355 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4358 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4359 // FIXME: Need a better way to get rid of this, there's no latency difference
4360 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4361 // the former later. We should also remove the "_undef" special mask.
4362 if (NumElts == 4 && Is256BitVec)
4365 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4366 // independently on 128-bit lanes.
4367 unsigned NumLanes = VT.getSizeInBits()/128;
4368 unsigned NumLaneElts = NumElts/NumLanes;
4370 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4371 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4372 int BitI = Mask[l+i];
4373 int BitI1 = Mask[l+i+1];
4375 if (!isUndefOrEqual(BitI, j))
4377 if (!isUndefOrEqual(BitI1, j))
4385 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4386 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4388 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4389 unsigned NumElts = VT.getVectorNumElements();
4391 if (VT.is512BitVector())
4394 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4395 "Unsupported vector type for unpckh");
4397 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4398 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4401 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4402 // independently on 128-bit lanes.
4403 unsigned NumLanes = VT.getSizeInBits()/128;
4404 unsigned NumLaneElts = NumElts/NumLanes;
4406 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4407 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4408 int BitI = Mask[l+i];
4409 int BitI1 = Mask[l+i+1];
4410 if (!isUndefOrEqual(BitI, j))
4412 if (!isUndefOrEqual(BitI1, j))
4419 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4420 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4421 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4422 if (!VT.is512BitVector())
4425 unsigned NumElts = VT.getVectorNumElements();
4426 unsigned HalfSize = NumElts/2;
4427 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4428 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4433 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4434 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4442 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4443 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4444 /// MOVSD, and MOVD, i.e. setting the lowest element.
4445 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4446 if (VT.getVectorElementType().getSizeInBits() < 32)
4448 if (!VT.is128BitVector())
4451 unsigned NumElts = VT.getVectorNumElements();
4453 if (!isUndefOrEqual(Mask[0], NumElts))
4456 for (unsigned i = 1; i != NumElts; ++i)
4457 if (!isUndefOrEqual(Mask[i], i))
4463 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4464 /// as permutations between 128-bit chunks or halves. As an example: this
4466 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4467 /// The first half comes from the second half of V1 and the second half from the
4468 /// the second half of V2.
4469 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4470 if (!HasFp256 || !VT.is256BitVector())
4473 // The shuffle result is divided into half A and half B. In total the two
4474 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4475 // B must come from C, D, E or F.
4476 unsigned HalfSize = VT.getVectorNumElements()/2;
4477 bool MatchA = false, MatchB = false;
4479 // Check if A comes from one of C, D, E, F.
4480 for (unsigned Half = 0; Half != 4; ++Half) {
4481 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4487 // Check if B comes from one of C, D, E, F.
4488 for (unsigned Half = 0; Half != 4; ++Half) {
4489 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4495 return MatchA && MatchB;
4498 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4499 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4500 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4501 MVT VT = SVOp->getSimpleValueType(0);
4503 unsigned HalfSize = VT.getVectorNumElements()/2;
4505 unsigned FstHalf = 0, SndHalf = 0;
4506 for (unsigned i = 0; i < HalfSize; ++i) {
4507 if (SVOp->getMaskElt(i) > 0) {
4508 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4512 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4513 if (SVOp->getMaskElt(i) > 0) {
4514 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4519 return (FstHalf | (SndHalf << 4));
4522 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4523 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4524 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4528 unsigned NumElts = VT.getVectorNumElements();
4530 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4531 for (unsigned i = 0; i != NumElts; ++i) {
4534 Imm8 |= Mask[i] << (i*2);
4539 unsigned LaneSize = 4;
4540 SmallVector<int, 4> MaskVal(LaneSize, -1);
4542 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4543 for (unsigned i = 0; i != LaneSize; ++i) {
4544 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4548 if (MaskVal[i] < 0) {
4549 MaskVal[i] = Mask[i+l] - l;
4550 Imm8 |= MaskVal[i] << (i*2);
4553 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4560 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4561 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4562 /// Note that VPERMIL mask matching is different depending whether theunderlying
4563 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4564 /// to the same elements of the low, but to the higher half of the source.
4565 /// In VPERMILPD the two lanes could be shuffled independently of each other
4566 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4567 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4568 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4569 if (VT.getSizeInBits() < 256 || EltSize < 32)
4571 bool symetricMaskRequired = (EltSize == 32);
4572 unsigned NumElts = VT.getVectorNumElements();
4574 unsigned NumLanes = VT.getSizeInBits()/128;
4575 unsigned LaneSize = NumElts/NumLanes;
4576 // 2 or 4 elements in one lane
4578 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4579 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4580 for (unsigned i = 0; i != LaneSize; ++i) {
4581 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4583 if (symetricMaskRequired) {
4584 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4585 ExpectedMaskVal[i] = Mask[i+l] - l;
4588 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4596 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4597 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4598 /// element of vector 2 and the other elements to come from vector 1 in order.
4599 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4600 bool V2IsSplat = false, bool V2IsUndef = false) {
4601 if (!VT.is128BitVector())
4604 unsigned NumOps = VT.getVectorNumElements();
4605 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4608 if (!isUndefOrEqual(Mask[0], 0))
4611 for (unsigned i = 1; i != NumOps; ++i)
4612 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4613 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4614 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4620 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4621 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4622 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4623 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4624 const X86Subtarget *Subtarget) {
4625 if (!Subtarget->hasSSE3())
4628 unsigned NumElems = VT.getVectorNumElements();
4630 if ((VT.is128BitVector() && NumElems != 4) ||
4631 (VT.is256BitVector() && NumElems != 8) ||
4632 (VT.is512BitVector() && NumElems != 16))
4635 // "i+1" is the value the indexed mask element must have
4636 for (unsigned i = 0; i != NumElems; i += 2)
4637 if (!isUndefOrEqual(Mask[i], i+1) ||
4638 !isUndefOrEqual(Mask[i+1], i+1))
4644 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4645 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4646 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4647 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4648 const X86Subtarget *Subtarget) {
4649 if (!Subtarget->hasSSE3())
4652 unsigned NumElems = VT.getVectorNumElements();
4654 if ((VT.is128BitVector() && NumElems != 4) ||
4655 (VT.is256BitVector() && NumElems != 8) ||
4656 (VT.is512BitVector() && NumElems != 16))
4659 // "i" is the value the indexed mask element must have
4660 for (unsigned i = 0; i != NumElems; i += 2)
4661 if (!isUndefOrEqual(Mask[i], i) ||
4662 !isUndefOrEqual(Mask[i+1], i))
4668 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4669 /// specifies a shuffle of elements that is suitable for input to 256-bit
4670 /// version of MOVDDUP.
4671 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4672 if (!HasFp256 || !VT.is256BitVector())
4675 unsigned NumElts = VT.getVectorNumElements();
4679 for (unsigned i = 0; i != NumElts/2; ++i)
4680 if (!isUndefOrEqual(Mask[i], 0))
4682 for (unsigned i = NumElts/2; i != NumElts; ++i)
4683 if (!isUndefOrEqual(Mask[i], NumElts/2))
4688 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4689 /// specifies a shuffle of elements that is suitable for input to 128-bit
4690 /// version of MOVDDUP.
4691 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4692 if (!VT.is128BitVector())
4695 unsigned e = VT.getVectorNumElements() / 2;
4696 for (unsigned i = 0; i != e; ++i)
4697 if (!isUndefOrEqual(Mask[i], i))
4699 for (unsigned i = 0; i != e; ++i)
4700 if (!isUndefOrEqual(Mask[e+i], i))
4705 /// isVEXTRACTIndex - Return true if the specified
4706 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4707 /// suitable for instruction that extract 128 or 256 bit vectors
4708 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4709 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4710 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4713 // The index should be aligned on a vecWidth-bit boundary.
4715 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4717 MVT VT = N->getSimpleValueType(0);
4718 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4719 bool Result = (Index * ElSize) % vecWidth == 0;
4724 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4725 /// operand specifies a subvector insert that is suitable for input to
4726 /// insertion of 128 or 256-bit subvectors
4727 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4728 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4729 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4731 // The index should be aligned on a vecWidth-bit boundary.
4733 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4735 MVT VT = N->getSimpleValueType(0);
4736 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4737 bool Result = (Index * ElSize) % vecWidth == 0;
4742 bool X86::isVINSERT128Index(SDNode *N) {
4743 return isVINSERTIndex(N, 128);
4746 bool X86::isVINSERT256Index(SDNode *N) {
4747 return isVINSERTIndex(N, 256);
4750 bool X86::isVEXTRACT128Index(SDNode *N) {
4751 return isVEXTRACTIndex(N, 128);
4754 bool X86::isVEXTRACT256Index(SDNode *N) {
4755 return isVEXTRACTIndex(N, 256);
4758 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4759 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4760 /// Handles 128-bit and 256-bit.
4761 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4762 MVT VT = N->getSimpleValueType(0);
4764 assert((VT.getSizeInBits() >= 128) &&
4765 "Unsupported vector type for PSHUF/SHUFP");
4767 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4768 // independently on 128-bit lanes.
4769 unsigned NumElts = VT.getVectorNumElements();
4770 unsigned NumLanes = VT.getSizeInBits()/128;
4771 unsigned NumLaneElts = NumElts/NumLanes;
4773 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4774 "Only supports 2, 4 or 8 elements per lane");
4776 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4778 for (unsigned i = 0; i != NumElts; ++i) {
4779 int Elt = N->getMaskElt(i);
4780 if (Elt < 0) continue;
4781 Elt &= NumLaneElts - 1;
4782 unsigned ShAmt = (i << Shift) % 8;
4783 Mask |= Elt << ShAmt;
4789 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4790 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4791 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4792 MVT VT = N->getSimpleValueType(0);
4794 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4795 "Unsupported vector type for PSHUFHW");
4797 unsigned NumElts = VT.getVectorNumElements();
4800 for (unsigned l = 0; l != NumElts; l += 8) {
4801 // 8 nodes per lane, but we only care about the last 4.
4802 for (unsigned i = 0; i < 4; ++i) {
4803 int Elt = N->getMaskElt(l+i+4);
4804 if (Elt < 0) continue;
4805 Elt &= 0x3; // only 2-bits.
4806 Mask |= Elt << (i * 2);
4813 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4814 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4815 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4816 MVT VT = N->getSimpleValueType(0);
4818 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4819 "Unsupported vector type for PSHUFHW");
4821 unsigned NumElts = VT.getVectorNumElements();
4824 for (unsigned l = 0; l != NumElts; l += 8) {
4825 // 8 nodes per lane, but we only care about the first 4.
4826 for (unsigned i = 0; i < 4; ++i) {
4827 int Elt = N->getMaskElt(l+i);
4828 if (Elt < 0) continue;
4829 Elt &= 0x3; // only 2-bits
4830 Mask |= Elt << (i * 2);
4837 /// \brief Return the appropriate immediate to shuffle the specified
4838 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4839 /// VALIGN (if Interlane is true) instructions.
4840 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4842 MVT VT = SVOp->getSimpleValueType(0);
4843 unsigned EltSize = InterLane ? 1 :
4844 VT.getVectorElementType().getSizeInBits() >> 3;
4846 unsigned NumElts = VT.getVectorNumElements();
4847 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4848 unsigned NumLaneElts = NumElts/NumLanes;
4852 for (i = 0; i != NumElts; ++i) {
4853 Val = SVOp->getMaskElt(i);
4857 if (Val >= (int)NumElts)
4858 Val -= NumElts - NumLaneElts;
4860 assert(Val - i > 0 && "PALIGNR imm should be positive");
4861 return (Val - i) * EltSize;
4864 /// \brief Return the appropriate immediate to shuffle the specified
4865 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4866 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4867 return getShuffleAlignrImmediate(SVOp, false);
4870 /// \brief Return the appropriate immediate to shuffle the specified
4871 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4872 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4873 return getShuffleAlignrImmediate(SVOp, true);
4877 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4878 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4879 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4880 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4883 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4885 MVT VecVT = N->getOperand(0).getSimpleValueType();
4886 MVT ElVT = VecVT.getVectorElementType();
4888 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4889 return Index / NumElemsPerChunk;
4892 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4893 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4894 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4895 llvm_unreachable("Illegal insert subvector for VINSERT");
4898 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4900 MVT VecVT = N->getSimpleValueType(0);
4901 MVT ElVT = VecVT.getVectorElementType();
4903 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4904 return Index / NumElemsPerChunk;
4907 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4908 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4909 /// and VINSERTI128 instructions.
4910 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4911 return getExtractVEXTRACTImmediate(N, 128);
4914 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4915 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4916 /// and VINSERTI64x4 instructions.
4917 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4918 return getExtractVEXTRACTImmediate(N, 256);
4921 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4922 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4923 /// and VINSERTI128 instructions.
4924 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4925 return getInsertVINSERTImmediate(N, 128);
4928 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4929 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4930 /// and VINSERTI64x4 instructions.
4931 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4932 return getInsertVINSERTImmediate(N, 256);
4935 /// isZero - Returns true if Elt is a constant integer zero
4936 static bool isZero(SDValue V) {
4937 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4938 return C && C->isNullValue();
4941 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4943 bool X86::isZeroNode(SDValue Elt) {
4946 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4947 return CFP->getValueAPF().isPosZero();
4951 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4952 /// match movhlps. The lower half elements should come from upper half of
4953 /// V1 (and in order), and the upper half elements should come from the upper
4954 /// half of V2 (and in order).
4955 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4956 if (!VT.is128BitVector())
4958 if (VT.getVectorNumElements() != 4)
4960 for (unsigned i = 0, e = 2; i != e; ++i)
4961 if (!isUndefOrEqual(Mask[i], i+2))
4963 for (unsigned i = 2; i != 4; ++i)
4964 if (!isUndefOrEqual(Mask[i], i+4))
4969 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4970 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4972 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4973 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4975 N = N->getOperand(0).getNode();
4976 if (!ISD::isNON_EXTLoad(N))
4979 *LD = cast<LoadSDNode>(N);
4983 // Test whether the given value is a vector value which will be legalized
4985 static bool WillBeConstantPoolLoad(SDNode *N) {
4986 if (N->getOpcode() != ISD::BUILD_VECTOR)
4989 // Check for any non-constant elements.
4990 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4991 switch (N->getOperand(i).getNode()->getOpcode()) {
4993 case ISD::ConstantFP:
5000 // Vectors of all-zeros and all-ones are materialized with special
5001 // instructions rather than being loaded.
5002 return !ISD::isBuildVectorAllZeros(N) &&
5003 !ISD::isBuildVectorAllOnes(N);
5006 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5007 /// match movlp{s|d}. The lower half elements should come from lower half of
5008 /// V1 (and in order), and the upper half elements should come from the upper
5009 /// half of V2 (and in order). And since V1 will become the source of the
5010 /// MOVLP, it must be either a vector load or a scalar load to vector.
5011 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5012 ArrayRef<int> Mask, MVT VT) {
5013 if (!VT.is128BitVector())
5016 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5018 // Is V2 is a vector load, don't do this transformation. We will try to use
5019 // load folding shufps op.
5020 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5023 unsigned NumElems = VT.getVectorNumElements();
5025 if (NumElems != 2 && NumElems != 4)
5027 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5028 if (!isUndefOrEqual(Mask[i], i))
5030 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5031 if (!isUndefOrEqual(Mask[i], i+NumElems))
5036 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5037 /// to an zero vector.
5038 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5039 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5040 SDValue V1 = N->getOperand(0);
5041 SDValue V2 = N->getOperand(1);
5042 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5043 for (unsigned i = 0; i != NumElems; ++i) {
5044 int Idx = N->getMaskElt(i);
5045 if (Idx >= (int)NumElems) {
5046 unsigned Opc = V2.getOpcode();
5047 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5049 if (Opc != ISD::BUILD_VECTOR ||
5050 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5052 } else if (Idx >= 0) {
5053 unsigned Opc = V1.getOpcode();
5054 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5056 if (Opc != ISD::BUILD_VECTOR ||
5057 !X86::isZeroNode(V1.getOperand(Idx)))
5064 /// getZeroVector - Returns a vector of specified type with all zero elements.
5066 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5067 SelectionDAG &DAG, SDLoc dl) {
5068 assert(VT.isVector() && "Expected a vector type");
5070 // Always build SSE zero vectors as <4 x i32> bitcasted
5071 // to their dest type. This ensures they get CSE'd.
5073 if (VT.is128BitVector()) { // SSE
5074 if (Subtarget->hasSSE2()) { // SSE2
5075 SDValue Cst = DAG.getConstant(0, MVT::i32);
5076 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5078 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5079 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5081 } else if (VT.is256BitVector()) { // AVX
5082 if (Subtarget->hasInt256()) { // AVX2
5083 SDValue Cst = DAG.getConstant(0, MVT::i32);
5084 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5085 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5087 // 256-bit logic and arithmetic instructions in AVX are all
5088 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5089 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5090 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5091 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5093 } else if (VT.is512BitVector()) { // AVX-512
5094 SDValue Cst = DAG.getConstant(0, MVT::i32);
5095 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5096 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5097 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5098 } else if (VT.getScalarType() == MVT::i1) {
5099 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5100 SDValue Cst = DAG.getConstant(0, MVT::i1);
5101 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5102 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5104 llvm_unreachable("Unexpected vector type");
5106 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5109 /// getOnesVector - Returns a vector of specified type with all bits set.
5110 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5111 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5112 /// Then bitcast to their original type, ensuring they get CSE'd.
5113 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5115 assert(VT.isVector() && "Expected a vector type");
5117 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5119 if (VT.is256BitVector()) {
5120 if (HasInt256) { // AVX2
5121 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5122 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5124 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5125 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5127 } else if (VT.is128BitVector()) {
5128 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5130 llvm_unreachable("Unexpected vector type");
5132 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5135 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5136 /// that point to V2 points to its first element.
5137 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5138 for (unsigned i = 0; i != NumElems; ++i) {
5139 if (Mask[i] > (int)NumElems) {
5145 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5146 /// operation of specified width.
5147 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5149 unsigned NumElems = VT.getVectorNumElements();
5150 SmallVector<int, 8> Mask;
5151 Mask.push_back(NumElems);
5152 for (unsigned i = 1; i != NumElems; ++i)
5154 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5157 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5158 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5160 unsigned NumElems = VT.getVectorNumElements();
5161 SmallVector<int, 8> Mask;
5162 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5164 Mask.push_back(i + NumElems);
5166 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5169 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5170 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5172 unsigned NumElems = VT.getVectorNumElements();
5173 SmallVector<int, 8> Mask;
5174 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5175 Mask.push_back(i + Half);
5176 Mask.push_back(i + NumElems + Half);
5178 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5181 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5182 // a generic shuffle instruction because the target has no such instructions.
5183 // Generate shuffles which repeat i16 and i8 several times until they can be
5184 // represented by v4f32 and then be manipulated by target suported shuffles.
5185 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5186 MVT VT = V.getSimpleValueType();
5187 int NumElems = VT.getVectorNumElements();
5190 while (NumElems > 4) {
5191 if (EltNo < NumElems/2) {
5192 V = getUnpackl(DAG, dl, VT, V, V);
5194 V = getUnpackh(DAG, dl, VT, V, V);
5195 EltNo -= NumElems/2;
5202 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5203 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5204 MVT VT = V.getSimpleValueType();
5207 if (VT.is128BitVector()) {
5208 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5209 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5210 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5212 } else if (VT.is256BitVector()) {
5213 // To use VPERMILPS to splat scalars, the second half of indicies must
5214 // refer to the higher part, which is a duplication of the lower one,
5215 // because VPERMILPS can only handle in-lane permutations.
5216 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5217 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5219 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5220 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5223 llvm_unreachable("Vector size not supported");
5225 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5228 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5229 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5230 MVT SrcVT = SV->getSimpleValueType(0);
5231 SDValue V1 = SV->getOperand(0);
5234 int EltNo = SV->getSplatIndex();
5235 int NumElems = SrcVT.getVectorNumElements();
5236 bool Is256BitVec = SrcVT.is256BitVector();
5238 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5239 "Unknown how to promote splat for type");
5241 // Extract the 128-bit part containing the splat element and update
5242 // the splat element index when it refers to the higher register.
5244 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5245 if (EltNo >= NumElems/2)
5246 EltNo -= NumElems/2;
5249 // All i16 and i8 vector types can't be used directly by a generic shuffle
5250 // instruction because the target has no such instruction. Generate shuffles
5251 // which repeat i16 and i8 several times until they fit in i32, and then can
5252 // be manipulated by target suported shuffles.
5253 MVT EltVT = SrcVT.getVectorElementType();
5254 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5255 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5257 // Recreate the 256-bit vector and place the same 128-bit vector
5258 // into the low and high part. This is necessary because we want
5259 // to use VPERM* to shuffle the vectors
5261 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5264 return getLegalSplat(DAG, V1, EltNo);
5267 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5268 /// vector of zero or undef vector. This produces a shuffle where the low
5269 /// element of V2 is swizzled into the zero/undef vector, landing at element
5270 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5271 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5273 const X86Subtarget *Subtarget,
5274 SelectionDAG &DAG) {
5275 MVT VT = V2.getSimpleValueType();
5277 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5278 unsigned NumElems = VT.getVectorNumElements();
5279 SmallVector<int, 16> MaskVec;
5280 for (unsigned i = 0; i != NumElems; ++i)
5281 // If this is the insertion idx, put the low elt of V2 here.
5282 MaskVec.push_back(i == Idx ? NumElems : i);
5283 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5286 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5287 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5288 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5289 /// shuffles which use a single input multiple times, and in those cases it will
5290 /// adjust the mask to only have indices within that single input.
5291 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5292 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5293 unsigned NumElems = VT.getVectorNumElements();
5297 bool IsFakeUnary = false;
5298 switch(N->getOpcode()) {
5299 case X86ISD::BLENDI:
5300 ImmN = N->getOperand(N->getNumOperands()-1);
5301 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5304 ImmN = N->getOperand(N->getNumOperands()-1);
5305 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5306 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5308 case X86ISD::UNPCKH:
5309 DecodeUNPCKHMask(VT, Mask);
5310 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5312 case X86ISD::UNPCKL:
5313 DecodeUNPCKLMask(VT, Mask);
5314 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5316 case X86ISD::MOVHLPS:
5317 DecodeMOVHLPSMask(NumElems, Mask);
5318 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5320 case X86ISD::MOVLHPS:
5321 DecodeMOVLHPSMask(NumElems, Mask);
5322 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5324 case X86ISD::PALIGNR:
5325 ImmN = N->getOperand(N->getNumOperands()-1);
5326 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5328 case X86ISD::PSHUFD:
5329 case X86ISD::VPERMILPI:
5330 ImmN = N->getOperand(N->getNumOperands()-1);
5331 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5334 case X86ISD::PSHUFHW:
5335 ImmN = N->getOperand(N->getNumOperands()-1);
5336 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5339 case X86ISD::PSHUFLW:
5340 ImmN = N->getOperand(N->getNumOperands()-1);
5341 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5344 case X86ISD::PSHUFB: {
5346 SDValue MaskNode = N->getOperand(1);
5347 while (MaskNode->getOpcode() == ISD::BITCAST)
5348 MaskNode = MaskNode->getOperand(0);
5350 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5351 // If we have a build-vector, then things are easy.
5352 EVT VT = MaskNode.getValueType();
5353 assert(VT.isVector() &&
5354 "Can't produce a non-vector with a build_vector!");
5355 if (!VT.isInteger())
5358 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5360 SmallVector<uint64_t, 32> RawMask;
5361 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5362 SDValue Op = MaskNode->getOperand(i);
5363 if (Op->getOpcode() == ISD::UNDEF) {
5364 RawMask.push_back((uint64_t)SM_SentinelUndef);
5367 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5370 APInt MaskElement = CN->getAPIntValue();
5372 // We now have to decode the element which could be any integer size and
5373 // extract each byte of it.
5374 for (int j = 0; j < NumBytesPerElement; ++j) {
5375 // Note that this is x86 and so always little endian: the low byte is
5376 // the first byte of the mask.
5377 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5378 MaskElement = MaskElement.lshr(8);
5381 DecodePSHUFBMask(RawMask, Mask);
5385 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5389 SDValue Ptr = MaskLoad->getBasePtr();
5390 if (Ptr->getOpcode() == X86ISD::Wrapper)
5391 Ptr = Ptr->getOperand(0);
5393 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5394 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5397 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5398 // FIXME: Support AVX-512 here.
5399 Type *Ty = C->getType();
5400 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5401 Ty->getVectorNumElements() != 32))
5404 DecodePSHUFBMask(C, Mask);
5410 case X86ISD::VPERMI:
5411 ImmN = N->getOperand(N->getNumOperands()-1);
5412 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5416 case X86ISD::MOVSD: {
5417 // The index 0 always comes from the first element of the second source,
5418 // this is why MOVSS and MOVSD are used in the first place. The other
5419 // elements come from the other positions of the first source vector
5420 Mask.push_back(NumElems);
5421 for (unsigned i = 1; i != NumElems; ++i) {
5426 case X86ISD::VPERM2X128:
5427 ImmN = N->getOperand(N->getNumOperands()-1);
5428 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5429 if (Mask.empty()) return false;
5431 case X86ISD::MOVSLDUP:
5432 DecodeMOVSLDUPMask(VT, Mask);
5434 case X86ISD::MOVSHDUP:
5435 DecodeMOVSHDUPMask(VT, Mask);
5437 case X86ISD::MOVDDUP:
5438 case X86ISD::MOVLHPD:
5439 case X86ISD::MOVLPD:
5440 case X86ISD::MOVLPS:
5441 // Not yet implemented
5443 default: llvm_unreachable("unknown target shuffle node");
5446 // If we have a fake unary shuffle, the shuffle mask is spread across two
5447 // inputs that are actually the same node. Re-map the mask to always point
5448 // into the first input.
5451 if (M >= (int)Mask.size())
5457 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5458 /// element of the result of the vector shuffle.
5459 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5462 return SDValue(); // Limit search depth.
5464 SDValue V = SDValue(N, 0);
5465 EVT VT = V.getValueType();
5466 unsigned Opcode = V.getOpcode();
5468 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5469 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5470 int Elt = SV->getMaskElt(Index);
5473 return DAG.getUNDEF(VT.getVectorElementType());
5475 unsigned NumElems = VT.getVectorNumElements();
5476 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5477 : SV->getOperand(1);
5478 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5481 // Recurse into target specific vector shuffles to find scalars.
5482 if (isTargetShuffle(Opcode)) {
5483 MVT ShufVT = V.getSimpleValueType();
5484 unsigned NumElems = ShufVT.getVectorNumElements();
5485 SmallVector<int, 16> ShuffleMask;
5488 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5491 int Elt = ShuffleMask[Index];
5493 return DAG.getUNDEF(ShufVT.getVectorElementType());
5495 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5497 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5501 // Actual nodes that may contain scalar elements
5502 if (Opcode == ISD::BITCAST) {
5503 V = V.getOperand(0);
5504 EVT SrcVT = V.getValueType();
5505 unsigned NumElems = VT.getVectorNumElements();
5507 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5511 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5512 return (Index == 0) ? V.getOperand(0)
5513 : DAG.getUNDEF(VT.getVectorElementType());
5515 if (V.getOpcode() == ISD::BUILD_VECTOR)
5516 return V.getOperand(Index);
5521 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5522 /// shuffle operation which come from a consecutively from a zero. The
5523 /// search can start in two different directions, from left or right.
5524 /// We count undefs as zeros until PreferredNum is reached.
5525 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5526 unsigned NumElems, bool ZerosFromLeft,
5528 unsigned PreferredNum = -1U) {
5529 unsigned NumZeros = 0;
5530 for (unsigned i = 0; i != NumElems; ++i) {
5531 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5532 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5536 if (X86::isZeroNode(Elt))
5538 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5539 NumZeros = std::min(NumZeros + 1, PreferredNum);
5547 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5548 /// correspond consecutively to elements from one of the vector operands,
5549 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5551 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5552 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5553 unsigned NumElems, unsigned &OpNum) {
5554 bool SeenV1 = false;
5555 bool SeenV2 = false;
5557 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5558 int Idx = SVOp->getMaskElt(i);
5559 // Ignore undef indicies
5563 if (Idx < (int)NumElems)
5568 // Only accept consecutive elements from the same vector
5569 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5573 OpNum = SeenV1 ? 0 : 1;
5577 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5578 /// logical left shift of a vector.
5579 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5580 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5582 SVOp->getSimpleValueType(0).getVectorNumElements();
5583 unsigned NumZeros = getNumOfConsecutiveZeros(
5584 SVOp, NumElems, false /* check zeros from right */, DAG,
5585 SVOp->getMaskElt(0));
5591 // Considering the elements in the mask that are not consecutive zeros,
5592 // check if they consecutively come from only one of the source vectors.
5594 // V1 = {X, A, B, C} 0
5596 // vector_shuffle V1, V2 <1, 2, 3, X>
5598 if (!isShuffleMaskConsecutive(SVOp,
5599 0, // Mask Start Index
5600 NumElems-NumZeros, // Mask End Index(exclusive)
5601 NumZeros, // Where to start looking in the src vector
5602 NumElems, // Number of elements in vector
5603 OpSrc)) // Which source operand ?
5608 ShVal = SVOp->getOperand(OpSrc);
5612 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5613 /// logical left shift of a vector.
5614 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5615 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5617 SVOp->getSimpleValueType(0).getVectorNumElements();
5618 unsigned NumZeros = getNumOfConsecutiveZeros(
5619 SVOp, NumElems, true /* check zeros from left */, DAG,
5620 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5626 // Considering the elements in the mask that are not consecutive zeros,
5627 // check if they consecutively come from only one of the source vectors.
5629 // 0 { A, B, X, X } = V2
5631 // vector_shuffle V1, V2 <X, X, 4, 5>
5633 if (!isShuffleMaskConsecutive(SVOp,
5634 NumZeros, // Mask Start Index
5635 NumElems, // Mask End Index(exclusive)
5636 0, // Where to start looking in the src vector
5637 NumElems, // Number of elements in vector
5638 OpSrc)) // Which source operand ?
5643 ShVal = SVOp->getOperand(OpSrc);
5647 /// isVectorShift - Returns true if the shuffle can be implemented as a
5648 /// logical left or right shift of a vector.
5649 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5650 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5651 // Although the logic below support any bitwidth size, there are no
5652 // shift instructions which handle more than 128-bit vectors.
5653 if (!SVOp->getSimpleValueType(0).is128BitVector())
5656 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5657 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5663 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5665 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5666 unsigned NumNonZero, unsigned NumZero,
5668 const X86Subtarget* Subtarget,
5669 const TargetLowering &TLI) {
5676 for (unsigned i = 0; i < 16; ++i) {
5677 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5678 if (ThisIsNonZero && First) {
5680 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5682 V = DAG.getUNDEF(MVT::v8i16);
5687 SDValue ThisElt, LastElt;
5688 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5689 if (LastIsNonZero) {
5690 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5691 MVT::i16, Op.getOperand(i-1));
5693 if (ThisIsNonZero) {
5694 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5695 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5696 ThisElt, DAG.getConstant(8, MVT::i8));
5698 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5702 if (ThisElt.getNode())
5703 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5704 DAG.getIntPtrConstant(i/2));
5708 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5711 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5713 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5714 unsigned NumNonZero, unsigned NumZero,
5716 const X86Subtarget* Subtarget,
5717 const TargetLowering &TLI) {
5724 for (unsigned i = 0; i < 8; ++i) {
5725 bool isNonZero = (NonZeros & (1 << i)) != 0;
5729 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5731 V = DAG.getUNDEF(MVT::v8i16);
5734 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5735 MVT::v8i16, V, Op.getOperand(i),
5736 DAG.getIntPtrConstant(i));
5743 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5744 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5745 const X86Subtarget *Subtarget,
5746 const TargetLowering &TLI) {
5747 // Find all zeroable elements.
5749 for (int i=0; i < 4; ++i) {
5750 SDValue Elt = Op->getOperand(i);
5751 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5753 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5754 [](bool M) { return !M; }) > 1 &&
5755 "We expect at least two non-zero elements!");
5757 // We only know how to deal with build_vector nodes where elements are either
5758 // zeroable or extract_vector_elt with constant index.
5759 SDValue FirstNonZero;
5760 for (int i=0; i < 4; ++i) {
5763 SDValue Elt = Op->getOperand(i);
5764 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5765 !isa<ConstantSDNode>(Elt.getOperand(1)))
5767 // Make sure that this node is extracting from a 128-bit vector.
5768 MVT VT = Elt.getOperand(0).getSimpleValueType();
5769 if (!VT.is128BitVector())
5771 if (!FirstNonZero.getNode())
5775 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5776 SDValue V1 = FirstNonZero.getOperand(0);
5777 MVT VT = V1.getSimpleValueType();
5779 // See if this build_vector can be lowered as a blend with zero.
5781 unsigned EltMaskIdx, EltIdx;
5783 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5784 if (Zeroable[EltIdx]) {
5785 // The zero vector will be on the right hand side.
5786 Mask[EltIdx] = EltIdx+4;
5790 Elt = Op->getOperand(EltIdx);
5791 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5792 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5793 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5795 Mask[EltIdx] = EltIdx;
5799 // Let the shuffle legalizer deal with blend operations.
5800 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5801 if (V1.getSimpleValueType() != VT)
5802 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5803 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5806 // See if we can lower this build_vector to a INSERTPS.
5807 if (!Subtarget->hasSSE41())
5810 SDValue V2 = Elt.getOperand(0);
5811 if (Elt == FirstNonZero)
5814 bool CanFold = true;
5815 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5819 SDValue Current = Op->getOperand(i);
5820 SDValue SrcVector = Current->getOperand(0);
5823 CanFold = SrcVector == V1 &&
5824 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5830 assert(V1.getNode() && "Expected at least two non-zero elements!");
5831 if (V1.getSimpleValueType() != MVT::v4f32)
5832 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5833 if (V2.getSimpleValueType() != MVT::v4f32)
5834 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5836 // Ok, we can emit an INSERTPS instruction.
5838 for (int i = 0; i < 4; ++i)
5842 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5843 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5844 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5845 DAG.getIntPtrConstant(InsertPSMask));
5846 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5849 /// getVShift - Return a vector logical shift node.
5851 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5852 unsigned NumBits, SelectionDAG &DAG,
5853 const TargetLowering &TLI, SDLoc dl) {
5854 assert(VT.is128BitVector() && "Unknown type for VShift");
5855 EVT ShVT = MVT::v2i64;
5856 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5857 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5858 return DAG.getNode(ISD::BITCAST, dl, VT,
5859 DAG.getNode(Opc, dl, ShVT, SrcOp,
5860 DAG.getConstant(NumBits,
5861 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5865 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5867 // Check if the scalar load can be widened into a vector load. And if
5868 // the address is "base + cst" see if the cst can be "absorbed" into
5869 // the shuffle mask.
5870 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5871 SDValue Ptr = LD->getBasePtr();
5872 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5874 EVT PVT = LD->getValueType(0);
5875 if (PVT != MVT::i32 && PVT != MVT::f32)
5880 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5881 FI = FINode->getIndex();
5883 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5884 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5885 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5886 Offset = Ptr.getConstantOperandVal(1);
5887 Ptr = Ptr.getOperand(0);
5892 // FIXME: 256-bit vector instructions don't require a strict alignment,
5893 // improve this code to support it better.
5894 unsigned RequiredAlign = VT.getSizeInBits()/8;
5895 SDValue Chain = LD->getChain();
5896 // Make sure the stack object alignment is at least 16 or 32.
5897 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5898 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5899 if (MFI->isFixedObjectIndex(FI)) {
5900 // Can't change the alignment. FIXME: It's possible to compute
5901 // the exact stack offset and reference FI + adjust offset instead.
5902 // If someone *really* cares about this. That's the way to implement it.
5905 MFI->setObjectAlignment(FI, RequiredAlign);
5909 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5910 // Ptr + (Offset & ~15).
5913 if ((Offset % RequiredAlign) & 3)
5915 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5917 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5918 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5920 int EltNo = (Offset - StartOffset) >> 2;
5921 unsigned NumElems = VT.getVectorNumElements();
5923 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5924 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5925 LD->getPointerInfo().getWithOffset(StartOffset),
5926 false, false, false, 0);
5928 SmallVector<int, 8> Mask;
5929 for (unsigned i = 0; i != NumElems; ++i)
5930 Mask.push_back(EltNo);
5932 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5938 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5939 /// vector of type 'VT', see if the elements can be replaced by a single large
5940 /// load which has the same value as a build_vector whose operands are 'elts'.
5942 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5944 /// FIXME: we'd also like to handle the case where the last elements are zero
5945 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5946 /// There's even a handy isZeroNode for that purpose.
5947 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5948 SDLoc &DL, SelectionDAG &DAG,
5949 bool isAfterLegalize) {
5950 EVT EltVT = VT.getVectorElementType();
5951 unsigned NumElems = Elts.size();
5953 LoadSDNode *LDBase = nullptr;
5954 unsigned LastLoadedElt = -1U;
5956 // For each element in the initializer, see if we've found a load or an undef.
5957 // If we don't find an initial load element, or later load elements are
5958 // non-consecutive, bail out.
5959 for (unsigned i = 0; i < NumElems; ++i) {
5960 SDValue Elt = Elts[i];
5962 if (!Elt.getNode() ||
5963 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5966 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5968 LDBase = cast<LoadSDNode>(Elt.getNode());
5972 if (Elt.getOpcode() == ISD::UNDEF)
5975 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5976 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5981 // If we have found an entire vector of loads and undefs, then return a large
5982 // load of the entire vector width starting at the base pointer. If we found
5983 // consecutive loads for the low half, generate a vzext_load node.
5984 if (LastLoadedElt == NumElems - 1) {
5986 if (isAfterLegalize &&
5987 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5990 SDValue NewLd = SDValue();
5992 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5993 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5994 LDBase->getPointerInfo(),
5995 LDBase->isVolatile(), LDBase->isNonTemporal(),
5996 LDBase->isInvariant(), 0);
5997 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5998 LDBase->getPointerInfo(),
5999 LDBase->isVolatile(), LDBase->isNonTemporal(),
6000 LDBase->isInvariant(), LDBase->getAlignment());
6002 if (LDBase->hasAnyUseOfValue(1)) {
6003 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6005 SDValue(NewLd.getNode(), 1));
6006 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6007 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6008 SDValue(NewLd.getNode(), 1));
6013 if (NumElems == 4 && LastLoadedElt == 1 &&
6014 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6015 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6016 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6018 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6019 LDBase->getPointerInfo(),
6020 LDBase->getAlignment(),
6021 false/*isVolatile*/, true/*ReadMem*/,
6024 // Make sure the newly-created LOAD is in the same position as LDBase in
6025 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6026 // update uses of LDBase's output chain to use the TokenFactor.
6027 if (LDBase->hasAnyUseOfValue(1)) {
6028 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6029 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6030 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6031 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6032 SDValue(ResNode.getNode(), 1));
6035 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6040 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6041 /// to generate a splat value for the following cases:
6042 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6043 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6044 /// a scalar load, or a constant.
6045 /// The VBROADCAST node is returned when a pattern is found,
6046 /// or SDValue() otherwise.
6047 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6048 SelectionDAG &DAG) {
6049 // VBROADCAST requires AVX.
6050 // TODO: Splats could be generated for non-AVX CPUs using SSE
6051 // instructions, but there's less potential gain for only 128-bit vectors.
6052 if (!Subtarget->hasAVX())
6055 MVT VT = Op.getSimpleValueType();
6058 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6059 "Unsupported vector type for broadcast.");
6064 switch (Op.getOpcode()) {
6066 // Unknown pattern found.
6069 case ISD::BUILD_VECTOR: {
6070 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6071 BitVector UndefElements;
6072 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6074 // We need a splat of a single value to use broadcast, and it doesn't
6075 // make any sense if the value is only in one element of the vector.
6076 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6080 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6081 Ld.getOpcode() == ISD::ConstantFP);
6083 // Make sure that all of the users of a non-constant load are from the
6084 // BUILD_VECTOR node.
6085 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6090 case ISD::VECTOR_SHUFFLE: {
6091 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6093 // Shuffles must have a splat mask where the first element is
6095 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6098 SDValue Sc = Op.getOperand(0);
6099 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6100 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6102 if (!Subtarget->hasInt256())
6105 // Use the register form of the broadcast instruction available on AVX2.
6106 if (VT.getSizeInBits() >= 256)
6107 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6108 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6111 Ld = Sc.getOperand(0);
6112 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6113 Ld.getOpcode() == ISD::ConstantFP);
6115 // The scalar_to_vector node and the suspected
6116 // load node must have exactly one user.
6117 // Constants may have multiple users.
6119 // AVX-512 has register version of the broadcast
6120 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6121 Ld.getValueType().getSizeInBits() >= 32;
6122 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6129 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6130 bool IsGE256 = (VT.getSizeInBits() >= 256);
6132 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6133 // instruction to save 8 or more bytes of constant pool data.
6134 // TODO: If multiple splats are generated to load the same constant,
6135 // it may be detrimental to overall size. There needs to be a way to detect
6136 // that condition to know if this is truly a size win.
6137 const Function *F = DAG.getMachineFunction().getFunction();
6138 bool OptForSize = F->getAttributes().
6139 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6141 // Handle broadcasting a single constant scalar from the constant pool
6143 // On Sandybridge (no AVX2), it is still better to load a constant vector
6144 // from the constant pool and not to broadcast it from a scalar.
6145 // But override that restriction when optimizing for size.
6146 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6147 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6148 EVT CVT = Ld.getValueType();
6149 assert(!CVT.isVector() && "Must not broadcast a vector type");
6151 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6152 // For size optimization, also splat v2f64 and v2i64, and for size opt
6153 // with AVX2, also splat i8 and i16.
6154 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6155 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6156 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6157 const Constant *C = nullptr;
6158 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6159 C = CI->getConstantIntValue();
6160 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6161 C = CF->getConstantFPValue();
6163 assert(C && "Invalid constant type");
6165 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6166 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6167 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6168 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6169 MachinePointerInfo::getConstantPool(),
6170 false, false, false, Alignment);
6172 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6176 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6178 // Handle AVX2 in-register broadcasts.
6179 if (!IsLoad && Subtarget->hasInt256() &&
6180 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6181 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6183 // The scalar source must be a normal load.
6187 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6188 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6190 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6191 // double since there is no vbroadcastsd xmm
6192 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6193 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6194 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6197 // Unsupported broadcast.
6201 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6202 /// underlying vector and index.
6204 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6206 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6208 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6209 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6212 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6214 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6216 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6217 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6220 // In this case the vector is the extract_subvector expression and the index
6221 // is 2, as specified by the shuffle.
6222 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6223 SDValue ShuffleVec = SVOp->getOperand(0);
6224 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6225 assert(ShuffleVecVT.getVectorElementType() ==
6226 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6228 int ShuffleIdx = SVOp->getMaskElt(Idx);
6229 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6230 ExtractedFromVec = ShuffleVec;
6236 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6237 MVT VT = Op.getSimpleValueType();
6239 // Skip if insert_vec_elt is not supported.
6240 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6241 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6245 unsigned NumElems = Op.getNumOperands();
6249 SmallVector<unsigned, 4> InsertIndices;
6250 SmallVector<int, 8> Mask(NumElems, -1);
6252 for (unsigned i = 0; i != NumElems; ++i) {
6253 unsigned Opc = Op.getOperand(i).getOpcode();
6255 if (Opc == ISD::UNDEF)
6258 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6259 // Quit if more than 1 elements need inserting.
6260 if (InsertIndices.size() > 1)
6263 InsertIndices.push_back(i);
6267 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6268 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6269 // Quit if non-constant index.
6270 if (!isa<ConstantSDNode>(ExtIdx))
6272 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6274 // Quit if extracted from vector of different type.
6275 if (ExtractedFromVec.getValueType() != VT)
6278 if (!VecIn1.getNode())
6279 VecIn1 = ExtractedFromVec;
6280 else if (VecIn1 != ExtractedFromVec) {
6281 if (!VecIn2.getNode())
6282 VecIn2 = ExtractedFromVec;
6283 else if (VecIn2 != ExtractedFromVec)
6284 // Quit if more than 2 vectors to shuffle
6288 if (ExtractedFromVec == VecIn1)
6290 else if (ExtractedFromVec == VecIn2)
6291 Mask[i] = Idx + NumElems;
6294 if (!VecIn1.getNode())
6297 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6298 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6299 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6300 unsigned Idx = InsertIndices[i];
6301 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6302 DAG.getIntPtrConstant(Idx));
6308 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6310 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6312 MVT VT = Op.getSimpleValueType();
6313 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6314 "Unexpected type in LowerBUILD_VECTORvXi1!");
6317 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6318 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6319 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6320 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6323 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6324 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6325 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6326 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6329 bool AllContants = true;
6330 uint64_t Immediate = 0;
6331 int NonConstIdx = -1;
6332 bool IsSplat = true;
6333 unsigned NumNonConsts = 0;
6334 unsigned NumConsts = 0;
6335 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6336 SDValue In = Op.getOperand(idx);
6337 if (In.getOpcode() == ISD::UNDEF)
6339 if (!isa<ConstantSDNode>(In)) {
6340 AllContants = false;
6346 if (cast<ConstantSDNode>(In)->getZExtValue())
6347 Immediate |= (1ULL << idx);
6349 if (In != Op.getOperand(0))
6354 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6355 DAG.getConstant(Immediate, MVT::i16));
6356 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6357 DAG.getIntPtrConstant(0));
6360 if (NumNonConsts == 1 && NonConstIdx != 0) {
6363 SDValue VecAsImm = DAG.getConstant(Immediate,
6364 MVT::getIntegerVT(VT.getSizeInBits()));
6365 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6368 DstVec = DAG.getUNDEF(VT);
6369 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6370 Op.getOperand(NonConstIdx),
6371 DAG.getIntPtrConstant(NonConstIdx));
6373 if (!IsSplat && (NonConstIdx != 0))
6374 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6375 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6378 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6379 DAG.getConstant(-1, SelectVT),
6380 DAG.getConstant(0, SelectVT));
6382 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6383 DAG.getConstant((Immediate | 1), SelectVT),
6384 DAG.getConstant(Immediate, SelectVT));
6385 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6388 /// \brief Return true if \p N implements a horizontal binop and return the
6389 /// operands for the horizontal binop into V0 and V1.
6391 /// This is a helper function of PerformBUILD_VECTORCombine.
6392 /// This function checks that the build_vector \p N in input implements a
6393 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6394 /// operation to match.
6395 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6396 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6397 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6400 /// This function only analyzes elements of \p N whose indices are
6401 /// in range [BaseIdx, LastIdx).
6402 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6404 unsigned BaseIdx, unsigned LastIdx,
6405 SDValue &V0, SDValue &V1) {
6406 EVT VT = N->getValueType(0);
6408 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6409 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6410 "Invalid Vector in input!");
6412 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6413 bool CanFold = true;
6414 unsigned ExpectedVExtractIdx = BaseIdx;
6415 unsigned NumElts = LastIdx - BaseIdx;
6416 V0 = DAG.getUNDEF(VT);
6417 V1 = DAG.getUNDEF(VT);
6419 // Check if N implements a horizontal binop.
6420 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6421 SDValue Op = N->getOperand(i + BaseIdx);
6424 if (Op->getOpcode() == ISD::UNDEF) {
6425 // Update the expected vector extract index.
6426 if (i * 2 == NumElts)
6427 ExpectedVExtractIdx = BaseIdx;
6428 ExpectedVExtractIdx += 2;
6432 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6437 SDValue Op0 = Op.getOperand(0);
6438 SDValue Op1 = Op.getOperand(1);
6440 // Try to match the following pattern:
6441 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6442 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6443 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6444 Op0.getOperand(0) == Op1.getOperand(0) &&
6445 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6446 isa<ConstantSDNode>(Op1.getOperand(1)));
6450 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6451 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6453 if (i * 2 < NumElts) {
6454 if (V0.getOpcode() == ISD::UNDEF)
6455 V0 = Op0.getOperand(0);
6457 if (V1.getOpcode() == ISD::UNDEF)
6458 V1 = Op0.getOperand(0);
6459 if (i * 2 == NumElts)
6460 ExpectedVExtractIdx = BaseIdx;
6463 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6464 if (I0 == ExpectedVExtractIdx)
6465 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6466 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6467 // Try to match the following dag sequence:
6468 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6469 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6473 ExpectedVExtractIdx += 2;
6479 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6480 /// a concat_vector.
6482 /// This is a helper function of PerformBUILD_VECTORCombine.
6483 /// This function expects two 256-bit vectors called V0 and V1.
6484 /// At first, each vector is split into two separate 128-bit vectors.
6485 /// Then, the resulting 128-bit vectors are used to implement two
6486 /// horizontal binary operations.
6488 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6490 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6491 /// the two new horizontal binop.
6492 /// When Mode is set, the first horizontal binop dag node would take as input
6493 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6494 /// horizontal binop dag node would take as input the lower 128-bit of V1
6495 /// and the upper 128-bit of V1.
6497 /// HADD V0_LO, V0_HI
6498 /// HADD V1_LO, V1_HI
6500 /// Otherwise, the first horizontal binop dag node takes as input the lower
6501 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6502 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6504 /// HADD V0_LO, V1_LO
6505 /// HADD V0_HI, V1_HI
6507 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6508 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6509 /// the upper 128-bits of the result.
6510 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6511 SDLoc DL, SelectionDAG &DAG,
6512 unsigned X86Opcode, bool Mode,
6513 bool isUndefLO, bool isUndefHI) {
6514 EVT VT = V0.getValueType();
6515 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6516 "Invalid nodes in input!");
6518 unsigned NumElts = VT.getVectorNumElements();
6519 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6520 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6521 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6522 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6523 EVT NewVT = V0_LO.getValueType();
6525 SDValue LO = DAG.getUNDEF(NewVT);
6526 SDValue HI = DAG.getUNDEF(NewVT);
6529 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6530 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6531 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6532 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6533 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6535 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6536 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6537 V1_LO->getOpcode() != ISD::UNDEF))
6538 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6540 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6541 V1_HI->getOpcode() != ISD::UNDEF))
6542 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6545 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6548 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6549 /// sequence of 'vadd + vsub + blendi'.
6550 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6551 const X86Subtarget *Subtarget) {
6553 EVT VT = BV->getValueType(0);
6554 unsigned NumElts = VT.getVectorNumElements();
6555 SDValue InVec0 = DAG.getUNDEF(VT);
6556 SDValue InVec1 = DAG.getUNDEF(VT);
6558 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6559 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6561 // Odd-numbered elements in the input build vector are obtained from
6562 // adding two integer/float elements.
6563 // Even-numbered elements in the input build vector are obtained from
6564 // subtracting two integer/float elements.
6565 unsigned ExpectedOpcode = ISD::FSUB;
6566 unsigned NextExpectedOpcode = ISD::FADD;
6567 bool AddFound = false;
6568 bool SubFound = false;
6570 for (unsigned i = 0, e = NumElts; i != e; i++) {
6571 SDValue Op = BV->getOperand(i);
6573 // Skip 'undef' values.
6574 unsigned Opcode = Op.getOpcode();
6575 if (Opcode == ISD::UNDEF) {
6576 std::swap(ExpectedOpcode, NextExpectedOpcode);
6580 // Early exit if we found an unexpected opcode.
6581 if (Opcode != ExpectedOpcode)
6584 SDValue Op0 = Op.getOperand(0);
6585 SDValue Op1 = Op.getOperand(1);
6587 // Try to match the following pattern:
6588 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6589 // Early exit if we cannot match that sequence.
6590 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6591 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6592 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6593 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6594 Op0.getOperand(1) != Op1.getOperand(1))
6597 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6601 // We found a valid add/sub node. Update the information accordingly.
6607 // Update InVec0 and InVec1.
6608 if (InVec0.getOpcode() == ISD::UNDEF)
6609 InVec0 = Op0.getOperand(0);
6610 if (InVec1.getOpcode() == ISD::UNDEF)
6611 InVec1 = Op1.getOperand(0);
6613 // Make sure that operands in input to each add/sub node always
6614 // come from a same pair of vectors.
6615 if (InVec0 != Op0.getOperand(0)) {
6616 if (ExpectedOpcode == ISD::FSUB)
6619 // FADD is commutable. Try to commute the operands
6620 // and then test again.
6621 std::swap(Op0, Op1);
6622 if (InVec0 != Op0.getOperand(0))
6626 if (InVec1 != Op1.getOperand(0))
6629 // Update the pair of expected opcodes.
6630 std::swap(ExpectedOpcode, NextExpectedOpcode);
6633 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6634 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6635 InVec1.getOpcode() != ISD::UNDEF)
6636 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6641 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6642 const X86Subtarget *Subtarget) {
6644 EVT VT = N->getValueType(0);
6645 unsigned NumElts = VT.getVectorNumElements();
6646 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6647 SDValue InVec0, InVec1;
6649 // Try to match an ADDSUB.
6650 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6651 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6652 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6653 if (Value.getNode())
6657 // Try to match horizontal ADD/SUB.
6658 unsigned NumUndefsLO = 0;
6659 unsigned NumUndefsHI = 0;
6660 unsigned Half = NumElts/2;
6662 // Count the number of UNDEF operands in the build_vector in input.
6663 for (unsigned i = 0, e = Half; i != e; ++i)
6664 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6667 for (unsigned i = Half, e = NumElts; i != e; ++i)
6668 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6671 // Early exit if this is either a build_vector of all UNDEFs or all the
6672 // operands but one are UNDEF.
6673 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6676 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6677 // Try to match an SSE3 float HADD/HSUB.
6678 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6679 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6681 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6682 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6683 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6684 // Try to match an SSSE3 integer HADD/HSUB.
6685 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6686 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6688 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6689 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6692 if (!Subtarget->hasAVX())
6695 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6696 // Try to match an AVX horizontal add/sub of packed single/double
6697 // precision floating point values from 256-bit vectors.
6698 SDValue InVec2, InVec3;
6699 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6700 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6701 ((InVec0.getOpcode() == ISD::UNDEF ||
6702 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6703 ((InVec1.getOpcode() == ISD::UNDEF ||
6704 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6705 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6707 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6708 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6709 ((InVec0.getOpcode() == ISD::UNDEF ||
6710 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6711 ((InVec1.getOpcode() == ISD::UNDEF ||
6712 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6713 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6714 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6715 // Try to match an AVX2 horizontal add/sub of signed integers.
6716 SDValue InVec2, InVec3;
6718 bool CanFold = true;
6720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6721 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6722 ((InVec0.getOpcode() == ISD::UNDEF ||
6723 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6724 ((InVec1.getOpcode() == ISD::UNDEF ||
6725 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6726 X86Opcode = X86ISD::HADD;
6727 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6728 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6729 ((InVec0.getOpcode() == ISD::UNDEF ||
6730 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6731 ((InVec1.getOpcode() == ISD::UNDEF ||
6732 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6733 X86Opcode = X86ISD::HSUB;
6738 // Fold this build_vector into a single horizontal add/sub.
6739 // Do this only if the target has AVX2.
6740 if (Subtarget->hasAVX2())
6741 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6743 // Do not try to expand this build_vector into a pair of horizontal
6744 // add/sub if we can emit a pair of scalar add/sub.
6745 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6748 // Convert this build_vector into a pair of horizontal binop followed by
6750 bool isUndefLO = NumUndefsLO == Half;
6751 bool isUndefHI = NumUndefsHI == Half;
6752 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6753 isUndefLO, isUndefHI);
6757 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6758 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6760 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6761 X86Opcode = X86ISD::HADD;
6762 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6763 X86Opcode = X86ISD::HSUB;
6764 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6765 X86Opcode = X86ISD::FHADD;
6766 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6767 X86Opcode = X86ISD::FHSUB;
6771 // Don't try to expand this build_vector into a pair of horizontal add/sub
6772 // if we can simply emit a pair of scalar add/sub.
6773 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6776 // Convert this build_vector into two horizontal add/sub followed by
6778 bool isUndefLO = NumUndefsLO == Half;
6779 bool isUndefHI = NumUndefsHI == Half;
6780 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6781 isUndefLO, isUndefHI);
6788 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6791 MVT VT = Op.getSimpleValueType();
6792 MVT ExtVT = VT.getVectorElementType();
6793 unsigned NumElems = Op.getNumOperands();
6795 // Generate vectors for predicate vectors.
6796 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6797 return LowerBUILD_VECTORvXi1(Op, DAG);
6799 // Vectors containing all zeros can be matched by pxor and xorps later
6800 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6801 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6802 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6803 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6806 return getZeroVector(VT, Subtarget, DAG, dl);
6809 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6810 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6811 // vpcmpeqd on 256-bit vectors.
6812 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6813 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6816 if (!VT.is512BitVector())
6817 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6820 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6821 if (Broadcast.getNode())
6824 unsigned EVTBits = ExtVT.getSizeInBits();
6826 unsigned NumZero = 0;
6827 unsigned NumNonZero = 0;
6828 unsigned NonZeros = 0;
6829 bool IsAllConstants = true;
6830 SmallSet<SDValue, 8> Values;
6831 for (unsigned i = 0; i < NumElems; ++i) {
6832 SDValue Elt = Op.getOperand(i);
6833 if (Elt.getOpcode() == ISD::UNDEF)
6836 if (Elt.getOpcode() != ISD::Constant &&
6837 Elt.getOpcode() != ISD::ConstantFP)
6838 IsAllConstants = false;
6839 if (X86::isZeroNode(Elt))
6842 NonZeros |= (1 << i);
6847 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6848 if (NumNonZero == 0)
6849 return DAG.getUNDEF(VT);
6851 // Special case for single non-zero, non-undef, element.
6852 if (NumNonZero == 1) {
6853 unsigned Idx = countTrailingZeros(NonZeros);
6854 SDValue Item = Op.getOperand(Idx);
6856 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6857 // the value are obviously zero, truncate the value to i32 and do the
6858 // insertion that way. Only do this if the value is non-constant or if the
6859 // value is a constant being inserted into element 0. It is cheaper to do
6860 // a constant pool load than it is to do a movd + shuffle.
6861 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6862 (!IsAllConstants || Idx == 0)) {
6863 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6865 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6866 EVT VecVT = MVT::v4i32;
6867 unsigned VecElts = 4;
6869 // Truncate the value (which may itself be a constant) to i32, and
6870 // convert it to a vector with movd (S2V+shuffle to zero extend).
6871 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6872 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6874 // If using the new shuffle lowering, just directly insert this.
6875 if (ExperimentalVectorShuffleLowering)
6877 ISD::BITCAST, dl, VT,
6878 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6880 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6882 // Now we have our 32-bit value zero extended in the low element of
6883 // a vector. If Idx != 0, swizzle it into place.
6885 SmallVector<int, 4> Mask;
6886 Mask.push_back(Idx);
6887 for (unsigned i = 1; i != VecElts; ++i)
6889 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6892 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6896 // If we have a constant or non-constant insertion into the low element of
6897 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6898 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6899 // depending on what the source datatype is.
6902 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6904 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6905 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6906 if (VT.is256BitVector() || VT.is512BitVector()) {
6907 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6908 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6909 Item, DAG.getIntPtrConstant(0));
6911 assert(VT.is128BitVector() && "Expected an SSE value type!");
6912 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6913 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6914 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6917 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6918 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6919 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6920 if (VT.is256BitVector()) {
6921 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6922 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6924 assert(VT.is128BitVector() && "Expected an SSE value type!");
6925 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6927 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6931 // Is it a vector logical left shift?
6932 if (NumElems == 2 && Idx == 1 &&
6933 X86::isZeroNode(Op.getOperand(0)) &&
6934 !X86::isZeroNode(Op.getOperand(1))) {
6935 unsigned NumBits = VT.getSizeInBits();
6936 return getVShift(true, VT,
6937 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6938 VT, Op.getOperand(1)),
6939 NumBits/2, DAG, *this, dl);
6942 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6945 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6946 // is a non-constant being inserted into an element other than the low one,
6947 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6948 // movd/movss) to move this into the low element, then shuffle it into
6950 if (EVTBits == 32) {
6951 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6953 // If using the new shuffle lowering, just directly insert this.
6954 if (ExperimentalVectorShuffleLowering)
6955 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6957 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6958 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6959 SmallVector<int, 8> MaskVec;
6960 for (unsigned i = 0; i != NumElems; ++i)
6961 MaskVec.push_back(i == Idx ? 0 : 1);
6962 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6966 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6967 if (Values.size() == 1) {
6968 if (EVTBits == 32) {
6969 // Instead of a shuffle like this:
6970 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6971 // Check if it's possible to issue this instead.
6972 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6973 unsigned Idx = countTrailingZeros(NonZeros);
6974 SDValue Item = Op.getOperand(Idx);
6975 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6976 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6981 // A vector full of immediates; various special cases are already
6982 // handled, so this is best done with a single constant-pool load.
6986 // For AVX-length vectors, build the individual 128-bit pieces and use
6987 // shuffles to put them in place.
6988 if (VT.is256BitVector() || VT.is512BitVector()) {
6989 SmallVector<SDValue, 64> V;
6990 for (unsigned i = 0; i != NumElems; ++i)
6991 V.push_back(Op.getOperand(i));
6993 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6995 // Build both the lower and upper subvector.
6996 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6997 makeArrayRef(&V[0], NumElems/2));
6998 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6999 makeArrayRef(&V[NumElems / 2], NumElems/2));
7001 // Recreate the wider vector with the lower and upper part.
7002 if (VT.is256BitVector())
7003 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7004 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7007 // Let legalizer expand 2-wide build_vectors.
7008 if (EVTBits == 64) {
7009 if (NumNonZero == 1) {
7010 // One half is zero or undef.
7011 unsigned Idx = countTrailingZeros(NonZeros);
7012 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7013 Op.getOperand(Idx));
7014 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7019 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7020 if (EVTBits == 8 && NumElems == 16) {
7021 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7023 if (V.getNode()) return V;
7026 if (EVTBits == 16 && NumElems == 8) {
7027 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7029 if (V.getNode()) return V;
7032 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7033 if (EVTBits == 32 && NumElems == 4) {
7034 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7039 // If element VT is == 32 bits, turn it into a number of shuffles.
7040 SmallVector<SDValue, 8> V(NumElems);
7041 if (NumElems == 4 && NumZero > 0) {
7042 for (unsigned i = 0; i < 4; ++i) {
7043 bool isZero = !(NonZeros & (1 << i));
7045 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7047 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7050 for (unsigned i = 0; i < 2; ++i) {
7051 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7054 V[i] = V[i*2]; // Must be a zero vector.
7057 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7060 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7063 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7068 bool Reverse1 = (NonZeros & 0x3) == 2;
7069 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7073 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7074 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7076 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7079 if (Values.size() > 1 && VT.is128BitVector()) {
7080 // Check for a build vector of consecutive loads.
7081 for (unsigned i = 0; i < NumElems; ++i)
7082 V[i] = Op.getOperand(i);
7084 // Check for elements which are consecutive loads.
7085 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7089 // Check for a build vector from mostly shuffle plus few inserting.
7090 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7094 // For SSE 4.1, use insertps to put the high elements into the low element.
7095 if (getSubtarget()->hasSSE41()) {
7097 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7098 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7100 Result = DAG.getUNDEF(VT);
7102 for (unsigned i = 1; i < NumElems; ++i) {
7103 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7104 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7105 Op.getOperand(i), DAG.getIntPtrConstant(i));
7110 // Otherwise, expand into a number of unpckl*, start by extending each of
7111 // our (non-undef) elements to the full vector width with the element in the
7112 // bottom slot of the vector (which generates no code for SSE).
7113 for (unsigned i = 0; i < NumElems; ++i) {
7114 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7115 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7117 V[i] = DAG.getUNDEF(VT);
7120 // Next, we iteratively mix elements, e.g. for v4f32:
7121 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7122 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7123 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7124 unsigned EltStride = NumElems >> 1;
7125 while (EltStride != 0) {
7126 for (unsigned i = 0; i < EltStride; ++i) {
7127 // If V[i+EltStride] is undef and this is the first round of mixing,
7128 // then it is safe to just drop this shuffle: V[i] is already in the
7129 // right place, the one element (since it's the first round) being
7130 // inserted as undef can be dropped. This isn't safe for successive
7131 // rounds because they will permute elements within both vectors.
7132 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7133 EltStride == NumElems/2)
7136 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7145 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7146 // to create 256-bit vectors from two other 128-bit ones.
7147 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7149 MVT ResVT = Op.getSimpleValueType();
7151 assert((ResVT.is256BitVector() ||
7152 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7154 SDValue V1 = Op.getOperand(0);
7155 SDValue V2 = Op.getOperand(1);
7156 unsigned NumElems = ResVT.getVectorNumElements();
7157 if(ResVT.is256BitVector())
7158 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7160 if (Op.getNumOperands() == 4) {
7161 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7162 ResVT.getVectorNumElements()/2);
7163 SDValue V3 = Op.getOperand(2);
7164 SDValue V4 = Op.getOperand(3);
7165 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7166 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7168 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7171 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7172 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7173 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7174 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7175 Op.getNumOperands() == 4)));
7177 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7178 // from two other 128-bit ones.
7180 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7181 return LowerAVXCONCAT_VECTORS(Op, DAG);
7185 //===----------------------------------------------------------------------===//
7186 // Vector shuffle lowering
7188 // This is an experimental code path for lowering vector shuffles on x86. It is
7189 // designed to handle arbitrary vector shuffles and blends, gracefully
7190 // degrading performance as necessary. It works hard to recognize idiomatic
7191 // shuffles and lower them to optimal instruction patterns without leaving
7192 // a framework that allows reasonably efficient handling of all vector shuffle
7194 //===----------------------------------------------------------------------===//
7196 /// \brief Tiny helper function to identify a no-op mask.
7198 /// This is a somewhat boring predicate function. It checks whether the mask
7199 /// array input, which is assumed to be a single-input shuffle mask of the kind
7200 /// used by the X86 shuffle instructions (not a fully general
7201 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7202 /// in-place shuffle are 'no-op's.
7203 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7204 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7205 if (Mask[i] != -1 && Mask[i] != i)
7210 /// \brief Helper function to classify a mask as a single-input mask.
7212 /// This isn't a generic single-input test because in the vector shuffle
7213 /// lowering we canonicalize single inputs to be the first input operand. This
7214 /// means we can more quickly test for a single input by only checking whether
7215 /// an input from the second operand exists. We also assume that the size of
7216 /// mask corresponds to the size of the input vectors which isn't true in the
7217 /// fully general case.
7218 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7220 if (M >= (int)Mask.size())
7225 /// \brief Test whether there are elements crossing 128-bit lanes in this
7228 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7229 /// and we routinely test for these.
7230 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7231 int LaneSize = 128 / VT.getScalarSizeInBits();
7232 int Size = Mask.size();
7233 for (int i = 0; i < Size; ++i)
7234 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7239 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7241 /// This checks a shuffle mask to see if it is performing the same
7242 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7243 /// that it is also not lane-crossing. It may however involve a blend from the
7244 /// same lane of a second vector.
7246 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7247 /// non-trivial to compute in the face of undef lanes. The representation is
7248 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7249 /// entries from both V1 and V2 inputs to the wider mask.
7251 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7252 SmallVectorImpl<int> &RepeatedMask) {
7253 int LaneSize = 128 / VT.getScalarSizeInBits();
7254 RepeatedMask.resize(LaneSize, -1);
7255 int Size = Mask.size();
7256 for (int i = 0; i < Size; ++i) {
7259 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7260 // This entry crosses lanes, so there is no way to model this shuffle.
7263 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7264 if (RepeatedMask[i % LaneSize] == -1)
7265 // This is the first non-undef entry in this slot of a 128-bit lane.
7266 RepeatedMask[i % LaneSize] =
7267 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7268 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7269 // Found a mismatch with the repeated mask.
7275 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7276 // 2013 will allow us to use it as a non-type template parameter.
7279 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7281 /// See its documentation for details.
7282 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7283 if (Mask.size() != Args.size())
7285 for (int i = 0, e = Mask.size(); i < e; ++i) {
7286 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7287 if (Mask[i] != -1 && Mask[i] != *Args[i])
7295 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7298 /// This is a fast way to test a shuffle mask against a fixed pattern:
7300 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7302 /// It returns true if the mask is exactly as wide as the argument list, and
7303 /// each element of the mask is either -1 (signifying undef) or the value given
7304 /// in the argument.
7305 static const VariadicFunction1<
7306 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7308 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7310 /// This helper function produces an 8-bit shuffle immediate corresponding to
7311 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7312 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7315 /// NB: We rely heavily on "undef" masks preserving the input lane.
7316 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7317 SelectionDAG &DAG) {
7318 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7319 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7320 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7321 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7322 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7325 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7326 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7327 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7328 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7329 return DAG.getConstant(Imm, MVT::i8);
7332 /// \brief Try to emit a blend instruction for a shuffle.
7334 /// This doesn't do any checks for the availability of instructions for blending
7335 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7336 /// be matched in the backend with the type given. What it does check for is
7337 /// that the shuffle mask is in fact a blend.
7338 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7339 SDValue V2, ArrayRef<int> Mask,
7340 const X86Subtarget *Subtarget,
7341 SelectionDAG &DAG) {
7343 unsigned BlendMask = 0;
7344 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7345 if (Mask[i] >= Size) {
7346 if (Mask[i] != i + Size)
7347 return SDValue(); // Shuffled V2 input!
7348 BlendMask |= 1u << i;
7351 if (Mask[i] >= 0 && Mask[i] != i)
7352 return SDValue(); // Shuffled V1 input!
7354 switch (VT.SimpleTy) {
7359 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7360 DAG.getConstant(BlendMask, MVT::i8));
7364 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7368 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7369 // that instruction.
7370 if (Subtarget->hasAVX2()) {
7371 // Scale the blend by the number of 32-bit dwords per element.
7372 int Scale = VT.getScalarSizeInBits() / 32;
7374 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7375 if (Mask[i] >= Size)
7376 for (int j = 0; j < Scale; ++j)
7377 BlendMask |= 1u << (i * Scale + j);
7379 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7380 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7381 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7382 return DAG.getNode(ISD::BITCAST, DL, VT,
7383 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7384 DAG.getConstant(BlendMask, MVT::i8)));
7388 // For integer shuffles we need to expand the mask and cast the inputs to
7389 // v8i16s prior to blending.
7390 int Scale = 8 / VT.getVectorNumElements();
7392 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7393 if (Mask[i] >= Size)
7394 for (int j = 0; j < Scale; ++j)
7395 BlendMask |= 1u << (i * Scale + j);
7397 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7398 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7399 return DAG.getNode(ISD::BITCAST, DL, VT,
7400 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7401 DAG.getConstant(BlendMask, MVT::i8)));
7405 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7406 SmallVector<int, 8> RepeatedMask;
7407 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7408 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7409 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7411 for (int i = 0; i < 8; ++i)
7412 if (RepeatedMask[i] >= 16)
7413 BlendMask |= 1u << i;
7414 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7415 DAG.getConstant(BlendMask, MVT::i8));
7420 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7421 // Scale the blend by the number of bytes per element.
7422 int Scale = VT.getScalarSizeInBits() / 8;
7423 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7425 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7426 // mix of LLVM's code generator and the x86 backend. We tell the code
7427 // generator that boolean values in the elements of an x86 vector register
7428 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7429 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7430 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7431 // of the element (the remaining are ignored) and 0 in that high bit would
7432 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7433 // the LLVM model for boolean values in vector elements gets the relevant
7434 // bit set, it is set backwards and over constrained relative to x86's
7436 SDValue VSELECTMask[32];
7437 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7438 for (int j = 0; j < Scale; ++j)
7439 VSELECTMask[Scale * i + j] =
7440 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7441 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7443 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7444 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7446 ISD::BITCAST, DL, VT,
7447 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7448 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7453 llvm_unreachable("Not a supported integer vector type!");
7457 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7458 /// unblended shuffles followed by an unshuffled blend.
7460 /// This matches the extremely common pattern for handling combined
7461 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7463 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7467 SelectionDAG &DAG) {
7468 // Shuffle the input elements into the desired positions in V1 and V2 and
7469 // blend them together.
7470 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7471 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7472 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7473 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7474 if (Mask[i] >= 0 && Mask[i] < Size) {
7475 V1Mask[i] = Mask[i];
7477 } else if (Mask[i] >= Size) {
7478 V2Mask[i] = Mask[i] - Size;
7479 BlendMask[i] = i + Size;
7482 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7483 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7484 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7487 /// \brief Try to lower a vector shuffle as a byte rotation.
7489 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7490 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7491 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7492 /// try to generically lower a vector shuffle through such an pattern. It
7493 /// does not check for the profitability of lowering either as PALIGNR or
7494 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7495 /// This matches shuffle vectors that look like:
7497 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7499 /// Essentially it concatenates V1 and V2, shifts right by some number of
7500 /// elements, and takes the low elements as the result. Note that while this is
7501 /// specified as a *right shift* because x86 is little-endian, it is a *left
7502 /// rotate* of the vector lanes.
7504 /// Note that this only handles 128-bit vector widths currently.
7505 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7508 const X86Subtarget *Subtarget,
7509 SelectionDAG &DAG) {
7510 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7512 // We need to detect various ways of spelling a rotation:
7513 // [11, 12, 13, 14, 15, 0, 1, 2]
7514 // [-1, 12, 13, 14, -1, -1, 1, -1]
7515 // [-1, -1, -1, -1, -1, -1, 1, 2]
7516 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7517 // [-1, 4, 5, 6, -1, -1, 9, -1]
7518 // [-1, 4, 5, 6, -1, -1, -1, -1]
7521 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7524 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7526 // Based on the mod-Size value of this mask element determine where
7527 // a rotated vector would have started.
7528 int StartIdx = i - (Mask[i] % Size);
7530 // The identity rotation isn't interesting, stop.
7533 // If we found the tail of a vector the rotation must be the missing
7534 // front. If we found the head of a vector, it must be how much of the head.
7535 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7538 Rotation = CandidateRotation;
7539 else if (Rotation != CandidateRotation)
7540 // The rotations don't match, so we can't match this mask.
7543 // Compute which value this mask is pointing at.
7544 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7546 // Compute which of the two target values this index should be assigned to.
7547 // This reflects whether the high elements are remaining or the low elements
7549 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7551 // Either set up this value if we've not encountered it before, or check
7552 // that it remains consistent.
7555 else if (TargetV != MaskV)
7556 // This may be a rotation, but it pulls from the inputs in some
7557 // unsupported interleaving.
7561 // Check that we successfully analyzed the mask, and normalize the results.
7562 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7563 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7569 assert(VT.getSizeInBits() == 128 &&
7570 "Rotate-based lowering only supports 128-bit lowering!");
7571 assert(Mask.size() <= 16 &&
7572 "Can shuffle at most 16 bytes in a 128-bit vector!");
7574 // The actual rotate instruction rotates bytes, so we need to scale the
7575 // rotation based on how many bytes are in the vector.
7576 int Scale = 16 / Mask.size();
7578 // SSSE3 targets can use the palignr instruction
7579 if (Subtarget->hasSSSE3()) {
7580 // Cast the inputs to v16i8 to match PALIGNR.
7581 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7582 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7584 return DAG.getNode(ISD::BITCAST, DL, VT,
7585 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7586 DAG.getConstant(Rotation * Scale, MVT::i8)));
7589 // Default SSE2 implementation
7590 int LoByteShift = 16 - Rotation * Scale;
7591 int HiByteShift = Rotation * Scale;
7593 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7594 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7595 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7597 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7598 DAG.getConstant(8 * LoByteShift, MVT::i8));
7599 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7600 DAG.getConstant(8 * HiByteShift, MVT::i8));
7601 return DAG.getNode(ISD::BITCAST, DL, VT,
7602 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7605 /// \brief Compute whether each element of a shuffle is zeroable.
7607 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7608 /// Either it is an undef element in the shuffle mask, the element of the input
7609 /// referenced is undef, or the element of the input referenced is known to be
7610 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7611 /// as many lanes with this technique as possible to simplify the remaining
7613 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7614 SDValue V1, SDValue V2) {
7615 SmallBitVector Zeroable(Mask.size(), false);
7617 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7618 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7620 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7622 // Handle the easy cases.
7623 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7628 // If this is an index into a build_vector node, dig out the input value and
7630 SDValue V = M < Size ? V1 : V2;
7631 if (V.getOpcode() != ISD::BUILD_VECTOR)
7634 SDValue Input = V.getOperand(M % Size);
7635 // The UNDEF opcode check really should be dead code here, but not quite
7636 // worth asserting on (it isn't invalid, just unexpected).
7637 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7644 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7646 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7647 /// byte-shift instructions. The mask must consist of a shifted sequential
7648 /// shuffle from one of the input vectors and zeroable elements for the
7649 /// remaining 'shifted in' elements.
7651 /// Note that this only handles 128-bit vector widths currently.
7652 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7653 SDValue V2, ArrayRef<int> Mask,
7654 SelectionDAG &DAG) {
7655 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7657 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7659 int Size = Mask.size();
7660 int Scale = 16 / Size;
7662 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7663 ArrayRef<int> Mask) {
7664 for (int i = StartIndex; i < EndIndex; i++) {
7667 if (i + Base != Mask[i] - MaskOffset)
7673 for (int Shift = 1; Shift < Size; Shift++) {
7674 int ByteShift = Shift * Scale;
7676 // PSRLDQ : (little-endian) right byte shift
7677 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7678 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7679 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7680 bool ZeroableRight = true;
7681 for (int i = Size - Shift; i < Size; i++) {
7682 ZeroableRight &= Zeroable[i];
7685 if (ZeroableRight) {
7686 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7687 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7689 if (ValidShiftRight1 || ValidShiftRight2) {
7690 // Cast the inputs to v2i64 to match PSRLDQ.
7691 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7692 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7693 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7694 DAG.getConstant(ByteShift * 8, MVT::i8));
7695 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7699 // PSLLDQ : (little-endian) left byte shift
7700 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7701 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7702 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7703 bool ZeroableLeft = true;
7704 for (int i = 0; i < Shift; i++) {
7705 ZeroableLeft &= Zeroable[i];
7709 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7710 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7712 if (ValidShiftLeft1 || ValidShiftLeft2) {
7713 // Cast the inputs to v2i64 to match PSLLDQ.
7714 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7715 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7716 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7717 DAG.getConstant(ByteShift * 8, MVT::i8));
7718 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7726 /// \brief Lower a vector shuffle as a zero or any extension.
7728 /// Given a specific number of elements, element bit width, and extension
7729 /// stride, produce either a zero or any extension based on the available
7730 /// features of the subtarget.
7731 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7732 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7733 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7734 assert(Scale > 1 && "Need a scale to extend.");
7735 int EltBits = VT.getSizeInBits() / NumElements;
7736 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7737 "Only 8, 16, and 32 bit elements can be extended.");
7738 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7740 // Found a valid zext mask! Try various lowering strategies based on the
7741 // input type and available ISA extensions.
7742 if (Subtarget->hasSSE41()) {
7743 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7744 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7745 NumElements / Scale);
7746 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7747 return DAG.getNode(ISD::BITCAST, DL, VT,
7748 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7751 // For any extends we can cheat for larger element sizes and use shuffle
7752 // instructions that can fold with a load and/or copy.
7753 if (AnyExt && EltBits == 32) {
7754 int PSHUFDMask[4] = {0, -1, 1, -1};
7756 ISD::BITCAST, DL, VT,
7757 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7758 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7759 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7761 if (AnyExt && EltBits == 16 && Scale > 2) {
7762 int PSHUFDMask[4] = {0, -1, 0, -1};
7763 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7764 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7765 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7766 int PSHUFHWMask[4] = {1, -1, -1, -1};
7768 ISD::BITCAST, DL, VT,
7769 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7770 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7771 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7774 // If this would require more than 2 unpack instructions to expand, use
7775 // pshufb when available. We can only use more than 2 unpack instructions
7776 // when zero extending i8 elements which also makes it easier to use pshufb.
7777 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7778 assert(NumElements == 16 && "Unexpected byte vector width!");
7779 SDValue PSHUFBMask[16];
7780 for (int i = 0; i < 16; ++i)
7782 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7783 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7784 return DAG.getNode(ISD::BITCAST, DL, VT,
7785 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7786 DAG.getNode(ISD::BUILD_VECTOR, DL,
7787 MVT::v16i8, PSHUFBMask)));
7790 // Otherwise emit a sequence of unpacks.
7792 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7793 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7794 : getZeroVector(InputVT, Subtarget, DAG, DL);
7795 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7796 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7800 } while (Scale > 1);
7801 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7804 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7806 /// This routine will try to do everything in its power to cleverly lower
7807 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7808 /// check for the profitability of this lowering, it tries to aggressively
7809 /// match this pattern. It will use all of the micro-architectural details it
7810 /// can to emit an efficient lowering. It handles both blends with all-zero
7811 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7812 /// masking out later).
7814 /// The reason we have dedicated lowering for zext-style shuffles is that they
7815 /// are both incredibly common and often quite performance sensitive.
7816 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7817 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7818 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7819 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7821 int Bits = VT.getSizeInBits();
7822 int NumElements = Mask.size();
7824 // Define a helper function to check a particular ext-scale and lower to it if
7826 auto Lower = [&](int Scale) -> SDValue {
7829 for (int i = 0; i < NumElements; ++i) {
7831 continue; // Valid anywhere but doesn't tell us anything.
7832 if (i % Scale != 0) {
7833 // Each of the extend elements needs to be zeroable.
7837 // We no lorger are in the anyext case.
7842 // Each of the base elements needs to be consecutive indices into the
7843 // same input vector.
7844 SDValue V = Mask[i] < NumElements ? V1 : V2;
7847 else if (InputV != V)
7848 return SDValue(); // Flip-flopping inputs.
7850 if (Mask[i] % NumElements != i / Scale)
7851 return SDValue(); // Non-consecutive strided elemenst.
7854 // If we fail to find an input, we have a zero-shuffle which should always
7855 // have already been handled.
7856 // FIXME: Maybe handle this here in case during blending we end up with one?
7860 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7861 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7864 // The widest scale possible for extending is to a 64-bit integer.
7865 assert(Bits % 64 == 0 &&
7866 "The number of bits in a vector must be divisible by 64 on x86!");
7867 int NumExtElements = Bits / 64;
7869 // Each iteration, try extending the elements half as much, but into twice as
7871 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7872 assert(NumElements % NumExtElements == 0 &&
7873 "The input vector size must be divisble by the extended size.");
7874 if (SDValue V = Lower(NumElements / NumExtElements))
7878 // No viable ext lowering found.
7882 /// \brief Try to get a scalar value for a specific element of a vector.
7884 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7885 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7886 SelectionDAG &DAG) {
7887 MVT VT = V.getSimpleValueType();
7888 MVT EltVT = VT.getVectorElementType();
7889 while (V.getOpcode() == ISD::BITCAST)
7890 V = V.getOperand(0);
7891 // If the bitcasts shift the element size, we can't extract an equivalent
7893 MVT NewVT = V.getSimpleValueType();
7894 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7897 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7898 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7899 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7904 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7906 /// This is particularly important because the set of instructions varies
7907 /// significantly based on whether the operand is a load or not.
7908 static bool isShuffleFoldableLoad(SDValue V) {
7909 while (V.getOpcode() == ISD::BITCAST)
7910 V = V.getOperand(0);
7912 return ISD::isNON_EXTLoad(V.getNode());
7915 /// \brief Try to lower insertion of a single element into a zero vector.
7917 /// This is a common pattern that we have especially efficient patterns to lower
7918 /// across all subtarget feature sets.
7919 static SDValue lowerVectorShuffleAsElementInsertion(
7920 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7921 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7922 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7924 MVT EltVT = VT.getVectorElementType();
7926 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7927 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7929 bool IsV1Zeroable = true;
7930 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7931 if (i != V2Index && !Zeroable[i]) {
7932 IsV1Zeroable = false;
7936 // Check for a single input from a SCALAR_TO_VECTOR node.
7937 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7938 // all the smarts here sunk into that routine. However, the current
7939 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7940 // vector shuffle lowering is dead.
7941 if (SDValue V2S = getScalarValueForVectorElement(
7942 V2, Mask[V2Index] - Mask.size(), DAG)) {
7943 // We need to zext the scalar if it is smaller than an i32.
7944 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7945 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7946 // Using zext to expand a narrow element won't work for non-zero
7951 // Zero-extend directly to i32.
7953 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7955 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7956 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7957 EltVT == MVT::i16) {
7958 // Either not inserting from the low element of the input or the input
7959 // element size is too small to use VZEXT_MOVL to clear the high bits.
7963 if (!IsV1Zeroable) {
7964 // If V1 can't be treated as a zero vector we have fewer options to lower
7965 // this. We can't support integer vectors or non-zero targets cheaply, and
7966 // the V1 elements can't be permuted in any way.
7967 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7968 if (!VT.isFloatingPoint() || V2Index != 0)
7970 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7971 V1Mask[V2Index] = -1;
7972 if (!isNoopShuffleMask(V1Mask))
7974 // This is essentially a special case blend operation, but if we have
7975 // general purpose blend operations, they are always faster. Bail and let
7976 // the rest of the lowering handle these as blends.
7977 if (Subtarget->hasSSE41())
7980 // Otherwise, use MOVSD or MOVSS.
7981 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7982 "Only two types of floating point element types to handle!");
7983 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7987 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7989 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7992 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7993 // the desired position. Otherwise it is more efficient to do a vector
7994 // shift left. We know that we can do a vector shift left because all
7995 // the inputs are zero.
7996 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7997 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7998 V2Shuffle[V2Index] = 0;
7999 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8001 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8003 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8005 V2Index * EltVT.getSizeInBits(),
8006 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8007 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8013 /// \brief Try to lower broadcast of a single element.
8015 /// For convenience, this code also bundles all of the subtarget feature set
8016 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8017 /// a convenient way to factor it out.
8018 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8020 const X86Subtarget *Subtarget,
8021 SelectionDAG &DAG) {
8022 if (!Subtarget->hasAVX())
8024 if (VT.isInteger() && !Subtarget->hasAVX2())
8027 // Check that the mask is a broadcast.
8028 int BroadcastIdx = -1;
8030 if (M >= 0 && BroadcastIdx == -1)
8032 else if (M >= 0 && M != BroadcastIdx)
8035 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8036 "a sorted mask where the broadcast "
8039 // Go up the chain of (vector) values to try and find a scalar load that
8040 // we can combine with the broadcast.
8042 switch (V.getOpcode()) {
8043 case ISD::CONCAT_VECTORS: {
8044 int OperandSize = Mask.size() / V.getNumOperands();
8045 V = V.getOperand(BroadcastIdx / OperandSize);
8046 BroadcastIdx %= OperandSize;
8050 case ISD::INSERT_SUBVECTOR: {
8051 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8052 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8056 int BeginIdx = (int)ConstantIdx->getZExtValue();
8058 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8059 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8060 BroadcastIdx -= BeginIdx;
8071 // Check if this is a broadcast of a scalar. We special case lowering
8072 // for scalars so that we can more effectively fold with loads.
8073 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8074 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8075 V = V.getOperand(BroadcastIdx);
8077 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8079 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8081 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8082 // We can't broadcast from a vector register w/o AVX2, and we can only
8083 // broadcast from the zero-element of a vector register.
8087 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8090 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8092 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8093 /// support for floating point shuffles but not integer shuffles. These
8094 /// instructions will incur a domain crossing penalty on some chips though so
8095 /// it is better to avoid lowering through this for integer vectors where
8097 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8098 const X86Subtarget *Subtarget,
8099 SelectionDAG &DAG) {
8101 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8102 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8103 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8104 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8105 ArrayRef<int> Mask = SVOp->getMask();
8106 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8108 if (isSingleInputShuffleMask(Mask)) {
8109 // Straight shuffle of a single input vector. Simulate this by using the
8110 // single input as both of the "inputs" to this instruction..
8111 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8113 if (Subtarget->hasAVX()) {
8114 // If we have AVX, we can use VPERMILPS which will allow folding a load
8115 // into the shuffle.
8116 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8117 DAG.getConstant(SHUFPDMask, MVT::i8));
8120 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8121 DAG.getConstant(SHUFPDMask, MVT::i8));
8123 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8124 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8126 // Use dedicated unpack instructions for masks that match their pattern.
8127 if (isShuffleEquivalent(Mask, 0, 2))
8128 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8129 if (isShuffleEquivalent(Mask, 1, 3))
8130 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8132 // If we have a single input, insert that into V1 if we can do so cheaply.
8133 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8134 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8135 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8137 // Try inverting the insertion since for v2 masks it is easy to do and we
8138 // can't reliably sort the mask one way or the other.
8139 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8140 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8141 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8142 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8146 // Try to use one of the special instruction patterns to handle two common
8147 // blend patterns if a zero-blend above didn't work.
8148 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8149 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8150 // We can either use a special instruction to load over the low double or
8151 // to move just the low double.
8153 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8155 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8157 if (Subtarget->hasSSE41())
8158 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8162 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8163 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8164 DAG.getConstant(SHUFPDMask, MVT::i8));
8167 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8169 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8170 /// the integer unit to minimize domain crossing penalties. However, for blends
8171 /// it falls back to the floating point shuffle operation with appropriate bit
8173 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8174 const X86Subtarget *Subtarget,
8175 SelectionDAG &DAG) {
8177 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8178 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8179 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8180 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8181 ArrayRef<int> Mask = SVOp->getMask();
8182 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8184 if (isSingleInputShuffleMask(Mask)) {
8185 // Check for being able to broadcast a single element.
8186 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8187 Mask, Subtarget, DAG))
8190 // Straight shuffle of a single input vector. For everything from SSE2
8191 // onward this has a single fast instruction with no scary immediates.
8192 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8193 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8194 int WidenedMask[4] = {
8195 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8196 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8198 ISD::BITCAST, DL, MVT::v2i64,
8199 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8200 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8203 // If we have a single input from V2 insert that into V1 if we can do so
8205 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8206 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8207 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8209 // Try inverting the insertion since for v2 masks it is easy to do and we
8210 // can't reliably sort the mask one way or the other.
8211 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8212 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8213 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8214 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8218 // Use dedicated unpack instructions for masks that match their pattern.
8219 if (isShuffleEquivalent(Mask, 0, 2))
8220 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8221 if (isShuffleEquivalent(Mask, 1, 3))
8222 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8224 if (Subtarget->hasSSE41())
8225 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8229 // Try to use byte shift instructions.
8230 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8231 DL, MVT::v2i64, V1, V2, Mask, DAG))
8234 // Try to use byte rotation instructions.
8235 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8236 if (Subtarget->hasSSSE3())
8237 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8238 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8241 // We implement this with SHUFPD which is pretty lame because it will likely
8242 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8243 // However, all the alternatives are still more cycles and newer chips don't
8244 // have this problem. It would be really nice if x86 had better shuffles here.
8245 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8246 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8247 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8248 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8251 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8253 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8254 /// It makes no assumptions about whether this is the *best* lowering, it simply
8256 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8257 ArrayRef<int> Mask, SDValue V1,
8258 SDValue V2, SelectionDAG &DAG) {
8259 SDValue LowV = V1, HighV = V2;
8260 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8263 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8265 if (NumV2Elements == 1) {
8267 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8270 // Compute the index adjacent to V2Index and in the same half by toggling
8272 int V2AdjIndex = V2Index ^ 1;
8274 if (Mask[V2AdjIndex] == -1) {
8275 // Handles all the cases where we have a single V2 element and an undef.
8276 // This will only ever happen in the high lanes because we commute the
8277 // vector otherwise.
8279 std::swap(LowV, HighV);
8280 NewMask[V2Index] -= 4;
8282 // Handle the case where the V2 element ends up adjacent to a V1 element.
8283 // To make this work, blend them together as the first step.
8284 int V1Index = V2AdjIndex;
8285 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8286 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8287 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8289 // Now proceed to reconstruct the final blend as we have the necessary
8290 // high or low half formed.
8297 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8298 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8300 } else if (NumV2Elements == 2) {
8301 if (Mask[0] < 4 && Mask[1] < 4) {
8302 // Handle the easy case where we have V1 in the low lanes and V2 in the
8306 } else if (Mask[2] < 4 && Mask[3] < 4) {
8307 // We also handle the reversed case because this utility may get called
8308 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8309 // arrange things in the right direction.
8315 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8316 // trying to place elements directly, just blend them and set up the final
8317 // shuffle to place them.
8319 // The first two blend mask elements are for V1, the second two are for
8321 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8322 Mask[2] < 4 ? Mask[2] : Mask[3],
8323 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8324 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8325 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8326 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8328 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8331 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8332 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8333 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8334 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8337 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8338 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8341 /// \brief Lower 4-lane 32-bit floating point shuffles.
8343 /// Uses instructions exclusively from the floating point unit to minimize
8344 /// domain crossing penalties, as these are sufficient to implement all v4f32
8346 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8347 const X86Subtarget *Subtarget,
8348 SelectionDAG &DAG) {
8350 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8351 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8352 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8353 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8354 ArrayRef<int> Mask = SVOp->getMask();
8355 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8358 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8360 if (NumV2Elements == 0) {
8361 // Check for being able to broadcast a single element.
8362 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8363 Mask, Subtarget, DAG))
8366 if (Subtarget->hasAVX()) {
8367 // If we have AVX, we can use VPERMILPS which will allow folding a load
8368 // into the shuffle.
8369 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8370 getV4X86ShuffleImm8ForMask(Mask, DAG));
8373 // Otherwise, use a straight shuffle of a single input vector. We pass the
8374 // input vector to both operands to simulate this with a SHUFPS.
8375 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8376 getV4X86ShuffleImm8ForMask(Mask, DAG));
8379 // Use dedicated unpack instructions for masks that match their pattern.
8380 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8381 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8382 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8383 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8385 // There are special ways we can lower some single-element blends. However, we
8386 // have custom ways we can lower more complex single-element blends below that
8387 // we defer to if both this and BLENDPS fail to match, so restrict this to
8388 // when the V2 input is targeting element 0 of the mask -- that is the fast
8390 if (NumV2Elements == 1 && Mask[0] >= 4)
8391 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8392 Mask, Subtarget, DAG))
8395 if (Subtarget->hasSSE41())
8396 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8400 // Check for whether we can use INSERTPS to perform the blend. We only use
8401 // INSERTPS when the V1 elements are already in the correct locations
8402 // because otherwise we can just always use two SHUFPS instructions which
8403 // are much smaller to encode than a SHUFPS and an INSERTPS.
8404 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8406 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8409 // When using INSERTPS we can zero any lane of the destination. Collect
8410 // the zero inputs into a mask and drop them from the lanes of V1 which
8411 // actually need to be present as inputs to the INSERTPS.
8412 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8414 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8415 bool InsertNeedsShuffle = false;
8417 for (int i = 0; i < 4; ++i)
8421 } else if (Mask[i] != i) {
8422 InsertNeedsShuffle = true;
8427 // We don't want to use INSERTPS or other insertion techniques if it will
8428 // require shuffling anyways.
8429 if (!InsertNeedsShuffle) {
8430 // If all of V1 is zeroable, replace it with undef.
8431 if ((ZMask | 1 << V2Index) == 0xF)
8432 V1 = DAG.getUNDEF(MVT::v4f32);
8434 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8435 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8437 // Insert the V2 element into the desired position.
8438 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8439 DAG.getConstant(InsertPSMask, MVT::i8));
8443 // Otherwise fall back to a SHUFPS lowering strategy.
8444 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8447 /// \brief Lower 4-lane i32 vector shuffles.
8449 /// We try to handle these with integer-domain shuffles where we can, but for
8450 /// blends we use the floating point domain blend instructions.
8451 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8452 const X86Subtarget *Subtarget,
8453 SelectionDAG &DAG) {
8455 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8456 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8457 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8458 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8459 ArrayRef<int> Mask = SVOp->getMask();
8460 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8462 // Whenever we can lower this as a zext, that instruction is strictly faster
8463 // than any alternative. It also allows us to fold memory operands into the
8464 // shuffle in many cases.
8465 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8466 Mask, Subtarget, DAG))
8470 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8472 if (NumV2Elements == 0) {
8473 // Check for being able to broadcast a single element.
8474 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8475 Mask, Subtarget, DAG))
8478 // Straight shuffle of a single input vector. For everything from SSE2
8479 // onward this has a single fast instruction with no scary immediates.
8480 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8481 // but we aren't actually going to use the UNPCK instruction because doing
8482 // so prevents folding a load into this instruction or making a copy.
8483 const int UnpackLoMask[] = {0, 0, 1, 1};
8484 const int UnpackHiMask[] = {2, 2, 3, 3};
8485 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8486 Mask = UnpackLoMask;
8487 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8488 Mask = UnpackHiMask;
8490 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8491 getV4X86ShuffleImm8ForMask(Mask, DAG));
8494 // There are special ways we can lower some single-element blends.
8495 if (NumV2Elements == 1)
8496 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8497 Mask, Subtarget, DAG))
8500 // Use dedicated unpack instructions for masks that match their pattern.
8501 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8502 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8503 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8504 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8506 if (Subtarget->hasSSE41())
8507 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8511 // Try to use byte shift instructions.
8512 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8513 DL, MVT::v4i32, V1, V2, Mask, DAG))
8516 // Try to use byte rotation instructions.
8517 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8518 if (Subtarget->hasSSSE3())
8519 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8520 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8523 // We implement this with SHUFPS because it can blend from two vectors.
8524 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8525 // up the inputs, bypassing domain shift penalties that we would encur if we
8526 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8528 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8529 DAG.getVectorShuffle(
8531 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8532 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8535 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8536 /// shuffle lowering, and the most complex part.
8538 /// The lowering strategy is to try to form pairs of input lanes which are
8539 /// targeted at the same half of the final vector, and then use a dword shuffle
8540 /// to place them onto the right half, and finally unpack the paired lanes into
8541 /// their final position.
8543 /// The exact breakdown of how to form these dword pairs and align them on the
8544 /// correct sides is really tricky. See the comments within the function for
8545 /// more of the details.
8546 static SDValue lowerV8I16SingleInputVectorShuffle(
8547 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8548 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8549 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8550 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8551 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8553 SmallVector<int, 4> LoInputs;
8554 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8555 [](int M) { return M >= 0; });
8556 std::sort(LoInputs.begin(), LoInputs.end());
8557 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8558 SmallVector<int, 4> HiInputs;
8559 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8560 [](int M) { return M >= 0; });
8561 std::sort(HiInputs.begin(), HiInputs.end());
8562 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8564 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8565 int NumHToL = LoInputs.size() - NumLToL;
8567 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8568 int NumHToH = HiInputs.size() - NumLToH;
8569 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8570 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8571 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8572 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8574 // Check for being able to broadcast a single element.
8575 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8576 Mask, Subtarget, DAG))
8579 // Use dedicated unpack instructions for masks that match their pattern.
8580 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8581 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8582 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8583 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8585 // Try to use byte shift instructions.
8586 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8587 DL, MVT::v8i16, V, V, Mask, DAG))
8590 // Try to use byte rotation instructions.
8591 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8592 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8595 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8596 // such inputs we can swap two of the dwords across the half mark and end up
8597 // with <=2 inputs to each half in each half. Once there, we can fall through
8598 // to the generic code below. For example:
8600 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8601 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8603 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8604 // and an existing 2-into-2 on the other half. In this case we may have to
8605 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8606 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8607 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8608 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8609 // half than the one we target for fixing) will be fixed when we re-enter this
8610 // path. We will also combine away any sequence of PSHUFD instructions that
8611 // result into a single instruction. Here is an example of the tricky case:
8613 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8614 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8616 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8618 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8619 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8621 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8622 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8624 // The result is fine to be handled by the generic logic.
8625 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8626 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8627 int AOffset, int BOffset) {
8628 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8629 "Must call this with A having 3 or 1 inputs from the A half.");
8630 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8631 "Must call this with B having 1 or 3 inputs from the B half.");
8632 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8633 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8635 // Compute the index of dword with only one word among the three inputs in
8636 // a half by taking the sum of the half with three inputs and subtracting
8637 // the sum of the actual three inputs. The difference is the remaining
8640 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8641 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8642 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8643 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8644 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8645 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8646 int TripleNonInputIdx =
8647 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8648 TripleDWord = TripleNonInputIdx / 2;
8650 // We use xor with one to compute the adjacent DWord to whichever one the
8652 OneInputDWord = (OneInput / 2) ^ 1;
8654 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8655 // and BToA inputs. If there is also such a problem with the BToB and AToB
8656 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8657 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8658 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8659 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8660 // Compute how many inputs will be flipped by swapping these DWords. We
8662 // to balance this to ensure we don't form a 3-1 shuffle in the other
8664 int NumFlippedAToBInputs =
8665 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8666 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8667 int NumFlippedBToBInputs =
8668 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8669 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8670 if ((NumFlippedAToBInputs == 1 &&
8671 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8672 (NumFlippedBToBInputs == 1 &&
8673 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8674 // We choose whether to fix the A half or B half based on whether that
8675 // half has zero flipped inputs. At zero, we may not be able to fix it
8676 // with that half. We also bias towards fixing the B half because that
8677 // will more commonly be the high half, and we have to bias one way.
8678 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8679 ArrayRef<int> Inputs) {
8680 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8681 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8682 PinnedIdx ^ 1) != Inputs.end();
8683 // Determine whether the free index is in the flipped dword or the
8684 // unflipped dword based on where the pinned index is. We use this bit
8685 // in an xor to conditionally select the adjacent dword.
8686 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8687 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8688 FixFreeIdx) != Inputs.end();
8689 if (IsFixIdxInput == IsFixFreeIdxInput)
8691 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8692 FixFreeIdx) != Inputs.end();
8693 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8694 "We need to be changing the number of flipped inputs!");
8695 int PSHUFHalfMask[] = {0, 1, 2, 3};
8696 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8697 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8699 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8702 if (M != -1 && M == FixIdx)
8704 else if (M != -1 && M == FixFreeIdx)
8707 if (NumFlippedBToBInputs != 0) {
8709 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8710 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8712 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8714 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8715 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8720 int PSHUFDMask[] = {0, 1, 2, 3};
8721 PSHUFDMask[ADWord] = BDWord;
8722 PSHUFDMask[BDWord] = ADWord;
8723 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8724 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8725 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8726 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8728 // Adjust the mask to match the new locations of A and B.
8730 if (M != -1 && M/2 == ADWord)
8731 M = 2 * BDWord + M % 2;
8732 else if (M != -1 && M/2 == BDWord)
8733 M = 2 * ADWord + M % 2;
8735 // Recurse back into this routine to re-compute state now that this isn't
8736 // a 3 and 1 problem.
8737 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8740 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8741 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8742 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8743 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8745 // At this point there are at most two inputs to the low and high halves from
8746 // each half. That means the inputs can always be grouped into dwords and
8747 // those dwords can then be moved to the correct half with a dword shuffle.
8748 // We use at most one low and one high word shuffle to collect these paired
8749 // inputs into dwords, and finally a dword shuffle to place them.
8750 int PSHUFLMask[4] = {-1, -1, -1, -1};
8751 int PSHUFHMask[4] = {-1, -1, -1, -1};
8752 int PSHUFDMask[4] = {-1, -1, -1, -1};
8754 // First fix the masks for all the inputs that are staying in their
8755 // original halves. This will then dictate the targets of the cross-half
8757 auto fixInPlaceInputs =
8758 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8759 MutableArrayRef<int> SourceHalfMask,
8760 MutableArrayRef<int> HalfMask, int HalfOffset) {
8761 if (InPlaceInputs.empty())
8763 if (InPlaceInputs.size() == 1) {
8764 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8765 InPlaceInputs[0] - HalfOffset;
8766 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8769 if (IncomingInputs.empty()) {
8770 // Just fix all of the in place inputs.
8771 for (int Input : InPlaceInputs) {
8772 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8773 PSHUFDMask[Input / 2] = Input / 2;
8778 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8779 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8780 InPlaceInputs[0] - HalfOffset;
8781 // Put the second input next to the first so that they are packed into
8782 // a dword. We find the adjacent index by toggling the low bit.
8783 int AdjIndex = InPlaceInputs[0] ^ 1;
8784 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8785 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8786 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8788 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8789 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8791 // Now gather the cross-half inputs and place them into a free dword of
8792 // their target half.
8793 // FIXME: This operation could almost certainly be simplified dramatically to
8794 // look more like the 3-1 fixing operation.
8795 auto moveInputsToRightHalf = [&PSHUFDMask](
8796 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8797 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8798 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8800 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8801 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8803 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8805 int LowWord = Word & ~1;
8806 int HighWord = Word | 1;
8807 return isWordClobbered(SourceHalfMask, LowWord) ||
8808 isWordClobbered(SourceHalfMask, HighWord);
8811 if (IncomingInputs.empty())
8814 if (ExistingInputs.empty()) {
8815 // Map any dwords with inputs from them into the right half.
8816 for (int Input : IncomingInputs) {
8817 // If the source half mask maps over the inputs, turn those into
8818 // swaps and use the swapped lane.
8819 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8820 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8821 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8822 Input - SourceOffset;
8823 // We have to swap the uses in our half mask in one sweep.
8824 for (int &M : HalfMask)
8825 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8827 else if (M == Input)
8828 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8830 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8831 Input - SourceOffset &&
8832 "Previous placement doesn't match!");
8834 // Note that this correctly re-maps both when we do a swap and when
8835 // we observe the other side of the swap above. We rely on that to
8836 // avoid swapping the members of the input list directly.
8837 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8840 // Map the input's dword into the correct half.
8841 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8842 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8844 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8846 "Previous placement doesn't match!");
8849 // And just directly shift any other-half mask elements to be same-half
8850 // as we will have mirrored the dword containing the element into the
8851 // same position within that half.
8852 for (int &M : HalfMask)
8853 if (M >= SourceOffset && M < SourceOffset + 4) {
8854 M = M - SourceOffset + DestOffset;
8855 assert(M >= 0 && "This should never wrap below zero!");
8860 // Ensure we have the input in a viable dword of its current half. This
8861 // is particularly tricky because the original position may be clobbered
8862 // by inputs being moved and *staying* in that half.
8863 if (IncomingInputs.size() == 1) {
8864 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8865 int InputFixed = std::find(std::begin(SourceHalfMask),
8866 std::end(SourceHalfMask), -1) -
8867 std::begin(SourceHalfMask) + SourceOffset;
8868 SourceHalfMask[InputFixed - SourceOffset] =
8869 IncomingInputs[0] - SourceOffset;
8870 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8872 IncomingInputs[0] = InputFixed;
8874 } else if (IncomingInputs.size() == 2) {
8875 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8876 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8877 // We have two non-adjacent or clobbered inputs we need to extract from
8878 // the source half. To do this, we need to map them into some adjacent
8879 // dword slot in the source mask.
8880 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8881 IncomingInputs[1] - SourceOffset};
8883 // If there is a free slot in the source half mask adjacent to one of
8884 // the inputs, place the other input in it. We use (Index XOR 1) to
8885 // compute an adjacent index.
8886 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8887 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8888 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8889 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8890 InputsFixed[1] = InputsFixed[0] ^ 1;
8891 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8892 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8893 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8894 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8895 InputsFixed[0] = InputsFixed[1] ^ 1;
8896 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8897 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8898 // The two inputs are in the same DWord but it is clobbered and the
8899 // adjacent DWord isn't used at all. Move both inputs to the free
8901 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8902 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8903 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8904 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8906 // The only way we hit this point is if there is no clobbering
8907 // (because there are no off-half inputs to this half) and there is no
8908 // free slot adjacent to one of the inputs. In this case, we have to
8909 // swap an input with a non-input.
8910 for (int i = 0; i < 4; ++i)
8911 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8912 "We can't handle any clobbers here!");
8913 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8914 "Cannot have adjacent inputs here!");
8916 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8917 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8919 // We also have to update the final source mask in this case because
8920 // it may need to undo the above swap.
8921 for (int &M : FinalSourceHalfMask)
8922 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8923 M = InputsFixed[1] + SourceOffset;
8924 else if (M == InputsFixed[1] + SourceOffset)
8925 M = (InputsFixed[0] ^ 1) + SourceOffset;
8927 InputsFixed[1] = InputsFixed[0] ^ 1;
8930 // Point everything at the fixed inputs.
8931 for (int &M : HalfMask)
8932 if (M == IncomingInputs[0])
8933 M = InputsFixed[0] + SourceOffset;
8934 else if (M == IncomingInputs[1])
8935 M = InputsFixed[1] + SourceOffset;
8937 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8938 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8941 llvm_unreachable("Unhandled input size!");
8944 // Now hoist the DWord down to the right half.
8945 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8946 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8947 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8948 for (int &M : HalfMask)
8949 for (int Input : IncomingInputs)
8951 M = FreeDWord * 2 + Input % 2;
8953 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8954 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8955 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8956 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8958 // Now enact all the shuffles we've computed to move the inputs into their
8960 if (!isNoopShuffleMask(PSHUFLMask))
8961 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8962 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8963 if (!isNoopShuffleMask(PSHUFHMask))
8964 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8965 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8966 if (!isNoopShuffleMask(PSHUFDMask))
8967 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8968 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8969 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8970 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8972 // At this point, each half should contain all its inputs, and we can then
8973 // just shuffle them into their final position.
8974 assert(std::count_if(LoMask.begin(), LoMask.end(),
8975 [](int M) { return M >= 4; }) == 0 &&
8976 "Failed to lift all the high half inputs to the low mask!");
8977 assert(std::count_if(HiMask.begin(), HiMask.end(),
8978 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8979 "Failed to lift all the low half inputs to the high mask!");
8981 // Do a half shuffle for the low mask.
8982 if (!isNoopShuffleMask(LoMask))
8983 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8984 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8986 // Do a half shuffle with the high mask after shifting its values down.
8987 for (int &M : HiMask)
8990 if (!isNoopShuffleMask(HiMask))
8991 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8992 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8997 /// \brief Detect whether the mask pattern should be lowered through
9000 /// This essentially tests whether viewing the mask as an interleaving of two
9001 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9002 /// lowering it through interleaving is a significantly better strategy.
9003 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9004 int NumEvenInputs[2] = {0, 0};
9005 int NumOddInputs[2] = {0, 0};
9006 int NumLoInputs[2] = {0, 0};
9007 int NumHiInputs[2] = {0, 0};
9008 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9012 int InputIdx = Mask[i] >= Size;
9015 ++NumLoInputs[InputIdx];
9017 ++NumHiInputs[InputIdx];
9020 ++NumEvenInputs[InputIdx];
9022 ++NumOddInputs[InputIdx];
9025 // The minimum number of cross-input results for both the interleaved and
9026 // split cases. If interleaving results in fewer cross-input results, return
9028 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9029 NumEvenInputs[0] + NumOddInputs[1]);
9030 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9031 NumLoInputs[0] + NumHiInputs[1]);
9032 return InterleavedCrosses < SplitCrosses;
9035 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9037 /// This strategy only works when the inputs from each vector fit into a single
9038 /// half of that vector, and generally there are not so many inputs as to leave
9039 /// the in-place shuffles required highly constrained (and thus expensive). It
9040 /// shifts all the inputs into a single side of both input vectors and then
9041 /// uses an unpack to interleave these inputs in a single vector. At that
9042 /// point, we will fall back on the generic single input shuffle lowering.
9043 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9045 MutableArrayRef<int> Mask,
9046 const X86Subtarget *Subtarget,
9047 SelectionDAG &DAG) {
9048 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9049 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9050 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9051 for (int i = 0; i < 8; ++i)
9052 if (Mask[i] >= 0 && Mask[i] < 4)
9053 LoV1Inputs.push_back(i);
9054 else if (Mask[i] >= 4 && Mask[i] < 8)
9055 HiV1Inputs.push_back(i);
9056 else if (Mask[i] >= 8 && Mask[i] < 12)
9057 LoV2Inputs.push_back(i);
9058 else if (Mask[i] >= 12)
9059 HiV2Inputs.push_back(i);
9061 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9062 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9065 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9066 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9067 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9069 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9070 HiV1Inputs.size() + HiV2Inputs.size();
9072 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9073 ArrayRef<int> HiInputs, bool MoveToLo,
9075 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9076 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9077 if (BadInputs.empty())
9080 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9081 int MoveOffset = MoveToLo ? 0 : 4;
9083 if (GoodInputs.empty()) {
9084 for (int BadInput : BadInputs) {
9085 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9086 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9089 if (GoodInputs.size() == 2) {
9090 // If the low inputs are spread across two dwords, pack them into
9092 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9093 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9094 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9095 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9097 // Otherwise pin the good inputs.
9098 for (int GoodInput : GoodInputs)
9099 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9102 if (BadInputs.size() == 2) {
9103 // If we have two bad inputs then there may be either one or two good
9104 // inputs fixed in place. Find a fixed input, and then find the *other*
9105 // two adjacent indices by using modular arithmetic.
9107 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9108 [](int M) { return M >= 0; }) -
9109 std::begin(MoveMask);
9111 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9112 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9113 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9114 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9115 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9116 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9117 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9119 assert(BadInputs.size() == 1 && "All sizes handled");
9120 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9121 std::end(MoveMask), -1) -
9122 std::begin(MoveMask);
9123 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9124 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9128 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9131 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9133 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9136 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9137 // cross-half traffic in the final shuffle.
9139 // Munge the mask to be a single-input mask after the unpack merges the
9143 M = 2 * (M % 4) + (M / 8);
9145 return DAG.getVectorShuffle(
9146 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9147 DL, MVT::v8i16, V1, V2),
9148 DAG.getUNDEF(MVT::v8i16), Mask);
9151 /// \brief Generic lowering of 8-lane i16 shuffles.
9153 /// This handles both single-input shuffles and combined shuffle/blends with
9154 /// two inputs. The single input shuffles are immediately delegated to
9155 /// a dedicated lowering routine.
9157 /// The blends are lowered in one of three fundamental ways. If there are few
9158 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9159 /// of the input is significantly cheaper when lowered as an interleaving of
9160 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9161 /// halves of the inputs separately (making them have relatively few inputs)
9162 /// and then concatenate them.
9163 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9164 const X86Subtarget *Subtarget,
9165 SelectionDAG &DAG) {
9167 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9168 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9169 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9170 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9171 ArrayRef<int> OrigMask = SVOp->getMask();
9172 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9173 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9174 MutableArrayRef<int> Mask(MaskStorage);
9176 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9178 // Whenever we can lower this as a zext, that instruction is strictly faster
9179 // than any alternative.
9180 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9181 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9184 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9185 auto isV2 = [](int M) { return M >= 8; };
9187 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9188 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9190 if (NumV2Inputs == 0)
9191 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9193 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9194 "to be V1-input shuffles.");
9196 // There are special ways we can lower some single-element blends.
9197 if (NumV2Inputs == 1)
9198 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9199 Mask, Subtarget, DAG))
9202 // Use dedicated unpack instructions for masks that match their pattern.
9203 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9204 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9205 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9206 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9208 if (Subtarget->hasSSE41())
9209 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9213 // Try to use byte shift instructions.
9214 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9215 DL, MVT::v8i16, V1, V2, Mask, DAG))
9218 // Try to use byte rotation instructions.
9219 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9220 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9223 if (NumV1Inputs + NumV2Inputs <= 4)
9224 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9226 // Check whether an interleaving lowering is likely to be more efficient.
9227 // This isn't perfect but it is a strong heuristic that tends to work well on
9228 // the kinds of shuffles that show up in practice.
9230 // FIXME: Handle 1x, 2x, and 4x interleaving.
9231 if (shouldLowerAsInterleaving(Mask)) {
9232 // FIXME: Figure out whether we should pack these into the low or high
9235 int EMask[8], OMask[8];
9236 for (int i = 0; i < 4; ++i) {
9237 EMask[i] = Mask[2*i];
9238 OMask[i] = Mask[2*i + 1];
9243 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9244 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9246 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9249 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9250 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9252 for (int i = 0; i < 4; ++i) {
9253 LoBlendMask[i] = Mask[i];
9254 HiBlendMask[i] = Mask[i + 4];
9257 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9258 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9259 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9260 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9262 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9263 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9266 /// \brief Check whether a compaction lowering can be done by dropping even
9267 /// elements and compute how many times even elements must be dropped.
9269 /// This handles shuffles which take every Nth element where N is a power of
9270 /// two. Example shuffle masks:
9272 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9273 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9274 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9275 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9276 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9277 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9279 /// Any of these lanes can of course be undef.
9281 /// This routine only supports N <= 3.
9282 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9285 /// \returns N above, or the number of times even elements must be dropped if
9286 /// there is such a number. Otherwise returns zero.
9287 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9288 // Figure out whether we're looping over two inputs or just one.
9289 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9291 // The modulus for the shuffle vector entries is based on whether this is
9292 // a single input or not.
9293 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9294 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9295 "We should only be called with masks with a power-of-2 size!");
9297 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9299 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9300 // and 2^3 simultaneously. This is because we may have ambiguity with
9301 // partially undef inputs.
9302 bool ViableForN[3] = {true, true, true};
9304 for (int i = 0, e = Mask.size(); i < e; ++i) {
9305 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9310 bool IsAnyViable = false;
9311 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9312 if (ViableForN[j]) {
9315 // The shuffle mask must be equal to (i * 2^N) % M.
9316 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9319 ViableForN[j] = false;
9321 // Early exit if we exhaust the possible powers of two.
9326 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9330 // Return 0 as there is no viable power of two.
9334 /// \brief Generic lowering of v16i8 shuffles.
9336 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9337 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9338 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9339 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9341 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9342 const X86Subtarget *Subtarget,
9343 SelectionDAG &DAG) {
9345 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9346 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9347 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9348 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9349 ArrayRef<int> OrigMask = SVOp->getMask();
9350 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9352 // Try to use byte shift instructions.
9353 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9354 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9357 // Try to use byte rotation instructions.
9358 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9359 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9362 // Try to use a zext lowering.
9363 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9364 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9367 int MaskStorage[16] = {
9368 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9369 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9370 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9371 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9372 MutableArrayRef<int> Mask(MaskStorage);
9373 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9374 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9377 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9379 // For single-input shuffles, there are some nicer lowering tricks we can use.
9380 if (NumV2Elements == 0) {
9381 // Check for being able to broadcast a single element.
9382 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9383 Mask, Subtarget, DAG))
9386 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9387 // Notably, this handles splat and partial-splat shuffles more efficiently.
9388 // However, it only makes sense if the pre-duplication shuffle simplifies
9389 // things significantly. Currently, this means we need to be able to
9390 // express the pre-duplication shuffle as an i16 shuffle.
9392 // FIXME: We should check for other patterns which can be widened into an
9393 // i16 shuffle as well.
9394 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9395 for (int i = 0; i < 16; i += 2)
9396 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9401 auto tryToWidenViaDuplication = [&]() -> SDValue {
9402 if (!canWidenViaDuplication(Mask))
9404 SmallVector<int, 4> LoInputs;
9405 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9406 [](int M) { return M >= 0 && M < 8; });
9407 std::sort(LoInputs.begin(), LoInputs.end());
9408 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9410 SmallVector<int, 4> HiInputs;
9411 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9412 [](int M) { return M >= 8; });
9413 std::sort(HiInputs.begin(), HiInputs.end());
9414 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9417 bool TargetLo = LoInputs.size() >= HiInputs.size();
9418 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9419 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9421 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9422 SmallDenseMap<int, int, 8> LaneMap;
9423 for (int I : InPlaceInputs) {
9424 PreDupI16Shuffle[I/2] = I/2;
9427 int j = TargetLo ? 0 : 4, je = j + 4;
9428 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9429 // Check if j is already a shuffle of this input. This happens when
9430 // there are two adjacent bytes after we move the low one.
9431 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9432 // If we haven't yet mapped the input, search for a slot into which
9434 while (j < je && PreDupI16Shuffle[j] != -1)
9438 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9441 // Map this input with the i16 shuffle.
9442 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9445 // Update the lane map based on the mapping we ended up with.
9446 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9449 ISD::BITCAST, DL, MVT::v16i8,
9450 DAG.getVectorShuffle(MVT::v8i16, DL,
9451 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9452 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9454 // Unpack the bytes to form the i16s that will be shuffled into place.
9455 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9456 MVT::v16i8, V1, V1);
9458 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9459 for (int i = 0; i < 16; ++i)
9460 if (Mask[i] != -1) {
9461 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9462 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9463 if (PostDupI16Shuffle[i / 2] == -1)
9464 PostDupI16Shuffle[i / 2] = MappedMask;
9466 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9467 "Conflicting entrties in the original shuffle!");
9470 ISD::BITCAST, DL, MVT::v16i8,
9471 DAG.getVectorShuffle(MVT::v8i16, DL,
9472 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9473 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9475 if (SDValue V = tryToWidenViaDuplication())
9479 // Check whether an interleaving lowering is likely to be more efficient.
9480 // This isn't perfect but it is a strong heuristic that tends to work well on
9481 // the kinds of shuffles that show up in practice.
9483 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9484 if (shouldLowerAsInterleaving(Mask)) {
9485 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9486 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9488 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9489 return (M >= 8 && M < 16) || M >= 24;
9491 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9492 -1, -1, -1, -1, -1, -1, -1, -1};
9493 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9494 -1, -1, -1, -1, -1, -1, -1, -1};
9495 bool UnpackLo = NumLoHalf >= NumHiHalf;
9496 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9497 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9498 for (int i = 0; i < 8; ++i) {
9499 TargetEMask[i] = Mask[2 * i];
9500 TargetOMask[i] = Mask[2 * i + 1];
9503 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9504 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9506 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9507 MVT::v16i8, Evens, Odds);
9510 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9511 // with PSHUFB. It is important to do this before we attempt to generate any
9512 // blends but after all of the single-input lowerings. If the single input
9513 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9514 // want to preserve that and we can DAG combine any longer sequences into
9515 // a PSHUFB in the end. But once we start blending from multiple inputs,
9516 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9517 // and there are *very* few patterns that would actually be faster than the
9518 // PSHUFB approach because of its ability to zero lanes.
9520 // FIXME: The only exceptions to the above are blends which are exact
9521 // interleavings with direct instructions supporting them. We currently don't
9522 // handle those well here.
9523 if (Subtarget->hasSSSE3()) {
9526 for (int i = 0; i < 16; ++i)
9527 if (Mask[i] == -1) {
9528 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9530 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9532 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9534 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9535 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9536 if (isSingleInputShuffleMask(Mask))
9537 return V1; // Single inputs are easy.
9539 // Otherwise, blend the two.
9540 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9541 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9542 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9545 // There are special ways we can lower some single-element blends.
9546 if (NumV2Elements == 1)
9547 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9548 Mask, Subtarget, DAG))
9551 // Check whether a compaction lowering can be done. This handles shuffles
9552 // which take every Nth element for some even N. See the helper function for
9555 // We special case these as they can be particularly efficiently handled with
9556 // the PACKUSB instruction on x86 and they show up in common patterns of
9557 // rearranging bytes to truncate wide elements.
9558 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9559 // NumEvenDrops is the power of two stride of the elements. Another way of
9560 // thinking about it is that we need to drop the even elements this many
9561 // times to get the original input.
9562 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9564 // First we need to zero all the dropped bytes.
9565 assert(NumEvenDrops <= 3 &&
9566 "No support for dropping even elements more than 3 times.");
9567 // We use the mask type to pick which bytes are preserved based on how many
9568 // elements are dropped.
9569 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9570 SDValue ByteClearMask =
9571 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9572 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9573 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9575 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9577 // Now pack things back together.
9578 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9579 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9580 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9581 for (int i = 1; i < NumEvenDrops; ++i) {
9582 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9583 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9589 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9590 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9591 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9592 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9594 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9595 MutableArrayRef<int> V1HalfBlendMask,
9596 MutableArrayRef<int> V2HalfBlendMask) {
9597 for (int i = 0; i < 8; ++i)
9598 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9599 V1HalfBlendMask[i] = HalfMask[i];
9601 } else if (HalfMask[i] >= 16) {
9602 V2HalfBlendMask[i] = HalfMask[i] - 16;
9603 HalfMask[i] = i + 8;
9606 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9607 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9609 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9611 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9612 MutableArrayRef<int> HiBlendMask) {
9614 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9615 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9617 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9618 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9619 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9620 [](int M) { return M >= 0 && M % 2 == 1; })) {
9621 // Use a mask to drop the high bytes.
9622 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9623 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9624 DAG.getConstant(0x00FF, MVT::v8i16));
9626 // This will be a single vector shuffle instead of a blend so nuke V2.
9627 V2 = DAG.getUNDEF(MVT::v8i16);
9629 // Squash the masks to point directly into V1.
9630 for (int &M : LoBlendMask)
9633 for (int &M : HiBlendMask)
9637 // Otherwise just unpack the low half of V into V1 and the high half into
9638 // V2 so that we can blend them as i16s.
9639 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9640 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9641 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9642 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9645 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9646 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9647 return std::make_pair(BlendedLo, BlendedHi);
9649 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9650 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9651 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9653 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9654 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9656 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9659 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9661 /// This routine breaks down the specific type of 128-bit shuffle and
9662 /// dispatches to the lowering routines accordingly.
9663 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9664 MVT VT, const X86Subtarget *Subtarget,
9665 SelectionDAG &DAG) {
9666 switch (VT.SimpleTy) {
9668 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9670 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9672 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9674 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9676 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9678 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9681 llvm_unreachable("Unimplemented!");
9685 /// \brief Helper function to test whether a shuffle mask could be
9686 /// simplified by widening the elements being shuffled.
9688 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9689 /// leaves it in an unspecified state.
9691 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9692 /// shuffle masks. The latter have the special property of a '-2' representing
9693 /// a zero-ed lane of a vector.
9694 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9695 SmallVectorImpl<int> &WidenedMask) {
9696 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9697 // If both elements are undef, its trivial.
9698 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9699 WidenedMask.push_back(SM_SentinelUndef);
9703 // Check for an undef mask and a mask value properly aligned to fit with
9704 // a pair of values. If we find such a case, use the non-undef mask's value.
9705 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9706 WidenedMask.push_back(Mask[i + 1] / 2);
9709 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9710 WidenedMask.push_back(Mask[i] / 2);
9714 // When zeroing, we need to spread the zeroing across both lanes to widen.
9715 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9716 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9717 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9718 WidenedMask.push_back(SM_SentinelZero);
9724 // Finally check if the two mask values are adjacent and aligned with
9726 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9727 WidenedMask.push_back(Mask[i] / 2);
9731 // Otherwise we can't safely widen the elements used in this shuffle.
9734 assert(WidenedMask.size() == Mask.size() / 2 &&
9735 "Incorrect size of mask after widening the elements!");
9740 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9742 /// This routine just extracts two subvectors, shuffles them independently, and
9743 /// then concatenates them back together. This should work effectively with all
9744 /// AVX vector shuffle types.
9745 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9746 SDValue V2, ArrayRef<int> Mask,
9747 SelectionDAG &DAG) {
9748 assert(VT.getSizeInBits() >= 256 &&
9749 "Only for 256-bit or wider vector shuffles!");
9750 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9751 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9753 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9754 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9756 int NumElements = VT.getVectorNumElements();
9757 int SplitNumElements = NumElements / 2;
9758 MVT ScalarVT = VT.getScalarType();
9759 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9761 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9762 DAG.getIntPtrConstant(0));
9763 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9764 DAG.getIntPtrConstant(SplitNumElements));
9765 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9766 DAG.getIntPtrConstant(0));
9767 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9768 DAG.getIntPtrConstant(SplitNumElements));
9770 // Now create two 4-way blends of these half-width vectors.
9771 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9772 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9773 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9774 for (int i = 0; i < SplitNumElements; ++i) {
9775 int M = HalfMask[i];
9776 if (M >= NumElements) {
9777 if (M >= NumElements + SplitNumElements)
9781 V2BlendMask.push_back(M - NumElements);
9782 V1BlendMask.push_back(-1);
9783 BlendMask.push_back(SplitNumElements + i);
9784 } else if (M >= 0) {
9785 if (M >= SplitNumElements)
9789 V2BlendMask.push_back(-1);
9790 V1BlendMask.push_back(M);
9791 BlendMask.push_back(i);
9793 V2BlendMask.push_back(-1);
9794 V1BlendMask.push_back(-1);
9795 BlendMask.push_back(-1);
9799 // Because the lowering happens after all combining takes place, we need to
9800 // manually combine these blend masks as much as possible so that we create
9801 // a minimal number of high-level vector shuffle nodes.
9803 // First try just blending the halves of V1 or V2.
9804 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9805 return DAG.getUNDEF(SplitVT);
9806 if (!UseLoV2 && !UseHiV2)
9807 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9808 if (!UseLoV1 && !UseHiV1)
9809 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9811 SDValue V1Blend, V2Blend;
9812 if (UseLoV1 && UseHiV1) {
9814 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9816 // We only use half of V1 so map the usage down into the final blend mask.
9817 V1Blend = UseLoV1 ? LoV1 : HiV1;
9818 for (int i = 0; i < SplitNumElements; ++i)
9819 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9820 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9822 if (UseLoV2 && UseHiV2) {
9824 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9826 // We only use half of V2 so map the usage down into the final blend mask.
9827 V2Blend = UseLoV2 ? LoV2 : HiV2;
9828 for (int i = 0; i < SplitNumElements; ++i)
9829 if (BlendMask[i] >= SplitNumElements)
9830 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9832 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9834 SDValue Lo = HalfBlend(LoMask);
9835 SDValue Hi = HalfBlend(HiMask);
9836 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9839 /// \brief Either split a vector in halves or decompose the shuffles and the
9842 /// This is provided as a good fallback for many lowerings of non-single-input
9843 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9844 /// between splitting the shuffle into 128-bit components and stitching those
9845 /// back together vs. extracting the single-input shuffles and blending those
9847 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9848 SDValue V2, ArrayRef<int> Mask,
9849 SelectionDAG &DAG) {
9850 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9851 "lower single-input shuffles as it "
9852 "could then recurse on itself.");
9853 int Size = Mask.size();
9855 // If this can be modeled as a broadcast of two elements followed by a blend,
9856 // prefer that lowering. This is especially important because broadcasts can
9857 // often fold with memory operands.
9858 auto DoBothBroadcast = [&] {
9859 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9862 if (V2BroadcastIdx == -1)
9863 V2BroadcastIdx = M - Size;
9864 else if (M - Size != V2BroadcastIdx)
9866 } else if (M >= 0) {
9867 if (V1BroadcastIdx == -1)
9869 else if (M != V1BroadcastIdx)
9874 if (DoBothBroadcast())
9875 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9878 // If the inputs all stem from a single 128-bit lane of each input, then we
9879 // split them rather than blending because the split will decompose to
9880 // unusually few instructions.
9881 int LaneCount = VT.getSizeInBits() / 128;
9882 int LaneSize = Size / LaneCount;
9883 SmallBitVector LaneInputs[2];
9884 LaneInputs[0].resize(LaneCount, false);
9885 LaneInputs[1].resize(LaneCount, false);
9886 for (int i = 0; i < Size; ++i)
9888 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9889 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9890 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9892 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9893 // that the decomposed single-input shuffles don't end up here.
9894 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9897 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9898 /// a permutation and blend of those lanes.
9900 /// This essentially blends the out-of-lane inputs to each lane into the lane
9901 /// from a permuted copy of the vector. This lowering strategy results in four
9902 /// instructions in the worst case for a single-input cross lane shuffle which
9903 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9904 /// of. Special cases for each particular shuffle pattern should be handled
9905 /// prior to trying this lowering.
9906 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9907 SDValue V1, SDValue V2,
9909 SelectionDAG &DAG) {
9910 // FIXME: This should probably be generalized for 512-bit vectors as well.
9911 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9912 int LaneSize = Mask.size() / 2;
9914 // If there are only inputs from one 128-bit lane, splitting will in fact be
9915 // less expensive. The flags track wether the given lane contains an element
9916 // that crosses to another lane.
9917 bool LaneCrossing[2] = {false, false};
9918 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9919 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9920 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9921 if (!LaneCrossing[0] || !LaneCrossing[1])
9922 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9924 if (isSingleInputShuffleMask(Mask)) {
9925 SmallVector<int, 32> FlippedBlendMask;
9926 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9927 FlippedBlendMask.push_back(
9928 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9930 : Mask[i] % LaneSize +
9931 (i / LaneSize) * LaneSize + Size));
9933 // Flip the vector, and blend the results which should now be in-lane. The
9934 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9935 // 5 for the high source. The value 3 selects the high half of source 2 and
9936 // the value 2 selects the low half of source 2. We only use source 2 to
9937 // allow folding it into a memory operand.
9938 unsigned PERMMask = 3 | 2 << 4;
9939 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9940 V1, DAG.getConstant(PERMMask, MVT::i8));
9941 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9944 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9945 // will be handled by the above logic and a blend of the results, much like
9946 // other patterns in AVX.
9947 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9950 /// \brief Handle lowering 2-lane 128-bit shuffles.
9951 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9952 SDValue V2, ArrayRef<int> Mask,
9953 const X86Subtarget *Subtarget,
9954 SelectionDAG &DAG) {
9955 // Blends are faster and handle all the non-lane-crossing cases.
9956 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9960 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9961 VT.getVectorNumElements() / 2);
9962 // Check for patterns which can be matched with a single insert of a 128-bit
9964 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9965 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9966 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9967 DAG.getIntPtrConstant(0));
9968 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9969 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9970 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9972 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9973 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9974 DAG.getIntPtrConstant(0));
9975 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9976 DAG.getIntPtrConstant(2));
9977 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9980 // Otherwise form a 128-bit permutation.
9981 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9982 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9983 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9984 DAG.getConstant(PermMask, MVT::i8));
9987 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9988 /// shuffling each lane.
9990 /// This will only succeed when the result of fixing the 128-bit lanes results
9991 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9992 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9993 /// the lane crosses early and then use simpler shuffles within each lane.
9995 /// FIXME: It might be worthwhile at some point to support this without
9996 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9997 /// in x86 only floating point has interesting non-repeating shuffles, and even
9998 /// those are still *marginally* more expensive.
9999 static SDValue lowerVectorShuffleByMerging128BitLanes(
10000 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10001 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10002 assert(!isSingleInputShuffleMask(Mask) &&
10003 "This is only useful with multiple inputs.");
10005 int Size = Mask.size();
10006 int LaneSize = 128 / VT.getScalarSizeInBits();
10007 int NumLanes = Size / LaneSize;
10008 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10010 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10011 // check whether the in-128-bit lane shuffles share a repeating pattern.
10012 SmallVector<int, 4> Lanes;
10013 Lanes.resize(NumLanes, -1);
10014 SmallVector<int, 4> InLaneMask;
10015 InLaneMask.resize(LaneSize, -1);
10016 for (int i = 0; i < Size; ++i) {
10020 int j = i / LaneSize;
10022 if (Lanes[j] < 0) {
10023 // First entry we've seen for this lane.
10024 Lanes[j] = Mask[i] / LaneSize;
10025 } else if (Lanes[j] != Mask[i] / LaneSize) {
10026 // This doesn't match the lane selected previously!
10030 // Check that within each lane we have a consistent shuffle mask.
10031 int k = i % LaneSize;
10032 if (InLaneMask[k] < 0) {
10033 InLaneMask[k] = Mask[i] % LaneSize;
10034 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10035 // This doesn't fit a repeating in-lane mask.
10040 // First shuffle the lanes into place.
10041 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10042 VT.getSizeInBits() / 64);
10043 SmallVector<int, 8> LaneMask;
10044 LaneMask.resize(NumLanes * 2, -1);
10045 for (int i = 0; i < NumLanes; ++i)
10046 if (Lanes[i] >= 0) {
10047 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10048 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10051 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10052 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10053 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10055 // Cast it back to the type we actually want.
10056 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10058 // Now do a simple shuffle that isn't lane crossing.
10059 SmallVector<int, 8> NewMask;
10060 NewMask.resize(Size, -1);
10061 for (int i = 0; i < Size; ++i)
10063 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10064 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10065 "Must not introduce lane crosses at this point!");
10067 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10070 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10073 /// This returns true if the elements from a particular input are already in the
10074 /// slot required by the given mask and require no permutation.
10075 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10076 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10077 int Size = Mask.size();
10078 for (int i = 0; i < Size; ++i)
10079 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10085 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10087 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10088 /// isn't available.
10089 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10090 const X86Subtarget *Subtarget,
10091 SelectionDAG &DAG) {
10093 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10094 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10095 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10096 ArrayRef<int> Mask = SVOp->getMask();
10097 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10099 SmallVector<int, 4> WidenedMask;
10100 if (canWidenShuffleElements(Mask, WidenedMask))
10101 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10104 if (isSingleInputShuffleMask(Mask)) {
10105 // Check for being able to broadcast a single element.
10106 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10107 Mask, Subtarget, DAG))
10110 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10111 // Non-half-crossing single input shuffles can be lowerid with an
10112 // interleaved permutation.
10113 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10114 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10115 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10116 DAG.getConstant(VPERMILPMask, MVT::i8));
10119 // With AVX2 we have direct support for this permutation.
10120 if (Subtarget->hasAVX2())
10121 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10122 getV4X86ShuffleImm8ForMask(Mask, DAG));
10124 // Otherwise, fall back.
10125 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10129 // X86 has dedicated unpack instructions that can handle specific blend
10130 // operations: UNPCKH and UNPCKL.
10131 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10132 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10133 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10134 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10136 // If we have a single input to the zero element, insert that into V1 if we
10137 // can do so cheaply.
10138 int NumV2Elements =
10139 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10140 if (NumV2Elements == 1 && Mask[0] >= 4)
10141 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10142 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10145 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10149 // Check if the blend happens to exactly fit that of SHUFPD.
10150 if ((Mask[0] == -1 || Mask[0] < 2) &&
10151 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10152 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10153 (Mask[3] == -1 || Mask[3] >= 6)) {
10154 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10155 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10156 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10157 DAG.getConstant(SHUFPDMask, MVT::i8));
10159 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10160 (Mask[1] == -1 || Mask[1] < 2) &&
10161 (Mask[2] == -1 || Mask[2] >= 6) &&
10162 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10163 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10164 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10165 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10166 DAG.getConstant(SHUFPDMask, MVT::i8));
10169 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10170 // shuffle. However, if we have AVX2 and either inputs are already in place,
10171 // we will be able to shuffle even across lanes the other input in a single
10172 // instruction so skip this pattern.
10173 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10174 isShuffleMaskInputInPlace(1, Mask))))
10175 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10176 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10179 // If we have AVX2 then we always want to lower with a blend because an v4 we
10180 // can fully permute the elements.
10181 if (Subtarget->hasAVX2())
10182 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10185 // Otherwise fall back on generic lowering.
10186 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10189 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10191 /// This routine is only called when we have AVX2 and thus a reasonable
10192 /// instruction set for v4i64 shuffling..
10193 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10194 const X86Subtarget *Subtarget,
10195 SelectionDAG &DAG) {
10197 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10198 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10199 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10200 ArrayRef<int> Mask = SVOp->getMask();
10201 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10202 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10204 SmallVector<int, 4> WidenedMask;
10205 if (canWidenShuffleElements(Mask, WidenedMask))
10206 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10209 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10213 // Check for being able to broadcast a single element.
10214 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10215 Mask, Subtarget, DAG))
10218 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10219 // use lower latency instructions that will operate on both 128-bit lanes.
10220 SmallVector<int, 2> RepeatedMask;
10221 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10222 if (isSingleInputShuffleMask(Mask)) {
10223 int PSHUFDMask[] = {-1, -1, -1, -1};
10224 for (int i = 0; i < 2; ++i)
10225 if (RepeatedMask[i] >= 0) {
10226 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10227 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10229 return DAG.getNode(
10230 ISD::BITCAST, DL, MVT::v4i64,
10231 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10232 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10233 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10236 // Use dedicated unpack instructions for masks that match their pattern.
10237 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10238 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10239 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10240 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10243 // AVX2 provides a direct instruction for permuting a single input across
10245 if (isSingleInputShuffleMask(Mask))
10246 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10247 getV4X86ShuffleImm8ForMask(Mask, DAG));
10249 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10250 // shuffle. However, if we have AVX2 and either inputs are already in place,
10251 // we will be able to shuffle even across lanes the other input in a single
10252 // instruction so skip this pattern.
10253 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10254 isShuffleMaskInputInPlace(1, Mask))))
10255 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10256 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10259 // Otherwise fall back on generic blend lowering.
10260 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10264 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10266 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10267 /// isn't available.
10268 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10269 const X86Subtarget *Subtarget,
10270 SelectionDAG &DAG) {
10272 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10273 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10274 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10275 ArrayRef<int> Mask = SVOp->getMask();
10276 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10278 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10282 // Check for being able to broadcast a single element.
10283 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10284 Mask, Subtarget, DAG))
10287 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10288 // options to efficiently lower the shuffle.
10289 SmallVector<int, 4> RepeatedMask;
10290 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10291 assert(RepeatedMask.size() == 4 &&
10292 "Repeated masks must be half the mask width!");
10293 if (isSingleInputShuffleMask(Mask))
10294 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10295 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10297 // Use dedicated unpack instructions for masks that match their pattern.
10298 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10299 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10300 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10301 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10303 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10304 // have already handled any direct blends. We also need to squash the
10305 // repeated mask into a simulated v4f32 mask.
10306 for (int i = 0; i < 4; ++i)
10307 if (RepeatedMask[i] >= 8)
10308 RepeatedMask[i] -= 4;
10309 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10312 // If we have a single input shuffle with different shuffle patterns in the
10313 // two 128-bit lanes use the variable mask to VPERMILPS.
10314 if (isSingleInputShuffleMask(Mask)) {
10315 SDValue VPermMask[8];
10316 for (int i = 0; i < 8; ++i)
10317 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10318 : DAG.getConstant(Mask[i], MVT::i32);
10319 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10320 return DAG.getNode(
10321 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10322 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10324 if (Subtarget->hasAVX2())
10325 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10326 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10327 DAG.getNode(ISD::BUILD_VECTOR, DL,
10328 MVT::v8i32, VPermMask)),
10331 // Otherwise, fall back.
10332 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10336 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10338 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10339 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10342 // If we have AVX2 then we always want to lower with a blend because at v8 we
10343 // can fully permute the elements.
10344 if (Subtarget->hasAVX2())
10345 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10348 // Otherwise fall back on generic lowering.
10349 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10352 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10354 /// This routine is only called when we have AVX2 and thus a reasonable
10355 /// instruction set for v8i32 shuffling..
10356 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10357 const X86Subtarget *Subtarget,
10358 SelectionDAG &DAG) {
10360 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10361 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10362 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10363 ArrayRef<int> Mask = SVOp->getMask();
10364 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10365 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10367 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10371 // Check for being able to broadcast a single element.
10372 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10373 Mask, Subtarget, DAG))
10376 // If the shuffle mask is repeated in each 128-bit lane we can use more
10377 // efficient instructions that mirror the shuffles across the two 128-bit
10379 SmallVector<int, 4> RepeatedMask;
10380 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10381 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10382 if (isSingleInputShuffleMask(Mask))
10383 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10384 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10386 // Use dedicated unpack instructions for masks that match their pattern.
10387 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10388 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10389 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10390 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10393 // If the shuffle patterns aren't repeated but it is a single input, directly
10394 // generate a cross-lane VPERMD instruction.
10395 if (isSingleInputShuffleMask(Mask)) {
10396 SDValue VPermMask[8];
10397 for (int i = 0; i < 8; ++i)
10398 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10399 : DAG.getConstant(Mask[i], MVT::i32);
10400 return DAG.getNode(
10401 X86ISD::VPERMV, DL, MVT::v8i32,
10402 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10405 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10407 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10408 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10411 // Otherwise fall back on generic blend lowering.
10412 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10416 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10418 /// This routine is only called when we have AVX2 and thus a reasonable
10419 /// instruction set for v16i16 shuffling..
10420 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10421 const X86Subtarget *Subtarget,
10422 SelectionDAG &DAG) {
10424 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10425 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10426 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10427 ArrayRef<int> Mask = SVOp->getMask();
10428 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10429 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10431 // Check for being able to broadcast a single element.
10432 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10433 Mask, Subtarget, DAG))
10436 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10440 // Use dedicated unpack instructions for masks that match their pattern.
10441 if (isShuffleEquivalent(Mask,
10442 // First 128-bit lane:
10443 0, 16, 1, 17, 2, 18, 3, 19,
10444 // Second 128-bit lane:
10445 8, 24, 9, 25, 10, 26, 11, 27))
10446 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10447 if (isShuffleEquivalent(Mask,
10448 // First 128-bit lane:
10449 4, 20, 5, 21, 6, 22, 7, 23,
10450 // Second 128-bit lane:
10451 12, 28, 13, 29, 14, 30, 15, 31))
10452 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10454 if (isSingleInputShuffleMask(Mask)) {
10455 // There are no generalized cross-lane shuffle operations available on i16
10457 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10458 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10461 SDValue PSHUFBMask[32];
10462 for (int i = 0; i < 16; ++i) {
10463 if (Mask[i] == -1) {
10464 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10468 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10469 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10470 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10471 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10473 return DAG.getNode(
10474 ISD::BITCAST, DL, MVT::v16i16,
10476 X86ISD::PSHUFB, DL, MVT::v32i8,
10477 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10478 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10481 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10483 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10484 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10487 // Otherwise fall back on generic lowering.
10488 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10491 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10493 /// This routine is only called when we have AVX2 and thus a reasonable
10494 /// instruction set for v32i8 shuffling..
10495 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10496 const X86Subtarget *Subtarget,
10497 SelectionDAG &DAG) {
10499 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10500 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10501 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10502 ArrayRef<int> Mask = SVOp->getMask();
10503 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10504 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10506 // Check for being able to broadcast a single element.
10507 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10508 Mask, Subtarget, DAG))
10511 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10515 // Use dedicated unpack instructions for masks that match their pattern.
10516 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10518 if (isShuffleEquivalent(
10520 // First 128-bit lane:
10521 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10522 // Second 128-bit lane:
10523 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10524 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10525 if (isShuffleEquivalent(
10527 // First 128-bit lane:
10528 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10529 // Second 128-bit lane:
10530 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10531 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10533 if (isSingleInputShuffleMask(Mask)) {
10534 // There are no generalized cross-lane shuffle operations available on i8
10536 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10537 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10540 SDValue PSHUFBMask[32];
10541 for (int i = 0; i < 32; ++i)
10544 ? DAG.getUNDEF(MVT::i8)
10545 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10547 return DAG.getNode(
10548 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10549 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10552 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10554 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10555 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10558 // Otherwise fall back on generic lowering.
10559 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10562 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10564 /// This routine either breaks down the specific type of a 256-bit x86 vector
10565 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10566 /// together based on the available instructions.
10567 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10568 MVT VT, const X86Subtarget *Subtarget,
10569 SelectionDAG &DAG) {
10571 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10572 ArrayRef<int> Mask = SVOp->getMask();
10574 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10575 // check for those subtargets here and avoid much of the subtarget querying in
10576 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10577 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10578 // floating point types there eventually, just immediately cast everything to
10579 // a float and operate entirely in that domain.
10580 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10581 int ElementBits = VT.getScalarSizeInBits();
10582 if (ElementBits < 32)
10583 // No floating point type available, decompose into 128-bit vectors.
10584 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10586 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10587 VT.getVectorNumElements());
10588 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10589 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10590 return DAG.getNode(ISD::BITCAST, DL, VT,
10591 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10594 switch (VT.SimpleTy) {
10596 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10598 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10600 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10602 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10604 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10606 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10609 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10613 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10614 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10615 const X86Subtarget *Subtarget,
10616 SelectionDAG &DAG) {
10618 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10619 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10620 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10621 ArrayRef<int> Mask = SVOp->getMask();
10622 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10624 // FIXME: Implement direct support for this type!
10625 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10628 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10629 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10630 const X86Subtarget *Subtarget,
10631 SelectionDAG &DAG) {
10633 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10634 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10635 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10636 ArrayRef<int> Mask = SVOp->getMask();
10637 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10639 // FIXME: Implement direct support for this type!
10640 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10643 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10644 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10645 const X86Subtarget *Subtarget,
10646 SelectionDAG &DAG) {
10648 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10649 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10650 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10651 ArrayRef<int> Mask = SVOp->getMask();
10652 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10654 // FIXME: Implement direct support for this type!
10655 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10658 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10659 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10660 const X86Subtarget *Subtarget,
10661 SelectionDAG &DAG) {
10663 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10664 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10665 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10666 ArrayRef<int> Mask = SVOp->getMask();
10667 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10669 // FIXME: Implement direct support for this type!
10670 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10673 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10674 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10675 const X86Subtarget *Subtarget,
10676 SelectionDAG &DAG) {
10678 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10679 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10680 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10681 ArrayRef<int> Mask = SVOp->getMask();
10682 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10683 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10685 // FIXME: Implement direct support for this type!
10686 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10689 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10690 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10691 const X86Subtarget *Subtarget,
10692 SelectionDAG &DAG) {
10694 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10695 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10696 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10697 ArrayRef<int> Mask = SVOp->getMask();
10698 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10699 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10701 // FIXME: Implement direct support for this type!
10702 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10705 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10707 /// This routine either breaks down the specific type of a 512-bit x86 vector
10708 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10709 /// together based on the available instructions.
10710 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10711 MVT VT, const X86Subtarget *Subtarget,
10712 SelectionDAG &DAG) {
10714 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10715 ArrayRef<int> Mask = SVOp->getMask();
10716 assert(Subtarget->hasAVX512() &&
10717 "Cannot lower 512-bit vectors w/ basic ISA!");
10719 // Check for being able to broadcast a single element.
10720 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10721 Mask, Subtarget, DAG))
10724 // Dispatch to each element type for lowering. If we don't have supprot for
10725 // specific element type shuffles at 512 bits, immediately split them and
10726 // lower them. Each lowering routine of a given type is allowed to assume that
10727 // the requisite ISA extensions for that element type are available.
10728 switch (VT.SimpleTy) {
10730 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10732 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10734 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10736 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10738 if (Subtarget->hasBWI())
10739 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10742 if (Subtarget->hasBWI())
10743 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10747 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10750 // Otherwise fall back on splitting.
10751 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10754 /// \brief Top-level lowering for x86 vector shuffles.
10756 /// This handles decomposition, canonicalization, and lowering of all x86
10757 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10758 /// above in helper routines. The canonicalization attempts to widen shuffles
10759 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10760 /// s.t. only one of the two inputs needs to be tested, etc.
10761 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10762 SelectionDAG &DAG) {
10763 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10764 ArrayRef<int> Mask = SVOp->getMask();
10765 SDValue V1 = Op.getOperand(0);
10766 SDValue V2 = Op.getOperand(1);
10767 MVT VT = Op.getSimpleValueType();
10768 int NumElements = VT.getVectorNumElements();
10771 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10773 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10774 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10775 if (V1IsUndef && V2IsUndef)
10776 return DAG.getUNDEF(VT);
10778 // When we create a shuffle node we put the UNDEF node to second operand,
10779 // but in some cases the first operand may be transformed to UNDEF.
10780 // In this case we should just commute the node.
10782 return DAG.getCommutedVectorShuffle(*SVOp);
10784 // Check for non-undef masks pointing at an undef vector and make the masks
10785 // undef as well. This makes it easier to match the shuffle based solely on
10789 if (M >= NumElements) {
10790 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10791 for (int &M : NewMask)
10792 if (M >= NumElements)
10794 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10797 // Try to collapse shuffles into using a vector type with fewer elements but
10798 // wider element types. We cap this to not form integers or floating point
10799 // elements wider than 64 bits, but it might be interesting to form i128
10800 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10801 SmallVector<int, 16> WidenedMask;
10802 if (VT.getScalarSizeInBits() < 64 &&
10803 canWidenShuffleElements(Mask, WidenedMask)) {
10804 MVT NewEltVT = VT.isFloatingPoint()
10805 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10806 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10807 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10808 // Make sure that the new vector type is legal. For example, v2f64 isn't
10810 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10811 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10812 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10813 return DAG.getNode(ISD::BITCAST, dl, VT,
10814 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10818 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10819 for (int M : SVOp->getMask())
10821 ++NumUndefElements;
10822 else if (M < NumElements)
10827 // Commute the shuffle as needed such that more elements come from V1 than
10828 // V2. This allows us to match the shuffle pattern strictly on how many
10829 // elements come from V1 without handling the symmetric cases.
10830 if (NumV2Elements > NumV1Elements)
10831 return DAG.getCommutedVectorShuffle(*SVOp);
10833 // When the number of V1 and V2 elements are the same, try to minimize the
10834 // number of uses of V2 in the low half of the vector. When that is tied,
10835 // ensure that the sum of indices for V1 is equal to or lower than the sum
10837 if (NumV1Elements == NumV2Elements) {
10838 int LowV1Elements = 0, LowV2Elements = 0;
10839 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10840 if (M >= NumElements)
10844 if (LowV2Elements > LowV1Elements) {
10845 return DAG.getCommutedVectorShuffle(*SVOp);
10846 } else if (LowV2Elements == LowV1Elements) {
10847 int SumV1Indices = 0, SumV2Indices = 0;
10848 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10849 if (SVOp->getMask()[i] >= NumElements)
10851 else if (SVOp->getMask()[i] >= 0)
10853 if (SumV2Indices < SumV1Indices)
10854 return DAG.getCommutedVectorShuffle(*SVOp);
10858 // For each vector width, delegate to a specialized lowering routine.
10859 if (VT.getSizeInBits() == 128)
10860 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10862 if (VT.getSizeInBits() == 256)
10863 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10865 // Force AVX-512 vectors to be scalarized for now.
10866 // FIXME: Implement AVX-512 support!
10867 if (VT.getSizeInBits() == 512)
10868 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10870 llvm_unreachable("Unimplemented!");
10874 //===----------------------------------------------------------------------===//
10875 // Legacy vector shuffle lowering
10877 // This code is the legacy code handling vector shuffles until the above
10878 // replaces its functionality and performance.
10879 //===----------------------------------------------------------------------===//
10881 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10882 bool hasInt256, unsigned *MaskOut = nullptr) {
10883 MVT EltVT = VT.getVectorElementType();
10885 // There is no blend with immediate in AVX-512.
10886 if (VT.is512BitVector())
10889 if (!hasSSE41 || EltVT == MVT::i8)
10891 if (!hasInt256 && VT == MVT::v16i16)
10894 unsigned MaskValue = 0;
10895 unsigned NumElems = VT.getVectorNumElements();
10896 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10897 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10898 unsigned NumElemsInLane = NumElems / NumLanes;
10900 // Blend for v16i16 should be symetric for the both lanes.
10901 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10903 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10904 int EltIdx = MaskVals[i];
10906 if ((EltIdx < 0 || EltIdx == (int)i) &&
10907 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10910 if (((unsigned)EltIdx == (i + NumElems)) &&
10911 (SndLaneEltIdx < 0 ||
10912 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10913 MaskValue |= (1 << i);
10919 *MaskOut = MaskValue;
10923 // Try to lower a shuffle node into a simple blend instruction.
10924 // This function assumes isBlendMask returns true for this
10925 // SuffleVectorSDNode
10926 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10927 unsigned MaskValue,
10928 const X86Subtarget *Subtarget,
10929 SelectionDAG &DAG) {
10930 MVT VT = SVOp->getSimpleValueType(0);
10931 MVT EltVT = VT.getVectorElementType();
10932 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10933 Subtarget->hasInt256() && "Trying to lower a "
10934 "VECTOR_SHUFFLE to a Blend but "
10935 "with the wrong mask"));
10936 SDValue V1 = SVOp->getOperand(0);
10937 SDValue V2 = SVOp->getOperand(1);
10939 unsigned NumElems = VT.getVectorNumElements();
10941 // Convert i32 vectors to floating point if it is not AVX2.
10942 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10944 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10945 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10947 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10948 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10951 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10952 DAG.getConstant(MaskValue, MVT::i32));
10953 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10956 /// In vector type \p VT, return true if the element at index \p InputIdx
10957 /// falls on a different 128-bit lane than \p OutputIdx.
10958 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10959 unsigned OutputIdx) {
10960 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10961 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10964 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10965 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10966 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10967 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10969 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10970 SelectionDAG &DAG) {
10971 MVT VT = V1.getSimpleValueType();
10972 assert(VT.is128BitVector() || VT.is256BitVector());
10974 MVT EltVT = VT.getVectorElementType();
10975 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10976 unsigned NumElts = VT.getVectorNumElements();
10978 SmallVector<SDValue, 32> PshufbMask;
10979 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10980 int InputIdx = MaskVals[OutputIdx];
10981 unsigned InputByteIdx;
10983 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10984 InputByteIdx = 0x80;
10986 // Cross lane is not allowed.
10987 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10989 InputByteIdx = InputIdx * EltSizeInBytes;
10990 // Index is an byte offset within the 128-bit lane.
10991 InputByteIdx &= 0xf;
10994 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10995 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10996 if (InputByteIdx != 0x80)
11001 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11003 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11004 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11005 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11008 // v8i16 shuffles - Prefer shuffles in the following order:
11009 // 1. [all] pshuflw, pshufhw, optional move
11010 // 2. [ssse3] 1 x pshufb
11011 // 3. [ssse3] 2 x pshufb + 1 x por
11012 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11014 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11015 SelectionDAG &DAG) {
11016 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11017 SDValue V1 = SVOp->getOperand(0);
11018 SDValue V2 = SVOp->getOperand(1);
11020 SmallVector<int, 8> MaskVals;
11022 // Determine if more than 1 of the words in each of the low and high quadwords
11023 // of the result come from the same quadword of one of the two inputs. Undef
11024 // mask values count as coming from any quadword, for better codegen.
11026 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11027 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11028 unsigned LoQuad[] = { 0, 0, 0, 0 };
11029 unsigned HiQuad[] = { 0, 0, 0, 0 };
11030 // Indices of quads used.
11031 std::bitset<4> InputQuads;
11032 for (unsigned i = 0; i < 8; ++i) {
11033 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11034 int EltIdx = SVOp->getMaskElt(i);
11035 MaskVals.push_back(EltIdx);
11043 ++Quad[EltIdx / 4];
11044 InputQuads.set(EltIdx / 4);
11047 int BestLoQuad = -1;
11048 unsigned MaxQuad = 1;
11049 for (unsigned i = 0; i < 4; ++i) {
11050 if (LoQuad[i] > MaxQuad) {
11052 MaxQuad = LoQuad[i];
11056 int BestHiQuad = -1;
11058 for (unsigned i = 0; i < 4; ++i) {
11059 if (HiQuad[i] > MaxQuad) {
11061 MaxQuad = HiQuad[i];
11065 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11066 // of the two input vectors, shuffle them into one input vector so only a
11067 // single pshufb instruction is necessary. If there are more than 2 input
11068 // quads, disable the next transformation since it does not help SSSE3.
11069 bool V1Used = InputQuads[0] || InputQuads[1];
11070 bool V2Used = InputQuads[2] || InputQuads[3];
11071 if (Subtarget->hasSSSE3()) {
11072 if (InputQuads.count() == 2 && V1Used && V2Used) {
11073 BestLoQuad = InputQuads[0] ? 0 : 1;
11074 BestHiQuad = InputQuads[2] ? 2 : 3;
11076 if (InputQuads.count() > 2) {
11082 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11083 // the shuffle mask. If a quad is scored as -1, that means that it contains
11084 // words from all 4 input quadwords.
11086 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11088 BestLoQuad < 0 ? 0 : BestLoQuad,
11089 BestHiQuad < 0 ? 1 : BestHiQuad
11091 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11092 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11093 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11094 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11096 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11097 // source words for the shuffle, to aid later transformations.
11098 bool AllWordsInNewV = true;
11099 bool InOrder[2] = { true, true };
11100 for (unsigned i = 0; i != 8; ++i) {
11101 int idx = MaskVals[i];
11103 InOrder[i/4] = false;
11104 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11106 AllWordsInNewV = false;
11110 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11111 if (AllWordsInNewV) {
11112 for (int i = 0; i != 8; ++i) {
11113 int idx = MaskVals[i];
11116 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11117 if ((idx != i) && idx < 4)
11119 if ((idx != i) && idx > 3)
11128 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11129 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11130 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11131 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11132 unsigned TargetMask = 0;
11133 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11134 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11135 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11136 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11137 getShufflePSHUFLWImmediate(SVOp);
11138 V1 = NewV.getOperand(0);
11139 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11143 // Promote splats to a larger type which usually leads to more efficient code.
11144 // FIXME: Is this true if pshufb is available?
11145 if (SVOp->isSplat())
11146 return PromoteSplat(SVOp, DAG);
11148 // If we have SSSE3, and all words of the result are from 1 input vector,
11149 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11150 // is present, fall back to case 4.
11151 if (Subtarget->hasSSSE3()) {
11152 SmallVector<SDValue,16> pshufbMask;
11154 // If we have elements from both input vectors, set the high bit of the
11155 // shuffle mask element to zero out elements that come from V2 in the V1
11156 // mask, and elements that come from V1 in the V2 mask, so that the two
11157 // results can be OR'd together.
11158 bool TwoInputs = V1Used && V2Used;
11159 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11161 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11163 // Calculate the shuffle mask for the second input, shuffle it, and
11164 // OR it with the first shuffled input.
11165 CommuteVectorShuffleMask(MaskVals, 8);
11166 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11167 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11168 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11171 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11172 // and update MaskVals with new element order.
11173 std::bitset<8> InOrder;
11174 if (BestLoQuad >= 0) {
11175 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11176 for (int i = 0; i != 4; ++i) {
11177 int idx = MaskVals[i];
11180 } else if ((idx / 4) == BestLoQuad) {
11181 MaskV[i] = idx & 3;
11185 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11188 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11189 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11190 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11191 NewV.getOperand(0),
11192 getShufflePSHUFLWImmediate(SVOp), DAG);
11196 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11197 // and update MaskVals with the new element order.
11198 if (BestHiQuad >= 0) {
11199 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11200 for (unsigned i = 4; i != 8; ++i) {
11201 int idx = MaskVals[i];
11204 } else if ((idx / 4) == BestHiQuad) {
11205 MaskV[i] = (idx & 3) + 4;
11209 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11212 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11213 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11214 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11215 NewV.getOperand(0),
11216 getShufflePSHUFHWImmediate(SVOp), DAG);
11220 // In case BestHi & BestLo were both -1, which means each quadword has a word
11221 // from each of the four input quadwords, calculate the InOrder bitvector now
11222 // before falling through to the insert/extract cleanup.
11223 if (BestLoQuad == -1 && BestHiQuad == -1) {
11225 for (int i = 0; i != 8; ++i)
11226 if (MaskVals[i] < 0 || MaskVals[i] == i)
11230 // The other elements are put in the right place using pextrw and pinsrw.
11231 for (unsigned i = 0; i != 8; ++i) {
11234 int EltIdx = MaskVals[i];
11237 SDValue ExtOp = (EltIdx < 8) ?
11238 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11239 DAG.getIntPtrConstant(EltIdx)) :
11240 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11241 DAG.getIntPtrConstant(EltIdx - 8));
11242 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11243 DAG.getIntPtrConstant(i));
11248 /// \brief v16i16 shuffles
11250 /// FIXME: We only support generation of a single pshufb currently. We can
11251 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11252 /// well (e.g 2 x pshufb + 1 x por).
11254 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11255 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11256 SDValue V1 = SVOp->getOperand(0);
11257 SDValue V2 = SVOp->getOperand(1);
11260 if (V2.getOpcode() != ISD::UNDEF)
11263 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11264 return getPSHUFB(MaskVals, V1, dl, DAG);
11267 // v16i8 shuffles - Prefer shuffles in the following order:
11268 // 1. [ssse3] 1 x pshufb
11269 // 2. [ssse3] 2 x pshufb + 1 x por
11270 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11271 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11272 const X86Subtarget* Subtarget,
11273 SelectionDAG &DAG) {
11274 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11275 SDValue V1 = SVOp->getOperand(0);
11276 SDValue V2 = SVOp->getOperand(1);
11278 ArrayRef<int> MaskVals = SVOp->getMask();
11280 // Promote splats to a larger type which usually leads to more efficient code.
11281 // FIXME: Is this true if pshufb is available?
11282 if (SVOp->isSplat())
11283 return PromoteSplat(SVOp, DAG);
11285 // If we have SSSE3, case 1 is generated when all result bytes come from
11286 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11287 // present, fall back to case 3.
11289 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11290 if (Subtarget->hasSSSE3()) {
11291 SmallVector<SDValue,16> pshufbMask;
11293 // If all result elements are from one input vector, then only translate
11294 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11296 // Otherwise, we have elements from both input vectors, and must zero out
11297 // elements that come from V2 in the first mask, and V1 in the second mask
11298 // so that we can OR them together.
11299 for (unsigned i = 0; i != 16; ++i) {
11300 int EltIdx = MaskVals[i];
11301 if (EltIdx < 0 || EltIdx >= 16)
11303 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11305 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11306 DAG.getNode(ISD::BUILD_VECTOR, dl,
11307 MVT::v16i8, pshufbMask));
11309 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11310 // the 2nd operand if it's undefined or zero.
11311 if (V2.getOpcode() == ISD::UNDEF ||
11312 ISD::isBuildVectorAllZeros(V2.getNode()))
11315 // Calculate the shuffle mask for the second input, shuffle it, and
11316 // OR it with the first shuffled input.
11317 pshufbMask.clear();
11318 for (unsigned i = 0; i != 16; ++i) {
11319 int EltIdx = MaskVals[i];
11320 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11321 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11323 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11324 DAG.getNode(ISD::BUILD_VECTOR, dl,
11325 MVT::v16i8, pshufbMask));
11326 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11329 // No SSSE3 - Calculate in place words and then fix all out of place words
11330 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11331 // the 16 different words that comprise the two doublequadword input vectors.
11332 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11333 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11335 for (int i = 0; i != 8; ++i) {
11336 int Elt0 = MaskVals[i*2];
11337 int Elt1 = MaskVals[i*2+1];
11339 // This word of the result is all undef, skip it.
11340 if (Elt0 < 0 && Elt1 < 0)
11343 // This word of the result is already in the correct place, skip it.
11344 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11347 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11348 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11351 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11352 // using a single extract together, load it and store it.
11353 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11354 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11355 DAG.getIntPtrConstant(Elt1 / 2));
11356 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11357 DAG.getIntPtrConstant(i));
11361 // If Elt1 is defined, extract it from the appropriate source. If the
11362 // source byte is not also odd, shift the extracted word left 8 bits
11363 // otherwise clear the bottom 8 bits if we need to do an or.
11365 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11366 DAG.getIntPtrConstant(Elt1 / 2));
11367 if ((Elt1 & 1) == 0)
11368 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11370 TLI.getShiftAmountTy(InsElt.getValueType())));
11371 else if (Elt0 >= 0)
11372 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11373 DAG.getConstant(0xFF00, MVT::i16));
11375 // If Elt0 is defined, extract it from the appropriate source. If the
11376 // source byte is not also even, shift the extracted word right 8 bits. If
11377 // Elt1 was also defined, OR the extracted values together before
11378 // inserting them in the result.
11380 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11381 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11382 if ((Elt0 & 1) != 0)
11383 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11385 TLI.getShiftAmountTy(InsElt0.getValueType())));
11386 else if (Elt1 >= 0)
11387 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11388 DAG.getConstant(0x00FF, MVT::i16));
11389 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11392 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11393 DAG.getIntPtrConstant(i));
11395 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11398 // v32i8 shuffles - Translate to VPSHUFB if possible.
11400 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11401 const X86Subtarget *Subtarget,
11402 SelectionDAG &DAG) {
11403 MVT VT = SVOp->getSimpleValueType(0);
11404 SDValue V1 = SVOp->getOperand(0);
11405 SDValue V2 = SVOp->getOperand(1);
11407 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11409 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11410 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11411 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11413 // VPSHUFB may be generated if
11414 // (1) one of input vector is undefined or zeroinitializer.
11415 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11416 // And (2) the mask indexes don't cross the 128-bit lane.
11417 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11418 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11421 if (V1IsAllZero && !V2IsAllZero) {
11422 CommuteVectorShuffleMask(MaskVals, 32);
11425 return getPSHUFB(MaskVals, V1, dl, DAG);
11428 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11429 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11430 /// done when every pair / quad of shuffle mask elements point to elements in
11431 /// the right sequence. e.g.
11432 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11434 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11435 SelectionDAG &DAG) {
11436 MVT VT = SVOp->getSimpleValueType(0);
11438 unsigned NumElems = VT.getVectorNumElements();
11441 switch (VT.SimpleTy) {
11442 default: llvm_unreachable("Unexpected!");
11445 return SDValue(SVOp, 0);
11446 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11447 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11448 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11449 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11450 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11451 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11454 SmallVector<int, 8> MaskVec;
11455 for (unsigned i = 0; i != NumElems; i += Scale) {
11457 for (unsigned j = 0; j != Scale; ++j) {
11458 int EltIdx = SVOp->getMaskElt(i+j);
11462 StartIdx = (EltIdx / Scale);
11463 if (EltIdx != (int)(StartIdx*Scale + j))
11466 MaskVec.push_back(StartIdx);
11469 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11470 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11471 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11474 /// getVZextMovL - Return a zero-extending vector move low node.
11476 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11477 SDValue SrcOp, SelectionDAG &DAG,
11478 const X86Subtarget *Subtarget, SDLoc dl) {
11479 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11480 LoadSDNode *LD = nullptr;
11481 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11482 LD = dyn_cast<LoadSDNode>(SrcOp);
11484 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11486 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11487 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11488 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11489 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11490 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11492 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11493 return DAG.getNode(ISD::BITCAST, dl, VT,
11494 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11495 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11497 SrcOp.getOperand(0)
11503 return DAG.getNode(ISD::BITCAST, dl, VT,
11504 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11505 DAG.getNode(ISD::BITCAST, dl,
11509 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11510 /// which could not be matched by any known target speficic shuffle
11512 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11514 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11515 if (NewOp.getNode())
11518 MVT VT = SVOp->getSimpleValueType(0);
11520 unsigned NumElems = VT.getVectorNumElements();
11521 unsigned NumLaneElems = NumElems / 2;
11524 MVT EltVT = VT.getVectorElementType();
11525 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11528 SmallVector<int, 16> Mask;
11529 for (unsigned l = 0; l < 2; ++l) {
11530 // Build a shuffle mask for the output, discovering on the fly which
11531 // input vectors to use as shuffle operands (recorded in InputUsed).
11532 // If building a suitable shuffle vector proves too hard, then bail
11533 // out with UseBuildVector set.
11534 bool UseBuildVector = false;
11535 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11536 unsigned LaneStart = l * NumLaneElems;
11537 for (unsigned i = 0; i != NumLaneElems; ++i) {
11538 // The mask element. This indexes into the input.
11539 int Idx = SVOp->getMaskElt(i+LaneStart);
11541 // the mask element does not index into any input vector.
11542 Mask.push_back(-1);
11546 // The input vector this mask element indexes into.
11547 int Input = Idx / NumLaneElems;
11549 // Turn the index into an offset from the start of the input vector.
11550 Idx -= Input * NumLaneElems;
11552 // Find or create a shuffle vector operand to hold this input.
11554 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11555 if (InputUsed[OpNo] == Input)
11556 // This input vector is already an operand.
11558 if (InputUsed[OpNo] < 0) {
11559 // Create a new operand for this input vector.
11560 InputUsed[OpNo] = Input;
11565 if (OpNo >= array_lengthof(InputUsed)) {
11566 // More than two input vectors used! Give up on trying to create a
11567 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11568 UseBuildVector = true;
11572 // Add the mask index for the new shuffle vector.
11573 Mask.push_back(Idx + OpNo * NumLaneElems);
11576 if (UseBuildVector) {
11577 SmallVector<SDValue, 16> SVOps;
11578 for (unsigned i = 0; i != NumLaneElems; ++i) {
11579 // The mask element. This indexes into the input.
11580 int Idx = SVOp->getMaskElt(i+LaneStart);
11582 SVOps.push_back(DAG.getUNDEF(EltVT));
11586 // The input vector this mask element indexes into.
11587 int Input = Idx / NumElems;
11589 // Turn the index into an offset from the start of the input vector.
11590 Idx -= Input * NumElems;
11592 // Extract the vector element by hand.
11593 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11594 SVOp->getOperand(Input),
11595 DAG.getIntPtrConstant(Idx)));
11598 // Construct the output using a BUILD_VECTOR.
11599 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11600 } else if (InputUsed[0] < 0) {
11601 // No input vectors were used! The result is undefined.
11602 Output[l] = DAG.getUNDEF(NVT);
11604 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11605 (InputUsed[0] % 2) * NumLaneElems,
11607 // If only one input was used, use an undefined vector for the other.
11608 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11609 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11610 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11611 // At least one input vector was used. Create a new shuffle vector.
11612 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11618 // Concatenate the result back
11619 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11622 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11623 /// 4 elements, and match them with several different shuffle types.
11625 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11626 SDValue V1 = SVOp->getOperand(0);
11627 SDValue V2 = SVOp->getOperand(1);
11629 MVT VT = SVOp->getSimpleValueType(0);
11631 assert(VT.is128BitVector() && "Unsupported vector size");
11633 std::pair<int, int> Locs[4];
11634 int Mask1[] = { -1, -1, -1, -1 };
11635 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11637 unsigned NumHi = 0;
11638 unsigned NumLo = 0;
11639 for (unsigned i = 0; i != 4; ++i) {
11640 int Idx = PermMask[i];
11642 Locs[i] = std::make_pair(-1, -1);
11644 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11646 Locs[i] = std::make_pair(0, NumLo);
11647 Mask1[NumLo] = Idx;
11650 Locs[i] = std::make_pair(1, NumHi);
11652 Mask1[2+NumHi] = Idx;
11658 if (NumLo <= 2 && NumHi <= 2) {
11659 // If no more than two elements come from either vector. This can be
11660 // implemented with two shuffles. First shuffle gather the elements.
11661 // The second shuffle, which takes the first shuffle as both of its
11662 // vector operands, put the elements into the right order.
11663 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11665 int Mask2[] = { -1, -1, -1, -1 };
11667 for (unsigned i = 0; i != 4; ++i)
11668 if (Locs[i].first != -1) {
11669 unsigned Idx = (i < 2) ? 0 : 4;
11670 Idx += Locs[i].first * 2 + Locs[i].second;
11674 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11677 if (NumLo == 3 || NumHi == 3) {
11678 // Otherwise, we must have three elements from one vector, call it X, and
11679 // one element from the other, call it Y. First, use a shufps to build an
11680 // intermediate vector with the one element from Y and the element from X
11681 // that will be in the same half in the final destination (the indexes don't
11682 // matter). Then, use a shufps to build the final vector, taking the half
11683 // containing the element from Y from the intermediate, and the other half
11686 // Normalize it so the 3 elements come from V1.
11687 CommuteVectorShuffleMask(PermMask, 4);
11691 // Find the element from V2.
11693 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11694 int Val = PermMask[HiIndex];
11701 Mask1[0] = PermMask[HiIndex];
11703 Mask1[2] = PermMask[HiIndex^1];
11705 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11707 if (HiIndex >= 2) {
11708 Mask1[0] = PermMask[0];
11709 Mask1[1] = PermMask[1];
11710 Mask1[2] = HiIndex & 1 ? 6 : 4;
11711 Mask1[3] = HiIndex & 1 ? 4 : 6;
11712 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11715 Mask1[0] = HiIndex & 1 ? 2 : 0;
11716 Mask1[1] = HiIndex & 1 ? 0 : 2;
11717 Mask1[2] = PermMask[2];
11718 Mask1[3] = PermMask[3];
11723 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11726 // Break it into (shuffle shuffle_hi, shuffle_lo).
11727 int LoMask[] = { -1, -1, -1, -1 };
11728 int HiMask[] = { -1, -1, -1, -1 };
11730 int *MaskPtr = LoMask;
11731 unsigned MaskIdx = 0;
11732 unsigned LoIdx = 0;
11733 unsigned HiIdx = 2;
11734 for (unsigned i = 0; i != 4; ++i) {
11741 int Idx = PermMask[i];
11743 Locs[i] = std::make_pair(-1, -1);
11744 } else if (Idx < 4) {
11745 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11746 MaskPtr[LoIdx] = Idx;
11749 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11750 MaskPtr[HiIdx] = Idx;
11755 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11756 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11757 int MaskOps[] = { -1, -1, -1, -1 };
11758 for (unsigned i = 0; i != 4; ++i)
11759 if (Locs[i].first != -1)
11760 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11761 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11764 static bool MayFoldVectorLoad(SDValue V) {
11765 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11766 V = V.getOperand(0);
11768 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11769 V = V.getOperand(0);
11770 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11771 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11772 // BUILD_VECTOR (load), undef
11773 V = V.getOperand(0);
11775 return MayFoldLoad(V);
11779 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11780 MVT VT = Op.getSimpleValueType();
11782 // Canonizalize to v2f64.
11783 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11784 return DAG.getNode(ISD::BITCAST, dl, VT,
11785 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11790 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11792 SDValue V1 = Op.getOperand(0);
11793 SDValue V2 = Op.getOperand(1);
11794 MVT VT = Op.getSimpleValueType();
11796 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11798 if (HasSSE2 && VT == MVT::v2f64)
11799 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11801 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11802 return DAG.getNode(ISD::BITCAST, dl, VT,
11803 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11804 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11805 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11809 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11810 SDValue V1 = Op.getOperand(0);
11811 SDValue V2 = Op.getOperand(1);
11812 MVT VT = Op.getSimpleValueType();
11814 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11815 "unsupported shuffle type");
11817 if (V2.getOpcode() == ISD::UNDEF)
11821 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11825 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11826 SDValue V1 = Op.getOperand(0);
11827 SDValue V2 = Op.getOperand(1);
11828 MVT VT = Op.getSimpleValueType();
11829 unsigned NumElems = VT.getVectorNumElements();
11831 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11832 // operand of these instructions is only memory, so check if there's a
11833 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11835 bool CanFoldLoad = false;
11837 // Trivial case, when V2 comes from a load.
11838 if (MayFoldVectorLoad(V2))
11839 CanFoldLoad = true;
11841 // When V1 is a load, it can be folded later into a store in isel, example:
11842 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11844 // (MOVLPSmr addr:$src1, VR128:$src2)
11845 // So, recognize this potential and also use MOVLPS or MOVLPD
11846 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11847 CanFoldLoad = true;
11849 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11851 if (HasSSE2 && NumElems == 2)
11852 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11855 // If we don't care about the second element, proceed to use movss.
11856 if (SVOp->getMaskElt(1) != -1)
11857 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11860 // movl and movlp will both match v2i64, but v2i64 is never matched by
11861 // movl earlier because we make it strict to avoid messing with the movlp load
11862 // folding logic (see the code above getMOVLP call). Match it here then,
11863 // this is horrible, but will stay like this until we move all shuffle
11864 // matching to x86 specific nodes. Note that for the 1st condition all
11865 // types are matched with movsd.
11867 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11868 // as to remove this logic from here, as much as possible
11869 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11870 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11871 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11874 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11876 // Invert the operand order and use SHUFPS to match it.
11877 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11878 getShuffleSHUFImmediate(SVOp), DAG);
11881 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11882 SelectionDAG &DAG) {
11884 MVT VT = Load->getSimpleValueType(0);
11885 MVT EVT = VT.getVectorElementType();
11886 SDValue Addr = Load->getOperand(1);
11887 SDValue NewAddr = DAG.getNode(
11888 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11889 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11892 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11893 DAG.getMachineFunction().getMachineMemOperand(
11894 Load->getMemOperand(), 0, EVT.getStoreSize()));
11898 // It is only safe to call this function if isINSERTPSMask is true for
11899 // this shufflevector mask.
11900 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11901 SelectionDAG &DAG) {
11902 // Generate an insertps instruction when inserting an f32 from memory onto a
11903 // v4f32 or when copying a member from one v4f32 to another.
11904 // We also use it for transferring i32 from one register to another,
11905 // since it simply copies the same bits.
11906 // If we're transferring an i32 from memory to a specific element in a
11907 // register, we output a generic DAG that will match the PINSRD
11909 MVT VT = SVOp->getSimpleValueType(0);
11910 MVT EVT = VT.getVectorElementType();
11911 SDValue V1 = SVOp->getOperand(0);
11912 SDValue V2 = SVOp->getOperand(1);
11913 auto Mask = SVOp->getMask();
11914 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11915 "unsupported vector type for insertps/pinsrd");
11917 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11918 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11919 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11923 unsigned DestIndex;
11927 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11930 // If we have 1 element from each vector, we have to check if we're
11931 // changing V1's element's place. If so, we're done. Otherwise, we
11932 // should assume we're changing V2's element's place and behave
11934 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11935 assert(DestIndex <= INT32_MAX && "truncated destination index");
11936 if (FromV1 == FromV2 &&
11937 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11941 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11944 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11945 "More than one element from V1 and from V2, or no elements from one "
11946 "of the vectors. This case should not have returned true from "
11951 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11954 // Get an index into the source vector in the range [0,4) (the mask is
11955 // in the range [0,8) because it can address V1 and V2)
11956 unsigned SrcIndex = Mask[DestIndex] % 4;
11957 if (MayFoldLoad(From)) {
11958 // Trivial case, when From comes from a load and is only used by the
11959 // shuffle. Make it use insertps from the vector that we need from that
11962 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11963 if (!NewLoad.getNode())
11966 if (EVT == MVT::f32) {
11967 // Create this as a scalar to vector to match the instruction pattern.
11968 SDValue LoadScalarToVector =
11969 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11970 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11971 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11973 } else { // EVT == MVT::i32
11974 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11975 // instruction, to match the PINSRD instruction, which loads an i32 to a
11976 // certain vector element.
11977 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11978 DAG.getConstant(DestIndex, MVT::i32));
11982 // Vector-element-to-vector
11983 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11984 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11987 // Reduce a vector shuffle to zext.
11988 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11989 SelectionDAG &DAG) {
11990 // PMOVZX is only available from SSE41.
11991 if (!Subtarget->hasSSE41())
11994 MVT VT = Op.getSimpleValueType();
11996 // Only AVX2 support 256-bit vector integer extending.
11997 if (!Subtarget->hasInt256() && VT.is256BitVector())
12000 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12002 SDValue V1 = Op.getOperand(0);
12003 SDValue V2 = Op.getOperand(1);
12004 unsigned NumElems = VT.getVectorNumElements();
12006 // Extending is an unary operation and the element type of the source vector
12007 // won't be equal to or larger than i64.
12008 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12009 VT.getVectorElementType() == MVT::i64)
12012 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12013 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12014 while ((1U << Shift) < NumElems) {
12015 if (SVOp->getMaskElt(1U << Shift) == 1)
12018 // The maximal ratio is 8, i.e. from i8 to i64.
12023 // Check the shuffle mask.
12024 unsigned Mask = (1U << Shift) - 1;
12025 for (unsigned i = 0; i != NumElems; ++i) {
12026 int EltIdx = SVOp->getMaskElt(i);
12027 if ((i & Mask) != 0 && EltIdx != -1)
12029 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12033 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12034 MVT NeVT = MVT::getIntegerVT(NBits);
12035 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12037 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12040 return DAG.getNode(ISD::BITCAST, DL, VT,
12041 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12044 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12045 SelectionDAG &DAG) {
12046 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12047 MVT VT = Op.getSimpleValueType();
12049 SDValue V1 = Op.getOperand(0);
12050 SDValue V2 = Op.getOperand(1);
12052 if (isZeroShuffle(SVOp))
12053 return getZeroVector(VT, Subtarget, DAG, dl);
12055 // Handle splat operations
12056 if (SVOp->isSplat()) {
12057 // Use vbroadcast whenever the splat comes from a foldable load
12058 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12059 if (Broadcast.getNode())
12063 // Check integer expanding shuffles.
12064 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12065 if (NewOp.getNode())
12068 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12070 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12071 VT == MVT::v32i8) {
12072 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12073 if (NewOp.getNode())
12074 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12075 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12076 // FIXME: Figure out a cleaner way to do this.
12077 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12078 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12079 if (NewOp.getNode()) {
12080 MVT NewVT = NewOp.getSimpleValueType();
12081 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12082 NewVT, true, false))
12083 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12086 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12087 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12088 if (NewOp.getNode()) {
12089 MVT NewVT = NewOp.getSimpleValueType();
12090 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12091 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12100 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12101 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12102 SDValue V1 = Op.getOperand(0);
12103 SDValue V2 = Op.getOperand(1);
12104 MVT VT = Op.getSimpleValueType();
12106 unsigned NumElems = VT.getVectorNumElements();
12107 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12108 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12109 bool V1IsSplat = false;
12110 bool V2IsSplat = false;
12111 bool HasSSE2 = Subtarget->hasSSE2();
12112 bool HasFp256 = Subtarget->hasFp256();
12113 bool HasInt256 = Subtarget->hasInt256();
12114 MachineFunction &MF = DAG.getMachineFunction();
12115 bool OptForSize = MF.getFunction()->getAttributes().
12116 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12118 // Check if we should use the experimental vector shuffle lowering. If so,
12119 // delegate completely to that code path.
12120 if (ExperimentalVectorShuffleLowering)
12121 return lowerVectorShuffle(Op, Subtarget, DAG);
12123 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12125 if (V1IsUndef && V2IsUndef)
12126 return DAG.getUNDEF(VT);
12128 // When we create a shuffle node we put the UNDEF node to second operand,
12129 // but in some cases the first operand may be transformed to UNDEF.
12130 // In this case we should just commute the node.
12132 return DAG.getCommutedVectorShuffle(*SVOp);
12134 // Vector shuffle lowering takes 3 steps:
12136 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12137 // narrowing and commutation of operands should be handled.
12138 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12140 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12141 // so the shuffle can be broken into other shuffles and the legalizer can
12142 // try the lowering again.
12144 // The general idea is that no vector_shuffle operation should be left to
12145 // be matched during isel, all of them must be converted to a target specific
12148 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12149 // narrowing and commutation of operands should be handled. The actual code
12150 // doesn't include all of those, work in progress...
12151 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12152 if (NewOp.getNode())
12155 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12157 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12158 // unpckh_undef). Only use pshufd if speed is more important than size.
12159 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12160 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12161 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12162 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12164 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12165 V2IsUndef && MayFoldVectorLoad(V1))
12166 return getMOVDDup(Op, dl, V1, DAG);
12168 if (isMOVHLPS_v_undef_Mask(M, VT))
12169 return getMOVHighToLow(Op, dl, DAG);
12171 // Use to match splats
12172 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12173 (VT == MVT::v2f64 || VT == MVT::v2i64))
12174 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12176 if (isPSHUFDMask(M, VT)) {
12177 // The actual implementation will match the mask in the if above and then
12178 // during isel it can match several different instructions, not only pshufd
12179 // as its name says, sad but true, emulate the behavior for now...
12180 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12181 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12183 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12185 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12186 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12188 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12189 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12192 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12196 if (isPALIGNRMask(M, VT, Subtarget))
12197 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12198 getShufflePALIGNRImmediate(SVOp),
12201 if (isVALIGNMask(M, VT, Subtarget))
12202 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12203 getShuffleVALIGNImmediate(SVOp),
12206 // Check if this can be converted into a logical shift.
12207 bool isLeft = false;
12208 unsigned ShAmt = 0;
12210 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12211 if (isShift && ShVal.hasOneUse()) {
12212 // If the shifted value has multiple uses, it may be cheaper to use
12213 // v_set0 + movlhps or movhlps, etc.
12214 MVT EltVT = VT.getVectorElementType();
12215 ShAmt *= EltVT.getSizeInBits();
12216 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12219 if (isMOVLMask(M, VT)) {
12220 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12221 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12222 if (!isMOVLPMask(M, VT)) {
12223 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12224 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12226 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12227 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12231 // FIXME: fold these into legal mask.
12232 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12233 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12235 if (isMOVHLPSMask(M, VT))
12236 return getMOVHighToLow(Op, dl, DAG);
12238 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12239 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12241 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12242 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12244 if (isMOVLPMask(M, VT))
12245 return getMOVLP(Op, dl, DAG, HasSSE2);
12247 if (ShouldXformToMOVHLPS(M, VT) ||
12248 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12249 return DAG.getCommutedVectorShuffle(*SVOp);
12252 // No better options. Use a vshldq / vsrldq.
12253 MVT EltVT = VT.getVectorElementType();
12254 ShAmt *= EltVT.getSizeInBits();
12255 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12258 bool Commuted = false;
12259 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12260 // 1,1,1,1 -> v8i16 though.
12261 BitVector UndefElements;
12262 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12263 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12265 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12266 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12269 // Canonicalize the splat or undef, if present, to be on the RHS.
12270 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12271 CommuteVectorShuffleMask(M, NumElems);
12273 std::swap(V1IsSplat, V2IsSplat);
12277 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12278 // Shuffling low element of v1 into undef, just return v1.
12281 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12282 // the instruction selector will not match, so get a canonical MOVL with
12283 // swapped operands to undo the commute.
12284 return getMOVL(DAG, dl, VT, V2, V1);
12287 if (isUNPCKLMask(M, VT, HasInt256))
12288 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12290 if (isUNPCKHMask(M, VT, HasInt256))
12291 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12294 // Normalize mask so all entries that point to V2 points to its first
12295 // element then try to match unpck{h|l} again. If match, return a
12296 // new vector_shuffle with the corrected mask.p
12297 SmallVector<int, 8> NewMask(M.begin(), M.end());
12298 NormalizeMask(NewMask, NumElems);
12299 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12300 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12301 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12302 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12306 // Commute is back and try unpck* again.
12307 // FIXME: this seems wrong.
12308 CommuteVectorShuffleMask(M, NumElems);
12310 std::swap(V1IsSplat, V2IsSplat);
12312 if (isUNPCKLMask(M, VT, HasInt256))
12313 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12315 if (isUNPCKHMask(M, VT, HasInt256))
12316 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12319 // Normalize the node to match x86 shuffle ops if needed
12320 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12321 return DAG.getCommutedVectorShuffle(*SVOp);
12323 // The checks below are all present in isShuffleMaskLegal, but they are
12324 // inlined here right now to enable us to directly emit target specific
12325 // nodes, and remove one by one until they don't return Op anymore.
12327 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12328 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12329 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12330 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12333 if (isPSHUFHWMask(M, VT, HasInt256))
12334 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12335 getShufflePSHUFHWImmediate(SVOp),
12338 if (isPSHUFLWMask(M, VT, HasInt256))
12339 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12340 getShufflePSHUFLWImmediate(SVOp),
12343 unsigned MaskValue;
12344 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12346 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12348 if (isSHUFPMask(M, VT))
12349 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12350 getShuffleSHUFImmediate(SVOp), DAG);
12352 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12353 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12354 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12355 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12357 //===--------------------------------------------------------------------===//
12358 // Generate target specific nodes for 128 or 256-bit shuffles only
12359 // supported in the AVX instruction set.
12362 // Handle VMOVDDUPY permutations
12363 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12364 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12366 // Handle VPERMILPS/D* permutations
12367 if (isVPERMILPMask(M, VT)) {
12368 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12369 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12370 getShuffleSHUFImmediate(SVOp), DAG);
12371 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12372 getShuffleSHUFImmediate(SVOp), DAG);
12376 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12377 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12378 Idx*(NumElems/2), DAG, dl);
12380 // Handle VPERM2F128/VPERM2I128 permutations
12381 if (isVPERM2X128Mask(M, VT, HasFp256))
12382 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12383 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12385 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12386 return getINSERTPS(SVOp, dl, DAG);
12389 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12390 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12392 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12393 VT.is512BitVector()) {
12394 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12395 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12396 SmallVector<SDValue, 16> permclMask;
12397 for (unsigned i = 0; i != NumElems; ++i) {
12398 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12401 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12403 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12404 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12405 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12406 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12407 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12410 //===--------------------------------------------------------------------===//
12411 // Since no target specific shuffle was selected for this generic one,
12412 // lower it into other known shuffles. FIXME: this isn't true yet, but
12413 // this is the plan.
12416 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12417 if (VT == MVT::v8i16) {
12418 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12419 if (NewOp.getNode())
12423 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12424 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12425 if (NewOp.getNode())
12429 if (VT == MVT::v16i8) {
12430 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12431 if (NewOp.getNode())
12435 if (VT == MVT::v32i8) {
12436 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12437 if (NewOp.getNode())
12441 // Handle all 128-bit wide vectors with 4 elements, and match them with
12442 // several different shuffle types.
12443 if (NumElems == 4 && VT.is128BitVector())
12444 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12446 // Handle general 256-bit shuffles
12447 if (VT.is256BitVector())
12448 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12453 // This function assumes its argument is a BUILD_VECTOR of constants or
12454 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12456 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12457 unsigned &MaskValue) {
12459 unsigned NumElems = BuildVector->getNumOperands();
12460 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12461 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12462 unsigned NumElemsInLane = NumElems / NumLanes;
12464 // Blend for v16i16 should be symetric for the both lanes.
12465 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12466 SDValue EltCond = BuildVector->getOperand(i);
12467 SDValue SndLaneEltCond =
12468 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12470 int Lane1Cond = -1, Lane2Cond = -1;
12471 if (isa<ConstantSDNode>(EltCond))
12472 Lane1Cond = !isZero(EltCond);
12473 if (isa<ConstantSDNode>(SndLaneEltCond))
12474 Lane2Cond = !isZero(SndLaneEltCond);
12476 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12477 // Lane1Cond != 0, means we want the first argument.
12478 // Lane1Cond == 0, means we want the second argument.
12479 // The encoding of this argument is 0 for the first argument, 1
12480 // for the second. Therefore, invert the condition.
12481 MaskValue |= !Lane1Cond << i;
12482 else if (Lane1Cond < 0)
12483 MaskValue |= !Lane2Cond << i;
12490 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12492 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12493 SelectionDAG &DAG) {
12494 SDValue Cond = Op.getOperand(0);
12495 SDValue LHS = Op.getOperand(1);
12496 SDValue RHS = Op.getOperand(2);
12498 MVT VT = Op.getSimpleValueType();
12499 MVT EltVT = VT.getVectorElementType();
12500 unsigned NumElems = VT.getVectorNumElements();
12502 // There is no blend with immediate in AVX-512.
12503 if (VT.is512BitVector())
12506 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12508 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12511 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12514 // Check the mask for BLEND and build the value.
12515 unsigned MaskValue = 0;
12516 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12519 // Convert i32 vectors to floating point if it is not AVX2.
12520 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12522 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12523 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12525 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12526 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12529 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12530 DAG.getConstant(MaskValue, MVT::i32));
12531 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12534 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12535 // A vselect where all conditions and data are constants can be optimized into
12536 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12537 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12538 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12539 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12542 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12543 if (BlendOp.getNode())
12546 // Some types for vselect were previously set to Expand, not Legal or
12547 // Custom. Return an empty SDValue so we fall-through to Expand, after
12548 // the Custom lowering phase.
12549 MVT VT = Op.getSimpleValueType();
12550 switch (VT.SimpleTy) {
12555 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12560 // We couldn't create a "Blend with immediate" node.
12561 // This node should still be legal, but we'll have to emit a blendv*
12566 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12567 MVT VT = Op.getSimpleValueType();
12570 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12573 if (VT.getSizeInBits() == 8) {
12574 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12575 Op.getOperand(0), Op.getOperand(1));
12576 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12577 DAG.getValueType(VT));
12578 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12581 if (VT.getSizeInBits() == 16) {
12582 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12583 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12585 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12586 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12587 DAG.getNode(ISD::BITCAST, dl,
12590 Op.getOperand(1)));
12591 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12592 Op.getOperand(0), Op.getOperand(1));
12593 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12594 DAG.getValueType(VT));
12595 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12598 if (VT == MVT::f32) {
12599 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12600 // the result back to FR32 register. It's only worth matching if the
12601 // result has a single use which is a store or a bitcast to i32. And in
12602 // the case of a store, it's not worth it if the index is a constant 0,
12603 // because a MOVSSmr can be used instead, which is smaller and faster.
12604 if (!Op.hasOneUse())
12606 SDNode *User = *Op.getNode()->use_begin();
12607 if ((User->getOpcode() != ISD::STORE ||
12608 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12609 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12610 (User->getOpcode() != ISD::BITCAST ||
12611 User->getValueType(0) != MVT::i32))
12613 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12614 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12617 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12620 if (VT == MVT::i32 || VT == MVT::i64) {
12621 // ExtractPS/pextrq works with constant index.
12622 if (isa<ConstantSDNode>(Op.getOperand(1)))
12628 /// Extract one bit from mask vector, like v16i1 or v8i1.
12629 /// AVX-512 feature.
12631 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12632 SDValue Vec = Op.getOperand(0);
12634 MVT VecVT = Vec.getSimpleValueType();
12635 SDValue Idx = Op.getOperand(1);
12636 MVT EltVT = Op.getSimpleValueType();
12638 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12640 // variable index can't be handled in mask registers,
12641 // extend vector to VR512
12642 if (!isa<ConstantSDNode>(Idx)) {
12643 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12644 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12645 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12646 ExtVT.getVectorElementType(), Ext, Idx);
12647 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12650 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12651 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12652 unsigned MaxSift = rc->getSize()*8 - 1;
12653 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12654 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12655 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12656 DAG.getConstant(MaxSift, MVT::i8));
12657 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12658 DAG.getIntPtrConstant(0));
12662 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12663 SelectionDAG &DAG) const {
12665 SDValue Vec = Op.getOperand(0);
12666 MVT VecVT = Vec.getSimpleValueType();
12667 SDValue Idx = Op.getOperand(1);
12669 if (Op.getSimpleValueType() == MVT::i1)
12670 return ExtractBitFromMaskVector(Op, DAG);
12672 if (!isa<ConstantSDNode>(Idx)) {
12673 if (VecVT.is512BitVector() ||
12674 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12675 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12678 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12679 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12680 MaskEltVT.getSizeInBits());
12682 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12683 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12684 getZeroVector(MaskVT, Subtarget, DAG, dl),
12685 Idx, DAG.getConstant(0, getPointerTy()));
12686 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12687 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12688 Perm, DAG.getConstant(0, getPointerTy()));
12693 // If this is a 256-bit vector result, first extract the 128-bit vector and
12694 // then extract the element from the 128-bit vector.
12695 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12697 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12698 // Get the 128-bit vector.
12699 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12700 MVT EltVT = VecVT.getVectorElementType();
12702 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12704 //if (IdxVal >= NumElems/2)
12705 // IdxVal -= NumElems/2;
12706 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12707 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12708 DAG.getConstant(IdxVal, MVT::i32));
12711 assert(VecVT.is128BitVector() && "Unexpected vector length");
12713 if (Subtarget->hasSSE41()) {
12714 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12719 MVT VT = Op.getSimpleValueType();
12720 // TODO: handle v16i8.
12721 if (VT.getSizeInBits() == 16) {
12722 SDValue Vec = Op.getOperand(0);
12723 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12725 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12726 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12727 DAG.getNode(ISD::BITCAST, dl,
12729 Op.getOperand(1)));
12730 // Transform it so it match pextrw which produces a 32-bit result.
12731 MVT EltVT = MVT::i32;
12732 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12733 Op.getOperand(0), Op.getOperand(1));
12734 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12735 DAG.getValueType(VT));
12736 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12739 if (VT.getSizeInBits() == 32) {
12740 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12744 // SHUFPS the element to the lowest double word, then movss.
12745 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12746 MVT VVT = Op.getOperand(0).getSimpleValueType();
12747 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12748 DAG.getUNDEF(VVT), Mask);
12749 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12750 DAG.getIntPtrConstant(0));
12753 if (VT.getSizeInBits() == 64) {
12754 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12755 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12756 // to match extract_elt for f64.
12757 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12761 // UNPCKHPD the element to the lowest double word, then movsd.
12762 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12763 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12764 int Mask[2] = { 1, -1 };
12765 MVT VVT = Op.getOperand(0).getSimpleValueType();
12766 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12767 DAG.getUNDEF(VVT), Mask);
12768 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12769 DAG.getIntPtrConstant(0));
12775 /// Insert one bit to mask vector, like v16i1 or v8i1.
12776 /// AVX-512 feature.
12778 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12780 SDValue Vec = Op.getOperand(0);
12781 SDValue Elt = Op.getOperand(1);
12782 SDValue Idx = Op.getOperand(2);
12783 MVT VecVT = Vec.getSimpleValueType();
12785 if (!isa<ConstantSDNode>(Idx)) {
12786 // Non constant index. Extend source and destination,
12787 // insert element and then truncate the result.
12788 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12789 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12790 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12791 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12792 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12793 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12796 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12797 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12798 if (Vec.getOpcode() == ISD::UNDEF)
12799 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12800 DAG.getConstant(IdxVal, MVT::i8));
12801 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12802 unsigned MaxSift = rc->getSize()*8 - 1;
12803 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12804 DAG.getConstant(MaxSift, MVT::i8));
12805 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12806 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12807 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12810 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12811 SelectionDAG &DAG) const {
12812 MVT VT = Op.getSimpleValueType();
12813 MVT EltVT = VT.getVectorElementType();
12815 if (EltVT == MVT::i1)
12816 return InsertBitToMaskVector(Op, DAG);
12819 SDValue N0 = Op.getOperand(0);
12820 SDValue N1 = Op.getOperand(1);
12821 SDValue N2 = Op.getOperand(2);
12822 if (!isa<ConstantSDNode>(N2))
12824 auto *N2C = cast<ConstantSDNode>(N2);
12825 unsigned IdxVal = N2C->getZExtValue();
12827 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12828 // into that, and then insert the subvector back into the result.
12829 if (VT.is256BitVector() || VT.is512BitVector()) {
12830 // Get the desired 128-bit vector half.
12831 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12833 // Insert the element into the desired half.
12834 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12835 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12837 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12838 DAG.getConstant(IdxIn128, MVT::i32));
12840 // Insert the changed part back to the 256-bit vector
12841 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12843 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12845 if (Subtarget->hasSSE41()) {
12846 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12848 if (VT == MVT::v8i16) {
12849 Opc = X86ISD::PINSRW;
12851 assert(VT == MVT::v16i8);
12852 Opc = X86ISD::PINSRB;
12855 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12857 if (N1.getValueType() != MVT::i32)
12858 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12859 if (N2.getValueType() != MVT::i32)
12860 N2 = DAG.getIntPtrConstant(IdxVal);
12861 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12864 if (EltVT == MVT::f32) {
12865 // Bits [7:6] of the constant are the source select. This will always be
12866 // zero here. The DAG Combiner may combine an extract_elt index into
12868 // bits. For example (insert (extract, 3), 2) could be matched by
12870 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12871 // Bits [5:4] of the constant are the destination select. This is the
12872 // value of the incoming immediate.
12873 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12874 // combine either bitwise AND or insert of float 0.0 to set these bits.
12875 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12876 // Create this as a scalar to vector..
12877 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12878 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12881 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12882 // PINSR* works with constant index.
12887 if (EltVT == MVT::i8)
12890 if (EltVT.getSizeInBits() == 16) {
12891 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12892 // as its second argument.
12893 if (N1.getValueType() != MVT::i32)
12894 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12895 if (N2.getValueType() != MVT::i32)
12896 N2 = DAG.getIntPtrConstant(IdxVal);
12897 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12902 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12904 MVT OpVT = Op.getSimpleValueType();
12906 // If this is a 256-bit vector result, first insert into a 128-bit
12907 // vector and then insert into the 256-bit vector.
12908 if (!OpVT.is128BitVector()) {
12909 // Insert into a 128-bit vector.
12910 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12911 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12912 OpVT.getVectorNumElements() / SizeFactor);
12914 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12916 // Insert the 128-bit vector.
12917 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12920 if (OpVT == MVT::v1i64 &&
12921 Op.getOperand(0).getValueType() == MVT::i64)
12922 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12924 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12925 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12926 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12927 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12930 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12931 // a simple subregister reference or explicit instructions to grab
12932 // upper bits of a vector.
12933 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12934 SelectionDAG &DAG) {
12936 SDValue In = Op.getOperand(0);
12937 SDValue Idx = Op.getOperand(1);
12938 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12939 MVT ResVT = Op.getSimpleValueType();
12940 MVT InVT = In.getSimpleValueType();
12942 if (Subtarget->hasFp256()) {
12943 if (ResVT.is128BitVector() &&
12944 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12945 isa<ConstantSDNode>(Idx)) {
12946 return Extract128BitVector(In, IdxVal, DAG, dl);
12948 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12949 isa<ConstantSDNode>(Idx)) {
12950 return Extract256BitVector(In, IdxVal, DAG, dl);
12956 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12957 // simple superregister reference or explicit instructions to insert
12958 // the upper bits of a vector.
12959 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12960 SelectionDAG &DAG) {
12961 if (Subtarget->hasFp256()) {
12962 SDLoc dl(Op.getNode());
12963 SDValue Vec = Op.getNode()->getOperand(0);
12964 SDValue SubVec = Op.getNode()->getOperand(1);
12965 SDValue Idx = Op.getNode()->getOperand(2);
12967 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12968 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12969 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12970 isa<ConstantSDNode>(Idx)) {
12971 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12972 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12975 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12976 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12977 isa<ConstantSDNode>(Idx)) {
12978 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12979 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12985 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12986 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12987 // one of the above mentioned nodes. It has to be wrapped because otherwise
12988 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12989 // be used to form addressing mode. These wrapped nodes will be selected
12992 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12993 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12995 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12996 // global base reg.
12997 unsigned char OpFlag = 0;
12998 unsigned WrapperKind = X86ISD::Wrapper;
12999 CodeModel::Model M = DAG.getTarget().getCodeModel();
13001 if (Subtarget->isPICStyleRIPRel() &&
13002 (M == CodeModel::Small || M == CodeModel::Kernel))
13003 WrapperKind = X86ISD::WrapperRIP;
13004 else if (Subtarget->isPICStyleGOT())
13005 OpFlag = X86II::MO_GOTOFF;
13006 else if (Subtarget->isPICStyleStubPIC())
13007 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13009 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13010 CP->getAlignment(),
13011 CP->getOffset(), OpFlag);
13013 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13014 // With PIC, the address is actually $g + Offset.
13016 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13017 DAG.getNode(X86ISD::GlobalBaseReg,
13018 SDLoc(), getPointerTy()),
13025 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13026 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13028 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13029 // global base reg.
13030 unsigned char OpFlag = 0;
13031 unsigned WrapperKind = X86ISD::Wrapper;
13032 CodeModel::Model M = DAG.getTarget().getCodeModel();
13034 if (Subtarget->isPICStyleRIPRel() &&
13035 (M == CodeModel::Small || M == CodeModel::Kernel))
13036 WrapperKind = X86ISD::WrapperRIP;
13037 else if (Subtarget->isPICStyleGOT())
13038 OpFlag = X86II::MO_GOTOFF;
13039 else if (Subtarget->isPICStyleStubPIC())
13040 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13042 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13045 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13047 // With PIC, the address is actually $g + Offset.
13049 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13050 DAG.getNode(X86ISD::GlobalBaseReg,
13051 SDLoc(), getPointerTy()),
13058 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13059 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13061 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13062 // global base reg.
13063 unsigned char OpFlag = 0;
13064 unsigned WrapperKind = X86ISD::Wrapper;
13065 CodeModel::Model M = DAG.getTarget().getCodeModel();
13067 if (Subtarget->isPICStyleRIPRel() &&
13068 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13069 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13070 OpFlag = X86II::MO_GOTPCREL;
13071 WrapperKind = X86ISD::WrapperRIP;
13072 } else if (Subtarget->isPICStyleGOT()) {
13073 OpFlag = X86II::MO_GOT;
13074 } else if (Subtarget->isPICStyleStubPIC()) {
13075 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13076 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13077 OpFlag = X86II::MO_DARWIN_NONLAZY;
13080 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13083 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13085 // With PIC, the address is actually $g + Offset.
13086 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13087 !Subtarget->is64Bit()) {
13088 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13089 DAG.getNode(X86ISD::GlobalBaseReg,
13090 SDLoc(), getPointerTy()),
13094 // For symbols that require a load from a stub to get the address, emit the
13096 if (isGlobalStubReference(OpFlag))
13097 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13098 MachinePointerInfo::getGOT(), false, false, false, 0);
13104 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13105 // Create the TargetBlockAddressAddress node.
13106 unsigned char OpFlags =
13107 Subtarget->ClassifyBlockAddressReference();
13108 CodeModel::Model M = DAG.getTarget().getCodeModel();
13109 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13110 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13112 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13115 if (Subtarget->isPICStyleRIPRel() &&
13116 (M == CodeModel::Small || M == CodeModel::Kernel))
13117 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13119 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13121 // With PIC, the address is actually $g + Offset.
13122 if (isGlobalRelativeToPICBase(OpFlags)) {
13123 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13124 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13132 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13133 int64_t Offset, SelectionDAG &DAG) const {
13134 // Create the TargetGlobalAddress node, folding in the constant
13135 // offset if it is legal.
13136 unsigned char OpFlags =
13137 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13138 CodeModel::Model M = DAG.getTarget().getCodeModel();
13140 if (OpFlags == X86II::MO_NO_FLAG &&
13141 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13142 // A direct static reference to a global.
13143 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13146 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13149 if (Subtarget->isPICStyleRIPRel() &&
13150 (M == CodeModel::Small || M == CodeModel::Kernel))
13151 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13153 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13155 // With PIC, the address is actually $g + Offset.
13156 if (isGlobalRelativeToPICBase(OpFlags)) {
13157 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13158 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13162 // For globals that require a load from a stub to get the address, emit the
13164 if (isGlobalStubReference(OpFlags))
13165 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13166 MachinePointerInfo::getGOT(), false, false, false, 0);
13168 // If there was a non-zero offset that we didn't fold, create an explicit
13169 // addition for it.
13171 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13172 DAG.getConstant(Offset, getPointerTy()));
13178 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13179 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13180 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13181 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13185 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13186 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13187 unsigned char OperandFlags, bool LocalDynamic = false) {
13188 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13189 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13191 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13192 GA->getValueType(0),
13196 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13200 SDValue Ops[] = { Chain, TGA, *InFlag };
13201 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13203 SDValue Ops[] = { Chain, TGA };
13204 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13207 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13208 MFI->setAdjustsStack(true);
13209 MFI->setHasCalls(true);
13211 SDValue Flag = Chain.getValue(1);
13212 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13215 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13217 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13220 SDLoc dl(GA); // ? function entry point might be better
13221 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13222 DAG.getNode(X86ISD::GlobalBaseReg,
13223 SDLoc(), PtrVT), InFlag);
13224 InFlag = Chain.getValue(1);
13226 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13229 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13231 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13233 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13234 X86::RAX, X86II::MO_TLSGD);
13237 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13243 // Get the start address of the TLS block for this module.
13244 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13245 .getInfo<X86MachineFunctionInfo>();
13246 MFI->incNumLocalDynamicTLSAccesses();
13250 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13251 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13254 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13255 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13256 InFlag = Chain.getValue(1);
13257 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13258 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13261 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13265 unsigned char OperandFlags = X86II::MO_DTPOFF;
13266 unsigned WrapperKind = X86ISD::Wrapper;
13267 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13268 GA->getValueType(0),
13269 GA->getOffset(), OperandFlags);
13270 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13272 // Add x@dtpoff with the base.
13273 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13276 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13277 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13278 const EVT PtrVT, TLSModel::Model model,
13279 bool is64Bit, bool isPIC) {
13282 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13283 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13284 is64Bit ? 257 : 256));
13286 SDValue ThreadPointer =
13287 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13288 MachinePointerInfo(Ptr), false, false, false, 0);
13290 unsigned char OperandFlags = 0;
13291 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13293 unsigned WrapperKind = X86ISD::Wrapper;
13294 if (model == TLSModel::LocalExec) {
13295 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13296 } else if (model == TLSModel::InitialExec) {
13298 OperandFlags = X86II::MO_GOTTPOFF;
13299 WrapperKind = X86ISD::WrapperRIP;
13301 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13304 llvm_unreachable("Unexpected model");
13307 // emit "addl x@ntpoff,%eax" (local exec)
13308 // or "addl x@indntpoff,%eax" (initial exec)
13309 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13311 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13312 GA->getOffset(), OperandFlags);
13313 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13315 if (model == TLSModel::InitialExec) {
13316 if (isPIC && !is64Bit) {
13317 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13318 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13322 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13323 MachinePointerInfo::getGOT(), false, false, false, 0);
13326 // The address of the thread local variable is the add of the thread
13327 // pointer with the offset of the variable.
13328 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13332 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13334 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13335 const GlobalValue *GV = GA->getGlobal();
13337 if (Subtarget->isTargetELF()) {
13338 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13341 case TLSModel::GeneralDynamic:
13342 if (Subtarget->is64Bit())
13343 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13344 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13345 case TLSModel::LocalDynamic:
13346 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13347 Subtarget->is64Bit());
13348 case TLSModel::InitialExec:
13349 case TLSModel::LocalExec:
13350 return LowerToTLSExecModel(
13351 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13352 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13354 llvm_unreachable("Unknown TLS model.");
13357 if (Subtarget->isTargetDarwin()) {
13358 // Darwin only has one model of TLS. Lower to that.
13359 unsigned char OpFlag = 0;
13360 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13361 X86ISD::WrapperRIP : X86ISD::Wrapper;
13363 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13364 // global base reg.
13365 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13366 !Subtarget->is64Bit();
13368 OpFlag = X86II::MO_TLVP_PIC_BASE;
13370 OpFlag = X86II::MO_TLVP;
13372 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13373 GA->getValueType(0),
13374 GA->getOffset(), OpFlag);
13375 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13377 // With PIC32, the address is actually $g + Offset.
13379 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13380 DAG.getNode(X86ISD::GlobalBaseReg,
13381 SDLoc(), getPointerTy()),
13384 // Lowering the machine isd will make sure everything is in the right
13386 SDValue Chain = DAG.getEntryNode();
13387 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13388 SDValue Args[] = { Chain, Offset };
13389 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13391 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13392 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13393 MFI->setAdjustsStack(true);
13395 // And our return value (tls address) is in the standard call return value
13397 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13398 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13399 Chain.getValue(1));
13402 if (Subtarget->isTargetKnownWindowsMSVC() ||
13403 Subtarget->isTargetWindowsGNU()) {
13404 // Just use the implicit TLS architecture
13405 // Need to generate someting similar to:
13406 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13408 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13409 // mov rcx, qword [rdx+rcx*8]
13410 // mov eax, .tls$:tlsvar
13411 // [rax+rcx] contains the address
13412 // Windows 64bit: gs:0x58
13413 // Windows 32bit: fs:__tls_array
13416 SDValue Chain = DAG.getEntryNode();
13418 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13419 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13420 // use its literal value of 0x2C.
13421 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13422 ? Type::getInt8PtrTy(*DAG.getContext(),
13424 : Type::getInt32PtrTy(*DAG.getContext(),
13428 Subtarget->is64Bit()
13429 ? DAG.getIntPtrConstant(0x58)
13430 : (Subtarget->isTargetWindowsGNU()
13431 ? DAG.getIntPtrConstant(0x2C)
13432 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13434 SDValue ThreadPointer =
13435 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13436 MachinePointerInfo(Ptr), false, false, false, 0);
13438 // Load the _tls_index variable
13439 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13440 if (Subtarget->is64Bit())
13441 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13442 IDX, MachinePointerInfo(), MVT::i32,
13443 false, false, false, 0);
13445 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13446 false, false, false, 0);
13448 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13450 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13452 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13453 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13454 false, false, false, 0);
13456 // Get the offset of start of .tls section
13457 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13458 GA->getValueType(0),
13459 GA->getOffset(), X86II::MO_SECREL);
13460 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13462 // The address of the thread local variable is the add of the thread
13463 // pointer with the offset of the variable.
13464 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13467 llvm_unreachable("TLS not implemented for this target.");
13470 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13471 /// and take a 2 x i32 value to shift plus a shift amount.
13472 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13473 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13474 MVT VT = Op.getSimpleValueType();
13475 unsigned VTBits = VT.getSizeInBits();
13477 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13478 SDValue ShOpLo = Op.getOperand(0);
13479 SDValue ShOpHi = Op.getOperand(1);
13480 SDValue ShAmt = Op.getOperand(2);
13481 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13482 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13484 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13485 DAG.getConstant(VTBits - 1, MVT::i8));
13486 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13487 DAG.getConstant(VTBits - 1, MVT::i8))
13488 : DAG.getConstant(0, VT);
13490 SDValue Tmp2, Tmp3;
13491 if (Op.getOpcode() == ISD::SHL_PARTS) {
13492 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13493 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13495 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13496 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13499 // If the shift amount is larger or equal than the width of a part we can't
13500 // rely on the results of shld/shrd. Insert a test and select the appropriate
13501 // values for large shift amounts.
13502 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13503 DAG.getConstant(VTBits, MVT::i8));
13504 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13505 AndNode, DAG.getConstant(0, MVT::i8));
13508 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13509 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13510 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13512 if (Op.getOpcode() == ISD::SHL_PARTS) {
13513 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13514 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13516 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13517 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13520 SDValue Ops[2] = { Lo, Hi };
13521 return DAG.getMergeValues(Ops, dl);
13524 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13525 SelectionDAG &DAG) const {
13526 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13529 if (SrcVT.isVector()) {
13530 if (SrcVT.getVectorElementType() == MVT::i1) {
13531 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13532 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13533 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13534 Op.getOperand(0)));
13539 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13540 "Unknown SINT_TO_FP to lower!");
13542 // These are really Legal; return the operand so the caller accepts it as
13544 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13546 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13547 Subtarget->is64Bit()) {
13551 unsigned Size = SrcVT.getSizeInBits()/8;
13552 MachineFunction &MF = DAG.getMachineFunction();
13553 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13554 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13555 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13557 MachinePointerInfo::getFixedStack(SSFI),
13559 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13562 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13564 SelectionDAG &DAG) const {
13568 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13570 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13572 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13574 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13576 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13577 MachineMemOperand *MMO;
13579 int SSFI = FI->getIndex();
13581 DAG.getMachineFunction()
13582 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13583 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13585 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13586 StackSlot = StackSlot.getOperand(1);
13588 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13589 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13591 Tys, Ops, SrcVT, MMO);
13594 Chain = Result.getValue(1);
13595 SDValue InFlag = Result.getValue(2);
13597 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13598 // shouldn't be necessary except that RFP cannot be live across
13599 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13600 MachineFunction &MF = DAG.getMachineFunction();
13601 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13602 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13603 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13604 Tys = DAG.getVTList(MVT::Other);
13606 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13608 MachineMemOperand *MMO =
13609 DAG.getMachineFunction()
13610 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13611 MachineMemOperand::MOStore, SSFISize, SSFISize);
13613 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13614 Ops, Op.getValueType(), MMO);
13615 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13616 MachinePointerInfo::getFixedStack(SSFI),
13617 false, false, false, 0);
13623 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13624 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13625 SelectionDAG &DAG) const {
13626 // This algorithm is not obvious. Here it is what we're trying to output:
13629 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13630 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13632 haddpd %xmm0, %xmm0
13634 pshufd $0x4e, %xmm0, %xmm1
13640 LLVMContext *Context = DAG.getContext();
13642 // Build some magic constants.
13643 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13644 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13645 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13647 SmallVector<Constant*,2> CV1;
13649 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13650 APInt(64, 0x4330000000000000ULL))));
13652 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13653 APInt(64, 0x4530000000000000ULL))));
13654 Constant *C1 = ConstantVector::get(CV1);
13655 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13657 // Load the 64-bit value into an XMM register.
13658 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13660 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13661 MachinePointerInfo::getConstantPool(),
13662 false, false, false, 16);
13663 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13664 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13667 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13668 MachinePointerInfo::getConstantPool(),
13669 false, false, false, 16);
13670 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13671 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13674 if (Subtarget->hasSSE3()) {
13675 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13676 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13678 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13679 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13681 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13682 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13686 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13687 DAG.getIntPtrConstant(0));
13690 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13691 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13692 SelectionDAG &DAG) const {
13694 // FP constant to bias correct the final result.
13695 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13698 // Load the 32-bit value into an XMM register.
13699 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13702 // Zero out the upper parts of the register.
13703 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13705 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13706 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13707 DAG.getIntPtrConstant(0));
13709 // Or the load with the bias.
13710 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13711 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13712 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13713 MVT::v2f64, Load)),
13714 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13715 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13716 MVT::v2f64, Bias)));
13717 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13718 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13719 DAG.getIntPtrConstant(0));
13721 // Subtract the bias.
13722 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13724 // Handle final rounding.
13725 EVT DestVT = Op.getValueType();
13727 if (DestVT.bitsLT(MVT::f64))
13728 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13729 DAG.getIntPtrConstant(0));
13730 if (DestVT.bitsGT(MVT::f64))
13731 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13733 // Handle final rounding.
13737 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13738 const X86Subtarget &Subtarget) {
13739 // The algorithm is the following:
13740 // #ifdef __SSE4_1__
13741 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13742 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13743 // (uint4) 0x53000000, 0xaa);
13745 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13746 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13748 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13749 // return (float4) lo + fhi;
13752 SDValue V = Op->getOperand(0);
13753 EVT VecIntVT = V.getValueType();
13754 bool Is128 = VecIntVT == MVT::v4i32;
13755 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13756 // If we convert to something else than the supported type, e.g., to v4f64,
13758 if (VecFloatVT != Op->getValueType(0))
13761 unsigned NumElts = VecIntVT.getVectorNumElements();
13762 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13763 "Unsupported custom type");
13764 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13766 // In the #idef/#else code, we have in common:
13767 // - The vector of constants:
13773 // Create the splat vector for 0x4b000000.
13774 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13775 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13776 CstLow, CstLow, CstLow, CstLow};
13777 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13778 makeArrayRef(&CstLowArray[0], NumElts));
13779 // Create the splat vector for 0x53000000.
13780 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13781 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13782 CstHigh, CstHigh, CstHigh, CstHigh};
13783 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13784 makeArrayRef(&CstHighArray[0], NumElts));
13786 // Create the right shift.
13787 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13788 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13789 CstShift, CstShift, CstShift, CstShift};
13790 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13791 makeArrayRef(&CstShiftArray[0], NumElts));
13792 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13795 if (Subtarget.hasSSE41()) {
13796 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13797 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13798 SDValue VecCstLowBitcast =
13799 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13800 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13801 // Low will be bitcasted right away, so do not bother bitcasting back to its
13803 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13804 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13805 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13806 // (uint4) 0x53000000, 0xaa);
13807 SDValue VecCstHighBitcast =
13808 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13809 SDValue VecShiftBitcast =
13810 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13811 // High will be bitcasted right away, so do not bother bitcasting back to
13812 // its original type.
13813 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13814 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13816 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13817 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13818 CstMask, CstMask, CstMask);
13819 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13820 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13821 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13823 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13824 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13827 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13828 SDValue CstFAdd = DAG.getConstantFP(
13829 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13830 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13831 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13832 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13833 makeArrayRef(&CstFAddArray[0], NumElts));
13835 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13836 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13838 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13839 // return (float4) lo + fhi;
13840 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13841 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13844 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13845 SelectionDAG &DAG) const {
13846 SDValue N0 = Op.getOperand(0);
13847 MVT SVT = N0.getSimpleValueType();
13850 switch (SVT.SimpleTy) {
13852 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13857 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13858 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13859 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13863 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13865 llvm_unreachable(nullptr);
13868 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13869 SelectionDAG &DAG) const {
13870 SDValue N0 = Op.getOperand(0);
13873 if (Op.getValueType().isVector())
13874 return lowerUINT_TO_FP_vec(Op, DAG);
13876 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13877 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13878 // the optimization here.
13879 if (DAG.SignBitIsZero(N0))
13880 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13882 MVT SrcVT = N0.getSimpleValueType();
13883 MVT DstVT = Op.getSimpleValueType();
13884 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13885 return LowerUINT_TO_FP_i64(Op, DAG);
13886 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13887 return LowerUINT_TO_FP_i32(Op, DAG);
13888 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13891 // Make a 64-bit buffer, and use it to build an FILD.
13892 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13893 if (SrcVT == MVT::i32) {
13894 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13895 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13896 getPointerTy(), StackSlot, WordOff);
13897 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13898 StackSlot, MachinePointerInfo(),
13900 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13901 OffsetSlot, MachinePointerInfo(),
13903 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13907 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13908 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13909 StackSlot, MachinePointerInfo(),
13911 // For i64 source, we need to add the appropriate power of 2 if the input
13912 // was negative. This is the same as the optimization in
13913 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13914 // we must be careful to do the computation in x87 extended precision, not
13915 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13916 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13917 MachineMemOperand *MMO =
13918 DAG.getMachineFunction()
13919 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13920 MachineMemOperand::MOLoad, 8, 8);
13922 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13923 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13924 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13927 APInt FF(32, 0x5F800000ULL);
13929 // Check whether the sign bit is set.
13930 SDValue SignSet = DAG.getSetCC(dl,
13931 getSetCCResultType(*DAG.getContext(), MVT::i64),
13932 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13935 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13936 SDValue FudgePtr = DAG.getConstantPool(
13937 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13940 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13941 SDValue Zero = DAG.getIntPtrConstant(0);
13942 SDValue Four = DAG.getIntPtrConstant(4);
13943 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13945 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13947 // Load the value out, extending it from f32 to f80.
13948 // FIXME: Avoid the extend by constructing the right constant pool?
13949 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13950 FudgePtr, MachinePointerInfo::getConstantPool(),
13951 MVT::f32, false, false, false, 4);
13952 // Extend everything to 80 bits to force it to be done on x87.
13953 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13954 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13957 std::pair<SDValue,SDValue>
13958 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13959 bool IsSigned, bool IsReplace) const {
13962 EVT DstTy = Op.getValueType();
13964 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13965 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13969 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13970 DstTy.getSimpleVT() >= MVT::i16 &&
13971 "Unknown FP_TO_INT to lower!");
13973 // These are really Legal.
13974 if (DstTy == MVT::i32 &&
13975 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13976 return std::make_pair(SDValue(), SDValue());
13977 if (Subtarget->is64Bit() &&
13978 DstTy == MVT::i64 &&
13979 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13980 return std::make_pair(SDValue(), SDValue());
13982 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13983 // stack slot, or into the FTOL runtime function.
13984 MachineFunction &MF = DAG.getMachineFunction();
13985 unsigned MemSize = DstTy.getSizeInBits()/8;
13986 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13987 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13990 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13991 Opc = X86ISD::WIN_FTOL;
13993 switch (DstTy.getSimpleVT().SimpleTy) {
13994 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13995 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13996 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13997 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14000 SDValue Chain = DAG.getEntryNode();
14001 SDValue Value = Op.getOperand(0);
14002 EVT TheVT = Op.getOperand(0).getValueType();
14003 // FIXME This causes a redundant load/store if the SSE-class value is already
14004 // in memory, such as if it is on the callstack.
14005 if (isScalarFPTypeInSSEReg(TheVT)) {
14006 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14007 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14008 MachinePointerInfo::getFixedStack(SSFI),
14010 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14012 Chain, StackSlot, DAG.getValueType(TheVT)
14015 MachineMemOperand *MMO =
14016 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14017 MachineMemOperand::MOLoad, MemSize, MemSize);
14018 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14019 Chain = Value.getValue(1);
14020 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14021 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14024 MachineMemOperand *MMO =
14025 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14026 MachineMemOperand::MOStore, MemSize, MemSize);
14028 if (Opc != X86ISD::WIN_FTOL) {
14029 // Build the FP_TO_INT*_IN_MEM
14030 SDValue Ops[] = { Chain, Value, StackSlot };
14031 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14033 return std::make_pair(FIST, StackSlot);
14035 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14036 DAG.getVTList(MVT::Other, MVT::Glue),
14038 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14039 MVT::i32, ftol.getValue(1));
14040 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14041 MVT::i32, eax.getValue(2));
14042 SDValue Ops[] = { eax, edx };
14043 SDValue pair = IsReplace
14044 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14045 : DAG.getMergeValues(Ops, DL);
14046 return std::make_pair(pair, SDValue());
14050 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14051 const X86Subtarget *Subtarget) {
14052 MVT VT = Op->getSimpleValueType(0);
14053 SDValue In = Op->getOperand(0);
14054 MVT InVT = In.getSimpleValueType();
14057 // Optimize vectors in AVX mode:
14060 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14061 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14062 // Concat upper and lower parts.
14065 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14066 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14067 // Concat upper and lower parts.
14070 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14071 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14072 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14075 if (Subtarget->hasInt256())
14076 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14078 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14079 SDValue Undef = DAG.getUNDEF(InVT);
14080 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14081 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14082 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14084 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14085 VT.getVectorNumElements()/2);
14087 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14088 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14090 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14093 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14094 SelectionDAG &DAG) {
14095 MVT VT = Op->getSimpleValueType(0);
14096 SDValue In = Op->getOperand(0);
14097 MVT InVT = In.getSimpleValueType();
14099 unsigned int NumElts = VT.getVectorNumElements();
14100 if (NumElts != 8 && NumElts != 16)
14103 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14104 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14106 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14107 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14108 // Now we have only mask extension
14109 assert(InVT.getVectorElementType() == MVT::i1);
14110 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14111 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14112 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14113 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14114 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14115 MachinePointerInfo::getConstantPool(),
14116 false, false, false, Alignment);
14118 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14119 if (VT.is512BitVector())
14121 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14124 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14125 SelectionDAG &DAG) {
14126 if (Subtarget->hasFp256()) {
14127 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14135 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14136 SelectionDAG &DAG) {
14138 MVT VT = Op.getSimpleValueType();
14139 SDValue In = Op.getOperand(0);
14140 MVT SVT = In.getSimpleValueType();
14142 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14143 return LowerZERO_EXTEND_AVX512(Op, DAG);
14145 if (Subtarget->hasFp256()) {
14146 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14151 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14152 VT.getVectorNumElements() != SVT.getVectorNumElements());
14156 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14158 MVT VT = Op.getSimpleValueType();
14159 SDValue In = Op.getOperand(0);
14160 MVT InVT = In.getSimpleValueType();
14162 if (VT == MVT::i1) {
14163 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14164 "Invalid scalar TRUNCATE operation");
14165 if (InVT.getSizeInBits() >= 32)
14167 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14168 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14170 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14171 "Invalid TRUNCATE operation");
14173 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14174 if (VT.getVectorElementType().getSizeInBits() >=8)
14175 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14177 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14178 unsigned NumElts = InVT.getVectorNumElements();
14179 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14180 if (InVT.getSizeInBits() < 512) {
14181 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14182 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14186 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14187 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14188 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14189 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14190 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14191 MachinePointerInfo::getConstantPool(),
14192 false, false, false, Alignment);
14193 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14194 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14195 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14198 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14199 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14200 if (Subtarget->hasInt256()) {
14201 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14202 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14203 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14205 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14206 DAG.getIntPtrConstant(0));
14209 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14210 DAG.getIntPtrConstant(0));
14211 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14212 DAG.getIntPtrConstant(2));
14213 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14214 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14215 static const int ShufMask[] = {0, 2, 4, 6};
14216 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14219 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14220 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14221 if (Subtarget->hasInt256()) {
14222 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14224 SmallVector<SDValue,32> pshufbMask;
14225 for (unsigned i = 0; i < 2; ++i) {
14226 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14227 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14228 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14229 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14230 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14231 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14232 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14233 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14234 for (unsigned j = 0; j < 8; ++j)
14235 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14237 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14238 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14239 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14241 static const int ShufMask[] = {0, 2, -1, -1};
14242 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14244 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14245 DAG.getIntPtrConstant(0));
14246 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14249 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14250 DAG.getIntPtrConstant(0));
14252 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14253 DAG.getIntPtrConstant(4));
14255 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14256 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14258 // The PSHUFB mask:
14259 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14260 -1, -1, -1, -1, -1, -1, -1, -1};
14262 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14263 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14264 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14266 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14267 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14269 // The MOVLHPS Mask:
14270 static const int ShufMask2[] = {0, 1, 4, 5};
14271 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14272 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14275 // Handle truncation of V256 to V128 using shuffles.
14276 if (!VT.is128BitVector() || !InVT.is256BitVector())
14279 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14281 unsigned NumElems = VT.getVectorNumElements();
14282 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14284 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14285 // Prepare truncation shuffle mask
14286 for (unsigned i = 0; i != NumElems; ++i)
14287 MaskVec[i] = i * 2;
14288 SDValue V = DAG.getVectorShuffle(NVT, DL,
14289 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14290 DAG.getUNDEF(NVT), &MaskVec[0]);
14291 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14292 DAG.getIntPtrConstant(0));
14295 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14296 SelectionDAG &DAG) const {
14297 assert(!Op.getSimpleValueType().isVector());
14299 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14300 /*IsSigned=*/ true, /*IsReplace=*/ false);
14301 SDValue FIST = Vals.first, StackSlot = Vals.second;
14302 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14303 if (!FIST.getNode()) return Op;
14305 if (StackSlot.getNode())
14306 // Load the result.
14307 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14308 FIST, StackSlot, MachinePointerInfo(),
14309 false, false, false, 0);
14311 // The node is the result.
14315 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14316 SelectionDAG &DAG) const {
14317 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14318 /*IsSigned=*/ false, /*IsReplace=*/ false);
14319 SDValue FIST = Vals.first, StackSlot = Vals.second;
14320 assert(FIST.getNode() && "Unexpected failure");
14322 if (StackSlot.getNode())
14323 // Load the result.
14324 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14325 FIST, StackSlot, MachinePointerInfo(),
14326 false, false, false, 0);
14328 // The node is the result.
14332 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14334 MVT VT = Op.getSimpleValueType();
14335 SDValue In = Op.getOperand(0);
14336 MVT SVT = In.getSimpleValueType();
14338 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14340 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14341 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14342 In, DAG.getUNDEF(SVT)));
14345 /// The only differences between FABS and FNEG are the mask and the logic op.
14346 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14347 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14348 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14349 "Wrong opcode for lowering FABS or FNEG.");
14351 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14353 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14354 // into an FNABS. We'll lower the FABS after that if it is still in use.
14356 for (SDNode *User : Op->uses())
14357 if (User->getOpcode() == ISD::FNEG)
14360 SDValue Op0 = Op.getOperand(0);
14361 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14364 MVT VT = Op.getSimpleValueType();
14365 // Assume scalar op for initialization; update for vector if needed.
14366 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14367 // generate a 16-byte vector constant and logic op even for the scalar case.
14368 // Using a 16-byte mask allows folding the load of the mask with
14369 // the logic op, so it can save (~4 bytes) on code size.
14371 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14372 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14373 // decide if we should generate a 16-byte constant mask when we only need 4 or
14374 // 8 bytes for the scalar case.
14375 if (VT.isVector()) {
14376 EltVT = VT.getVectorElementType();
14377 NumElts = VT.getVectorNumElements();
14380 unsigned EltBits = EltVT.getSizeInBits();
14381 LLVMContext *Context = DAG.getContext();
14382 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14384 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14385 Constant *C = ConstantInt::get(*Context, MaskElt);
14386 C = ConstantVector::getSplat(NumElts, C);
14387 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14388 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14389 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14390 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14391 MachinePointerInfo::getConstantPool(),
14392 false, false, false, Alignment);
14394 if (VT.isVector()) {
14395 // For a vector, cast operands to a vector type, perform the logic op,
14396 // and cast the result back to the original value type.
14397 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14398 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14399 SDValue Operand = IsFNABS ?
14400 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14401 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14402 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14403 return DAG.getNode(ISD::BITCAST, dl, VT,
14404 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14407 // If not vector, then scalar.
14408 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14409 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14410 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14413 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14414 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14415 LLVMContext *Context = DAG.getContext();
14416 SDValue Op0 = Op.getOperand(0);
14417 SDValue Op1 = Op.getOperand(1);
14419 MVT VT = Op.getSimpleValueType();
14420 MVT SrcVT = Op1.getSimpleValueType();
14422 // If second operand is smaller, extend it first.
14423 if (SrcVT.bitsLT(VT)) {
14424 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14427 // And if it is bigger, shrink it first.
14428 if (SrcVT.bitsGT(VT)) {
14429 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14433 // At this point the operands and the result should have the same
14434 // type, and that won't be f80 since that is not custom lowered.
14436 // First get the sign bit of second operand.
14437 SmallVector<Constant*,4> CV;
14438 if (SrcVT == MVT::f64) {
14439 const fltSemantics &Sem = APFloat::IEEEdouble;
14440 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14441 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14443 const fltSemantics &Sem = APFloat::IEEEsingle;
14444 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14445 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14446 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14447 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14449 Constant *C = ConstantVector::get(CV);
14450 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14451 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14452 MachinePointerInfo::getConstantPool(),
14453 false, false, false, 16);
14454 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14456 // Shift sign bit right or left if the two operands have different types.
14457 if (SrcVT.bitsGT(VT)) {
14458 // Op0 is MVT::f32, Op1 is MVT::f64.
14459 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14460 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14461 DAG.getConstant(32, MVT::i32));
14462 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14463 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14464 DAG.getIntPtrConstant(0));
14467 // Clear first operand sign bit.
14469 if (VT == MVT::f64) {
14470 const fltSemantics &Sem = APFloat::IEEEdouble;
14471 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14472 APInt(64, ~(1ULL << 63)))));
14473 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14475 const fltSemantics &Sem = APFloat::IEEEsingle;
14476 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14477 APInt(32, ~(1U << 31)))));
14478 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14479 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14480 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14482 C = ConstantVector::get(CV);
14483 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14484 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14485 MachinePointerInfo::getConstantPool(),
14486 false, false, false, 16);
14487 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14489 // Or the value with the sign bit.
14490 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14493 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14494 SDValue N0 = Op.getOperand(0);
14496 MVT VT = Op.getSimpleValueType();
14498 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14499 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14500 DAG.getConstant(1, VT));
14501 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14504 // Check whether an OR'd tree is PTEST-able.
14505 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14506 SelectionDAG &DAG) {
14507 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14509 if (!Subtarget->hasSSE41())
14512 if (!Op->hasOneUse())
14515 SDNode *N = Op.getNode();
14518 SmallVector<SDValue, 8> Opnds;
14519 DenseMap<SDValue, unsigned> VecInMap;
14520 SmallVector<SDValue, 8> VecIns;
14521 EVT VT = MVT::Other;
14523 // Recognize a special case where a vector is casted into wide integer to
14525 Opnds.push_back(N->getOperand(0));
14526 Opnds.push_back(N->getOperand(1));
14528 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14529 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14530 // BFS traverse all OR'd operands.
14531 if (I->getOpcode() == ISD::OR) {
14532 Opnds.push_back(I->getOperand(0));
14533 Opnds.push_back(I->getOperand(1));
14534 // Re-evaluate the number of nodes to be traversed.
14535 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14539 // Quit if a non-EXTRACT_VECTOR_ELT
14540 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14543 // Quit if without a constant index.
14544 SDValue Idx = I->getOperand(1);
14545 if (!isa<ConstantSDNode>(Idx))
14548 SDValue ExtractedFromVec = I->getOperand(0);
14549 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14550 if (M == VecInMap.end()) {
14551 VT = ExtractedFromVec.getValueType();
14552 // Quit if not 128/256-bit vector.
14553 if (!VT.is128BitVector() && !VT.is256BitVector())
14555 // Quit if not the same type.
14556 if (VecInMap.begin() != VecInMap.end() &&
14557 VT != VecInMap.begin()->first.getValueType())
14559 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14560 VecIns.push_back(ExtractedFromVec);
14562 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14565 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14566 "Not extracted from 128-/256-bit vector.");
14568 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14570 for (DenseMap<SDValue, unsigned>::const_iterator
14571 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14572 // Quit if not all elements are used.
14573 if (I->second != FullMask)
14577 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14579 // Cast all vectors into TestVT for PTEST.
14580 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14581 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14583 // If more than one full vectors are evaluated, OR them first before PTEST.
14584 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14585 // Each iteration will OR 2 nodes and append the result until there is only
14586 // 1 node left, i.e. the final OR'd value of all vectors.
14587 SDValue LHS = VecIns[Slot];
14588 SDValue RHS = VecIns[Slot + 1];
14589 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14592 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14593 VecIns.back(), VecIns.back());
14596 /// \brief return true if \c Op has a use that doesn't just read flags.
14597 static bool hasNonFlagsUse(SDValue Op) {
14598 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14600 SDNode *User = *UI;
14601 unsigned UOpNo = UI.getOperandNo();
14602 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14603 // Look pass truncate.
14604 UOpNo = User->use_begin().getOperandNo();
14605 User = *User->use_begin();
14608 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14609 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14615 /// Emit nodes that will be selected as "test Op0,Op0", or something
14617 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14618 SelectionDAG &DAG) const {
14619 if (Op.getValueType() == MVT::i1)
14620 // KORTEST instruction should be selected
14621 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14622 DAG.getConstant(0, Op.getValueType()));
14624 // CF and OF aren't always set the way we want. Determine which
14625 // of these we need.
14626 bool NeedCF = false;
14627 bool NeedOF = false;
14630 case X86::COND_A: case X86::COND_AE:
14631 case X86::COND_B: case X86::COND_BE:
14634 case X86::COND_G: case X86::COND_GE:
14635 case X86::COND_L: case X86::COND_LE:
14636 case X86::COND_O: case X86::COND_NO: {
14637 // Check if we really need to set the
14638 // Overflow flag. If NoSignedWrap is present
14639 // that is not actually needed.
14640 switch (Op->getOpcode()) {
14645 const BinaryWithFlagsSDNode *BinNode =
14646 cast<BinaryWithFlagsSDNode>(Op.getNode());
14647 if (BinNode->hasNoSignedWrap())
14657 // See if we can use the EFLAGS value from the operand instead of
14658 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14659 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14660 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14661 // Emit a CMP with 0, which is the TEST pattern.
14662 //if (Op.getValueType() == MVT::i1)
14663 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14664 // DAG.getConstant(0, MVT::i1));
14665 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14666 DAG.getConstant(0, Op.getValueType()));
14668 unsigned Opcode = 0;
14669 unsigned NumOperands = 0;
14671 // Truncate operations may prevent the merge of the SETCC instruction
14672 // and the arithmetic instruction before it. Attempt to truncate the operands
14673 // of the arithmetic instruction and use a reduced bit-width instruction.
14674 bool NeedTruncation = false;
14675 SDValue ArithOp = Op;
14676 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14677 SDValue Arith = Op->getOperand(0);
14678 // Both the trunc and the arithmetic op need to have one user each.
14679 if (Arith->hasOneUse())
14680 switch (Arith.getOpcode()) {
14687 NeedTruncation = true;
14693 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14694 // which may be the result of a CAST. We use the variable 'Op', which is the
14695 // non-casted variable when we check for possible users.
14696 switch (ArithOp.getOpcode()) {
14698 // Due to an isel shortcoming, be conservative if this add is likely to be
14699 // selected as part of a load-modify-store instruction. When the root node
14700 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14701 // uses of other nodes in the match, such as the ADD in this case. This
14702 // leads to the ADD being left around and reselected, with the result being
14703 // two adds in the output. Alas, even if none our users are stores, that
14704 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14705 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14706 // climbing the DAG back to the root, and it doesn't seem to be worth the
14708 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14709 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14710 if (UI->getOpcode() != ISD::CopyToReg &&
14711 UI->getOpcode() != ISD::SETCC &&
14712 UI->getOpcode() != ISD::STORE)
14715 if (ConstantSDNode *C =
14716 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14717 // An add of one will be selected as an INC.
14718 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14719 Opcode = X86ISD::INC;
14724 // An add of negative one (subtract of one) will be selected as a DEC.
14725 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14726 Opcode = X86ISD::DEC;
14732 // Otherwise use a regular EFLAGS-setting add.
14733 Opcode = X86ISD::ADD;
14738 // If we have a constant logical shift that's only used in a comparison
14739 // against zero turn it into an equivalent AND. This allows turning it into
14740 // a TEST instruction later.
14741 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14742 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14743 EVT VT = Op.getValueType();
14744 unsigned BitWidth = VT.getSizeInBits();
14745 unsigned ShAmt = Op->getConstantOperandVal(1);
14746 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14748 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14749 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14750 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14751 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14753 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14754 DAG.getConstant(Mask, VT));
14755 DAG.ReplaceAllUsesWith(Op, New);
14761 // If the primary and result isn't used, don't bother using X86ISD::AND,
14762 // because a TEST instruction will be better.
14763 if (!hasNonFlagsUse(Op))
14769 // Due to the ISEL shortcoming noted above, be conservative if this op is
14770 // likely to be selected as part of a load-modify-store instruction.
14771 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14772 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14773 if (UI->getOpcode() == ISD::STORE)
14776 // Otherwise use a regular EFLAGS-setting instruction.
14777 switch (ArithOp.getOpcode()) {
14778 default: llvm_unreachable("unexpected operator!");
14779 case ISD::SUB: Opcode = X86ISD::SUB; break;
14780 case ISD::XOR: Opcode = X86ISD::XOR; break;
14781 case ISD::AND: Opcode = X86ISD::AND; break;
14783 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14784 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14785 if (EFLAGS.getNode())
14788 Opcode = X86ISD::OR;
14802 return SDValue(Op.getNode(), 1);
14808 // If we found that truncation is beneficial, perform the truncation and
14810 if (NeedTruncation) {
14811 EVT VT = Op.getValueType();
14812 SDValue WideVal = Op->getOperand(0);
14813 EVT WideVT = WideVal.getValueType();
14814 unsigned ConvertedOp = 0;
14815 // Use a target machine opcode to prevent further DAGCombine
14816 // optimizations that may separate the arithmetic operations
14817 // from the setcc node.
14818 switch (WideVal.getOpcode()) {
14820 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14821 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14822 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14823 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14824 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14828 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14829 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14830 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14831 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14832 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14838 // Emit a CMP with 0, which is the TEST pattern.
14839 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14840 DAG.getConstant(0, Op.getValueType()));
14842 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14843 SmallVector<SDValue, 4> Ops;
14844 for (unsigned i = 0; i != NumOperands; ++i)
14845 Ops.push_back(Op.getOperand(i));
14847 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14848 DAG.ReplaceAllUsesWith(Op, New);
14849 return SDValue(New.getNode(), 1);
14852 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14854 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14855 SDLoc dl, SelectionDAG &DAG) const {
14856 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14857 if (C->getAPIntValue() == 0)
14858 return EmitTest(Op0, X86CC, dl, DAG);
14860 if (Op0.getValueType() == MVT::i1)
14861 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14864 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14865 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14866 // Do the comparison at i32 if it's smaller, besides the Atom case.
14867 // This avoids subregister aliasing issues. Keep the smaller reference
14868 // if we're optimizing for size, however, as that'll allow better folding
14869 // of memory operations.
14870 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14871 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14872 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14873 !Subtarget->isAtom()) {
14874 unsigned ExtendOp =
14875 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14876 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14877 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14879 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14880 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14881 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14883 return SDValue(Sub.getNode(), 1);
14885 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14888 /// Convert a comparison if required by the subtarget.
14889 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14890 SelectionDAG &DAG) const {
14891 // If the subtarget does not support the FUCOMI instruction, floating-point
14892 // comparisons have to be converted.
14893 if (Subtarget->hasCMov() ||
14894 Cmp.getOpcode() != X86ISD::CMP ||
14895 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14896 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14899 // The instruction selector will select an FUCOM instruction instead of
14900 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14901 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14902 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14904 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14905 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14906 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14907 DAG.getConstant(8, MVT::i8));
14908 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14909 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14912 /// The minimum architected relative accuracy is 2^-12. We need one
14913 /// Newton-Raphson step to have a good float result (24 bits of precision).
14914 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14915 DAGCombinerInfo &DCI,
14916 unsigned &RefinementSteps,
14917 bool &UseOneConstNR) const {
14918 // FIXME: We should use instruction latency models to calculate the cost of
14919 // each potential sequence, but this is very hard to do reliably because
14920 // at least Intel's Core* chips have variable timing based on the number of
14921 // significant digits in the divisor and/or sqrt operand.
14922 if (!Subtarget->useSqrtEst())
14925 EVT VT = Op.getValueType();
14927 // SSE1 has rsqrtss and rsqrtps.
14928 // TODO: Add support for AVX512 (v16f32).
14929 // It is likely not profitable to do this for f64 because a double-precision
14930 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14931 // instructions: convert to single, rsqrtss, convert back to double, refine
14932 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14933 // along with FMA, this could be a throughput win.
14934 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14935 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14936 RefinementSteps = 1;
14937 UseOneConstNR = false;
14938 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14943 /// The minimum architected relative accuracy is 2^-12. We need one
14944 /// Newton-Raphson step to have a good float result (24 bits of precision).
14945 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14946 DAGCombinerInfo &DCI,
14947 unsigned &RefinementSteps) const {
14948 // FIXME: We should use instruction latency models to calculate the cost of
14949 // each potential sequence, but this is very hard to do reliably because
14950 // at least Intel's Core* chips have variable timing based on the number of
14951 // significant digits in the divisor.
14952 if (!Subtarget->useReciprocalEst())
14955 EVT VT = Op.getValueType();
14957 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14958 // TODO: Add support for AVX512 (v16f32).
14959 // It is likely not profitable to do this for f64 because a double-precision
14960 // reciprocal estimate with refinement on x86 prior to FMA requires
14961 // 15 instructions: convert to single, rcpss, convert back to double, refine
14962 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14963 // along with FMA, this could be a throughput win.
14964 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14965 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14966 RefinementSteps = ReciprocalEstimateRefinementSteps;
14967 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14972 static bool isAllOnes(SDValue V) {
14973 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14974 return C && C->isAllOnesValue();
14977 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14978 /// if it's possible.
14979 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14980 SDLoc dl, SelectionDAG &DAG) const {
14981 SDValue Op0 = And.getOperand(0);
14982 SDValue Op1 = And.getOperand(1);
14983 if (Op0.getOpcode() == ISD::TRUNCATE)
14984 Op0 = Op0.getOperand(0);
14985 if (Op1.getOpcode() == ISD::TRUNCATE)
14986 Op1 = Op1.getOperand(0);
14989 if (Op1.getOpcode() == ISD::SHL)
14990 std::swap(Op0, Op1);
14991 if (Op0.getOpcode() == ISD::SHL) {
14992 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14993 if (And00C->getZExtValue() == 1) {
14994 // If we looked past a truncate, check that it's only truncating away
14996 unsigned BitWidth = Op0.getValueSizeInBits();
14997 unsigned AndBitWidth = And.getValueSizeInBits();
14998 if (BitWidth > AndBitWidth) {
15000 DAG.computeKnownBits(Op0, Zeros, Ones);
15001 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15005 RHS = Op0.getOperand(1);
15007 } else if (Op1.getOpcode() == ISD::Constant) {
15008 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15009 uint64_t AndRHSVal = AndRHS->getZExtValue();
15010 SDValue AndLHS = Op0;
15012 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15013 LHS = AndLHS.getOperand(0);
15014 RHS = AndLHS.getOperand(1);
15017 // Use BT if the immediate can't be encoded in a TEST instruction.
15018 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15020 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15024 if (LHS.getNode()) {
15025 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15026 // instruction. Since the shift amount is in-range-or-undefined, we know
15027 // that doing a bittest on the i32 value is ok. We extend to i32 because
15028 // the encoding for the i16 version is larger than the i32 version.
15029 // Also promote i16 to i32 for performance / code size reason.
15030 if (LHS.getValueType() == MVT::i8 ||
15031 LHS.getValueType() == MVT::i16)
15032 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15034 // If the operand types disagree, extend the shift amount to match. Since
15035 // BT ignores high bits (like shifts) we can use anyextend.
15036 if (LHS.getValueType() != RHS.getValueType())
15037 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15039 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15040 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15041 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15042 DAG.getConstant(Cond, MVT::i8), BT);
15048 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15050 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15055 // SSE Condition code mapping:
15064 switch (SetCCOpcode) {
15065 default: llvm_unreachable("Unexpected SETCC condition");
15067 case ISD::SETEQ: SSECC = 0; break;
15069 case ISD::SETGT: Swap = true; // Fallthrough
15071 case ISD::SETOLT: SSECC = 1; break;
15073 case ISD::SETGE: Swap = true; // Fallthrough
15075 case ISD::SETOLE: SSECC = 2; break;
15076 case ISD::SETUO: SSECC = 3; break;
15078 case ISD::SETNE: SSECC = 4; break;
15079 case ISD::SETULE: Swap = true; // Fallthrough
15080 case ISD::SETUGE: SSECC = 5; break;
15081 case ISD::SETULT: Swap = true; // Fallthrough
15082 case ISD::SETUGT: SSECC = 6; break;
15083 case ISD::SETO: SSECC = 7; break;
15085 case ISD::SETONE: SSECC = 8; break;
15088 std::swap(Op0, Op1);
15093 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15094 // ones, and then concatenate the result back.
15095 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15096 MVT VT = Op.getSimpleValueType();
15098 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15099 "Unsupported value type for operation");
15101 unsigned NumElems = VT.getVectorNumElements();
15103 SDValue CC = Op.getOperand(2);
15105 // Extract the LHS vectors
15106 SDValue LHS = Op.getOperand(0);
15107 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15108 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15110 // Extract the RHS vectors
15111 SDValue RHS = Op.getOperand(1);
15112 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15113 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15115 // Issue the operation on the smaller types and concatenate the result back
15116 MVT EltVT = VT.getVectorElementType();
15117 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15118 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15119 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15120 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15123 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15124 const X86Subtarget *Subtarget) {
15125 SDValue Op0 = Op.getOperand(0);
15126 SDValue Op1 = Op.getOperand(1);
15127 SDValue CC = Op.getOperand(2);
15128 MVT VT = Op.getSimpleValueType();
15131 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15132 Op.getValueType().getScalarType() == MVT::i1 &&
15133 "Cannot set masked compare for this operation");
15135 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15137 bool Unsigned = false;
15140 switch (SetCCOpcode) {
15141 default: llvm_unreachable("Unexpected SETCC condition");
15142 case ISD::SETNE: SSECC = 4; break;
15143 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15144 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15145 case ISD::SETLT: Swap = true; //fall-through
15146 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15147 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15148 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15149 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15150 case ISD::SETULE: Unsigned = true; //fall-through
15151 case ISD::SETLE: SSECC = 2; break;
15155 std::swap(Op0, Op1);
15157 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15158 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15159 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15160 DAG.getConstant(SSECC, MVT::i8));
15163 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15164 /// operand \p Op1. If non-trivial (for example because it's not constant)
15165 /// return an empty value.
15166 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15168 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15172 MVT VT = Op1.getSimpleValueType();
15173 MVT EVT = VT.getVectorElementType();
15174 unsigned n = VT.getVectorNumElements();
15175 SmallVector<SDValue, 8> ULTOp1;
15177 for (unsigned i = 0; i < n; ++i) {
15178 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15179 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15182 // Avoid underflow.
15183 APInt Val = Elt->getAPIntValue();
15187 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15190 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15193 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15194 SelectionDAG &DAG) {
15195 SDValue Op0 = Op.getOperand(0);
15196 SDValue Op1 = Op.getOperand(1);
15197 SDValue CC = Op.getOperand(2);
15198 MVT VT = Op.getSimpleValueType();
15199 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15200 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15205 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15206 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15209 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15210 unsigned Opc = X86ISD::CMPP;
15211 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15212 assert(VT.getVectorNumElements() <= 16);
15213 Opc = X86ISD::CMPM;
15215 // In the two special cases we can't handle, emit two comparisons.
15218 unsigned CombineOpc;
15219 if (SetCCOpcode == ISD::SETUEQ) {
15220 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15222 assert(SetCCOpcode == ISD::SETONE);
15223 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15226 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15227 DAG.getConstant(CC0, MVT::i8));
15228 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15229 DAG.getConstant(CC1, MVT::i8));
15230 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15232 // Handle all other FP comparisons here.
15233 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15234 DAG.getConstant(SSECC, MVT::i8));
15237 // Break 256-bit integer vector compare into smaller ones.
15238 if (VT.is256BitVector() && !Subtarget->hasInt256())
15239 return Lower256IntVSETCC(Op, DAG);
15241 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15242 EVT OpVT = Op1.getValueType();
15243 if (Subtarget->hasAVX512()) {
15244 if (Op1.getValueType().is512BitVector() ||
15245 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15246 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15247 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15249 // In AVX-512 architecture setcc returns mask with i1 elements,
15250 // But there is no compare instruction for i8 and i16 elements in KNL.
15251 // We are not talking about 512-bit operands in this case, these
15252 // types are illegal.
15254 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15255 OpVT.getVectorElementType().getSizeInBits() >= 8))
15256 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15257 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15260 // We are handling one of the integer comparisons here. Since SSE only has
15261 // GT and EQ comparisons for integer, swapping operands and multiple
15262 // operations may be required for some comparisons.
15264 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15265 bool Subus = false;
15267 switch (SetCCOpcode) {
15268 default: llvm_unreachable("Unexpected SETCC condition");
15269 case ISD::SETNE: Invert = true;
15270 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15271 case ISD::SETLT: Swap = true;
15272 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15273 case ISD::SETGE: Swap = true;
15274 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15275 Invert = true; break;
15276 case ISD::SETULT: Swap = true;
15277 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15278 FlipSigns = true; break;
15279 case ISD::SETUGE: Swap = true;
15280 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15281 FlipSigns = true; Invert = true; break;
15284 // Special case: Use min/max operations for SETULE/SETUGE
15285 MVT VET = VT.getVectorElementType();
15287 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15288 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15291 switch (SetCCOpcode) {
15293 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15294 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15297 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15300 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15301 if (!MinMax && hasSubus) {
15302 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15304 // t = psubus Op0, Op1
15305 // pcmpeq t, <0..0>
15306 switch (SetCCOpcode) {
15308 case ISD::SETULT: {
15309 // If the comparison is against a constant we can turn this into a
15310 // setule. With psubus, setule does not require a swap. This is
15311 // beneficial because the constant in the register is no longer
15312 // destructed as the destination so it can be hoisted out of a loop.
15313 // Only do this pre-AVX since vpcmp* is no longer destructive.
15314 if (Subtarget->hasAVX())
15316 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15317 if (ULEOp1.getNode()) {
15319 Subus = true; Invert = false; Swap = false;
15323 // Psubus is better than flip-sign because it requires no inversion.
15324 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15325 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15329 Opc = X86ISD::SUBUS;
15335 std::swap(Op0, Op1);
15337 // Check that the operation in question is available (most are plain SSE2,
15338 // but PCMPGTQ and PCMPEQQ have different requirements).
15339 if (VT == MVT::v2i64) {
15340 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15341 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15343 // First cast everything to the right type.
15344 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15345 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15347 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15348 // bits of the inputs before performing those operations. The lower
15349 // compare is always unsigned.
15352 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15354 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15355 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15356 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15357 Sign, Zero, Sign, Zero);
15359 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15360 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15362 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15363 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15364 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15366 // Create masks for only the low parts/high parts of the 64 bit integers.
15367 static const int MaskHi[] = { 1, 1, 3, 3 };
15368 static const int MaskLo[] = { 0, 0, 2, 2 };
15369 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15370 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15371 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15373 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15374 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15377 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15379 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15382 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15383 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15384 // pcmpeqd + pshufd + pand.
15385 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15387 // First cast everything to the right type.
15388 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15389 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15392 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15394 // Make sure the lower and upper halves are both all-ones.
15395 static const int Mask[] = { 1, 0, 3, 2 };
15396 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15397 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15400 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15402 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15406 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15407 // bits of the inputs before performing those operations.
15409 EVT EltVT = VT.getVectorElementType();
15410 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15411 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15412 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15415 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15417 // If the logical-not of the result is required, perform that now.
15419 Result = DAG.getNOT(dl, Result, VT);
15422 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15425 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15426 getZeroVector(VT, Subtarget, DAG, dl));
15431 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15433 MVT VT = Op.getSimpleValueType();
15435 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15437 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15438 && "SetCC type must be 8-bit or 1-bit integer");
15439 SDValue Op0 = Op.getOperand(0);
15440 SDValue Op1 = Op.getOperand(1);
15442 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15444 // Optimize to BT if possible.
15445 // Lower (X & (1 << N)) == 0 to BT(X, N).
15446 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15447 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15448 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15449 Op1.getOpcode() == ISD::Constant &&
15450 cast<ConstantSDNode>(Op1)->isNullValue() &&
15451 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15452 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15453 if (NewSetCC.getNode())
15457 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15459 if (Op1.getOpcode() == ISD::Constant &&
15460 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15461 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15462 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15464 // If the input is a setcc, then reuse the input setcc or use a new one with
15465 // the inverted condition.
15466 if (Op0.getOpcode() == X86ISD::SETCC) {
15467 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15468 bool Invert = (CC == ISD::SETNE) ^
15469 cast<ConstantSDNode>(Op1)->isNullValue();
15473 CCode = X86::GetOppositeBranchCondition(CCode);
15474 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15475 DAG.getConstant(CCode, MVT::i8),
15476 Op0.getOperand(1));
15478 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15482 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15483 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15484 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15486 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15487 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15490 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15491 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15492 if (X86CC == X86::COND_INVALID)
15495 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15496 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15497 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15498 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15500 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15504 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15505 static bool isX86LogicalCmp(SDValue Op) {
15506 unsigned Opc = Op.getNode()->getOpcode();
15507 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15508 Opc == X86ISD::SAHF)
15510 if (Op.getResNo() == 1 &&
15511 (Opc == X86ISD::ADD ||
15512 Opc == X86ISD::SUB ||
15513 Opc == X86ISD::ADC ||
15514 Opc == X86ISD::SBB ||
15515 Opc == X86ISD::SMUL ||
15516 Opc == X86ISD::UMUL ||
15517 Opc == X86ISD::INC ||
15518 Opc == X86ISD::DEC ||
15519 Opc == X86ISD::OR ||
15520 Opc == X86ISD::XOR ||
15521 Opc == X86ISD::AND))
15524 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15530 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15531 if (V.getOpcode() != ISD::TRUNCATE)
15534 SDValue VOp0 = V.getOperand(0);
15535 unsigned InBits = VOp0.getValueSizeInBits();
15536 unsigned Bits = V.getValueSizeInBits();
15537 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15540 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15541 bool addTest = true;
15542 SDValue Cond = Op.getOperand(0);
15543 SDValue Op1 = Op.getOperand(1);
15544 SDValue Op2 = Op.getOperand(2);
15546 EVT VT = Op1.getValueType();
15549 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15550 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15551 // sequence later on.
15552 if (Cond.getOpcode() == ISD::SETCC &&
15553 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15554 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15555 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15556 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15557 int SSECC = translateX86FSETCC(
15558 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15561 if (Subtarget->hasAVX512()) {
15562 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15563 DAG.getConstant(SSECC, MVT::i8));
15564 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15566 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15567 DAG.getConstant(SSECC, MVT::i8));
15568 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15569 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15570 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15574 if (Cond.getOpcode() == ISD::SETCC) {
15575 SDValue NewCond = LowerSETCC(Cond, DAG);
15576 if (NewCond.getNode())
15580 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15581 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15582 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15583 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15584 if (Cond.getOpcode() == X86ISD::SETCC &&
15585 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15586 isZero(Cond.getOperand(1).getOperand(1))) {
15587 SDValue Cmp = Cond.getOperand(1);
15589 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15591 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15592 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15593 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15595 SDValue CmpOp0 = Cmp.getOperand(0);
15596 // Apply further optimizations for special cases
15597 // (select (x != 0), -1, 0) -> neg & sbb
15598 // (select (x == 0), 0, -1) -> neg & sbb
15599 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15600 if (YC->isNullValue() &&
15601 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15602 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15603 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15604 DAG.getConstant(0, CmpOp0.getValueType()),
15606 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15607 DAG.getConstant(X86::COND_B, MVT::i8),
15608 SDValue(Neg.getNode(), 1));
15612 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15613 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15614 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15616 SDValue Res = // Res = 0 or -1.
15617 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15618 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15620 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15621 Res = DAG.getNOT(DL, Res, Res.getValueType());
15623 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15624 if (!N2C || !N2C->isNullValue())
15625 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15630 // Look past (and (setcc_carry (cmp ...)), 1).
15631 if (Cond.getOpcode() == ISD::AND &&
15632 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15633 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15634 if (C && C->getAPIntValue() == 1)
15635 Cond = Cond.getOperand(0);
15638 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15639 // setting operand in place of the X86ISD::SETCC.
15640 unsigned CondOpcode = Cond.getOpcode();
15641 if (CondOpcode == X86ISD::SETCC ||
15642 CondOpcode == X86ISD::SETCC_CARRY) {
15643 CC = Cond.getOperand(0);
15645 SDValue Cmp = Cond.getOperand(1);
15646 unsigned Opc = Cmp.getOpcode();
15647 MVT VT = Op.getSimpleValueType();
15649 bool IllegalFPCMov = false;
15650 if (VT.isFloatingPoint() && !VT.isVector() &&
15651 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15652 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15654 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15655 Opc == X86ISD::BT) { // FIXME
15659 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15660 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15661 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15662 Cond.getOperand(0).getValueType() != MVT::i8)) {
15663 SDValue LHS = Cond.getOperand(0);
15664 SDValue RHS = Cond.getOperand(1);
15665 unsigned X86Opcode;
15668 switch (CondOpcode) {
15669 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15670 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15671 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15672 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15673 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15674 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15675 default: llvm_unreachable("unexpected overflowing operator");
15677 if (CondOpcode == ISD::UMULO)
15678 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15681 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15683 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15685 if (CondOpcode == ISD::UMULO)
15686 Cond = X86Op.getValue(2);
15688 Cond = X86Op.getValue(1);
15690 CC = DAG.getConstant(X86Cond, MVT::i8);
15695 // Look pass the truncate if the high bits are known zero.
15696 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15697 Cond = Cond.getOperand(0);
15699 // We know the result of AND is compared against zero. Try to match
15701 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15702 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15703 if (NewSetCC.getNode()) {
15704 CC = NewSetCC.getOperand(0);
15705 Cond = NewSetCC.getOperand(1);
15712 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15713 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15716 // a < b ? -1 : 0 -> RES = ~setcc_carry
15717 // a < b ? 0 : -1 -> RES = setcc_carry
15718 // a >= b ? -1 : 0 -> RES = setcc_carry
15719 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15720 if (Cond.getOpcode() == X86ISD::SUB) {
15721 Cond = ConvertCmpIfNecessary(Cond, DAG);
15722 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15724 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15725 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15726 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15727 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15728 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15729 return DAG.getNOT(DL, Res, Res.getValueType());
15734 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15735 // widen the cmov and push the truncate through. This avoids introducing a new
15736 // branch during isel and doesn't add any extensions.
15737 if (Op.getValueType() == MVT::i8 &&
15738 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15739 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15740 if (T1.getValueType() == T2.getValueType() &&
15741 // Blacklist CopyFromReg to avoid partial register stalls.
15742 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15743 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15744 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15745 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15749 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15750 // condition is true.
15751 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15752 SDValue Ops[] = { Op2, Op1, CC, Cond };
15753 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15756 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15757 SelectionDAG &DAG) {
15758 MVT VT = Op->getSimpleValueType(0);
15759 SDValue In = Op->getOperand(0);
15760 MVT InVT = In.getSimpleValueType();
15761 MVT VTElt = VT.getVectorElementType();
15762 MVT InVTElt = InVT.getVectorElementType();
15766 if ((InVTElt == MVT::i1) &&
15767 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15768 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15770 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15771 VTElt.getSizeInBits() <= 16)) ||
15773 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15774 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15776 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15777 VTElt.getSizeInBits() >= 32))))
15778 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15780 unsigned int NumElts = VT.getVectorNumElements();
15782 if (NumElts != 8 && NumElts != 16)
15785 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15786 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15787 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15788 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15791 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15792 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15794 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15795 Constant *C = ConstantInt::get(*DAG.getContext(),
15796 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15798 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15799 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15800 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15801 MachinePointerInfo::getConstantPool(),
15802 false, false, false, Alignment);
15803 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15804 if (VT.is512BitVector())
15806 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15809 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15810 SelectionDAG &DAG) {
15811 MVT VT = Op->getSimpleValueType(0);
15812 SDValue In = Op->getOperand(0);
15813 MVT InVT = In.getSimpleValueType();
15816 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15817 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15819 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15820 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15821 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15824 if (Subtarget->hasInt256())
15825 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15827 // Optimize vectors in AVX mode
15828 // Sign extend v8i16 to v8i32 and
15831 // Divide input vector into two parts
15832 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15833 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15834 // concat the vectors to original VT
15836 unsigned NumElems = InVT.getVectorNumElements();
15837 SDValue Undef = DAG.getUNDEF(InVT);
15839 SmallVector<int,8> ShufMask1(NumElems, -1);
15840 for (unsigned i = 0; i != NumElems/2; ++i)
15843 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15845 SmallVector<int,8> ShufMask2(NumElems, -1);
15846 for (unsigned i = 0; i != NumElems/2; ++i)
15847 ShufMask2[i] = i + NumElems/2;
15849 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15851 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15852 VT.getVectorNumElements()/2);
15854 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15855 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15857 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15860 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15861 // may emit an illegal shuffle but the expansion is still better than scalar
15862 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15863 // we'll emit a shuffle and a arithmetic shift.
15864 // TODO: It is possible to support ZExt by zeroing the undef values during
15865 // the shuffle phase or after the shuffle.
15866 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15867 SelectionDAG &DAG) {
15868 MVT RegVT = Op.getSimpleValueType();
15869 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15870 assert(RegVT.isInteger() &&
15871 "We only custom lower integer vector sext loads.");
15873 // Nothing useful we can do without SSE2 shuffles.
15874 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15876 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15878 EVT MemVT = Ld->getMemoryVT();
15879 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15880 unsigned RegSz = RegVT.getSizeInBits();
15882 ISD::LoadExtType Ext = Ld->getExtensionType();
15884 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15885 && "Only anyext and sext are currently implemented.");
15886 assert(MemVT != RegVT && "Cannot extend to the same type");
15887 assert(MemVT.isVector() && "Must load a vector from memory");
15889 unsigned NumElems = RegVT.getVectorNumElements();
15890 unsigned MemSz = MemVT.getSizeInBits();
15891 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15893 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15894 // The only way in which we have a legal 256-bit vector result but not the
15895 // integer 256-bit operations needed to directly lower a sextload is if we
15896 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15897 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15898 // correctly legalized. We do this late to allow the canonical form of
15899 // sextload to persist throughout the rest of the DAG combiner -- it wants
15900 // to fold together any extensions it can, and so will fuse a sign_extend
15901 // of an sextload into a sextload targeting a wider value.
15903 if (MemSz == 128) {
15904 // Just switch this to a normal load.
15905 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15906 "it must be a legal 128-bit vector "
15908 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15909 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15910 Ld->isInvariant(), Ld->getAlignment());
15912 assert(MemSz < 128 &&
15913 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15914 // Do an sext load to a 128-bit vector type. We want to use the same
15915 // number of elements, but elements half as wide. This will end up being
15916 // recursively lowered by this routine, but will succeed as we definitely
15917 // have all the necessary features if we're using AVX1.
15919 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15920 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15922 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15923 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15924 Ld->isNonTemporal(), Ld->isInvariant(),
15925 Ld->getAlignment());
15928 // Replace chain users with the new chain.
15929 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15930 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15932 // Finally, do a normal sign-extend to the desired register.
15933 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15936 // All sizes must be a power of two.
15937 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15938 "Non-power-of-two elements are not custom lowered!");
15940 // Attempt to load the original value using scalar loads.
15941 // Find the largest scalar type that divides the total loaded size.
15942 MVT SclrLoadTy = MVT::i8;
15943 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15944 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15945 MVT Tp = (MVT::SimpleValueType)tp;
15946 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15951 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15952 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15954 SclrLoadTy = MVT::f64;
15956 // Calculate the number of scalar loads that we need to perform
15957 // in order to load our vector from memory.
15958 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15960 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15961 "Can only lower sext loads with a single scalar load!");
15963 unsigned loadRegZize = RegSz;
15964 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15967 // Represent our vector as a sequence of elements which are the
15968 // largest scalar that we can load.
15969 EVT LoadUnitVecVT = EVT::getVectorVT(
15970 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15972 // Represent the data using the same element type that is stored in
15973 // memory. In practice, we ''widen'' MemVT.
15975 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15976 loadRegZize / MemVT.getScalarType().getSizeInBits());
15978 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15979 "Invalid vector type");
15981 // We can't shuffle using an illegal type.
15982 assert(TLI.isTypeLegal(WideVecVT) &&
15983 "We only lower types that form legal widened vector types");
15985 SmallVector<SDValue, 8> Chains;
15986 SDValue Ptr = Ld->getBasePtr();
15987 SDValue Increment =
15988 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15989 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15991 for (unsigned i = 0; i < NumLoads; ++i) {
15992 // Perform a single load.
15993 SDValue ScalarLoad =
15994 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15995 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15996 Ld->getAlignment());
15997 Chains.push_back(ScalarLoad.getValue(1));
15998 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15999 // another round of DAGCombining.
16001 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16003 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16004 ScalarLoad, DAG.getIntPtrConstant(i));
16006 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16009 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16011 // Bitcast the loaded value to a vector of the original element type, in
16012 // the size of the target vector type.
16013 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16014 unsigned SizeRatio = RegSz / MemSz;
16016 if (Ext == ISD::SEXTLOAD) {
16017 // If we have SSE4.1, we can directly emit a VSEXT node.
16018 if (Subtarget->hasSSE41()) {
16019 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16020 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16024 // Otherwise we'll shuffle the small elements in the high bits of the
16025 // larger type and perform an arithmetic shift. If the shift is not legal
16026 // it's better to scalarize.
16027 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16028 "We can't implement a sext load without an arithmetic right shift!");
16030 // Redistribute the loaded elements into the different locations.
16031 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16032 for (unsigned i = 0; i != NumElems; ++i)
16033 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16035 SDValue Shuff = DAG.getVectorShuffle(
16036 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16038 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16040 // Build the arithmetic shift.
16041 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16042 MemVT.getVectorElementType().getSizeInBits();
16044 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16046 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16050 // Redistribute the loaded elements into the different locations.
16051 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16052 for (unsigned i = 0; i != NumElems; ++i)
16053 ShuffleVec[i * SizeRatio] = i;
16055 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16056 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16058 // Bitcast to the requested type.
16059 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16060 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16064 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16065 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16066 // from the AND / OR.
16067 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16068 Opc = Op.getOpcode();
16069 if (Opc != ISD::OR && Opc != ISD::AND)
16071 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16072 Op.getOperand(0).hasOneUse() &&
16073 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16074 Op.getOperand(1).hasOneUse());
16077 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16078 // 1 and that the SETCC node has a single use.
16079 static bool isXor1OfSetCC(SDValue Op) {
16080 if (Op.getOpcode() != ISD::XOR)
16082 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16083 if (N1C && N1C->getAPIntValue() == 1) {
16084 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16085 Op.getOperand(0).hasOneUse();
16090 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16091 bool addTest = true;
16092 SDValue Chain = Op.getOperand(0);
16093 SDValue Cond = Op.getOperand(1);
16094 SDValue Dest = Op.getOperand(2);
16097 bool Inverted = false;
16099 if (Cond.getOpcode() == ISD::SETCC) {
16100 // Check for setcc([su]{add,sub,mul}o == 0).
16101 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16102 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16103 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16104 Cond.getOperand(0).getResNo() == 1 &&
16105 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16106 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16107 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16108 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16109 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16110 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16112 Cond = Cond.getOperand(0);
16114 SDValue NewCond = LowerSETCC(Cond, DAG);
16115 if (NewCond.getNode())
16120 // FIXME: LowerXALUO doesn't handle these!!
16121 else if (Cond.getOpcode() == X86ISD::ADD ||
16122 Cond.getOpcode() == X86ISD::SUB ||
16123 Cond.getOpcode() == X86ISD::SMUL ||
16124 Cond.getOpcode() == X86ISD::UMUL)
16125 Cond = LowerXALUO(Cond, DAG);
16128 // Look pass (and (setcc_carry (cmp ...)), 1).
16129 if (Cond.getOpcode() == ISD::AND &&
16130 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16131 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16132 if (C && C->getAPIntValue() == 1)
16133 Cond = Cond.getOperand(0);
16136 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16137 // setting operand in place of the X86ISD::SETCC.
16138 unsigned CondOpcode = Cond.getOpcode();
16139 if (CondOpcode == X86ISD::SETCC ||
16140 CondOpcode == X86ISD::SETCC_CARRY) {
16141 CC = Cond.getOperand(0);
16143 SDValue Cmp = Cond.getOperand(1);
16144 unsigned Opc = Cmp.getOpcode();
16145 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16146 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16150 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16154 // These can only come from an arithmetic instruction with overflow,
16155 // e.g. SADDO, UADDO.
16156 Cond = Cond.getNode()->getOperand(1);
16162 CondOpcode = Cond.getOpcode();
16163 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16164 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16165 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16166 Cond.getOperand(0).getValueType() != MVT::i8)) {
16167 SDValue LHS = Cond.getOperand(0);
16168 SDValue RHS = Cond.getOperand(1);
16169 unsigned X86Opcode;
16172 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16173 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16175 switch (CondOpcode) {
16176 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16178 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16180 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16183 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16184 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16186 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16188 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16191 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16192 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16193 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16194 default: llvm_unreachable("unexpected overflowing operator");
16197 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16198 if (CondOpcode == ISD::UMULO)
16199 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16202 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16204 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16206 if (CondOpcode == ISD::UMULO)
16207 Cond = X86Op.getValue(2);
16209 Cond = X86Op.getValue(1);
16211 CC = DAG.getConstant(X86Cond, MVT::i8);
16215 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16216 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16217 if (CondOpc == ISD::OR) {
16218 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16219 // two branches instead of an explicit OR instruction with a
16221 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16222 isX86LogicalCmp(Cmp)) {
16223 CC = Cond.getOperand(0).getOperand(0);
16224 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16225 Chain, Dest, CC, Cmp);
16226 CC = Cond.getOperand(1).getOperand(0);
16230 } else { // ISD::AND
16231 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16232 // two branches instead of an explicit AND instruction with a
16233 // separate test. However, we only do this if this block doesn't
16234 // have a fall-through edge, because this requires an explicit
16235 // jmp when the condition is false.
16236 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16237 isX86LogicalCmp(Cmp) &&
16238 Op.getNode()->hasOneUse()) {
16239 X86::CondCode CCode =
16240 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16241 CCode = X86::GetOppositeBranchCondition(CCode);
16242 CC = DAG.getConstant(CCode, MVT::i8);
16243 SDNode *User = *Op.getNode()->use_begin();
16244 // Look for an unconditional branch following this conditional branch.
16245 // We need this because we need to reverse the successors in order
16246 // to implement FCMP_OEQ.
16247 if (User->getOpcode() == ISD::BR) {
16248 SDValue FalseBB = User->getOperand(1);
16250 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16251 assert(NewBR == User);
16255 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16256 Chain, Dest, CC, Cmp);
16257 X86::CondCode CCode =
16258 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16259 CCode = X86::GetOppositeBranchCondition(CCode);
16260 CC = DAG.getConstant(CCode, MVT::i8);
16266 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16267 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16268 // It should be transformed during dag combiner except when the condition
16269 // is set by a arithmetics with overflow node.
16270 X86::CondCode CCode =
16271 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16272 CCode = X86::GetOppositeBranchCondition(CCode);
16273 CC = DAG.getConstant(CCode, MVT::i8);
16274 Cond = Cond.getOperand(0).getOperand(1);
16276 } else if (Cond.getOpcode() == ISD::SETCC &&
16277 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16278 // For FCMP_OEQ, we can emit
16279 // two branches instead of an explicit AND instruction with a
16280 // separate test. However, we only do this if this block doesn't
16281 // have a fall-through edge, because this requires an explicit
16282 // jmp when the condition is false.
16283 if (Op.getNode()->hasOneUse()) {
16284 SDNode *User = *Op.getNode()->use_begin();
16285 // Look for an unconditional branch following this conditional branch.
16286 // We need this because we need to reverse the successors in order
16287 // to implement FCMP_OEQ.
16288 if (User->getOpcode() == ISD::BR) {
16289 SDValue FalseBB = User->getOperand(1);
16291 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16292 assert(NewBR == User);
16296 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16297 Cond.getOperand(0), Cond.getOperand(1));
16298 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16299 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16300 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16301 Chain, Dest, CC, Cmp);
16302 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16307 } else if (Cond.getOpcode() == ISD::SETCC &&
16308 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16309 // For FCMP_UNE, we can emit
16310 // two branches instead of an explicit AND instruction with a
16311 // separate test. However, we only do this if this block doesn't
16312 // have a fall-through edge, because this requires an explicit
16313 // jmp when the condition is false.
16314 if (Op.getNode()->hasOneUse()) {
16315 SDNode *User = *Op.getNode()->use_begin();
16316 // Look for an unconditional branch following this conditional branch.
16317 // We need this because we need to reverse the successors in order
16318 // to implement FCMP_UNE.
16319 if (User->getOpcode() == ISD::BR) {
16320 SDValue FalseBB = User->getOperand(1);
16322 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16323 assert(NewBR == User);
16326 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16327 Cond.getOperand(0), Cond.getOperand(1));
16328 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16329 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16330 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16331 Chain, Dest, CC, Cmp);
16332 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16342 // Look pass the truncate if the high bits are known zero.
16343 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16344 Cond = Cond.getOperand(0);
16346 // We know the result of AND is compared against zero. Try to match
16348 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16349 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16350 if (NewSetCC.getNode()) {
16351 CC = NewSetCC.getOperand(0);
16352 Cond = NewSetCC.getOperand(1);
16359 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16360 CC = DAG.getConstant(X86Cond, MVT::i8);
16361 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16363 Cond = ConvertCmpIfNecessary(Cond, DAG);
16364 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16365 Chain, Dest, CC, Cond);
16368 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16369 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16370 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16371 // that the guard pages used by the OS virtual memory manager are allocated in
16372 // correct sequence.
16374 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16375 SelectionDAG &DAG) const {
16376 MachineFunction &MF = DAG.getMachineFunction();
16377 bool SplitStack = MF.shouldSplitStack();
16378 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
16383 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16384 SDNode* Node = Op.getNode();
16386 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16387 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16388 " not tell us which reg is the stack pointer!");
16389 EVT VT = Node->getValueType(0);
16390 SDValue Tmp1 = SDValue(Node, 0);
16391 SDValue Tmp2 = SDValue(Node, 1);
16392 SDValue Tmp3 = Node->getOperand(2);
16393 SDValue Chain = Tmp1.getOperand(0);
16395 // Chain the dynamic stack allocation so that it doesn't modify the stack
16396 // pointer when other instructions are using the stack.
16397 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16400 SDValue Size = Tmp2.getOperand(1);
16401 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16402 Chain = SP.getValue(1);
16403 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16404 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16405 unsigned StackAlign = TFI.getStackAlignment();
16406 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16407 if (Align > StackAlign)
16408 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16409 DAG.getConstant(-(uint64_t)Align, VT));
16410 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16412 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16413 DAG.getIntPtrConstant(0, true), SDValue(),
16416 SDValue Ops[2] = { Tmp1, Tmp2 };
16417 return DAG.getMergeValues(Ops, dl);
16421 SDValue Chain = Op.getOperand(0);
16422 SDValue Size = Op.getOperand(1);
16423 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16424 EVT VT = Op.getNode()->getValueType(0);
16426 bool Is64Bit = Subtarget->is64Bit();
16427 EVT SPTy = getPointerTy();
16430 MachineRegisterInfo &MRI = MF.getRegInfo();
16433 // The 64 bit implementation of segmented stacks needs to clobber both r10
16434 // r11. This makes it impossible to use it along with nested parameters.
16435 const Function *F = MF.getFunction();
16437 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16439 if (I->hasNestAttr())
16440 report_fatal_error("Cannot use segmented stacks with functions that "
16441 "have nested arguments.");
16444 const TargetRegisterClass *AddrRegClass =
16445 getRegClassFor(getPointerTy());
16446 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16447 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16448 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16449 DAG.getRegister(Vreg, SPTy));
16450 SDValue Ops1[2] = { Value, Chain };
16451 return DAG.getMergeValues(Ops1, dl);
16454 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16456 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16457 Flag = Chain.getValue(1);
16458 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16460 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16462 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16463 DAG.getSubtarget().getRegisterInfo());
16464 unsigned SPReg = RegInfo->getStackRegister();
16465 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16466 Chain = SP.getValue(1);
16469 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16470 DAG.getConstant(-(uint64_t)Align, VT));
16471 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16474 SDValue Ops1[2] = { SP, Chain };
16475 return DAG.getMergeValues(Ops1, dl);
16479 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16480 MachineFunction &MF = DAG.getMachineFunction();
16481 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16483 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16486 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16487 // vastart just stores the address of the VarArgsFrameIndex slot into the
16488 // memory location argument.
16489 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16491 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16492 MachinePointerInfo(SV), false, false, 0);
16496 // gp_offset (0 - 6 * 8)
16497 // fp_offset (48 - 48 + 8 * 16)
16498 // overflow_arg_area (point to parameters coming in memory).
16500 SmallVector<SDValue, 8> MemOps;
16501 SDValue FIN = Op.getOperand(1);
16503 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16504 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16506 FIN, MachinePointerInfo(SV), false, false, 0);
16507 MemOps.push_back(Store);
16510 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16511 FIN, DAG.getIntPtrConstant(4));
16512 Store = DAG.getStore(Op.getOperand(0), DL,
16513 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16515 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16516 MemOps.push_back(Store);
16518 // Store ptr to overflow_arg_area
16519 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16520 FIN, DAG.getIntPtrConstant(4));
16521 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16523 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16524 MachinePointerInfo(SV, 8),
16526 MemOps.push_back(Store);
16528 // Store ptr to reg_save_area.
16529 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16530 FIN, DAG.getIntPtrConstant(8));
16531 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16533 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16534 MachinePointerInfo(SV, 16), false, false, 0);
16535 MemOps.push_back(Store);
16536 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16539 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16540 assert(Subtarget->is64Bit() &&
16541 "LowerVAARG only handles 64-bit va_arg!");
16542 assert((Subtarget->isTargetLinux() ||
16543 Subtarget->isTargetDarwin()) &&
16544 "Unhandled target in LowerVAARG");
16545 assert(Op.getNode()->getNumOperands() == 4);
16546 SDValue Chain = Op.getOperand(0);
16547 SDValue SrcPtr = Op.getOperand(1);
16548 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16549 unsigned Align = Op.getConstantOperandVal(3);
16552 EVT ArgVT = Op.getNode()->getValueType(0);
16553 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16554 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16557 // Decide which area this value should be read from.
16558 // TODO: Implement the AMD64 ABI in its entirety. This simple
16559 // selection mechanism works only for the basic types.
16560 if (ArgVT == MVT::f80) {
16561 llvm_unreachable("va_arg for f80 not yet implemented");
16562 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16563 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16564 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16565 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16567 llvm_unreachable("Unhandled argument type in LowerVAARG");
16570 if (ArgMode == 2) {
16571 // Sanity Check: Make sure using fp_offset makes sense.
16572 assert(!DAG.getTarget().Options.UseSoftFloat &&
16573 !(DAG.getMachineFunction()
16574 .getFunction()->getAttributes()
16575 .hasAttribute(AttributeSet::FunctionIndex,
16576 Attribute::NoImplicitFloat)) &&
16577 Subtarget->hasSSE1());
16580 // Insert VAARG_64 node into the DAG
16581 // VAARG_64 returns two values: Variable Argument Address, Chain
16582 SmallVector<SDValue, 11> InstOps;
16583 InstOps.push_back(Chain);
16584 InstOps.push_back(SrcPtr);
16585 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16586 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16587 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16588 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16589 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16590 VTs, InstOps, MVT::i64,
16591 MachinePointerInfo(SV),
16593 /*Volatile=*/false,
16595 /*WriteMem=*/true);
16596 Chain = VAARG.getValue(1);
16598 // Load the next argument and return it
16599 return DAG.getLoad(ArgVT, dl,
16602 MachinePointerInfo(),
16603 false, false, false, 0);
16606 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16607 SelectionDAG &DAG) {
16608 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16609 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16610 SDValue Chain = Op.getOperand(0);
16611 SDValue DstPtr = Op.getOperand(1);
16612 SDValue SrcPtr = Op.getOperand(2);
16613 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16614 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16617 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16618 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16620 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16623 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16624 // amount is a constant. Takes immediate version of shift as input.
16625 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16626 SDValue SrcOp, uint64_t ShiftAmt,
16627 SelectionDAG &DAG) {
16628 MVT ElementType = VT.getVectorElementType();
16630 // Fold this packed shift into its first operand if ShiftAmt is 0.
16634 // Check for ShiftAmt >= element width
16635 if (ShiftAmt >= ElementType.getSizeInBits()) {
16636 if (Opc == X86ISD::VSRAI)
16637 ShiftAmt = ElementType.getSizeInBits() - 1;
16639 return DAG.getConstant(0, VT);
16642 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16643 && "Unknown target vector shift-by-constant node");
16645 // Fold this packed vector shift into a build vector if SrcOp is a
16646 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16647 if (VT == SrcOp.getSimpleValueType() &&
16648 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16649 SmallVector<SDValue, 8> Elts;
16650 unsigned NumElts = SrcOp->getNumOperands();
16651 ConstantSDNode *ND;
16654 default: llvm_unreachable(nullptr);
16655 case X86ISD::VSHLI:
16656 for (unsigned i=0; i!=NumElts; ++i) {
16657 SDValue CurrentOp = SrcOp->getOperand(i);
16658 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16659 Elts.push_back(CurrentOp);
16662 ND = cast<ConstantSDNode>(CurrentOp);
16663 const APInt &C = ND->getAPIntValue();
16664 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16667 case X86ISD::VSRLI:
16668 for (unsigned i=0; i!=NumElts; ++i) {
16669 SDValue CurrentOp = SrcOp->getOperand(i);
16670 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16671 Elts.push_back(CurrentOp);
16674 ND = cast<ConstantSDNode>(CurrentOp);
16675 const APInt &C = ND->getAPIntValue();
16676 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16679 case X86ISD::VSRAI:
16680 for (unsigned i=0; i!=NumElts; ++i) {
16681 SDValue CurrentOp = SrcOp->getOperand(i);
16682 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16683 Elts.push_back(CurrentOp);
16686 ND = cast<ConstantSDNode>(CurrentOp);
16687 const APInt &C = ND->getAPIntValue();
16688 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16693 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16696 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16699 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16700 // may or may not be a constant. Takes immediate version of shift as input.
16701 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16702 SDValue SrcOp, SDValue ShAmt,
16703 SelectionDAG &DAG) {
16704 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16706 // Catch shift-by-constant.
16707 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16708 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16709 CShAmt->getZExtValue(), DAG);
16711 // Change opcode to non-immediate version
16713 default: llvm_unreachable("Unknown target vector shift node");
16714 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16715 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16716 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16719 // Need to build a vector containing shift amount
16720 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16723 ShOps[1] = DAG.getConstant(0, MVT::i32);
16724 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16725 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16727 // The return type has to be a 128-bit type with the same element
16728 // type as the input type.
16729 MVT EltVT = VT.getVectorElementType();
16730 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16732 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16733 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16736 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16737 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16738 /// necessary casting for \p Mask when lowering masking intrinsics.
16739 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16740 SDValue PreservedSrc,
16741 const X86Subtarget *Subtarget,
16742 SelectionDAG &DAG) {
16743 EVT VT = Op.getValueType();
16744 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16745 MVT::i1, VT.getVectorNumElements());
16746 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16747 Mask.getValueType().getSizeInBits());
16750 assert(MaskVT.isSimple() && "invalid mask type");
16752 if (isAllOnes(Mask))
16755 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16756 // are extracted by EXTRACT_SUBVECTOR.
16757 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16758 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16759 DAG.getIntPtrConstant(0));
16761 switch (Op.getOpcode()) {
16763 case X86ISD::PCMPEQM:
16764 case X86ISD::PCMPGTM:
16766 case X86ISD::CMPMU:
16767 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16769 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16770 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16771 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16774 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16776 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16777 case Intrinsic::x86_fma_vfmadd_ps:
16778 case Intrinsic::x86_fma_vfmadd_pd:
16779 case Intrinsic::x86_fma_vfmadd_ps_256:
16780 case Intrinsic::x86_fma_vfmadd_pd_256:
16781 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16782 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16783 return X86ISD::FMADD;
16784 case Intrinsic::x86_fma_vfmsub_ps:
16785 case Intrinsic::x86_fma_vfmsub_pd:
16786 case Intrinsic::x86_fma_vfmsub_ps_256:
16787 case Intrinsic::x86_fma_vfmsub_pd_256:
16788 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16789 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16790 return X86ISD::FMSUB;
16791 case Intrinsic::x86_fma_vfnmadd_ps:
16792 case Intrinsic::x86_fma_vfnmadd_pd:
16793 case Intrinsic::x86_fma_vfnmadd_ps_256:
16794 case Intrinsic::x86_fma_vfnmadd_pd_256:
16795 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16796 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16797 return X86ISD::FNMADD;
16798 case Intrinsic::x86_fma_vfnmsub_ps:
16799 case Intrinsic::x86_fma_vfnmsub_pd:
16800 case Intrinsic::x86_fma_vfnmsub_ps_256:
16801 case Intrinsic::x86_fma_vfnmsub_pd_256:
16802 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16803 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16804 return X86ISD::FNMSUB;
16805 case Intrinsic::x86_fma_vfmaddsub_ps:
16806 case Intrinsic::x86_fma_vfmaddsub_pd:
16807 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16808 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16809 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16810 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16811 return X86ISD::FMADDSUB;
16812 case Intrinsic::x86_fma_vfmsubadd_ps:
16813 case Intrinsic::x86_fma_vfmsubadd_pd:
16814 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16815 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16816 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16817 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16818 return X86ISD::FMSUBADD;
16822 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16823 SelectionDAG &DAG) {
16825 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16826 EVT VT = Op.getValueType();
16827 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16829 switch(IntrData->Type) {
16830 case INTR_TYPE_1OP:
16831 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16832 case INTR_TYPE_2OP:
16833 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16835 case INTR_TYPE_3OP:
16836 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16837 Op.getOperand(2), Op.getOperand(3));
16838 case INTR_TYPE_1OP_MASK_RM: {
16839 SDValue Src = Op.getOperand(1);
16840 SDValue Src0 = Op.getOperand(2);
16841 SDValue Mask = Op.getOperand(3);
16842 SDValue RoundingMode = Op.getOperand(4);
16843 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16845 Mask, Src0, Subtarget, DAG);
16849 case CMP_MASK_CC: {
16850 // Comparison intrinsics with masks.
16851 // Example of transformation:
16852 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16853 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16855 // (v8i1 (insert_subvector undef,
16856 // (v2i1 (and (PCMPEQM %a, %b),
16857 // (extract_subvector
16858 // (v8i1 (bitcast %mask)), 0))), 0))))
16859 EVT VT = Op.getOperand(1).getValueType();
16860 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16861 VT.getVectorNumElements());
16862 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16863 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16864 Mask.getValueType().getSizeInBits());
16866 if (IntrData->Type == CMP_MASK_CC) {
16867 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16868 Op.getOperand(2), Op.getOperand(3));
16870 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16871 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16874 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16875 DAG.getTargetConstant(0, MaskVT),
16877 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16878 DAG.getUNDEF(BitcastVT), CmpMask,
16879 DAG.getIntPtrConstant(0));
16880 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16882 case COMI: { // Comparison intrinsics
16883 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16884 SDValue LHS = Op.getOperand(1);
16885 SDValue RHS = Op.getOperand(2);
16886 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16887 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16888 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16889 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16890 DAG.getConstant(X86CC, MVT::i8), Cond);
16891 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16894 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16895 Op.getOperand(1), Op.getOperand(2), DAG);
16897 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16898 Op.getOperand(1), Op.getOperand(2), DAG),
16899 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);;
16906 default: return SDValue(); // Don't custom lower most intrinsics.
16908 // Arithmetic intrinsics.
16909 case Intrinsic::x86_sse2_pmulu_dq:
16910 case Intrinsic::x86_avx2_pmulu_dq:
16911 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16912 Op.getOperand(1), Op.getOperand(2));
16914 case Intrinsic::x86_sse41_pmuldq:
16915 case Intrinsic::x86_avx2_pmul_dq:
16916 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16917 Op.getOperand(1), Op.getOperand(2));
16919 case Intrinsic::x86_sse2_pmulhu_w:
16920 case Intrinsic::x86_avx2_pmulhu_w:
16921 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16922 Op.getOperand(1), Op.getOperand(2));
16924 case Intrinsic::x86_sse2_pmulh_w:
16925 case Intrinsic::x86_avx2_pmulh_w:
16926 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16927 Op.getOperand(1), Op.getOperand(2));
16929 // SSE/SSE2/AVX floating point max/min intrinsics.
16930 case Intrinsic::x86_sse_max_ps:
16931 case Intrinsic::x86_sse2_max_pd:
16932 case Intrinsic::x86_avx_max_ps_256:
16933 case Intrinsic::x86_avx_max_pd_256:
16934 case Intrinsic::x86_sse_min_ps:
16935 case Intrinsic::x86_sse2_min_pd:
16936 case Intrinsic::x86_avx_min_ps_256:
16937 case Intrinsic::x86_avx_min_pd_256: {
16940 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16941 case Intrinsic::x86_sse_max_ps:
16942 case Intrinsic::x86_sse2_max_pd:
16943 case Intrinsic::x86_avx_max_ps_256:
16944 case Intrinsic::x86_avx_max_pd_256:
16945 Opcode = X86ISD::FMAX;
16947 case Intrinsic::x86_sse_min_ps:
16948 case Intrinsic::x86_sse2_min_pd:
16949 case Intrinsic::x86_avx_min_ps_256:
16950 case Intrinsic::x86_avx_min_pd_256:
16951 Opcode = X86ISD::FMIN;
16954 return DAG.getNode(Opcode, dl, Op.getValueType(),
16955 Op.getOperand(1), Op.getOperand(2));
16958 // AVX2 variable shift intrinsics
16959 case Intrinsic::x86_avx2_psllv_d:
16960 case Intrinsic::x86_avx2_psllv_q:
16961 case Intrinsic::x86_avx2_psllv_d_256:
16962 case Intrinsic::x86_avx2_psllv_q_256:
16963 case Intrinsic::x86_avx2_psrlv_d:
16964 case Intrinsic::x86_avx2_psrlv_q:
16965 case Intrinsic::x86_avx2_psrlv_d_256:
16966 case Intrinsic::x86_avx2_psrlv_q_256:
16967 case Intrinsic::x86_avx2_psrav_d:
16968 case Intrinsic::x86_avx2_psrav_d_256: {
16971 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16972 case Intrinsic::x86_avx2_psllv_d:
16973 case Intrinsic::x86_avx2_psllv_q:
16974 case Intrinsic::x86_avx2_psllv_d_256:
16975 case Intrinsic::x86_avx2_psllv_q_256:
16978 case Intrinsic::x86_avx2_psrlv_d:
16979 case Intrinsic::x86_avx2_psrlv_q:
16980 case Intrinsic::x86_avx2_psrlv_d_256:
16981 case Intrinsic::x86_avx2_psrlv_q_256:
16984 case Intrinsic::x86_avx2_psrav_d:
16985 case Intrinsic::x86_avx2_psrav_d_256:
16989 return DAG.getNode(Opcode, dl, Op.getValueType(),
16990 Op.getOperand(1), Op.getOperand(2));
16993 case Intrinsic::x86_sse2_packssdw_128:
16994 case Intrinsic::x86_sse2_packsswb_128:
16995 case Intrinsic::x86_avx2_packssdw:
16996 case Intrinsic::x86_avx2_packsswb:
16997 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16998 Op.getOperand(1), Op.getOperand(2));
17000 case Intrinsic::x86_sse2_packuswb_128:
17001 case Intrinsic::x86_sse41_packusdw:
17002 case Intrinsic::x86_avx2_packuswb:
17003 case Intrinsic::x86_avx2_packusdw:
17004 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
17005 Op.getOperand(1), Op.getOperand(2));
17007 case Intrinsic::x86_ssse3_pshuf_b_128:
17008 case Intrinsic::x86_avx2_pshuf_b:
17009 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
17010 Op.getOperand(1), Op.getOperand(2));
17012 case Intrinsic::x86_sse2_pshuf_d:
17013 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
17014 Op.getOperand(1), Op.getOperand(2));
17016 case Intrinsic::x86_sse2_pshufl_w:
17017 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
17018 Op.getOperand(1), Op.getOperand(2));
17020 case Intrinsic::x86_sse2_pshufh_w:
17021 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
17022 Op.getOperand(1), Op.getOperand(2));
17024 case Intrinsic::x86_ssse3_psign_b_128:
17025 case Intrinsic::x86_ssse3_psign_w_128:
17026 case Intrinsic::x86_ssse3_psign_d_128:
17027 case Intrinsic::x86_avx2_psign_b:
17028 case Intrinsic::x86_avx2_psign_w:
17029 case Intrinsic::x86_avx2_psign_d:
17030 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
17031 Op.getOperand(1), Op.getOperand(2));
17033 case Intrinsic::x86_avx2_permd:
17034 case Intrinsic::x86_avx2_permps:
17035 // Operands intentionally swapped. Mask is last operand to intrinsic,
17036 // but second operand for node/instruction.
17037 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
17038 Op.getOperand(2), Op.getOperand(1));
17040 case Intrinsic::x86_avx512_mask_valign_q_512:
17041 case Intrinsic::x86_avx512_mask_valign_d_512:
17042 // Vector source operands are swapped.
17043 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17044 Op.getValueType(), Op.getOperand(2),
17047 Op.getOperand(5), Op.getOperand(4),
17050 // ptest and testp intrinsics. The intrinsic these come from are designed to
17051 // return an integer value, not just an instruction so lower it to the ptest
17052 // or testp pattern and a setcc for the result.
17053 case Intrinsic::x86_sse41_ptestz:
17054 case Intrinsic::x86_sse41_ptestc:
17055 case Intrinsic::x86_sse41_ptestnzc:
17056 case Intrinsic::x86_avx_ptestz_256:
17057 case Intrinsic::x86_avx_ptestc_256:
17058 case Intrinsic::x86_avx_ptestnzc_256:
17059 case Intrinsic::x86_avx_vtestz_ps:
17060 case Intrinsic::x86_avx_vtestc_ps:
17061 case Intrinsic::x86_avx_vtestnzc_ps:
17062 case Intrinsic::x86_avx_vtestz_pd:
17063 case Intrinsic::x86_avx_vtestc_pd:
17064 case Intrinsic::x86_avx_vtestnzc_pd:
17065 case Intrinsic::x86_avx_vtestz_ps_256:
17066 case Intrinsic::x86_avx_vtestc_ps_256:
17067 case Intrinsic::x86_avx_vtestnzc_ps_256:
17068 case Intrinsic::x86_avx_vtestz_pd_256:
17069 case Intrinsic::x86_avx_vtestc_pd_256:
17070 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17071 bool IsTestPacked = false;
17074 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17075 case Intrinsic::x86_avx_vtestz_ps:
17076 case Intrinsic::x86_avx_vtestz_pd:
17077 case Intrinsic::x86_avx_vtestz_ps_256:
17078 case Intrinsic::x86_avx_vtestz_pd_256:
17079 IsTestPacked = true; // Fallthrough
17080 case Intrinsic::x86_sse41_ptestz:
17081 case Intrinsic::x86_avx_ptestz_256:
17083 X86CC = X86::COND_E;
17085 case Intrinsic::x86_avx_vtestc_ps:
17086 case Intrinsic::x86_avx_vtestc_pd:
17087 case Intrinsic::x86_avx_vtestc_ps_256:
17088 case Intrinsic::x86_avx_vtestc_pd_256:
17089 IsTestPacked = true; // Fallthrough
17090 case Intrinsic::x86_sse41_ptestc:
17091 case Intrinsic::x86_avx_ptestc_256:
17093 X86CC = X86::COND_B;
17095 case Intrinsic::x86_avx_vtestnzc_ps:
17096 case Intrinsic::x86_avx_vtestnzc_pd:
17097 case Intrinsic::x86_avx_vtestnzc_ps_256:
17098 case Intrinsic::x86_avx_vtestnzc_pd_256:
17099 IsTestPacked = true; // Fallthrough
17100 case Intrinsic::x86_sse41_ptestnzc:
17101 case Intrinsic::x86_avx_ptestnzc_256:
17103 X86CC = X86::COND_A;
17107 SDValue LHS = Op.getOperand(1);
17108 SDValue RHS = Op.getOperand(2);
17109 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17110 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17111 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17112 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17113 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17115 case Intrinsic::x86_avx512_kortestz_w:
17116 case Intrinsic::x86_avx512_kortestc_w: {
17117 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17118 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17119 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17120 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17121 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17122 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17123 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17126 case Intrinsic::x86_sse42_pcmpistria128:
17127 case Intrinsic::x86_sse42_pcmpestria128:
17128 case Intrinsic::x86_sse42_pcmpistric128:
17129 case Intrinsic::x86_sse42_pcmpestric128:
17130 case Intrinsic::x86_sse42_pcmpistrio128:
17131 case Intrinsic::x86_sse42_pcmpestrio128:
17132 case Intrinsic::x86_sse42_pcmpistris128:
17133 case Intrinsic::x86_sse42_pcmpestris128:
17134 case Intrinsic::x86_sse42_pcmpistriz128:
17135 case Intrinsic::x86_sse42_pcmpestriz128: {
17139 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17140 case Intrinsic::x86_sse42_pcmpistria128:
17141 Opcode = X86ISD::PCMPISTRI;
17142 X86CC = X86::COND_A;
17144 case Intrinsic::x86_sse42_pcmpestria128:
17145 Opcode = X86ISD::PCMPESTRI;
17146 X86CC = X86::COND_A;
17148 case Intrinsic::x86_sse42_pcmpistric128:
17149 Opcode = X86ISD::PCMPISTRI;
17150 X86CC = X86::COND_B;
17152 case Intrinsic::x86_sse42_pcmpestric128:
17153 Opcode = X86ISD::PCMPESTRI;
17154 X86CC = X86::COND_B;
17156 case Intrinsic::x86_sse42_pcmpistrio128:
17157 Opcode = X86ISD::PCMPISTRI;
17158 X86CC = X86::COND_O;
17160 case Intrinsic::x86_sse42_pcmpestrio128:
17161 Opcode = X86ISD::PCMPESTRI;
17162 X86CC = X86::COND_O;
17164 case Intrinsic::x86_sse42_pcmpistris128:
17165 Opcode = X86ISD::PCMPISTRI;
17166 X86CC = X86::COND_S;
17168 case Intrinsic::x86_sse42_pcmpestris128:
17169 Opcode = X86ISD::PCMPESTRI;
17170 X86CC = X86::COND_S;
17172 case Intrinsic::x86_sse42_pcmpistriz128:
17173 Opcode = X86ISD::PCMPISTRI;
17174 X86CC = X86::COND_E;
17176 case Intrinsic::x86_sse42_pcmpestriz128:
17177 Opcode = X86ISD::PCMPESTRI;
17178 X86CC = X86::COND_E;
17181 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17182 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17183 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17184 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17185 DAG.getConstant(X86CC, MVT::i8),
17186 SDValue(PCMP.getNode(), 1));
17187 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17190 case Intrinsic::x86_sse42_pcmpistri128:
17191 case Intrinsic::x86_sse42_pcmpestri128: {
17193 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17194 Opcode = X86ISD::PCMPISTRI;
17196 Opcode = X86ISD::PCMPESTRI;
17198 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17199 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17200 return DAG.getNode(Opcode, dl, VTs, NewOps);
17203 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17204 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17205 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17206 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17207 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17208 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17209 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17210 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17211 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17212 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17213 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17214 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17215 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17216 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17217 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17218 dl, Op.getValueType(),
17222 Op.getOperand(4), Op.getOperand(1),
17228 case Intrinsic::x86_fma_vfmadd_ps:
17229 case Intrinsic::x86_fma_vfmadd_pd:
17230 case Intrinsic::x86_fma_vfmsub_ps:
17231 case Intrinsic::x86_fma_vfmsub_pd:
17232 case Intrinsic::x86_fma_vfnmadd_ps:
17233 case Intrinsic::x86_fma_vfnmadd_pd:
17234 case Intrinsic::x86_fma_vfnmsub_ps:
17235 case Intrinsic::x86_fma_vfnmsub_pd:
17236 case Intrinsic::x86_fma_vfmaddsub_ps:
17237 case Intrinsic::x86_fma_vfmaddsub_pd:
17238 case Intrinsic::x86_fma_vfmsubadd_ps:
17239 case Intrinsic::x86_fma_vfmsubadd_pd:
17240 case Intrinsic::x86_fma_vfmadd_ps_256:
17241 case Intrinsic::x86_fma_vfmadd_pd_256:
17242 case Intrinsic::x86_fma_vfmsub_ps_256:
17243 case Intrinsic::x86_fma_vfmsub_pd_256:
17244 case Intrinsic::x86_fma_vfnmadd_ps_256:
17245 case Intrinsic::x86_fma_vfnmadd_pd_256:
17246 case Intrinsic::x86_fma_vfnmsub_ps_256:
17247 case Intrinsic::x86_fma_vfnmsub_pd_256:
17248 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17249 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17250 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17251 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17252 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17253 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17257 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17258 SDValue Src, SDValue Mask, SDValue Base,
17259 SDValue Index, SDValue ScaleOp, SDValue Chain,
17260 const X86Subtarget * Subtarget) {
17262 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17263 assert(C && "Invalid scale type");
17264 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17265 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17266 Index.getSimpleValueType().getVectorNumElements());
17268 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17270 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17272 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17273 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17274 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17275 SDValue Segment = DAG.getRegister(0, MVT::i32);
17276 if (Src.getOpcode() == ISD::UNDEF)
17277 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17278 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17279 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17280 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17281 return DAG.getMergeValues(RetOps, dl);
17284 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17285 SDValue Src, SDValue Mask, SDValue Base,
17286 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17288 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17289 assert(C && "Invalid scale type");
17290 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17291 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17292 SDValue Segment = DAG.getRegister(0, MVT::i32);
17293 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17294 Index.getSimpleValueType().getVectorNumElements());
17296 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17298 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17300 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17301 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17302 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17303 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17304 return SDValue(Res, 1);
17307 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17308 SDValue Mask, SDValue Base, SDValue Index,
17309 SDValue ScaleOp, SDValue Chain) {
17311 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17312 assert(C && "Invalid scale type");
17313 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17314 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17315 SDValue Segment = DAG.getRegister(0, MVT::i32);
17317 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17319 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17321 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17323 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17324 //SDVTList VTs = DAG.getVTList(MVT::Other);
17325 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17326 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17327 return SDValue(Res, 0);
17330 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17331 // read performance monitor counters (x86_rdpmc).
17332 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17333 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17334 SmallVectorImpl<SDValue> &Results) {
17335 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17336 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17339 // The ECX register is used to select the index of the performance counter
17341 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17343 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17345 // Reads the content of a 64-bit performance counter and returns it in the
17346 // registers EDX:EAX.
17347 if (Subtarget->is64Bit()) {
17348 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17349 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17352 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17353 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17356 Chain = HI.getValue(1);
17358 if (Subtarget->is64Bit()) {
17359 // The EAX register is loaded with the low-order 32 bits. The EDX register
17360 // is loaded with the supported high-order bits of the counter.
17361 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17362 DAG.getConstant(32, MVT::i8));
17363 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17364 Results.push_back(Chain);
17368 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17369 SDValue Ops[] = { LO, HI };
17370 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17371 Results.push_back(Pair);
17372 Results.push_back(Chain);
17375 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17376 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17377 // also used to custom lower READCYCLECOUNTER nodes.
17378 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17379 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17380 SmallVectorImpl<SDValue> &Results) {
17381 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17382 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17385 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17386 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17387 // and the EAX register is loaded with the low-order 32 bits.
17388 if (Subtarget->is64Bit()) {
17389 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17390 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17393 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17394 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17397 SDValue Chain = HI.getValue(1);
17399 if (Opcode == X86ISD::RDTSCP_DAG) {
17400 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17402 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17403 // the ECX register. Add 'ecx' explicitly to the chain.
17404 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17406 // Explicitly store the content of ECX at the location passed in input
17407 // to the 'rdtscp' intrinsic.
17408 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17409 MachinePointerInfo(), false, false, 0);
17412 if (Subtarget->is64Bit()) {
17413 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17414 // the EAX register is loaded with the low-order 32 bits.
17415 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17416 DAG.getConstant(32, MVT::i8));
17417 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17418 Results.push_back(Chain);
17422 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17423 SDValue Ops[] = { LO, HI };
17424 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17425 Results.push_back(Pair);
17426 Results.push_back(Chain);
17429 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17430 SelectionDAG &DAG) {
17431 SmallVector<SDValue, 2> Results;
17433 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17435 return DAG.getMergeValues(Results, DL);
17439 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17440 SelectionDAG &DAG) {
17441 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17443 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17448 switch(IntrData->Type) {
17450 llvm_unreachable("Unknown Intrinsic Type");
17454 // Emit the node with the right value type.
17455 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17456 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17458 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17459 // Otherwise return the value from Rand, which is always 0, casted to i32.
17460 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17461 DAG.getConstant(1, Op->getValueType(1)),
17462 DAG.getConstant(X86::COND_B, MVT::i32),
17463 SDValue(Result.getNode(), 1) };
17464 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17465 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17468 // Return { result, isValid, chain }.
17469 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17470 SDValue(Result.getNode(), 2));
17473 //gather(v1, mask, index, base, scale);
17474 SDValue Chain = Op.getOperand(0);
17475 SDValue Src = Op.getOperand(2);
17476 SDValue Base = Op.getOperand(3);
17477 SDValue Index = Op.getOperand(4);
17478 SDValue Mask = Op.getOperand(5);
17479 SDValue Scale = Op.getOperand(6);
17480 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17484 //scatter(base, mask, index, v1, scale);
17485 SDValue Chain = Op.getOperand(0);
17486 SDValue Base = Op.getOperand(2);
17487 SDValue Mask = Op.getOperand(3);
17488 SDValue Index = Op.getOperand(4);
17489 SDValue Src = Op.getOperand(5);
17490 SDValue Scale = Op.getOperand(6);
17491 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17494 SDValue Hint = Op.getOperand(6);
17496 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17497 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17498 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17499 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17500 SDValue Chain = Op.getOperand(0);
17501 SDValue Mask = Op.getOperand(2);
17502 SDValue Index = Op.getOperand(3);
17503 SDValue Base = Op.getOperand(4);
17504 SDValue Scale = Op.getOperand(5);
17505 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17507 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17509 SmallVector<SDValue, 2> Results;
17510 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17511 return DAG.getMergeValues(Results, dl);
17513 // Read Performance Monitoring Counters.
17515 SmallVector<SDValue, 2> Results;
17516 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17517 return DAG.getMergeValues(Results, dl);
17519 // XTEST intrinsics.
17521 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17522 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17523 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17524 DAG.getConstant(X86::COND_NE, MVT::i8),
17526 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17527 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17528 Ret, SDValue(InTrans.getNode(), 1));
17532 SmallVector<SDValue, 2> Results;
17533 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17534 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17535 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17536 DAG.getConstant(-1, MVT::i8));
17537 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17538 Op.getOperand(4), GenCF.getValue(1));
17539 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17540 Op.getOperand(5), MachinePointerInfo(),
17542 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17543 DAG.getConstant(X86::COND_B, MVT::i8),
17545 Results.push_back(SetCC);
17546 Results.push_back(Store);
17547 return DAG.getMergeValues(Results, dl);
17552 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17553 SelectionDAG &DAG) const {
17554 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17555 MFI->setReturnAddressIsTaken(true);
17557 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17560 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17562 EVT PtrVT = getPointerTy();
17565 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17566 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17567 DAG.getSubtarget().getRegisterInfo());
17568 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17569 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17570 DAG.getNode(ISD::ADD, dl, PtrVT,
17571 FrameAddr, Offset),
17572 MachinePointerInfo(), false, false, false, 0);
17575 // Just load the return address.
17576 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17577 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17578 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17581 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17582 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17583 MFI->setFrameAddressIsTaken(true);
17585 EVT VT = Op.getValueType();
17586 SDLoc dl(Op); // FIXME probably not meaningful
17587 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17588 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17589 DAG.getSubtarget().getRegisterInfo());
17590 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17591 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17592 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17593 "Invalid Frame Register!");
17594 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17596 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17597 MachinePointerInfo(),
17598 false, false, false, 0);
17602 // FIXME? Maybe this could be a TableGen attribute on some registers and
17603 // this table could be generated automatically from RegInfo.
17604 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17606 unsigned Reg = StringSwitch<unsigned>(RegName)
17607 .Case("esp", X86::ESP)
17608 .Case("rsp", X86::RSP)
17612 report_fatal_error("Invalid register name global variable");
17615 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17616 SelectionDAG &DAG) const {
17617 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17618 DAG.getSubtarget().getRegisterInfo());
17619 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17622 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17623 SDValue Chain = Op.getOperand(0);
17624 SDValue Offset = Op.getOperand(1);
17625 SDValue Handler = Op.getOperand(2);
17628 EVT PtrVT = getPointerTy();
17629 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17630 DAG.getSubtarget().getRegisterInfo());
17631 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17632 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17633 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17634 "Invalid Frame Register!");
17635 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17636 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17638 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17639 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17640 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17641 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17643 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17645 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17646 DAG.getRegister(StoreAddrReg, PtrVT));
17649 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17650 SelectionDAG &DAG) const {
17652 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17653 DAG.getVTList(MVT::i32, MVT::Other),
17654 Op.getOperand(0), Op.getOperand(1));
17657 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17658 SelectionDAG &DAG) const {
17660 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17661 Op.getOperand(0), Op.getOperand(1));
17664 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17665 return Op.getOperand(0);
17668 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17669 SelectionDAG &DAG) const {
17670 SDValue Root = Op.getOperand(0);
17671 SDValue Trmp = Op.getOperand(1); // trampoline
17672 SDValue FPtr = Op.getOperand(2); // nested function
17673 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17676 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17677 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17679 if (Subtarget->is64Bit()) {
17680 SDValue OutChains[6];
17682 // Large code-model.
17683 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17684 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17686 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17687 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17689 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17691 // Load the pointer to the nested function into R11.
17692 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17693 SDValue Addr = Trmp;
17694 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17695 Addr, MachinePointerInfo(TrmpAddr),
17698 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17699 DAG.getConstant(2, MVT::i64));
17700 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17701 MachinePointerInfo(TrmpAddr, 2),
17704 // Load the 'nest' parameter value into R10.
17705 // R10 is specified in X86CallingConv.td
17706 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17707 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17708 DAG.getConstant(10, MVT::i64));
17709 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17710 Addr, MachinePointerInfo(TrmpAddr, 10),
17713 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17714 DAG.getConstant(12, MVT::i64));
17715 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17716 MachinePointerInfo(TrmpAddr, 12),
17719 // Jump to the nested function.
17720 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17721 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17722 DAG.getConstant(20, MVT::i64));
17723 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17724 Addr, MachinePointerInfo(TrmpAddr, 20),
17727 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17728 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17729 DAG.getConstant(22, MVT::i64));
17730 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17731 MachinePointerInfo(TrmpAddr, 22),
17734 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17736 const Function *Func =
17737 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17738 CallingConv::ID CC = Func->getCallingConv();
17743 llvm_unreachable("Unsupported calling convention");
17744 case CallingConv::C:
17745 case CallingConv::X86_StdCall: {
17746 // Pass 'nest' parameter in ECX.
17747 // Must be kept in sync with X86CallingConv.td
17748 NestReg = X86::ECX;
17750 // Check that ECX wasn't needed by an 'inreg' parameter.
17751 FunctionType *FTy = Func->getFunctionType();
17752 const AttributeSet &Attrs = Func->getAttributes();
17754 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17755 unsigned InRegCount = 0;
17758 for (FunctionType::param_iterator I = FTy->param_begin(),
17759 E = FTy->param_end(); I != E; ++I, ++Idx)
17760 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17761 // FIXME: should only count parameters that are lowered to integers.
17762 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17764 if (InRegCount > 2) {
17765 report_fatal_error("Nest register in use - reduce number of inreg"
17771 case CallingConv::X86_FastCall:
17772 case CallingConv::X86_ThisCall:
17773 case CallingConv::Fast:
17774 // Pass 'nest' parameter in EAX.
17775 // Must be kept in sync with X86CallingConv.td
17776 NestReg = X86::EAX;
17780 SDValue OutChains[4];
17781 SDValue Addr, Disp;
17783 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17784 DAG.getConstant(10, MVT::i32));
17785 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17787 // This is storing the opcode for MOV32ri.
17788 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17789 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17790 OutChains[0] = DAG.getStore(Root, dl,
17791 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17792 Trmp, MachinePointerInfo(TrmpAddr),
17795 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17796 DAG.getConstant(1, MVT::i32));
17797 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17798 MachinePointerInfo(TrmpAddr, 1),
17801 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17802 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17803 DAG.getConstant(5, MVT::i32));
17804 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17805 MachinePointerInfo(TrmpAddr, 5),
17808 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17809 DAG.getConstant(6, MVT::i32));
17810 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17811 MachinePointerInfo(TrmpAddr, 6),
17814 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17818 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17819 SelectionDAG &DAG) const {
17821 The rounding mode is in bits 11:10 of FPSR, and has the following
17823 00 Round to nearest
17828 FLT_ROUNDS, on the other hand, expects the following:
17835 To perform the conversion, we do:
17836 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17839 MachineFunction &MF = DAG.getMachineFunction();
17840 const TargetMachine &TM = MF.getTarget();
17841 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17842 unsigned StackAlignment = TFI.getStackAlignment();
17843 MVT VT = Op.getSimpleValueType();
17846 // Save FP Control Word to stack slot
17847 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17848 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17850 MachineMemOperand *MMO =
17851 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17852 MachineMemOperand::MOStore, 2, 2);
17854 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17855 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17856 DAG.getVTList(MVT::Other),
17857 Ops, MVT::i16, MMO);
17859 // Load FP Control Word from stack slot
17860 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17861 MachinePointerInfo(), false, false, false, 0);
17863 // Transform as necessary
17865 DAG.getNode(ISD::SRL, DL, MVT::i16,
17866 DAG.getNode(ISD::AND, DL, MVT::i16,
17867 CWD, DAG.getConstant(0x800, MVT::i16)),
17868 DAG.getConstant(11, MVT::i8));
17870 DAG.getNode(ISD::SRL, DL, MVT::i16,
17871 DAG.getNode(ISD::AND, DL, MVT::i16,
17872 CWD, DAG.getConstant(0x400, MVT::i16)),
17873 DAG.getConstant(9, MVT::i8));
17876 DAG.getNode(ISD::AND, DL, MVT::i16,
17877 DAG.getNode(ISD::ADD, DL, MVT::i16,
17878 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17879 DAG.getConstant(1, MVT::i16)),
17880 DAG.getConstant(3, MVT::i16));
17882 return DAG.getNode((VT.getSizeInBits() < 16 ?
17883 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17886 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17887 MVT VT = Op.getSimpleValueType();
17889 unsigned NumBits = VT.getSizeInBits();
17892 Op = Op.getOperand(0);
17893 if (VT == MVT::i8) {
17894 // Zero extend to i32 since there is not an i8 bsr.
17896 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17899 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17900 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17901 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17903 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17906 DAG.getConstant(NumBits+NumBits-1, OpVT),
17907 DAG.getConstant(X86::COND_E, MVT::i8),
17910 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17912 // Finally xor with NumBits-1.
17913 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17916 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17920 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17921 MVT VT = Op.getSimpleValueType();
17923 unsigned NumBits = VT.getSizeInBits();
17926 Op = Op.getOperand(0);
17927 if (VT == MVT::i8) {
17928 // Zero extend to i32 since there is not an i8 bsr.
17930 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17933 // Issue a bsr (scan bits in reverse).
17934 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17935 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17937 // And xor with NumBits-1.
17938 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17941 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17945 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17946 MVT VT = Op.getSimpleValueType();
17947 unsigned NumBits = VT.getSizeInBits();
17949 Op = Op.getOperand(0);
17951 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17952 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17953 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17955 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17958 DAG.getConstant(NumBits, VT),
17959 DAG.getConstant(X86::COND_E, MVT::i8),
17962 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17965 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17966 // ones, and then concatenate the result back.
17967 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17968 MVT VT = Op.getSimpleValueType();
17970 assert(VT.is256BitVector() && VT.isInteger() &&
17971 "Unsupported value type for operation");
17973 unsigned NumElems = VT.getVectorNumElements();
17976 // Extract the LHS vectors
17977 SDValue LHS = Op.getOperand(0);
17978 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17979 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17981 // Extract the RHS vectors
17982 SDValue RHS = Op.getOperand(1);
17983 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17984 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17986 MVT EltVT = VT.getVectorElementType();
17987 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17989 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17990 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17991 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17994 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17995 assert(Op.getSimpleValueType().is256BitVector() &&
17996 Op.getSimpleValueType().isInteger() &&
17997 "Only handle AVX 256-bit vector integer operation");
17998 return Lower256IntArith(Op, DAG);
18001 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18002 assert(Op.getSimpleValueType().is256BitVector() &&
18003 Op.getSimpleValueType().isInteger() &&
18004 "Only handle AVX 256-bit vector integer operation");
18005 return Lower256IntArith(Op, DAG);
18008 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18009 SelectionDAG &DAG) {
18011 MVT VT = Op.getSimpleValueType();
18013 // Decompose 256-bit ops into smaller 128-bit ops.
18014 if (VT.is256BitVector() && !Subtarget->hasInt256())
18015 return Lower256IntArith(Op, DAG);
18017 SDValue A = Op.getOperand(0);
18018 SDValue B = Op.getOperand(1);
18020 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18021 if (VT == MVT::v4i32) {
18022 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18023 "Should not custom lower when pmuldq is available!");
18025 // Extract the odd parts.
18026 static const int UnpackMask[] = { 1, -1, 3, -1 };
18027 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18028 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18030 // Multiply the even parts.
18031 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18032 // Now multiply odd parts.
18033 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18035 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18036 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18038 // Merge the two vectors back together with a shuffle. This expands into 2
18040 static const int ShufMask[] = { 0, 4, 2, 6 };
18041 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18044 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18045 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18047 // Ahi = psrlqi(a, 32);
18048 // Bhi = psrlqi(b, 32);
18050 // AloBlo = pmuludq(a, b);
18051 // AloBhi = pmuludq(a, Bhi);
18052 // AhiBlo = pmuludq(Ahi, b);
18054 // AloBhi = psllqi(AloBhi, 32);
18055 // AhiBlo = psllqi(AhiBlo, 32);
18056 // return AloBlo + AloBhi + AhiBlo;
18058 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18059 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18061 // Bit cast to 32-bit vectors for MULUDQ
18062 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18063 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18064 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18065 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18066 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18067 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18069 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18070 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18071 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18073 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18074 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18076 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18077 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18080 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18081 assert(Subtarget->isTargetWin64() && "Unexpected target");
18082 EVT VT = Op.getValueType();
18083 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18084 "Unexpected return type for lowering");
18088 switch (Op->getOpcode()) {
18089 default: llvm_unreachable("Unexpected request for libcall!");
18090 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18091 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18092 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18093 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18094 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18095 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18099 SDValue InChain = DAG.getEntryNode();
18101 TargetLowering::ArgListTy Args;
18102 TargetLowering::ArgListEntry Entry;
18103 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18104 EVT ArgVT = Op->getOperand(i).getValueType();
18105 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18106 "Unexpected argument type for lowering");
18107 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18108 Entry.Node = StackPtr;
18109 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18111 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18112 Entry.Ty = PointerType::get(ArgTy,0);
18113 Entry.isSExt = false;
18114 Entry.isZExt = false;
18115 Args.push_back(Entry);
18118 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18121 TargetLowering::CallLoweringInfo CLI(DAG);
18122 CLI.setDebugLoc(dl).setChain(InChain)
18123 .setCallee(getLibcallCallingConv(LC),
18124 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18125 Callee, std::move(Args), 0)
18126 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18128 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18129 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18132 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18133 SelectionDAG &DAG) {
18134 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18135 EVT VT = Op0.getValueType();
18138 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18139 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18141 // PMULxD operations multiply each even value (starting at 0) of LHS with
18142 // the related value of RHS and produce a widen result.
18143 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18144 // => <2 x i64> <ae|cg>
18146 // In other word, to have all the results, we need to perform two PMULxD:
18147 // 1. one with the even values.
18148 // 2. one with the odd values.
18149 // To achieve #2, with need to place the odd values at an even position.
18151 // Place the odd value at an even position (basically, shift all values 1
18152 // step to the left):
18153 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18154 // <a|b|c|d> => <b|undef|d|undef>
18155 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18156 // <e|f|g|h> => <f|undef|h|undef>
18157 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18159 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18161 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18162 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18164 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18165 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18166 // => <2 x i64> <ae|cg>
18167 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18168 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18169 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18170 // => <2 x i64> <bf|dh>
18171 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18172 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18174 // Shuffle it back into the right order.
18175 SDValue Highs, Lows;
18176 if (VT == MVT::v8i32) {
18177 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18178 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18179 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18180 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18182 const int HighMask[] = {1, 5, 3, 7};
18183 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18184 const int LowMask[] = {0, 4, 2, 6};
18185 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18188 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18189 // unsigned multiply.
18190 if (IsSigned && !Subtarget->hasSSE41()) {
18192 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18193 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18194 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18195 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18196 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18198 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18199 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18202 // The first result of MUL_LOHI is actually the low value, followed by the
18204 SDValue Ops[] = {Lows, Highs};
18205 return DAG.getMergeValues(Ops, dl);
18208 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18209 const X86Subtarget *Subtarget) {
18210 MVT VT = Op.getSimpleValueType();
18212 SDValue R = Op.getOperand(0);
18213 SDValue Amt = Op.getOperand(1);
18215 // Optimize shl/srl/sra with constant shift amount.
18216 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18217 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18218 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18220 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18221 (Subtarget->hasInt256() &&
18222 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18223 (Subtarget->hasAVX512() &&
18224 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18225 if (Op.getOpcode() == ISD::SHL)
18226 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18228 if (Op.getOpcode() == ISD::SRL)
18229 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18231 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18232 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18236 if (VT == MVT::v16i8) {
18237 if (Op.getOpcode() == ISD::SHL) {
18238 // Make a large shift.
18239 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18240 MVT::v8i16, R, ShiftAmt,
18242 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18243 // Zero out the rightmost bits.
18244 SmallVector<SDValue, 16> V(16,
18245 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18247 return DAG.getNode(ISD::AND, dl, VT, SHL,
18248 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18250 if (Op.getOpcode() == ISD::SRL) {
18251 // Make a large shift.
18252 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18253 MVT::v8i16, R, ShiftAmt,
18255 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18256 // Zero out the leftmost bits.
18257 SmallVector<SDValue, 16> V(16,
18258 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18260 return DAG.getNode(ISD::AND, dl, VT, SRL,
18261 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18263 if (Op.getOpcode() == ISD::SRA) {
18264 if (ShiftAmt == 7) {
18265 // R s>> 7 === R s< 0
18266 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18267 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18270 // R s>> a === ((R u>> a) ^ m) - m
18271 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18272 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18274 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18275 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18276 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18279 llvm_unreachable("Unknown shift opcode.");
18282 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18283 if (Op.getOpcode() == ISD::SHL) {
18284 // Make a large shift.
18285 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18286 MVT::v16i16, R, ShiftAmt,
18288 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18289 // Zero out the rightmost bits.
18290 SmallVector<SDValue, 32> V(32,
18291 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18293 return DAG.getNode(ISD::AND, dl, VT, SHL,
18294 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18296 if (Op.getOpcode() == ISD::SRL) {
18297 // Make a large shift.
18298 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18299 MVT::v16i16, R, ShiftAmt,
18301 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18302 // Zero out the leftmost bits.
18303 SmallVector<SDValue, 32> V(32,
18304 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18306 return DAG.getNode(ISD::AND, dl, VT, SRL,
18307 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18309 if (Op.getOpcode() == ISD::SRA) {
18310 if (ShiftAmt == 7) {
18311 // R s>> 7 === R s< 0
18312 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18313 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18316 // R s>> a === ((R u>> a) ^ m) - m
18317 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18318 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18320 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18321 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18322 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18325 llvm_unreachable("Unknown shift opcode.");
18330 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18331 if (!Subtarget->is64Bit() &&
18332 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18333 Amt.getOpcode() == ISD::BITCAST &&
18334 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18335 Amt = Amt.getOperand(0);
18336 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18337 VT.getVectorNumElements();
18338 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18339 uint64_t ShiftAmt = 0;
18340 for (unsigned i = 0; i != Ratio; ++i) {
18341 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18345 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18347 // Check remaining shift amounts.
18348 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18349 uint64_t ShAmt = 0;
18350 for (unsigned j = 0; j != Ratio; ++j) {
18351 ConstantSDNode *C =
18352 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18356 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18358 if (ShAmt != ShiftAmt)
18361 switch (Op.getOpcode()) {
18363 llvm_unreachable("Unknown shift opcode!");
18365 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18368 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18371 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18379 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18380 const X86Subtarget* Subtarget) {
18381 MVT VT = Op.getSimpleValueType();
18383 SDValue R = Op.getOperand(0);
18384 SDValue Amt = Op.getOperand(1);
18386 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18387 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18388 (Subtarget->hasInt256() &&
18389 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18390 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18391 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18393 EVT EltVT = VT.getVectorElementType();
18395 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18396 unsigned NumElts = VT.getVectorNumElements();
18398 for (i = 0; i != NumElts; ++i) {
18399 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
18403 for (j = i; j != NumElts; ++j) {
18404 SDValue Arg = Amt.getOperand(j);
18405 if (Arg.getOpcode() == ISD::UNDEF) continue;
18406 if (Arg != Amt.getOperand(i))
18409 if (i != NumElts && j == NumElts)
18410 BaseShAmt = Amt.getOperand(i);
18412 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18413 Amt = Amt.getOperand(0);
18414 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18415 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18416 SDValue InVec = Amt.getOperand(0);
18417 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18418 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18420 for (; i != NumElts; ++i) {
18421 SDValue Arg = InVec.getOperand(i);
18422 if (Arg.getOpcode() == ISD::UNDEF) continue;
18426 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18427 if (ConstantSDNode *C =
18428 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18429 unsigned SplatIdx =
18430 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18431 if (C->getZExtValue() == SplatIdx)
18432 BaseShAmt = InVec.getOperand(1);
18435 if (!BaseShAmt.getNode())
18436 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18437 DAG.getIntPtrConstant(0));
18441 if (BaseShAmt.getNode()) {
18442 if (EltVT.bitsGT(MVT::i32))
18443 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18444 else if (EltVT.bitsLT(MVT::i32))
18445 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18447 switch (Op.getOpcode()) {
18449 llvm_unreachable("Unknown shift opcode!");
18451 switch (VT.SimpleTy) {
18452 default: return SDValue();
18461 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18464 switch (VT.SimpleTy) {
18465 default: return SDValue();
18472 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18475 switch (VT.SimpleTy) {
18476 default: return SDValue();
18485 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18491 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18492 if (!Subtarget->is64Bit() &&
18493 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18494 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18495 Amt.getOpcode() == ISD::BITCAST &&
18496 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18497 Amt = Amt.getOperand(0);
18498 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18499 VT.getVectorNumElements();
18500 std::vector<SDValue> Vals(Ratio);
18501 for (unsigned i = 0; i != Ratio; ++i)
18502 Vals[i] = Amt.getOperand(i);
18503 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18504 for (unsigned j = 0; j != Ratio; ++j)
18505 if (Vals[j] != Amt.getOperand(i + j))
18508 switch (Op.getOpcode()) {
18510 llvm_unreachable("Unknown shift opcode!");
18512 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18514 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18516 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18523 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18524 SelectionDAG &DAG) {
18525 MVT VT = Op.getSimpleValueType();
18527 SDValue R = Op.getOperand(0);
18528 SDValue Amt = Op.getOperand(1);
18531 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18532 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18534 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18538 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18542 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18544 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18545 if (Subtarget->hasInt256()) {
18546 if (Op.getOpcode() == ISD::SRL &&
18547 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18548 VT == MVT::v4i64 || VT == MVT::v8i32))
18550 if (Op.getOpcode() == ISD::SHL &&
18551 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18552 VT == MVT::v4i64 || VT == MVT::v8i32))
18554 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18558 // If possible, lower this packed shift into a vector multiply instead of
18559 // expanding it into a sequence of scalar shifts.
18560 // Do this only if the vector shift count is a constant build_vector.
18561 if (Op.getOpcode() == ISD::SHL &&
18562 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18563 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18564 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18565 SmallVector<SDValue, 8> Elts;
18566 EVT SVT = VT.getScalarType();
18567 unsigned SVTBits = SVT.getSizeInBits();
18568 const APInt &One = APInt(SVTBits, 1);
18569 unsigned NumElems = VT.getVectorNumElements();
18571 for (unsigned i=0; i !=NumElems; ++i) {
18572 SDValue Op = Amt->getOperand(i);
18573 if (Op->getOpcode() == ISD::UNDEF) {
18574 Elts.push_back(Op);
18578 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18579 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18580 uint64_t ShAmt = C.getZExtValue();
18581 if (ShAmt >= SVTBits) {
18582 Elts.push_back(DAG.getUNDEF(SVT));
18585 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18587 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18588 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18591 // Lower SHL with variable shift amount.
18592 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18593 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18595 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18596 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18597 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18598 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18601 // If possible, lower this shift as a sequence of two shifts by
18602 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18604 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18606 // Could be rewritten as:
18607 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18609 // The advantage is that the two shifts from the example would be
18610 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18611 // the vector shift into four scalar shifts plus four pairs of vector
18613 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18614 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18615 unsigned TargetOpcode = X86ISD::MOVSS;
18616 bool CanBeSimplified;
18617 // The splat value for the first packed shift (the 'X' from the example).
18618 SDValue Amt1 = Amt->getOperand(0);
18619 // The splat value for the second packed shift (the 'Y' from the example).
18620 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18621 Amt->getOperand(2);
18623 // See if it is possible to replace this node with a sequence of
18624 // two shifts followed by a MOVSS/MOVSD
18625 if (VT == MVT::v4i32) {
18626 // Check if it is legal to use a MOVSS.
18627 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18628 Amt2 == Amt->getOperand(3);
18629 if (!CanBeSimplified) {
18630 // Otherwise, check if we can still simplify this node using a MOVSD.
18631 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18632 Amt->getOperand(2) == Amt->getOperand(3);
18633 TargetOpcode = X86ISD::MOVSD;
18634 Amt2 = Amt->getOperand(2);
18637 // Do similar checks for the case where the machine value type
18639 CanBeSimplified = Amt1 == Amt->getOperand(1);
18640 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18641 CanBeSimplified = Amt2 == Amt->getOperand(i);
18643 if (!CanBeSimplified) {
18644 TargetOpcode = X86ISD::MOVSD;
18645 CanBeSimplified = true;
18646 Amt2 = Amt->getOperand(4);
18647 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18648 CanBeSimplified = Amt1 == Amt->getOperand(i);
18649 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18650 CanBeSimplified = Amt2 == Amt->getOperand(j);
18654 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18655 isa<ConstantSDNode>(Amt2)) {
18656 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18657 EVT CastVT = MVT::v4i32;
18659 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18660 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18662 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18663 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18664 if (TargetOpcode == X86ISD::MOVSD)
18665 CastVT = MVT::v2i64;
18666 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18667 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18668 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18670 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18674 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18675 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18678 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18679 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18681 // Turn 'a' into a mask suitable for VSELECT
18682 SDValue VSelM = DAG.getConstant(0x80, VT);
18683 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18684 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18686 SDValue CM1 = DAG.getConstant(0x0f, VT);
18687 SDValue CM2 = DAG.getConstant(0x3f, VT);
18689 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18690 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18691 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18692 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18693 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18696 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18697 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18698 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18700 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18701 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18702 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18703 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18704 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18707 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18708 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18709 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18711 // return VSELECT(r, r+r, a);
18712 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18713 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18717 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18718 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18719 // solution better.
18720 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18721 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18723 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18724 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18725 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18726 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18727 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18730 // Decompose 256-bit shifts into smaller 128-bit shifts.
18731 if (VT.is256BitVector()) {
18732 unsigned NumElems = VT.getVectorNumElements();
18733 MVT EltVT = VT.getVectorElementType();
18734 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18736 // Extract the two vectors
18737 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18738 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18740 // Recreate the shift amount vectors
18741 SDValue Amt1, Amt2;
18742 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18743 // Constant shift amount
18744 SmallVector<SDValue, 4> Amt1Csts;
18745 SmallVector<SDValue, 4> Amt2Csts;
18746 for (unsigned i = 0; i != NumElems/2; ++i)
18747 Amt1Csts.push_back(Amt->getOperand(i));
18748 for (unsigned i = NumElems/2; i != NumElems; ++i)
18749 Amt2Csts.push_back(Amt->getOperand(i));
18751 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18752 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18754 // Variable shift amount
18755 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18756 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18759 // Issue new vector shifts for the smaller types
18760 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18761 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18763 // Concatenate the result back
18764 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18770 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18771 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18772 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18773 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18774 // has only one use.
18775 SDNode *N = Op.getNode();
18776 SDValue LHS = N->getOperand(0);
18777 SDValue RHS = N->getOperand(1);
18778 unsigned BaseOp = 0;
18781 switch (Op.getOpcode()) {
18782 default: llvm_unreachable("Unknown ovf instruction!");
18784 // A subtract of one will be selected as a INC. Note that INC doesn't
18785 // set CF, so we can't do this for UADDO.
18786 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18788 BaseOp = X86ISD::INC;
18789 Cond = X86::COND_O;
18792 BaseOp = X86ISD::ADD;
18793 Cond = X86::COND_O;
18796 BaseOp = X86ISD::ADD;
18797 Cond = X86::COND_B;
18800 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18801 // set CF, so we can't do this for USUBO.
18802 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18804 BaseOp = X86ISD::DEC;
18805 Cond = X86::COND_O;
18808 BaseOp = X86ISD::SUB;
18809 Cond = X86::COND_O;
18812 BaseOp = X86ISD::SUB;
18813 Cond = X86::COND_B;
18816 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18817 Cond = X86::COND_O;
18819 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18820 if (N->getValueType(0) == MVT::i8) {
18821 BaseOp = X86ISD::UMUL8;
18822 Cond = X86::COND_O;
18825 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18827 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18830 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18831 DAG.getConstant(X86::COND_O, MVT::i32),
18832 SDValue(Sum.getNode(), 2));
18834 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18838 // Also sets EFLAGS.
18839 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18840 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18843 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18844 DAG.getConstant(Cond, MVT::i32),
18845 SDValue(Sum.getNode(), 1));
18847 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18850 // Sign extension of the low part of vector elements. This may be used either
18851 // when sign extend instructions are not available or if the vector element
18852 // sizes already match the sign-extended size. If the vector elements are in
18853 // their pre-extended size and sign extend instructions are available, that will
18854 // be handled by LowerSIGN_EXTEND.
18855 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18856 SelectionDAG &DAG) const {
18858 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18859 MVT VT = Op.getSimpleValueType();
18861 if (!Subtarget->hasSSE2() || !VT.isVector())
18864 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18865 ExtraVT.getScalarType().getSizeInBits();
18867 switch (VT.SimpleTy) {
18868 default: return SDValue();
18871 if (!Subtarget->hasFp256())
18873 if (!Subtarget->hasInt256()) {
18874 // needs to be split
18875 unsigned NumElems = VT.getVectorNumElements();
18877 // Extract the LHS vectors
18878 SDValue LHS = Op.getOperand(0);
18879 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18880 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18882 MVT EltVT = VT.getVectorElementType();
18883 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18885 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18886 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18887 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18889 SDValue Extra = DAG.getValueType(ExtraVT);
18891 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18892 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18894 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18899 SDValue Op0 = Op.getOperand(0);
18901 // This is a sign extension of some low part of vector elements without
18902 // changing the size of the vector elements themselves:
18903 // Shift-Left + Shift-Right-Algebraic.
18904 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18906 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18912 /// Returns true if the operand type is exactly twice the native width, and
18913 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18914 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18915 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18916 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18917 const X86Subtarget &Subtarget =
18918 getTargetMachine().getSubtarget<X86Subtarget>();
18919 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18922 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18923 else if (OpWidth == 128)
18924 return Subtarget.hasCmpxchg16b();
18929 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18930 return needsCmpXchgNb(SI->getValueOperand()->getType());
18933 // Note: this turns large loads into lock cmpxchg8b/16b.
18934 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18935 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18936 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18937 return needsCmpXchgNb(PTy->getElementType());
18940 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18941 const X86Subtarget &Subtarget =
18942 getTargetMachine().getSubtarget<X86Subtarget>();
18943 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18944 const Type *MemType = AI->getType();
18946 // If the operand is too big, we must see if cmpxchg8/16b is available
18947 // and default to library calls otherwise.
18948 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18949 return needsCmpXchgNb(MemType);
18951 AtomicRMWInst::BinOp Op = AI->getOperation();
18954 llvm_unreachable("Unknown atomic operation");
18955 case AtomicRMWInst::Xchg:
18956 case AtomicRMWInst::Add:
18957 case AtomicRMWInst::Sub:
18958 // It's better to use xadd, xsub or xchg for these in all cases.
18960 case AtomicRMWInst::Or:
18961 case AtomicRMWInst::And:
18962 case AtomicRMWInst::Xor:
18963 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18964 // prefix to a normal instruction for these operations.
18965 return !AI->use_empty();
18966 case AtomicRMWInst::Nand:
18967 case AtomicRMWInst::Max:
18968 case AtomicRMWInst::Min:
18969 case AtomicRMWInst::UMax:
18970 case AtomicRMWInst::UMin:
18971 // These always require a non-trivial set of data operations on x86. We must
18972 // use a cmpxchg loop.
18977 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18978 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18979 // no-sse2). There isn't any reason to disable it if the target processor
18981 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18985 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18986 const X86Subtarget &Subtarget =
18987 getTargetMachine().getSubtarget<X86Subtarget>();
18988 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18989 const Type *MemType = AI->getType();
18990 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18991 // there is no benefit in turning such RMWs into loads, and it is actually
18992 // harmful as it introduces a mfence.
18993 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18996 auto Builder = IRBuilder<>(AI);
18997 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18998 auto SynchScope = AI->getSynchScope();
18999 // We must restrict the ordering to avoid generating loads with Release or
19000 // ReleaseAcquire orderings.
19001 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19002 auto Ptr = AI->getPointerOperand();
19004 // Before the load we need a fence. Here is an example lifted from
19005 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19008 // x.store(1, relaxed);
19009 // r1 = y.fetch_add(0, release);
19011 // y.fetch_add(42, acquire);
19012 // r2 = x.load(relaxed);
19013 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19014 // lowered to just a load without a fence. A mfence flushes the store buffer,
19015 // making the optimization clearly correct.
19016 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19017 // otherwise, we might be able to be more agressive on relaxed idempotent
19018 // rmw. In practice, they do not look useful, so we don't try to be
19019 // especially clever.
19020 if (SynchScope == SingleThread) {
19021 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19022 // the IR level, so we must wrap it in an intrinsic.
19024 } else if (hasMFENCE(Subtarget)) {
19025 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19026 Intrinsic::x86_sse2_mfence);
19027 Builder.CreateCall(MFence);
19029 // FIXME: it might make sense to use a locked operation here but on a
19030 // different cache-line to prevent cache-line bouncing. In practice it
19031 // is probably a small win, and x86 processors without mfence are rare
19032 // enough that we do not bother.
19036 // Finally we can emit the atomic load.
19037 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19038 AI->getType()->getPrimitiveSizeInBits());
19039 Loaded->setAtomic(Order, SynchScope);
19040 AI->replaceAllUsesWith(Loaded);
19041 AI->eraseFromParent();
19045 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19046 SelectionDAG &DAG) {
19048 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19049 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19050 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19051 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19053 // The only fence that needs an instruction is a sequentially-consistent
19054 // cross-thread fence.
19055 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19056 if (hasMFENCE(*Subtarget))
19057 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19059 SDValue Chain = Op.getOperand(0);
19060 SDValue Zero = DAG.getConstant(0, MVT::i32);
19062 DAG.getRegister(X86::ESP, MVT::i32), // Base
19063 DAG.getTargetConstant(1, MVT::i8), // Scale
19064 DAG.getRegister(0, MVT::i32), // Index
19065 DAG.getTargetConstant(0, MVT::i32), // Disp
19066 DAG.getRegister(0, MVT::i32), // Segment.
19070 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19071 return SDValue(Res, 0);
19074 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19075 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19078 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19079 SelectionDAG &DAG) {
19080 MVT T = Op.getSimpleValueType();
19084 switch(T.SimpleTy) {
19085 default: llvm_unreachable("Invalid value type!");
19086 case MVT::i8: Reg = X86::AL; size = 1; break;
19087 case MVT::i16: Reg = X86::AX; size = 2; break;
19088 case MVT::i32: Reg = X86::EAX; size = 4; break;
19090 assert(Subtarget->is64Bit() && "Node not type legal!");
19091 Reg = X86::RAX; size = 8;
19094 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19095 Op.getOperand(2), SDValue());
19096 SDValue Ops[] = { cpIn.getValue(0),
19099 DAG.getTargetConstant(size, MVT::i8),
19100 cpIn.getValue(1) };
19101 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19102 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19103 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19107 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19108 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19109 MVT::i32, cpOut.getValue(2));
19110 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19111 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19113 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19114 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19115 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19119 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19120 SelectionDAG &DAG) {
19121 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19122 MVT DstVT = Op.getSimpleValueType();
19124 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19125 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19126 if (DstVT != MVT::f64)
19127 // This conversion needs to be expanded.
19130 SDValue InVec = Op->getOperand(0);
19132 unsigned NumElts = SrcVT.getVectorNumElements();
19133 EVT SVT = SrcVT.getVectorElementType();
19135 // Widen the vector in input in the case of MVT::v2i32.
19136 // Example: from MVT::v2i32 to MVT::v4i32.
19137 SmallVector<SDValue, 16> Elts;
19138 for (unsigned i = 0, e = NumElts; i != e; ++i)
19139 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19140 DAG.getIntPtrConstant(i)));
19142 // Explicitly mark the extra elements as Undef.
19143 SDValue Undef = DAG.getUNDEF(SVT);
19144 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19145 Elts.push_back(Undef);
19147 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19148 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19149 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19150 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19151 DAG.getIntPtrConstant(0));
19154 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19155 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19156 assert((DstVT == MVT::i64 ||
19157 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19158 "Unexpected custom BITCAST");
19159 // i64 <=> MMX conversions are Legal.
19160 if (SrcVT==MVT::i64 && DstVT.isVector())
19162 if (DstVT==MVT::i64 && SrcVT.isVector())
19164 // MMX <=> MMX conversions are Legal.
19165 if (SrcVT.isVector() && DstVT.isVector())
19167 // All other conversions need to be expanded.
19171 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19172 SDNode *Node = Op.getNode();
19174 EVT T = Node->getValueType(0);
19175 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19176 DAG.getConstant(0, T), Node->getOperand(2));
19177 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19178 cast<AtomicSDNode>(Node)->getMemoryVT(),
19179 Node->getOperand(0),
19180 Node->getOperand(1), negOp,
19181 cast<AtomicSDNode>(Node)->getMemOperand(),
19182 cast<AtomicSDNode>(Node)->getOrdering(),
19183 cast<AtomicSDNode>(Node)->getSynchScope());
19186 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19187 SDNode *Node = Op.getNode();
19189 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19191 // Convert seq_cst store -> xchg
19192 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19193 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19194 // (The only way to get a 16-byte store is cmpxchg16b)
19195 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19196 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19197 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19198 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19199 cast<AtomicSDNode>(Node)->getMemoryVT(),
19200 Node->getOperand(0),
19201 Node->getOperand(1), Node->getOperand(2),
19202 cast<AtomicSDNode>(Node)->getMemOperand(),
19203 cast<AtomicSDNode>(Node)->getOrdering(),
19204 cast<AtomicSDNode>(Node)->getSynchScope());
19205 return Swap.getValue(1);
19207 // Other atomic stores have a simple pattern.
19211 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19212 EVT VT = Op.getNode()->getSimpleValueType(0);
19214 // Let legalize expand this if it isn't a legal type yet.
19215 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19218 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19221 bool ExtraOp = false;
19222 switch (Op.getOpcode()) {
19223 default: llvm_unreachable("Invalid code");
19224 case ISD::ADDC: Opc = X86ISD::ADD; break;
19225 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19226 case ISD::SUBC: Opc = X86ISD::SUB; break;
19227 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19231 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19233 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19234 Op.getOperand(1), Op.getOperand(2));
19237 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19238 SelectionDAG &DAG) {
19239 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19241 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19242 // which returns the values as { float, float } (in XMM0) or
19243 // { double, double } (which is returned in XMM0, XMM1).
19245 SDValue Arg = Op.getOperand(0);
19246 EVT ArgVT = Arg.getValueType();
19247 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19249 TargetLowering::ArgListTy Args;
19250 TargetLowering::ArgListEntry Entry;
19254 Entry.isSExt = false;
19255 Entry.isZExt = false;
19256 Args.push_back(Entry);
19258 bool isF64 = ArgVT == MVT::f64;
19259 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19260 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19261 // the results are returned via SRet in memory.
19262 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19263 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19264 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19266 Type *RetTy = isF64
19267 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19268 : (Type*)VectorType::get(ArgTy, 4);
19270 TargetLowering::CallLoweringInfo CLI(DAG);
19271 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19272 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19274 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19277 // Returned in xmm0 and xmm1.
19278 return CallResult.first;
19280 // Returned in bits 0:31 and 32:64 xmm0.
19281 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19282 CallResult.first, DAG.getIntPtrConstant(0));
19283 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19284 CallResult.first, DAG.getIntPtrConstant(1));
19285 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19286 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19289 /// LowerOperation - Provide custom lowering hooks for some operations.
19291 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19292 switch (Op.getOpcode()) {
19293 default: llvm_unreachable("Should not custom lower this!");
19294 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19295 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19296 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19297 return LowerCMP_SWAP(Op, Subtarget, DAG);
19298 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19299 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19300 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19301 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19302 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19303 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19304 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19305 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19306 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19307 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19308 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19309 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19310 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19311 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19312 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19313 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19314 case ISD::SHL_PARTS:
19315 case ISD::SRA_PARTS:
19316 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19317 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19318 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19319 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19320 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19321 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19322 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19323 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19324 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19325 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19326 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19328 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19329 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19330 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19331 case ISD::SETCC: return LowerSETCC(Op, DAG);
19332 case ISD::SELECT: return LowerSELECT(Op, DAG);
19333 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19334 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19335 case ISD::VASTART: return LowerVASTART(Op, DAG);
19336 case ISD::VAARG: return LowerVAARG(Op, DAG);
19337 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19338 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19339 case ISD::INTRINSIC_VOID:
19340 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19341 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19342 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19343 case ISD::FRAME_TO_ARGS_OFFSET:
19344 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19345 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19346 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19347 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19348 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19349 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19350 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19351 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19352 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19353 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19354 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19355 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19356 case ISD::UMUL_LOHI:
19357 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19360 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19366 case ISD::UMULO: return LowerXALUO(Op, DAG);
19367 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19368 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19372 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19373 case ISD::ADD: return LowerADD(Op, DAG);
19374 case ISD::SUB: return LowerSUB(Op, DAG);
19375 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19379 /// ReplaceNodeResults - Replace a node with an illegal result type
19380 /// with a new node built out of custom code.
19381 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19382 SmallVectorImpl<SDValue>&Results,
19383 SelectionDAG &DAG) const {
19385 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19386 switch (N->getOpcode()) {
19388 llvm_unreachable("Do not know how to custom type legalize this operation!");
19389 case ISD::SIGN_EXTEND_INREG:
19394 // We don't want to expand or promote these.
19401 case ISD::UDIVREM: {
19402 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19403 Results.push_back(V);
19406 case ISD::FP_TO_SINT:
19407 case ISD::FP_TO_UINT: {
19408 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19410 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19413 std::pair<SDValue,SDValue> Vals =
19414 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19415 SDValue FIST = Vals.first, StackSlot = Vals.second;
19416 if (FIST.getNode()) {
19417 EVT VT = N->getValueType(0);
19418 // Return a load from the stack slot.
19419 if (StackSlot.getNode())
19420 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19421 MachinePointerInfo(),
19422 false, false, false, 0));
19424 Results.push_back(FIST);
19428 case ISD::UINT_TO_FP: {
19429 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19430 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19431 N->getValueType(0) != MVT::v2f32)
19433 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19435 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19437 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19438 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19439 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19440 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19441 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19442 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19445 case ISD::FP_ROUND: {
19446 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19448 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19449 Results.push_back(V);
19452 case ISD::INTRINSIC_W_CHAIN: {
19453 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19455 default : llvm_unreachable("Do not know how to custom type "
19456 "legalize this intrinsic operation!");
19457 case Intrinsic::x86_rdtsc:
19458 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19460 case Intrinsic::x86_rdtscp:
19461 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19463 case Intrinsic::x86_rdpmc:
19464 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19467 case ISD::READCYCLECOUNTER: {
19468 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19471 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19472 EVT T = N->getValueType(0);
19473 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19474 bool Regs64bit = T == MVT::i128;
19475 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19476 SDValue cpInL, cpInH;
19477 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19478 DAG.getConstant(0, HalfT));
19479 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19480 DAG.getConstant(1, HalfT));
19481 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19482 Regs64bit ? X86::RAX : X86::EAX,
19484 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19485 Regs64bit ? X86::RDX : X86::EDX,
19486 cpInH, cpInL.getValue(1));
19487 SDValue swapInL, swapInH;
19488 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19489 DAG.getConstant(0, HalfT));
19490 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19491 DAG.getConstant(1, HalfT));
19492 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19493 Regs64bit ? X86::RBX : X86::EBX,
19494 swapInL, cpInH.getValue(1));
19495 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19496 Regs64bit ? X86::RCX : X86::ECX,
19497 swapInH, swapInL.getValue(1));
19498 SDValue Ops[] = { swapInH.getValue(0),
19500 swapInH.getValue(1) };
19501 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19502 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19503 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19504 X86ISD::LCMPXCHG8_DAG;
19505 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19506 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19507 Regs64bit ? X86::RAX : X86::EAX,
19508 HalfT, Result.getValue(1));
19509 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19510 Regs64bit ? X86::RDX : X86::EDX,
19511 HalfT, cpOutL.getValue(2));
19512 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19514 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19515 MVT::i32, cpOutH.getValue(2));
19517 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19518 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19519 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19521 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19522 Results.push_back(Success);
19523 Results.push_back(EFLAGS.getValue(1));
19526 case ISD::ATOMIC_SWAP:
19527 case ISD::ATOMIC_LOAD_ADD:
19528 case ISD::ATOMIC_LOAD_SUB:
19529 case ISD::ATOMIC_LOAD_AND:
19530 case ISD::ATOMIC_LOAD_OR:
19531 case ISD::ATOMIC_LOAD_XOR:
19532 case ISD::ATOMIC_LOAD_NAND:
19533 case ISD::ATOMIC_LOAD_MIN:
19534 case ISD::ATOMIC_LOAD_MAX:
19535 case ISD::ATOMIC_LOAD_UMIN:
19536 case ISD::ATOMIC_LOAD_UMAX:
19537 case ISD::ATOMIC_LOAD: {
19538 // Delegate to generic TypeLegalization. Situations we can really handle
19539 // should have already been dealt with by AtomicExpandPass.cpp.
19542 case ISD::BITCAST: {
19543 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19544 EVT DstVT = N->getValueType(0);
19545 EVT SrcVT = N->getOperand(0)->getValueType(0);
19547 if (SrcVT != MVT::f64 ||
19548 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19551 unsigned NumElts = DstVT.getVectorNumElements();
19552 EVT SVT = DstVT.getVectorElementType();
19553 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19554 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19555 MVT::v2f64, N->getOperand(0));
19556 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19558 if (ExperimentalVectorWideningLegalization) {
19559 // If we are legalizing vectors by widening, we already have the desired
19560 // legal vector type, just return it.
19561 Results.push_back(ToVecInt);
19565 SmallVector<SDValue, 8> Elts;
19566 for (unsigned i = 0, e = NumElts; i != e; ++i)
19567 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19568 ToVecInt, DAG.getIntPtrConstant(i)));
19570 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19575 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19577 default: return nullptr;
19578 case X86ISD::BSF: return "X86ISD::BSF";
19579 case X86ISD::BSR: return "X86ISD::BSR";
19580 case X86ISD::SHLD: return "X86ISD::SHLD";
19581 case X86ISD::SHRD: return "X86ISD::SHRD";
19582 case X86ISD::FAND: return "X86ISD::FAND";
19583 case X86ISD::FANDN: return "X86ISD::FANDN";
19584 case X86ISD::FOR: return "X86ISD::FOR";
19585 case X86ISD::FXOR: return "X86ISD::FXOR";
19586 case X86ISD::FSRL: return "X86ISD::FSRL";
19587 case X86ISD::FILD: return "X86ISD::FILD";
19588 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19589 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19590 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19591 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19592 case X86ISD::FLD: return "X86ISD::FLD";
19593 case X86ISD::FST: return "X86ISD::FST";
19594 case X86ISD::CALL: return "X86ISD::CALL";
19595 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19596 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19597 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19598 case X86ISD::BT: return "X86ISD::BT";
19599 case X86ISD::CMP: return "X86ISD::CMP";
19600 case X86ISD::COMI: return "X86ISD::COMI";
19601 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19602 case X86ISD::CMPM: return "X86ISD::CMPM";
19603 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19604 case X86ISD::SETCC: return "X86ISD::SETCC";
19605 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19606 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19607 case X86ISD::CMOV: return "X86ISD::CMOV";
19608 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19609 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19610 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19611 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19612 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19613 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19614 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19615 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19616 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19617 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19618 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19619 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19620 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19621 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19622 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19623 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19624 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19625 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19626 case X86ISD::HADD: return "X86ISD::HADD";
19627 case X86ISD::HSUB: return "X86ISD::HSUB";
19628 case X86ISD::FHADD: return "X86ISD::FHADD";
19629 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19630 case X86ISD::UMAX: return "X86ISD::UMAX";
19631 case X86ISD::UMIN: return "X86ISD::UMIN";
19632 case X86ISD::SMAX: return "X86ISD::SMAX";
19633 case X86ISD::SMIN: return "X86ISD::SMIN";
19634 case X86ISD::FMAX: return "X86ISD::FMAX";
19635 case X86ISD::FMIN: return "X86ISD::FMIN";
19636 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19637 case X86ISD::FMINC: return "X86ISD::FMINC";
19638 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19639 case X86ISD::FRCP: return "X86ISD::FRCP";
19640 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19641 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19642 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19643 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19644 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19645 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19646 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19647 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19648 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19649 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19650 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19651 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19652 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19653 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19654 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19655 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19656 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19657 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19658 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19659 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19660 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19661 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19662 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19663 case X86ISD::VSHL: return "X86ISD::VSHL";
19664 case X86ISD::VSRL: return "X86ISD::VSRL";
19665 case X86ISD::VSRA: return "X86ISD::VSRA";
19666 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19667 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19668 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19669 case X86ISD::CMPP: return "X86ISD::CMPP";
19670 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19671 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19672 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19673 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19674 case X86ISD::ADD: return "X86ISD::ADD";
19675 case X86ISD::SUB: return "X86ISD::SUB";
19676 case X86ISD::ADC: return "X86ISD::ADC";
19677 case X86ISD::SBB: return "X86ISD::SBB";
19678 case X86ISD::SMUL: return "X86ISD::SMUL";
19679 case X86ISD::UMUL: return "X86ISD::UMUL";
19680 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19681 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19682 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19683 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19684 case X86ISD::INC: return "X86ISD::INC";
19685 case X86ISD::DEC: return "X86ISD::DEC";
19686 case X86ISD::OR: return "X86ISD::OR";
19687 case X86ISD::XOR: return "X86ISD::XOR";
19688 case X86ISD::AND: return "X86ISD::AND";
19689 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19690 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19691 case X86ISD::PTEST: return "X86ISD::PTEST";
19692 case X86ISD::TESTP: return "X86ISD::TESTP";
19693 case X86ISD::TESTM: return "X86ISD::TESTM";
19694 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19695 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19696 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19697 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19698 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19699 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19700 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19701 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19702 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19703 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19704 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19705 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19706 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19707 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19708 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19709 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19710 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19711 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19712 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19713 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19714 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19715 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19716 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19717 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19718 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19719 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19720 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19721 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19722 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19723 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19724 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19725 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19726 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19727 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19728 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19729 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19730 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19731 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19732 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19733 case X86ISD::SAHF: return "X86ISD::SAHF";
19734 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19735 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19736 case X86ISD::FMADD: return "X86ISD::FMADD";
19737 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19738 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19739 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19740 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19741 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19742 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19743 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19744 case X86ISD::XTEST: return "X86ISD::XTEST";
19748 // isLegalAddressingMode - Return true if the addressing mode represented
19749 // by AM is legal for this target, for a load/store of the specified type.
19750 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19752 // X86 supports extremely general addressing modes.
19753 CodeModel::Model M = getTargetMachine().getCodeModel();
19754 Reloc::Model R = getTargetMachine().getRelocationModel();
19756 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19757 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19762 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19764 // If a reference to this global requires an extra load, we can't fold it.
19765 if (isGlobalStubReference(GVFlags))
19768 // If BaseGV requires a register for the PIC base, we cannot also have a
19769 // BaseReg specified.
19770 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19773 // If lower 4G is not available, then we must use rip-relative addressing.
19774 if ((M != CodeModel::Small || R != Reloc::Static) &&
19775 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19779 switch (AM.Scale) {
19785 // These scales always work.
19790 // These scales are formed with basereg+scalereg. Only accept if there is
19795 default: // Other stuff never works.
19802 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19803 unsigned Bits = Ty->getScalarSizeInBits();
19805 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19806 // particularly cheaper than those without.
19810 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19811 // variable shifts just as cheap as scalar ones.
19812 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19815 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19816 // fully general vector.
19820 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19821 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19823 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19824 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19825 return NumBits1 > NumBits2;
19828 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19829 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19832 if (!isTypeLegal(EVT::getEVT(Ty1)))
19835 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19837 // Assuming the caller doesn't have a zeroext or signext return parameter,
19838 // truncation all the way down to i1 is valid.
19842 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19843 return isInt<32>(Imm);
19846 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19847 // Can also use sub to handle negated immediates.
19848 return isInt<32>(Imm);
19851 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19852 if (!VT1.isInteger() || !VT2.isInteger())
19854 unsigned NumBits1 = VT1.getSizeInBits();
19855 unsigned NumBits2 = VT2.getSizeInBits();
19856 return NumBits1 > NumBits2;
19859 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19860 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19861 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19864 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19865 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19866 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19869 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19870 EVT VT1 = Val.getValueType();
19871 if (isZExtFree(VT1, VT2))
19874 if (Val.getOpcode() != ISD::LOAD)
19877 if (!VT1.isSimple() || !VT1.isInteger() ||
19878 !VT2.isSimple() || !VT2.isInteger())
19881 switch (VT1.getSimpleVT().SimpleTy) {
19886 // X86 has 8, 16, and 32-bit zero-extending loads.
19894 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19895 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19898 VT = VT.getScalarType();
19900 if (!VT.isSimple())
19903 switch (VT.getSimpleVT().SimpleTy) {
19914 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19915 // i16 instructions are longer (0x66 prefix) and potentially slower.
19916 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19919 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19920 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19921 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19922 /// are assumed to be legal.
19924 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19926 if (!VT.isSimple())
19929 MVT SVT = VT.getSimpleVT();
19931 // Very little shuffling can be done for 64-bit vectors right now.
19932 if (VT.getSizeInBits() == 64)
19935 // If this is a single-input shuffle with no 128 bit lane crossings we can
19936 // lower it into pshufb.
19937 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19938 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19939 bool isLegal = true;
19940 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19941 if (M[I] >= (int)SVT.getVectorNumElements() ||
19942 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19951 // FIXME: blends, shifts.
19952 return (SVT.getVectorNumElements() == 2 ||
19953 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19954 isMOVLMask(M, SVT) ||
19955 isMOVHLPSMask(M, SVT) ||
19956 isSHUFPMask(M, SVT) ||
19957 isSHUFPMask(M, SVT, /* Commuted */ true) ||
19958 isPSHUFDMask(M, SVT) ||
19959 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
19960 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19961 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19962 isPALIGNRMask(M, SVT, Subtarget) ||
19963 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19964 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19965 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19966 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19967 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19968 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19972 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19974 if (!VT.isSimple())
19977 MVT SVT = VT.getSimpleVT();
19978 unsigned NumElts = SVT.getVectorNumElements();
19979 // FIXME: This collection of masks seems suspect.
19982 if (NumElts == 4 && SVT.is128BitVector()) {
19983 return (isMOVLMask(Mask, SVT) ||
19984 isCommutedMOVLMask(Mask, SVT, true) ||
19985 isSHUFPMask(Mask, SVT) ||
19986 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19987 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19988 Subtarget->hasInt256()));
19993 //===----------------------------------------------------------------------===//
19994 // X86 Scheduler Hooks
19995 //===----------------------------------------------------------------------===//
19997 /// Utility function to emit xbegin specifying the start of an RTM region.
19998 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19999 const TargetInstrInfo *TII) {
20000 DebugLoc DL = MI->getDebugLoc();
20002 const BasicBlock *BB = MBB->getBasicBlock();
20003 MachineFunction::iterator I = MBB;
20006 // For the v = xbegin(), we generate
20017 MachineBasicBlock *thisMBB = MBB;
20018 MachineFunction *MF = MBB->getParent();
20019 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20020 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20021 MF->insert(I, mainMBB);
20022 MF->insert(I, sinkMBB);
20024 // Transfer the remainder of BB and its successor edges to sinkMBB.
20025 sinkMBB->splice(sinkMBB->begin(), MBB,
20026 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20027 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20031 // # fallthrough to mainMBB
20032 // # abortion to sinkMBB
20033 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20034 thisMBB->addSuccessor(mainMBB);
20035 thisMBB->addSuccessor(sinkMBB);
20039 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20040 mainMBB->addSuccessor(sinkMBB);
20043 // EAX is live into the sinkMBB
20044 sinkMBB->addLiveIn(X86::EAX);
20045 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20046 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20049 MI->eraseFromParent();
20053 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20054 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20055 // in the .td file.
20056 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20057 const TargetInstrInfo *TII) {
20059 switch (MI->getOpcode()) {
20060 default: llvm_unreachable("illegal opcode!");
20061 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20062 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20063 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20064 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20065 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20066 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20067 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20068 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20071 DebugLoc dl = MI->getDebugLoc();
20072 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20074 unsigned NumArgs = MI->getNumOperands();
20075 for (unsigned i = 1; i < NumArgs; ++i) {
20076 MachineOperand &Op = MI->getOperand(i);
20077 if (!(Op.isReg() && Op.isImplicit()))
20078 MIB.addOperand(Op);
20080 if (MI->hasOneMemOperand())
20081 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20083 BuildMI(*BB, MI, dl,
20084 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20085 .addReg(X86::XMM0);
20087 MI->eraseFromParent();
20091 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20092 // defs in an instruction pattern
20093 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20094 const TargetInstrInfo *TII) {
20096 switch (MI->getOpcode()) {
20097 default: llvm_unreachable("illegal opcode!");
20098 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20099 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20100 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20101 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20102 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20103 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20104 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20105 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20108 DebugLoc dl = MI->getDebugLoc();
20109 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20111 unsigned NumArgs = MI->getNumOperands(); // remove the results
20112 for (unsigned i = 1; i < NumArgs; ++i) {
20113 MachineOperand &Op = MI->getOperand(i);
20114 if (!(Op.isReg() && Op.isImplicit()))
20115 MIB.addOperand(Op);
20117 if (MI->hasOneMemOperand())
20118 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20120 BuildMI(*BB, MI, dl,
20121 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20124 MI->eraseFromParent();
20128 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20129 const TargetInstrInfo *TII,
20130 const X86Subtarget* Subtarget) {
20131 DebugLoc dl = MI->getDebugLoc();
20133 // Address into RAX/EAX, other two args into ECX, EDX.
20134 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20135 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20136 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20137 for (int i = 0; i < X86::AddrNumOperands; ++i)
20138 MIB.addOperand(MI->getOperand(i));
20140 unsigned ValOps = X86::AddrNumOperands;
20141 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20142 .addReg(MI->getOperand(ValOps).getReg());
20143 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20144 .addReg(MI->getOperand(ValOps+1).getReg());
20146 // The instruction doesn't actually take any operands though.
20147 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20149 MI->eraseFromParent(); // The pseudo is gone now.
20153 MachineBasicBlock *
20154 X86TargetLowering::EmitVAARG64WithCustomInserter(
20156 MachineBasicBlock *MBB) const {
20157 // Emit va_arg instruction on X86-64.
20159 // Operands to this pseudo-instruction:
20160 // 0 ) Output : destination address (reg)
20161 // 1-5) Input : va_list address (addr, i64mem)
20162 // 6 ) ArgSize : Size (in bytes) of vararg type
20163 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20164 // 8 ) Align : Alignment of type
20165 // 9 ) EFLAGS (implicit-def)
20167 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20168 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20170 unsigned DestReg = MI->getOperand(0).getReg();
20171 MachineOperand &Base = MI->getOperand(1);
20172 MachineOperand &Scale = MI->getOperand(2);
20173 MachineOperand &Index = MI->getOperand(3);
20174 MachineOperand &Disp = MI->getOperand(4);
20175 MachineOperand &Segment = MI->getOperand(5);
20176 unsigned ArgSize = MI->getOperand(6).getImm();
20177 unsigned ArgMode = MI->getOperand(7).getImm();
20178 unsigned Align = MI->getOperand(8).getImm();
20180 // Memory Reference
20181 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20182 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20183 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20185 // Machine Information
20186 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20187 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20188 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20189 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20190 DebugLoc DL = MI->getDebugLoc();
20192 // struct va_list {
20195 // i64 overflow_area (address)
20196 // i64 reg_save_area (address)
20198 // sizeof(va_list) = 24
20199 // alignment(va_list) = 8
20201 unsigned TotalNumIntRegs = 6;
20202 unsigned TotalNumXMMRegs = 8;
20203 bool UseGPOffset = (ArgMode == 1);
20204 bool UseFPOffset = (ArgMode == 2);
20205 unsigned MaxOffset = TotalNumIntRegs * 8 +
20206 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20208 /* Align ArgSize to a multiple of 8 */
20209 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20210 bool NeedsAlign = (Align > 8);
20212 MachineBasicBlock *thisMBB = MBB;
20213 MachineBasicBlock *overflowMBB;
20214 MachineBasicBlock *offsetMBB;
20215 MachineBasicBlock *endMBB;
20217 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20218 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20219 unsigned OffsetReg = 0;
20221 if (!UseGPOffset && !UseFPOffset) {
20222 // If we only pull from the overflow region, we don't create a branch.
20223 // We don't need to alter control flow.
20224 OffsetDestReg = 0; // unused
20225 OverflowDestReg = DestReg;
20227 offsetMBB = nullptr;
20228 overflowMBB = thisMBB;
20231 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20232 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20233 // If not, pull from overflow_area. (branch to overflowMBB)
20238 // offsetMBB overflowMBB
20243 // Registers for the PHI in endMBB
20244 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20245 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20247 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20248 MachineFunction *MF = MBB->getParent();
20249 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20250 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20251 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20253 MachineFunction::iterator MBBIter = MBB;
20256 // Insert the new basic blocks
20257 MF->insert(MBBIter, offsetMBB);
20258 MF->insert(MBBIter, overflowMBB);
20259 MF->insert(MBBIter, endMBB);
20261 // Transfer the remainder of MBB and its successor edges to endMBB.
20262 endMBB->splice(endMBB->begin(), thisMBB,
20263 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20264 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20266 // Make offsetMBB and overflowMBB successors of thisMBB
20267 thisMBB->addSuccessor(offsetMBB);
20268 thisMBB->addSuccessor(overflowMBB);
20270 // endMBB is a successor of both offsetMBB and overflowMBB
20271 offsetMBB->addSuccessor(endMBB);
20272 overflowMBB->addSuccessor(endMBB);
20274 // Load the offset value into a register
20275 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20276 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20280 .addDisp(Disp, UseFPOffset ? 4 : 0)
20281 .addOperand(Segment)
20282 .setMemRefs(MMOBegin, MMOEnd);
20284 // Check if there is enough room left to pull this argument.
20285 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20287 .addImm(MaxOffset + 8 - ArgSizeA8);
20289 // Branch to "overflowMBB" if offset >= max
20290 // Fall through to "offsetMBB" otherwise
20291 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20292 .addMBB(overflowMBB);
20295 // In offsetMBB, emit code to use the reg_save_area.
20297 assert(OffsetReg != 0);
20299 // Read the reg_save_area address.
20300 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20301 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20306 .addOperand(Segment)
20307 .setMemRefs(MMOBegin, MMOEnd);
20309 // Zero-extend the offset
20310 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20311 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20314 .addImm(X86::sub_32bit);
20316 // Add the offset to the reg_save_area to get the final address.
20317 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20318 .addReg(OffsetReg64)
20319 .addReg(RegSaveReg);
20321 // Compute the offset for the next argument
20322 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20323 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20325 .addImm(UseFPOffset ? 16 : 8);
20327 // Store it back into the va_list.
20328 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20332 .addDisp(Disp, UseFPOffset ? 4 : 0)
20333 .addOperand(Segment)
20334 .addReg(NextOffsetReg)
20335 .setMemRefs(MMOBegin, MMOEnd);
20338 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20343 // Emit code to use overflow area
20346 // Load the overflow_area address into a register.
20347 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20348 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20353 .addOperand(Segment)
20354 .setMemRefs(MMOBegin, MMOEnd);
20356 // If we need to align it, do so. Otherwise, just copy the address
20357 // to OverflowDestReg.
20359 // Align the overflow address
20360 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20361 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20363 // aligned_addr = (addr + (align-1)) & ~(align-1)
20364 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20365 .addReg(OverflowAddrReg)
20368 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20370 .addImm(~(uint64_t)(Align-1));
20372 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20373 .addReg(OverflowAddrReg);
20376 // Compute the next overflow address after this argument.
20377 // (the overflow address should be kept 8-byte aligned)
20378 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20379 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20380 .addReg(OverflowDestReg)
20381 .addImm(ArgSizeA8);
20383 // Store the new overflow address.
20384 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20389 .addOperand(Segment)
20390 .addReg(NextAddrReg)
20391 .setMemRefs(MMOBegin, MMOEnd);
20393 // If we branched, emit the PHI to the front of endMBB.
20395 BuildMI(*endMBB, endMBB->begin(), DL,
20396 TII->get(X86::PHI), DestReg)
20397 .addReg(OffsetDestReg).addMBB(offsetMBB)
20398 .addReg(OverflowDestReg).addMBB(overflowMBB);
20401 // Erase the pseudo instruction
20402 MI->eraseFromParent();
20407 MachineBasicBlock *
20408 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20410 MachineBasicBlock *MBB) const {
20411 // Emit code to save XMM registers to the stack. The ABI says that the
20412 // number of registers to save is given in %al, so it's theoretically
20413 // possible to do an indirect jump trick to avoid saving all of them,
20414 // however this code takes a simpler approach and just executes all
20415 // of the stores if %al is non-zero. It's less code, and it's probably
20416 // easier on the hardware branch predictor, and stores aren't all that
20417 // expensive anyway.
20419 // Create the new basic blocks. One block contains all the XMM stores,
20420 // and one block is the final destination regardless of whether any
20421 // stores were performed.
20422 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20423 MachineFunction *F = MBB->getParent();
20424 MachineFunction::iterator MBBIter = MBB;
20426 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20427 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20428 F->insert(MBBIter, XMMSaveMBB);
20429 F->insert(MBBIter, EndMBB);
20431 // Transfer the remainder of MBB and its successor edges to EndMBB.
20432 EndMBB->splice(EndMBB->begin(), MBB,
20433 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20434 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20436 // The original block will now fall through to the XMM save block.
20437 MBB->addSuccessor(XMMSaveMBB);
20438 // The XMMSaveMBB will fall through to the end block.
20439 XMMSaveMBB->addSuccessor(EndMBB);
20441 // Now add the instructions.
20442 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20443 DebugLoc DL = MI->getDebugLoc();
20445 unsigned CountReg = MI->getOperand(0).getReg();
20446 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20447 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20449 if (!Subtarget->isTargetWin64()) {
20450 // If %al is 0, branch around the XMM save block.
20451 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20452 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20453 MBB->addSuccessor(EndMBB);
20456 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20457 // that was just emitted, but clearly shouldn't be "saved".
20458 assert((MI->getNumOperands() <= 3 ||
20459 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20460 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20461 && "Expected last argument to be EFLAGS");
20462 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20463 // In the XMM save block, save all the XMM argument registers.
20464 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20465 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20466 MachineMemOperand *MMO =
20467 F->getMachineMemOperand(
20468 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20469 MachineMemOperand::MOStore,
20470 /*Size=*/16, /*Align=*/16);
20471 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20472 .addFrameIndex(RegSaveFrameIndex)
20473 .addImm(/*Scale=*/1)
20474 .addReg(/*IndexReg=*/0)
20475 .addImm(/*Disp=*/Offset)
20476 .addReg(/*Segment=*/0)
20477 .addReg(MI->getOperand(i).getReg())
20478 .addMemOperand(MMO);
20481 MI->eraseFromParent(); // The pseudo instruction is gone now.
20486 // The EFLAGS operand of SelectItr might be missing a kill marker
20487 // because there were multiple uses of EFLAGS, and ISel didn't know
20488 // which to mark. Figure out whether SelectItr should have had a
20489 // kill marker, and set it if it should. Returns the correct kill
20491 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20492 MachineBasicBlock* BB,
20493 const TargetRegisterInfo* TRI) {
20494 // Scan forward through BB for a use/def of EFLAGS.
20495 MachineBasicBlock::iterator miI(std::next(SelectItr));
20496 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20497 const MachineInstr& mi = *miI;
20498 if (mi.readsRegister(X86::EFLAGS))
20500 if (mi.definesRegister(X86::EFLAGS))
20501 break; // Should have kill-flag - update below.
20504 // If we hit the end of the block, check whether EFLAGS is live into a
20506 if (miI == BB->end()) {
20507 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20508 sEnd = BB->succ_end();
20509 sItr != sEnd; ++sItr) {
20510 MachineBasicBlock* succ = *sItr;
20511 if (succ->isLiveIn(X86::EFLAGS))
20516 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20517 // out. SelectMI should have a kill flag on EFLAGS.
20518 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20522 MachineBasicBlock *
20523 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20524 MachineBasicBlock *BB) const {
20525 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20526 DebugLoc DL = MI->getDebugLoc();
20528 // To "insert" a SELECT_CC instruction, we actually have to insert the
20529 // diamond control-flow pattern. The incoming instruction knows the
20530 // destination vreg to set, the condition code register to branch on, the
20531 // true/false values to select between, and a branch opcode to use.
20532 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20533 MachineFunction::iterator It = BB;
20539 // cmpTY ccX, r1, r2
20541 // fallthrough --> copy0MBB
20542 MachineBasicBlock *thisMBB = BB;
20543 MachineFunction *F = BB->getParent();
20544 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20545 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20546 F->insert(It, copy0MBB);
20547 F->insert(It, sinkMBB);
20549 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20550 // live into the sink and copy blocks.
20551 const TargetRegisterInfo *TRI =
20552 BB->getParent()->getSubtarget().getRegisterInfo();
20553 if (!MI->killsRegister(X86::EFLAGS) &&
20554 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20555 copy0MBB->addLiveIn(X86::EFLAGS);
20556 sinkMBB->addLiveIn(X86::EFLAGS);
20559 // Transfer the remainder of BB and its successor edges to sinkMBB.
20560 sinkMBB->splice(sinkMBB->begin(), BB,
20561 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20562 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20564 // Add the true and fallthrough blocks as its successors.
20565 BB->addSuccessor(copy0MBB);
20566 BB->addSuccessor(sinkMBB);
20568 // Create the conditional branch instruction.
20570 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20571 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20574 // %FalseValue = ...
20575 // # fallthrough to sinkMBB
20576 copy0MBB->addSuccessor(sinkMBB);
20579 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20581 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20582 TII->get(X86::PHI), MI->getOperand(0).getReg())
20583 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20584 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20586 MI->eraseFromParent(); // The pseudo instruction is gone now.
20590 MachineBasicBlock *
20591 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20592 MachineBasicBlock *BB) const {
20593 MachineFunction *MF = BB->getParent();
20594 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20595 DebugLoc DL = MI->getDebugLoc();
20596 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20598 assert(MF->shouldSplitStack());
20600 const bool Is64Bit = Subtarget->is64Bit();
20601 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20603 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20604 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20607 // ... [Till the alloca]
20608 // If stacklet is not large enough, jump to mallocMBB
20611 // Allocate by subtracting from RSP
20612 // Jump to continueMBB
20615 // Allocate by call to runtime
20619 // [rest of original BB]
20622 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20623 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20624 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20626 MachineRegisterInfo &MRI = MF->getRegInfo();
20627 const TargetRegisterClass *AddrRegClass =
20628 getRegClassFor(getPointerTy());
20630 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20631 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20632 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20633 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20634 sizeVReg = MI->getOperand(1).getReg(),
20635 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20637 MachineFunction::iterator MBBIter = BB;
20640 MF->insert(MBBIter, bumpMBB);
20641 MF->insert(MBBIter, mallocMBB);
20642 MF->insert(MBBIter, continueMBB);
20644 continueMBB->splice(continueMBB->begin(), BB,
20645 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20646 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20648 // Add code to the main basic block to check if the stack limit has been hit,
20649 // and if so, jump to mallocMBB otherwise to bumpMBB.
20650 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20651 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20652 .addReg(tmpSPVReg).addReg(sizeVReg);
20653 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20654 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20655 .addReg(SPLimitVReg);
20656 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20658 // bumpMBB simply decreases the stack pointer, since we know the current
20659 // stacklet has enough space.
20660 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20661 .addReg(SPLimitVReg);
20662 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20663 .addReg(SPLimitVReg);
20664 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20666 // Calls into a routine in libgcc to allocate more space from the heap.
20667 const uint32_t *RegMask = MF->getTarget()
20668 .getSubtargetImpl()
20669 ->getRegisterInfo()
20670 ->getCallPreservedMask(CallingConv::C);
20672 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20674 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20675 .addExternalSymbol("__morestack_allocate_stack_space")
20676 .addRegMask(RegMask)
20677 .addReg(X86::RDI, RegState::Implicit)
20678 .addReg(X86::RAX, RegState::ImplicitDefine);
20679 } else if (Is64Bit) {
20680 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20682 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20683 .addExternalSymbol("__morestack_allocate_stack_space")
20684 .addRegMask(RegMask)
20685 .addReg(X86::EDI, RegState::Implicit)
20686 .addReg(X86::EAX, RegState::ImplicitDefine);
20688 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20690 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20691 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20692 .addExternalSymbol("__morestack_allocate_stack_space")
20693 .addRegMask(RegMask)
20694 .addReg(X86::EAX, RegState::ImplicitDefine);
20698 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20701 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20702 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20703 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20705 // Set up the CFG correctly.
20706 BB->addSuccessor(bumpMBB);
20707 BB->addSuccessor(mallocMBB);
20708 mallocMBB->addSuccessor(continueMBB);
20709 bumpMBB->addSuccessor(continueMBB);
20711 // Take care of the PHI nodes.
20712 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20713 MI->getOperand(0).getReg())
20714 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20715 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20717 // Delete the original pseudo instruction.
20718 MI->eraseFromParent();
20721 return continueMBB;
20724 MachineBasicBlock *
20725 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20726 MachineBasicBlock *BB) const {
20727 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20728 DebugLoc DL = MI->getDebugLoc();
20730 assert(!Subtarget->isTargetMacho());
20732 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20733 // non-trivial part is impdef of ESP.
20735 if (Subtarget->isTargetWin64()) {
20736 if (Subtarget->isTargetCygMing()) {
20737 // ___chkstk(Mingw64):
20738 // Clobbers R10, R11, RAX and EFLAGS.
20740 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20741 .addExternalSymbol("___chkstk")
20742 .addReg(X86::RAX, RegState::Implicit)
20743 .addReg(X86::RSP, RegState::Implicit)
20744 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20745 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20746 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20748 // __chkstk(MSVCRT): does not update stack pointer.
20749 // Clobbers R10, R11 and EFLAGS.
20750 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20751 .addExternalSymbol("__chkstk")
20752 .addReg(X86::RAX, RegState::Implicit)
20753 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20754 // RAX has the offset to be subtracted from RSP.
20755 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20760 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20761 Subtarget->isTargetWindowsItanium())
20765 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20766 .addExternalSymbol(StackProbeSymbol)
20767 .addReg(X86::EAX, RegState::Implicit)
20768 .addReg(X86::ESP, RegState::Implicit)
20769 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20770 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20771 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20774 MI->eraseFromParent(); // The pseudo instruction is gone now.
20778 MachineBasicBlock *
20779 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20780 MachineBasicBlock *BB) const {
20781 // This is pretty easy. We're taking the value that we received from
20782 // our load from the relocation, sticking it in either RDI (x86-64)
20783 // or EAX and doing an indirect call. The return value will then
20784 // be in the normal return register.
20785 MachineFunction *F = BB->getParent();
20786 const X86InstrInfo *TII =
20787 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20788 DebugLoc DL = MI->getDebugLoc();
20790 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20791 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20793 // Get a register mask for the lowered call.
20794 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20795 // proper register mask.
20796 const uint32_t *RegMask = F->getTarget()
20797 .getSubtargetImpl()
20798 ->getRegisterInfo()
20799 ->getCallPreservedMask(CallingConv::C);
20800 if (Subtarget->is64Bit()) {
20801 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20802 TII->get(X86::MOV64rm), X86::RDI)
20804 .addImm(0).addReg(0)
20805 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20806 MI->getOperand(3).getTargetFlags())
20808 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20809 addDirectMem(MIB, X86::RDI);
20810 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20811 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20812 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20813 TII->get(X86::MOV32rm), X86::EAX)
20815 .addImm(0).addReg(0)
20816 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20817 MI->getOperand(3).getTargetFlags())
20819 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20820 addDirectMem(MIB, X86::EAX);
20821 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20823 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20824 TII->get(X86::MOV32rm), X86::EAX)
20825 .addReg(TII->getGlobalBaseReg(F))
20826 .addImm(0).addReg(0)
20827 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20828 MI->getOperand(3).getTargetFlags())
20830 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20831 addDirectMem(MIB, X86::EAX);
20832 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20835 MI->eraseFromParent(); // The pseudo instruction is gone now.
20839 MachineBasicBlock *
20840 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20841 MachineBasicBlock *MBB) const {
20842 DebugLoc DL = MI->getDebugLoc();
20843 MachineFunction *MF = MBB->getParent();
20844 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20845 MachineRegisterInfo &MRI = MF->getRegInfo();
20847 const BasicBlock *BB = MBB->getBasicBlock();
20848 MachineFunction::iterator I = MBB;
20851 // Memory Reference
20852 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20853 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20856 unsigned MemOpndSlot = 0;
20858 unsigned CurOp = 0;
20860 DstReg = MI->getOperand(CurOp++).getReg();
20861 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20862 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20863 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20864 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20866 MemOpndSlot = CurOp;
20868 MVT PVT = getPointerTy();
20869 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20870 "Invalid Pointer Size!");
20872 // For v = setjmp(buf), we generate
20875 // buf[LabelOffset] = restoreMBB
20876 // SjLjSetup restoreMBB
20882 // v = phi(main, restore)
20887 MachineBasicBlock *thisMBB = MBB;
20888 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20889 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20890 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20891 MF->insert(I, mainMBB);
20892 MF->insert(I, sinkMBB);
20893 MF->push_back(restoreMBB);
20895 MachineInstrBuilder MIB;
20897 // Transfer the remainder of BB and its successor edges to sinkMBB.
20898 sinkMBB->splice(sinkMBB->begin(), MBB,
20899 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20900 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20903 unsigned PtrStoreOpc = 0;
20904 unsigned LabelReg = 0;
20905 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20906 Reloc::Model RM = MF->getTarget().getRelocationModel();
20907 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20908 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20910 // Prepare IP either in reg or imm.
20911 if (!UseImmLabel) {
20912 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20913 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20914 LabelReg = MRI.createVirtualRegister(PtrRC);
20915 if (Subtarget->is64Bit()) {
20916 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20920 .addMBB(restoreMBB)
20923 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20924 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20925 .addReg(XII->getGlobalBaseReg(MF))
20928 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20932 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20934 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20935 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20936 if (i == X86::AddrDisp)
20937 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20939 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20942 MIB.addReg(LabelReg);
20944 MIB.addMBB(restoreMBB);
20945 MIB.setMemRefs(MMOBegin, MMOEnd);
20947 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20948 .addMBB(restoreMBB);
20950 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20951 MF->getSubtarget().getRegisterInfo());
20952 MIB.addRegMask(RegInfo->getNoPreservedMask());
20953 thisMBB->addSuccessor(mainMBB);
20954 thisMBB->addSuccessor(restoreMBB);
20958 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20959 mainMBB->addSuccessor(sinkMBB);
20962 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20963 TII->get(X86::PHI), DstReg)
20964 .addReg(mainDstReg).addMBB(mainMBB)
20965 .addReg(restoreDstReg).addMBB(restoreMBB);
20968 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20969 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20970 restoreMBB->addSuccessor(sinkMBB);
20972 MI->eraseFromParent();
20976 MachineBasicBlock *
20977 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20978 MachineBasicBlock *MBB) const {
20979 DebugLoc DL = MI->getDebugLoc();
20980 MachineFunction *MF = MBB->getParent();
20981 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20982 MachineRegisterInfo &MRI = MF->getRegInfo();
20984 // Memory Reference
20985 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20986 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20988 MVT PVT = getPointerTy();
20989 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20990 "Invalid Pointer Size!");
20992 const TargetRegisterClass *RC =
20993 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20994 unsigned Tmp = MRI.createVirtualRegister(RC);
20995 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20996 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20997 MF->getSubtarget().getRegisterInfo());
20998 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20999 unsigned SP = RegInfo->getStackRegister();
21001 MachineInstrBuilder MIB;
21003 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21004 const int64_t SPOffset = 2 * PVT.getStoreSize();
21006 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21007 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21010 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21011 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21012 MIB.addOperand(MI->getOperand(i));
21013 MIB.setMemRefs(MMOBegin, MMOEnd);
21015 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21016 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21017 if (i == X86::AddrDisp)
21018 MIB.addDisp(MI->getOperand(i), LabelOffset);
21020 MIB.addOperand(MI->getOperand(i));
21022 MIB.setMemRefs(MMOBegin, MMOEnd);
21024 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21025 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21026 if (i == X86::AddrDisp)
21027 MIB.addDisp(MI->getOperand(i), SPOffset);
21029 MIB.addOperand(MI->getOperand(i));
21031 MIB.setMemRefs(MMOBegin, MMOEnd);
21033 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21035 MI->eraseFromParent();
21039 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21040 // accumulator loops. Writing back to the accumulator allows the coalescer
21041 // to remove extra copies in the loop.
21042 MachineBasicBlock *
21043 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21044 MachineBasicBlock *MBB) const {
21045 MachineOperand &AddendOp = MI->getOperand(3);
21047 // Bail out early if the addend isn't a register - we can't switch these.
21048 if (!AddendOp.isReg())
21051 MachineFunction &MF = *MBB->getParent();
21052 MachineRegisterInfo &MRI = MF.getRegInfo();
21054 // Check whether the addend is defined by a PHI:
21055 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21056 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21057 if (!AddendDef.isPHI())
21060 // Look for the following pattern:
21062 // %addend = phi [%entry, 0], [%loop, %result]
21064 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21068 // %addend = phi [%entry, 0], [%loop, %result]
21070 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21072 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21073 assert(AddendDef.getOperand(i).isReg());
21074 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21075 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21076 if (&PHISrcInst == MI) {
21077 // Found a matching instruction.
21078 unsigned NewFMAOpc = 0;
21079 switch (MI->getOpcode()) {
21080 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21081 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21082 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21083 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21084 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21085 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21086 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21087 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21088 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21089 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21090 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21091 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21092 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21093 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21094 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21095 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21096 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21097 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21098 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21099 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21101 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21102 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21103 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21104 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21105 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21106 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21107 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21108 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21109 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21110 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21111 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21112 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21113 default: llvm_unreachable("Unrecognized FMA variant.");
21116 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21117 MachineInstrBuilder MIB =
21118 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21119 .addOperand(MI->getOperand(0))
21120 .addOperand(MI->getOperand(3))
21121 .addOperand(MI->getOperand(2))
21122 .addOperand(MI->getOperand(1));
21123 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21124 MI->eraseFromParent();
21131 MachineBasicBlock *
21132 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21133 MachineBasicBlock *BB) const {
21134 switch (MI->getOpcode()) {
21135 default: llvm_unreachable("Unexpected instr type to insert");
21136 case X86::TAILJMPd64:
21137 case X86::TAILJMPr64:
21138 case X86::TAILJMPm64:
21139 llvm_unreachable("TAILJMP64 would not be touched here.");
21140 case X86::TCRETURNdi64:
21141 case X86::TCRETURNri64:
21142 case X86::TCRETURNmi64:
21144 case X86::WIN_ALLOCA:
21145 return EmitLoweredWinAlloca(MI, BB);
21146 case X86::SEG_ALLOCA_32:
21147 case X86::SEG_ALLOCA_64:
21148 return EmitLoweredSegAlloca(MI, BB);
21149 case X86::TLSCall_32:
21150 case X86::TLSCall_64:
21151 return EmitLoweredTLSCall(MI, BB);
21152 case X86::CMOV_GR8:
21153 case X86::CMOV_FR32:
21154 case X86::CMOV_FR64:
21155 case X86::CMOV_V4F32:
21156 case X86::CMOV_V2F64:
21157 case X86::CMOV_V2I64:
21158 case X86::CMOV_V8F32:
21159 case X86::CMOV_V4F64:
21160 case X86::CMOV_V4I64:
21161 case X86::CMOV_V16F32:
21162 case X86::CMOV_V8F64:
21163 case X86::CMOV_V8I64:
21164 case X86::CMOV_GR16:
21165 case X86::CMOV_GR32:
21166 case X86::CMOV_RFP32:
21167 case X86::CMOV_RFP64:
21168 case X86::CMOV_RFP80:
21169 return EmitLoweredSelect(MI, BB);
21171 case X86::FP32_TO_INT16_IN_MEM:
21172 case X86::FP32_TO_INT32_IN_MEM:
21173 case X86::FP32_TO_INT64_IN_MEM:
21174 case X86::FP64_TO_INT16_IN_MEM:
21175 case X86::FP64_TO_INT32_IN_MEM:
21176 case X86::FP64_TO_INT64_IN_MEM:
21177 case X86::FP80_TO_INT16_IN_MEM:
21178 case X86::FP80_TO_INT32_IN_MEM:
21179 case X86::FP80_TO_INT64_IN_MEM: {
21180 MachineFunction *F = BB->getParent();
21181 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21182 DebugLoc DL = MI->getDebugLoc();
21184 // Change the floating point control register to use "round towards zero"
21185 // mode when truncating to an integer value.
21186 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21187 addFrameReference(BuildMI(*BB, MI, DL,
21188 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21190 // Load the old value of the high byte of the control word...
21192 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21193 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21196 // Set the high part to be round to zero...
21197 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21200 // Reload the modified control word now...
21201 addFrameReference(BuildMI(*BB, MI, DL,
21202 TII->get(X86::FLDCW16m)), CWFrameIdx);
21204 // Restore the memory image of control word to original value
21205 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21208 // Get the X86 opcode to use.
21210 switch (MI->getOpcode()) {
21211 default: llvm_unreachable("illegal opcode!");
21212 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21213 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21214 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21215 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21216 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21217 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21218 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21219 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21220 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21224 MachineOperand &Op = MI->getOperand(0);
21226 AM.BaseType = X86AddressMode::RegBase;
21227 AM.Base.Reg = Op.getReg();
21229 AM.BaseType = X86AddressMode::FrameIndexBase;
21230 AM.Base.FrameIndex = Op.getIndex();
21232 Op = MI->getOperand(1);
21234 AM.Scale = Op.getImm();
21235 Op = MI->getOperand(2);
21237 AM.IndexReg = Op.getImm();
21238 Op = MI->getOperand(3);
21239 if (Op.isGlobal()) {
21240 AM.GV = Op.getGlobal();
21242 AM.Disp = Op.getImm();
21244 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21245 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21247 // Reload the original control word now.
21248 addFrameReference(BuildMI(*BB, MI, DL,
21249 TII->get(X86::FLDCW16m)), CWFrameIdx);
21251 MI->eraseFromParent(); // The pseudo instruction is gone now.
21254 // String/text processing lowering.
21255 case X86::PCMPISTRM128REG:
21256 case X86::VPCMPISTRM128REG:
21257 case X86::PCMPISTRM128MEM:
21258 case X86::VPCMPISTRM128MEM:
21259 case X86::PCMPESTRM128REG:
21260 case X86::VPCMPESTRM128REG:
21261 case X86::PCMPESTRM128MEM:
21262 case X86::VPCMPESTRM128MEM:
21263 assert(Subtarget->hasSSE42() &&
21264 "Target must have SSE4.2 or AVX features enabled");
21265 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21267 // String/text processing lowering.
21268 case X86::PCMPISTRIREG:
21269 case X86::VPCMPISTRIREG:
21270 case X86::PCMPISTRIMEM:
21271 case X86::VPCMPISTRIMEM:
21272 case X86::PCMPESTRIREG:
21273 case X86::VPCMPESTRIREG:
21274 case X86::PCMPESTRIMEM:
21275 case X86::VPCMPESTRIMEM:
21276 assert(Subtarget->hasSSE42() &&
21277 "Target must have SSE4.2 or AVX features enabled");
21278 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21280 // Thread synchronization.
21282 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21287 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21289 case X86::VASTART_SAVE_XMM_REGS:
21290 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21292 case X86::VAARG_64:
21293 return EmitVAARG64WithCustomInserter(MI, BB);
21295 case X86::EH_SjLj_SetJmp32:
21296 case X86::EH_SjLj_SetJmp64:
21297 return emitEHSjLjSetJmp(MI, BB);
21299 case X86::EH_SjLj_LongJmp32:
21300 case X86::EH_SjLj_LongJmp64:
21301 return emitEHSjLjLongJmp(MI, BB);
21303 case TargetOpcode::STACKMAP:
21304 case TargetOpcode::PATCHPOINT:
21305 return emitPatchPoint(MI, BB);
21307 case X86::VFMADDPDr213r:
21308 case X86::VFMADDPSr213r:
21309 case X86::VFMADDSDr213r:
21310 case X86::VFMADDSSr213r:
21311 case X86::VFMSUBPDr213r:
21312 case X86::VFMSUBPSr213r:
21313 case X86::VFMSUBSDr213r:
21314 case X86::VFMSUBSSr213r:
21315 case X86::VFNMADDPDr213r:
21316 case X86::VFNMADDPSr213r:
21317 case X86::VFNMADDSDr213r:
21318 case X86::VFNMADDSSr213r:
21319 case X86::VFNMSUBPDr213r:
21320 case X86::VFNMSUBPSr213r:
21321 case X86::VFNMSUBSDr213r:
21322 case X86::VFNMSUBSSr213r:
21323 case X86::VFMADDSUBPDr213r:
21324 case X86::VFMADDSUBPSr213r:
21325 case X86::VFMSUBADDPDr213r:
21326 case X86::VFMSUBADDPSr213r:
21327 case X86::VFMADDPDr213rY:
21328 case X86::VFMADDPSr213rY:
21329 case X86::VFMSUBPDr213rY:
21330 case X86::VFMSUBPSr213rY:
21331 case X86::VFNMADDPDr213rY:
21332 case X86::VFNMADDPSr213rY:
21333 case X86::VFNMSUBPDr213rY:
21334 case X86::VFNMSUBPSr213rY:
21335 case X86::VFMADDSUBPDr213rY:
21336 case X86::VFMADDSUBPSr213rY:
21337 case X86::VFMSUBADDPDr213rY:
21338 case X86::VFMSUBADDPSr213rY:
21339 return emitFMA3Instr(MI, BB);
21343 //===----------------------------------------------------------------------===//
21344 // X86 Optimization Hooks
21345 //===----------------------------------------------------------------------===//
21347 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21350 const SelectionDAG &DAG,
21351 unsigned Depth) const {
21352 unsigned BitWidth = KnownZero.getBitWidth();
21353 unsigned Opc = Op.getOpcode();
21354 assert((Opc >= ISD::BUILTIN_OP_END ||
21355 Opc == ISD::INTRINSIC_WO_CHAIN ||
21356 Opc == ISD::INTRINSIC_W_CHAIN ||
21357 Opc == ISD::INTRINSIC_VOID) &&
21358 "Should use MaskedValueIsZero if you don't know whether Op"
21359 " is a target node!");
21361 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21375 // These nodes' second result is a boolean.
21376 if (Op.getResNo() == 0)
21379 case X86ISD::SETCC:
21380 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21382 case ISD::INTRINSIC_WO_CHAIN: {
21383 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21384 unsigned NumLoBits = 0;
21387 case Intrinsic::x86_sse_movmsk_ps:
21388 case Intrinsic::x86_avx_movmsk_ps_256:
21389 case Intrinsic::x86_sse2_movmsk_pd:
21390 case Intrinsic::x86_avx_movmsk_pd_256:
21391 case Intrinsic::x86_mmx_pmovmskb:
21392 case Intrinsic::x86_sse2_pmovmskb_128:
21393 case Intrinsic::x86_avx2_pmovmskb: {
21394 // High bits of movmskp{s|d}, pmovmskb are known zero.
21396 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21397 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21398 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21399 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21400 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21401 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21402 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21403 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21405 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21414 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21416 const SelectionDAG &,
21417 unsigned Depth) const {
21418 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21419 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21420 return Op.getValueType().getScalarType().getSizeInBits();
21426 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21427 /// node is a GlobalAddress + offset.
21428 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21429 const GlobalValue* &GA,
21430 int64_t &Offset) const {
21431 if (N->getOpcode() == X86ISD::Wrapper) {
21432 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21433 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21434 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21438 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21441 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21442 /// same as extracting the high 128-bit part of 256-bit vector and then
21443 /// inserting the result into the low part of a new 256-bit vector
21444 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21445 EVT VT = SVOp->getValueType(0);
21446 unsigned NumElems = VT.getVectorNumElements();
21448 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21449 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21450 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21451 SVOp->getMaskElt(j) >= 0)
21457 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21458 /// same as extracting the low 128-bit part of 256-bit vector and then
21459 /// inserting the result into the high part of a new 256-bit vector
21460 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21461 EVT VT = SVOp->getValueType(0);
21462 unsigned NumElems = VT.getVectorNumElements();
21464 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21465 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21466 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21467 SVOp->getMaskElt(j) >= 0)
21473 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21474 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21475 TargetLowering::DAGCombinerInfo &DCI,
21476 const X86Subtarget* Subtarget) {
21478 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21479 SDValue V1 = SVOp->getOperand(0);
21480 SDValue V2 = SVOp->getOperand(1);
21481 EVT VT = SVOp->getValueType(0);
21482 unsigned NumElems = VT.getVectorNumElements();
21484 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21485 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21489 // V UNDEF BUILD_VECTOR UNDEF
21491 // CONCAT_VECTOR CONCAT_VECTOR
21494 // RESULT: V + zero extended
21496 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21497 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21498 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21501 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21504 // To match the shuffle mask, the first half of the mask should
21505 // be exactly the first vector, and all the rest a splat with the
21506 // first element of the second one.
21507 for (unsigned i = 0; i != NumElems/2; ++i)
21508 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21509 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21512 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21513 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21514 if (Ld->hasNUsesOfValue(1, 0)) {
21515 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21516 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21518 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21520 Ld->getPointerInfo(),
21521 Ld->getAlignment(),
21522 false/*isVolatile*/, true/*ReadMem*/,
21523 false/*WriteMem*/);
21525 // Make sure the newly-created LOAD is in the same position as Ld in
21526 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21527 // and update uses of Ld's output chain to use the TokenFactor.
21528 if (Ld->hasAnyUseOfValue(1)) {
21529 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21530 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21531 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21532 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21533 SDValue(ResNode.getNode(), 1));
21536 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21540 // Emit a zeroed vector and insert the desired subvector on its
21542 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21543 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21544 return DCI.CombineTo(N, InsV);
21547 //===--------------------------------------------------------------------===//
21548 // Combine some shuffles into subvector extracts and inserts:
21551 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21552 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21553 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21554 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21555 return DCI.CombineTo(N, InsV);
21558 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21559 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21560 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21561 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21562 return DCI.CombineTo(N, InsV);
21568 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21571 /// This is the leaf of the recursive combinine below. When we have found some
21572 /// chain of single-use x86 shuffle instructions and accumulated the combined
21573 /// shuffle mask represented by them, this will try to pattern match that mask
21574 /// into either a single instruction if there is a special purpose instruction
21575 /// for this operation, or into a PSHUFB instruction which is a fully general
21576 /// instruction but should only be used to replace chains over a certain depth.
21577 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21578 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21579 TargetLowering::DAGCombinerInfo &DCI,
21580 const X86Subtarget *Subtarget) {
21581 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21583 // Find the operand that enters the chain. Note that multiple uses are OK
21584 // here, we're not going to remove the operand we find.
21585 SDValue Input = Op.getOperand(0);
21586 while (Input.getOpcode() == ISD::BITCAST)
21587 Input = Input.getOperand(0);
21589 MVT VT = Input.getSimpleValueType();
21590 MVT RootVT = Root.getSimpleValueType();
21593 // Just remove no-op shuffle masks.
21594 if (Mask.size() == 1) {
21595 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21600 // Use the float domain if the operand type is a floating point type.
21601 bool FloatDomain = VT.isFloatingPoint();
21603 // For floating point shuffles, we don't have free copies in the shuffle
21604 // instructions or the ability to load as part of the instruction, so
21605 // canonicalize their shuffles to UNPCK or MOV variants.
21607 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21608 // vectors because it can have a load folded into it that UNPCK cannot. This
21609 // doesn't preclude something switching to the shorter encoding post-RA.
21611 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21612 bool Lo = Mask.equals(0, 0);
21615 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21616 // is no slower than UNPCKLPD but has the option to fold the input operand
21617 // into even an unaligned memory load.
21618 if (Lo && Subtarget->hasSSE3()) {
21619 Shuffle = X86ISD::MOVDDUP;
21620 ShuffleVT = MVT::v2f64;
21622 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21623 // than the UNPCK variants.
21624 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21625 ShuffleVT = MVT::v4f32;
21627 if (Depth == 1 && Root->getOpcode() == Shuffle)
21628 return false; // Nothing to do!
21629 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21630 DCI.AddToWorklist(Op.getNode());
21631 if (Shuffle == X86ISD::MOVDDUP)
21632 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21634 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21635 DCI.AddToWorklist(Op.getNode());
21636 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21640 if (Subtarget->hasSSE3() &&
21641 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21642 bool Lo = Mask.equals(0, 0, 2, 2);
21643 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21644 MVT ShuffleVT = MVT::v4f32;
21645 if (Depth == 1 && Root->getOpcode() == Shuffle)
21646 return false; // Nothing to do!
21647 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21648 DCI.AddToWorklist(Op.getNode());
21649 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21650 DCI.AddToWorklist(Op.getNode());
21651 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21655 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21656 bool Lo = Mask.equals(0, 0, 1, 1);
21657 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21658 MVT ShuffleVT = MVT::v4f32;
21659 if (Depth == 1 && Root->getOpcode() == Shuffle)
21660 return false; // Nothing to do!
21661 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21662 DCI.AddToWorklist(Op.getNode());
21663 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21664 DCI.AddToWorklist(Op.getNode());
21665 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21671 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21672 // variants as none of these have single-instruction variants that are
21673 // superior to the UNPCK formulation.
21674 if (!FloatDomain &&
21675 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21676 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21677 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21678 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21680 bool Lo = Mask[0] == 0;
21681 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21682 if (Depth == 1 && Root->getOpcode() == Shuffle)
21683 return false; // Nothing to do!
21685 switch (Mask.size()) {
21687 ShuffleVT = MVT::v8i16;
21690 ShuffleVT = MVT::v16i8;
21693 llvm_unreachable("Impossible mask size!");
21695 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21696 DCI.AddToWorklist(Op.getNode());
21697 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21698 DCI.AddToWorklist(Op.getNode());
21699 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21704 // Don't try to re-form single instruction chains under any circumstances now
21705 // that we've done encoding canonicalization for them.
21709 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21710 // can replace them with a single PSHUFB instruction profitably. Intel's
21711 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21712 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21713 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21714 SmallVector<SDValue, 16> PSHUFBMask;
21715 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21716 int Ratio = 16 / Mask.size();
21717 for (unsigned i = 0; i < 16; ++i) {
21718 if (Mask[i / Ratio] == SM_SentinelUndef) {
21719 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21722 int M = Mask[i / Ratio] != SM_SentinelZero
21723 ? Ratio * Mask[i / Ratio] + i % Ratio
21725 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21727 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21728 DCI.AddToWorklist(Op.getNode());
21729 SDValue PSHUFBMaskOp =
21730 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21731 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21732 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21733 DCI.AddToWorklist(Op.getNode());
21734 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21739 // Failed to find any combines.
21743 /// \brief Fully generic combining of x86 shuffle instructions.
21745 /// This should be the last combine run over the x86 shuffle instructions. Once
21746 /// they have been fully optimized, this will recursively consider all chains
21747 /// of single-use shuffle instructions, build a generic model of the cumulative
21748 /// shuffle operation, and check for simpler instructions which implement this
21749 /// operation. We use this primarily for two purposes:
21751 /// 1) Collapse generic shuffles to specialized single instructions when
21752 /// equivalent. In most cases, this is just an encoding size win, but
21753 /// sometimes we will collapse multiple generic shuffles into a single
21754 /// special-purpose shuffle.
21755 /// 2) Look for sequences of shuffle instructions with 3 or more total
21756 /// instructions, and replace them with the slightly more expensive SSSE3
21757 /// PSHUFB instruction if available. We do this as the last combining step
21758 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21759 /// a suitable short sequence of other instructions. The PHUFB will either
21760 /// use a register or have to read from memory and so is slightly (but only
21761 /// slightly) more expensive than the other shuffle instructions.
21763 /// Because this is inherently a quadratic operation (for each shuffle in
21764 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21765 /// This should never be an issue in practice as the shuffle lowering doesn't
21766 /// produce sequences of more than 8 instructions.
21768 /// FIXME: We will currently miss some cases where the redundant shuffling
21769 /// would simplify under the threshold for PSHUFB formation because of
21770 /// combine-ordering. To fix this, we should do the redundant instruction
21771 /// combining in this recursive walk.
21772 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21773 ArrayRef<int> RootMask,
21774 int Depth, bool HasPSHUFB,
21776 TargetLowering::DAGCombinerInfo &DCI,
21777 const X86Subtarget *Subtarget) {
21778 // Bound the depth of our recursive combine because this is ultimately
21779 // quadratic in nature.
21783 // Directly rip through bitcasts to find the underlying operand.
21784 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21785 Op = Op.getOperand(0);
21787 MVT VT = Op.getSimpleValueType();
21788 if (!VT.isVector())
21789 return false; // Bail if we hit a non-vector.
21790 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21791 // version should be added.
21792 if (VT.getSizeInBits() != 128)
21795 assert(Root.getSimpleValueType().isVector() &&
21796 "Shuffles operate on vector types!");
21797 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21798 "Can only combine shuffles of the same vector register size.");
21800 if (!isTargetShuffle(Op.getOpcode()))
21802 SmallVector<int, 16> OpMask;
21804 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21805 // We only can combine unary shuffles which we can decode the mask for.
21806 if (!HaveMask || !IsUnary)
21809 assert(VT.getVectorNumElements() == OpMask.size() &&
21810 "Different mask size from vector size!");
21811 assert(((RootMask.size() > OpMask.size() &&
21812 RootMask.size() % OpMask.size() == 0) ||
21813 (OpMask.size() > RootMask.size() &&
21814 OpMask.size() % RootMask.size() == 0) ||
21815 OpMask.size() == RootMask.size()) &&
21816 "The smaller number of elements must divide the larger.");
21817 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21818 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21819 assert(((RootRatio == 1 && OpRatio == 1) ||
21820 (RootRatio == 1) != (OpRatio == 1)) &&
21821 "Must not have a ratio for both incoming and op masks!");
21823 SmallVector<int, 16> Mask;
21824 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21826 // Merge this shuffle operation's mask into our accumulated mask. Note that
21827 // this shuffle's mask will be the first applied to the input, followed by the
21828 // root mask to get us all the way to the root value arrangement. The reason
21829 // for this order is that we are recursing up the operation chain.
21830 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21831 int RootIdx = i / RootRatio;
21832 if (RootMask[RootIdx] < 0) {
21833 // This is a zero or undef lane, we're done.
21834 Mask.push_back(RootMask[RootIdx]);
21838 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21839 int OpIdx = RootMaskedIdx / OpRatio;
21840 if (OpMask[OpIdx] < 0) {
21841 // The incoming lanes are zero or undef, it doesn't matter which ones we
21843 Mask.push_back(OpMask[OpIdx]);
21847 // Ok, we have non-zero lanes, map them through.
21848 Mask.push_back(OpMask[OpIdx] * OpRatio +
21849 RootMaskedIdx % OpRatio);
21852 // See if we can recurse into the operand to combine more things.
21853 switch (Op.getOpcode()) {
21854 case X86ISD::PSHUFB:
21856 case X86ISD::PSHUFD:
21857 case X86ISD::PSHUFHW:
21858 case X86ISD::PSHUFLW:
21859 if (Op.getOperand(0).hasOneUse() &&
21860 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21861 HasPSHUFB, DAG, DCI, Subtarget))
21865 case X86ISD::UNPCKL:
21866 case X86ISD::UNPCKH:
21867 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21868 // We can't check for single use, we have to check that this shuffle is the only user.
21869 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21870 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21871 HasPSHUFB, DAG, DCI, Subtarget))
21876 // Minor canonicalization of the accumulated shuffle mask to make it easier
21877 // to match below. All this does is detect masks with squential pairs of
21878 // elements, and shrink them to the half-width mask. It does this in a loop
21879 // so it will reduce the size of the mask to the minimal width mask which
21880 // performs an equivalent shuffle.
21881 SmallVector<int, 16> WidenedMask;
21882 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21883 Mask = std::move(WidenedMask);
21884 WidenedMask.clear();
21887 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21891 /// \brief Get the PSHUF-style mask from PSHUF node.
21893 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21894 /// PSHUF-style masks that can be reused with such instructions.
21895 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21896 SmallVector<int, 4> Mask;
21898 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21902 switch (N.getOpcode()) {
21903 case X86ISD::PSHUFD:
21905 case X86ISD::PSHUFLW:
21908 case X86ISD::PSHUFHW:
21909 Mask.erase(Mask.begin(), Mask.begin() + 4);
21910 for (int &M : Mask)
21914 llvm_unreachable("No valid shuffle instruction found!");
21918 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21920 /// We walk up the chain and look for a combinable shuffle, skipping over
21921 /// shuffles that we could hoist this shuffle's transformation past without
21922 /// altering anything.
21924 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21926 TargetLowering::DAGCombinerInfo &DCI) {
21927 assert(N.getOpcode() == X86ISD::PSHUFD &&
21928 "Called with something other than an x86 128-bit half shuffle!");
21931 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21932 // of the shuffles in the chain so that we can form a fresh chain to replace
21934 SmallVector<SDValue, 8> Chain;
21935 SDValue V = N.getOperand(0);
21936 for (; V.hasOneUse(); V = V.getOperand(0)) {
21937 switch (V.getOpcode()) {
21939 return SDValue(); // Nothing combined!
21942 // Skip bitcasts as we always know the type for the target specific
21946 case X86ISD::PSHUFD:
21947 // Found another dword shuffle.
21950 case X86ISD::PSHUFLW:
21951 // Check that the low words (being shuffled) are the identity in the
21952 // dword shuffle, and the high words are self-contained.
21953 if (Mask[0] != 0 || Mask[1] != 1 ||
21954 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21957 Chain.push_back(V);
21960 case X86ISD::PSHUFHW:
21961 // Check that the high words (being shuffled) are the identity in the
21962 // dword shuffle, and the low words are self-contained.
21963 if (Mask[2] != 2 || Mask[3] != 3 ||
21964 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21967 Chain.push_back(V);
21970 case X86ISD::UNPCKL:
21971 case X86ISD::UNPCKH:
21972 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21973 // shuffle into a preceding word shuffle.
21974 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21977 // Search for a half-shuffle which we can combine with.
21978 unsigned CombineOp =
21979 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21980 if (V.getOperand(0) != V.getOperand(1) ||
21981 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21983 Chain.push_back(V);
21984 V = V.getOperand(0);
21986 switch (V.getOpcode()) {
21988 return SDValue(); // Nothing to combine.
21990 case X86ISD::PSHUFLW:
21991 case X86ISD::PSHUFHW:
21992 if (V.getOpcode() == CombineOp)
21995 Chain.push_back(V);
21999 V = V.getOperand(0);
22003 } while (V.hasOneUse());
22006 // Break out of the loop if we break out of the switch.
22010 if (!V.hasOneUse())
22011 // We fell out of the loop without finding a viable combining instruction.
22014 // Merge this node's mask and our incoming mask.
22015 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22016 for (int &M : Mask)
22018 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22019 getV4X86ShuffleImm8ForMask(Mask, DAG));
22021 // Rebuild the chain around this new shuffle.
22022 while (!Chain.empty()) {
22023 SDValue W = Chain.pop_back_val();
22025 if (V.getValueType() != W.getOperand(0).getValueType())
22026 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22028 switch (W.getOpcode()) {
22030 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22032 case X86ISD::UNPCKL:
22033 case X86ISD::UNPCKH:
22034 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22037 case X86ISD::PSHUFD:
22038 case X86ISD::PSHUFLW:
22039 case X86ISD::PSHUFHW:
22040 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22044 if (V.getValueType() != N.getValueType())
22045 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22047 // Return the new chain to replace N.
22051 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22053 /// We walk up the chain, skipping shuffles of the other half and looking
22054 /// through shuffles which switch halves trying to find a shuffle of the same
22055 /// pair of dwords.
22056 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22058 TargetLowering::DAGCombinerInfo &DCI) {
22060 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22061 "Called with something other than an x86 128-bit half shuffle!");
22063 unsigned CombineOpcode = N.getOpcode();
22065 // Walk up a single-use chain looking for a combinable shuffle.
22066 SDValue V = N.getOperand(0);
22067 for (; V.hasOneUse(); V = V.getOperand(0)) {
22068 switch (V.getOpcode()) {
22070 return false; // Nothing combined!
22073 // Skip bitcasts as we always know the type for the target specific
22077 case X86ISD::PSHUFLW:
22078 case X86ISD::PSHUFHW:
22079 if (V.getOpcode() == CombineOpcode)
22082 // Other-half shuffles are no-ops.
22085 // Break out of the loop if we break out of the switch.
22089 if (!V.hasOneUse())
22090 // We fell out of the loop without finding a viable combining instruction.
22093 // Combine away the bottom node as its shuffle will be accumulated into
22094 // a preceding shuffle.
22095 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22097 // Record the old value.
22100 // Merge this node's mask and our incoming mask (adjusted to account for all
22101 // the pshufd instructions encountered).
22102 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22103 for (int &M : Mask)
22105 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22106 getV4X86ShuffleImm8ForMask(Mask, DAG));
22108 // Check that the shuffles didn't cancel each other out. If not, we need to
22109 // combine to the new one.
22111 // Replace the combinable shuffle with the combined one, updating all users
22112 // so that we re-evaluate the chain here.
22113 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22118 /// \brief Try to combine x86 target specific shuffles.
22119 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22120 TargetLowering::DAGCombinerInfo &DCI,
22121 const X86Subtarget *Subtarget) {
22123 MVT VT = N.getSimpleValueType();
22124 SmallVector<int, 4> Mask;
22126 switch (N.getOpcode()) {
22127 case X86ISD::PSHUFD:
22128 case X86ISD::PSHUFLW:
22129 case X86ISD::PSHUFHW:
22130 Mask = getPSHUFShuffleMask(N);
22131 assert(Mask.size() == 4);
22137 // Nuke no-op shuffles that show up after combining.
22138 if (isNoopShuffleMask(Mask))
22139 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22141 // Look for simplifications involving one or two shuffle instructions.
22142 SDValue V = N.getOperand(0);
22143 switch (N.getOpcode()) {
22146 case X86ISD::PSHUFLW:
22147 case X86ISD::PSHUFHW:
22148 assert(VT == MVT::v8i16);
22151 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22152 return SDValue(); // We combined away this shuffle, so we're done.
22154 // See if this reduces to a PSHUFD which is no more expensive and can
22155 // combine with more operations. Note that it has to at least flip the
22156 // dwords as otherwise it would have been removed as a no-op.
22157 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22158 int DMask[] = {0, 1, 2, 3};
22159 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22160 DMask[DOffset + 0] = DOffset + 1;
22161 DMask[DOffset + 1] = DOffset + 0;
22162 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22163 DCI.AddToWorklist(V.getNode());
22164 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22165 getV4X86ShuffleImm8ForMask(DMask, DAG));
22166 DCI.AddToWorklist(V.getNode());
22167 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22170 // Look for shuffle patterns which can be implemented as a single unpack.
22171 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22172 // only works when we have a PSHUFD followed by two half-shuffles.
22173 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22174 (V.getOpcode() == X86ISD::PSHUFLW ||
22175 V.getOpcode() == X86ISD::PSHUFHW) &&
22176 V.getOpcode() != N.getOpcode() &&
22178 SDValue D = V.getOperand(0);
22179 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22180 D = D.getOperand(0);
22181 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22182 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22183 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22184 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22185 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22187 for (int i = 0; i < 4; ++i) {
22188 WordMask[i + NOffset] = Mask[i] + NOffset;
22189 WordMask[i + VOffset] = VMask[i] + VOffset;
22191 // Map the word mask through the DWord mask.
22193 for (int i = 0; i < 8; ++i)
22194 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22195 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22196 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22197 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22198 std::begin(UnpackLoMask)) ||
22199 std::equal(std::begin(MappedMask), std::end(MappedMask),
22200 std::begin(UnpackHiMask))) {
22201 // We can replace all three shuffles with an unpack.
22202 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22203 DCI.AddToWorklist(V.getNode());
22204 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22206 DL, MVT::v8i16, V, V);
22213 case X86ISD::PSHUFD:
22214 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22223 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22225 /// We combine this directly on the abstract vector shuffle nodes so it is
22226 /// easier to generically match. We also insert dummy vector shuffle nodes for
22227 /// the operands which explicitly discard the lanes which are unused by this
22228 /// operation to try to flow through the rest of the combiner the fact that
22229 /// they're unused.
22230 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22232 EVT VT = N->getValueType(0);
22234 // We only handle target-independent shuffles.
22235 // FIXME: It would be easy and harmless to use the target shuffle mask
22236 // extraction tool to support more.
22237 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22240 auto *SVN = cast<ShuffleVectorSDNode>(N);
22241 ArrayRef<int> Mask = SVN->getMask();
22242 SDValue V1 = N->getOperand(0);
22243 SDValue V2 = N->getOperand(1);
22245 // We require the first shuffle operand to be the SUB node, and the second to
22246 // be the ADD node.
22247 // FIXME: We should support the commuted patterns.
22248 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22251 // If there are other uses of these operations we can't fold them.
22252 if (!V1->hasOneUse() || !V2->hasOneUse())
22255 // Ensure that both operations have the same operands. Note that we can
22256 // commute the FADD operands.
22257 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22258 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22259 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22262 // We're looking for blends between FADD and FSUB nodes. We insist on these
22263 // nodes being lined up in a specific expected pattern.
22264 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22265 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22266 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22269 // Only specific types are legal at this point, assert so we notice if and
22270 // when these change.
22271 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22272 VT == MVT::v4f64) &&
22273 "Unknown vector type encountered!");
22275 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22278 /// PerformShuffleCombine - Performs several different shuffle combines.
22279 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22280 TargetLowering::DAGCombinerInfo &DCI,
22281 const X86Subtarget *Subtarget) {
22283 SDValue N0 = N->getOperand(0);
22284 SDValue N1 = N->getOperand(1);
22285 EVT VT = N->getValueType(0);
22287 // Don't create instructions with illegal types after legalize types has run.
22288 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22289 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22292 // If we have legalized the vector types, look for blends of FADD and FSUB
22293 // nodes that we can fuse into an ADDSUB node.
22294 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22295 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22298 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22299 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22300 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22301 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22303 // During Type Legalization, when promoting illegal vector types,
22304 // the backend might introduce new shuffle dag nodes and bitcasts.
22306 // This code performs the following transformation:
22307 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22308 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22310 // We do this only if both the bitcast and the BINOP dag nodes have
22311 // one use. Also, perform this transformation only if the new binary
22312 // operation is legal. This is to avoid introducing dag nodes that
22313 // potentially need to be further expanded (or custom lowered) into a
22314 // less optimal sequence of dag nodes.
22315 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22316 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22317 N0.getOpcode() == ISD::BITCAST) {
22318 SDValue BC0 = N0.getOperand(0);
22319 EVT SVT = BC0.getValueType();
22320 unsigned Opcode = BC0.getOpcode();
22321 unsigned NumElts = VT.getVectorNumElements();
22323 if (BC0.hasOneUse() && SVT.isVector() &&
22324 SVT.getVectorNumElements() * 2 == NumElts &&
22325 TLI.isOperationLegal(Opcode, VT)) {
22326 bool CanFold = false;
22338 unsigned SVTNumElts = SVT.getVectorNumElements();
22339 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22340 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22341 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22342 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22343 CanFold = SVOp->getMaskElt(i) < 0;
22346 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22347 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22348 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22349 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22354 // Only handle 128 wide vector from here on.
22355 if (!VT.is128BitVector())
22358 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22359 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22360 // consecutive, non-overlapping, and in the right order.
22361 SmallVector<SDValue, 16> Elts;
22362 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22363 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22365 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22369 if (isTargetShuffle(N->getOpcode())) {
22371 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22372 if (Shuffle.getNode())
22375 // Try recursively combining arbitrary sequences of x86 shuffle
22376 // instructions into higher-order shuffles. We do this after combining
22377 // specific PSHUF instruction sequences into their minimal form so that we
22378 // can evaluate how many specialized shuffle instructions are involved in
22379 // a particular chain.
22380 SmallVector<int, 1> NonceMask; // Just a placeholder.
22381 NonceMask.push_back(0);
22382 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22383 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22385 return SDValue(); // This routine will use CombineTo to replace N.
22391 /// PerformTruncateCombine - Converts truncate operation to
22392 /// a sequence of vector shuffle operations.
22393 /// It is possible when we truncate 256-bit vector to 128-bit vector
22394 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22395 TargetLowering::DAGCombinerInfo &DCI,
22396 const X86Subtarget *Subtarget) {
22400 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22401 /// specific shuffle of a load can be folded into a single element load.
22402 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22403 /// shuffles have been custom lowered so we need to handle those here.
22404 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22405 TargetLowering::DAGCombinerInfo &DCI) {
22406 if (DCI.isBeforeLegalizeOps())
22409 SDValue InVec = N->getOperand(0);
22410 SDValue EltNo = N->getOperand(1);
22412 if (!isa<ConstantSDNode>(EltNo))
22415 EVT OriginalVT = InVec.getValueType();
22417 if (InVec.getOpcode() == ISD::BITCAST) {
22418 // Don't duplicate a load with other uses.
22419 if (!InVec.hasOneUse())
22421 EVT BCVT = InVec.getOperand(0).getValueType();
22422 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22424 InVec = InVec.getOperand(0);
22427 EVT CurrentVT = InVec.getValueType();
22429 if (!isTargetShuffle(InVec.getOpcode()))
22432 // Don't duplicate a load with other uses.
22433 if (!InVec.hasOneUse())
22436 SmallVector<int, 16> ShuffleMask;
22438 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22439 ShuffleMask, UnaryShuffle))
22442 // Select the input vector, guarding against out of range extract vector.
22443 unsigned NumElems = CurrentVT.getVectorNumElements();
22444 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22445 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22446 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22447 : InVec.getOperand(1);
22449 // If inputs to shuffle are the same for both ops, then allow 2 uses
22450 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22452 if (LdNode.getOpcode() == ISD::BITCAST) {
22453 // Don't duplicate a load with other uses.
22454 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22457 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22458 LdNode = LdNode.getOperand(0);
22461 if (!ISD::isNormalLoad(LdNode.getNode()))
22464 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22466 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22469 EVT EltVT = N->getValueType(0);
22470 // If there's a bitcast before the shuffle, check if the load type and
22471 // alignment is valid.
22472 unsigned Align = LN0->getAlignment();
22473 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22474 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22475 EltVT.getTypeForEVT(*DAG.getContext()));
22477 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22480 // All checks match so transform back to vector_shuffle so that DAG combiner
22481 // can finish the job
22484 // Create shuffle node taking into account the case that its a unary shuffle
22485 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22486 : InVec.getOperand(1);
22487 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22488 InVec.getOperand(0), Shuffle,
22490 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22491 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22495 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22496 /// generation and convert it from being a bunch of shuffles and extracts
22497 /// to a simple store and scalar loads to extract the elements.
22498 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22499 TargetLowering::DAGCombinerInfo &DCI) {
22500 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22501 if (NewOp.getNode())
22504 SDValue InputVector = N->getOperand(0);
22506 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22507 // from mmx to v2i32 has a single usage.
22508 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22509 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22510 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22511 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22512 N->getValueType(0),
22513 InputVector.getNode()->getOperand(0));
22515 // Only operate on vectors of 4 elements, where the alternative shuffling
22516 // gets to be more expensive.
22517 if (InputVector.getValueType() != MVT::v4i32)
22520 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22521 // single use which is a sign-extend or zero-extend, and all elements are
22523 SmallVector<SDNode *, 4> Uses;
22524 unsigned ExtractedElements = 0;
22525 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22526 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22527 if (UI.getUse().getResNo() != InputVector.getResNo())
22530 SDNode *Extract = *UI;
22531 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22534 if (Extract->getValueType(0) != MVT::i32)
22536 if (!Extract->hasOneUse())
22538 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22539 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22541 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22544 // Record which element was extracted.
22545 ExtractedElements |=
22546 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22548 Uses.push_back(Extract);
22551 // If not all the elements were used, this may not be worthwhile.
22552 if (ExtractedElements != 15)
22555 // Ok, we've now decided to do the transformation.
22556 SDLoc dl(InputVector);
22558 // Store the value to a temporary stack slot.
22559 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22560 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22561 MachinePointerInfo(), false, false, 0);
22563 // Replace each use (extract) with a load of the appropriate element.
22564 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22565 UE = Uses.end(); UI != UE; ++UI) {
22566 SDNode *Extract = *UI;
22568 // cOMpute the element's address.
22569 SDValue Idx = Extract->getOperand(1);
22571 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22572 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22573 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22574 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22576 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22577 StackPtr, OffsetVal);
22579 // Load the scalar.
22580 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22581 ScalarAddr, MachinePointerInfo(),
22582 false, false, false, 0);
22584 // Replace the exact with the load.
22585 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22588 // The replacement was made in place; don't return anything.
22592 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22593 static std::pair<unsigned, bool>
22594 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22595 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22596 if (!VT.isVector())
22597 return std::make_pair(0, false);
22599 bool NeedSplit = false;
22600 switch (VT.getSimpleVT().SimpleTy) {
22601 default: return std::make_pair(0, false);
22605 if (!Subtarget->hasAVX2())
22607 if (!Subtarget->hasAVX())
22608 return std::make_pair(0, false);
22613 if (!Subtarget->hasSSE2())
22614 return std::make_pair(0, false);
22617 // SSE2 has only a small subset of the operations.
22618 bool hasUnsigned = Subtarget->hasSSE41() ||
22619 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22620 bool hasSigned = Subtarget->hasSSE41() ||
22621 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22623 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22626 // Check for x CC y ? x : y.
22627 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22628 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22633 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22636 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22639 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22642 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22644 // Check for x CC y ? y : x -- a min/max with reversed arms.
22645 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22646 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22651 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22654 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22657 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22660 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22664 return std::make_pair(Opc, NeedSplit);
22668 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22669 const X86Subtarget *Subtarget) {
22671 SDValue Cond = N->getOperand(0);
22672 SDValue LHS = N->getOperand(1);
22673 SDValue RHS = N->getOperand(2);
22675 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22676 SDValue CondSrc = Cond->getOperand(0);
22677 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22678 Cond = CondSrc->getOperand(0);
22681 MVT VT = N->getSimpleValueType(0);
22682 MVT EltVT = VT.getVectorElementType();
22683 unsigned NumElems = VT.getVectorNumElements();
22684 // There is no blend with immediate in AVX-512.
22685 if (VT.is512BitVector())
22688 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
22690 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
22693 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22696 // A vselect where all conditions and data are constants can be optimized into
22697 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22698 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22699 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22702 unsigned MaskValue = 0;
22703 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22706 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22707 for (unsigned i = 0; i < NumElems; ++i) {
22708 // Be sure we emit undef where we can.
22709 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22710 ShuffleMask[i] = -1;
22712 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22715 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22718 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22720 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22721 TargetLowering::DAGCombinerInfo &DCI,
22722 const X86Subtarget *Subtarget) {
22724 SDValue Cond = N->getOperand(0);
22725 // Get the LHS/RHS of the select.
22726 SDValue LHS = N->getOperand(1);
22727 SDValue RHS = N->getOperand(2);
22728 EVT VT = LHS.getValueType();
22729 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22731 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22732 // instructions match the semantics of the common C idiom x<y?x:y but not
22733 // x<=y?x:y, because of how they handle negative zero (which can be
22734 // ignored in unsafe-math mode).
22735 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22736 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22737 (Subtarget->hasSSE2() ||
22738 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22739 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22741 unsigned Opcode = 0;
22742 // Check for x CC y ? x : y.
22743 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22744 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22748 // Converting this to a min would handle NaNs incorrectly, and swapping
22749 // the operands would cause it to handle comparisons between positive
22750 // and negative zero incorrectly.
22751 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22752 if (!DAG.getTarget().Options.UnsafeFPMath &&
22753 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22755 std::swap(LHS, RHS);
22757 Opcode = X86ISD::FMIN;
22760 // Converting this to a min would handle comparisons between positive
22761 // and negative zero incorrectly.
22762 if (!DAG.getTarget().Options.UnsafeFPMath &&
22763 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22765 Opcode = X86ISD::FMIN;
22768 // Converting this to a min would handle both negative zeros and NaNs
22769 // incorrectly, but we can swap the operands to fix both.
22770 std::swap(LHS, RHS);
22774 Opcode = X86ISD::FMIN;
22778 // Converting this to a max would handle comparisons between positive
22779 // and negative zero incorrectly.
22780 if (!DAG.getTarget().Options.UnsafeFPMath &&
22781 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22783 Opcode = X86ISD::FMAX;
22786 // Converting this to a max would handle NaNs incorrectly, and swapping
22787 // the operands would cause it to handle comparisons between positive
22788 // and negative zero incorrectly.
22789 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22790 if (!DAG.getTarget().Options.UnsafeFPMath &&
22791 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22793 std::swap(LHS, RHS);
22795 Opcode = X86ISD::FMAX;
22798 // Converting this to a max would handle both negative zeros and NaNs
22799 // incorrectly, but we can swap the operands to fix both.
22800 std::swap(LHS, RHS);
22804 Opcode = X86ISD::FMAX;
22807 // Check for x CC y ? y : x -- a min/max with reversed arms.
22808 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22809 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22813 // Converting this to a min would handle comparisons between positive
22814 // and negative zero incorrectly, and swapping the operands would
22815 // cause it to handle NaNs incorrectly.
22816 if (!DAG.getTarget().Options.UnsafeFPMath &&
22817 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22818 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22820 std::swap(LHS, RHS);
22822 Opcode = X86ISD::FMIN;
22825 // Converting this to a min would handle NaNs incorrectly.
22826 if (!DAG.getTarget().Options.UnsafeFPMath &&
22827 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22829 Opcode = X86ISD::FMIN;
22832 // Converting this to a min would handle both negative zeros and NaNs
22833 // incorrectly, but we can swap the operands to fix both.
22834 std::swap(LHS, RHS);
22838 Opcode = X86ISD::FMIN;
22842 // Converting this to a max would handle NaNs incorrectly.
22843 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22845 Opcode = X86ISD::FMAX;
22848 // Converting this to a max would handle comparisons between positive
22849 // and negative zero incorrectly, and swapping the operands would
22850 // cause it to handle NaNs incorrectly.
22851 if (!DAG.getTarget().Options.UnsafeFPMath &&
22852 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22853 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22855 std::swap(LHS, RHS);
22857 Opcode = X86ISD::FMAX;
22860 // Converting this to a max would handle both negative zeros and NaNs
22861 // incorrectly, but we can swap the operands to fix both.
22862 std::swap(LHS, RHS);
22866 Opcode = X86ISD::FMAX;
22872 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22875 EVT CondVT = Cond.getValueType();
22876 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22877 CondVT.getVectorElementType() == MVT::i1) {
22878 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22879 // lowering on KNL. In this case we convert it to
22880 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22881 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22882 // Since SKX these selects have a proper lowering.
22883 EVT OpVT = LHS.getValueType();
22884 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22885 (OpVT.getVectorElementType() == MVT::i8 ||
22886 OpVT.getVectorElementType() == MVT::i16) &&
22887 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22888 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22889 DCI.AddToWorklist(Cond.getNode());
22890 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22893 // If this is a select between two integer constants, try to do some
22895 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22896 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22897 // Don't do this for crazy integer types.
22898 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22899 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22900 // so that TrueC (the true value) is larger than FalseC.
22901 bool NeedsCondInvert = false;
22903 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22904 // Efficiently invertible.
22905 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22906 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22907 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22908 NeedsCondInvert = true;
22909 std::swap(TrueC, FalseC);
22912 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22913 if (FalseC->getAPIntValue() == 0 &&
22914 TrueC->getAPIntValue().isPowerOf2()) {
22915 if (NeedsCondInvert) // Invert the condition if needed.
22916 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22917 DAG.getConstant(1, Cond.getValueType()));
22919 // Zero extend the condition if needed.
22920 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22922 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22923 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22924 DAG.getConstant(ShAmt, MVT::i8));
22927 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22928 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22929 if (NeedsCondInvert) // Invert the condition if needed.
22930 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22931 DAG.getConstant(1, Cond.getValueType()));
22933 // Zero extend the condition if needed.
22934 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22935 FalseC->getValueType(0), Cond);
22936 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22937 SDValue(FalseC, 0));
22940 // Optimize cases that will turn into an LEA instruction. This requires
22941 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22942 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22943 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22944 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22946 bool isFastMultiplier = false;
22948 switch ((unsigned char)Diff) {
22950 case 1: // result = add base, cond
22951 case 2: // result = lea base( , cond*2)
22952 case 3: // result = lea base(cond, cond*2)
22953 case 4: // result = lea base( , cond*4)
22954 case 5: // result = lea base(cond, cond*4)
22955 case 8: // result = lea base( , cond*8)
22956 case 9: // result = lea base(cond, cond*8)
22957 isFastMultiplier = true;
22962 if (isFastMultiplier) {
22963 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22964 if (NeedsCondInvert) // Invert the condition if needed.
22965 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22966 DAG.getConstant(1, Cond.getValueType()));
22968 // Zero extend the condition if needed.
22969 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22971 // Scale the condition by the difference.
22973 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22974 DAG.getConstant(Diff, Cond.getValueType()));
22976 // Add the base if non-zero.
22977 if (FalseC->getAPIntValue() != 0)
22978 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22979 SDValue(FalseC, 0));
22986 // Canonicalize max and min:
22987 // (x > y) ? x : y -> (x >= y) ? x : y
22988 // (x < y) ? x : y -> (x <= y) ? x : y
22989 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22990 // the need for an extra compare
22991 // against zero. e.g.
22992 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22994 // testl %edi, %edi
22996 // cmovgl %edi, %eax
23000 // cmovsl %eax, %edi
23001 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23002 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23003 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23004 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23009 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23010 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23011 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23012 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23017 // Early exit check
23018 if (!TLI.isTypeLegal(VT))
23021 // Match VSELECTs into subs with unsigned saturation.
23022 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23023 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23024 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23025 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23026 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23028 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23029 // left side invert the predicate to simplify logic below.
23031 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23033 CC = ISD::getSetCCInverse(CC, true);
23034 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23038 if (Other.getNode() && Other->getNumOperands() == 2 &&
23039 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23040 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23041 SDValue CondRHS = Cond->getOperand(1);
23043 // Look for a general sub with unsigned saturation first.
23044 // x >= y ? x-y : 0 --> subus x, y
23045 // x > y ? x-y : 0 --> subus x, y
23046 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23047 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23048 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23050 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23051 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23052 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23053 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23054 // If the RHS is a constant we have to reverse the const
23055 // canonicalization.
23056 // x > C-1 ? x+-C : 0 --> subus x, C
23057 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23058 CondRHSConst->getAPIntValue() ==
23059 (-OpRHSConst->getAPIntValue() - 1))
23060 return DAG.getNode(
23061 X86ISD::SUBUS, DL, VT, OpLHS,
23062 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23064 // Another special case: If C was a sign bit, the sub has been
23065 // canonicalized into a xor.
23066 // FIXME: Would it be better to use computeKnownBits to determine
23067 // whether it's safe to decanonicalize the xor?
23068 // x s< 0 ? x^C : 0 --> subus x, C
23069 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23070 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23071 OpRHSConst->getAPIntValue().isSignBit())
23072 // Note that we have to rebuild the RHS constant here to ensure we
23073 // don't rely on particular values of undef lanes.
23074 return DAG.getNode(
23075 X86ISD::SUBUS, DL, VT, OpLHS,
23076 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23081 // Try to match a min/max vector operation.
23082 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23083 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23084 unsigned Opc = ret.first;
23085 bool NeedSplit = ret.second;
23087 if (Opc && NeedSplit) {
23088 unsigned NumElems = VT.getVectorNumElements();
23089 // Extract the LHS vectors
23090 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23091 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23093 // Extract the RHS vectors
23094 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23095 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23097 // Create min/max for each subvector
23098 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23099 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23101 // Merge the result
23102 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23104 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23107 // Simplify vector selection if condition value type matches vselect
23109 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23110 assert(Cond.getValueType().isVector() &&
23111 "vector select expects a vector selector!");
23113 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23114 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23116 // Try invert the condition if true value is not all 1s and false value
23118 if (!TValIsAllOnes && !FValIsAllZeros &&
23119 // Check if the selector will be produced by CMPP*/PCMP*
23120 Cond.getOpcode() == ISD::SETCC &&
23121 // Check if SETCC has already been promoted
23122 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23123 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23124 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23126 if (TValIsAllZeros || FValIsAllOnes) {
23127 SDValue CC = Cond.getOperand(2);
23128 ISD::CondCode NewCC =
23129 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23130 Cond.getOperand(0).getValueType().isInteger());
23131 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23132 std::swap(LHS, RHS);
23133 TValIsAllOnes = FValIsAllOnes;
23134 FValIsAllZeros = TValIsAllZeros;
23138 if (TValIsAllOnes || FValIsAllZeros) {
23141 if (TValIsAllOnes && FValIsAllZeros)
23143 else if (TValIsAllOnes)
23144 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23145 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23146 else if (FValIsAllZeros)
23147 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23148 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23150 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23154 // Try to fold this VSELECT into a MOVSS/MOVSD
23155 if (N->getOpcode() == ISD::VSELECT &&
23156 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
23157 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
23158 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
23159 bool CanFold = false;
23160 unsigned NumElems = Cond.getNumOperands();
23164 if (isZero(Cond.getOperand(0))) {
23167 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
23168 // fold (vselect <0,-1> -> (movsd A, B)
23169 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
23170 CanFold = isAllOnes(Cond.getOperand(i));
23171 } else if (isAllOnes(Cond.getOperand(0))) {
23175 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
23176 // fold (vselect <-1,0> -> (movsd B, A)
23177 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
23178 CanFold = isZero(Cond.getOperand(i));
23182 if (VT == MVT::v4i32 || VT == MVT::v4f32)
23183 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
23184 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
23187 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
23188 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
23189 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
23190 // (v2i64 (bitcast B)))))
23192 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
23193 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
23194 // (v2f64 (bitcast B)))))
23196 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
23197 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
23198 // (v2i64 (bitcast A)))))
23200 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
23201 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
23202 // (v2f64 (bitcast A)))))
23204 CanFold = (isZero(Cond.getOperand(0)) &&
23205 isZero(Cond.getOperand(1)) &&
23206 isAllOnes(Cond.getOperand(2)) &&
23207 isAllOnes(Cond.getOperand(3)));
23209 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
23210 isAllOnes(Cond.getOperand(1)) &&
23211 isZero(Cond.getOperand(2)) &&
23212 isZero(Cond.getOperand(3))) {
23214 std::swap(LHS, RHS);
23218 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
23219 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
23220 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
23221 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
23223 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
23229 // If we know that this node is legal then we know that it is going to be
23230 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23231 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23232 // to simplify previous instructions.
23233 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23234 !DCI.isBeforeLegalize() &&
23235 // We explicitly check against v8i16 and v16i16 because, although
23236 // they're marked as Custom, they might only be legal when Cond is a
23237 // build_vector of constants. This will be taken care in a later
23239 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23240 VT != MVT::v8i16) &&
23241 // Don't optimize vector of constants. Those are handled by
23242 // the generic code and all the bits must be properly set for
23243 // the generic optimizer.
23244 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23245 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23247 // Don't optimize vector selects that map to mask-registers.
23251 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23252 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23254 APInt KnownZero, KnownOne;
23255 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23256 DCI.isBeforeLegalizeOps());
23257 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23258 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23260 // If we changed the computation somewhere in the DAG, this change
23261 // will affect all users of Cond.
23262 // Make sure it is fine and update all the nodes so that we do not
23263 // use the generic VSELECT anymore. Otherwise, we may perform
23264 // wrong optimizations as we messed up with the actual expectation
23265 // for the vector boolean values.
23266 if (Cond != TLO.Old) {
23267 // Check all uses of that condition operand to check whether it will be
23268 // consumed by non-BLEND instructions, which may depend on all bits are
23270 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23272 if (I->getOpcode() != ISD::VSELECT)
23273 // TODO: Add other opcodes eventually lowered into BLEND.
23276 // Update all the users of the condition, before committing the change,
23277 // so that the VSELECT optimizations that expect the correct vector
23278 // boolean value will not be triggered.
23279 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23281 DAG.ReplaceAllUsesOfValueWith(
23283 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23284 Cond, I->getOperand(1), I->getOperand(2)));
23285 DCI.CommitTargetLoweringOpt(TLO);
23288 // At this point, only Cond is changed. Change the condition
23289 // just for N to keep the opportunity to optimize all other
23290 // users their own way.
23291 DAG.ReplaceAllUsesOfValueWith(
23293 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23294 TLO.New, N->getOperand(1), N->getOperand(2)));
23299 // We should generate an X86ISD::BLENDI from a vselect if its argument
23300 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23301 // constants. This specific pattern gets generated when we split a
23302 // selector for a 512 bit vector in a machine without AVX512 (but with
23303 // 256-bit vectors), during legalization:
23305 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23307 // Iff we find this pattern and the build_vectors are built from
23308 // constants, we translate the vselect into a shuffle_vector that we
23309 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23310 if ((N->getOpcode() == ISD::VSELECT ||
23311 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23312 !DCI.isBeforeLegalize()) {
23313 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23314 if (Shuffle.getNode())
23321 // Check whether a boolean test is testing a boolean value generated by
23322 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23325 // Simplify the following patterns:
23326 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23327 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23328 // to (Op EFLAGS Cond)
23330 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23331 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23332 // to (Op EFLAGS !Cond)
23334 // where Op could be BRCOND or CMOV.
23336 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23337 // Quit if not CMP and SUB with its value result used.
23338 if (Cmp.getOpcode() != X86ISD::CMP &&
23339 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23342 // Quit if not used as a boolean value.
23343 if (CC != X86::COND_E && CC != X86::COND_NE)
23346 // Check CMP operands. One of them should be 0 or 1 and the other should be
23347 // an SetCC or extended from it.
23348 SDValue Op1 = Cmp.getOperand(0);
23349 SDValue Op2 = Cmp.getOperand(1);
23352 const ConstantSDNode* C = nullptr;
23353 bool needOppositeCond = (CC == X86::COND_E);
23354 bool checkAgainstTrue = false; // Is it a comparison against 1?
23356 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23358 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23360 else // Quit if all operands are not constants.
23363 if (C->getZExtValue() == 1) {
23364 needOppositeCond = !needOppositeCond;
23365 checkAgainstTrue = true;
23366 } else if (C->getZExtValue() != 0)
23367 // Quit if the constant is neither 0 or 1.
23370 bool truncatedToBoolWithAnd = false;
23371 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23372 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23373 SetCC.getOpcode() == ISD::TRUNCATE ||
23374 SetCC.getOpcode() == ISD::AND) {
23375 if (SetCC.getOpcode() == ISD::AND) {
23377 ConstantSDNode *CS;
23378 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23379 CS->getZExtValue() == 1)
23381 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23382 CS->getZExtValue() == 1)
23386 SetCC = SetCC.getOperand(OpIdx);
23387 truncatedToBoolWithAnd = true;
23389 SetCC = SetCC.getOperand(0);
23392 switch (SetCC.getOpcode()) {
23393 case X86ISD::SETCC_CARRY:
23394 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23395 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23396 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23397 // truncated to i1 using 'and'.
23398 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23400 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23401 "Invalid use of SETCC_CARRY!");
23403 case X86ISD::SETCC:
23404 // Set the condition code or opposite one if necessary.
23405 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23406 if (needOppositeCond)
23407 CC = X86::GetOppositeBranchCondition(CC);
23408 return SetCC.getOperand(1);
23409 case X86ISD::CMOV: {
23410 // Check whether false/true value has canonical one, i.e. 0 or 1.
23411 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23412 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23413 // Quit if true value is not a constant.
23416 // Quit if false value is not a constant.
23418 SDValue Op = SetCC.getOperand(0);
23419 // Skip 'zext' or 'trunc' node.
23420 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23421 Op.getOpcode() == ISD::TRUNCATE)
23422 Op = Op.getOperand(0);
23423 // A special case for rdrand/rdseed, where 0 is set if false cond is
23425 if ((Op.getOpcode() != X86ISD::RDRAND &&
23426 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23429 // Quit if false value is not the constant 0 or 1.
23430 bool FValIsFalse = true;
23431 if (FVal && FVal->getZExtValue() != 0) {
23432 if (FVal->getZExtValue() != 1)
23434 // If FVal is 1, opposite cond is needed.
23435 needOppositeCond = !needOppositeCond;
23436 FValIsFalse = false;
23438 // Quit if TVal is not the constant opposite of FVal.
23439 if (FValIsFalse && TVal->getZExtValue() != 1)
23441 if (!FValIsFalse && TVal->getZExtValue() != 0)
23443 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23444 if (needOppositeCond)
23445 CC = X86::GetOppositeBranchCondition(CC);
23446 return SetCC.getOperand(3);
23453 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23454 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23455 TargetLowering::DAGCombinerInfo &DCI,
23456 const X86Subtarget *Subtarget) {
23459 // If the flag operand isn't dead, don't touch this CMOV.
23460 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23463 SDValue FalseOp = N->getOperand(0);
23464 SDValue TrueOp = N->getOperand(1);
23465 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23466 SDValue Cond = N->getOperand(3);
23468 if (CC == X86::COND_E || CC == X86::COND_NE) {
23469 switch (Cond.getOpcode()) {
23473 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23474 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23475 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23481 Flags = checkBoolTestSetCCCombine(Cond, CC);
23482 if (Flags.getNode() &&
23483 // Extra check as FCMOV only supports a subset of X86 cond.
23484 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23485 SDValue Ops[] = { FalseOp, TrueOp,
23486 DAG.getConstant(CC, MVT::i8), Flags };
23487 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23490 // If this is a select between two integer constants, try to do some
23491 // optimizations. Note that the operands are ordered the opposite of SELECT
23493 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23494 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23495 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23496 // larger than FalseC (the false value).
23497 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23498 CC = X86::GetOppositeBranchCondition(CC);
23499 std::swap(TrueC, FalseC);
23500 std::swap(TrueOp, FalseOp);
23503 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23504 // This is efficient for any integer data type (including i8/i16) and
23506 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23507 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23508 DAG.getConstant(CC, MVT::i8), Cond);
23510 // Zero extend the condition if needed.
23511 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23513 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23514 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23515 DAG.getConstant(ShAmt, MVT::i8));
23516 if (N->getNumValues() == 2) // Dead flag value?
23517 return DCI.CombineTo(N, Cond, SDValue());
23521 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23522 // for any integer data type, including i8/i16.
23523 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23524 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23525 DAG.getConstant(CC, MVT::i8), Cond);
23527 // Zero extend the condition if needed.
23528 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23529 FalseC->getValueType(0), Cond);
23530 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23531 SDValue(FalseC, 0));
23533 if (N->getNumValues() == 2) // Dead flag value?
23534 return DCI.CombineTo(N, Cond, SDValue());
23538 // Optimize cases that will turn into an LEA instruction. This requires
23539 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23540 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23541 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23542 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23544 bool isFastMultiplier = false;
23546 switch ((unsigned char)Diff) {
23548 case 1: // result = add base, cond
23549 case 2: // result = lea base( , cond*2)
23550 case 3: // result = lea base(cond, cond*2)
23551 case 4: // result = lea base( , cond*4)
23552 case 5: // result = lea base(cond, cond*4)
23553 case 8: // result = lea base( , cond*8)
23554 case 9: // result = lea base(cond, cond*8)
23555 isFastMultiplier = true;
23560 if (isFastMultiplier) {
23561 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23562 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23563 DAG.getConstant(CC, MVT::i8), Cond);
23564 // Zero extend the condition if needed.
23565 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23567 // Scale the condition by the difference.
23569 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23570 DAG.getConstant(Diff, Cond.getValueType()));
23572 // Add the base if non-zero.
23573 if (FalseC->getAPIntValue() != 0)
23574 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23575 SDValue(FalseC, 0));
23576 if (N->getNumValues() == 2) // Dead flag value?
23577 return DCI.CombineTo(N, Cond, SDValue());
23584 // Handle these cases:
23585 // (select (x != c), e, c) -> select (x != c), e, x),
23586 // (select (x == c), c, e) -> select (x == c), x, e)
23587 // where the c is an integer constant, and the "select" is the combination
23588 // of CMOV and CMP.
23590 // The rationale for this change is that the conditional-move from a constant
23591 // needs two instructions, however, conditional-move from a register needs
23592 // only one instruction.
23594 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23595 // some instruction-combining opportunities. This opt needs to be
23596 // postponed as late as possible.
23598 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23599 // the DCI.xxxx conditions are provided to postpone the optimization as
23600 // late as possible.
23602 ConstantSDNode *CmpAgainst = nullptr;
23603 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23604 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23605 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23607 if (CC == X86::COND_NE &&
23608 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23609 CC = X86::GetOppositeBranchCondition(CC);
23610 std::swap(TrueOp, FalseOp);
23613 if (CC == X86::COND_E &&
23614 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23615 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23616 DAG.getConstant(CC, MVT::i8), Cond };
23617 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23625 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23626 const X86Subtarget *Subtarget) {
23627 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23629 default: return SDValue();
23630 // SSE/AVX/AVX2 blend intrinsics.
23631 case Intrinsic::x86_avx2_pblendvb:
23632 case Intrinsic::x86_avx2_pblendw:
23633 case Intrinsic::x86_avx2_pblendd_128:
23634 case Intrinsic::x86_avx2_pblendd_256:
23635 // Don't try to simplify this intrinsic if we don't have AVX2.
23636 if (!Subtarget->hasAVX2())
23639 case Intrinsic::x86_avx_blend_pd_256:
23640 case Intrinsic::x86_avx_blend_ps_256:
23641 case Intrinsic::x86_avx_blendv_pd_256:
23642 case Intrinsic::x86_avx_blendv_ps_256:
23643 // Don't try to simplify this intrinsic if we don't have AVX.
23644 if (!Subtarget->hasAVX())
23647 case Intrinsic::x86_sse41_pblendw:
23648 case Intrinsic::x86_sse41_blendpd:
23649 case Intrinsic::x86_sse41_blendps:
23650 case Intrinsic::x86_sse41_blendvps:
23651 case Intrinsic::x86_sse41_blendvpd:
23652 case Intrinsic::x86_sse41_pblendvb: {
23653 SDValue Op0 = N->getOperand(1);
23654 SDValue Op1 = N->getOperand(2);
23655 SDValue Mask = N->getOperand(3);
23657 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23658 if (!Subtarget->hasSSE41())
23661 // fold (blend A, A, Mask) -> A
23664 // fold (blend A, B, allZeros) -> A
23665 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23667 // fold (blend A, B, allOnes) -> B
23668 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23671 // Simplify the case where the mask is a constant i32 value.
23672 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23673 if (C->isNullValue())
23675 if (C->isAllOnesValue())
23682 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23683 case Intrinsic::x86_sse2_psrai_w:
23684 case Intrinsic::x86_sse2_psrai_d:
23685 case Intrinsic::x86_avx2_psrai_w:
23686 case Intrinsic::x86_avx2_psrai_d:
23687 case Intrinsic::x86_sse2_psra_w:
23688 case Intrinsic::x86_sse2_psra_d:
23689 case Intrinsic::x86_avx2_psra_w:
23690 case Intrinsic::x86_avx2_psra_d: {
23691 SDValue Op0 = N->getOperand(1);
23692 SDValue Op1 = N->getOperand(2);
23693 EVT VT = Op0.getValueType();
23694 assert(VT.isVector() && "Expected a vector type!");
23696 if (isa<BuildVectorSDNode>(Op1))
23697 Op1 = Op1.getOperand(0);
23699 if (!isa<ConstantSDNode>(Op1))
23702 EVT SVT = VT.getVectorElementType();
23703 unsigned SVTBits = SVT.getSizeInBits();
23705 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23706 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23707 uint64_t ShAmt = C.getZExtValue();
23709 // Don't try to convert this shift into a ISD::SRA if the shift
23710 // count is bigger than or equal to the element size.
23711 if (ShAmt >= SVTBits)
23714 // Trivial case: if the shift count is zero, then fold this
23715 // into the first operand.
23719 // Replace this packed shift intrinsic with a target independent
23721 SDValue Splat = DAG.getConstant(C, VT);
23722 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23727 /// PerformMulCombine - Optimize a single multiply with constant into two
23728 /// in order to implement it with two cheaper instructions, e.g.
23729 /// LEA + SHL, LEA + LEA.
23730 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23731 TargetLowering::DAGCombinerInfo &DCI) {
23732 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23735 EVT VT = N->getValueType(0);
23736 if (VT != MVT::i64)
23739 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23742 uint64_t MulAmt = C->getZExtValue();
23743 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23746 uint64_t MulAmt1 = 0;
23747 uint64_t MulAmt2 = 0;
23748 if ((MulAmt % 9) == 0) {
23750 MulAmt2 = MulAmt / 9;
23751 } else if ((MulAmt % 5) == 0) {
23753 MulAmt2 = MulAmt / 5;
23754 } else if ((MulAmt % 3) == 0) {
23756 MulAmt2 = MulAmt / 3;
23759 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23762 if (isPowerOf2_64(MulAmt2) &&
23763 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23764 // If second multiplifer is pow2, issue it first. We want the multiply by
23765 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23767 std::swap(MulAmt1, MulAmt2);
23770 if (isPowerOf2_64(MulAmt1))
23771 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23772 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23774 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23775 DAG.getConstant(MulAmt1, VT));
23777 if (isPowerOf2_64(MulAmt2))
23778 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23779 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23781 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23782 DAG.getConstant(MulAmt2, VT));
23784 // Do not add new nodes to DAG combiner worklist.
23785 DCI.CombineTo(N, NewMul, false);
23790 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23791 SDValue N0 = N->getOperand(0);
23792 SDValue N1 = N->getOperand(1);
23793 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23794 EVT VT = N0.getValueType();
23796 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23797 // since the result of setcc_c is all zero's or all ones.
23798 if (VT.isInteger() && !VT.isVector() &&
23799 N1C && N0.getOpcode() == ISD::AND &&
23800 N0.getOperand(1).getOpcode() == ISD::Constant) {
23801 SDValue N00 = N0.getOperand(0);
23802 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23803 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23804 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23805 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23806 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23807 APInt ShAmt = N1C->getAPIntValue();
23808 Mask = Mask.shl(ShAmt);
23810 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23811 N00, DAG.getConstant(Mask, VT));
23815 // Hardware support for vector shifts is sparse which makes us scalarize the
23816 // vector operations in many cases. Also, on sandybridge ADD is faster than
23818 // (shl V, 1) -> add V,V
23819 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23820 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23821 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23822 // We shift all of the values by one. In many cases we do not have
23823 // hardware support for this operation. This is better expressed as an ADD
23825 if (N1SplatC->getZExtValue() == 1)
23826 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23832 /// \brief Returns a vector of 0s if the node in input is a vector logical
23833 /// shift by a constant amount which is known to be bigger than or equal
23834 /// to the vector element size in bits.
23835 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23836 const X86Subtarget *Subtarget) {
23837 EVT VT = N->getValueType(0);
23839 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23840 (!Subtarget->hasInt256() ||
23841 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23844 SDValue Amt = N->getOperand(1);
23846 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23847 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23848 APInt ShiftAmt = AmtSplat->getAPIntValue();
23849 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23851 // SSE2/AVX2 logical shifts always return a vector of 0s
23852 // if the shift amount is bigger than or equal to
23853 // the element size. The constant shift amount will be
23854 // encoded as a 8-bit immediate.
23855 if (ShiftAmt.trunc(8).uge(MaxAmount))
23856 return getZeroVector(VT, Subtarget, DAG, DL);
23862 /// PerformShiftCombine - Combine shifts.
23863 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23864 TargetLowering::DAGCombinerInfo &DCI,
23865 const X86Subtarget *Subtarget) {
23866 if (N->getOpcode() == ISD::SHL) {
23867 SDValue V = PerformSHLCombine(N, DAG);
23868 if (V.getNode()) return V;
23871 if (N->getOpcode() != ISD::SRA) {
23872 // Try to fold this logical shift into a zero vector.
23873 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23874 if (V.getNode()) return V;
23880 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23881 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23882 // and friends. Likewise for OR -> CMPNEQSS.
23883 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23884 TargetLowering::DAGCombinerInfo &DCI,
23885 const X86Subtarget *Subtarget) {
23888 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23889 // we're requiring SSE2 for both.
23890 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23891 SDValue N0 = N->getOperand(0);
23892 SDValue N1 = N->getOperand(1);
23893 SDValue CMP0 = N0->getOperand(1);
23894 SDValue CMP1 = N1->getOperand(1);
23897 // The SETCCs should both refer to the same CMP.
23898 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23901 SDValue CMP00 = CMP0->getOperand(0);
23902 SDValue CMP01 = CMP0->getOperand(1);
23903 EVT VT = CMP00.getValueType();
23905 if (VT == MVT::f32 || VT == MVT::f64) {
23906 bool ExpectingFlags = false;
23907 // Check for any users that want flags:
23908 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23909 !ExpectingFlags && UI != UE; ++UI)
23910 switch (UI->getOpcode()) {
23915 ExpectingFlags = true;
23917 case ISD::CopyToReg:
23918 case ISD::SIGN_EXTEND:
23919 case ISD::ZERO_EXTEND:
23920 case ISD::ANY_EXTEND:
23924 if (!ExpectingFlags) {
23925 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23926 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23928 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23929 X86::CondCode tmp = cc0;
23934 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23935 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23936 // FIXME: need symbolic constants for these magic numbers.
23937 // See X86ATTInstPrinter.cpp:printSSECC().
23938 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23939 if (Subtarget->hasAVX512()) {
23940 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23941 CMP01, DAG.getConstant(x86cc, MVT::i8));
23942 if (N->getValueType(0) != MVT::i1)
23943 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23947 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23948 CMP00.getValueType(), CMP00, CMP01,
23949 DAG.getConstant(x86cc, MVT::i8));
23951 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23952 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23954 if (is64BitFP && !Subtarget->is64Bit()) {
23955 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23956 // 64-bit integer, since that's not a legal type. Since
23957 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23958 // bits, but can do this little dance to extract the lowest 32 bits
23959 // and work with those going forward.
23960 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23962 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23964 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23965 Vector32, DAG.getIntPtrConstant(0));
23969 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23970 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23971 DAG.getConstant(1, IntVT));
23972 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23973 return OneBitOfTruth;
23981 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23982 /// so it can be folded inside ANDNP.
23983 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23984 EVT VT = N->getValueType(0);
23986 // Match direct AllOnes for 128 and 256-bit vectors
23987 if (ISD::isBuildVectorAllOnes(N))
23990 // Look through a bit convert.
23991 if (N->getOpcode() == ISD::BITCAST)
23992 N = N->getOperand(0).getNode();
23994 // Sometimes the operand may come from a insert_subvector building a 256-bit
23996 if (VT.is256BitVector() &&
23997 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23998 SDValue V1 = N->getOperand(0);
23999 SDValue V2 = N->getOperand(1);
24001 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24002 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24003 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24004 ISD::isBuildVectorAllOnes(V2.getNode()))
24011 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24012 // register. In most cases we actually compare or select YMM-sized registers
24013 // and mixing the two types creates horrible code. This method optimizes
24014 // some of the transition sequences.
24015 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24016 TargetLowering::DAGCombinerInfo &DCI,
24017 const X86Subtarget *Subtarget) {
24018 EVT VT = N->getValueType(0);
24019 if (!VT.is256BitVector())
24022 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24023 N->getOpcode() == ISD::ZERO_EXTEND ||
24024 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24026 SDValue Narrow = N->getOperand(0);
24027 EVT NarrowVT = Narrow->getValueType(0);
24028 if (!NarrowVT.is128BitVector())
24031 if (Narrow->getOpcode() != ISD::XOR &&
24032 Narrow->getOpcode() != ISD::AND &&
24033 Narrow->getOpcode() != ISD::OR)
24036 SDValue N0 = Narrow->getOperand(0);
24037 SDValue N1 = Narrow->getOperand(1);
24040 // The Left side has to be a trunc.
24041 if (N0.getOpcode() != ISD::TRUNCATE)
24044 // The type of the truncated inputs.
24045 EVT WideVT = N0->getOperand(0)->getValueType(0);
24049 // The right side has to be a 'trunc' or a constant vector.
24050 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24051 ConstantSDNode *RHSConstSplat = nullptr;
24052 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24053 RHSConstSplat = RHSBV->getConstantSplatNode();
24054 if (!RHSTrunc && !RHSConstSplat)
24057 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24059 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24062 // Set N0 and N1 to hold the inputs to the new wide operation.
24063 N0 = N0->getOperand(0);
24064 if (RHSConstSplat) {
24065 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24066 SDValue(RHSConstSplat, 0));
24067 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24068 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24069 } else if (RHSTrunc) {
24070 N1 = N1->getOperand(0);
24073 // Generate the wide operation.
24074 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24075 unsigned Opcode = N->getOpcode();
24077 case ISD::ANY_EXTEND:
24079 case ISD::ZERO_EXTEND: {
24080 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24081 APInt Mask = APInt::getAllOnesValue(InBits);
24082 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24083 return DAG.getNode(ISD::AND, DL, VT,
24084 Op, DAG.getConstant(Mask, VT));
24086 case ISD::SIGN_EXTEND:
24087 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24088 Op, DAG.getValueType(NarrowVT));
24090 llvm_unreachable("Unexpected opcode");
24094 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24095 TargetLowering::DAGCombinerInfo &DCI,
24096 const X86Subtarget *Subtarget) {
24097 EVT VT = N->getValueType(0);
24098 if (DCI.isBeforeLegalizeOps())
24101 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24105 // Create BEXTR instructions
24106 // BEXTR is ((X >> imm) & (2**size-1))
24107 if (VT == MVT::i32 || VT == MVT::i64) {
24108 SDValue N0 = N->getOperand(0);
24109 SDValue N1 = N->getOperand(1);
24112 // Check for BEXTR.
24113 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24114 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24115 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24116 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24117 if (MaskNode && ShiftNode) {
24118 uint64_t Mask = MaskNode->getZExtValue();
24119 uint64_t Shift = ShiftNode->getZExtValue();
24120 if (isMask_64(Mask)) {
24121 uint64_t MaskSize = CountPopulation_64(Mask);
24122 if (Shift + MaskSize <= VT.getSizeInBits())
24123 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24124 DAG.getConstant(Shift | (MaskSize << 8), VT));
24132 // Want to form ANDNP nodes:
24133 // 1) In the hopes of then easily combining them with OR and AND nodes
24134 // to form PBLEND/PSIGN.
24135 // 2) To match ANDN packed intrinsics
24136 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24139 SDValue N0 = N->getOperand(0);
24140 SDValue N1 = N->getOperand(1);
24143 // Check LHS for vnot
24144 if (N0.getOpcode() == ISD::XOR &&
24145 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24146 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24147 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24149 // Check RHS for vnot
24150 if (N1.getOpcode() == ISD::XOR &&
24151 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24152 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24153 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24158 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24159 TargetLowering::DAGCombinerInfo &DCI,
24160 const X86Subtarget *Subtarget) {
24161 if (DCI.isBeforeLegalizeOps())
24164 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24168 SDValue N0 = N->getOperand(0);
24169 SDValue N1 = N->getOperand(1);
24170 EVT VT = N->getValueType(0);
24172 // look for psign/blend
24173 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24174 if (!Subtarget->hasSSSE3() ||
24175 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24178 // Canonicalize pandn to RHS
24179 if (N0.getOpcode() == X86ISD::ANDNP)
24181 // or (and (m, y), (pandn m, x))
24182 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24183 SDValue Mask = N1.getOperand(0);
24184 SDValue X = N1.getOperand(1);
24186 if (N0.getOperand(0) == Mask)
24187 Y = N0.getOperand(1);
24188 if (N0.getOperand(1) == Mask)
24189 Y = N0.getOperand(0);
24191 // Check to see if the mask appeared in both the AND and ANDNP and
24195 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24196 // Look through mask bitcast.
24197 if (Mask.getOpcode() == ISD::BITCAST)
24198 Mask = Mask.getOperand(0);
24199 if (X.getOpcode() == ISD::BITCAST)
24200 X = X.getOperand(0);
24201 if (Y.getOpcode() == ISD::BITCAST)
24202 Y = Y.getOperand(0);
24204 EVT MaskVT = Mask.getValueType();
24206 // Validate that the Mask operand is a vector sra node.
24207 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24208 // there is no psrai.b
24209 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24210 unsigned SraAmt = ~0;
24211 if (Mask.getOpcode() == ISD::SRA) {
24212 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24213 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24214 SraAmt = AmtConst->getZExtValue();
24215 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24216 SDValue SraC = Mask.getOperand(1);
24217 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24219 if ((SraAmt + 1) != EltBits)
24224 // Now we know we at least have a plendvb with the mask val. See if
24225 // we can form a psignb/w/d.
24226 // psign = x.type == y.type == mask.type && y = sub(0, x);
24227 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24228 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24229 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24230 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24231 "Unsupported VT for PSIGN");
24232 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24233 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24235 // PBLENDVB only available on SSE 4.1
24236 if (!Subtarget->hasSSE41())
24239 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24241 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24242 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24243 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24244 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24245 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24249 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24252 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24253 MachineFunction &MF = DAG.getMachineFunction();
24254 bool OptForSize = MF.getFunction()->getAttributes().
24255 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24257 // SHLD/SHRD instructions have lower register pressure, but on some
24258 // platforms they have higher latency than the equivalent
24259 // series of shifts/or that would otherwise be generated.
24260 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24261 // have higher latencies and we are not optimizing for size.
24262 if (!OptForSize && Subtarget->isSHLDSlow())
24265 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24267 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24269 if (!N0.hasOneUse() || !N1.hasOneUse())
24272 SDValue ShAmt0 = N0.getOperand(1);
24273 if (ShAmt0.getValueType() != MVT::i8)
24275 SDValue ShAmt1 = N1.getOperand(1);
24276 if (ShAmt1.getValueType() != MVT::i8)
24278 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24279 ShAmt0 = ShAmt0.getOperand(0);
24280 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24281 ShAmt1 = ShAmt1.getOperand(0);
24284 unsigned Opc = X86ISD::SHLD;
24285 SDValue Op0 = N0.getOperand(0);
24286 SDValue Op1 = N1.getOperand(0);
24287 if (ShAmt0.getOpcode() == ISD::SUB) {
24288 Opc = X86ISD::SHRD;
24289 std::swap(Op0, Op1);
24290 std::swap(ShAmt0, ShAmt1);
24293 unsigned Bits = VT.getSizeInBits();
24294 if (ShAmt1.getOpcode() == ISD::SUB) {
24295 SDValue Sum = ShAmt1.getOperand(0);
24296 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24297 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24298 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24299 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24300 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24301 return DAG.getNode(Opc, DL, VT,
24303 DAG.getNode(ISD::TRUNCATE, DL,
24306 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24307 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24309 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24310 return DAG.getNode(Opc, DL, VT,
24311 N0.getOperand(0), N1.getOperand(0),
24312 DAG.getNode(ISD::TRUNCATE, DL,
24319 // Generate NEG and CMOV for integer abs.
24320 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24321 EVT VT = N->getValueType(0);
24323 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24324 // 8-bit integer abs to NEG and CMOV.
24325 if (VT.isInteger() && VT.getSizeInBits() == 8)
24328 SDValue N0 = N->getOperand(0);
24329 SDValue N1 = N->getOperand(1);
24332 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24333 // and change it to SUB and CMOV.
24334 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24335 N0.getOpcode() == ISD::ADD &&
24336 N0.getOperand(1) == N1 &&
24337 N1.getOpcode() == ISD::SRA &&
24338 N1.getOperand(0) == N0.getOperand(0))
24339 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24340 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24341 // Generate SUB & CMOV.
24342 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24343 DAG.getConstant(0, VT), N0.getOperand(0));
24345 SDValue Ops[] = { N0.getOperand(0), Neg,
24346 DAG.getConstant(X86::COND_GE, MVT::i8),
24347 SDValue(Neg.getNode(), 1) };
24348 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24353 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24354 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24355 TargetLowering::DAGCombinerInfo &DCI,
24356 const X86Subtarget *Subtarget) {
24357 if (DCI.isBeforeLegalizeOps())
24360 if (Subtarget->hasCMov()) {
24361 SDValue RV = performIntegerAbsCombine(N, DAG);
24369 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24370 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24371 TargetLowering::DAGCombinerInfo &DCI,
24372 const X86Subtarget *Subtarget) {
24373 LoadSDNode *Ld = cast<LoadSDNode>(N);
24374 EVT RegVT = Ld->getValueType(0);
24375 EVT MemVT = Ld->getMemoryVT();
24377 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24379 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24380 // into two 16-byte operations.
24381 ISD::LoadExtType Ext = Ld->getExtensionType();
24382 unsigned Alignment = Ld->getAlignment();
24383 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24384 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24385 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24386 unsigned NumElems = RegVT.getVectorNumElements();
24390 SDValue Ptr = Ld->getBasePtr();
24391 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24393 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24395 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24396 Ld->getPointerInfo(), Ld->isVolatile(),
24397 Ld->isNonTemporal(), Ld->isInvariant(),
24399 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24400 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24401 Ld->getPointerInfo(), Ld->isVolatile(),
24402 Ld->isNonTemporal(), Ld->isInvariant(),
24403 std::min(16U, Alignment));
24404 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24406 Load2.getValue(1));
24408 SDValue NewVec = DAG.getUNDEF(RegVT);
24409 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24410 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24411 return DCI.CombineTo(N, NewVec, TF, true);
24417 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24418 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24419 const X86Subtarget *Subtarget) {
24420 StoreSDNode *St = cast<StoreSDNode>(N);
24421 EVT VT = St->getValue().getValueType();
24422 EVT StVT = St->getMemoryVT();
24424 SDValue StoredVal = St->getOperand(1);
24425 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24427 // If we are saving a concatenation of two XMM registers and 32-byte stores
24428 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24429 unsigned Alignment = St->getAlignment();
24430 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24431 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24432 StVT == VT && !IsAligned) {
24433 unsigned NumElems = VT.getVectorNumElements();
24437 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24438 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24440 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24441 SDValue Ptr0 = St->getBasePtr();
24442 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24444 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24445 St->getPointerInfo(), St->isVolatile(),
24446 St->isNonTemporal(), Alignment);
24447 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24448 St->getPointerInfo(), St->isVolatile(),
24449 St->isNonTemporal(),
24450 std::min(16U, Alignment));
24451 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24454 // Optimize trunc store (of multiple scalars) to shuffle and store.
24455 // First, pack all of the elements in one place. Next, store to memory
24456 // in fewer chunks.
24457 if (St->isTruncatingStore() && VT.isVector()) {
24458 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24459 unsigned NumElems = VT.getVectorNumElements();
24460 assert(StVT != VT && "Cannot truncate to the same type");
24461 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24462 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24464 // From, To sizes and ElemCount must be pow of two
24465 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24466 // We are going to use the original vector elt for storing.
24467 // Accumulated smaller vector elements must be a multiple of the store size.
24468 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24470 unsigned SizeRatio = FromSz / ToSz;
24472 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24474 // Create a type on which we perform the shuffle
24475 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24476 StVT.getScalarType(), NumElems*SizeRatio);
24478 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24480 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24481 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24482 for (unsigned i = 0; i != NumElems; ++i)
24483 ShuffleVec[i] = i * SizeRatio;
24485 // Can't shuffle using an illegal type.
24486 if (!TLI.isTypeLegal(WideVecVT))
24489 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24490 DAG.getUNDEF(WideVecVT),
24492 // At this point all of the data is stored at the bottom of the
24493 // register. We now need to save it to mem.
24495 // Find the largest store unit
24496 MVT StoreType = MVT::i8;
24497 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24498 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24499 MVT Tp = (MVT::SimpleValueType)tp;
24500 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24504 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24505 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24506 (64 <= NumElems * ToSz))
24507 StoreType = MVT::f64;
24509 // Bitcast the original vector into a vector of store-size units
24510 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24511 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24512 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24513 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24514 SmallVector<SDValue, 8> Chains;
24515 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24516 TLI.getPointerTy());
24517 SDValue Ptr = St->getBasePtr();
24519 // Perform one or more big stores into memory.
24520 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24521 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24522 StoreType, ShuffWide,
24523 DAG.getIntPtrConstant(i));
24524 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24525 St->getPointerInfo(), St->isVolatile(),
24526 St->isNonTemporal(), St->getAlignment());
24527 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24528 Chains.push_back(Ch);
24531 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24534 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24535 // the FP state in cases where an emms may be missing.
24536 // A preferable solution to the general problem is to figure out the right
24537 // places to insert EMMS. This qualifies as a quick hack.
24539 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24540 if (VT.getSizeInBits() != 64)
24543 const Function *F = DAG.getMachineFunction().getFunction();
24544 bool NoImplicitFloatOps = F->getAttributes().
24545 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24546 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24547 && Subtarget->hasSSE2();
24548 if ((VT.isVector() ||
24549 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24550 isa<LoadSDNode>(St->getValue()) &&
24551 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24552 St->getChain().hasOneUse() && !St->isVolatile()) {
24553 SDNode* LdVal = St->getValue().getNode();
24554 LoadSDNode *Ld = nullptr;
24555 int TokenFactorIndex = -1;
24556 SmallVector<SDValue, 8> Ops;
24557 SDNode* ChainVal = St->getChain().getNode();
24558 // Must be a store of a load. We currently handle two cases: the load
24559 // is a direct child, and it's under an intervening TokenFactor. It is
24560 // possible to dig deeper under nested TokenFactors.
24561 if (ChainVal == LdVal)
24562 Ld = cast<LoadSDNode>(St->getChain());
24563 else if (St->getValue().hasOneUse() &&
24564 ChainVal->getOpcode() == ISD::TokenFactor) {
24565 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24566 if (ChainVal->getOperand(i).getNode() == LdVal) {
24567 TokenFactorIndex = i;
24568 Ld = cast<LoadSDNode>(St->getValue());
24570 Ops.push_back(ChainVal->getOperand(i));
24574 if (!Ld || !ISD::isNormalLoad(Ld))
24577 // If this is not the MMX case, i.e. we are just turning i64 load/store
24578 // into f64 load/store, avoid the transformation if there are multiple
24579 // uses of the loaded value.
24580 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24585 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24586 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24588 if (Subtarget->is64Bit() || F64IsLegal) {
24589 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24590 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24591 Ld->getPointerInfo(), Ld->isVolatile(),
24592 Ld->isNonTemporal(), Ld->isInvariant(),
24593 Ld->getAlignment());
24594 SDValue NewChain = NewLd.getValue(1);
24595 if (TokenFactorIndex != -1) {
24596 Ops.push_back(NewChain);
24597 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24599 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24600 St->getPointerInfo(),
24601 St->isVolatile(), St->isNonTemporal(),
24602 St->getAlignment());
24605 // Otherwise, lower to two pairs of 32-bit loads / stores.
24606 SDValue LoAddr = Ld->getBasePtr();
24607 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24608 DAG.getConstant(4, MVT::i32));
24610 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24611 Ld->getPointerInfo(),
24612 Ld->isVolatile(), Ld->isNonTemporal(),
24613 Ld->isInvariant(), Ld->getAlignment());
24614 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24615 Ld->getPointerInfo().getWithOffset(4),
24616 Ld->isVolatile(), Ld->isNonTemporal(),
24618 MinAlign(Ld->getAlignment(), 4));
24620 SDValue NewChain = LoLd.getValue(1);
24621 if (TokenFactorIndex != -1) {
24622 Ops.push_back(LoLd);
24623 Ops.push_back(HiLd);
24624 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24627 LoAddr = St->getBasePtr();
24628 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24629 DAG.getConstant(4, MVT::i32));
24631 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24632 St->getPointerInfo(),
24633 St->isVolatile(), St->isNonTemporal(),
24634 St->getAlignment());
24635 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24636 St->getPointerInfo().getWithOffset(4),
24638 St->isNonTemporal(),
24639 MinAlign(St->getAlignment(), 4));
24640 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24645 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24646 /// and return the operands for the horizontal operation in LHS and RHS. A
24647 /// horizontal operation performs the binary operation on successive elements
24648 /// of its first operand, then on successive elements of its second operand,
24649 /// returning the resulting values in a vector. For example, if
24650 /// A = < float a0, float a1, float a2, float a3 >
24652 /// B = < float b0, float b1, float b2, float b3 >
24653 /// then the result of doing a horizontal operation on A and B is
24654 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24655 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24656 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24657 /// set to A, RHS to B, and the routine returns 'true'.
24658 /// Note that the binary operation should have the property that if one of the
24659 /// operands is UNDEF then the result is UNDEF.
24660 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24661 // Look for the following pattern: if
24662 // A = < float a0, float a1, float a2, float a3 >
24663 // B = < float b0, float b1, float b2, float b3 >
24665 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24666 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24667 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24668 // which is A horizontal-op B.
24670 // At least one of the operands should be a vector shuffle.
24671 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24672 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24675 MVT VT = LHS.getSimpleValueType();
24677 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24678 "Unsupported vector type for horizontal add/sub");
24680 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24681 // operate independently on 128-bit lanes.
24682 unsigned NumElts = VT.getVectorNumElements();
24683 unsigned NumLanes = VT.getSizeInBits()/128;
24684 unsigned NumLaneElts = NumElts / NumLanes;
24685 assert((NumLaneElts % 2 == 0) &&
24686 "Vector type should have an even number of elements in each lane");
24687 unsigned HalfLaneElts = NumLaneElts/2;
24689 // View LHS in the form
24690 // LHS = VECTOR_SHUFFLE A, B, LMask
24691 // If LHS is not a shuffle then pretend it is the shuffle
24692 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24693 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24696 SmallVector<int, 16> LMask(NumElts);
24697 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24698 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24699 A = LHS.getOperand(0);
24700 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24701 B = LHS.getOperand(1);
24702 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24703 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24705 if (LHS.getOpcode() != ISD::UNDEF)
24707 for (unsigned i = 0; i != NumElts; ++i)
24711 // Likewise, view RHS in the form
24712 // RHS = VECTOR_SHUFFLE C, D, RMask
24714 SmallVector<int, 16> RMask(NumElts);
24715 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24716 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24717 C = RHS.getOperand(0);
24718 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24719 D = RHS.getOperand(1);
24720 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24721 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24723 if (RHS.getOpcode() != ISD::UNDEF)
24725 for (unsigned i = 0; i != NumElts; ++i)
24729 // Check that the shuffles are both shuffling the same vectors.
24730 if (!(A == C && B == D) && !(A == D && B == C))
24733 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24734 if (!A.getNode() && !B.getNode())
24737 // If A and B occur in reverse order in RHS, then "swap" them (which means
24738 // rewriting the mask).
24740 CommuteVectorShuffleMask(RMask, NumElts);
24742 // At this point LHS and RHS are equivalent to
24743 // LHS = VECTOR_SHUFFLE A, B, LMask
24744 // RHS = VECTOR_SHUFFLE A, B, RMask
24745 // Check that the masks correspond to performing a horizontal operation.
24746 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24747 for (unsigned i = 0; i != NumLaneElts; ++i) {
24748 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24750 // Ignore any UNDEF components.
24751 if (LIdx < 0 || RIdx < 0 ||
24752 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24753 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24756 // Check that successive elements are being operated on. If not, this is
24757 // not a horizontal operation.
24758 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24759 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24760 if (!(LIdx == Index && RIdx == Index + 1) &&
24761 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24766 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24767 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24771 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24772 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24773 const X86Subtarget *Subtarget) {
24774 EVT VT = N->getValueType(0);
24775 SDValue LHS = N->getOperand(0);
24776 SDValue RHS = N->getOperand(1);
24778 // Try to synthesize horizontal adds from adds of shuffles.
24779 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24780 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24781 isHorizontalBinOp(LHS, RHS, true))
24782 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24786 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24787 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24788 const X86Subtarget *Subtarget) {
24789 EVT VT = N->getValueType(0);
24790 SDValue LHS = N->getOperand(0);
24791 SDValue RHS = N->getOperand(1);
24793 // Try to synthesize horizontal subs from subs of shuffles.
24794 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24795 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24796 isHorizontalBinOp(LHS, RHS, false))
24797 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24801 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24802 /// X86ISD::FXOR nodes.
24803 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24804 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24805 // F[X]OR(0.0, x) -> x
24806 // F[X]OR(x, 0.0) -> x
24807 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24808 if (C->getValueAPF().isPosZero())
24809 return N->getOperand(1);
24810 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24811 if (C->getValueAPF().isPosZero())
24812 return N->getOperand(0);
24816 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24817 /// X86ISD::FMAX nodes.
24818 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24819 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24821 // Only perform optimizations if UnsafeMath is used.
24822 if (!DAG.getTarget().Options.UnsafeFPMath)
24825 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24826 // into FMINC and FMAXC, which are Commutative operations.
24827 unsigned NewOp = 0;
24828 switch (N->getOpcode()) {
24829 default: llvm_unreachable("unknown opcode");
24830 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24831 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24834 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24835 N->getOperand(0), N->getOperand(1));
24838 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24839 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24840 // FAND(0.0, x) -> 0.0
24841 // FAND(x, 0.0) -> 0.0
24842 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24843 if (C->getValueAPF().isPosZero())
24844 return N->getOperand(0);
24845 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24846 if (C->getValueAPF().isPosZero())
24847 return N->getOperand(1);
24851 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24852 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24853 // FANDN(x, 0.0) -> 0.0
24854 // FANDN(0.0, x) -> x
24855 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24856 if (C->getValueAPF().isPosZero())
24857 return N->getOperand(1);
24858 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24859 if (C->getValueAPF().isPosZero())
24860 return N->getOperand(1);
24864 static SDValue PerformBTCombine(SDNode *N,
24866 TargetLowering::DAGCombinerInfo &DCI) {
24867 // BT ignores high bits in the bit index operand.
24868 SDValue Op1 = N->getOperand(1);
24869 if (Op1.hasOneUse()) {
24870 unsigned BitWidth = Op1.getValueSizeInBits();
24871 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24872 APInt KnownZero, KnownOne;
24873 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24874 !DCI.isBeforeLegalizeOps());
24875 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24876 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24877 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24878 DCI.CommitTargetLoweringOpt(TLO);
24883 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24884 SDValue Op = N->getOperand(0);
24885 if (Op.getOpcode() == ISD::BITCAST)
24886 Op = Op.getOperand(0);
24887 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24888 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24889 VT.getVectorElementType().getSizeInBits() ==
24890 OpVT.getVectorElementType().getSizeInBits()) {
24891 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24896 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24897 const X86Subtarget *Subtarget) {
24898 EVT VT = N->getValueType(0);
24899 if (!VT.isVector())
24902 SDValue N0 = N->getOperand(0);
24903 SDValue N1 = N->getOperand(1);
24904 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24907 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24908 // both SSE and AVX2 since there is no sign-extended shift right
24909 // operation on a vector with 64-bit elements.
24910 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24911 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24912 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24913 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24914 SDValue N00 = N0.getOperand(0);
24916 // EXTLOAD has a better solution on AVX2,
24917 // it may be replaced with X86ISD::VSEXT node.
24918 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24919 if (!ISD::isNormalLoad(N00.getNode()))
24922 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24923 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24925 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24931 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24932 TargetLowering::DAGCombinerInfo &DCI,
24933 const X86Subtarget *Subtarget) {
24934 SDValue N0 = N->getOperand(0);
24935 EVT VT = N->getValueType(0);
24937 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24938 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24939 // This exposes the sext to the sdivrem lowering, so that it directly extends
24940 // from AH (which we otherwise need to do contortions to access).
24941 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24942 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24944 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24945 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24946 N0.getOperand(0), N0.getOperand(1));
24947 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24948 return R.getValue(1);
24951 if (!DCI.isBeforeLegalizeOps())
24954 if (!Subtarget->hasFp256())
24957 if (VT.isVector() && VT.getSizeInBits() == 256) {
24958 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24966 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24967 const X86Subtarget* Subtarget) {
24969 EVT VT = N->getValueType(0);
24971 // Let legalize expand this if it isn't a legal type yet.
24972 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24975 EVT ScalarVT = VT.getScalarType();
24976 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24977 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24980 SDValue A = N->getOperand(0);
24981 SDValue B = N->getOperand(1);
24982 SDValue C = N->getOperand(2);
24984 bool NegA = (A.getOpcode() == ISD::FNEG);
24985 bool NegB = (B.getOpcode() == ISD::FNEG);
24986 bool NegC = (C.getOpcode() == ISD::FNEG);
24988 // Negative multiplication when NegA xor NegB
24989 bool NegMul = (NegA != NegB);
24991 A = A.getOperand(0);
24993 B = B.getOperand(0);
24995 C = C.getOperand(0);
24999 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
25001 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
25003 return DAG.getNode(Opcode, dl, VT, A, B, C);
25006 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
25007 TargetLowering::DAGCombinerInfo &DCI,
25008 const X86Subtarget *Subtarget) {
25009 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
25010 // (and (i32 x86isd::setcc_carry), 1)
25011 // This eliminates the zext. This transformation is necessary because
25012 // ISD::SETCC is always legalized to i8.
25014 SDValue N0 = N->getOperand(0);
25015 EVT VT = N->getValueType(0);
25017 if (N0.getOpcode() == ISD::AND &&
25019 N0.getOperand(0).hasOneUse()) {
25020 SDValue N00 = N0.getOperand(0);
25021 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25022 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25023 if (!C || C->getZExtValue() != 1)
25025 return DAG.getNode(ISD::AND, dl, VT,
25026 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25027 N00.getOperand(0), N00.getOperand(1)),
25028 DAG.getConstant(1, VT));
25032 if (N0.getOpcode() == ISD::TRUNCATE &&
25034 N0.getOperand(0).hasOneUse()) {
25035 SDValue N00 = N0.getOperand(0);
25036 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25037 return DAG.getNode(ISD::AND, dl, VT,
25038 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25039 N00.getOperand(0), N00.getOperand(1)),
25040 DAG.getConstant(1, VT));
25043 if (VT.is256BitVector()) {
25044 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25049 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25050 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25051 // This exposes the zext to the udivrem lowering, so that it directly extends
25052 // from AH (which we otherwise need to do contortions to access).
25053 if (N0.getOpcode() == ISD::UDIVREM &&
25054 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25055 (VT == MVT::i32 || VT == MVT::i64)) {
25056 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25057 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25058 N0.getOperand(0), N0.getOperand(1));
25059 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25060 return R.getValue(1);
25066 // Optimize x == -y --> x+y == 0
25067 // x != -y --> x+y != 0
25068 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25069 const X86Subtarget* Subtarget) {
25070 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25071 SDValue LHS = N->getOperand(0);
25072 SDValue RHS = N->getOperand(1);
25073 EVT VT = N->getValueType(0);
25076 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25077 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25078 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25079 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25080 LHS.getValueType(), RHS, LHS.getOperand(1));
25081 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25082 addV, DAG.getConstant(0, addV.getValueType()), CC);
25084 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25085 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25086 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25087 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25088 RHS.getValueType(), LHS, RHS.getOperand(1));
25089 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25090 addV, DAG.getConstant(0, addV.getValueType()), CC);
25093 if (VT.getScalarType() == MVT::i1) {
25094 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25095 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25096 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25097 if (!IsSEXT0 && !IsVZero0)
25099 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25100 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25101 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25103 if (!IsSEXT1 && !IsVZero1)
25106 if (IsSEXT0 && IsVZero1) {
25107 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25108 if (CC == ISD::SETEQ)
25109 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25110 return LHS.getOperand(0);
25112 if (IsSEXT1 && IsVZero0) {
25113 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25114 if (CC == ISD::SETEQ)
25115 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25116 return RHS.getOperand(0);
25123 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25124 const X86Subtarget *Subtarget) {
25126 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25127 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25128 "X86insertps is only defined for v4x32");
25130 SDValue Ld = N->getOperand(1);
25131 if (MayFoldLoad(Ld)) {
25132 // Extract the countS bits from the immediate so we can get the proper
25133 // address when narrowing the vector load to a specific element.
25134 // When the second source op is a memory address, interps doesn't use
25135 // countS and just gets an f32 from that address.
25136 unsigned DestIndex =
25137 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25138 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25142 // Create this as a scalar to vector to match the instruction pattern.
25143 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25144 // countS bits are ignored when loading from memory on insertps, which
25145 // means we don't need to explicitly set them to 0.
25146 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25147 LoadScalarToVector, N->getOperand(2));
25150 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25151 // as "sbb reg,reg", since it can be extended without zext and produces
25152 // an all-ones bit which is more useful than 0/1 in some cases.
25153 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25156 return DAG.getNode(ISD::AND, DL, VT,
25157 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25158 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25159 DAG.getConstant(1, VT));
25160 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25161 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25162 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25163 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25166 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25167 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25168 TargetLowering::DAGCombinerInfo &DCI,
25169 const X86Subtarget *Subtarget) {
25171 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25172 SDValue EFLAGS = N->getOperand(1);
25174 if (CC == X86::COND_A) {
25175 // Try to convert COND_A into COND_B in an attempt to facilitate
25176 // materializing "setb reg".
25178 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25179 // cannot take an immediate as its first operand.
25181 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25182 EFLAGS.getValueType().isInteger() &&
25183 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25184 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25185 EFLAGS.getNode()->getVTList(),
25186 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25187 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25188 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25192 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25193 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25195 if (CC == X86::COND_B)
25196 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25200 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25201 if (Flags.getNode()) {
25202 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25203 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25209 // Optimize branch condition evaluation.
25211 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25212 TargetLowering::DAGCombinerInfo &DCI,
25213 const X86Subtarget *Subtarget) {
25215 SDValue Chain = N->getOperand(0);
25216 SDValue Dest = N->getOperand(1);
25217 SDValue EFLAGS = N->getOperand(3);
25218 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25222 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25223 if (Flags.getNode()) {
25224 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25225 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25232 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25233 SelectionDAG &DAG) {
25234 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25235 // optimize away operation when it's from a constant.
25237 // The general transformation is:
25238 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25239 // AND(VECTOR_CMP(x,y), constant2)
25240 // constant2 = UNARYOP(constant)
25242 // Early exit if this isn't a vector operation, the operand of the
25243 // unary operation isn't a bitwise AND, or if the sizes of the operations
25244 // aren't the same.
25245 EVT VT = N->getValueType(0);
25246 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25247 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25248 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25251 // Now check that the other operand of the AND is a constant. We could
25252 // make the transformation for non-constant splats as well, but it's unclear
25253 // that would be a benefit as it would not eliminate any operations, just
25254 // perform one more step in scalar code before moving to the vector unit.
25255 if (BuildVectorSDNode *BV =
25256 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25257 // Bail out if the vector isn't a constant.
25258 if (!BV->isConstant())
25261 // Everything checks out. Build up the new and improved node.
25263 EVT IntVT = BV->getValueType(0);
25264 // Create a new constant of the appropriate type for the transformed
25266 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25267 // The AND node needs bitcasts to/from an integer vector type around it.
25268 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25269 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25270 N->getOperand(0)->getOperand(0), MaskConst);
25271 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25278 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25279 const X86TargetLowering *XTLI) {
25280 // First try to optimize away the conversion entirely when it's
25281 // conditionally from a constant. Vectors only.
25282 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25283 if (Res != SDValue())
25286 // Now move on to more general possibilities.
25287 SDValue Op0 = N->getOperand(0);
25288 EVT InVT = Op0->getValueType(0);
25290 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25291 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25293 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25294 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25295 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25298 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25299 // a 32-bit target where SSE doesn't support i64->FP operations.
25300 if (Op0.getOpcode() == ISD::LOAD) {
25301 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25302 EVT VT = Ld->getValueType(0);
25303 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25304 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25305 !XTLI->getSubtarget()->is64Bit() &&
25307 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25308 Ld->getChain(), Op0, DAG);
25309 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25316 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25317 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25318 X86TargetLowering::DAGCombinerInfo &DCI) {
25319 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25320 // the result is either zero or one (depending on the input carry bit).
25321 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25322 if (X86::isZeroNode(N->getOperand(0)) &&
25323 X86::isZeroNode(N->getOperand(1)) &&
25324 // We don't have a good way to replace an EFLAGS use, so only do this when
25326 SDValue(N, 1).use_empty()) {
25328 EVT VT = N->getValueType(0);
25329 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25330 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25331 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25332 DAG.getConstant(X86::COND_B,MVT::i8),
25334 DAG.getConstant(1, VT));
25335 return DCI.CombineTo(N, Res1, CarryOut);
25341 // fold (add Y, (sete X, 0)) -> adc 0, Y
25342 // (add Y, (setne X, 0)) -> sbb -1, Y
25343 // (sub (sete X, 0), Y) -> sbb 0, Y
25344 // (sub (setne X, 0), Y) -> adc -1, Y
25345 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25348 // Look through ZExts.
25349 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25350 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25353 SDValue SetCC = Ext.getOperand(0);
25354 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25357 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25358 if (CC != X86::COND_E && CC != X86::COND_NE)
25361 SDValue Cmp = SetCC.getOperand(1);
25362 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25363 !X86::isZeroNode(Cmp.getOperand(1)) ||
25364 !Cmp.getOperand(0).getValueType().isInteger())
25367 SDValue CmpOp0 = Cmp.getOperand(0);
25368 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25369 DAG.getConstant(1, CmpOp0.getValueType()));
25371 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25372 if (CC == X86::COND_NE)
25373 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25374 DL, OtherVal.getValueType(), OtherVal,
25375 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25376 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25377 DL, OtherVal.getValueType(), OtherVal,
25378 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25381 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25382 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25383 const X86Subtarget *Subtarget) {
25384 EVT VT = N->getValueType(0);
25385 SDValue Op0 = N->getOperand(0);
25386 SDValue Op1 = N->getOperand(1);
25388 // Try to synthesize horizontal adds from adds of shuffles.
25389 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25390 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25391 isHorizontalBinOp(Op0, Op1, true))
25392 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25394 return OptimizeConditionalInDecrement(N, DAG);
25397 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25398 const X86Subtarget *Subtarget) {
25399 SDValue Op0 = N->getOperand(0);
25400 SDValue Op1 = N->getOperand(1);
25402 // X86 can't encode an immediate LHS of a sub. See if we can push the
25403 // negation into a preceding instruction.
25404 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25405 // If the RHS of the sub is a XOR with one use and a constant, invert the
25406 // immediate. Then add one to the LHS of the sub so we can turn
25407 // X-Y -> X+~Y+1, saving one register.
25408 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25409 isa<ConstantSDNode>(Op1.getOperand(1))) {
25410 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25411 EVT VT = Op0.getValueType();
25412 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25414 DAG.getConstant(~XorC, VT));
25415 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25416 DAG.getConstant(C->getAPIntValue()+1, VT));
25420 // Try to synthesize horizontal adds from adds of shuffles.
25421 EVT VT = N->getValueType(0);
25422 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25423 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25424 isHorizontalBinOp(Op0, Op1, true))
25425 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25427 return OptimizeConditionalInDecrement(N, DAG);
25430 /// performVZEXTCombine - Performs build vector combines
25431 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25432 TargetLowering::DAGCombinerInfo &DCI,
25433 const X86Subtarget *Subtarget) {
25435 MVT VT = N->getSimpleValueType(0);
25436 SDValue Op = N->getOperand(0);
25437 MVT OpVT = Op.getSimpleValueType();
25438 MVT OpEltVT = OpVT.getVectorElementType();
25439 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25441 // (vzext (bitcast (vzext (x)) -> (vzext x)
25443 while (V.getOpcode() == ISD::BITCAST)
25444 V = V.getOperand(0);
25446 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25447 MVT InnerVT = V.getSimpleValueType();
25448 MVT InnerEltVT = InnerVT.getVectorElementType();
25450 // If the element sizes match exactly, we can just do one larger vzext. This
25451 // is always an exact type match as vzext operates on integer types.
25452 if (OpEltVT == InnerEltVT) {
25453 assert(OpVT == InnerVT && "Types must match for vzext!");
25454 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25457 // The only other way we can combine them is if only a single element of the
25458 // inner vzext is used in the input to the outer vzext.
25459 if (InnerEltVT.getSizeInBits() < InputBits)
25462 // In this case, the inner vzext is completely dead because we're going to
25463 // only look at bits inside of the low element. Just do the outer vzext on
25464 // a bitcast of the input to the inner.
25465 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25466 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25469 // Check if we can bypass extracting and re-inserting an element of an input
25470 // vector. Essentialy:
25471 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25472 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25473 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25474 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25475 SDValue ExtractedV = V.getOperand(0);
25476 SDValue OrigV = ExtractedV.getOperand(0);
25477 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25478 if (ExtractIdx->getZExtValue() == 0) {
25479 MVT OrigVT = OrigV.getSimpleValueType();
25480 // Extract a subvector if necessary...
25481 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25482 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25483 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25484 OrigVT.getVectorNumElements() / Ratio);
25485 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25486 DAG.getIntPtrConstant(0));
25488 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25489 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25496 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25497 DAGCombinerInfo &DCI) const {
25498 SelectionDAG &DAG = DCI.DAG;
25499 switch (N->getOpcode()) {
25501 case ISD::EXTRACT_VECTOR_ELT:
25502 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25505 case X86ISD::SHRUNKBLEND:
25506 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25507 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25508 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25509 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25510 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25511 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25514 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25515 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25516 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25517 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25518 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25519 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25520 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25521 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25522 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25524 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25526 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25527 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25528 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25529 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25530 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25531 case ISD::ANY_EXTEND:
25532 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25533 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25534 case ISD::SIGN_EXTEND_INREG:
25535 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25536 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25537 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25538 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25539 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25540 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25541 case X86ISD::SHUFP: // Handle all target specific shuffles
25542 case X86ISD::PALIGNR:
25543 case X86ISD::UNPCKH:
25544 case X86ISD::UNPCKL:
25545 case X86ISD::MOVHLPS:
25546 case X86ISD::MOVLHPS:
25547 case X86ISD::PSHUFB:
25548 case X86ISD::PSHUFD:
25549 case X86ISD::PSHUFHW:
25550 case X86ISD::PSHUFLW:
25551 case X86ISD::MOVSS:
25552 case X86ISD::MOVSD:
25553 case X86ISD::VPERMILPI:
25554 case X86ISD::VPERM2X128:
25555 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25556 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25557 case ISD::INTRINSIC_WO_CHAIN:
25558 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25559 case X86ISD::INSERTPS:
25560 return PerformINSERTPSCombine(N, DAG, Subtarget);
25561 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25567 /// isTypeDesirableForOp - Return true if the target has native support for
25568 /// the specified value type and it is 'desirable' to use the type for the
25569 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25570 /// instruction encodings are longer and some i16 instructions are slow.
25571 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25572 if (!isTypeLegal(VT))
25574 if (VT != MVT::i16)
25581 case ISD::SIGN_EXTEND:
25582 case ISD::ZERO_EXTEND:
25583 case ISD::ANY_EXTEND:
25596 /// IsDesirableToPromoteOp - This method query the target whether it is
25597 /// beneficial for dag combiner to promote the specified node. If true, it
25598 /// should return the desired promotion type by reference.
25599 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25600 EVT VT = Op.getValueType();
25601 if (VT != MVT::i16)
25604 bool Promote = false;
25605 bool Commute = false;
25606 switch (Op.getOpcode()) {
25609 LoadSDNode *LD = cast<LoadSDNode>(Op);
25610 // If the non-extending load has a single use and it's not live out, then it
25611 // might be folded.
25612 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25613 Op.hasOneUse()*/) {
25614 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25615 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25616 // The only case where we'd want to promote LOAD (rather then it being
25617 // promoted as an operand is when it's only use is liveout.
25618 if (UI->getOpcode() != ISD::CopyToReg)
25625 case ISD::SIGN_EXTEND:
25626 case ISD::ZERO_EXTEND:
25627 case ISD::ANY_EXTEND:
25632 SDValue N0 = Op.getOperand(0);
25633 // Look out for (store (shl (load), x)).
25634 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25647 SDValue N0 = Op.getOperand(0);
25648 SDValue N1 = Op.getOperand(1);
25649 if (!Commute && MayFoldLoad(N1))
25651 // Avoid disabling potential load folding opportunities.
25652 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25654 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25664 //===----------------------------------------------------------------------===//
25665 // X86 Inline Assembly Support
25666 //===----------------------------------------------------------------------===//
25669 // Helper to match a string separated by whitespace.
25670 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25671 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25673 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25674 StringRef piece(*args[i]);
25675 if (!s.startswith(piece)) // Check if the piece matches.
25678 s = s.substr(piece.size());
25679 StringRef::size_type pos = s.find_first_not_of(" \t");
25680 if (pos == 0) // We matched a prefix.
25688 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25691 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25693 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25694 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25695 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25696 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25698 if (AsmPieces.size() == 3)
25700 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25707 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25708 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25710 std::string AsmStr = IA->getAsmString();
25712 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25713 if (!Ty || Ty->getBitWidth() % 16 != 0)
25716 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25717 SmallVector<StringRef, 4> AsmPieces;
25718 SplitString(AsmStr, AsmPieces, ";\n");
25720 switch (AsmPieces.size()) {
25721 default: return false;
25723 // FIXME: this should verify that we are targeting a 486 or better. If not,
25724 // we will turn this bswap into something that will be lowered to logical
25725 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25726 // lower so don't worry about this.
25728 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25729 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25730 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25731 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25732 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25733 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25734 // No need to check constraints, nothing other than the equivalent of
25735 // "=r,0" would be valid here.
25736 return IntrinsicLowering::LowerToByteSwap(CI);
25739 // rorw $$8, ${0:w} --> llvm.bswap.i16
25740 if (CI->getType()->isIntegerTy(16) &&
25741 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25742 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25743 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25745 const std::string &ConstraintsStr = IA->getConstraintString();
25746 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25747 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25748 if (clobbersFlagRegisters(AsmPieces))
25749 return IntrinsicLowering::LowerToByteSwap(CI);
25753 if (CI->getType()->isIntegerTy(32) &&
25754 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25755 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25756 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25757 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25759 const std::string &ConstraintsStr = IA->getConstraintString();
25760 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25761 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25762 if (clobbersFlagRegisters(AsmPieces))
25763 return IntrinsicLowering::LowerToByteSwap(CI);
25766 if (CI->getType()->isIntegerTy(64)) {
25767 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25768 if (Constraints.size() >= 2 &&
25769 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25770 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25771 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25772 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25773 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25774 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25775 return IntrinsicLowering::LowerToByteSwap(CI);
25783 /// getConstraintType - Given a constraint letter, return the type of
25784 /// constraint it is for this target.
25785 X86TargetLowering::ConstraintType
25786 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25787 if (Constraint.size() == 1) {
25788 switch (Constraint[0]) {
25799 return C_RegisterClass;
25823 return TargetLowering::getConstraintType(Constraint);
25826 /// Examine constraint type and operand type and determine a weight value.
25827 /// This object must already have been set up with the operand type
25828 /// and the current alternative constraint selected.
25829 TargetLowering::ConstraintWeight
25830 X86TargetLowering::getSingleConstraintMatchWeight(
25831 AsmOperandInfo &info, const char *constraint) const {
25832 ConstraintWeight weight = CW_Invalid;
25833 Value *CallOperandVal = info.CallOperandVal;
25834 // If we don't have a value, we can't do a match,
25835 // but allow it at the lowest weight.
25836 if (!CallOperandVal)
25838 Type *type = CallOperandVal->getType();
25839 // Look at the constraint type.
25840 switch (*constraint) {
25842 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25853 if (CallOperandVal->getType()->isIntegerTy())
25854 weight = CW_SpecificReg;
25859 if (type->isFloatingPointTy())
25860 weight = CW_SpecificReg;
25863 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25864 weight = CW_SpecificReg;
25868 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25869 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25870 weight = CW_Register;
25873 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25874 if (C->getZExtValue() <= 31)
25875 weight = CW_Constant;
25879 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25880 if (C->getZExtValue() <= 63)
25881 weight = CW_Constant;
25885 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25886 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25887 weight = CW_Constant;
25891 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25892 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25893 weight = CW_Constant;
25897 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25898 if (C->getZExtValue() <= 3)
25899 weight = CW_Constant;
25903 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25904 if (C->getZExtValue() <= 0xff)
25905 weight = CW_Constant;
25910 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25911 weight = CW_Constant;
25915 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25916 if ((C->getSExtValue() >= -0x80000000LL) &&
25917 (C->getSExtValue() <= 0x7fffffffLL))
25918 weight = CW_Constant;
25922 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25923 if (C->getZExtValue() <= 0xffffffff)
25924 weight = CW_Constant;
25931 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25932 /// with another that has more specific requirements based on the type of the
25933 /// corresponding operand.
25934 const char *X86TargetLowering::
25935 LowerXConstraint(EVT ConstraintVT) const {
25936 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25937 // 'f' like normal targets.
25938 if (ConstraintVT.isFloatingPoint()) {
25939 if (Subtarget->hasSSE2())
25941 if (Subtarget->hasSSE1())
25945 return TargetLowering::LowerXConstraint(ConstraintVT);
25948 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25949 /// vector. If it is invalid, don't add anything to Ops.
25950 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25951 std::string &Constraint,
25952 std::vector<SDValue>&Ops,
25953 SelectionDAG &DAG) const {
25956 // Only support length 1 constraints for now.
25957 if (Constraint.length() > 1) return;
25959 char ConstraintLetter = Constraint[0];
25960 switch (ConstraintLetter) {
25963 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25964 if (C->getZExtValue() <= 31) {
25965 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25971 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25972 if (C->getZExtValue() <= 63) {
25973 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25979 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25980 if (isInt<8>(C->getSExtValue())) {
25981 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25987 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25988 if (C->getZExtValue() <= 255) {
25989 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25995 // 32-bit signed value
25996 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25997 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25998 C->getSExtValue())) {
25999 // Widen to 64 bits here to get it sign extended.
26000 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
26003 // FIXME gcc accepts some relocatable values here too, but only in certain
26004 // memory models; it's complicated.
26009 // 32-bit unsigned value
26010 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
26011 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
26012 C->getZExtValue())) {
26013 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
26017 // FIXME gcc accepts some relocatable values here too, but only in certain
26018 // memory models; it's complicated.
26022 // Literal immediates are always ok.
26023 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26024 // Widen to 64 bits here to get it sign extended.
26025 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26029 // In any sort of PIC mode addresses need to be computed at runtime by
26030 // adding in a register or some sort of table lookup. These can't
26031 // be used as immediates.
26032 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26035 // If we are in non-pic codegen mode, we allow the address of a global (with
26036 // an optional displacement) to be used with 'i'.
26037 GlobalAddressSDNode *GA = nullptr;
26038 int64_t Offset = 0;
26040 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26042 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26043 Offset += GA->getOffset();
26045 } else if (Op.getOpcode() == ISD::ADD) {
26046 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26047 Offset += C->getZExtValue();
26048 Op = Op.getOperand(0);
26051 } else if (Op.getOpcode() == ISD::SUB) {
26052 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26053 Offset += -C->getZExtValue();
26054 Op = Op.getOperand(0);
26059 // Otherwise, this isn't something we can handle, reject it.
26063 const GlobalValue *GV = GA->getGlobal();
26064 // If we require an extra load to get this address, as in PIC mode, we
26065 // can't accept it.
26066 if (isGlobalStubReference(
26067 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26070 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26071 GA->getValueType(0), Offset);
26076 if (Result.getNode()) {
26077 Ops.push_back(Result);
26080 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26083 std::pair<unsigned, const TargetRegisterClass*>
26084 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26086 // First, see if this is a constraint that directly corresponds to an LLVM
26088 if (Constraint.size() == 1) {
26089 // GCC Constraint Letters
26090 switch (Constraint[0]) {
26092 // TODO: Slight differences here in allocation order and leaving
26093 // RIP in the class. Do they matter any more here than they do
26094 // in the normal allocation?
26095 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26096 if (Subtarget->is64Bit()) {
26097 if (VT == MVT::i32 || VT == MVT::f32)
26098 return std::make_pair(0U, &X86::GR32RegClass);
26099 if (VT == MVT::i16)
26100 return std::make_pair(0U, &X86::GR16RegClass);
26101 if (VT == MVT::i8 || VT == MVT::i1)
26102 return std::make_pair(0U, &X86::GR8RegClass);
26103 if (VT == MVT::i64 || VT == MVT::f64)
26104 return std::make_pair(0U, &X86::GR64RegClass);
26107 // 32-bit fallthrough
26108 case 'Q': // Q_REGS
26109 if (VT == MVT::i32 || VT == MVT::f32)
26110 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26111 if (VT == MVT::i16)
26112 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26113 if (VT == MVT::i8 || VT == MVT::i1)
26114 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26115 if (VT == MVT::i64)
26116 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26118 case 'r': // GENERAL_REGS
26119 case 'l': // INDEX_REGS
26120 if (VT == MVT::i8 || VT == MVT::i1)
26121 return std::make_pair(0U, &X86::GR8RegClass);
26122 if (VT == MVT::i16)
26123 return std::make_pair(0U, &X86::GR16RegClass);
26124 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26125 return std::make_pair(0U, &X86::GR32RegClass);
26126 return std::make_pair(0U, &X86::GR64RegClass);
26127 case 'R': // LEGACY_REGS
26128 if (VT == MVT::i8 || VT == MVT::i1)
26129 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26130 if (VT == MVT::i16)
26131 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26132 if (VT == MVT::i32 || !Subtarget->is64Bit())
26133 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26134 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26135 case 'f': // FP Stack registers.
26136 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26137 // value to the correct fpstack register class.
26138 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26139 return std::make_pair(0U, &X86::RFP32RegClass);
26140 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26141 return std::make_pair(0U, &X86::RFP64RegClass);
26142 return std::make_pair(0U, &X86::RFP80RegClass);
26143 case 'y': // MMX_REGS if MMX allowed.
26144 if (!Subtarget->hasMMX()) break;
26145 return std::make_pair(0U, &X86::VR64RegClass);
26146 case 'Y': // SSE_REGS if SSE2 allowed
26147 if (!Subtarget->hasSSE2()) break;
26149 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26150 if (!Subtarget->hasSSE1()) break;
26152 switch (VT.SimpleTy) {
26154 // Scalar SSE types.
26157 return std::make_pair(0U, &X86::FR32RegClass);
26160 return std::make_pair(0U, &X86::FR64RegClass);
26168 return std::make_pair(0U, &X86::VR128RegClass);
26176 return std::make_pair(0U, &X86::VR256RegClass);
26181 return std::make_pair(0U, &X86::VR512RegClass);
26187 // Use the default implementation in TargetLowering to convert the register
26188 // constraint into a member of a register class.
26189 std::pair<unsigned, const TargetRegisterClass*> Res;
26190 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26192 // Not found as a standard register?
26194 // Map st(0) -> st(7) -> ST0
26195 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26196 tolower(Constraint[1]) == 's' &&
26197 tolower(Constraint[2]) == 't' &&
26198 Constraint[3] == '(' &&
26199 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26200 Constraint[5] == ')' &&
26201 Constraint[6] == '}') {
26203 Res.first = X86::FP0+Constraint[4]-'0';
26204 Res.second = &X86::RFP80RegClass;
26208 // GCC allows "st(0)" to be called just plain "st".
26209 if (StringRef("{st}").equals_lower(Constraint)) {
26210 Res.first = X86::FP0;
26211 Res.second = &X86::RFP80RegClass;
26216 if (StringRef("{flags}").equals_lower(Constraint)) {
26217 Res.first = X86::EFLAGS;
26218 Res.second = &X86::CCRRegClass;
26222 // 'A' means EAX + EDX.
26223 if (Constraint == "A") {
26224 Res.first = X86::EAX;
26225 Res.second = &X86::GR32_ADRegClass;
26231 // Otherwise, check to see if this is a register class of the wrong value
26232 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26233 // turn into {ax},{dx}.
26234 if (Res.second->hasType(VT))
26235 return Res; // Correct type already, nothing to do.
26237 // All of the single-register GCC register classes map their values onto
26238 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26239 // really want an 8-bit or 32-bit register, map to the appropriate register
26240 // class and return the appropriate register.
26241 if (Res.second == &X86::GR16RegClass) {
26242 if (VT == MVT::i8 || VT == MVT::i1) {
26243 unsigned DestReg = 0;
26244 switch (Res.first) {
26246 case X86::AX: DestReg = X86::AL; break;
26247 case X86::DX: DestReg = X86::DL; break;
26248 case X86::CX: DestReg = X86::CL; break;
26249 case X86::BX: DestReg = X86::BL; break;
26252 Res.first = DestReg;
26253 Res.second = &X86::GR8RegClass;
26255 } else if (VT == MVT::i32 || VT == MVT::f32) {
26256 unsigned DestReg = 0;
26257 switch (Res.first) {
26259 case X86::AX: DestReg = X86::EAX; break;
26260 case X86::DX: DestReg = X86::EDX; break;
26261 case X86::CX: DestReg = X86::ECX; break;
26262 case X86::BX: DestReg = X86::EBX; break;
26263 case X86::SI: DestReg = X86::ESI; break;
26264 case X86::DI: DestReg = X86::EDI; break;
26265 case X86::BP: DestReg = X86::EBP; break;
26266 case X86::SP: DestReg = X86::ESP; break;
26269 Res.first = DestReg;
26270 Res.second = &X86::GR32RegClass;
26272 } else if (VT == MVT::i64 || VT == MVT::f64) {
26273 unsigned DestReg = 0;
26274 switch (Res.first) {
26276 case X86::AX: DestReg = X86::RAX; break;
26277 case X86::DX: DestReg = X86::RDX; break;
26278 case X86::CX: DestReg = X86::RCX; break;
26279 case X86::BX: DestReg = X86::RBX; break;
26280 case X86::SI: DestReg = X86::RSI; break;
26281 case X86::DI: DestReg = X86::RDI; break;
26282 case X86::BP: DestReg = X86::RBP; break;
26283 case X86::SP: DestReg = X86::RSP; break;
26286 Res.first = DestReg;
26287 Res.second = &X86::GR64RegClass;
26290 } else if (Res.second == &X86::FR32RegClass ||
26291 Res.second == &X86::FR64RegClass ||
26292 Res.second == &X86::VR128RegClass ||
26293 Res.second == &X86::VR256RegClass ||
26294 Res.second == &X86::FR32XRegClass ||
26295 Res.second == &X86::FR64XRegClass ||
26296 Res.second == &X86::VR128XRegClass ||
26297 Res.second == &X86::VR256XRegClass ||
26298 Res.second == &X86::VR512RegClass) {
26299 // Handle references to XMM physical registers that got mapped into the
26300 // wrong class. This can happen with constraints like {xmm0} where the
26301 // target independent register mapper will just pick the first match it can
26302 // find, ignoring the required type.
26304 if (VT == MVT::f32 || VT == MVT::i32)
26305 Res.second = &X86::FR32RegClass;
26306 else if (VT == MVT::f64 || VT == MVT::i64)
26307 Res.second = &X86::FR64RegClass;
26308 else if (X86::VR128RegClass.hasType(VT))
26309 Res.second = &X86::VR128RegClass;
26310 else if (X86::VR256RegClass.hasType(VT))
26311 Res.second = &X86::VR256RegClass;
26312 else if (X86::VR512RegClass.hasType(VT))
26313 Res.second = &X86::VR512RegClass;
26319 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26321 // Scaling factors are not free at all.
26322 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26323 // will take 2 allocations in the out of order engine instead of 1
26324 // for plain addressing mode, i.e. inst (reg1).
26326 // vaddps (%rsi,%drx), %ymm0, %ymm1
26327 // Requires two allocations (one for the load, one for the computation)
26329 // vaddps (%rsi), %ymm0, %ymm1
26330 // Requires just 1 allocation, i.e., freeing allocations for other operations
26331 // and having less micro operations to execute.
26333 // For some X86 architectures, this is even worse because for instance for
26334 // stores, the complex addressing mode forces the instruction to use the
26335 // "load" ports instead of the dedicated "store" port.
26336 // E.g., on Haswell:
26337 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26338 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26339 if (isLegalAddressingMode(AM, Ty))
26340 // Scale represents reg2 * scale, thus account for 1
26341 // as soon as we use a second register.
26342 return AM.Scale != 0;
26346 bool X86TargetLowering::isTargetFTOL() const {
26347 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();