1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit bounday. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
171 unsigned IdxVal, SelectionDAG &DAG,
173 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
174 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
177 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
178 unsigned IdxVal, SelectionDAG &DAG,
180 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
181 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
184 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
185 /// instructions. This is used because creating CONCAT_VECTOR nodes of
186 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
187 /// large BUILD_VECTORS.
188 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
189 unsigned NumElems, SelectionDAG &DAG,
191 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
192 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
195 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
196 unsigned NumElems, SelectionDAG &DAG,
198 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
199 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
202 // FIXME: This should stop caching the target machine as soon as
203 // we can remove resetOperationActions et al.
204 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
205 : TargetLowering(TM, TM.getObjFileLowering()) {
206 Subtarget = &TM.getSubtarget<X86Subtarget>();
207 X86ScalarSSEf64 = Subtarget->hasSSE2();
208 X86ScalarSSEf32 = Subtarget->hasSSE1();
209 TD = getDataLayout();
211 resetOperationActions();
214 void X86TargetLowering::resetOperationActions() {
215 const TargetMachine &TM = getTargetMachine();
216 static bool FirstTimeThrough = true;
218 // If none of the target options have changed, then we don't need to reset the
219 // operation actions.
220 if (!FirstTimeThrough && TO == TM.Options) return;
222 if (!FirstTimeThrough) {
223 // Reinitialize the actions.
225 FirstTimeThrough = false;
230 // Set up the TargetLowering object.
231 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
233 // X86 is weird, it always uses i8 for shift amounts and setcc results.
234 setBooleanContents(ZeroOrOneBooleanContent);
235 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
236 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
238 // For 64-bit since we have so many registers use the ILP scheduler, for
239 // 32-bit code use the register pressure specific scheduling.
240 // For Atom, always use ILP scheduling.
241 if (Subtarget->isAtom())
242 setSchedulingPreference(Sched::ILP);
243 else if (Subtarget->is64Bit())
244 setSchedulingPreference(Sched::ILP);
246 setSchedulingPreference(Sched::RegPressure);
247 const X86RegisterInfo *RegInfo =
248 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
249 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
251 // Bypass expensive divides on Atom when compiling with O2
252 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
253 addBypassSlowDiv(32, 8);
254 if (Subtarget->is64Bit())
255 addBypassSlowDiv(64, 16);
258 if (Subtarget->isTargetKnownWindowsMSVC()) {
259 // Setup Windows compiler runtime calls.
260 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
261 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
262 setLibcallName(RTLIB::SREM_I64, "_allrem");
263 setLibcallName(RTLIB::UREM_I64, "_aullrem");
264 setLibcallName(RTLIB::MUL_I64, "_allmul");
265 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
266 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
268 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
269 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
271 // The _ftol2 runtime function has an unusual calling conv, which
272 // is modeled by a special pseudo-instruction.
273 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
274 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
275 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
276 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
279 if (Subtarget->isTargetDarwin()) {
280 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
281 setUseUnderscoreSetJmp(false);
282 setUseUnderscoreLongJmp(false);
283 } else if (Subtarget->isTargetWindowsGNU()) {
284 // MS runtime is weird: it exports _setjmp, but longjmp!
285 setUseUnderscoreSetJmp(true);
286 setUseUnderscoreLongJmp(false);
288 setUseUnderscoreSetJmp(true);
289 setUseUnderscoreLongJmp(true);
292 // Set up the register classes.
293 addRegisterClass(MVT::i8, &X86::GR8RegClass);
294 addRegisterClass(MVT::i16, &X86::GR16RegClass);
295 addRegisterClass(MVT::i32, &X86::GR32RegClass);
296 if (Subtarget->is64Bit())
297 addRegisterClass(MVT::i64, &X86::GR64RegClass);
299 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
301 // We don't accept any truncstore of integer registers.
302 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
303 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
304 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
305 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
306 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
307 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
309 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
311 // SETOEQ and SETUNE require checking two conditions.
312 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
313 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
314 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
315 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
316 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
317 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
319 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
321 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
322 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
325 if (Subtarget->is64Bit()) {
326 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 } else if (!TM.Options.UseSoftFloat) {
329 // We have an algorithm for SSE2->double, and we turn this into a
330 // 64-bit FILD followed by conditional FADD for other targets.
331 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
332 // We have an algorithm for SSE2, and we turn this into a 64-bit
333 // FILD for other targets.
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
337 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
339 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
342 if (!TM.Options.UseSoftFloat) {
343 // SSE has no i16 to fp conversion, only i32
344 if (X86ScalarSSEf32) {
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
346 // f32 and f64 cases are Legal, f80 case is not
347 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
357 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
358 // are Legal, f80 is custom lowered.
359 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
360 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
362 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
364 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
367 if (X86ScalarSSEf32) {
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
369 // f32 and f64 cases are Legal, f80 case is not
370 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
376 // Handle FP_TO_UINT by promoting the destination to a larger signed
378 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
379 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
382 if (Subtarget->is64Bit()) {
383 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
384 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
385 } else if (!TM.Options.UseSoftFloat) {
386 // Since AVX is a superset of SSE3, only check for SSE here.
387 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
388 // Expand FP_TO_UINT into a select.
389 // FIXME: We would like to use a Custom expander here eventually to do
390 // the optimal thing for SSE vs. the default expansion in the legalizer.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
393 // With SSE3 we can use fisttpll to convert to a signed i64; without
394 // SSE, we're stuck with a fistpll.
395 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
398 if (isTargetFTOL()) {
399 // Use the _ftol2 runtime function, which has a pseudo-instruction
400 // to handle its weird calling convention.
401 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
404 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
405 if (!X86ScalarSSEf64) {
406 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
407 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
408 if (Subtarget->is64Bit()) {
409 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
410 // Without SSE, i64->f64 goes through memory.
411 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
415 // Scalar integer divide and remainder are lowered to use operations that
416 // produce two results, to match the available instructions. This exposes
417 // the two-result form to trivial CSE, which is able to combine x/y and x%y
418 // into a single instruction.
420 // Scalar integer multiply-high is also lowered to use two-result
421 // operations, to match the available instructions. However, plain multiply
422 // (low) operations are left as Legal, as there are single-result
423 // instructions for this in x86. Using the two-result multiply instructions
424 // when both high and low results are needed must be arranged by dagcombine.
425 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
427 setOperationAction(ISD::MULHS, VT, Expand);
428 setOperationAction(ISD::MULHU, VT, Expand);
429 setOperationAction(ISD::SDIV, VT, Expand);
430 setOperationAction(ISD::UDIV, VT, Expand);
431 setOperationAction(ISD::SREM, VT, Expand);
432 setOperationAction(ISD::UREM, VT, Expand);
434 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
435 setOperationAction(ISD::ADDC, VT, Custom);
436 setOperationAction(ISD::ADDE, VT, Custom);
437 setOperationAction(ISD::SUBC, VT, Custom);
438 setOperationAction(ISD::SUBE, VT, Custom);
441 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
442 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
443 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
444 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
445 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
446 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
447 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
448 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
449 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
456 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
457 if (Subtarget->is64Bit())
458 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
461 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
462 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
463 setOperationAction(ISD::FREM , MVT::f32 , Expand);
464 setOperationAction(ISD::FREM , MVT::f64 , Expand);
465 setOperationAction(ISD::FREM , MVT::f80 , Expand);
466 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
468 // Promote the i8 variants and force them on up to i32 which has a shorter
470 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
471 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
473 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
474 if (Subtarget->hasBMI()) {
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
476 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
477 if (Subtarget->is64Bit())
478 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
480 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
481 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
482 if (Subtarget->is64Bit())
483 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
486 if (Subtarget->hasLZCNT()) {
487 // When promoting the i8 variants, force them to i32 for a shorter
489 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
490 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
492 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
494 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
495 if (Subtarget->is64Bit())
496 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
498 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
499 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
500 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
504 if (Subtarget->is64Bit()) {
505 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
510 // Special handling for half-precision floating point conversions.
511 // If we don't have F16C support, then lower half float conversions
512 // into library calls.
513 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
514 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
515 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
518 // There's never any support for operations beyond MVT::f32.
519 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
520 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
521 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
522 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
524 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
525 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
527 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
529 if (Subtarget->hasPOPCNT()) {
530 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
532 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
533 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
534 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
535 if (Subtarget->is64Bit())
536 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
539 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
541 if (!Subtarget->hasMOVBE())
542 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
544 // These should be promoted to a larger select which is supported.
545 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
546 // X86 wants to expand cmov itself.
547 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
548 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
549 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
550 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
552 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
553 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
555 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
556 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
558 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
559 if (Subtarget->is64Bit()) {
560 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
563 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
564 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
565 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
566 // support continuation, user-level threading, and etc.. As a result, no
567 // other SjLj exception interfaces are implemented and please don't build
568 // your own exception handling based on them.
569 // LLVM/Clang supports zero-cost DWARF exception handling.
570 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
571 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
574 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
575 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
576 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
577 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
578 if (Subtarget->is64Bit())
579 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
580 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
581 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
582 if (Subtarget->is64Bit()) {
583 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
584 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
585 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
586 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
587 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
589 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
590 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
591 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
592 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
593 if (Subtarget->is64Bit()) {
594 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
595 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
596 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
599 if (Subtarget->hasSSE1())
600 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
602 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
604 // Expand certain atomics
605 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
607 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
608 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
609 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
612 if (Subtarget->hasCmpxchg16b()) {
613 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
616 // FIXME - use subtarget debug flags
617 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
618 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
619 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
622 if (Subtarget->is64Bit()) {
623 setExceptionPointerRegister(X86::RAX);
624 setExceptionSelectorRegister(X86::RDX);
626 setExceptionPointerRegister(X86::EAX);
627 setExceptionSelectorRegister(X86::EDX);
629 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
630 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
632 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
633 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
635 setOperationAction(ISD::TRAP, MVT::Other, Legal);
636 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
638 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
639 setOperationAction(ISD::VASTART , MVT::Other, Custom);
640 setOperationAction(ISD::VAEND , MVT::Other, Expand);
641 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
642 // TargetInfo::X86_64ABIBuiltinVaList
643 setOperationAction(ISD::VAARG , MVT::Other, Custom);
644 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
646 // TargetInfo::CharPtrBuiltinVaList
647 setOperationAction(ISD::VAARG , MVT::Other, Expand);
648 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
651 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
652 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
654 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
656 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
657 // f32 and f64 use SSE.
658 // Set up the FP register classes.
659 addRegisterClass(MVT::f32, &X86::FR32RegClass);
660 addRegisterClass(MVT::f64, &X86::FR64RegClass);
662 // Use ANDPD to simulate FABS.
663 setOperationAction(ISD::FABS , MVT::f64, Custom);
664 setOperationAction(ISD::FABS , MVT::f32, Custom);
666 // Use XORP to simulate FNEG.
667 setOperationAction(ISD::FNEG , MVT::f64, Custom);
668 setOperationAction(ISD::FNEG , MVT::f32, Custom);
670 // Use ANDPD and ORPD to simulate FCOPYSIGN.
671 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
672 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
674 // Lower this to FGETSIGNx86 plus an AND.
675 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
676 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
678 // We don't support sin/cos/fmod
679 setOperationAction(ISD::FSIN , MVT::f64, Expand);
680 setOperationAction(ISD::FCOS , MVT::f64, Expand);
681 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
682 setOperationAction(ISD::FSIN , MVT::f32, Expand);
683 setOperationAction(ISD::FCOS , MVT::f32, Expand);
684 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
686 // Expand FP immediates into loads from the stack, except for the special
688 addLegalFPImmediate(APFloat(+0.0)); // xorpd
689 addLegalFPImmediate(APFloat(+0.0f)); // xorps
690 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
691 // Use SSE for f32, x87 for f64.
692 // Set up the FP register classes.
693 addRegisterClass(MVT::f32, &X86::FR32RegClass);
694 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
696 // Use ANDPS to simulate FABS.
697 setOperationAction(ISD::FABS , MVT::f32, Custom);
699 // Use XORP to simulate FNEG.
700 setOperationAction(ISD::FNEG , MVT::f32, Custom);
702 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
704 // Use ANDPS and ORPS to simulate FCOPYSIGN.
705 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
706 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
708 // We don't support sin/cos/fmod
709 setOperationAction(ISD::FSIN , MVT::f32, Expand);
710 setOperationAction(ISD::FCOS , MVT::f32, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
713 // Special cases we handle for FP constants.
714 addLegalFPImmediate(APFloat(+0.0f)); // xorps
715 addLegalFPImmediate(APFloat(+0.0)); // FLD0
716 addLegalFPImmediate(APFloat(+1.0)); // FLD1
717 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
718 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
720 if (!TM.Options.UnsafeFPMath) {
721 setOperationAction(ISD::FSIN , MVT::f64, Expand);
722 setOperationAction(ISD::FCOS , MVT::f64, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
725 } else if (!TM.Options.UseSoftFloat) {
726 // f32 and f64 in x87.
727 // Set up the FP register classes.
728 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
729 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
731 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
732 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
733 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
734 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
736 if (!TM.Options.UnsafeFPMath) {
737 setOperationAction(ISD::FSIN , MVT::f64, Expand);
738 setOperationAction(ISD::FSIN , MVT::f32, Expand);
739 setOperationAction(ISD::FCOS , MVT::f64, Expand);
740 setOperationAction(ISD::FCOS , MVT::f32, Expand);
741 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
742 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
744 addLegalFPImmediate(APFloat(+0.0)); // FLD0
745 addLegalFPImmediate(APFloat(+1.0)); // FLD1
746 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
747 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
748 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
749 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
750 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
751 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
754 // We don't support FMA.
755 setOperationAction(ISD::FMA, MVT::f64, Expand);
756 setOperationAction(ISD::FMA, MVT::f32, Expand);
758 // Long double always uses X87.
759 if (!TM.Options.UseSoftFloat) {
760 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
761 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
762 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
764 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
765 addLegalFPImmediate(TmpFlt); // FLD0
767 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
770 APFloat TmpFlt2(+1.0);
771 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
773 addLegalFPImmediate(TmpFlt2); // FLD1
774 TmpFlt2.changeSign();
775 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
778 if (!TM.Options.UnsafeFPMath) {
779 setOperationAction(ISD::FSIN , MVT::f80, Expand);
780 setOperationAction(ISD::FCOS , MVT::f80, Expand);
781 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
784 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
785 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
786 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
787 setOperationAction(ISD::FRINT, MVT::f80, Expand);
788 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
789 setOperationAction(ISD::FMA, MVT::f80, Expand);
792 // Always use a library call for pow.
793 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
794 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
795 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
797 setOperationAction(ISD::FLOG, MVT::f80, Expand);
798 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
799 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
800 setOperationAction(ISD::FEXP, MVT::f80, Expand);
801 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
802 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
803 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
805 // First set operation action for all vector types to either promote
806 // (for widening) or expand (for scalarization). Then we will selectively
807 // turn on ones that can be effectively codegen'd.
808 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
809 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
810 MVT VT = (MVT::SimpleValueType)i;
811 setOperationAction(ISD::ADD , VT, Expand);
812 setOperationAction(ISD::SUB , VT, Expand);
813 setOperationAction(ISD::FADD, VT, Expand);
814 setOperationAction(ISD::FNEG, VT, Expand);
815 setOperationAction(ISD::FSUB, VT, Expand);
816 setOperationAction(ISD::MUL , VT, Expand);
817 setOperationAction(ISD::FMUL, VT, Expand);
818 setOperationAction(ISD::SDIV, VT, Expand);
819 setOperationAction(ISD::UDIV, VT, Expand);
820 setOperationAction(ISD::FDIV, VT, Expand);
821 setOperationAction(ISD::SREM, VT, Expand);
822 setOperationAction(ISD::UREM, VT, Expand);
823 setOperationAction(ISD::LOAD, VT, Expand);
824 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
825 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
826 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
827 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
828 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
829 setOperationAction(ISD::FABS, VT, Expand);
830 setOperationAction(ISD::FSIN, VT, Expand);
831 setOperationAction(ISD::FSINCOS, VT, Expand);
832 setOperationAction(ISD::FCOS, VT, Expand);
833 setOperationAction(ISD::FSINCOS, VT, Expand);
834 setOperationAction(ISD::FREM, VT, Expand);
835 setOperationAction(ISD::FMA, VT, Expand);
836 setOperationAction(ISD::FPOWI, VT, Expand);
837 setOperationAction(ISD::FSQRT, VT, Expand);
838 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
839 setOperationAction(ISD::FFLOOR, VT, Expand);
840 setOperationAction(ISD::FCEIL, VT, Expand);
841 setOperationAction(ISD::FTRUNC, VT, Expand);
842 setOperationAction(ISD::FRINT, VT, Expand);
843 setOperationAction(ISD::FNEARBYINT, VT, Expand);
844 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
845 setOperationAction(ISD::MULHS, VT, Expand);
846 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
847 setOperationAction(ISD::MULHU, VT, Expand);
848 setOperationAction(ISD::SDIVREM, VT, Expand);
849 setOperationAction(ISD::UDIVREM, VT, Expand);
850 setOperationAction(ISD::FPOW, VT, Expand);
851 setOperationAction(ISD::CTPOP, VT, Expand);
852 setOperationAction(ISD::CTTZ, VT, Expand);
853 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
854 setOperationAction(ISD::CTLZ, VT, Expand);
855 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
856 setOperationAction(ISD::SHL, VT, Expand);
857 setOperationAction(ISD::SRA, VT, Expand);
858 setOperationAction(ISD::SRL, VT, Expand);
859 setOperationAction(ISD::ROTL, VT, Expand);
860 setOperationAction(ISD::ROTR, VT, Expand);
861 setOperationAction(ISD::BSWAP, VT, Expand);
862 setOperationAction(ISD::SETCC, VT, Expand);
863 setOperationAction(ISD::FLOG, VT, Expand);
864 setOperationAction(ISD::FLOG2, VT, Expand);
865 setOperationAction(ISD::FLOG10, VT, Expand);
866 setOperationAction(ISD::FEXP, VT, Expand);
867 setOperationAction(ISD::FEXP2, VT, Expand);
868 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
869 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
870 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
871 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
872 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
873 setOperationAction(ISD::TRUNCATE, VT, Expand);
874 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
875 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
876 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
877 setOperationAction(ISD::VSELECT, VT, Expand);
878 setOperationAction(ISD::SELECT_CC, VT, Expand);
879 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
880 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
881 setTruncStoreAction(VT,
882 (MVT::SimpleValueType)InnerVT, Expand);
883 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
884 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
886 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
887 // we have to deal with them whether we ask for Expansion or not. Setting
888 // Expand causes its own optimisation problems though, so leave them legal.
889 if (VT.getVectorElementType() == MVT::i1)
890 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
893 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
894 // with -msoft-float, disable use of MMX as well.
895 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
896 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
897 // No operations on x86mmx supported, everything uses intrinsics.
900 // MMX-sized vectors (other than x86mmx) are expected to be expanded
901 // into smaller operations.
902 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
903 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
904 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
905 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
906 setOperationAction(ISD::AND, MVT::v8i8, Expand);
907 setOperationAction(ISD::AND, MVT::v4i16, Expand);
908 setOperationAction(ISD::AND, MVT::v2i32, Expand);
909 setOperationAction(ISD::AND, MVT::v1i64, Expand);
910 setOperationAction(ISD::OR, MVT::v8i8, Expand);
911 setOperationAction(ISD::OR, MVT::v4i16, Expand);
912 setOperationAction(ISD::OR, MVT::v2i32, Expand);
913 setOperationAction(ISD::OR, MVT::v1i64, Expand);
914 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
915 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
916 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
917 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
918 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
921 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
922 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
923 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
924 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
925 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
926 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
927 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
928 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
929 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
930 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
932 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
933 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
935 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
936 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
937 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
938 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
939 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
940 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
941 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
942 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
943 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
944 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
945 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
946 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
947 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
950 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
951 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
953 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
954 // registers cannot be used even for integer operations.
955 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
956 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
957 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
958 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
960 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
961 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
962 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
963 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
964 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
965 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
966 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
967 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
968 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
969 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
970 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
971 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
972 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
973 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
974 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
975 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
976 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
977 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
978 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
979 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
980 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
981 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
983 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
984 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
985 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
986 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
988 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
989 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
994 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
995 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
996 MVT VT = (MVT::SimpleValueType)i;
997 // Do not attempt to custom lower non-power-of-2 vectors
998 if (!isPowerOf2_32(VT.getVectorNumElements()))
1000 // Do not attempt to custom lower non-128-bit vectors
1001 if (!VT.is128BitVector())
1003 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1004 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1008 // We support custom legalizing of sext and anyext loads for specific
1009 // memory vector types which we can load as a scalar (or sequence of
1010 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1011 // loads these must work with a single scalar load.
1012 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1013 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1014 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1015 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1017 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1018 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1022 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1023 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1024 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1025 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1026 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1027 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1029 if (Subtarget->is64Bit()) {
1030 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1031 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1034 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1035 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1036 MVT VT = (MVT::SimpleValueType)i;
1038 // Do not attempt to promote non-128-bit vectors
1039 if (!VT.is128BitVector())
1042 setOperationAction(ISD::AND, VT, Promote);
1043 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1044 setOperationAction(ISD::OR, VT, Promote);
1045 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1046 setOperationAction(ISD::XOR, VT, Promote);
1047 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1048 setOperationAction(ISD::LOAD, VT, Promote);
1049 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1050 setOperationAction(ISD::SELECT, VT, Promote);
1051 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1054 // Custom lower v2i64 and v2f64 selects.
1055 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1056 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1057 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1058 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1060 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1061 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1063 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1064 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1065 // As there is no 64-bit GPR available, we need build a special custom
1066 // sequence to convert from v2i32 to v2f32.
1067 if (!Subtarget->is64Bit())
1068 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1070 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1071 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1073 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1075 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1076 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1077 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1080 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1081 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1082 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1083 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1084 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1085 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1086 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1087 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1088 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1089 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1090 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1092 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1093 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1094 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1095 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1098 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1099 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1100 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1101 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1103 // FIXME: Do we need to handle scalar-to-vector here?
1104 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1106 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1107 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1108 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1109 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1110 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1111 // There is no BLENDI for byte vectors. We don't need to custom lower
1112 // some vselects for now.
1113 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1115 // SSE41 brings specific instructions for doing vector sign extend even in
1116 // cases where we don't have SRA.
1117 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1118 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1119 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1121 // i8 and i16 vectors are custom because the source register and source
1122 // source memory operand types are not the same width. f32 vectors are
1123 // custom since the immediate controlling the insert encodes additional
1125 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1128 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1130 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1133 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1135 // FIXME: these should be Legal, but that's only for the case where
1136 // the index is constant. For now custom expand to deal with that.
1137 if (Subtarget->is64Bit()) {
1138 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1143 if (Subtarget->hasSSE2()) {
1144 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1145 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1147 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1148 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1150 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1151 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1153 // In the customized shift lowering, the legal cases in AVX2 will be
1155 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1156 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1158 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1159 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1161 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1164 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1165 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1172 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1173 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1174 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1176 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1187 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1189 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1200 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1202 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1203 // even though v8i16 is a legal type.
1204 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1205 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1206 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1208 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1209 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1210 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1212 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1213 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1215 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1217 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1218 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1220 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1223 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1224 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1226 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1229 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1231 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1233 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1235 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1236 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1237 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1238 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1240 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1241 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1242 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1243 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1244 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1245 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1246 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1247 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1248 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1249 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1250 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1251 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1253 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1254 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1255 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1256 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1257 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1258 setOperationAction(ISD::FMA, MVT::f32, Legal);
1259 setOperationAction(ISD::FMA, MVT::f64, Legal);
1262 if (Subtarget->hasInt256()) {
1263 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1264 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1265 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1266 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1268 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1269 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1270 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1271 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1273 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1274 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1275 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1276 // Don't lower v32i8 because there is no 128-bit byte mul
1278 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1279 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1280 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1281 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1283 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1284 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1286 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1287 // when we have a 256bit-wide blend with immediate.
1288 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1290 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1291 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1292 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1293 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1295 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1296 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1297 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1298 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1300 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1301 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1302 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1303 // Don't lower v32i8 because there is no 128-bit byte mul
1306 // In the customized shift lowering, the legal cases in AVX2 will be
1308 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1309 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1311 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1312 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1314 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1316 // Custom lower several nodes for 256-bit types.
1317 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1318 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1319 MVT VT = (MVT::SimpleValueType)i;
1321 // Extract subvector is special because the value type
1322 // (result) is 128-bit but the source is 256-bit wide.
1323 if (VT.is128BitVector())
1324 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1326 // Do not attempt to custom lower other non-256-bit vectors
1327 if (!VT.is256BitVector())
1330 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1331 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1334 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1335 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1336 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1339 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1340 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1341 MVT VT = (MVT::SimpleValueType)i;
1343 // Do not attempt to promote non-256-bit vectors
1344 if (!VT.is256BitVector())
1347 setOperationAction(ISD::AND, VT, Promote);
1348 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1349 setOperationAction(ISD::OR, VT, Promote);
1350 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1351 setOperationAction(ISD::XOR, VT, Promote);
1352 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1353 setOperationAction(ISD::LOAD, VT, Promote);
1354 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1355 setOperationAction(ISD::SELECT, VT, Promote);
1356 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1360 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1361 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1362 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1363 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1364 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1366 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1367 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1368 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1370 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1371 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1372 setOperationAction(ISD::XOR, MVT::i1, Legal);
1373 setOperationAction(ISD::OR, MVT::i1, Legal);
1374 setOperationAction(ISD::AND, MVT::i1, Legal);
1375 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1376 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1377 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1378 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1379 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1380 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1382 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1383 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1384 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1385 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1386 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1387 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1389 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1390 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1391 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1392 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1393 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1394 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1395 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1398 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1399 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1400 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1401 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1402 if (Subtarget->is64Bit()) {
1403 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1404 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1408 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1409 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1410 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1411 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1412 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1414 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1415 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1417 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1420 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1421 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1423 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1429 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1437 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1444 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1445 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1447 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1449 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1451 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1453 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1455 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1459 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1460 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1462 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1463 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1465 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1467 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1468 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1470 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1471 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1473 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1476 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1477 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1478 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1480 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1481 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1483 if (Subtarget->hasCDI()) {
1484 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1485 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1488 // Custom lower several nodes.
1489 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1490 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1491 MVT VT = (MVT::SimpleValueType)i;
1493 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1494 // Extract subvector is special because the value type
1495 // (result) is 256/128-bit but the source is 512-bit wide.
1496 if (VT.is128BitVector() || VT.is256BitVector())
1497 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1499 if (VT.getVectorElementType() == MVT::i1)
1500 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1502 // Do not attempt to custom lower other non-512-bit vectors
1503 if (!VT.is512BitVector())
1506 if ( EltSize >= 32) {
1507 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1508 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1509 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1510 setOperationAction(ISD::VSELECT, VT, Legal);
1511 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1512 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1513 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1516 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1517 MVT VT = (MVT::SimpleValueType)i;
1519 // Do not attempt to promote non-256-bit vectors
1520 if (!VT.is512BitVector())
1523 setOperationAction(ISD::SELECT, VT, Promote);
1524 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1528 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1529 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1530 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1532 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1533 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1535 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1536 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1537 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1538 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1540 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1541 const MVT VT = (MVT::SimpleValueType)i;
1543 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1545 // Do not attempt to promote non-256-bit vectors
1546 if (!VT.is512BitVector())
1549 if ( EltSize < 32) {
1550 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1551 setOperationAction(ISD::VSELECT, VT, Legal);
1556 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1557 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1558 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1560 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1561 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1562 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1598 if (!Subtarget->is64Bit()) {
1599 // These libcalls are not available in 32-bit.
1600 setLibcallName(RTLIB::SHL_I128, nullptr);
1601 setLibcallName(RTLIB::SRL_I128, nullptr);
1602 setLibcallName(RTLIB::SRA_I128, nullptr);
1605 // Combine sin / cos into one node or libcall if possible.
1606 if (Subtarget->hasSinCos()) {
1607 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1608 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1609 if (Subtarget->isTargetDarwin()) {
1610 // For MacOSX, we don't want to the normal expansion of a libcall to
1611 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1613 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1614 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1618 if (Subtarget->isTargetWin64()) {
1619 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1620 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1621 setOperationAction(ISD::SREM, MVT::i128, Custom);
1622 setOperationAction(ISD::UREM, MVT::i128, Custom);
1623 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1624 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1627 // We have target-specific dag combine patterns for the following nodes:
1628 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1629 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1630 setTargetDAGCombine(ISD::VSELECT);
1631 setTargetDAGCombine(ISD::SELECT);
1632 setTargetDAGCombine(ISD::SHL);
1633 setTargetDAGCombine(ISD::SRA);
1634 setTargetDAGCombine(ISD::SRL);
1635 setTargetDAGCombine(ISD::OR);
1636 setTargetDAGCombine(ISD::AND);
1637 setTargetDAGCombine(ISD::ADD);
1638 setTargetDAGCombine(ISD::FADD);
1639 setTargetDAGCombine(ISD::FSUB);
1640 setTargetDAGCombine(ISD::FMA);
1641 setTargetDAGCombine(ISD::SUB);
1642 setTargetDAGCombine(ISD::LOAD);
1643 setTargetDAGCombine(ISD::STORE);
1644 setTargetDAGCombine(ISD::ZERO_EXTEND);
1645 setTargetDAGCombine(ISD::ANY_EXTEND);
1646 setTargetDAGCombine(ISD::SIGN_EXTEND);
1647 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1648 setTargetDAGCombine(ISD::TRUNCATE);
1649 setTargetDAGCombine(ISD::SINT_TO_FP);
1650 setTargetDAGCombine(ISD::SETCC);
1651 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1652 setTargetDAGCombine(ISD::BUILD_VECTOR);
1653 if (Subtarget->is64Bit())
1654 setTargetDAGCombine(ISD::MUL);
1655 setTargetDAGCombine(ISD::XOR);
1657 computeRegisterProperties();
1659 // On Darwin, -Os means optimize for size without hurting performance,
1660 // do not reduce the limit.
1661 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1662 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1663 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1664 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1665 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1666 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1667 setPrefLoopAlignment(4); // 2^4 bytes.
1669 // Predictable cmov don't hurt on atom because it's in-order.
1670 PredictableSelectIsExpensive = !Subtarget->isAtom();
1672 setPrefFunctionAlignment(4); // 2^4 bytes.
1674 verifyIntrinsicTables();
1677 // This has so far only been implemented for 64-bit MachO.
1678 bool X86TargetLowering::useLoadStackGuardNode() const {
1679 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1680 Subtarget->is64Bit();
1683 TargetLoweringBase::LegalizeTypeAction
1684 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1685 if (ExperimentalVectorWideningLegalization &&
1686 VT.getVectorNumElements() != 1 &&
1687 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1688 return TypeWidenVector;
1690 return TargetLoweringBase::getPreferredVectorAction(VT);
1693 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1695 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1697 const unsigned NumElts = VT.getVectorNumElements();
1698 const EVT EltVT = VT.getVectorElementType();
1699 if (VT.is512BitVector()) {
1700 if (Subtarget->hasAVX512())
1701 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1702 EltVT == MVT::f32 || EltVT == MVT::f64)
1704 case 8: return MVT::v8i1;
1705 case 16: return MVT::v16i1;
1707 if (Subtarget->hasBWI())
1708 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1710 case 32: return MVT::v32i1;
1711 case 64: return MVT::v64i1;
1715 if (VT.is256BitVector() || VT.is128BitVector()) {
1716 if (Subtarget->hasVLX())
1717 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1718 EltVT == MVT::f32 || EltVT == MVT::f64)
1720 case 2: return MVT::v2i1;
1721 case 4: return MVT::v4i1;
1722 case 8: return MVT::v8i1;
1724 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1725 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1727 case 8: return MVT::v8i1;
1728 case 16: return MVT::v16i1;
1729 case 32: return MVT::v32i1;
1733 return VT.changeVectorElementTypeToInteger();
1736 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1737 /// the desired ByVal argument alignment.
1738 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1741 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1742 if (VTy->getBitWidth() == 128)
1744 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1745 unsigned EltAlign = 0;
1746 getMaxByValAlign(ATy->getElementType(), EltAlign);
1747 if (EltAlign > MaxAlign)
1748 MaxAlign = EltAlign;
1749 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1750 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1751 unsigned EltAlign = 0;
1752 getMaxByValAlign(STy->getElementType(i), EltAlign);
1753 if (EltAlign > MaxAlign)
1754 MaxAlign = EltAlign;
1761 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1762 /// function arguments in the caller parameter area. For X86, aggregates
1763 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1764 /// are at 4-byte boundaries.
1765 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1766 if (Subtarget->is64Bit()) {
1767 // Max of 8 and alignment of type.
1768 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1775 if (Subtarget->hasSSE1())
1776 getMaxByValAlign(Ty, Align);
1780 /// getOptimalMemOpType - Returns the target specific optimal type for load
1781 /// and store operations as a result of memset, memcpy, and memmove
1782 /// lowering. If DstAlign is zero that means it's safe to destination
1783 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1784 /// means there isn't a need to check it against alignment requirement,
1785 /// probably because the source does not need to be loaded. If 'IsMemset' is
1786 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1787 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1788 /// source is constant so it does not need to be loaded.
1789 /// It returns EVT::Other if the type should be determined using generic
1790 /// target-independent logic.
1792 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1793 unsigned DstAlign, unsigned SrcAlign,
1794 bool IsMemset, bool ZeroMemset,
1796 MachineFunction &MF) const {
1797 const Function *F = MF.getFunction();
1798 if ((!IsMemset || ZeroMemset) &&
1799 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1800 Attribute::NoImplicitFloat)) {
1802 (Subtarget->isUnalignedMemAccessFast() ||
1803 ((DstAlign == 0 || DstAlign >= 16) &&
1804 (SrcAlign == 0 || SrcAlign >= 16)))) {
1806 if (Subtarget->hasInt256())
1808 if (Subtarget->hasFp256())
1811 if (Subtarget->hasSSE2())
1813 if (Subtarget->hasSSE1())
1815 } else if (!MemcpyStrSrc && Size >= 8 &&
1816 !Subtarget->is64Bit() &&
1817 Subtarget->hasSSE2()) {
1818 // Do not use f64 to lower memcpy if source is string constant. It's
1819 // better to use i32 to avoid the loads.
1823 if (Subtarget->is64Bit() && Size >= 8)
1828 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1830 return X86ScalarSSEf32;
1831 else if (VT == MVT::f64)
1832 return X86ScalarSSEf64;
1837 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1842 *Fast = Subtarget->isUnalignedMemAccessFast();
1846 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1847 /// current function. The returned value is a member of the
1848 /// MachineJumpTableInfo::JTEntryKind enum.
1849 unsigned X86TargetLowering::getJumpTableEncoding() const {
1850 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1852 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1853 Subtarget->isPICStyleGOT())
1854 return MachineJumpTableInfo::EK_Custom32;
1856 // Otherwise, use the normal jump table encoding heuristics.
1857 return TargetLowering::getJumpTableEncoding();
1861 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1862 const MachineBasicBlock *MBB,
1863 unsigned uid,MCContext &Ctx) const{
1864 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1865 Subtarget->isPICStyleGOT());
1866 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1868 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1869 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1872 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1874 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1875 SelectionDAG &DAG) const {
1876 if (!Subtarget->is64Bit())
1877 // This doesn't have SDLoc associated with it, but is not really the
1878 // same as a Register.
1879 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1883 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1884 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1886 const MCExpr *X86TargetLowering::
1887 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1888 MCContext &Ctx) const {
1889 // X86-64 uses RIP relative addressing based on the jump table label.
1890 if (Subtarget->isPICStyleRIPRel())
1891 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1893 // Otherwise, the reference is relative to the PIC base.
1894 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1897 // FIXME: Why this routine is here? Move to RegInfo!
1898 std::pair<const TargetRegisterClass*, uint8_t>
1899 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1900 const TargetRegisterClass *RRC = nullptr;
1902 switch (VT.SimpleTy) {
1904 return TargetLowering::findRepresentativeClass(VT);
1905 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1906 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1909 RRC = &X86::VR64RegClass;
1911 case MVT::f32: case MVT::f64:
1912 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1913 case MVT::v4f32: case MVT::v2f64:
1914 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1916 RRC = &X86::VR128RegClass;
1919 return std::make_pair(RRC, Cost);
1922 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1923 unsigned &Offset) const {
1924 if (!Subtarget->isTargetLinux())
1927 if (Subtarget->is64Bit()) {
1928 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1930 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1942 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1943 unsigned DestAS) const {
1944 assert(SrcAS != DestAS && "Expected different address spaces!");
1946 return SrcAS < 256 && DestAS < 256;
1949 //===----------------------------------------------------------------------===//
1950 // Return Value Calling Convention Implementation
1951 //===----------------------------------------------------------------------===//
1953 #include "X86GenCallingConv.inc"
1956 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1957 MachineFunction &MF, bool isVarArg,
1958 const SmallVectorImpl<ISD::OutputArg> &Outs,
1959 LLVMContext &Context) const {
1960 SmallVector<CCValAssign, 16> RVLocs;
1961 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1962 return CCInfo.CheckReturn(Outs, RetCC_X86);
1965 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1966 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1971 X86TargetLowering::LowerReturn(SDValue Chain,
1972 CallingConv::ID CallConv, bool isVarArg,
1973 const SmallVectorImpl<ISD::OutputArg> &Outs,
1974 const SmallVectorImpl<SDValue> &OutVals,
1975 SDLoc dl, SelectionDAG &DAG) const {
1976 MachineFunction &MF = DAG.getMachineFunction();
1977 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1979 SmallVector<CCValAssign, 16> RVLocs;
1980 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1981 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1984 SmallVector<SDValue, 6> RetOps;
1985 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1986 // Operand #1 = Bytes To Pop
1987 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1990 // Copy the result values into the output registers.
1991 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1992 CCValAssign &VA = RVLocs[i];
1993 assert(VA.isRegLoc() && "Can only return in registers!");
1994 SDValue ValToCopy = OutVals[i];
1995 EVT ValVT = ValToCopy.getValueType();
1997 // Promote values to the appropriate types
1998 if (VA.getLocInfo() == CCValAssign::SExt)
1999 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2000 else if (VA.getLocInfo() == CCValAssign::ZExt)
2001 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2002 else if (VA.getLocInfo() == CCValAssign::AExt)
2003 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2004 else if (VA.getLocInfo() == CCValAssign::BCvt)
2005 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2007 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2008 "Unexpected FP-extend for return value.");
2010 // If this is x86-64, and we disabled SSE, we can't return FP values,
2011 // or SSE or MMX vectors.
2012 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2013 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2014 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2015 report_fatal_error("SSE register return with SSE disabled");
2017 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2018 // llvm-gcc has never done it right and no one has noticed, so this
2019 // should be OK for now.
2020 if (ValVT == MVT::f64 &&
2021 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2022 report_fatal_error("SSE2 register return with SSE2 disabled");
2024 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2025 // the RET instruction and handled by the FP Stackifier.
2026 if (VA.getLocReg() == X86::FP0 ||
2027 VA.getLocReg() == X86::FP1) {
2028 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2029 // change the value to the FP stack register class.
2030 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2031 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2032 RetOps.push_back(ValToCopy);
2033 // Don't emit a copytoreg.
2037 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2038 // which is returned in RAX / RDX.
2039 if (Subtarget->is64Bit()) {
2040 if (ValVT == MVT::x86mmx) {
2041 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2042 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2043 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2045 // If we don't have SSE2 available, convert to v4f32 so the generated
2046 // register is legal.
2047 if (!Subtarget->hasSSE2())
2048 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2053 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2054 Flag = Chain.getValue(1);
2055 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2058 // The x86-64 ABIs require that for returning structs by value we copy
2059 // the sret argument into %rax/%eax (depending on ABI) for the return.
2060 // Win32 requires us to put the sret argument to %eax as well.
2061 // We saved the argument into a virtual register in the entry block,
2062 // so now we copy the value out and into %rax/%eax.
2063 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2064 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2065 MachineFunction &MF = DAG.getMachineFunction();
2066 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2067 unsigned Reg = FuncInfo->getSRetReturnReg();
2069 "SRetReturnReg should have been set in LowerFormalArguments().");
2070 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2073 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2074 X86::RAX : X86::EAX;
2075 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2076 Flag = Chain.getValue(1);
2078 // RAX/EAX now acts like a return value.
2079 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2082 RetOps[0] = Chain; // Update chain.
2084 // Add the flag if we have it.
2086 RetOps.push_back(Flag);
2088 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2091 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2092 if (N->getNumValues() != 1)
2094 if (!N->hasNUsesOfValue(1, 0))
2097 SDValue TCChain = Chain;
2098 SDNode *Copy = *N->use_begin();
2099 if (Copy->getOpcode() == ISD::CopyToReg) {
2100 // If the copy has a glue operand, we conservatively assume it isn't safe to
2101 // perform a tail call.
2102 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2104 TCChain = Copy->getOperand(0);
2105 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2108 bool HasRet = false;
2109 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2111 if (UI->getOpcode() != X86ISD::RET_FLAG)
2113 // If we are returning more than one value, we can definitely
2114 // not make a tail call see PR19530
2115 if (UI->getNumOperands() > 4)
2117 if (UI->getNumOperands() == 4 &&
2118 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2131 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2132 ISD::NodeType ExtendKind) const {
2134 // TODO: Is this also valid on 32-bit?
2135 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2136 ReturnMVT = MVT::i8;
2138 ReturnMVT = MVT::i32;
2140 EVT MinVT = getRegisterType(Context, ReturnMVT);
2141 return VT.bitsLT(MinVT) ? MinVT : VT;
2144 /// LowerCallResult - Lower the result values of a call into the
2145 /// appropriate copies out of appropriate physical registers.
2148 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2149 CallingConv::ID CallConv, bool isVarArg,
2150 const SmallVectorImpl<ISD::InputArg> &Ins,
2151 SDLoc dl, SelectionDAG &DAG,
2152 SmallVectorImpl<SDValue> &InVals) const {
2154 // Assign locations to each value returned by this call.
2155 SmallVector<CCValAssign, 16> RVLocs;
2156 bool Is64Bit = Subtarget->is64Bit();
2157 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2159 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2161 // Copy all of the result registers out of their specified physreg.
2162 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2163 CCValAssign &VA = RVLocs[i];
2164 EVT CopyVT = VA.getValVT();
2166 // If this is x86-64, and we disabled SSE, we can't return FP values
2167 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2168 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2169 report_fatal_error("SSE register return with SSE disabled");
2172 // If we prefer to use the value in xmm registers, copy it out as f80 and
2173 // use a truncate to move it from fp stack reg to xmm reg.
2174 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2175 isScalarFPTypeInSSEReg(VA.getValVT()))
2178 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2179 CopyVT, InFlag).getValue(1);
2180 SDValue Val = Chain.getValue(0);
2182 if (CopyVT != VA.getValVT())
2183 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2184 // This truncation won't change the value.
2185 DAG.getIntPtrConstant(1));
2187 InFlag = Chain.getValue(2);
2188 InVals.push_back(Val);
2194 //===----------------------------------------------------------------------===//
2195 // C & StdCall & Fast Calling Convention implementation
2196 //===----------------------------------------------------------------------===//
2197 // StdCall calling convention seems to be standard for many Windows' API
2198 // routines and around. It differs from C calling convention just a little:
2199 // callee should clean up the stack, not caller. Symbols should be also
2200 // decorated in some fancy way :) It doesn't support any vector arguments.
2201 // For info on fast calling convention see Fast Calling Convention (tail call)
2202 // implementation LowerX86_32FastCCCallTo.
2204 /// CallIsStructReturn - Determines whether a call uses struct return
2206 enum StructReturnType {
2211 static StructReturnType
2212 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2214 return NotStructReturn;
2216 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2217 if (!Flags.isSRet())
2218 return NotStructReturn;
2219 if (Flags.isInReg())
2220 return RegStructReturn;
2221 return StackStructReturn;
2224 /// ArgsAreStructReturn - Determines whether a function uses struct
2225 /// return semantics.
2226 static StructReturnType
2227 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2229 return NotStructReturn;
2231 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2232 if (!Flags.isSRet())
2233 return NotStructReturn;
2234 if (Flags.isInReg())
2235 return RegStructReturn;
2236 return StackStructReturn;
2239 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2240 /// by "Src" to address "Dst" with size and alignment information specified by
2241 /// the specific parameter attribute. The copy will be passed as a byval
2242 /// function parameter.
2244 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2245 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2247 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2249 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2250 /*isVolatile*/false, /*AlwaysInline=*/true,
2251 MachinePointerInfo(), MachinePointerInfo());
2254 /// IsTailCallConvention - Return true if the calling convention is one that
2255 /// supports tail call optimization.
2256 static bool IsTailCallConvention(CallingConv::ID CC) {
2257 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2258 CC == CallingConv::HiPE);
2261 /// \brief Return true if the calling convention is a C calling convention.
2262 static bool IsCCallConvention(CallingConv::ID CC) {
2263 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2264 CC == CallingConv::X86_64_SysV);
2267 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2268 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2272 CallingConv::ID CalleeCC = CS.getCallingConv();
2273 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2279 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2280 /// a tailcall target by changing its ABI.
2281 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2282 bool GuaranteedTailCallOpt) {
2283 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2287 X86TargetLowering::LowerMemArgument(SDValue Chain,
2288 CallingConv::ID CallConv,
2289 const SmallVectorImpl<ISD::InputArg> &Ins,
2290 SDLoc dl, SelectionDAG &DAG,
2291 const CCValAssign &VA,
2292 MachineFrameInfo *MFI,
2294 // Create the nodes corresponding to a load from this parameter slot.
2295 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2296 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2297 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2298 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2301 // If value is passed by pointer we have address passed instead of the value
2303 if (VA.getLocInfo() == CCValAssign::Indirect)
2304 ValVT = VA.getLocVT();
2306 ValVT = VA.getValVT();
2308 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2309 // changed with more analysis.
2310 // In case of tail call optimization mark all arguments mutable. Since they
2311 // could be overwritten by lowering of arguments in case of a tail call.
2312 if (Flags.isByVal()) {
2313 unsigned Bytes = Flags.getByValSize();
2314 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2315 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2316 return DAG.getFrameIndex(FI, getPointerTy());
2318 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2319 VA.getLocMemOffset(), isImmutable);
2320 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2321 return DAG.getLoad(ValVT, dl, Chain, FIN,
2322 MachinePointerInfo::getFixedStack(FI),
2323 false, false, false, 0);
2327 // FIXME: Get this from tablegen.
2328 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2329 const X86Subtarget *Subtarget) {
2330 assert(Subtarget->is64Bit());
2332 if (Subtarget->isCallingConvWin64(CallConv)) {
2333 static const MCPhysReg GPR64ArgRegsWin64[] = {
2334 X86::RCX, X86::RDX, X86::R8, X86::R9
2336 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2339 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2340 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2342 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2345 // FIXME: Get this from tablegen.
2346 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2347 CallingConv::ID CallConv,
2348 const X86Subtarget *Subtarget) {
2349 assert(Subtarget->is64Bit());
2350 if (Subtarget->isCallingConvWin64(CallConv)) {
2351 // The XMM registers which might contain var arg parameters are shadowed
2352 // in their paired GPR. So we only need to save the GPR to their home
2354 // TODO: __vectorcall will change this.
2358 const Function *Fn = MF.getFunction();
2359 bool NoImplicitFloatOps = Fn->getAttributes().
2360 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2361 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2362 "SSE register cannot be used when SSE is disabled!");
2363 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2364 !Subtarget->hasSSE1())
2365 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2369 static const MCPhysReg XMMArgRegs64Bit[] = {
2370 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2371 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2373 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2377 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2378 CallingConv::ID CallConv,
2380 const SmallVectorImpl<ISD::InputArg> &Ins,
2383 SmallVectorImpl<SDValue> &InVals)
2385 MachineFunction &MF = DAG.getMachineFunction();
2386 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2388 const Function* Fn = MF.getFunction();
2389 if (Fn->hasExternalLinkage() &&
2390 Subtarget->isTargetCygMing() &&
2391 Fn->getName() == "main")
2392 FuncInfo->setForceFramePointer(true);
2394 MachineFrameInfo *MFI = MF.getFrameInfo();
2395 bool Is64Bit = Subtarget->is64Bit();
2396 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2398 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2399 "Var args not supported with calling convention fastcc, ghc or hipe");
2401 // Assign locations to all of the incoming arguments.
2402 SmallVector<CCValAssign, 16> ArgLocs;
2403 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2405 // Allocate shadow area for Win64
2407 CCInfo.AllocateStack(32, 8);
2409 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2411 unsigned LastVal = ~0U;
2413 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2414 CCValAssign &VA = ArgLocs[i];
2415 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2417 assert(VA.getValNo() != LastVal &&
2418 "Don't support value assigned to multiple locs yet");
2420 LastVal = VA.getValNo();
2422 if (VA.isRegLoc()) {
2423 EVT RegVT = VA.getLocVT();
2424 const TargetRegisterClass *RC;
2425 if (RegVT == MVT::i32)
2426 RC = &X86::GR32RegClass;
2427 else if (Is64Bit && RegVT == MVT::i64)
2428 RC = &X86::GR64RegClass;
2429 else if (RegVT == MVT::f32)
2430 RC = &X86::FR32RegClass;
2431 else if (RegVT == MVT::f64)
2432 RC = &X86::FR64RegClass;
2433 else if (RegVT.is512BitVector())
2434 RC = &X86::VR512RegClass;
2435 else if (RegVT.is256BitVector())
2436 RC = &X86::VR256RegClass;
2437 else if (RegVT.is128BitVector())
2438 RC = &X86::VR128RegClass;
2439 else if (RegVT == MVT::x86mmx)
2440 RC = &X86::VR64RegClass;
2441 else if (RegVT == MVT::i1)
2442 RC = &X86::VK1RegClass;
2443 else if (RegVT == MVT::v8i1)
2444 RC = &X86::VK8RegClass;
2445 else if (RegVT == MVT::v16i1)
2446 RC = &X86::VK16RegClass;
2447 else if (RegVT == MVT::v32i1)
2448 RC = &X86::VK32RegClass;
2449 else if (RegVT == MVT::v64i1)
2450 RC = &X86::VK64RegClass;
2452 llvm_unreachable("Unknown argument type!");
2454 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2455 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2457 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2458 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2460 if (VA.getLocInfo() == CCValAssign::SExt)
2461 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2462 DAG.getValueType(VA.getValVT()));
2463 else if (VA.getLocInfo() == CCValAssign::ZExt)
2464 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::BCvt)
2467 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2469 if (VA.isExtInLoc()) {
2470 // Handle MMX values passed in XMM regs.
2471 if (RegVT.isVector())
2472 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2474 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2477 assert(VA.isMemLoc());
2478 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2481 // If value is passed via pointer - do a load.
2482 if (VA.getLocInfo() == CCValAssign::Indirect)
2483 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2484 MachinePointerInfo(), false, false, false, 0);
2486 InVals.push_back(ArgValue);
2489 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2490 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2491 // The x86-64 ABIs require that for returning structs by value we copy
2492 // the sret argument into %rax/%eax (depending on ABI) for the return.
2493 // Win32 requires us to put the sret argument to %eax as well.
2494 // Save the argument into a virtual register so that we can access it
2495 // from the return points.
2496 if (Ins[i].Flags.isSRet()) {
2497 unsigned Reg = FuncInfo->getSRetReturnReg();
2499 MVT PtrTy = getPointerTy();
2500 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2501 FuncInfo->setSRetReturnReg(Reg);
2503 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2504 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2510 unsigned StackSize = CCInfo.getNextStackOffset();
2511 // Align stack specially for tail calls.
2512 if (FuncIsMadeTailCallSafe(CallConv,
2513 MF.getTarget().Options.GuaranteedTailCallOpt))
2514 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2516 // If the function takes variable number of arguments, make a frame index for
2517 // the start of the first vararg value... for expansion of llvm.va_start. We
2518 // can skip this if there are no va_start calls.
2519 if (MFI->hasVAStart() &&
2520 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2521 CallConv != CallingConv::X86_ThisCall))) {
2522 FuncInfo->setVarArgsFrameIndex(
2523 MFI->CreateFixedObject(1, StackSize, true));
2526 // 64-bit calling conventions support varargs and register parameters, so we
2527 // have to do extra work to spill them in the prologue or forward them to
2529 if (Is64Bit && isVarArg &&
2530 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2531 // Find the first unallocated argument registers.
2532 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2533 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2534 unsigned NumIntRegs =
2535 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2536 unsigned NumXMMRegs =
2537 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2538 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2539 "SSE register cannot be used when SSE is disabled!");
2541 // Gather all the live in physical registers.
2542 SmallVector<SDValue, 6> LiveGPRs;
2543 SmallVector<SDValue, 8> LiveXMMRegs;
2545 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2546 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2548 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2550 if (!ArgXMMs.empty()) {
2551 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2552 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2553 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2554 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2555 LiveXMMRegs.push_back(
2556 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2560 // Store them to the va_list returned by va_start.
2561 if (MFI->hasVAStart()) {
2563 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2564 // Get to the caller-allocated home save location. Add 8 to account
2565 // for the return address.
2566 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2567 FuncInfo->setRegSaveFrameIndex(
2568 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2569 // Fixup to set vararg frame on shadow area (4 x i64).
2571 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2573 // For X86-64, if there are vararg parameters that are passed via
2574 // registers, then we must store them to their spots on the stack so
2575 // they may be loaded by deferencing the result of va_next.
2576 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2577 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2578 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2579 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2582 // Store the integer parameter registers.
2583 SmallVector<SDValue, 8> MemOps;
2584 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2586 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2587 for (SDValue Val : LiveGPRs) {
2588 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2589 DAG.getIntPtrConstant(Offset));
2591 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2592 MachinePointerInfo::getFixedStack(
2593 FuncInfo->getRegSaveFrameIndex(), Offset),
2595 MemOps.push_back(Store);
2599 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2600 // Now store the XMM (fp + vector) parameter registers.
2601 SmallVector<SDValue, 12> SaveXMMOps;
2602 SaveXMMOps.push_back(Chain);
2603 SaveXMMOps.push_back(ALVal);
2604 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2605 FuncInfo->getRegSaveFrameIndex()));
2606 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2607 FuncInfo->getVarArgsFPOffset()));
2608 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2610 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2611 MVT::Other, SaveXMMOps));
2614 if (!MemOps.empty())
2615 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2617 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2618 // to the liveout set on a musttail call.
2619 assert(MFI->hasMustTailInVarArgFunc());
2620 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2621 typedef X86MachineFunctionInfo::Forward Forward;
2623 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2625 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2626 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2627 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2630 if (!ArgXMMs.empty()) {
2632 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2633 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2634 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2636 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2638 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2639 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2641 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2647 // Some CCs need callee pop.
2648 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2649 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2650 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2652 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2653 // If this is an sret function, the return should pop the hidden pointer.
2654 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2655 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2656 argsAreStructReturn(Ins) == StackStructReturn)
2657 FuncInfo->setBytesToPopOnReturn(4);
2661 // RegSaveFrameIndex is X86-64 only.
2662 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2663 if (CallConv == CallingConv::X86_FastCall ||
2664 CallConv == CallingConv::X86_ThisCall)
2665 // fastcc functions can't have varargs.
2666 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2669 FuncInfo->setArgumentStackSize(StackSize);
2675 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2676 SDValue StackPtr, SDValue Arg,
2677 SDLoc dl, SelectionDAG &DAG,
2678 const CCValAssign &VA,
2679 ISD::ArgFlagsTy Flags) const {
2680 unsigned LocMemOffset = VA.getLocMemOffset();
2681 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2682 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2683 if (Flags.isByVal())
2684 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2686 return DAG.getStore(Chain, dl, Arg, PtrOff,
2687 MachinePointerInfo::getStack(LocMemOffset),
2691 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2692 /// optimization is performed and it is required.
2694 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2695 SDValue &OutRetAddr, SDValue Chain,
2696 bool IsTailCall, bool Is64Bit,
2697 int FPDiff, SDLoc dl) const {
2698 // Adjust the Return address stack slot.
2699 EVT VT = getPointerTy();
2700 OutRetAddr = getReturnAddressFrameIndex(DAG);
2702 // Load the "old" Return address.
2703 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2704 false, false, false, 0);
2705 return SDValue(OutRetAddr.getNode(), 1);
2708 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2709 /// optimization is performed and it is required (FPDiff!=0).
2710 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2711 SDValue Chain, SDValue RetAddrFrIdx,
2712 EVT PtrVT, unsigned SlotSize,
2713 int FPDiff, SDLoc dl) {
2714 // Store the return address to the appropriate stack slot.
2715 if (!FPDiff) return Chain;
2716 // Calculate the new stack slot for the return address.
2717 int NewReturnAddrFI =
2718 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2720 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2721 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2722 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2728 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2729 SmallVectorImpl<SDValue> &InVals) const {
2730 SelectionDAG &DAG = CLI.DAG;
2732 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2733 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2734 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2735 SDValue Chain = CLI.Chain;
2736 SDValue Callee = CLI.Callee;
2737 CallingConv::ID CallConv = CLI.CallConv;
2738 bool &isTailCall = CLI.IsTailCall;
2739 bool isVarArg = CLI.IsVarArg;
2741 MachineFunction &MF = DAG.getMachineFunction();
2742 bool Is64Bit = Subtarget->is64Bit();
2743 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2744 StructReturnType SR = callIsStructReturn(Outs);
2745 bool IsSibcall = false;
2746 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2748 if (MF.getTarget().Options.DisableTailCalls)
2751 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2753 // Force this to be a tail call. The verifier rules are enough to ensure
2754 // that we can lower this successfully without moving the return address
2757 } else if (isTailCall) {
2758 // Check if it's really possible to do a tail call.
2759 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2760 isVarArg, SR != NotStructReturn,
2761 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2762 Outs, OutVals, Ins, DAG);
2764 // Sibcalls are automatically detected tailcalls which do not require
2766 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2773 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2774 "Var args not supported with calling convention fastcc, ghc or hipe");
2776 // Analyze operands of the call, assigning locations to each operand.
2777 SmallVector<CCValAssign, 16> ArgLocs;
2778 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2780 // Allocate shadow area for Win64
2782 CCInfo.AllocateStack(32, 8);
2784 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2786 // Get a count of how many bytes are to be pushed on the stack.
2787 unsigned NumBytes = CCInfo.getNextStackOffset();
2789 // This is a sibcall. The memory operands are available in caller's
2790 // own caller's stack.
2792 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2793 IsTailCallConvention(CallConv))
2794 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2797 if (isTailCall && !IsSibcall && !IsMustTail) {
2798 // Lower arguments at fp - stackoffset + fpdiff.
2799 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2801 FPDiff = NumBytesCallerPushed - NumBytes;
2803 // Set the delta of movement of the returnaddr stackslot.
2804 // But only set if delta is greater than previous delta.
2805 if (FPDiff < X86Info->getTCReturnAddrDelta())
2806 X86Info->setTCReturnAddrDelta(FPDiff);
2809 unsigned NumBytesToPush = NumBytes;
2810 unsigned NumBytesToPop = NumBytes;
2812 // If we have an inalloca argument, all stack space has already been allocated
2813 // for us and be right at the top of the stack. We don't support multiple
2814 // arguments passed in memory when using inalloca.
2815 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2817 if (!ArgLocs.back().isMemLoc())
2818 report_fatal_error("cannot use inalloca attribute on a register "
2820 if (ArgLocs.back().getLocMemOffset() != 0)
2821 report_fatal_error("any parameter with the inalloca attribute must be "
2822 "the only memory argument");
2826 Chain = DAG.getCALLSEQ_START(
2827 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2829 SDValue RetAddrFrIdx;
2830 // Load return address for tail calls.
2831 if (isTailCall && FPDiff)
2832 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2833 Is64Bit, FPDiff, dl);
2835 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2836 SmallVector<SDValue, 8> MemOpChains;
2839 // Walk the register/memloc assignments, inserting copies/loads. In the case
2840 // of tail call optimization arguments are handle later.
2841 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2842 DAG.getSubtarget().getRegisterInfo());
2843 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2844 // Skip inalloca arguments, they have already been written.
2845 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2846 if (Flags.isInAlloca())
2849 CCValAssign &VA = ArgLocs[i];
2850 EVT RegVT = VA.getLocVT();
2851 SDValue Arg = OutVals[i];
2852 bool isByVal = Flags.isByVal();
2854 // Promote the value if needed.
2855 switch (VA.getLocInfo()) {
2856 default: llvm_unreachable("Unknown loc info!");
2857 case CCValAssign::Full: break;
2858 case CCValAssign::SExt:
2859 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2861 case CCValAssign::ZExt:
2862 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::AExt:
2865 if (RegVT.is128BitVector()) {
2866 // Special case: passing MMX values in XMM registers.
2867 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2868 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2869 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2871 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2873 case CCValAssign::BCvt:
2874 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2876 case CCValAssign::Indirect: {
2877 // Store the argument.
2878 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2879 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2880 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2881 MachinePointerInfo::getFixedStack(FI),
2888 if (VA.isRegLoc()) {
2889 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2890 if (isVarArg && IsWin64) {
2891 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2892 // shadow reg if callee is a varargs function.
2893 unsigned ShadowReg = 0;
2894 switch (VA.getLocReg()) {
2895 case X86::XMM0: ShadowReg = X86::RCX; break;
2896 case X86::XMM1: ShadowReg = X86::RDX; break;
2897 case X86::XMM2: ShadowReg = X86::R8; break;
2898 case X86::XMM3: ShadowReg = X86::R9; break;
2901 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2903 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2904 assert(VA.isMemLoc());
2905 if (!StackPtr.getNode())
2906 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2908 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2909 dl, DAG, VA, Flags));
2913 if (!MemOpChains.empty())
2914 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2916 if (Subtarget->isPICStyleGOT()) {
2917 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2920 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2921 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2923 // If we are tail calling and generating PIC/GOT style code load the
2924 // address of the callee into ECX. The value in ecx is used as target of
2925 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2926 // for tail calls on PIC/GOT architectures. Normally we would just put the
2927 // address of GOT into ebx and then call target@PLT. But for tail calls
2928 // ebx would be restored (since ebx is callee saved) before jumping to the
2931 // Note: The actual moving to ECX is done further down.
2932 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2933 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2934 !G->getGlobal()->hasProtectedVisibility())
2935 Callee = LowerGlobalAddress(Callee, DAG);
2936 else if (isa<ExternalSymbolSDNode>(Callee))
2937 Callee = LowerExternalSymbol(Callee, DAG);
2941 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2942 // From AMD64 ABI document:
2943 // For calls that may call functions that use varargs or stdargs
2944 // (prototype-less calls or calls to functions containing ellipsis (...) in
2945 // the declaration) %al is used as hidden argument to specify the number
2946 // of SSE registers used. The contents of %al do not need to match exactly
2947 // the number of registers, but must be an ubound on the number of SSE
2948 // registers used and is in the range 0 - 8 inclusive.
2950 // Count the number of XMM registers allocated.
2951 static const MCPhysReg XMMArgRegs[] = {
2952 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2953 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2955 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2956 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2957 && "SSE registers cannot be used when SSE is disabled");
2959 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2960 DAG.getConstant(NumXMMRegs, MVT::i8)));
2963 if (Is64Bit && isVarArg && IsMustTail) {
2964 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2965 for (const auto &F : Forwards) {
2966 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2967 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2971 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2972 // don't need this because the eligibility check rejects calls that require
2973 // shuffling arguments passed in memory.
2974 if (!IsSibcall && isTailCall) {
2975 // Force all the incoming stack arguments to be loaded from the stack
2976 // before any new outgoing arguments are stored to the stack, because the
2977 // outgoing stack slots may alias the incoming argument stack slots, and
2978 // the alias isn't otherwise explicit. This is slightly more conservative
2979 // than necessary, because it means that each store effectively depends
2980 // on every argument instead of just those arguments it would clobber.
2981 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2983 SmallVector<SDValue, 8> MemOpChains2;
2986 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2987 CCValAssign &VA = ArgLocs[i];
2990 assert(VA.isMemLoc());
2991 SDValue Arg = OutVals[i];
2992 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2993 // Skip inalloca arguments. They don't require any work.
2994 if (Flags.isInAlloca())
2996 // Create frame index.
2997 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2998 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2999 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3000 FIN = DAG.getFrameIndex(FI, getPointerTy());
3002 if (Flags.isByVal()) {
3003 // Copy relative to framepointer.
3004 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3005 if (!StackPtr.getNode())
3006 StackPtr = DAG.getCopyFromReg(Chain, dl,
3007 RegInfo->getStackRegister(),
3009 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3011 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3015 // Store relative to framepointer.
3016 MemOpChains2.push_back(
3017 DAG.getStore(ArgChain, dl, Arg, FIN,
3018 MachinePointerInfo::getFixedStack(FI),
3023 if (!MemOpChains2.empty())
3024 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3026 // Store the return address to the appropriate stack slot.
3027 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3028 getPointerTy(), RegInfo->getSlotSize(),
3032 // Build a sequence of copy-to-reg nodes chained together with token chain
3033 // and flag operands which copy the outgoing args into registers.
3035 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3036 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3037 RegsToPass[i].second, InFlag);
3038 InFlag = Chain.getValue(1);
3041 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3042 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3043 // In the 64-bit large code model, we have to make all calls
3044 // through a register, since the call instruction's 32-bit
3045 // pc-relative offset may not be large enough to hold the whole
3047 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3048 // If the callee is a GlobalAddress node (quite common, every direct call
3049 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3052 // We should use extra load for direct calls to dllimported functions in
3054 const GlobalValue *GV = G->getGlobal();
3055 if (!GV->hasDLLImportStorageClass()) {
3056 unsigned char OpFlags = 0;
3057 bool ExtraLoad = false;
3058 unsigned WrapperKind = ISD::DELETED_NODE;
3060 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3061 // external symbols most go through the PLT in PIC mode. If the symbol
3062 // has hidden or protected visibility, or if it is static or local, then
3063 // we don't need to use the PLT - we can directly call it.
3064 if (Subtarget->isTargetELF() &&
3065 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3066 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3067 OpFlags = X86II::MO_PLT;
3068 } else if (Subtarget->isPICStyleStubAny() &&
3069 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3070 (!Subtarget->getTargetTriple().isMacOSX() ||
3071 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3072 // PC-relative references to external symbols should go through $stub,
3073 // unless we're building with the leopard linker or later, which
3074 // automatically synthesizes these stubs.
3075 OpFlags = X86II::MO_DARWIN_STUB;
3076 } else if (Subtarget->isPICStyleRIPRel() &&
3077 isa<Function>(GV) &&
3078 cast<Function>(GV)->getAttributes().
3079 hasAttribute(AttributeSet::FunctionIndex,
3080 Attribute::NonLazyBind)) {
3081 // If the function is marked as non-lazy, generate an indirect call
3082 // which loads from the GOT directly. This avoids runtime overhead
3083 // at the cost of eager binding (and one extra byte of encoding).
3084 OpFlags = X86II::MO_GOTPCREL;
3085 WrapperKind = X86ISD::WrapperRIP;
3089 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3090 G->getOffset(), OpFlags);
3092 // Add a wrapper if needed.
3093 if (WrapperKind != ISD::DELETED_NODE)
3094 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3095 // Add extra indirection if needed.
3097 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3098 MachinePointerInfo::getGOT(),
3099 false, false, false, 0);
3101 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3102 unsigned char OpFlags = 0;
3104 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3105 // external symbols should go through the PLT.
3106 if (Subtarget->isTargetELF() &&
3107 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3108 OpFlags = X86II::MO_PLT;
3109 } else if (Subtarget->isPICStyleStubAny() &&
3110 (!Subtarget->getTargetTriple().isMacOSX() ||
3111 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3112 // PC-relative references to external symbols should go through $stub,
3113 // unless we're building with the leopard linker or later, which
3114 // automatically synthesizes these stubs.
3115 OpFlags = X86II::MO_DARWIN_STUB;
3118 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3120 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3121 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3122 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3125 // Returns a chain & a flag for retval copy to use.
3126 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3127 SmallVector<SDValue, 8> Ops;
3129 if (!IsSibcall && isTailCall) {
3130 Chain = DAG.getCALLSEQ_END(Chain,
3131 DAG.getIntPtrConstant(NumBytesToPop, true),
3132 DAG.getIntPtrConstant(0, true), InFlag, dl);
3133 InFlag = Chain.getValue(1);
3136 Ops.push_back(Chain);
3137 Ops.push_back(Callee);
3140 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3142 // Add argument registers to the end of the list so that they are known live
3144 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3145 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3146 RegsToPass[i].second.getValueType()));
3148 // Add a register mask operand representing the call-preserved registers.
3149 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3150 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3151 assert(Mask && "Missing call preserved mask for calling convention");
3152 Ops.push_back(DAG.getRegisterMask(Mask));
3154 if (InFlag.getNode())
3155 Ops.push_back(InFlag);
3159 //// If this is the first return lowered for this function, add the regs
3160 //// to the liveout set for the function.
3161 // This isn't right, although it's probably harmless on x86; liveouts
3162 // should be computed from returns not tail calls. Consider a void
3163 // function making a tail call to a function returning int.
3164 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3167 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3168 InFlag = Chain.getValue(1);
3170 // Create the CALLSEQ_END node.
3171 unsigned NumBytesForCalleeToPop;
3172 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3173 DAG.getTarget().Options.GuaranteedTailCallOpt))
3174 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3175 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3176 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3177 SR == StackStructReturn)
3178 // If this is a call to a struct-return function, the callee
3179 // pops the hidden struct pointer, so we have to push it back.
3180 // This is common for Darwin/X86, Linux & Mingw32 targets.
3181 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3182 NumBytesForCalleeToPop = 4;
3184 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3186 // Returns a flag for retval copy to use.
3188 Chain = DAG.getCALLSEQ_END(Chain,
3189 DAG.getIntPtrConstant(NumBytesToPop, true),
3190 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3193 InFlag = Chain.getValue(1);
3196 // Handle result values, copying them out of physregs into vregs that we
3198 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3199 Ins, dl, DAG, InVals);
3202 //===----------------------------------------------------------------------===//
3203 // Fast Calling Convention (tail call) implementation
3204 //===----------------------------------------------------------------------===//
3206 // Like std call, callee cleans arguments, convention except that ECX is
3207 // reserved for storing the tail called function address. Only 2 registers are
3208 // free for argument passing (inreg). Tail call optimization is performed
3210 // * tailcallopt is enabled
3211 // * caller/callee are fastcc
3212 // On X86_64 architecture with GOT-style position independent code only local
3213 // (within module) calls are supported at the moment.
3214 // To keep the stack aligned according to platform abi the function
3215 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3216 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3217 // If a tail called function callee has more arguments than the caller the
3218 // caller needs to make sure that there is room to move the RETADDR to. This is
3219 // achieved by reserving an area the size of the argument delta right after the
3220 // original RETADDR, but before the saved framepointer or the spilled registers
3221 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3233 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3234 /// for a 16 byte align requirement.
3236 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3237 SelectionDAG& DAG) const {
3238 MachineFunction &MF = DAG.getMachineFunction();
3239 const TargetMachine &TM = MF.getTarget();
3240 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3241 TM.getSubtargetImpl()->getRegisterInfo());
3242 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3243 unsigned StackAlignment = TFI.getStackAlignment();
3244 uint64_t AlignMask = StackAlignment - 1;
3245 int64_t Offset = StackSize;
3246 unsigned SlotSize = RegInfo->getSlotSize();
3247 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3248 // Number smaller than 12 so just add the difference.
3249 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3251 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3252 Offset = ((~AlignMask) & Offset) + StackAlignment +
3253 (StackAlignment-SlotSize);
3258 /// MatchingStackOffset - Return true if the given stack call argument is
3259 /// already available in the same position (relatively) of the caller's
3260 /// incoming argument stack.
3262 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3263 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3264 const X86InstrInfo *TII) {
3265 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3267 if (Arg.getOpcode() == ISD::CopyFromReg) {
3268 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3269 if (!TargetRegisterInfo::isVirtualRegister(VR))
3271 MachineInstr *Def = MRI->getVRegDef(VR);
3274 if (!Flags.isByVal()) {
3275 if (!TII->isLoadFromStackSlot(Def, FI))
3278 unsigned Opcode = Def->getOpcode();
3279 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3280 Def->getOperand(1).isFI()) {
3281 FI = Def->getOperand(1).getIndex();
3282 Bytes = Flags.getByValSize();
3286 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3287 if (Flags.isByVal())
3288 // ByVal argument is passed in as a pointer but it's now being
3289 // dereferenced. e.g.
3290 // define @foo(%struct.X* %A) {
3291 // tail call @bar(%struct.X* byval %A)
3294 SDValue Ptr = Ld->getBasePtr();
3295 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3298 FI = FINode->getIndex();
3299 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3300 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3301 FI = FINode->getIndex();
3302 Bytes = Flags.getByValSize();
3306 assert(FI != INT_MAX);
3307 if (!MFI->isFixedObjectIndex(FI))
3309 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3312 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3313 /// for tail call optimization. Targets which want to do tail call
3314 /// optimization should implement this function.
3316 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3317 CallingConv::ID CalleeCC,
3319 bool isCalleeStructRet,
3320 bool isCallerStructRet,
3322 const SmallVectorImpl<ISD::OutputArg> &Outs,
3323 const SmallVectorImpl<SDValue> &OutVals,
3324 const SmallVectorImpl<ISD::InputArg> &Ins,
3325 SelectionDAG &DAG) const {
3326 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3329 // If -tailcallopt is specified, make fastcc functions tail-callable.
3330 const MachineFunction &MF = DAG.getMachineFunction();
3331 const Function *CallerF = MF.getFunction();
3333 // If the function return type is x86_fp80 and the callee return type is not,
3334 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3335 // perform a tailcall optimization here.
3336 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3339 CallingConv::ID CallerCC = CallerF->getCallingConv();
3340 bool CCMatch = CallerCC == CalleeCC;
3341 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3342 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3344 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3345 if (IsTailCallConvention(CalleeCC) && CCMatch)
3350 // Look for obvious safe cases to perform tail call optimization that do not
3351 // require ABI changes. This is what gcc calls sibcall.
3353 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3354 // emit a special epilogue.
3355 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3356 DAG.getSubtarget().getRegisterInfo());
3357 if (RegInfo->needsStackRealignment(MF))
3360 // Also avoid sibcall optimization if either caller or callee uses struct
3361 // return semantics.
3362 if (isCalleeStructRet || isCallerStructRet)
3365 // An stdcall/thiscall caller is expected to clean up its arguments; the
3366 // callee isn't going to do that.
3367 // FIXME: this is more restrictive than needed. We could produce a tailcall
3368 // when the stack adjustment matches. For example, with a thiscall that takes
3369 // only one argument.
3370 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3371 CallerCC == CallingConv::X86_ThisCall))
3374 // Do not sibcall optimize vararg calls unless all arguments are passed via
3376 if (isVarArg && !Outs.empty()) {
3378 // Optimizing for varargs on Win64 is unlikely to be safe without
3379 // additional testing.
3380 if (IsCalleeWin64 || IsCallerWin64)
3383 SmallVector<CCValAssign, 16> ArgLocs;
3384 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3387 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3388 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3389 if (!ArgLocs[i].isRegLoc())
3393 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3394 // stack. Therefore, if it's not used by the call it is not safe to optimize
3395 // this into a sibcall.
3396 bool Unused = false;
3397 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3404 SmallVector<CCValAssign, 16> RVLocs;
3405 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3407 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3408 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3409 CCValAssign &VA = RVLocs[i];
3410 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3415 // If the calling conventions do not match, then we'd better make sure the
3416 // results are returned in the same way as what the caller expects.
3418 SmallVector<CCValAssign, 16> RVLocs1;
3419 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3421 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3423 SmallVector<CCValAssign, 16> RVLocs2;
3424 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3426 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3428 if (RVLocs1.size() != RVLocs2.size())
3430 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3431 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3433 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3435 if (RVLocs1[i].isRegLoc()) {
3436 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3439 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3445 // If the callee takes no arguments then go on to check the results of the
3447 if (!Outs.empty()) {
3448 // Check if stack adjustment is needed. For now, do not do this if any
3449 // argument is passed on the stack.
3450 SmallVector<CCValAssign, 16> ArgLocs;
3451 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3454 // Allocate shadow area for Win64
3456 CCInfo.AllocateStack(32, 8);
3458 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3459 if (CCInfo.getNextStackOffset()) {
3460 MachineFunction &MF = DAG.getMachineFunction();
3461 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3464 // Check if the arguments are already laid out in the right way as
3465 // the caller's fixed stack objects.
3466 MachineFrameInfo *MFI = MF.getFrameInfo();
3467 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3468 const X86InstrInfo *TII =
3469 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3470 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3471 CCValAssign &VA = ArgLocs[i];
3472 SDValue Arg = OutVals[i];
3473 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3474 if (VA.getLocInfo() == CCValAssign::Indirect)
3476 if (!VA.isRegLoc()) {
3477 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3484 // If the tailcall address may be in a register, then make sure it's
3485 // possible to register allocate for it. In 32-bit, the call address can
3486 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3487 // callee-saved registers are restored. These happen to be the same
3488 // registers used to pass 'inreg' arguments so watch out for those.
3489 if (!Subtarget->is64Bit() &&
3490 ((!isa<GlobalAddressSDNode>(Callee) &&
3491 !isa<ExternalSymbolSDNode>(Callee)) ||
3492 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3493 unsigned NumInRegs = 0;
3494 // In PIC we need an extra register to formulate the address computation
3496 unsigned MaxInRegs =
3497 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3499 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3500 CCValAssign &VA = ArgLocs[i];
3503 unsigned Reg = VA.getLocReg();
3506 case X86::EAX: case X86::EDX: case X86::ECX:
3507 if (++NumInRegs == MaxInRegs)
3519 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3520 const TargetLibraryInfo *libInfo) const {
3521 return X86::createFastISel(funcInfo, libInfo);
3524 //===----------------------------------------------------------------------===//
3525 // Other Lowering Hooks
3526 //===----------------------------------------------------------------------===//
3528 static bool MayFoldLoad(SDValue Op) {
3529 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3532 static bool MayFoldIntoStore(SDValue Op) {
3533 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3536 static bool isTargetShuffle(unsigned Opcode) {
3538 default: return false;
3539 case X86ISD::BLENDI:
3540 case X86ISD::PSHUFB:
3541 case X86ISD::PSHUFD:
3542 case X86ISD::PSHUFHW:
3543 case X86ISD::PSHUFLW:
3545 case X86ISD::PALIGNR:
3546 case X86ISD::MOVLHPS:
3547 case X86ISD::MOVLHPD:
3548 case X86ISD::MOVHLPS:
3549 case X86ISD::MOVLPS:
3550 case X86ISD::MOVLPD:
3551 case X86ISD::MOVSHDUP:
3552 case X86ISD::MOVSLDUP:
3553 case X86ISD::MOVDDUP:
3556 case X86ISD::UNPCKL:
3557 case X86ISD::UNPCKH:
3558 case X86ISD::VPERMILPI:
3559 case X86ISD::VPERM2X128:
3560 case X86ISD::VPERMI:
3565 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3566 SDValue V1, SelectionDAG &DAG) {
3568 default: llvm_unreachable("Unknown x86 shuffle node");
3569 case X86ISD::MOVSHDUP:
3570 case X86ISD::MOVSLDUP:
3571 case X86ISD::MOVDDUP:
3572 return DAG.getNode(Opc, dl, VT, V1);
3576 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3577 SDValue V1, unsigned TargetMask,
3578 SelectionDAG &DAG) {
3580 default: llvm_unreachable("Unknown x86 shuffle node");
3581 case X86ISD::PSHUFD:
3582 case X86ISD::PSHUFHW:
3583 case X86ISD::PSHUFLW:
3584 case X86ISD::VPERMILPI:
3585 case X86ISD::VPERMI:
3586 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3590 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3591 SDValue V1, SDValue V2, unsigned TargetMask,
3592 SelectionDAG &DAG) {
3594 default: llvm_unreachable("Unknown x86 shuffle node");
3595 case X86ISD::PALIGNR:
3596 case X86ISD::VALIGN:
3598 case X86ISD::VPERM2X128:
3599 return DAG.getNode(Opc, dl, VT, V1, V2,
3600 DAG.getConstant(TargetMask, MVT::i8));
3604 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3605 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3607 default: llvm_unreachable("Unknown x86 shuffle node");
3608 case X86ISD::MOVLHPS:
3609 case X86ISD::MOVLHPD:
3610 case X86ISD::MOVHLPS:
3611 case X86ISD::MOVLPS:
3612 case X86ISD::MOVLPD:
3615 case X86ISD::UNPCKL:
3616 case X86ISD::UNPCKH:
3617 return DAG.getNode(Opc, dl, VT, V1, V2);
3621 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3622 MachineFunction &MF = DAG.getMachineFunction();
3623 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3624 DAG.getSubtarget().getRegisterInfo());
3625 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3626 int ReturnAddrIndex = FuncInfo->getRAIndex();
3628 if (ReturnAddrIndex == 0) {
3629 // Set up a frame object for the return address.
3630 unsigned SlotSize = RegInfo->getSlotSize();
3631 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3634 FuncInfo->setRAIndex(ReturnAddrIndex);
3637 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3640 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3641 bool hasSymbolicDisplacement) {
3642 // Offset should fit into 32 bit immediate field.
3643 if (!isInt<32>(Offset))
3646 // If we don't have a symbolic displacement - we don't have any extra
3648 if (!hasSymbolicDisplacement)
3651 // FIXME: Some tweaks might be needed for medium code model.
3652 if (M != CodeModel::Small && M != CodeModel::Kernel)
3655 // For small code model we assume that latest object is 16MB before end of 31
3656 // bits boundary. We may also accept pretty large negative constants knowing
3657 // that all objects are in the positive half of address space.
3658 if (M == CodeModel::Small && Offset < 16*1024*1024)
3661 // For kernel code model we know that all object resist in the negative half
3662 // of 32bits address space. We may not accept negative offsets, since they may
3663 // be just off and we may accept pretty large positive ones.
3664 if (M == CodeModel::Kernel && Offset > 0)
3670 /// isCalleePop - Determines whether the callee is required to pop its
3671 /// own arguments. Callee pop is necessary to support tail calls.
3672 bool X86::isCalleePop(CallingConv::ID CallingConv,
3673 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3674 switch (CallingConv) {
3677 case CallingConv::X86_StdCall:
3678 case CallingConv::X86_FastCall:
3679 case CallingConv::X86_ThisCall:
3681 case CallingConv::Fast:
3682 case CallingConv::GHC:
3683 case CallingConv::HiPE:
3690 /// \brief Return true if the condition is an unsigned comparison operation.
3691 static bool isX86CCUnsigned(unsigned X86CC) {
3693 default: llvm_unreachable("Invalid integer condition!");
3694 case X86::COND_E: return true;
3695 case X86::COND_G: return false;
3696 case X86::COND_GE: return false;
3697 case X86::COND_L: return false;
3698 case X86::COND_LE: return false;
3699 case X86::COND_NE: return true;
3700 case X86::COND_B: return true;
3701 case X86::COND_A: return true;
3702 case X86::COND_BE: return true;
3703 case X86::COND_AE: return true;
3705 llvm_unreachable("covered switch fell through?!");
3708 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3709 /// specific condition code, returning the condition code and the LHS/RHS of the
3710 /// comparison to make.
3711 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3712 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3714 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3715 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3716 // X > -1 -> X == 0, jump !sign.
3717 RHS = DAG.getConstant(0, RHS.getValueType());
3718 return X86::COND_NS;
3720 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3721 // X < 0 -> X == 0, jump on sign.
3724 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3726 RHS = DAG.getConstant(0, RHS.getValueType());
3727 return X86::COND_LE;
3731 switch (SetCCOpcode) {
3732 default: llvm_unreachable("Invalid integer condition!");
3733 case ISD::SETEQ: return X86::COND_E;
3734 case ISD::SETGT: return X86::COND_G;
3735 case ISD::SETGE: return X86::COND_GE;
3736 case ISD::SETLT: return X86::COND_L;
3737 case ISD::SETLE: return X86::COND_LE;
3738 case ISD::SETNE: return X86::COND_NE;
3739 case ISD::SETULT: return X86::COND_B;
3740 case ISD::SETUGT: return X86::COND_A;
3741 case ISD::SETULE: return X86::COND_BE;
3742 case ISD::SETUGE: return X86::COND_AE;
3746 // First determine if it is required or is profitable to flip the operands.
3748 // If LHS is a foldable load, but RHS is not, flip the condition.
3749 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3750 !ISD::isNON_EXTLoad(RHS.getNode())) {
3751 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3752 std::swap(LHS, RHS);
3755 switch (SetCCOpcode) {
3761 std::swap(LHS, RHS);
3765 // On a floating point condition, the flags are set as follows:
3767 // 0 | 0 | 0 | X > Y
3768 // 0 | 0 | 1 | X < Y
3769 // 1 | 0 | 0 | X == Y
3770 // 1 | 1 | 1 | unordered
3771 switch (SetCCOpcode) {
3772 default: llvm_unreachable("Condcode should be pre-legalized away");
3774 case ISD::SETEQ: return X86::COND_E;
3775 case ISD::SETOLT: // flipped
3777 case ISD::SETGT: return X86::COND_A;
3778 case ISD::SETOLE: // flipped
3780 case ISD::SETGE: return X86::COND_AE;
3781 case ISD::SETUGT: // flipped
3783 case ISD::SETLT: return X86::COND_B;
3784 case ISD::SETUGE: // flipped
3786 case ISD::SETLE: return X86::COND_BE;
3788 case ISD::SETNE: return X86::COND_NE;
3789 case ISD::SETUO: return X86::COND_P;
3790 case ISD::SETO: return X86::COND_NP;
3792 case ISD::SETUNE: return X86::COND_INVALID;
3796 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3797 /// code. Current x86 isa includes the following FP cmov instructions:
3798 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3799 static bool hasFPCMov(unsigned X86CC) {
3815 /// isFPImmLegal - Returns true if the target can instruction select the
3816 /// specified FP immediate natively. If false, the legalizer will
3817 /// materialize the FP immediate as a load from a constant pool.
3818 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3819 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3820 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3826 /// \brief Returns true if it is beneficial to convert a load of a constant
3827 /// to just the constant itself.
3828 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3830 assert(Ty->isIntegerTy());
3832 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3833 if (BitSize == 0 || BitSize > 64)
3838 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3839 /// the specified range (L, H].
3840 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3841 return (Val < 0) || (Val >= Low && Val < Hi);
3844 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3845 /// specified value.
3846 static bool isUndefOrEqual(int Val, int CmpVal) {
3847 return (Val < 0 || Val == CmpVal);
3850 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3851 /// from position Pos and ending in Pos+Size, falls within the specified
3852 /// sequential range (L, L+Pos]. or is undef.
3853 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3854 unsigned Pos, unsigned Size, int Low) {
3855 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3856 if (!isUndefOrEqual(Mask[i], Low))
3861 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3862 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3863 /// the second operand.
3864 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3865 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3866 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3867 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3868 return (Mask[0] < 2 && Mask[1] < 2);
3872 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3873 /// is suitable for input to PSHUFHW.
3874 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3875 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3878 // Lower quadword copied in order or undef.
3879 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3882 // Upper quadword shuffled.
3883 for (unsigned i = 4; i != 8; ++i)
3884 if (!isUndefOrInRange(Mask[i], 4, 8))
3887 if (VT == MVT::v16i16) {
3888 // Lower quadword copied in order or undef.
3889 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3892 // Upper quadword shuffled.
3893 for (unsigned i = 12; i != 16; ++i)
3894 if (!isUndefOrInRange(Mask[i], 12, 16))
3901 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3902 /// is suitable for input to PSHUFLW.
3903 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3904 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3907 // Upper quadword copied in order.
3908 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3911 // Lower quadword shuffled.
3912 for (unsigned i = 0; i != 4; ++i)
3913 if (!isUndefOrInRange(Mask[i], 0, 4))
3916 if (VT == MVT::v16i16) {
3917 // Upper quadword copied in order.
3918 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3921 // Lower quadword shuffled.
3922 for (unsigned i = 8; i != 12; ++i)
3923 if (!isUndefOrInRange(Mask[i], 8, 12))
3930 /// \brief Return true if the mask specifies a shuffle of elements that is
3931 /// suitable for input to intralane (palignr) or interlane (valign) vector
3933 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3934 unsigned NumElts = VT.getVectorNumElements();
3935 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3936 unsigned NumLaneElts = NumElts/NumLanes;
3938 // Do not handle 64-bit element shuffles with palignr.
3939 if (NumLaneElts == 2)
3942 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3944 for (i = 0; i != NumLaneElts; ++i) {
3949 // Lane is all undef, go to next lane
3950 if (i == NumLaneElts)
3953 int Start = Mask[i+l];
3955 // Make sure its in this lane in one of the sources
3956 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3957 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3960 // If not lane 0, then we must match lane 0
3961 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3964 // Correct second source to be contiguous with first source
3965 if (Start >= (int)NumElts)
3966 Start -= NumElts - NumLaneElts;
3968 // Make sure we're shifting in the right direction.
3969 if (Start <= (int)(i+l))
3974 // Check the rest of the elements to see if they are consecutive.
3975 for (++i; i != NumLaneElts; ++i) {
3976 int Idx = Mask[i+l];
3978 // Make sure its in this lane
3979 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3980 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3983 // If not lane 0, then we must match lane 0
3984 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3987 if (Idx >= (int)NumElts)
3988 Idx -= NumElts - NumLaneElts;
3990 if (!isUndefOrEqual(Idx, Start+i))
3999 /// \brief Return true if the node specifies a shuffle of elements that is
4000 /// suitable for input to PALIGNR.
4001 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4002 const X86Subtarget *Subtarget) {
4003 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4004 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4005 VT.is512BitVector())
4006 // FIXME: Add AVX512BW.
4009 return isAlignrMask(Mask, VT, false);
4012 /// \brief Return true if the node specifies a shuffle of elements that is
4013 /// suitable for input to VALIGN.
4014 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4015 const X86Subtarget *Subtarget) {
4016 // FIXME: Add AVX512VL.
4017 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4019 return isAlignrMask(Mask, VT, true);
4022 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4023 /// the two vector operands have swapped position.
4024 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4025 unsigned NumElems) {
4026 for (unsigned i = 0; i != NumElems; ++i) {
4030 else if (idx < (int)NumElems)
4031 Mask[i] = idx + NumElems;
4033 Mask[i] = idx - NumElems;
4037 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4038 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4039 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4040 /// reverse of what x86 shuffles want.
4041 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4043 unsigned NumElems = VT.getVectorNumElements();
4044 unsigned NumLanes = VT.getSizeInBits()/128;
4045 unsigned NumLaneElems = NumElems/NumLanes;
4047 if (NumLaneElems != 2 && NumLaneElems != 4)
4050 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4051 bool symetricMaskRequired =
4052 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4054 // VSHUFPSY divides the resulting vector into 4 chunks.
4055 // The sources are also splitted into 4 chunks, and each destination
4056 // chunk must come from a different source chunk.
4058 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4059 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4061 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4062 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4064 // VSHUFPDY divides the resulting vector into 4 chunks.
4065 // The sources are also splitted into 4 chunks, and each destination
4066 // chunk must come from a different source chunk.
4068 // SRC1 => X3 X2 X1 X0
4069 // SRC2 => Y3 Y2 Y1 Y0
4071 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4073 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4074 unsigned HalfLaneElems = NumLaneElems/2;
4075 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4076 for (unsigned i = 0; i != NumLaneElems; ++i) {
4077 int Idx = Mask[i+l];
4078 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4079 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4081 // For VSHUFPSY, the mask of the second half must be the same as the
4082 // first but with the appropriate offsets. This works in the same way as
4083 // VPERMILPS works with masks.
4084 if (!symetricMaskRequired || Idx < 0)
4086 if (MaskVal[i] < 0) {
4087 MaskVal[i] = Idx - l;
4090 if ((signed)(Idx - l) != MaskVal[i])
4098 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4099 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4100 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4101 if (!VT.is128BitVector())
4104 unsigned NumElems = VT.getVectorNumElements();
4109 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4110 return isUndefOrEqual(Mask[0], 6) &&
4111 isUndefOrEqual(Mask[1], 7) &&
4112 isUndefOrEqual(Mask[2], 2) &&
4113 isUndefOrEqual(Mask[3], 3);
4116 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4117 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4119 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4120 if (!VT.is128BitVector())
4123 unsigned NumElems = VT.getVectorNumElements();
4128 return isUndefOrEqual(Mask[0], 2) &&
4129 isUndefOrEqual(Mask[1], 3) &&
4130 isUndefOrEqual(Mask[2], 2) &&
4131 isUndefOrEqual(Mask[3], 3);
4134 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4135 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4136 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4137 if (!VT.is128BitVector())
4140 unsigned NumElems = VT.getVectorNumElements();
4142 if (NumElems != 2 && NumElems != 4)
4145 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4146 if (!isUndefOrEqual(Mask[i], i + NumElems))
4149 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4150 if (!isUndefOrEqual(Mask[i], i))
4156 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4157 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4158 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4159 if (!VT.is128BitVector())
4162 unsigned NumElems = VT.getVectorNumElements();
4164 if (NumElems != 2 && NumElems != 4)
4167 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4168 if (!isUndefOrEqual(Mask[i], i))
4171 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4172 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4178 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4179 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4180 /// i. e: If all but one element come from the same vector.
4181 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4182 // TODO: Deal with AVX's VINSERTPS
4183 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4186 unsigned CorrectPosV1 = 0;
4187 unsigned CorrectPosV2 = 0;
4188 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4189 if (Mask[i] == -1) {
4197 else if (Mask[i] == i + 4)
4201 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4202 // We have 3 elements (undefs count as elements from any vector) from one
4203 // vector, and one from another.
4210 // Some special combinations that can be optimized.
4213 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4214 SelectionDAG &DAG) {
4215 MVT VT = SVOp->getSimpleValueType(0);
4218 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4221 ArrayRef<int> Mask = SVOp->getMask();
4223 // These are the special masks that may be optimized.
4224 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4225 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4226 bool MatchEvenMask = true;
4227 bool MatchOddMask = true;
4228 for (int i=0; i<8; ++i) {
4229 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4230 MatchEvenMask = false;
4231 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4232 MatchOddMask = false;
4235 if (!MatchEvenMask && !MatchOddMask)
4238 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4240 SDValue Op0 = SVOp->getOperand(0);
4241 SDValue Op1 = SVOp->getOperand(1);
4243 if (MatchEvenMask) {
4244 // Shift the second operand right to 32 bits.
4245 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4246 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4248 // Shift the first operand left to 32 bits.
4249 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4250 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4252 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4253 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4256 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4257 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4258 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4259 bool HasInt256, bool V2IsSplat = false) {
4261 assert(VT.getSizeInBits() >= 128 &&
4262 "Unsupported vector type for unpckl");
4264 unsigned NumElts = VT.getVectorNumElements();
4265 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4266 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4269 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4270 "Unsupported vector type for unpckh");
4272 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4273 unsigned NumLanes = VT.getSizeInBits()/128;
4274 unsigned NumLaneElts = NumElts/NumLanes;
4276 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4277 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4278 int BitI = Mask[l+i];
4279 int BitI1 = Mask[l+i+1];
4280 if (!isUndefOrEqual(BitI, j))
4283 if (!isUndefOrEqual(BitI1, NumElts))
4286 if (!isUndefOrEqual(BitI1, j + NumElts))
4295 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4296 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4297 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4298 bool HasInt256, bool V2IsSplat = false) {
4299 assert(VT.getSizeInBits() >= 128 &&
4300 "Unsupported vector type for unpckh");
4302 unsigned NumElts = VT.getVectorNumElements();
4303 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4304 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4307 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4308 "Unsupported vector type for unpckh");
4310 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4311 unsigned NumLanes = VT.getSizeInBits()/128;
4312 unsigned NumLaneElts = NumElts/NumLanes;
4314 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4315 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4316 int BitI = Mask[l+i];
4317 int BitI1 = Mask[l+i+1];
4318 if (!isUndefOrEqual(BitI, j))
4321 if (isUndefOrEqual(BitI1, NumElts))
4324 if (!isUndefOrEqual(BitI1, j+NumElts))
4332 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4333 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4335 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4336 unsigned NumElts = VT.getVectorNumElements();
4337 bool Is256BitVec = VT.is256BitVector();
4339 if (VT.is512BitVector())
4341 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4342 "Unsupported vector type for unpckh");
4344 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4345 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4348 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4349 // FIXME: Need a better way to get rid of this, there's no latency difference
4350 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4351 // the former later. We should also remove the "_undef" special mask.
4352 if (NumElts == 4 && Is256BitVec)
4355 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4356 // independently on 128-bit lanes.
4357 unsigned NumLanes = VT.getSizeInBits()/128;
4358 unsigned NumLaneElts = NumElts/NumLanes;
4360 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4361 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4362 int BitI = Mask[l+i];
4363 int BitI1 = Mask[l+i+1];
4365 if (!isUndefOrEqual(BitI, j))
4367 if (!isUndefOrEqual(BitI1, j))
4375 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4376 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4378 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4379 unsigned NumElts = VT.getVectorNumElements();
4381 if (VT.is512BitVector())
4384 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4385 "Unsupported vector type for unpckh");
4387 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4388 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4391 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4392 // independently on 128-bit lanes.
4393 unsigned NumLanes = VT.getSizeInBits()/128;
4394 unsigned NumLaneElts = NumElts/NumLanes;
4396 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4397 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4398 int BitI = Mask[l+i];
4399 int BitI1 = Mask[l+i+1];
4400 if (!isUndefOrEqual(BitI, j))
4402 if (!isUndefOrEqual(BitI1, j))
4409 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4410 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4411 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4412 if (!VT.is512BitVector())
4415 unsigned NumElts = VT.getVectorNumElements();
4416 unsigned HalfSize = NumElts/2;
4417 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4418 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4423 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4424 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4432 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4433 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4434 /// MOVSD, and MOVD, i.e. setting the lowest element.
4435 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4436 if (VT.getVectorElementType().getSizeInBits() < 32)
4438 if (!VT.is128BitVector())
4441 unsigned NumElts = VT.getVectorNumElements();
4443 if (!isUndefOrEqual(Mask[0], NumElts))
4446 for (unsigned i = 1; i != NumElts; ++i)
4447 if (!isUndefOrEqual(Mask[i], i))
4453 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4454 /// as permutations between 128-bit chunks or halves. As an example: this
4456 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4457 /// The first half comes from the second half of V1 and the second half from the
4458 /// the second half of V2.
4459 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4460 if (!HasFp256 || !VT.is256BitVector())
4463 // The shuffle result is divided into half A and half B. In total the two
4464 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4465 // B must come from C, D, E or F.
4466 unsigned HalfSize = VT.getVectorNumElements()/2;
4467 bool MatchA = false, MatchB = false;
4469 // Check if A comes from one of C, D, E, F.
4470 for (unsigned Half = 0; Half != 4; ++Half) {
4471 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4477 // Check if B comes from one of C, D, E, F.
4478 for (unsigned Half = 0; Half != 4; ++Half) {
4479 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4485 return MatchA && MatchB;
4488 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4489 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4490 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4491 MVT VT = SVOp->getSimpleValueType(0);
4493 unsigned HalfSize = VT.getVectorNumElements()/2;
4495 unsigned FstHalf = 0, SndHalf = 0;
4496 for (unsigned i = 0; i < HalfSize; ++i) {
4497 if (SVOp->getMaskElt(i) > 0) {
4498 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4502 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4503 if (SVOp->getMaskElt(i) > 0) {
4504 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4509 return (FstHalf | (SndHalf << 4));
4512 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4513 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4514 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4518 unsigned NumElts = VT.getVectorNumElements();
4520 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4521 for (unsigned i = 0; i != NumElts; ++i) {
4524 Imm8 |= Mask[i] << (i*2);
4529 unsigned LaneSize = 4;
4530 SmallVector<int, 4> MaskVal(LaneSize, -1);
4532 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4533 for (unsigned i = 0; i != LaneSize; ++i) {
4534 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4538 if (MaskVal[i] < 0) {
4539 MaskVal[i] = Mask[i+l] - l;
4540 Imm8 |= MaskVal[i] << (i*2);
4543 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4550 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4551 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4552 /// Note that VPERMIL mask matching is different depending whether theunderlying
4553 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4554 /// to the same elements of the low, but to the higher half of the source.
4555 /// In VPERMILPD the two lanes could be shuffled independently of each other
4556 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4557 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4558 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4559 if (VT.getSizeInBits() < 256 || EltSize < 32)
4561 bool symetricMaskRequired = (EltSize == 32);
4562 unsigned NumElts = VT.getVectorNumElements();
4564 unsigned NumLanes = VT.getSizeInBits()/128;
4565 unsigned LaneSize = NumElts/NumLanes;
4566 // 2 or 4 elements in one lane
4568 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4569 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4570 for (unsigned i = 0; i != LaneSize; ++i) {
4571 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4573 if (symetricMaskRequired) {
4574 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4575 ExpectedMaskVal[i] = Mask[i+l] - l;
4578 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4586 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4587 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4588 /// element of vector 2 and the other elements to come from vector 1 in order.
4589 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4590 bool V2IsSplat = false, bool V2IsUndef = false) {
4591 if (!VT.is128BitVector())
4594 unsigned NumOps = VT.getVectorNumElements();
4595 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4598 if (!isUndefOrEqual(Mask[0], 0))
4601 for (unsigned i = 1; i != NumOps; ++i)
4602 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4603 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4604 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4610 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4611 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4612 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4613 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4614 const X86Subtarget *Subtarget) {
4615 if (!Subtarget->hasSSE3())
4618 unsigned NumElems = VT.getVectorNumElements();
4620 if ((VT.is128BitVector() && NumElems != 4) ||
4621 (VT.is256BitVector() && NumElems != 8) ||
4622 (VT.is512BitVector() && NumElems != 16))
4625 // "i+1" is the value the indexed mask element must have
4626 for (unsigned i = 0; i != NumElems; i += 2)
4627 if (!isUndefOrEqual(Mask[i], i+1) ||
4628 !isUndefOrEqual(Mask[i+1], i+1))
4634 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4635 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4636 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4637 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4638 const X86Subtarget *Subtarget) {
4639 if (!Subtarget->hasSSE3())
4642 unsigned NumElems = VT.getVectorNumElements();
4644 if ((VT.is128BitVector() && NumElems != 4) ||
4645 (VT.is256BitVector() && NumElems != 8) ||
4646 (VT.is512BitVector() && NumElems != 16))
4649 // "i" is the value the indexed mask element must have
4650 for (unsigned i = 0; i != NumElems; i += 2)
4651 if (!isUndefOrEqual(Mask[i], i) ||
4652 !isUndefOrEqual(Mask[i+1], i))
4658 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4659 /// specifies a shuffle of elements that is suitable for input to 256-bit
4660 /// version of MOVDDUP.
4661 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4662 if (!HasFp256 || !VT.is256BitVector())
4665 unsigned NumElts = VT.getVectorNumElements();
4669 for (unsigned i = 0; i != NumElts/2; ++i)
4670 if (!isUndefOrEqual(Mask[i], 0))
4672 for (unsigned i = NumElts/2; i != NumElts; ++i)
4673 if (!isUndefOrEqual(Mask[i], NumElts/2))
4678 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4679 /// specifies a shuffle of elements that is suitable for input to 128-bit
4680 /// version of MOVDDUP.
4681 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4682 if (!VT.is128BitVector())
4685 unsigned e = VT.getVectorNumElements() / 2;
4686 for (unsigned i = 0; i != e; ++i)
4687 if (!isUndefOrEqual(Mask[i], i))
4689 for (unsigned i = 0; i != e; ++i)
4690 if (!isUndefOrEqual(Mask[e+i], i))
4695 /// isVEXTRACTIndex - Return true if the specified
4696 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4697 /// suitable for instruction that extract 128 or 256 bit vectors
4698 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4699 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4700 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4703 // The index should be aligned on a vecWidth-bit boundary.
4705 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4707 MVT VT = N->getSimpleValueType(0);
4708 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4709 bool Result = (Index * ElSize) % vecWidth == 0;
4714 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4715 /// operand specifies a subvector insert that is suitable for input to
4716 /// insertion of 128 or 256-bit subvectors
4717 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4718 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4719 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4721 // The index should be aligned on a vecWidth-bit boundary.
4723 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4725 MVT VT = N->getSimpleValueType(0);
4726 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4727 bool Result = (Index * ElSize) % vecWidth == 0;
4732 bool X86::isVINSERT128Index(SDNode *N) {
4733 return isVINSERTIndex(N, 128);
4736 bool X86::isVINSERT256Index(SDNode *N) {
4737 return isVINSERTIndex(N, 256);
4740 bool X86::isVEXTRACT128Index(SDNode *N) {
4741 return isVEXTRACTIndex(N, 128);
4744 bool X86::isVEXTRACT256Index(SDNode *N) {
4745 return isVEXTRACTIndex(N, 256);
4748 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4749 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4750 /// Handles 128-bit and 256-bit.
4751 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4752 MVT VT = N->getSimpleValueType(0);
4754 assert((VT.getSizeInBits() >= 128) &&
4755 "Unsupported vector type for PSHUF/SHUFP");
4757 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4758 // independently on 128-bit lanes.
4759 unsigned NumElts = VT.getVectorNumElements();
4760 unsigned NumLanes = VT.getSizeInBits()/128;
4761 unsigned NumLaneElts = NumElts/NumLanes;
4763 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4764 "Only supports 2, 4 or 8 elements per lane");
4766 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4768 for (unsigned i = 0; i != NumElts; ++i) {
4769 int Elt = N->getMaskElt(i);
4770 if (Elt < 0) continue;
4771 Elt &= NumLaneElts - 1;
4772 unsigned ShAmt = (i << Shift) % 8;
4773 Mask |= Elt << ShAmt;
4779 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4780 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4781 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4782 MVT VT = N->getSimpleValueType(0);
4784 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4785 "Unsupported vector type for PSHUFHW");
4787 unsigned NumElts = VT.getVectorNumElements();
4790 for (unsigned l = 0; l != NumElts; l += 8) {
4791 // 8 nodes per lane, but we only care about the last 4.
4792 for (unsigned i = 0; i < 4; ++i) {
4793 int Elt = N->getMaskElt(l+i+4);
4794 if (Elt < 0) continue;
4795 Elt &= 0x3; // only 2-bits.
4796 Mask |= Elt << (i * 2);
4803 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4804 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4805 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4806 MVT VT = N->getSimpleValueType(0);
4808 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4809 "Unsupported vector type for PSHUFHW");
4811 unsigned NumElts = VT.getVectorNumElements();
4814 for (unsigned l = 0; l != NumElts; l += 8) {
4815 // 8 nodes per lane, but we only care about the first 4.
4816 for (unsigned i = 0; i < 4; ++i) {
4817 int Elt = N->getMaskElt(l+i);
4818 if (Elt < 0) continue;
4819 Elt &= 0x3; // only 2-bits
4820 Mask |= Elt << (i * 2);
4827 /// \brief Return the appropriate immediate to shuffle the specified
4828 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4829 /// VALIGN (if Interlane is true) instructions.
4830 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4832 MVT VT = SVOp->getSimpleValueType(0);
4833 unsigned EltSize = InterLane ? 1 :
4834 VT.getVectorElementType().getSizeInBits() >> 3;
4836 unsigned NumElts = VT.getVectorNumElements();
4837 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4838 unsigned NumLaneElts = NumElts/NumLanes;
4842 for (i = 0; i != NumElts; ++i) {
4843 Val = SVOp->getMaskElt(i);
4847 if (Val >= (int)NumElts)
4848 Val -= NumElts - NumLaneElts;
4850 assert(Val - i > 0 && "PALIGNR imm should be positive");
4851 return (Val - i) * EltSize;
4854 /// \brief Return the appropriate immediate to shuffle the specified
4855 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4856 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4857 return getShuffleAlignrImmediate(SVOp, false);
4860 /// \brief Return the appropriate immediate to shuffle the specified
4861 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4862 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4863 return getShuffleAlignrImmediate(SVOp, true);
4867 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4868 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4869 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4870 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4873 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4875 MVT VecVT = N->getOperand(0).getSimpleValueType();
4876 MVT ElVT = VecVT.getVectorElementType();
4878 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4879 return Index / NumElemsPerChunk;
4882 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4883 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4884 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4885 llvm_unreachable("Illegal insert subvector for VINSERT");
4888 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4890 MVT VecVT = N->getSimpleValueType(0);
4891 MVT ElVT = VecVT.getVectorElementType();
4893 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4894 return Index / NumElemsPerChunk;
4897 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4898 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4899 /// and VINSERTI128 instructions.
4900 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4901 return getExtractVEXTRACTImmediate(N, 128);
4904 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4905 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4906 /// and VINSERTI64x4 instructions.
4907 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4908 return getExtractVEXTRACTImmediate(N, 256);
4911 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4912 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4913 /// and VINSERTI128 instructions.
4914 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4915 return getInsertVINSERTImmediate(N, 128);
4918 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4919 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4920 /// and VINSERTI64x4 instructions.
4921 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4922 return getInsertVINSERTImmediate(N, 256);
4925 /// isZero - Returns true if Elt is a constant integer zero
4926 static bool isZero(SDValue V) {
4927 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4928 return C && C->isNullValue();
4931 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4933 bool X86::isZeroNode(SDValue Elt) {
4936 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4937 return CFP->getValueAPF().isPosZero();
4941 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4942 /// match movhlps. The lower half elements should come from upper half of
4943 /// V1 (and in order), and the upper half elements should come from the upper
4944 /// half of V2 (and in order).
4945 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4946 if (!VT.is128BitVector())
4948 if (VT.getVectorNumElements() != 4)
4950 for (unsigned i = 0, e = 2; i != e; ++i)
4951 if (!isUndefOrEqual(Mask[i], i+2))
4953 for (unsigned i = 2; i != 4; ++i)
4954 if (!isUndefOrEqual(Mask[i], i+4))
4959 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4960 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4962 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4963 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4965 N = N->getOperand(0).getNode();
4966 if (!ISD::isNON_EXTLoad(N))
4969 *LD = cast<LoadSDNode>(N);
4973 // Test whether the given value is a vector value which will be legalized
4975 static bool WillBeConstantPoolLoad(SDNode *N) {
4976 if (N->getOpcode() != ISD::BUILD_VECTOR)
4979 // Check for any non-constant elements.
4980 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4981 switch (N->getOperand(i).getNode()->getOpcode()) {
4983 case ISD::ConstantFP:
4990 // Vectors of all-zeros and all-ones are materialized with special
4991 // instructions rather than being loaded.
4992 return !ISD::isBuildVectorAllZeros(N) &&
4993 !ISD::isBuildVectorAllOnes(N);
4996 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4997 /// match movlp{s|d}. The lower half elements should come from lower half of
4998 /// V1 (and in order), and the upper half elements should come from the upper
4999 /// half of V2 (and in order). And since V1 will become the source of the
5000 /// MOVLP, it must be either a vector load or a scalar load to vector.
5001 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5002 ArrayRef<int> Mask, MVT VT) {
5003 if (!VT.is128BitVector())
5006 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5008 // Is V2 is a vector load, don't do this transformation. We will try to use
5009 // load folding shufps op.
5010 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5013 unsigned NumElems = VT.getVectorNumElements();
5015 if (NumElems != 2 && NumElems != 4)
5017 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5018 if (!isUndefOrEqual(Mask[i], i))
5020 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5021 if (!isUndefOrEqual(Mask[i], i+NumElems))
5026 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5027 /// to an zero vector.
5028 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5029 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5030 SDValue V1 = N->getOperand(0);
5031 SDValue V2 = N->getOperand(1);
5032 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5033 for (unsigned i = 0; i != NumElems; ++i) {
5034 int Idx = N->getMaskElt(i);
5035 if (Idx >= (int)NumElems) {
5036 unsigned Opc = V2.getOpcode();
5037 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5039 if (Opc != ISD::BUILD_VECTOR ||
5040 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5042 } else if (Idx >= 0) {
5043 unsigned Opc = V1.getOpcode();
5044 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5046 if (Opc != ISD::BUILD_VECTOR ||
5047 !X86::isZeroNode(V1.getOperand(Idx)))
5054 /// getZeroVector - Returns a vector of specified type with all zero elements.
5056 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5057 SelectionDAG &DAG, SDLoc dl) {
5058 assert(VT.isVector() && "Expected a vector type");
5060 // Always build SSE zero vectors as <4 x i32> bitcasted
5061 // to their dest type. This ensures they get CSE'd.
5063 if (VT.is128BitVector()) { // SSE
5064 if (Subtarget->hasSSE2()) { // SSE2
5065 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5066 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5068 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5071 } else if (VT.is256BitVector()) { // AVX
5072 if (Subtarget->hasInt256()) { // AVX2
5073 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5074 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5075 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5077 // 256-bit logic and arithmetic instructions in AVX are all
5078 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5079 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5080 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5081 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5083 } else if (VT.is512BitVector()) { // AVX-512
5084 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5085 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5086 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5087 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5088 } else if (VT.getScalarType() == MVT::i1) {
5089 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5090 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5091 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5092 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5094 llvm_unreachable("Unexpected vector type");
5096 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5099 /// getOnesVector - Returns a vector of specified type with all bits set.
5100 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5101 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5102 /// Then bitcast to their original type, ensuring they get CSE'd.
5103 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5105 assert(VT.isVector() && "Expected a vector type");
5107 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5109 if (VT.is256BitVector()) {
5110 if (HasInt256) { // AVX2
5111 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5112 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5114 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5115 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5117 } else if (VT.is128BitVector()) {
5118 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5120 llvm_unreachable("Unexpected vector type");
5122 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5125 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5126 /// that point to V2 points to its first element.
5127 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5128 for (unsigned i = 0; i != NumElems; ++i) {
5129 if (Mask[i] > (int)NumElems) {
5135 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5136 /// operation of specified width.
5137 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5139 unsigned NumElems = VT.getVectorNumElements();
5140 SmallVector<int, 8> Mask;
5141 Mask.push_back(NumElems);
5142 for (unsigned i = 1; i != NumElems; ++i)
5144 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5147 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5148 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5150 unsigned NumElems = VT.getVectorNumElements();
5151 SmallVector<int, 8> Mask;
5152 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5154 Mask.push_back(i + NumElems);
5156 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5159 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5160 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5162 unsigned NumElems = VT.getVectorNumElements();
5163 SmallVector<int, 8> Mask;
5164 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5165 Mask.push_back(i + Half);
5166 Mask.push_back(i + NumElems + Half);
5168 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5171 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5172 // a generic shuffle instruction because the target has no such instructions.
5173 // Generate shuffles which repeat i16 and i8 several times until they can be
5174 // represented by v4f32 and then be manipulated by target suported shuffles.
5175 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5176 MVT VT = V.getSimpleValueType();
5177 int NumElems = VT.getVectorNumElements();
5180 while (NumElems > 4) {
5181 if (EltNo < NumElems/2) {
5182 V = getUnpackl(DAG, dl, VT, V, V);
5184 V = getUnpackh(DAG, dl, VT, V, V);
5185 EltNo -= NumElems/2;
5192 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5193 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5194 MVT VT = V.getSimpleValueType();
5197 if (VT.is128BitVector()) {
5198 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5199 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5200 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5202 } else if (VT.is256BitVector()) {
5203 // To use VPERMILPS to splat scalars, the second half of indicies must
5204 // refer to the higher part, which is a duplication of the lower one,
5205 // because VPERMILPS can only handle in-lane permutations.
5206 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5207 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5209 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5210 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5213 llvm_unreachable("Vector size not supported");
5215 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5218 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5219 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5220 MVT SrcVT = SV->getSimpleValueType(0);
5221 SDValue V1 = SV->getOperand(0);
5224 int EltNo = SV->getSplatIndex();
5225 int NumElems = SrcVT.getVectorNumElements();
5226 bool Is256BitVec = SrcVT.is256BitVector();
5228 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5229 "Unknown how to promote splat for type");
5231 // Extract the 128-bit part containing the splat element and update
5232 // the splat element index when it refers to the higher register.
5234 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5235 if (EltNo >= NumElems/2)
5236 EltNo -= NumElems/2;
5239 // All i16 and i8 vector types can't be used directly by a generic shuffle
5240 // instruction because the target has no such instruction. Generate shuffles
5241 // which repeat i16 and i8 several times until they fit in i32, and then can
5242 // be manipulated by target suported shuffles.
5243 MVT EltVT = SrcVT.getVectorElementType();
5244 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5245 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5247 // Recreate the 256-bit vector and place the same 128-bit vector
5248 // into the low and high part. This is necessary because we want
5249 // to use VPERM* to shuffle the vectors
5251 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5254 return getLegalSplat(DAG, V1, EltNo);
5257 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5258 /// vector of zero or undef vector. This produces a shuffle where the low
5259 /// element of V2 is swizzled into the zero/undef vector, landing at element
5260 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5261 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5263 const X86Subtarget *Subtarget,
5264 SelectionDAG &DAG) {
5265 MVT VT = V2.getSimpleValueType();
5267 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5268 unsigned NumElems = VT.getVectorNumElements();
5269 SmallVector<int, 16> MaskVec;
5270 for (unsigned i = 0; i != NumElems; ++i)
5271 // If this is the insertion idx, put the low elt of V2 here.
5272 MaskVec.push_back(i == Idx ? NumElems : i);
5273 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5276 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5277 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5278 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5279 /// shuffles which use a single input multiple times, and in those cases it will
5280 /// adjust the mask to only have indices within that single input.
5281 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5282 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5283 unsigned NumElems = VT.getVectorNumElements();
5287 bool IsFakeUnary = false;
5288 switch(N->getOpcode()) {
5289 case X86ISD::BLENDI:
5290 ImmN = N->getOperand(N->getNumOperands()-1);
5291 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5294 ImmN = N->getOperand(N->getNumOperands()-1);
5295 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5296 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5298 case X86ISD::UNPCKH:
5299 DecodeUNPCKHMask(VT, Mask);
5300 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5302 case X86ISD::UNPCKL:
5303 DecodeUNPCKLMask(VT, Mask);
5304 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5306 case X86ISD::MOVHLPS:
5307 DecodeMOVHLPSMask(NumElems, Mask);
5308 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5310 case X86ISD::MOVLHPS:
5311 DecodeMOVLHPSMask(NumElems, Mask);
5312 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5314 case X86ISD::PALIGNR:
5315 ImmN = N->getOperand(N->getNumOperands()-1);
5316 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5318 case X86ISD::PSHUFD:
5319 case X86ISD::VPERMILPI:
5320 ImmN = N->getOperand(N->getNumOperands()-1);
5321 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5324 case X86ISD::PSHUFHW:
5325 ImmN = N->getOperand(N->getNumOperands()-1);
5326 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5329 case X86ISD::PSHUFLW:
5330 ImmN = N->getOperand(N->getNumOperands()-1);
5331 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5334 case X86ISD::PSHUFB: {
5336 SDValue MaskNode = N->getOperand(1);
5337 while (MaskNode->getOpcode() == ISD::BITCAST)
5338 MaskNode = MaskNode->getOperand(0);
5340 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5341 // If we have a build-vector, then things are easy.
5342 EVT VT = MaskNode.getValueType();
5343 assert(VT.isVector() &&
5344 "Can't produce a non-vector with a build_vector!");
5345 if (!VT.isInteger())
5348 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5350 SmallVector<uint64_t, 32> RawMask;
5351 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5352 SDValue Op = MaskNode->getOperand(i);
5353 if (Op->getOpcode() == ISD::UNDEF) {
5354 RawMask.push_back((uint64_t)SM_SentinelUndef);
5357 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5360 APInt MaskElement = CN->getAPIntValue();
5362 // We now have to decode the element which could be any integer size and
5363 // extract each byte of it.
5364 for (int j = 0; j < NumBytesPerElement; ++j) {
5365 // Note that this is x86 and so always little endian: the low byte is
5366 // the first byte of the mask.
5367 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5368 MaskElement = MaskElement.lshr(8);
5371 DecodePSHUFBMask(RawMask, Mask);
5375 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5379 SDValue Ptr = MaskLoad->getBasePtr();
5380 if (Ptr->getOpcode() == X86ISD::Wrapper)
5381 Ptr = Ptr->getOperand(0);
5383 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5384 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5387 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5388 // FIXME: Support AVX-512 here.
5389 Type *Ty = C->getType();
5390 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5391 Ty->getVectorNumElements() != 32))
5394 DecodePSHUFBMask(C, Mask);
5400 case X86ISD::VPERMI:
5401 ImmN = N->getOperand(N->getNumOperands()-1);
5402 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5406 case X86ISD::MOVSD: {
5407 // The index 0 always comes from the first element of the second source,
5408 // this is why MOVSS and MOVSD are used in the first place. The other
5409 // elements come from the other positions of the first source vector
5410 Mask.push_back(NumElems);
5411 for (unsigned i = 1; i != NumElems; ++i) {
5416 case X86ISD::VPERM2X128:
5417 ImmN = N->getOperand(N->getNumOperands()-1);
5418 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5419 if (Mask.empty()) return false;
5421 case X86ISD::MOVSLDUP:
5422 DecodeMOVSLDUPMask(VT, Mask);
5424 case X86ISD::MOVSHDUP:
5425 DecodeMOVSHDUPMask(VT, Mask);
5427 case X86ISD::MOVDDUP:
5428 case X86ISD::MOVLHPD:
5429 case X86ISD::MOVLPD:
5430 case X86ISD::MOVLPS:
5431 // Not yet implemented
5433 default: llvm_unreachable("unknown target shuffle node");
5436 // If we have a fake unary shuffle, the shuffle mask is spread across two
5437 // inputs that are actually the same node. Re-map the mask to always point
5438 // into the first input.
5441 if (M >= (int)Mask.size())
5447 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5448 /// element of the result of the vector shuffle.
5449 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5452 return SDValue(); // Limit search depth.
5454 SDValue V = SDValue(N, 0);
5455 EVT VT = V.getValueType();
5456 unsigned Opcode = V.getOpcode();
5458 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5459 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5460 int Elt = SV->getMaskElt(Index);
5463 return DAG.getUNDEF(VT.getVectorElementType());
5465 unsigned NumElems = VT.getVectorNumElements();
5466 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5467 : SV->getOperand(1);
5468 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5471 // Recurse into target specific vector shuffles to find scalars.
5472 if (isTargetShuffle(Opcode)) {
5473 MVT ShufVT = V.getSimpleValueType();
5474 unsigned NumElems = ShufVT.getVectorNumElements();
5475 SmallVector<int, 16> ShuffleMask;
5478 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5481 int Elt = ShuffleMask[Index];
5483 return DAG.getUNDEF(ShufVT.getVectorElementType());
5485 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5487 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5491 // Actual nodes that may contain scalar elements
5492 if (Opcode == ISD::BITCAST) {
5493 V = V.getOperand(0);
5494 EVT SrcVT = V.getValueType();
5495 unsigned NumElems = VT.getVectorNumElements();
5497 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5501 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5502 return (Index == 0) ? V.getOperand(0)
5503 : DAG.getUNDEF(VT.getVectorElementType());
5505 if (V.getOpcode() == ISD::BUILD_VECTOR)
5506 return V.getOperand(Index);
5511 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5512 /// shuffle operation which come from a consecutively from a zero. The
5513 /// search can start in two different directions, from left or right.
5514 /// We count undefs as zeros until PreferredNum is reached.
5515 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5516 unsigned NumElems, bool ZerosFromLeft,
5518 unsigned PreferredNum = -1U) {
5519 unsigned NumZeros = 0;
5520 for (unsigned i = 0; i != NumElems; ++i) {
5521 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5522 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5526 if (X86::isZeroNode(Elt))
5528 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5529 NumZeros = std::min(NumZeros + 1, PreferredNum);
5537 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5538 /// correspond consecutively to elements from one of the vector operands,
5539 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5541 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5542 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5543 unsigned NumElems, unsigned &OpNum) {
5544 bool SeenV1 = false;
5545 bool SeenV2 = false;
5547 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5548 int Idx = SVOp->getMaskElt(i);
5549 // Ignore undef indicies
5553 if (Idx < (int)NumElems)
5558 // Only accept consecutive elements from the same vector
5559 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5563 OpNum = SeenV1 ? 0 : 1;
5567 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5568 /// logical left shift of a vector.
5569 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5570 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5572 SVOp->getSimpleValueType(0).getVectorNumElements();
5573 unsigned NumZeros = getNumOfConsecutiveZeros(
5574 SVOp, NumElems, false /* check zeros from right */, DAG,
5575 SVOp->getMaskElt(0));
5581 // Considering the elements in the mask that are not consecutive zeros,
5582 // check if they consecutively come from only one of the source vectors.
5584 // V1 = {X, A, B, C} 0
5586 // vector_shuffle V1, V2 <1, 2, 3, X>
5588 if (!isShuffleMaskConsecutive(SVOp,
5589 0, // Mask Start Index
5590 NumElems-NumZeros, // Mask End Index(exclusive)
5591 NumZeros, // Where to start looking in the src vector
5592 NumElems, // Number of elements in vector
5593 OpSrc)) // Which source operand ?
5598 ShVal = SVOp->getOperand(OpSrc);
5602 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5603 /// logical left shift of a vector.
5604 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5605 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5607 SVOp->getSimpleValueType(0).getVectorNumElements();
5608 unsigned NumZeros = getNumOfConsecutiveZeros(
5609 SVOp, NumElems, true /* check zeros from left */, DAG,
5610 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5616 // Considering the elements in the mask that are not consecutive zeros,
5617 // check if they consecutively come from only one of the source vectors.
5619 // 0 { A, B, X, X } = V2
5621 // vector_shuffle V1, V2 <X, X, 4, 5>
5623 if (!isShuffleMaskConsecutive(SVOp,
5624 NumZeros, // Mask Start Index
5625 NumElems, // Mask End Index(exclusive)
5626 0, // Where to start looking in the src vector
5627 NumElems, // Number of elements in vector
5628 OpSrc)) // Which source operand ?
5633 ShVal = SVOp->getOperand(OpSrc);
5637 /// isVectorShift - Returns true if the shuffle can be implemented as a
5638 /// logical left or right shift of a vector.
5639 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5640 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5641 // Although the logic below support any bitwidth size, there are no
5642 // shift instructions which handle more than 128-bit vectors.
5643 if (!SVOp->getSimpleValueType(0).is128BitVector())
5646 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5647 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5653 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5655 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5656 unsigned NumNonZero, unsigned NumZero,
5658 const X86Subtarget* Subtarget,
5659 const TargetLowering &TLI) {
5666 for (unsigned i = 0; i < 16; ++i) {
5667 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5668 if (ThisIsNonZero && First) {
5670 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5672 V = DAG.getUNDEF(MVT::v8i16);
5677 SDValue ThisElt, LastElt;
5678 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5679 if (LastIsNonZero) {
5680 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5681 MVT::i16, Op.getOperand(i-1));
5683 if (ThisIsNonZero) {
5684 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5685 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5686 ThisElt, DAG.getConstant(8, MVT::i8));
5688 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5692 if (ThisElt.getNode())
5693 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5694 DAG.getIntPtrConstant(i/2));
5698 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5701 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5703 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5704 unsigned NumNonZero, unsigned NumZero,
5706 const X86Subtarget* Subtarget,
5707 const TargetLowering &TLI) {
5714 for (unsigned i = 0; i < 8; ++i) {
5715 bool isNonZero = (NonZeros & (1 << i)) != 0;
5719 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5721 V = DAG.getUNDEF(MVT::v8i16);
5724 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5725 MVT::v8i16, V, Op.getOperand(i),
5726 DAG.getIntPtrConstant(i));
5733 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5734 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5735 unsigned NonZeros, unsigned NumNonZero,
5736 unsigned NumZero, SelectionDAG &DAG,
5737 const X86Subtarget *Subtarget,
5738 const TargetLowering &TLI) {
5739 // We know there's at least one non-zero element
5740 unsigned FirstNonZeroIdx = 0;
5741 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5742 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5743 X86::isZeroNode(FirstNonZero)) {
5745 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5748 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5749 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5752 SDValue V = FirstNonZero.getOperand(0);
5753 MVT VVT = V.getSimpleValueType();
5754 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5757 unsigned FirstNonZeroDst =
5758 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5759 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5760 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5761 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5763 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5764 SDValue Elem = Op.getOperand(Idx);
5765 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5768 // TODO: What else can be here? Deal with it.
5769 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5772 // TODO: Some optimizations are still possible here
5773 // ex: Getting one element from a vector, and the rest from another.
5774 if (Elem.getOperand(0) != V)
5777 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5780 else if (IncorrectIdx == -1U) {
5784 // There was already one element with an incorrect index.
5785 // We can't optimize this case to an insertps.
5789 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5791 EVT VT = Op.getSimpleValueType();
5792 unsigned ElementMoveMask = 0;
5793 if (IncorrectIdx == -1U)
5794 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5796 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5798 SDValue InsertpsMask =
5799 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5800 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5806 /// getVShift - Return a vector logical shift node.
5808 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5809 unsigned NumBits, SelectionDAG &DAG,
5810 const TargetLowering &TLI, SDLoc dl) {
5811 assert(VT.is128BitVector() && "Unknown type for VShift");
5812 EVT ShVT = MVT::v2i64;
5813 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5814 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5815 return DAG.getNode(ISD::BITCAST, dl, VT,
5816 DAG.getNode(Opc, dl, ShVT, SrcOp,
5817 DAG.getConstant(NumBits,
5818 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5822 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5824 // Check if the scalar load can be widened into a vector load. And if
5825 // the address is "base + cst" see if the cst can be "absorbed" into
5826 // the shuffle mask.
5827 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5828 SDValue Ptr = LD->getBasePtr();
5829 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5831 EVT PVT = LD->getValueType(0);
5832 if (PVT != MVT::i32 && PVT != MVT::f32)
5837 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5838 FI = FINode->getIndex();
5840 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5841 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5842 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5843 Offset = Ptr.getConstantOperandVal(1);
5844 Ptr = Ptr.getOperand(0);
5849 // FIXME: 256-bit vector instructions don't require a strict alignment,
5850 // improve this code to support it better.
5851 unsigned RequiredAlign = VT.getSizeInBits()/8;
5852 SDValue Chain = LD->getChain();
5853 // Make sure the stack object alignment is at least 16 or 32.
5854 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5855 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5856 if (MFI->isFixedObjectIndex(FI)) {
5857 // Can't change the alignment. FIXME: It's possible to compute
5858 // the exact stack offset and reference FI + adjust offset instead.
5859 // If someone *really* cares about this. That's the way to implement it.
5862 MFI->setObjectAlignment(FI, RequiredAlign);
5866 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5867 // Ptr + (Offset & ~15).
5870 if ((Offset % RequiredAlign) & 3)
5872 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5874 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5875 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5877 int EltNo = (Offset - StartOffset) >> 2;
5878 unsigned NumElems = VT.getVectorNumElements();
5880 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5881 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5882 LD->getPointerInfo().getWithOffset(StartOffset),
5883 false, false, false, 0);
5885 SmallVector<int, 8> Mask;
5886 for (unsigned i = 0; i != NumElems; ++i)
5887 Mask.push_back(EltNo);
5889 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5895 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5896 /// vector of type 'VT', see if the elements can be replaced by a single large
5897 /// load which has the same value as a build_vector whose operands are 'elts'.
5899 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5901 /// FIXME: we'd also like to handle the case where the last elements are zero
5902 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5903 /// There's even a handy isZeroNode for that purpose.
5904 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5905 SDLoc &DL, SelectionDAG &DAG,
5906 bool isAfterLegalize) {
5907 EVT EltVT = VT.getVectorElementType();
5908 unsigned NumElems = Elts.size();
5910 LoadSDNode *LDBase = nullptr;
5911 unsigned LastLoadedElt = -1U;
5913 // For each element in the initializer, see if we've found a load or an undef.
5914 // If we don't find an initial load element, or later load elements are
5915 // non-consecutive, bail out.
5916 for (unsigned i = 0; i < NumElems; ++i) {
5917 SDValue Elt = Elts[i];
5919 if (!Elt.getNode() ||
5920 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5923 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5925 LDBase = cast<LoadSDNode>(Elt.getNode());
5929 if (Elt.getOpcode() == ISD::UNDEF)
5932 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5933 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5938 // If we have found an entire vector of loads and undefs, then return a large
5939 // load of the entire vector width starting at the base pointer. If we found
5940 // consecutive loads for the low half, generate a vzext_load node.
5941 if (LastLoadedElt == NumElems - 1) {
5943 if (isAfterLegalize &&
5944 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5947 SDValue NewLd = SDValue();
5949 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5950 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5951 LDBase->getPointerInfo(),
5952 LDBase->isVolatile(), LDBase->isNonTemporal(),
5953 LDBase->isInvariant(), 0);
5954 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5955 LDBase->getPointerInfo(),
5956 LDBase->isVolatile(), LDBase->isNonTemporal(),
5957 LDBase->isInvariant(), LDBase->getAlignment());
5959 if (LDBase->hasAnyUseOfValue(1)) {
5960 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5962 SDValue(NewLd.getNode(), 1));
5963 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5964 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5965 SDValue(NewLd.getNode(), 1));
5970 if (NumElems == 4 && LastLoadedElt == 1 &&
5971 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5972 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5973 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5975 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5976 LDBase->getPointerInfo(),
5977 LDBase->getAlignment(),
5978 false/*isVolatile*/, true/*ReadMem*/,
5981 // Make sure the newly-created LOAD is in the same position as LDBase in
5982 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5983 // update uses of LDBase's output chain to use the TokenFactor.
5984 if (LDBase->hasAnyUseOfValue(1)) {
5985 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5986 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5987 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5988 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5989 SDValue(ResNode.getNode(), 1));
5992 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5997 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5998 /// to generate a splat value for the following cases:
5999 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6000 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6001 /// a scalar load, or a constant.
6002 /// The VBROADCAST node is returned when a pattern is found,
6003 /// or SDValue() otherwise.
6004 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6005 SelectionDAG &DAG) {
6006 // VBROADCAST requires AVX.
6007 // TODO: Splats could be generated for non-AVX CPUs using SSE
6008 // instructions, but there's less potential gain for only 128-bit vectors.
6009 if (!Subtarget->hasAVX())
6012 MVT VT = Op.getSimpleValueType();
6015 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6016 "Unsupported vector type for broadcast.");
6021 switch (Op.getOpcode()) {
6023 // Unknown pattern found.
6026 case ISD::BUILD_VECTOR: {
6027 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6028 BitVector UndefElements;
6029 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6031 // We need a splat of a single value to use broadcast, and it doesn't
6032 // make any sense if the value is only in one element of the vector.
6033 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6037 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6038 Ld.getOpcode() == ISD::ConstantFP);
6040 // Make sure that all of the users of a non-constant load are from the
6041 // BUILD_VECTOR node.
6042 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6047 case ISD::VECTOR_SHUFFLE: {
6048 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6050 // Shuffles must have a splat mask where the first element is
6052 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6055 SDValue Sc = Op.getOperand(0);
6056 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6057 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6059 if (!Subtarget->hasInt256())
6062 // Use the register form of the broadcast instruction available on AVX2.
6063 if (VT.getSizeInBits() >= 256)
6064 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6065 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6068 Ld = Sc.getOperand(0);
6069 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6070 Ld.getOpcode() == ISD::ConstantFP);
6072 // The scalar_to_vector node and the suspected
6073 // load node must have exactly one user.
6074 // Constants may have multiple users.
6076 // AVX-512 has register version of the broadcast
6077 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6078 Ld.getValueType().getSizeInBits() >= 32;
6079 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6086 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6087 bool IsGE256 = (VT.getSizeInBits() >= 256);
6089 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6090 // instruction to save 8 or more bytes of constant pool data.
6091 // TODO: If multiple splats are generated to load the same constant,
6092 // it may be detrimental to overall size. There needs to be a way to detect
6093 // that condition to know if this is truly a size win.
6094 const Function *F = DAG.getMachineFunction().getFunction();
6095 bool OptForSize = F->getAttributes().
6096 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6098 // Handle broadcasting a single constant scalar from the constant pool
6100 // On Sandybridge (no AVX2), it is still better to load a constant vector
6101 // from the constant pool and not to broadcast it from a scalar.
6102 // But override that restriction when optimizing for size.
6103 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6104 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6105 EVT CVT = Ld.getValueType();
6106 assert(!CVT.isVector() && "Must not broadcast a vector type");
6108 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6109 // For size optimization, also splat v2f64 and v2i64, and for size opt
6110 // with AVX2, also splat i8 and i16.
6111 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6112 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6113 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6114 const Constant *C = nullptr;
6115 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6116 C = CI->getConstantIntValue();
6117 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6118 C = CF->getConstantFPValue();
6120 assert(C && "Invalid constant type");
6122 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6123 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6124 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6125 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6126 MachinePointerInfo::getConstantPool(),
6127 false, false, false, Alignment);
6129 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6133 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6135 // Handle AVX2 in-register broadcasts.
6136 if (!IsLoad && Subtarget->hasInt256() &&
6137 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6138 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6140 // The scalar source must be a normal load.
6144 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6145 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6147 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6148 // double since there is no vbroadcastsd xmm
6149 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6150 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6151 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6154 // Unsupported broadcast.
6158 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6159 /// underlying vector and index.
6161 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6163 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6165 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6166 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6169 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6171 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6173 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6174 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6177 // In this case the vector is the extract_subvector expression and the index
6178 // is 2, as specified by the shuffle.
6179 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6180 SDValue ShuffleVec = SVOp->getOperand(0);
6181 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6182 assert(ShuffleVecVT.getVectorElementType() ==
6183 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6185 int ShuffleIdx = SVOp->getMaskElt(Idx);
6186 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6187 ExtractedFromVec = ShuffleVec;
6193 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6194 MVT VT = Op.getSimpleValueType();
6196 // Skip if insert_vec_elt is not supported.
6197 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6198 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6202 unsigned NumElems = Op.getNumOperands();
6206 SmallVector<unsigned, 4> InsertIndices;
6207 SmallVector<int, 8> Mask(NumElems, -1);
6209 for (unsigned i = 0; i != NumElems; ++i) {
6210 unsigned Opc = Op.getOperand(i).getOpcode();
6212 if (Opc == ISD::UNDEF)
6215 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6216 // Quit if more than 1 elements need inserting.
6217 if (InsertIndices.size() > 1)
6220 InsertIndices.push_back(i);
6224 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6225 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6226 // Quit if non-constant index.
6227 if (!isa<ConstantSDNode>(ExtIdx))
6229 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6231 // Quit if extracted from vector of different type.
6232 if (ExtractedFromVec.getValueType() != VT)
6235 if (!VecIn1.getNode())
6236 VecIn1 = ExtractedFromVec;
6237 else if (VecIn1 != ExtractedFromVec) {
6238 if (!VecIn2.getNode())
6239 VecIn2 = ExtractedFromVec;
6240 else if (VecIn2 != ExtractedFromVec)
6241 // Quit if more than 2 vectors to shuffle
6245 if (ExtractedFromVec == VecIn1)
6247 else if (ExtractedFromVec == VecIn2)
6248 Mask[i] = Idx + NumElems;
6251 if (!VecIn1.getNode())
6254 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6255 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6256 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6257 unsigned Idx = InsertIndices[i];
6258 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6259 DAG.getIntPtrConstant(Idx));
6265 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6267 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6269 MVT VT = Op.getSimpleValueType();
6270 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6271 "Unexpected type in LowerBUILD_VECTORvXi1!");
6274 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6275 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6276 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6277 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6280 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6281 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6282 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6283 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6286 bool AllContants = true;
6287 uint64_t Immediate = 0;
6288 int NonConstIdx = -1;
6289 bool IsSplat = true;
6290 unsigned NumNonConsts = 0;
6291 unsigned NumConsts = 0;
6292 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6293 SDValue In = Op.getOperand(idx);
6294 if (In.getOpcode() == ISD::UNDEF)
6296 if (!isa<ConstantSDNode>(In)) {
6297 AllContants = false;
6303 if (cast<ConstantSDNode>(In)->getZExtValue())
6304 Immediate |= (1ULL << idx);
6306 if (In != Op.getOperand(0))
6311 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6312 DAG.getConstant(Immediate, MVT::i16));
6313 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6314 DAG.getIntPtrConstant(0));
6317 if (NumNonConsts == 1 && NonConstIdx != 0) {
6320 SDValue VecAsImm = DAG.getConstant(Immediate,
6321 MVT::getIntegerVT(VT.getSizeInBits()));
6322 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6325 DstVec = DAG.getUNDEF(VT);
6326 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6327 Op.getOperand(NonConstIdx),
6328 DAG.getIntPtrConstant(NonConstIdx));
6330 if (!IsSplat && (NonConstIdx != 0))
6331 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6332 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6335 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6336 DAG.getConstant(-1, SelectVT),
6337 DAG.getConstant(0, SelectVT));
6339 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6340 DAG.getConstant((Immediate | 1), SelectVT),
6341 DAG.getConstant(Immediate, SelectVT));
6342 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6345 /// \brief Return true if \p N implements a horizontal binop and return the
6346 /// operands for the horizontal binop into V0 and V1.
6348 /// This is a helper function of PerformBUILD_VECTORCombine.
6349 /// This function checks that the build_vector \p N in input implements a
6350 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6351 /// operation to match.
6352 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6353 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6354 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6357 /// This function only analyzes elements of \p N whose indices are
6358 /// in range [BaseIdx, LastIdx).
6359 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6361 unsigned BaseIdx, unsigned LastIdx,
6362 SDValue &V0, SDValue &V1) {
6363 EVT VT = N->getValueType(0);
6365 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6366 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6367 "Invalid Vector in input!");
6369 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6370 bool CanFold = true;
6371 unsigned ExpectedVExtractIdx = BaseIdx;
6372 unsigned NumElts = LastIdx - BaseIdx;
6373 V0 = DAG.getUNDEF(VT);
6374 V1 = DAG.getUNDEF(VT);
6376 // Check if N implements a horizontal binop.
6377 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6378 SDValue Op = N->getOperand(i + BaseIdx);
6381 if (Op->getOpcode() == ISD::UNDEF) {
6382 // Update the expected vector extract index.
6383 if (i * 2 == NumElts)
6384 ExpectedVExtractIdx = BaseIdx;
6385 ExpectedVExtractIdx += 2;
6389 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6394 SDValue Op0 = Op.getOperand(0);
6395 SDValue Op1 = Op.getOperand(1);
6397 // Try to match the following pattern:
6398 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6399 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6400 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6401 Op0.getOperand(0) == Op1.getOperand(0) &&
6402 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6403 isa<ConstantSDNode>(Op1.getOperand(1)));
6407 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6408 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6410 if (i * 2 < NumElts) {
6411 if (V0.getOpcode() == ISD::UNDEF)
6412 V0 = Op0.getOperand(0);
6414 if (V1.getOpcode() == ISD::UNDEF)
6415 V1 = Op0.getOperand(0);
6416 if (i * 2 == NumElts)
6417 ExpectedVExtractIdx = BaseIdx;
6420 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6421 if (I0 == ExpectedVExtractIdx)
6422 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6423 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6424 // Try to match the following dag sequence:
6425 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6426 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6430 ExpectedVExtractIdx += 2;
6436 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6437 /// a concat_vector.
6439 /// This is a helper function of PerformBUILD_VECTORCombine.
6440 /// This function expects two 256-bit vectors called V0 and V1.
6441 /// At first, each vector is split into two separate 128-bit vectors.
6442 /// Then, the resulting 128-bit vectors are used to implement two
6443 /// horizontal binary operations.
6445 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6447 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6448 /// the two new horizontal binop.
6449 /// When Mode is set, the first horizontal binop dag node would take as input
6450 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6451 /// horizontal binop dag node would take as input the lower 128-bit of V1
6452 /// and the upper 128-bit of V1.
6454 /// HADD V0_LO, V0_HI
6455 /// HADD V1_LO, V1_HI
6457 /// Otherwise, the first horizontal binop dag node takes as input the lower
6458 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6459 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6461 /// HADD V0_LO, V1_LO
6462 /// HADD V0_HI, V1_HI
6464 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6465 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6466 /// the upper 128-bits of the result.
6467 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6468 SDLoc DL, SelectionDAG &DAG,
6469 unsigned X86Opcode, bool Mode,
6470 bool isUndefLO, bool isUndefHI) {
6471 EVT VT = V0.getValueType();
6472 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6473 "Invalid nodes in input!");
6475 unsigned NumElts = VT.getVectorNumElements();
6476 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6477 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6478 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6479 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6480 EVT NewVT = V0_LO.getValueType();
6482 SDValue LO = DAG.getUNDEF(NewVT);
6483 SDValue HI = DAG.getUNDEF(NewVT);
6486 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6487 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6488 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6489 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6490 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6492 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6493 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6494 V1_LO->getOpcode() != ISD::UNDEF))
6495 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6497 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6498 V1_HI->getOpcode() != ISD::UNDEF))
6499 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6502 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6505 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6506 /// sequence of 'vadd + vsub + blendi'.
6507 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6508 const X86Subtarget *Subtarget) {
6510 EVT VT = BV->getValueType(0);
6511 unsigned NumElts = VT.getVectorNumElements();
6512 SDValue InVec0 = DAG.getUNDEF(VT);
6513 SDValue InVec1 = DAG.getUNDEF(VT);
6515 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6516 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6518 // Odd-numbered elements in the input build vector are obtained from
6519 // adding two integer/float elements.
6520 // Even-numbered elements in the input build vector are obtained from
6521 // subtracting two integer/float elements.
6522 unsigned ExpectedOpcode = ISD::FSUB;
6523 unsigned NextExpectedOpcode = ISD::FADD;
6524 bool AddFound = false;
6525 bool SubFound = false;
6527 for (unsigned i = 0, e = NumElts; i != e; i++) {
6528 SDValue Op = BV->getOperand(i);
6530 // Skip 'undef' values.
6531 unsigned Opcode = Op.getOpcode();
6532 if (Opcode == ISD::UNDEF) {
6533 std::swap(ExpectedOpcode, NextExpectedOpcode);
6537 // Early exit if we found an unexpected opcode.
6538 if (Opcode != ExpectedOpcode)
6541 SDValue Op0 = Op.getOperand(0);
6542 SDValue Op1 = Op.getOperand(1);
6544 // Try to match the following pattern:
6545 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6546 // Early exit if we cannot match that sequence.
6547 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6548 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6549 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6550 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6551 Op0.getOperand(1) != Op1.getOperand(1))
6554 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6558 // We found a valid add/sub node. Update the information accordingly.
6564 // Update InVec0 and InVec1.
6565 if (InVec0.getOpcode() == ISD::UNDEF)
6566 InVec0 = Op0.getOperand(0);
6567 if (InVec1.getOpcode() == ISD::UNDEF)
6568 InVec1 = Op1.getOperand(0);
6570 // Make sure that operands in input to each add/sub node always
6571 // come from a same pair of vectors.
6572 if (InVec0 != Op0.getOperand(0)) {
6573 if (ExpectedOpcode == ISD::FSUB)
6576 // FADD is commutable. Try to commute the operands
6577 // and then test again.
6578 std::swap(Op0, Op1);
6579 if (InVec0 != Op0.getOperand(0))
6583 if (InVec1 != Op1.getOperand(0))
6586 // Update the pair of expected opcodes.
6587 std::swap(ExpectedOpcode, NextExpectedOpcode);
6590 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6591 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6592 InVec1.getOpcode() != ISD::UNDEF)
6593 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6598 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6599 const X86Subtarget *Subtarget) {
6601 EVT VT = N->getValueType(0);
6602 unsigned NumElts = VT.getVectorNumElements();
6603 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6604 SDValue InVec0, InVec1;
6606 // Try to match an ADDSUB.
6607 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6608 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6609 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6610 if (Value.getNode())
6614 // Try to match horizontal ADD/SUB.
6615 unsigned NumUndefsLO = 0;
6616 unsigned NumUndefsHI = 0;
6617 unsigned Half = NumElts/2;
6619 // Count the number of UNDEF operands in the build_vector in input.
6620 for (unsigned i = 0, e = Half; i != e; ++i)
6621 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6624 for (unsigned i = Half, e = NumElts; i != e; ++i)
6625 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6628 // Early exit if this is either a build_vector of all UNDEFs or all the
6629 // operands but one are UNDEF.
6630 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6633 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6634 // Try to match an SSE3 float HADD/HSUB.
6635 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6636 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6638 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6639 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6640 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6641 // Try to match an SSSE3 integer HADD/HSUB.
6642 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6643 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6645 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6646 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6649 if (!Subtarget->hasAVX())
6652 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6653 // Try to match an AVX horizontal add/sub of packed single/double
6654 // precision floating point values from 256-bit vectors.
6655 SDValue InVec2, InVec3;
6656 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6657 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6658 ((InVec0.getOpcode() == ISD::UNDEF ||
6659 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6660 ((InVec1.getOpcode() == ISD::UNDEF ||
6661 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6662 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6664 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6665 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6666 ((InVec0.getOpcode() == ISD::UNDEF ||
6667 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6668 ((InVec1.getOpcode() == ISD::UNDEF ||
6669 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6670 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6671 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6672 // Try to match an AVX2 horizontal add/sub of signed integers.
6673 SDValue InVec2, InVec3;
6675 bool CanFold = true;
6677 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6678 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6679 ((InVec0.getOpcode() == ISD::UNDEF ||
6680 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6681 ((InVec1.getOpcode() == ISD::UNDEF ||
6682 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6683 X86Opcode = X86ISD::HADD;
6684 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6685 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6686 ((InVec0.getOpcode() == ISD::UNDEF ||
6687 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6688 ((InVec1.getOpcode() == ISD::UNDEF ||
6689 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6690 X86Opcode = X86ISD::HSUB;
6695 // Fold this build_vector into a single horizontal add/sub.
6696 // Do this only if the target has AVX2.
6697 if (Subtarget->hasAVX2())
6698 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6700 // Do not try to expand this build_vector into a pair of horizontal
6701 // add/sub if we can emit a pair of scalar add/sub.
6702 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6705 // Convert this build_vector into a pair of horizontal binop followed by
6707 bool isUndefLO = NumUndefsLO == Half;
6708 bool isUndefHI = NumUndefsHI == Half;
6709 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6710 isUndefLO, isUndefHI);
6714 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6715 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6717 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6718 X86Opcode = X86ISD::HADD;
6719 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6720 X86Opcode = X86ISD::HSUB;
6721 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6722 X86Opcode = X86ISD::FHADD;
6723 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6724 X86Opcode = X86ISD::FHSUB;
6728 // Don't try to expand this build_vector into a pair of horizontal add/sub
6729 // if we can simply emit a pair of scalar add/sub.
6730 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6733 // Convert this build_vector into two horizontal add/sub followed by
6735 bool isUndefLO = NumUndefsLO == Half;
6736 bool isUndefHI = NumUndefsHI == Half;
6737 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6738 isUndefLO, isUndefHI);
6745 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6748 MVT VT = Op.getSimpleValueType();
6749 MVT ExtVT = VT.getVectorElementType();
6750 unsigned NumElems = Op.getNumOperands();
6752 // Generate vectors for predicate vectors.
6753 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6754 return LowerBUILD_VECTORvXi1(Op, DAG);
6756 // Vectors containing all zeros can be matched by pxor and xorps later
6757 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6758 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6759 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6760 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6763 return getZeroVector(VT, Subtarget, DAG, dl);
6766 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6767 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6768 // vpcmpeqd on 256-bit vectors.
6769 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6770 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6773 if (!VT.is512BitVector())
6774 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6777 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6778 if (Broadcast.getNode())
6781 unsigned EVTBits = ExtVT.getSizeInBits();
6783 unsigned NumZero = 0;
6784 unsigned NumNonZero = 0;
6785 unsigned NonZeros = 0;
6786 bool IsAllConstants = true;
6787 SmallSet<SDValue, 8> Values;
6788 for (unsigned i = 0; i < NumElems; ++i) {
6789 SDValue Elt = Op.getOperand(i);
6790 if (Elt.getOpcode() == ISD::UNDEF)
6793 if (Elt.getOpcode() != ISD::Constant &&
6794 Elt.getOpcode() != ISD::ConstantFP)
6795 IsAllConstants = false;
6796 if (X86::isZeroNode(Elt))
6799 NonZeros |= (1 << i);
6804 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6805 if (NumNonZero == 0)
6806 return DAG.getUNDEF(VT);
6808 // Special case for single non-zero, non-undef, element.
6809 if (NumNonZero == 1) {
6810 unsigned Idx = countTrailingZeros(NonZeros);
6811 SDValue Item = Op.getOperand(Idx);
6813 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6814 // the value are obviously zero, truncate the value to i32 and do the
6815 // insertion that way. Only do this if the value is non-constant or if the
6816 // value is a constant being inserted into element 0. It is cheaper to do
6817 // a constant pool load than it is to do a movd + shuffle.
6818 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6819 (!IsAllConstants || Idx == 0)) {
6820 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6822 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6823 EVT VecVT = MVT::v4i32;
6824 unsigned VecElts = 4;
6826 // Truncate the value (which may itself be a constant) to i32, and
6827 // convert it to a vector with movd (S2V+shuffle to zero extend).
6828 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6829 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6831 // If using the new shuffle lowering, just directly insert this.
6832 if (ExperimentalVectorShuffleLowering)
6834 ISD::BITCAST, dl, VT,
6835 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6837 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6839 // Now we have our 32-bit value zero extended in the low element of
6840 // a vector. If Idx != 0, swizzle it into place.
6842 SmallVector<int, 4> Mask;
6843 Mask.push_back(Idx);
6844 for (unsigned i = 1; i != VecElts; ++i)
6846 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6849 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6853 // If we have a constant or non-constant insertion into the low element of
6854 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6855 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6856 // depending on what the source datatype is.
6859 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6861 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6862 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6863 if (VT.is256BitVector() || VT.is512BitVector()) {
6864 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6865 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6866 Item, DAG.getIntPtrConstant(0));
6868 assert(VT.is128BitVector() && "Expected an SSE value type!");
6869 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6870 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6871 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6874 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6875 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6876 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6877 if (VT.is256BitVector()) {
6878 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6879 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6881 assert(VT.is128BitVector() && "Expected an SSE value type!");
6882 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6884 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6888 // Is it a vector logical left shift?
6889 if (NumElems == 2 && Idx == 1 &&
6890 X86::isZeroNode(Op.getOperand(0)) &&
6891 !X86::isZeroNode(Op.getOperand(1))) {
6892 unsigned NumBits = VT.getSizeInBits();
6893 return getVShift(true, VT,
6894 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6895 VT, Op.getOperand(1)),
6896 NumBits/2, DAG, *this, dl);
6899 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6902 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6903 // is a non-constant being inserted into an element other than the low one,
6904 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6905 // movd/movss) to move this into the low element, then shuffle it into
6907 if (EVTBits == 32) {
6908 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6910 // If using the new shuffle lowering, just directly insert this.
6911 if (ExperimentalVectorShuffleLowering)
6912 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6914 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6915 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6916 SmallVector<int, 8> MaskVec;
6917 for (unsigned i = 0; i != NumElems; ++i)
6918 MaskVec.push_back(i == Idx ? 0 : 1);
6919 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6923 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6924 if (Values.size() == 1) {
6925 if (EVTBits == 32) {
6926 // Instead of a shuffle like this:
6927 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6928 // Check if it's possible to issue this instead.
6929 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6930 unsigned Idx = countTrailingZeros(NonZeros);
6931 SDValue Item = Op.getOperand(Idx);
6932 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6933 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6938 // A vector full of immediates; various special cases are already
6939 // handled, so this is best done with a single constant-pool load.
6943 // For AVX-length vectors, build the individual 128-bit pieces and use
6944 // shuffles to put them in place.
6945 if (VT.is256BitVector() || VT.is512BitVector()) {
6946 SmallVector<SDValue, 64> V;
6947 for (unsigned i = 0; i != NumElems; ++i)
6948 V.push_back(Op.getOperand(i));
6950 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6952 // Build both the lower and upper subvector.
6953 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6954 makeArrayRef(&V[0], NumElems/2));
6955 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6956 makeArrayRef(&V[NumElems / 2], NumElems/2));
6958 // Recreate the wider vector with the lower and upper part.
6959 if (VT.is256BitVector())
6960 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6961 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6964 // Let legalizer expand 2-wide build_vectors.
6965 if (EVTBits == 64) {
6966 if (NumNonZero == 1) {
6967 // One half is zero or undef.
6968 unsigned Idx = countTrailingZeros(NonZeros);
6969 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6970 Op.getOperand(Idx));
6971 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6976 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6977 if (EVTBits == 8 && NumElems == 16) {
6978 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6980 if (V.getNode()) return V;
6983 if (EVTBits == 16 && NumElems == 8) {
6984 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6986 if (V.getNode()) return V;
6989 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6990 if (EVTBits == 32 && NumElems == 4) {
6991 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6992 NumZero, DAG, Subtarget, *this);
6997 // If element VT is == 32 bits, turn it into a number of shuffles.
6998 SmallVector<SDValue, 8> V(NumElems);
6999 if (NumElems == 4 && NumZero > 0) {
7000 for (unsigned i = 0; i < 4; ++i) {
7001 bool isZero = !(NonZeros & (1 << i));
7003 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7005 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7008 for (unsigned i = 0; i < 2; ++i) {
7009 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7012 V[i] = V[i*2]; // Must be a zero vector.
7015 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7018 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7021 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7026 bool Reverse1 = (NonZeros & 0x3) == 2;
7027 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7031 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7032 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7034 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7037 if (Values.size() > 1 && VT.is128BitVector()) {
7038 // Check for a build vector of consecutive loads.
7039 for (unsigned i = 0; i < NumElems; ++i)
7040 V[i] = Op.getOperand(i);
7042 // Check for elements which are consecutive loads.
7043 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7047 // Check for a build vector from mostly shuffle plus few inserting.
7048 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7052 // For SSE 4.1, use insertps to put the high elements into the low element.
7053 if (getSubtarget()->hasSSE41()) {
7055 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7056 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7058 Result = DAG.getUNDEF(VT);
7060 for (unsigned i = 1; i < NumElems; ++i) {
7061 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7062 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7063 Op.getOperand(i), DAG.getIntPtrConstant(i));
7068 // Otherwise, expand into a number of unpckl*, start by extending each of
7069 // our (non-undef) elements to the full vector width with the element in the
7070 // bottom slot of the vector (which generates no code for SSE).
7071 for (unsigned i = 0; i < NumElems; ++i) {
7072 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7073 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7075 V[i] = DAG.getUNDEF(VT);
7078 // Next, we iteratively mix elements, e.g. for v4f32:
7079 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7080 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7081 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7082 unsigned EltStride = NumElems >> 1;
7083 while (EltStride != 0) {
7084 for (unsigned i = 0; i < EltStride; ++i) {
7085 // If V[i+EltStride] is undef and this is the first round of mixing,
7086 // then it is safe to just drop this shuffle: V[i] is already in the
7087 // right place, the one element (since it's the first round) being
7088 // inserted as undef can be dropped. This isn't safe for successive
7089 // rounds because they will permute elements within both vectors.
7090 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7091 EltStride == NumElems/2)
7094 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7103 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7104 // to create 256-bit vectors from two other 128-bit ones.
7105 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7107 MVT ResVT = Op.getSimpleValueType();
7109 assert((ResVT.is256BitVector() ||
7110 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7112 SDValue V1 = Op.getOperand(0);
7113 SDValue V2 = Op.getOperand(1);
7114 unsigned NumElems = ResVT.getVectorNumElements();
7115 if(ResVT.is256BitVector())
7116 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7118 if (Op.getNumOperands() == 4) {
7119 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7120 ResVT.getVectorNumElements()/2);
7121 SDValue V3 = Op.getOperand(2);
7122 SDValue V4 = Op.getOperand(3);
7123 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7124 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7126 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7129 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7130 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7131 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7132 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7133 Op.getNumOperands() == 4)));
7135 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7136 // from two other 128-bit ones.
7138 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7139 return LowerAVXCONCAT_VECTORS(Op, DAG);
7143 //===----------------------------------------------------------------------===//
7144 // Vector shuffle lowering
7146 // This is an experimental code path for lowering vector shuffles on x86. It is
7147 // designed to handle arbitrary vector shuffles and blends, gracefully
7148 // degrading performance as necessary. It works hard to recognize idiomatic
7149 // shuffles and lower them to optimal instruction patterns without leaving
7150 // a framework that allows reasonably efficient handling of all vector shuffle
7152 //===----------------------------------------------------------------------===//
7154 /// \brief Tiny helper function to identify a no-op mask.
7156 /// This is a somewhat boring predicate function. It checks whether the mask
7157 /// array input, which is assumed to be a single-input shuffle mask of the kind
7158 /// used by the X86 shuffle instructions (not a fully general
7159 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7160 /// in-place shuffle are 'no-op's.
7161 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7162 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7163 if (Mask[i] != -1 && Mask[i] != i)
7168 /// \brief Helper function to classify a mask as a single-input mask.
7170 /// This isn't a generic single-input test because in the vector shuffle
7171 /// lowering we canonicalize single inputs to be the first input operand. This
7172 /// means we can more quickly test for a single input by only checking whether
7173 /// an input from the second operand exists. We also assume that the size of
7174 /// mask corresponds to the size of the input vectors which isn't true in the
7175 /// fully general case.
7176 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7178 if (M >= (int)Mask.size())
7183 /// \brief Test whether there are elements crossing 128-bit lanes in this
7186 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7187 /// and we routinely test for these.
7188 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7189 int LaneSize = 128 / VT.getScalarSizeInBits();
7190 int Size = Mask.size();
7191 for (int i = 0; i < Size; ++i)
7192 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7197 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7199 /// This checks a shuffle mask to see if it is performing the same
7200 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7201 /// that it is also not lane-crossing. It may however involve a blend from the
7202 /// same lane of a second vector.
7204 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7205 /// non-trivial to compute in the face of undef lanes. The representation is
7206 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7207 /// entries from both V1 and V2 inputs to the wider mask.
7209 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7210 SmallVectorImpl<int> &RepeatedMask) {
7211 int LaneSize = 128 / VT.getScalarSizeInBits();
7212 RepeatedMask.resize(LaneSize, -1);
7213 int Size = Mask.size();
7214 for (int i = 0; i < Size; ++i) {
7217 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7218 // This entry crosses lanes, so there is no way to model this shuffle.
7221 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7222 if (RepeatedMask[i % LaneSize] == -1)
7223 // This is the first non-undef entry in this slot of a 128-bit lane.
7224 RepeatedMask[i % LaneSize] =
7225 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7226 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7227 // Found a mismatch with the repeated mask.
7233 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7234 // 2013 will allow us to use it as a non-type template parameter.
7237 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7239 /// See its documentation for details.
7240 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7241 if (Mask.size() != Args.size())
7243 for (int i = 0, e = Mask.size(); i < e; ++i) {
7244 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7245 if (Mask[i] != -1 && Mask[i] != *Args[i])
7253 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7256 /// This is a fast way to test a shuffle mask against a fixed pattern:
7258 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7260 /// It returns true if the mask is exactly as wide as the argument list, and
7261 /// each element of the mask is either -1 (signifying undef) or the value given
7262 /// in the argument.
7263 static const VariadicFunction1<
7264 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7266 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7268 /// This helper function produces an 8-bit shuffle immediate corresponding to
7269 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7270 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7273 /// NB: We rely heavily on "undef" masks preserving the input lane.
7274 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7275 SelectionDAG &DAG) {
7276 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7277 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7278 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7279 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7280 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7283 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7284 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7285 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7286 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7287 return DAG.getConstant(Imm, MVT::i8);
7290 /// \brief Try to emit a blend instruction for a shuffle.
7292 /// This doesn't do any checks for the availability of instructions for blending
7293 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7294 /// be matched in the backend with the type given. What it does check for is
7295 /// that the shuffle mask is in fact a blend.
7296 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7297 SDValue V2, ArrayRef<int> Mask,
7298 const X86Subtarget *Subtarget,
7299 SelectionDAG &DAG) {
7301 unsigned BlendMask = 0;
7302 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7303 if (Mask[i] >= Size) {
7304 if (Mask[i] != i + Size)
7305 return SDValue(); // Shuffled V2 input!
7306 BlendMask |= 1u << i;
7309 if (Mask[i] >= 0 && Mask[i] != i)
7310 return SDValue(); // Shuffled V1 input!
7312 switch (VT.SimpleTy) {
7317 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7318 DAG.getConstant(BlendMask, MVT::i8));
7322 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7326 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7327 // that instruction.
7328 if (Subtarget->hasAVX2()) {
7329 // Scale the blend by the number of 32-bit dwords per element.
7330 int Scale = VT.getScalarSizeInBits() / 32;
7332 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7333 if (Mask[i] >= Size)
7334 for (int j = 0; j < Scale; ++j)
7335 BlendMask |= 1u << (i * Scale + j);
7337 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7338 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7339 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7340 return DAG.getNode(ISD::BITCAST, DL, VT,
7341 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7342 DAG.getConstant(BlendMask, MVT::i8)));
7346 // For integer shuffles we need to expand the mask and cast the inputs to
7347 // v8i16s prior to blending.
7348 int Scale = 8 / VT.getVectorNumElements();
7350 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7351 if (Mask[i] >= Size)
7352 for (int j = 0; j < Scale; ++j)
7353 BlendMask |= 1u << (i * Scale + j);
7355 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7356 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7357 return DAG.getNode(ISD::BITCAST, DL, VT,
7358 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7359 DAG.getConstant(BlendMask, MVT::i8)));
7363 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7364 SmallVector<int, 8> RepeatedMask;
7365 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7366 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7367 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7369 for (int i = 0; i < 8; ++i)
7370 if (RepeatedMask[i] >= 16)
7371 BlendMask |= 1u << i;
7372 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7373 DAG.getConstant(BlendMask, MVT::i8));
7378 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7379 // Scale the blend by the number of bytes per element.
7380 int Scale = VT.getScalarSizeInBits() / 8;
7381 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7383 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7384 // mix of LLVM's code generator and the x86 backend. We tell the code
7385 // generator that boolean values in the elements of an x86 vector register
7386 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7387 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7388 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7389 // of the element (the remaining are ignored) and 0 in that high bit would
7390 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7391 // the LLVM model for boolean values in vector elements gets the relevant
7392 // bit set, it is set backwards and over constrained relative to x86's
7394 SDValue VSELECTMask[32];
7395 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7396 for (int j = 0; j < Scale; ++j)
7397 VSELECTMask[Scale * i + j] =
7398 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7399 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7401 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7402 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7404 ISD::BITCAST, DL, VT,
7405 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7406 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7411 llvm_unreachable("Not a supported integer vector type!");
7415 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7416 /// unblended shuffles followed by an unshuffled blend.
7418 /// This matches the extremely common pattern for handling combined
7419 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7421 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7425 SelectionDAG &DAG) {
7426 // Shuffle the input elements into the desired positions in V1 and V2 and
7427 // blend them together.
7428 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7429 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7430 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7431 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7432 if (Mask[i] >= 0 && Mask[i] < Size) {
7433 V1Mask[i] = Mask[i];
7435 } else if (Mask[i] >= Size) {
7436 V2Mask[i] = Mask[i] - Size;
7437 BlendMask[i] = i + Size;
7440 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7441 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7442 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7445 /// \brief Try to lower a vector shuffle as a byte rotation.
7447 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7448 /// byte-rotation of the concatenation of two vectors. This routine will
7449 /// try to generically lower a vector shuffle through such an instruction. It
7450 /// does not check for the availability of PALIGNR-based lowerings, only the
7451 /// applicability of this strategy to the given mask. This matches shuffle
7452 /// vectors that look like:
7454 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7456 /// Essentially it concatenates V1 and V2, shifts right by some number of
7457 /// elements, and takes the low elements as the result. Note that while this is
7458 /// specified as a *right shift* because x86 is little-endian, it is a *left
7459 /// rotate* of the vector lanes.
7461 /// Note that this only handles 128-bit vector widths currently.
7462 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7465 SelectionDAG &DAG) {
7466 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7468 // We need to detect various ways of spelling a rotation:
7469 // [11, 12, 13, 14, 15, 0, 1, 2]
7470 // [-1, 12, 13, 14, -1, -1, 1, -1]
7471 // [-1, -1, -1, -1, -1, -1, 1, 2]
7472 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7473 // [-1, 4, 5, 6, -1, -1, 9, -1]
7474 // [-1, 4, 5, 6, -1, -1, -1, -1]
7477 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7480 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7482 // Based on the mod-Size value of this mask element determine where
7483 // a rotated vector would have started.
7484 int StartIdx = i - (Mask[i] % Size);
7486 // The identity rotation isn't interesting, stop.
7489 // If we found the tail of a vector the rotation must be the missing
7490 // front. If we found the head of a vector, it must be how much of the head.
7491 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7494 Rotation = CandidateRotation;
7495 else if (Rotation != CandidateRotation)
7496 // The rotations don't match, so we can't match this mask.
7499 // Compute which value this mask is pointing at.
7500 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7502 // Compute which of the two target values this index should be assigned to.
7503 // This reflects whether the high elements are remaining or the low elements
7505 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7507 // Either set up this value if we've not encountered it before, or check
7508 // that it remains consistent.
7511 else if (TargetV != MaskV)
7512 // This may be a rotation, but it pulls from the inputs in some
7513 // unsupported interleaving.
7517 // Check that we successfully analyzed the mask, and normalize the results.
7518 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7519 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7525 // Cast the inputs to v16i8 to match PALIGNR.
7526 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7527 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7529 assert(VT.getSizeInBits() == 128 &&
7530 "Rotate-based lowering only supports 128-bit lowering!");
7531 assert(Mask.size() <= 16 &&
7532 "Can shuffle at most 16 bytes in a 128-bit vector!");
7533 // The actual rotate instruction rotates bytes, so we need to scale the
7534 // rotation based on how many bytes are in the vector.
7535 int Scale = 16 / Mask.size();
7537 return DAG.getNode(ISD::BITCAST, DL, VT,
7538 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7539 DAG.getConstant(Rotation * Scale, MVT::i8)));
7542 /// \brief Compute whether each element of a shuffle is zeroable.
7544 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7545 /// Either it is an undef element in the shuffle mask, the element of the input
7546 /// referenced is undef, or the element of the input referenced is known to be
7547 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7548 /// as many lanes with this technique as possible to simplify the remaining
7550 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7551 SDValue V1, SDValue V2) {
7552 SmallBitVector Zeroable(Mask.size(), false);
7554 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7555 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7557 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7559 // Handle the easy cases.
7560 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7565 // If this is an index into a build_vector node, dig out the input value and
7567 SDValue V = M < Size ? V1 : V2;
7568 if (V.getOpcode() != ISD::BUILD_VECTOR)
7571 SDValue Input = V.getOperand(M % Size);
7572 // The UNDEF opcode check really should be dead code here, but not quite
7573 // worth asserting on (it isn't invalid, just unexpected).
7574 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7581 /// \brief Lower a vector shuffle as a zero or any extension.
7583 /// Given a specific number of elements, element bit width, and extension
7584 /// stride, produce either a zero or any extension based on the available
7585 /// features of the subtarget.
7586 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7587 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7588 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7589 assert(Scale > 1 && "Need a scale to extend.");
7590 int EltBits = VT.getSizeInBits() / NumElements;
7591 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7592 "Only 8, 16, and 32 bit elements can be extended.");
7593 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7595 // Found a valid zext mask! Try various lowering strategies based on the
7596 // input type and available ISA extensions.
7597 if (Subtarget->hasSSE41()) {
7598 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7599 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7600 NumElements / Scale);
7601 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7602 return DAG.getNode(ISD::BITCAST, DL, VT,
7603 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7606 // For any extends we can cheat for larger element sizes and use shuffle
7607 // instructions that can fold with a load and/or copy.
7608 if (AnyExt && EltBits == 32) {
7609 int PSHUFDMask[4] = {0, -1, 1, -1};
7611 ISD::BITCAST, DL, VT,
7612 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7613 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7614 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7616 if (AnyExt && EltBits == 16 && Scale > 2) {
7617 int PSHUFDMask[4] = {0, -1, 0, -1};
7618 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7619 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7620 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7621 int PSHUFHWMask[4] = {1, -1, -1, -1};
7623 ISD::BITCAST, DL, VT,
7624 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7625 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7626 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7629 // If this would require more than 2 unpack instructions to expand, use
7630 // pshufb when available. We can only use more than 2 unpack instructions
7631 // when zero extending i8 elements which also makes it easier to use pshufb.
7632 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7633 assert(NumElements == 16 && "Unexpected byte vector width!");
7634 SDValue PSHUFBMask[16];
7635 for (int i = 0; i < 16; ++i)
7637 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7638 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7639 return DAG.getNode(ISD::BITCAST, DL, VT,
7640 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7641 DAG.getNode(ISD::BUILD_VECTOR, DL,
7642 MVT::v16i8, PSHUFBMask)));
7645 // Otherwise emit a sequence of unpacks.
7647 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7648 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7649 : getZeroVector(InputVT, Subtarget, DAG, DL);
7650 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7651 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7655 } while (Scale > 1);
7656 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7659 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7661 /// This routine will try to do everything in its power to cleverly lower
7662 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7663 /// check for the profitability of this lowering, it tries to aggressively
7664 /// match this pattern. It will use all of the micro-architectural details it
7665 /// can to emit an efficient lowering. It handles both blends with all-zero
7666 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7667 /// masking out later).
7669 /// The reason we have dedicated lowering for zext-style shuffles is that they
7670 /// are both incredibly common and often quite performance sensitive.
7671 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7672 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7673 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7674 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7676 int Bits = VT.getSizeInBits();
7677 int NumElements = Mask.size();
7679 // Define a helper function to check a particular ext-scale and lower to it if
7681 auto Lower = [&](int Scale) -> SDValue {
7684 for (int i = 0; i < NumElements; ++i) {
7686 continue; // Valid anywhere but doesn't tell us anything.
7687 if (i % Scale != 0) {
7688 // Each of the extend elements needs to be zeroable.
7692 // We no lorger are in the anyext case.
7697 // Each of the base elements needs to be consecutive indices into the
7698 // same input vector.
7699 SDValue V = Mask[i] < NumElements ? V1 : V2;
7702 else if (InputV != V)
7703 return SDValue(); // Flip-flopping inputs.
7705 if (Mask[i] % NumElements != i / Scale)
7706 return SDValue(); // Non-consecutive strided elemenst.
7709 // If we fail to find an input, we have a zero-shuffle which should always
7710 // have already been handled.
7711 // FIXME: Maybe handle this here in case during blending we end up with one?
7715 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7716 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7719 // The widest scale possible for extending is to a 64-bit integer.
7720 assert(Bits % 64 == 0 &&
7721 "The number of bits in a vector must be divisible by 64 on x86!");
7722 int NumExtElements = Bits / 64;
7724 // Each iteration, try extending the elements half as much, but into twice as
7726 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7727 assert(NumElements % NumExtElements == 0 &&
7728 "The input vector size must be divisble by the extended size.");
7729 if (SDValue V = Lower(NumElements / NumExtElements))
7733 // No viable ext lowering found.
7737 /// \brief Try to get a scalar value for a specific element of a vector.
7739 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7740 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7741 SelectionDAG &DAG) {
7742 MVT VT = V.getSimpleValueType();
7743 MVT EltVT = VT.getVectorElementType();
7744 while (V.getOpcode() == ISD::BITCAST)
7745 V = V.getOperand(0);
7746 // If the bitcasts shift the element size, we can't extract an equivalent
7748 MVT NewVT = V.getSimpleValueType();
7749 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7752 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7753 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7754 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7759 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7761 /// This is particularly important because the set of instructions varies
7762 /// significantly based on whether the operand is a load or not.
7763 static bool isShuffleFoldableLoad(SDValue V) {
7764 while (V.getOpcode() == ISD::BITCAST)
7765 V = V.getOperand(0);
7767 return ISD::isNON_EXTLoad(V.getNode());
7770 /// \brief Try to lower insertion of a single element into a zero vector.
7772 /// This is a common pattern that we have especially efficient patterns to lower
7773 /// across all subtarget feature sets.
7774 static SDValue lowerVectorShuffleAsElementInsertion(
7775 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7776 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7777 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7779 MVT EltVT = VT.getVectorElementType();
7781 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7782 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7784 bool IsV1Zeroable = true;
7785 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7786 if (i != V2Index && !Zeroable[i]) {
7787 IsV1Zeroable = false;
7791 // Check for a single input from a SCALAR_TO_VECTOR node.
7792 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7793 // all the smarts here sunk into that routine. However, the current
7794 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7795 // vector shuffle lowering is dead.
7796 if (SDValue V2S = getScalarValueForVectorElement(
7797 V2, Mask[V2Index] - Mask.size(), DAG)) {
7798 // We need to zext the scalar if it is smaller than an i32.
7799 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7800 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7801 // Using zext to expand a narrow element won't work for non-zero
7806 // Zero-extend directly to i32.
7808 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7810 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7811 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7812 EltVT == MVT::i16) {
7813 // Either not inserting from the low element of the input or the input
7814 // element size is too small to use VZEXT_MOVL to clear the high bits.
7818 if (!IsV1Zeroable) {
7819 // If V1 can't be treated as a zero vector we have fewer options to lower
7820 // this. We can't support integer vectors or non-zero targets cheaply, and
7821 // the V1 elements can't be permuted in any way.
7822 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7823 if (!VT.isFloatingPoint() || V2Index != 0)
7825 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7826 V1Mask[V2Index] = -1;
7827 if (!isNoopShuffleMask(V1Mask))
7829 // This is essentially a special case blend operation, but if we have
7830 // general purpose blend operations, they are always faster. Bail and let
7831 // the rest of the lowering handle these as blends.
7832 if (Subtarget->hasSSE41())
7835 // Otherwise, use MOVSD or MOVSS.
7836 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7837 "Only two types of floating point element types to handle!");
7838 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7842 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7844 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7847 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7848 // the desired position. Otherwise it is more efficient to do a vector
7849 // shift left. We know that we can do a vector shift left because all
7850 // the inputs are zero.
7851 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7852 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7853 V2Shuffle[V2Index] = 0;
7854 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7856 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7858 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7860 V2Index * EltVT.getSizeInBits(),
7861 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7862 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7868 /// \brief Try to lower broadcast of a single element.
7870 /// For convenience, this code also bundles all of the subtarget feature set
7871 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7872 /// a convenient way to factor it out.
7873 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
7875 const X86Subtarget *Subtarget,
7876 SelectionDAG &DAG) {
7877 if (!Subtarget->hasAVX())
7879 if (VT.isInteger() && !Subtarget->hasAVX2())
7882 // Check that the mask is a broadcast.
7883 int BroadcastIdx = -1;
7885 if (M >= 0 && BroadcastIdx == -1)
7887 else if (M >= 0 && M != BroadcastIdx)
7890 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7891 "a sorted mask where the broadcast "
7894 // Go up the chain of (vector) values to try and find a scalar load that
7895 // we can combine with the broadcast.
7897 switch (V.getOpcode()) {
7898 case ISD::CONCAT_VECTORS: {
7899 int OperandSize = Mask.size() / V.getNumOperands();
7900 V = V.getOperand(BroadcastIdx / OperandSize);
7901 BroadcastIdx %= OperandSize;
7905 case ISD::INSERT_SUBVECTOR: {
7906 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7907 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7911 int BeginIdx = (int)ConstantIdx->getZExtValue();
7913 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7914 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7915 BroadcastIdx -= BeginIdx;
7926 // Check if this is a broadcast of a scalar. We special case lowering
7927 // for scalars so that we can more effectively fold with loads.
7928 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7929 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7930 V = V.getOperand(BroadcastIdx);
7932 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
7934 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7936 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7937 // We can't broadcast from a vector register w/o AVX2, and we can only
7938 // broadcast from the zero-element of a vector register.
7942 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7945 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7947 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7948 /// support for floating point shuffles but not integer shuffles. These
7949 /// instructions will incur a domain crossing penalty on some chips though so
7950 /// it is better to avoid lowering through this for integer vectors where
7952 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7953 const X86Subtarget *Subtarget,
7954 SelectionDAG &DAG) {
7956 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7957 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7958 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7959 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7960 ArrayRef<int> Mask = SVOp->getMask();
7961 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7963 if (isSingleInputShuffleMask(Mask)) {
7964 // Straight shuffle of a single input vector. Simulate this by using the
7965 // single input as both of the "inputs" to this instruction..
7966 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7968 if (Subtarget->hasAVX()) {
7969 // If we have AVX, we can use VPERMILPS which will allow folding a load
7970 // into the shuffle.
7971 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7972 DAG.getConstant(SHUFPDMask, MVT::i8));
7975 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7976 DAG.getConstant(SHUFPDMask, MVT::i8));
7978 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7979 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7981 // Use dedicated unpack instructions for masks that match their pattern.
7982 if (isShuffleEquivalent(Mask, 0, 2))
7983 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7984 if (isShuffleEquivalent(Mask, 1, 3))
7985 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7987 // If we have a single input, insert that into V1 if we can do so cheaply.
7988 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7989 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7990 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7992 // Try inverting the insertion since for v2 masks it is easy to do and we
7993 // can't reliably sort the mask one way or the other.
7994 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7995 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7996 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7997 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8001 // Try to use one of the special instruction patterns to handle two common
8002 // blend patterns if a zero-blend above didn't work.
8003 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8004 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8005 // We can either use a special instruction to load over the low double or
8006 // to move just the low double.
8008 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8010 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8012 if (Subtarget->hasSSE41())
8013 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8017 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8018 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8019 DAG.getConstant(SHUFPDMask, MVT::i8));
8022 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8024 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8025 /// the integer unit to minimize domain crossing penalties. However, for blends
8026 /// it falls back to the floating point shuffle operation with appropriate bit
8028 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8029 const X86Subtarget *Subtarget,
8030 SelectionDAG &DAG) {
8032 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8033 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8034 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8035 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8036 ArrayRef<int> Mask = SVOp->getMask();
8037 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8039 if (isSingleInputShuffleMask(Mask)) {
8040 // Check for being able to broadcast a single element.
8041 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8042 Mask, Subtarget, DAG))
8045 // Straight shuffle of a single input vector. For everything from SSE2
8046 // onward this has a single fast instruction with no scary immediates.
8047 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8048 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8049 int WidenedMask[4] = {
8050 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8051 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8053 ISD::BITCAST, DL, MVT::v2i64,
8054 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8055 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8058 // If we have a single input from V2 insert that into V1 if we can do so
8060 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8061 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8062 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8064 // Try inverting the insertion since for v2 masks it is easy to do and we
8065 // can't reliably sort the mask one way or the other.
8066 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8067 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8068 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8069 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8073 // Use dedicated unpack instructions for masks that match their pattern.
8074 if (isShuffleEquivalent(Mask, 0, 2))
8075 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8076 if (isShuffleEquivalent(Mask, 1, 3))
8077 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8079 if (Subtarget->hasSSE41())
8080 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8084 // Try to use rotation instructions if available.
8085 if (Subtarget->hasSSSE3())
8086 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8087 DL, MVT::v2i64, V1, V2, Mask, DAG))
8090 // We implement this with SHUFPD which is pretty lame because it will likely
8091 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8092 // However, all the alternatives are still more cycles and newer chips don't
8093 // have this problem. It would be really nice if x86 had better shuffles here.
8094 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8095 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8096 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8097 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8100 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8102 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8103 /// It makes no assumptions about whether this is the *best* lowering, it simply
8105 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8106 ArrayRef<int> Mask, SDValue V1,
8107 SDValue V2, SelectionDAG &DAG) {
8108 SDValue LowV = V1, HighV = V2;
8109 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8112 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8114 if (NumV2Elements == 1) {
8116 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8119 // Compute the index adjacent to V2Index and in the same half by toggling
8121 int V2AdjIndex = V2Index ^ 1;
8123 if (Mask[V2AdjIndex] == -1) {
8124 // Handles all the cases where we have a single V2 element and an undef.
8125 // This will only ever happen in the high lanes because we commute the
8126 // vector otherwise.
8128 std::swap(LowV, HighV);
8129 NewMask[V2Index] -= 4;
8131 // Handle the case where the V2 element ends up adjacent to a V1 element.
8132 // To make this work, blend them together as the first step.
8133 int V1Index = V2AdjIndex;
8134 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8135 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8136 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8138 // Now proceed to reconstruct the final blend as we have the necessary
8139 // high or low half formed.
8146 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8147 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8149 } else if (NumV2Elements == 2) {
8150 if (Mask[0] < 4 && Mask[1] < 4) {
8151 // Handle the easy case where we have V1 in the low lanes and V2 in the
8155 } else if (Mask[2] < 4 && Mask[3] < 4) {
8156 // We also handle the reversed case because this utility may get called
8157 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8158 // arrange things in the right direction.
8164 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8165 // trying to place elements directly, just blend them and set up the final
8166 // shuffle to place them.
8168 // The first two blend mask elements are for V1, the second two are for
8170 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8171 Mask[2] < 4 ? Mask[2] : Mask[3],
8172 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8173 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8174 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8175 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8177 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8180 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8181 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8182 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8183 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8186 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8187 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8190 /// \brief Lower 4-lane 32-bit floating point shuffles.
8192 /// Uses instructions exclusively from the floating point unit to minimize
8193 /// domain crossing penalties, as these are sufficient to implement all v4f32
8195 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8196 const X86Subtarget *Subtarget,
8197 SelectionDAG &DAG) {
8199 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8200 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8201 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8202 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8203 ArrayRef<int> Mask = SVOp->getMask();
8204 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8207 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8209 if (NumV2Elements == 0) {
8210 // Check for being able to broadcast a single element.
8211 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8212 Mask, Subtarget, DAG))
8215 if (Subtarget->hasAVX()) {
8216 // If we have AVX, we can use VPERMILPS which will allow folding a load
8217 // into the shuffle.
8218 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8219 getV4X86ShuffleImm8ForMask(Mask, DAG));
8222 // Otherwise, use a straight shuffle of a single input vector. We pass the
8223 // input vector to both operands to simulate this with a SHUFPS.
8224 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8225 getV4X86ShuffleImm8ForMask(Mask, DAG));
8228 // Use dedicated unpack instructions for masks that match their pattern.
8229 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8230 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8231 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8232 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8234 // There are special ways we can lower some single-element blends. However, we
8235 // have custom ways we can lower more complex single-element blends below that
8236 // we defer to if both this and BLENDPS fail to match, so restrict this to
8237 // when the V2 input is targeting element 0 of the mask -- that is the fast
8239 if (NumV2Elements == 1 && Mask[0] >= 4)
8240 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8241 Mask, Subtarget, DAG))
8244 if (Subtarget->hasSSE41())
8245 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8249 // Check for whether we can use INSERTPS to perform the blend. We only use
8250 // INSERTPS when the V1 elements are already in the correct locations
8251 // because otherwise we can just always use two SHUFPS instructions which
8252 // are much smaller to encode than a SHUFPS and an INSERTPS.
8253 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8255 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8258 // When using INSERTPS we can zero any lane of the destination. Collect
8259 // the zero inputs into a mask and drop them from the lanes of V1 which
8260 // actually need to be present as inputs to the INSERTPS.
8261 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8263 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8264 bool InsertNeedsShuffle = false;
8266 for (int i = 0; i < 4; ++i)
8270 } else if (Mask[i] != i) {
8271 InsertNeedsShuffle = true;
8276 // We don't want to use INSERTPS or other insertion techniques if it will
8277 // require shuffling anyways.
8278 if (!InsertNeedsShuffle) {
8279 // If all of V1 is zeroable, replace it with undef.
8280 if ((ZMask | 1 << V2Index) == 0xF)
8281 V1 = DAG.getUNDEF(MVT::v4f32);
8283 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8284 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8286 // Insert the V2 element into the desired position.
8287 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8288 DAG.getConstant(InsertPSMask, MVT::i8));
8292 // Otherwise fall back to a SHUFPS lowering strategy.
8293 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8296 /// \brief Lower 4-lane i32 vector shuffles.
8298 /// We try to handle these with integer-domain shuffles where we can, but for
8299 /// blends we use the floating point domain blend instructions.
8300 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8301 const X86Subtarget *Subtarget,
8302 SelectionDAG &DAG) {
8304 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8305 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8306 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8307 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8308 ArrayRef<int> Mask = SVOp->getMask();
8309 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8311 // Whenever we can lower this as a zext, that instruction is strictly faster
8312 // than any alternative. It also allows us to fold memory operands into the
8313 // shuffle in many cases.
8314 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8315 Mask, Subtarget, DAG))
8319 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8321 if (NumV2Elements == 0) {
8322 // Check for being able to broadcast a single element.
8323 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8324 Mask, Subtarget, DAG))
8327 // Straight shuffle of a single input vector. For everything from SSE2
8328 // onward this has a single fast instruction with no scary immediates.
8329 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8330 // but we aren't actually going to use the UNPCK instruction because doing
8331 // so prevents folding a load into this instruction or making a copy.
8332 const int UnpackLoMask[] = {0, 0, 1, 1};
8333 const int UnpackHiMask[] = {2, 2, 3, 3};
8334 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8335 Mask = UnpackLoMask;
8336 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8337 Mask = UnpackHiMask;
8339 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8340 getV4X86ShuffleImm8ForMask(Mask, DAG));
8343 // There are special ways we can lower some single-element blends.
8344 if (NumV2Elements == 1)
8345 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8346 Mask, Subtarget, DAG))
8349 // Use dedicated unpack instructions for masks that match their pattern.
8350 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8351 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8352 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8353 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8355 if (Subtarget->hasSSE41())
8356 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8360 // Try to use rotation instructions if available.
8361 if (Subtarget->hasSSSE3())
8362 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8363 DL, MVT::v4i32, V1, V2, Mask, DAG))
8366 // We implement this with SHUFPS because it can blend from two vectors.
8367 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8368 // up the inputs, bypassing domain shift penalties that we would encur if we
8369 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8371 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8372 DAG.getVectorShuffle(
8374 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8375 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8378 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8379 /// shuffle lowering, and the most complex part.
8381 /// The lowering strategy is to try to form pairs of input lanes which are
8382 /// targeted at the same half of the final vector, and then use a dword shuffle
8383 /// to place them onto the right half, and finally unpack the paired lanes into
8384 /// their final position.
8386 /// The exact breakdown of how to form these dword pairs and align them on the
8387 /// correct sides is really tricky. See the comments within the function for
8388 /// more of the details.
8389 static SDValue lowerV8I16SingleInputVectorShuffle(
8390 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8391 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8392 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8393 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8394 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8396 SmallVector<int, 4> LoInputs;
8397 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8398 [](int M) { return M >= 0; });
8399 std::sort(LoInputs.begin(), LoInputs.end());
8400 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8401 SmallVector<int, 4> HiInputs;
8402 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8403 [](int M) { return M >= 0; });
8404 std::sort(HiInputs.begin(), HiInputs.end());
8405 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8407 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8408 int NumHToL = LoInputs.size() - NumLToL;
8410 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8411 int NumHToH = HiInputs.size() - NumLToH;
8412 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8413 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8414 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8415 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8417 // Check for being able to broadcast a single element.
8418 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8419 Mask, Subtarget, DAG))
8422 // Use dedicated unpack instructions for masks that match their pattern.
8423 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8424 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8425 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8426 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8428 // Try to use rotation instructions if available.
8429 if (Subtarget->hasSSSE3())
8430 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8431 DL, MVT::v8i16, V, V, Mask, DAG))
8434 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8435 // such inputs we can swap two of the dwords across the half mark and end up
8436 // with <=2 inputs to each half in each half. Once there, we can fall through
8437 // to the generic code below. For example:
8439 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8440 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8442 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8443 // and an existing 2-into-2 on the other half. In this case we may have to
8444 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8445 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8446 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8447 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8448 // half than the one we target for fixing) will be fixed when we re-enter this
8449 // path. We will also combine away any sequence of PSHUFD instructions that
8450 // result into a single instruction. Here is an example of the tricky case:
8452 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8453 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8455 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8457 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8458 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8460 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8461 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8463 // The result is fine to be handled by the generic logic.
8464 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8465 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8466 int AOffset, int BOffset) {
8467 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8468 "Must call this with A having 3 or 1 inputs from the A half.");
8469 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8470 "Must call this with B having 1 or 3 inputs from the B half.");
8471 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8472 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8474 // Compute the index of dword with only one word among the three inputs in
8475 // a half by taking the sum of the half with three inputs and subtracting
8476 // the sum of the actual three inputs. The difference is the remaining
8479 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8480 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8481 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8482 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8483 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8484 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8485 int TripleNonInputIdx =
8486 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8487 TripleDWord = TripleNonInputIdx / 2;
8489 // We use xor with one to compute the adjacent DWord to whichever one the
8491 OneInputDWord = (OneInput / 2) ^ 1;
8493 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8494 // and BToA inputs. If there is also such a problem with the BToB and AToB
8495 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8496 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8497 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8498 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8499 // Compute how many inputs will be flipped by swapping these DWords. We
8501 // to balance this to ensure we don't form a 3-1 shuffle in the other
8503 int NumFlippedAToBInputs =
8504 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8505 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8506 int NumFlippedBToBInputs =
8507 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8508 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8509 if ((NumFlippedAToBInputs == 1 &&
8510 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8511 (NumFlippedBToBInputs == 1 &&
8512 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8513 // We choose whether to fix the A half or B half based on whether that
8514 // half has zero flipped inputs. At zero, we may not be able to fix it
8515 // with that half. We also bias towards fixing the B half because that
8516 // will more commonly be the high half, and we have to bias one way.
8517 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8518 ArrayRef<int> Inputs) {
8519 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8520 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8521 PinnedIdx ^ 1) != Inputs.end();
8522 // Determine whether the free index is in the flipped dword or the
8523 // unflipped dword based on where the pinned index is. We use this bit
8524 // in an xor to conditionally select the adjacent dword.
8525 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8526 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8527 FixFreeIdx) != Inputs.end();
8528 if (IsFixIdxInput == IsFixFreeIdxInput)
8530 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8531 FixFreeIdx) != Inputs.end();
8532 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8533 "We need to be changing the number of flipped inputs!");
8534 int PSHUFHalfMask[] = {0, 1, 2, 3};
8535 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8536 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8538 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8541 if (M != -1 && M == FixIdx)
8543 else if (M != -1 && M == FixFreeIdx)
8546 if (NumFlippedBToBInputs != 0) {
8548 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8549 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8551 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8553 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8554 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8559 int PSHUFDMask[] = {0, 1, 2, 3};
8560 PSHUFDMask[ADWord] = BDWord;
8561 PSHUFDMask[BDWord] = ADWord;
8562 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8563 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8564 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8565 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8567 // Adjust the mask to match the new locations of A and B.
8569 if (M != -1 && M/2 == ADWord)
8570 M = 2 * BDWord + M % 2;
8571 else if (M != -1 && M/2 == BDWord)
8572 M = 2 * ADWord + M % 2;
8574 // Recurse back into this routine to re-compute state now that this isn't
8575 // a 3 and 1 problem.
8576 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8579 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8580 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8581 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8582 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8584 // At this point there are at most two inputs to the low and high halves from
8585 // each half. That means the inputs can always be grouped into dwords and
8586 // those dwords can then be moved to the correct half with a dword shuffle.
8587 // We use at most one low and one high word shuffle to collect these paired
8588 // inputs into dwords, and finally a dword shuffle to place them.
8589 int PSHUFLMask[4] = {-1, -1, -1, -1};
8590 int PSHUFHMask[4] = {-1, -1, -1, -1};
8591 int PSHUFDMask[4] = {-1, -1, -1, -1};
8593 // First fix the masks for all the inputs that are staying in their
8594 // original halves. This will then dictate the targets of the cross-half
8596 auto fixInPlaceInputs =
8597 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8598 MutableArrayRef<int> SourceHalfMask,
8599 MutableArrayRef<int> HalfMask, int HalfOffset) {
8600 if (InPlaceInputs.empty())
8602 if (InPlaceInputs.size() == 1) {
8603 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8604 InPlaceInputs[0] - HalfOffset;
8605 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8608 if (IncomingInputs.empty()) {
8609 // Just fix all of the in place inputs.
8610 for (int Input : InPlaceInputs) {
8611 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8612 PSHUFDMask[Input / 2] = Input / 2;
8617 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8618 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8619 InPlaceInputs[0] - HalfOffset;
8620 // Put the second input next to the first so that they are packed into
8621 // a dword. We find the adjacent index by toggling the low bit.
8622 int AdjIndex = InPlaceInputs[0] ^ 1;
8623 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8624 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8625 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8627 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8628 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8630 // Now gather the cross-half inputs and place them into a free dword of
8631 // their target half.
8632 // FIXME: This operation could almost certainly be simplified dramatically to
8633 // look more like the 3-1 fixing operation.
8634 auto moveInputsToRightHalf = [&PSHUFDMask](
8635 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8636 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8637 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8639 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8640 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8642 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8644 int LowWord = Word & ~1;
8645 int HighWord = Word | 1;
8646 return isWordClobbered(SourceHalfMask, LowWord) ||
8647 isWordClobbered(SourceHalfMask, HighWord);
8650 if (IncomingInputs.empty())
8653 if (ExistingInputs.empty()) {
8654 // Map any dwords with inputs from them into the right half.
8655 for (int Input : IncomingInputs) {
8656 // If the source half mask maps over the inputs, turn those into
8657 // swaps and use the swapped lane.
8658 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8659 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8660 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8661 Input - SourceOffset;
8662 // We have to swap the uses in our half mask in one sweep.
8663 for (int &M : HalfMask)
8664 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8666 else if (M == Input)
8667 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8669 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8670 Input - SourceOffset &&
8671 "Previous placement doesn't match!");
8673 // Note that this correctly re-maps both when we do a swap and when
8674 // we observe the other side of the swap above. We rely on that to
8675 // avoid swapping the members of the input list directly.
8676 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8679 // Map the input's dword into the correct half.
8680 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8681 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8683 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8685 "Previous placement doesn't match!");
8688 // And just directly shift any other-half mask elements to be same-half
8689 // as we will have mirrored the dword containing the element into the
8690 // same position within that half.
8691 for (int &M : HalfMask)
8692 if (M >= SourceOffset && M < SourceOffset + 4) {
8693 M = M - SourceOffset + DestOffset;
8694 assert(M >= 0 && "This should never wrap below zero!");
8699 // Ensure we have the input in a viable dword of its current half. This
8700 // is particularly tricky because the original position may be clobbered
8701 // by inputs being moved and *staying* in that half.
8702 if (IncomingInputs.size() == 1) {
8703 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8704 int InputFixed = std::find(std::begin(SourceHalfMask),
8705 std::end(SourceHalfMask), -1) -
8706 std::begin(SourceHalfMask) + SourceOffset;
8707 SourceHalfMask[InputFixed - SourceOffset] =
8708 IncomingInputs[0] - SourceOffset;
8709 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8711 IncomingInputs[0] = InputFixed;
8713 } else if (IncomingInputs.size() == 2) {
8714 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8715 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8716 // We have two non-adjacent or clobbered inputs we need to extract from
8717 // the source half. To do this, we need to map them into some adjacent
8718 // dword slot in the source mask.
8719 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8720 IncomingInputs[1] - SourceOffset};
8722 // If there is a free slot in the source half mask adjacent to one of
8723 // the inputs, place the other input in it. We use (Index XOR 1) to
8724 // compute an adjacent index.
8725 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8726 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8727 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8728 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8729 InputsFixed[1] = InputsFixed[0] ^ 1;
8730 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8731 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8732 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8733 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8734 InputsFixed[0] = InputsFixed[1] ^ 1;
8735 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8736 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8737 // The two inputs are in the same DWord but it is clobbered and the
8738 // adjacent DWord isn't used at all. Move both inputs to the free
8740 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8741 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8742 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8743 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8745 // The only way we hit this point is if there is no clobbering
8746 // (because there are no off-half inputs to this half) and there is no
8747 // free slot adjacent to one of the inputs. In this case, we have to
8748 // swap an input with a non-input.
8749 for (int i = 0; i < 4; ++i)
8750 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8751 "We can't handle any clobbers here!");
8752 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8753 "Cannot have adjacent inputs here!");
8755 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8756 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8758 // We also have to update the final source mask in this case because
8759 // it may need to undo the above swap.
8760 for (int &M : FinalSourceHalfMask)
8761 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8762 M = InputsFixed[1] + SourceOffset;
8763 else if (M == InputsFixed[1] + SourceOffset)
8764 M = (InputsFixed[0] ^ 1) + SourceOffset;
8766 InputsFixed[1] = InputsFixed[0] ^ 1;
8769 // Point everything at the fixed inputs.
8770 for (int &M : HalfMask)
8771 if (M == IncomingInputs[0])
8772 M = InputsFixed[0] + SourceOffset;
8773 else if (M == IncomingInputs[1])
8774 M = InputsFixed[1] + SourceOffset;
8776 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8777 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8780 llvm_unreachable("Unhandled input size!");
8783 // Now hoist the DWord down to the right half.
8784 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8785 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8786 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8787 for (int &M : HalfMask)
8788 for (int Input : IncomingInputs)
8790 M = FreeDWord * 2 + Input % 2;
8792 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8793 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8794 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8795 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8797 // Now enact all the shuffles we've computed to move the inputs into their
8799 if (!isNoopShuffleMask(PSHUFLMask))
8800 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8801 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8802 if (!isNoopShuffleMask(PSHUFHMask))
8803 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8804 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8805 if (!isNoopShuffleMask(PSHUFDMask))
8806 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8807 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8808 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8809 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8811 // At this point, each half should contain all its inputs, and we can then
8812 // just shuffle them into their final position.
8813 assert(std::count_if(LoMask.begin(), LoMask.end(),
8814 [](int M) { return M >= 4; }) == 0 &&
8815 "Failed to lift all the high half inputs to the low mask!");
8816 assert(std::count_if(HiMask.begin(), HiMask.end(),
8817 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8818 "Failed to lift all the low half inputs to the high mask!");
8820 // Do a half shuffle for the low mask.
8821 if (!isNoopShuffleMask(LoMask))
8822 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8823 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8825 // Do a half shuffle with the high mask after shifting its values down.
8826 for (int &M : HiMask)
8829 if (!isNoopShuffleMask(HiMask))
8830 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8831 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8836 /// \brief Detect whether the mask pattern should be lowered through
8839 /// This essentially tests whether viewing the mask as an interleaving of two
8840 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8841 /// lowering it through interleaving is a significantly better strategy.
8842 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8843 int NumEvenInputs[2] = {0, 0};
8844 int NumOddInputs[2] = {0, 0};
8845 int NumLoInputs[2] = {0, 0};
8846 int NumHiInputs[2] = {0, 0};
8847 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8851 int InputIdx = Mask[i] >= Size;
8854 ++NumLoInputs[InputIdx];
8856 ++NumHiInputs[InputIdx];
8859 ++NumEvenInputs[InputIdx];
8861 ++NumOddInputs[InputIdx];
8864 // The minimum number of cross-input results for both the interleaved and
8865 // split cases. If interleaving results in fewer cross-input results, return
8867 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8868 NumEvenInputs[0] + NumOddInputs[1]);
8869 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8870 NumLoInputs[0] + NumHiInputs[1]);
8871 return InterleavedCrosses < SplitCrosses;
8874 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8876 /// This strategy only works when the inputs from each vector fit into a single
8877 /// half of that vector, and generally there are not so many inputs as to leave
8878 /// the in-place shuffles required highly constrained (and thus expensive). It
8879 /// shifts all the inputs into a single side of both input vectors and then
8880 /// uses an unpack to interleave these inputs in a single vector. At that
8881 /// point, we will fall back on the generic single input shuffle lowering.
8882 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8884 MutableArrayRef<int> Mask,
8885 const X86Subtarget *Subtarget,
8886 SelectionDAG &DAG) {
8887 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8888 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8889 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8890 for (int i = 0; i < 8; ++i)
8891 if (Mask[i] >= 0 && Mask[i] < 4)
8892 LoV1Inputs.push_back(i);
8893 else if (Mask[i] >= 4 && Mask[i] < 8)
8894 HiV1Inputs.push_back(i);
8895 else if (Mask[i] >= 8 && Mask[i] < 12)
8896 LoV2Inputs.push_back(i);
8897 else if (Mask[i] >= 12)
8898 HiV2Inputs.push_back(i);
8900 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8901 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8904 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8905 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8906 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8908 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8909 HiV1Inputs.size() + HiV2Inputs.size();
8911 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8912 ArrayRef<int> HiInputs, bool MoveToLo,
8914 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8915 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8916 if (BadInputs.empty())
8919 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8920 int MoveOffset = MoveToLo ? 0 : 4;
8922 if (GoodInputs.empty()) {
8923 for (int BadInput : BadInputs) {
8924 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8925 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8928 if (GoodInputs.size() == 2) {
8929 // If the low inputs are spread across two dwords, pack them into
8931 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8932 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8933 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8934 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8936 // Otherwise pin the good inputs.
8937 for (int GoodInput : GoodInputs)
8938 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8941 if (BadInputs.size() == 2) {
8942 // If we have two bad inputs then there may be either one or two good
8943 // inputs fixed in place. Find a fixed input, and then find the *other*
8944 // two adjacent indices by using modular arithmetic.
8946 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8947 [](int M) { return M >= 0; }) -
8948 std::begin(MoveMask);
8950 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8951 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8952 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8953 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8954 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8955 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8956 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8958 assert(BadInputs.size() == 1 && "All sizes handled");
8959 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8960 std::end(MoveMask), -1) -
8961 std::begin(MoveMask);
8962 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8963 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8967 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8970 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8972 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8975 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8976 // cross-half traffic in the final shuffle.
8978 // Munge the mask to be a single-input mask after the unpack merges the
8982 M = 2 * (M % 4) + (M / 8);
8984 return DAG.getVectorShuffle(
8985 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8986 DL, MVT::v8i16, V1, V2),
8987 DAG.getUNDEF(MVT::v8i16), Mask);
8990 /// \brief Generic lowering of 8-lane i16 shuffles.
8992 /// This handles both single-input shuffles and combined shuffle/blends with
8993 /// two inputs. The single input shuffles are immediately delegated to
8994 /// a dedicated lowering routine.
8996 /// The blends are lowered in one of three fundamental ways. If there are few
8997 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8998 /// of the input is significantly cheaper when lowered as an interleaving of
8999 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9000 /// halves of the inputs separately (making them have relatively few inputs)
9001 /// and then concatenate them.
9002 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9003 const X86Subtarget *Subtarget,
9004 SelectionDAG &DAG) {
9006 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9007 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9008 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9009 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9010 ArrayRef<int> OrigMask = SVOp->getMask();
9011 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9012 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9013 MutableArrayRef<int> Mask(MaskStorage);
9015 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9017 // Whenever we can lower this as a zext, that instruction is strictly faster
9018 // than any alternative.
9019 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9020 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9023 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9024 auto isV2 = [](int M) { return M >= 8; };
9026 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9027 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9029 if (NumV2Inputs == 0)
9030 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9032 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9033 "to be V1-input shuffles.");
9035 // There are special ways we can lower some single-element blends.
9036 if (NumV2Inputs == 1)
9037 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9038 Mask, Subtarget, DAG))
9041 // Use dedicated unpack instructions for masks that match their pattern.
9042 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9043 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9044 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9045 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9047 if (Subtarget->hasSSE41())
9048 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9052 // Try to use rotation instructions if available.
9053 if (Subtarget->hasSSSE3())
9054 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9055 DL, MVT::v8i16, V1, V2, Mask, DAG))
9058 if (NumV1Inputs + NumV2Inputs <= 4)
9059 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9061 // Check whether an interleaving lowering is likely to be more efficient.
9062 // This isn't perfect but it is a strong heuristic that tends to work well on
9063 // the kinds of shuffles that show up in practice.
9065 // FIXME: Handle 1x, 2x, and 4x interleaving.
9066 if (shouldLowerAsInterleaving(Mask)) {
9067 // FIXME: Figure out whether we should pack these into the low or high
9070 int EMask[8], OMask[8];
9071 for (int i = 0; i < 4; ++i) {
9072 EMask[i] = Mask[2*i];
9073 OMask[i] = Mask[2*i + 1];
9078 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9079 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9081 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9084 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9085 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9087 for (int i = 0; i < 4; ++i) {
9088 LoBlendMask[i] = Mask[i];
9089 HiBlendMask[i] = Mask[i + 4];
9092 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9093 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9094 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9095 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9097 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9098 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9101 /// \brief Check whether a compaction lowering can be done by dropping even
9102 /// elements and compute how many times even elements must be dropped.
9104 /// This handles shuffles which take every Nth element where N is a power of
9105 /// two. Example shuffle masks:
9107 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9108 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9109 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9110 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9111 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9112 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9114 /// Any of these lanes can of course be undef.
9116 /// This routine only supports N <= 3.
9117 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9120 /// \returns N above, or the number of times even elements must be dropped if
9121 /// there is such a number. Otherwise returns zero.
9122 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9123 // Figure out whether we're looping over two inputs or just one.
9124 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9126 // The modulus for the shuffle vector entries is based on whether this is
9127 // a single input or not.
9128 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9129 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9130 "We should only be called with masks with a power-of-2 size!");
9132 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9134 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9135 // and 2^3 simultaneously. This is because we may have ambiguity with
9136 // partially undef inputs.
9137 bool ViableForN[3] = {true, true, true};
9139 for (int i = 0, e = Mask.size(); i < e; ++i) {
9140 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9145 bool IsAnyViable = false;
9146 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9147 if (ViableForN[j]) {
9150 // The shuffle mask must be equal to (i * 2^N) % M.
9151 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9154 ViableForN[j] = false;
9156 // Early exit if we exhaust the possible powers of two.
9161 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9165 // Return 0 as there is no viable power of two.
9169 /// \brief Generic lowering of v16i8 shuffles.
9171 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9172 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9173 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9174 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9176 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9177 const X86Subtarget *Subtarget,
9178 SelectionDAG &DAG) {
9180 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9181 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9182 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9184 ArrayRef<int> OrigMask = SVOp->getMask();
9185 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9187 // Try to use rotation instructions if available.
9188 if (Subtarget->hasSSSE3())
9189 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9190 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9193 // Try to use a zext lowering.
9194 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9195 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9198 int MaskStorage[16] = {
9199 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9200 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9201 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9202 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9203 MutableArrayRef<int> Mask(MaskStorage);
9204 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9205 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9208 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9210 // For single-input shuffles, there are some nicer lowering tricks we can use.
9211 if (NumV2Elements == 0) {
9212 // Check for being able to broadcast a single element.
9213 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9214 Mask, Subtarget, DAG))
9217 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9218 // Notably, this handles splat and partial-splat shuffles more efficiently.
9219 // However, it only makes sense if the pre-duplication shuffle simplifies
9220 // things significantly. Currently, this means we need to be able to
9221 // express the pre-duplication shuffle as an i16 shuffle.
9223 // FIXME: We should check for other patterns which can be widened into an
9224 // i16 shuffle as well.
9225 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9226 for (int i = 0; i < 16; i += 2)
9227 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9232 auto tryToWidenViaDuplication = [&]() -> SDValue {
9233 if (!canWidenViaDuplication(Mask))
9235 SmallVector<int, 4> LoInputs;
9236 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9237 [](int M) { return M >= 0 && M < 8; });
9238 std::sort(LoInputs.begin(), LoInputs.end());
9239 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9241 SmallVector<int, 4> HiInputs;
9242 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9243 [](int M) { return M >= 8; });
9244 std::sort(HiInputs.begin(), HiInputs.end());
9245 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9248 bool TargetLo = LoInputs.size() >= HiInputs.size();
9249 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9250 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9252 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9253 SmallDenseMap<int, int, 8> LaneMap;
9254 for (int I : InPlaceInputs) {
9255 PreDupI16Shuffle[I/2] = I/2;
9258 int j = TargetLo ? 0 : 4, je = j + 4;
9259 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9260 // Check if j is already a shuffle of this input. This happens when
9261 // there are two adjacent bytes after we move the low one.
9262 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9263 // If we haven't yet mapped the input, search for a slot into which
9265 while (j < je && PreDupI16Shuffle[j] != -1)
9269 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9272 // Map this input with the i16 shuffle.
9273 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9276 // Update the lane map based on the mapping we ended up with.
9277 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9280 ISD::BITCAST, DL, MVT::v16i8,
9281 DAG.getVectorShuffle(MVT::v8i16, DL,
9282 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9283 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9285 // Unpack the bytes to form the i16s that will be shuffled into place.
9286 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9287 MVT::v16i8, V1, V1);
9289 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9290 for (int i = 0; i < 16; ++i)
9291 if (Mask[i] != -1) {
9292 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9293 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9294 if (PostDupI16Shuffle[i / 2] == -1)
9295 PostDupI16Shuffle[i / 2] = MappedMask;
9297 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9298 "Conflicting entrties in the original shuffle!");
9301 ISD::BITCAST, DL, MVT::v16i8,
9302 DAG.getVectorShuffle(MVT::v8i16, DL,
9303 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9304 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9306 if (SDValue V = tryToWidenViaDuplication())
9310 // Check whether an interleaving lowering is likely to be more efficient.
9311 // This isn't perfect but it is a strong heuristic that tends to work well on
9312 // the kinds of shuffles that show up in practice.
9314 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9315 if (shouldLowerAsInterleaving(Mask)) {
9316 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9317 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9319 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9320 return (M >= 8 && M < 16) || M >= 24;
9322 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9323 -1, -1, -1, -1, -1, -1, -1, -1};
9324 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9325 -1, -1, -1, -1, -1, -1, -1, -1};
9326 bool UnpackLo = NumLoHalf >= NumHiHalf;
9327 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9328 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9329 for (int i = 0; i < 8; ++i) {
9330 TargetEMask[i] = Mask[2 * i];
9331 TargetOMask[i] = Mask[2 * i + 1];
9334 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9335 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9337 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9338 MVT::v16i8, Evens, Odds);
9341 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9342 // with PSHUFB. It is important to do this before we attempt to generate any
9343 // blends but after all of the single-input lowerings. If the single input
9344 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9345 // want to preserve that and we can DAG combine any longer sequences into
9346 // a PSHUFB in the end. But once we start blending from multiple inputs,
9347 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9348 // and there are *very* few patterns that would actually be faster than the
9349 // PSHUFB approach because of its ability to zero lanes.
9351 // FIXME: The only exceptions to the above are blends which are exact
9352 // interleavings with direct instructions supporting them. We currently don't
9353 // handle those well here.
9354 if (Subtarget->hasSSSE3()) {
9357 for (int i = 0; i < 16; ++i)
9358 if (Mask[i] == -1) {
9359 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9361 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9363 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9365 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9366 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9367 if (isSingleInputShuffleMask(Mask))
9368 return V1; // Single inputs are easy.
9370 // Otherwise, blend the two.
9371 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9372 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9373 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9376 // There are special ways we can lower some single-element blends.
9377 if (NumV2Elements == 1)
9378 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9379 Mask, Subtarget, DAG))
9382 // Check whether a compaction lowering can be done. This handles shuffles
9383 // which take every Nth element for some even N. See the helper function for
9386 // We special case these as they can be particularly efficiently handled with
9387 // the PACKUSB instruction on x86 and they show up in common patterns of
9388 // rearranging bytes to truncate wide elements.
9389 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9390 // NumEvenDrops is the power of two stride of the elements. Another way of
9391 // thinking about it is that we need to drop the even elements this many
9392 // times to get the original input.
9393 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9395 // First we need to zero all the dropped bytes.
9396 assert(NumEvenDrops <= 3 &&
9397 "No support for dropping even elements more than 3 times.");
9398 // We use the mask type to pick which bytes are preserved based on how many
9399 // elements are dropped.
9400 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9401 SDValue ByteClearMask =
9402 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9403 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9404 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9406 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9408 // Now pack things back together.
9409 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9410 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9411 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9412 for (int i = 1; i < NumEvenDrops; ++i) {
9413 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9414 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9420 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9421 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9422 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9423 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9425 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9426 MutableArrayRef<int> V1HalfBlendMask,
9427 MutableArrayRef<int> V2HalfBlendMask) {
9428 for (int i = 0; i < 8; ++i)
9429 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9430 V1HalfBlendMask[i] = HalfMask[i];
9432 } else if (HalfMask[i] >= 16) {
9433 V2HalfBlendMask[i] = HalfMask[i] - 16;
9434 HalfMask[i] = i + 8;
9437 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9438 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9440 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9442 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9443 MutableArrayRef<int> HiBlendMask) {
9445 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9446 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9448 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9449 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9450 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9451 [](int M) { return M >= 0 && M % 2 == 1; })) {
9452 // Use a mask to drop the high bytes.
9453 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9454 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9455 DAG.getConstant(0x00FF, MVT::v8i16));
9457 // This will be a single vector shuffle instead of a blend so nuke V2.
9458 V2 = DAG.getUNDEF(MVT::v8i16);
9460 // Squash the masks to point directly into V1.
9461 for (int &M : LoBlendMask)
9464 for (int &M : HiBlendMask)
9468 // Otherwise just unpack the low half of V into V1 and the high half into
9469 // V2 so that we can blend them as i16s.
9470 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9471 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9472 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9473 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9476 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9477 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9478 return std::make_pair(BlendedLo, BlendedHi);
9480 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9481 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9482 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9484 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9485 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9487 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9490 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9492 /// This routine breaks down the specific type of 128-bit shuffle and
9493 /// dispatches to the lowering routines accordingly.
9494 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9495 MVT VT, const X86Subtarget *Subtarget,
9496 SelectionDAG &DAG) {
9497 switch (VT.SimpleTy) {
9499 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9501 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9503 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9505 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9507 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9509 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9512 llvm_unreachable("Unimplemented!");
9516 /// \brief Helper function to test whether a shuffle mask could be
9517 /// simplified by widening the elements being shuffled.
9519 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9520 /// leaves it in an unspecified state.
9522 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9523 /// shuffle masks. The latter have the special property of a '-2' representing
9524 /// a zero-ed lane of a vector.
9525 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9526 SmallVectorImpl<int> &WidenedMask) {
9527 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9528 // If both elements are undef, its trivial.
9529 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9530 WidenedMask.push_back(SM_SentinelUndef);
9534 // Check for an undef mask and a mask value properly aligned to fit with
9535 // a pair of values. If we find such a case, use the non-undef mask's value.
9536 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9537 WidenedMask.push_back(Mask[i + 1] / 2);
9540 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9541 WidenedMask.push_back(Mask[i] / 2);
9545 // When zeroing, we need to spread the zeroing across both lanes to widen.
9546 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9547 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9548 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9549 WidenedMask.push_back(SM_SentinelZero);
9555 // Finally check if the two mask values are adjacent and aligned with
9557 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9558 WidenedMask.push_back(Mask[i] / 2);
9562 // Otherwise we can't safely widen the elements used in this shuffle.
9565 assert(WidenedMask.size() == Mask.size() / 2 &&
9566 "Incorrect size of mask after widening the elements!");
9571 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9573 /// This routine just extracts two subvectors, shuffles them independently, and
9574 /// then concatenates them back together. This should work effectively with all
9575 /// AVX vector shuffle types.
9576 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9577 SDValue V2, ArrayRef<int> Mask,
9578 SelectionDAG &DAG) {
9579 assert(VT.getSizeInBits() >= 256 &&
9580 "Only for 256-bit or wider vector shuffles!");
9581 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9582 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9584 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9585 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9587 int NumElements = VT.getVectorNumElements();
9588 int SplitNumElements = NumElements / 2;
9589 MVT ScalarVT = VT.getScalarType();
9590 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9592 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9593 DAG.getIntPtrConstant(0));
9594 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9595 DAG.getIntPtrConstant(SplitNumElements));
9596 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9597 DAG.getIntPtrConstant(0));
9598 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9599 DAG.getIntPtrConstant(SplitNumElements));
9601 // Now create two 4-way blends of these half-width vectors.
9602 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9603 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9604 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9605 for (int i = 0; i < SplitNumElements; ++i) {
9606 int M = HalfMask[i];
9607 if (M >= NumElements) {
9608 if (M >= NumElements + SplitNumElements)
9612 V2BlendMask.push_back(M - NumElements);
9613 V1BlendMask.push_back(-1);
9614 BlendMask.push_back(SplitNumElements + i);
9615 } else if (M >= 0) {
9616 if (M >= SplitNumElements)
9620 V2BlendMask.push_back(-1);
9621 V1BlendMask.push_back(M);
9622 BlendMask.push_back(i);
9624 V2BlendMask.push_back(-1);
9625 V1BlendMask.push_back(-1);
9626 BlendMask.push_back(-1);
9630 // Because the lowering happens after all combining takes place, we need to
9631 // manually combine these blend masks as much as possible so that we create
9632 // a minimal number of high-level vector shuffle nodes.
9634 // First try just blending the halves of V1 or V2.
9635 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9636 return DAG.getUNDEF(SplitVT);
9637 if (!UseLoV2 && !UseHiV2)
9638 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9639 if (!UseLoV1 && !UseHiV1)
9640 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9642 SDValue V1Blend, V2Blend;
9643 if (UseLoV1 && UseHiV1) {
9645 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9647 // We only use half of V1 so map the usage down into the final blend mask.
9648 V1Blend = UseLoV1 ? LoV1 : HiV1;
9649 for (int i = 0; i < SplitNumElements; ++i)
9650 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9651 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9653 if (UseLoV2 && UseHiV2) {
9655 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9657 // We only use half of V2 so map the usage down into the final blend mask.
9658 V2Blend = UseLoV2 ? LoV2 : HiV2;
9659 for (int i = 0; i < SplitNumElements; ++i)
9660 if (BlendMask[i] >= SplitNumElements)
9661 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9663 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9665 SDValue Lo = HalfBlend(LoMask);
9666 SDValue Hi = HalfBlend(HiMask);
9667 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9670 /// \brief Either split a vector in halves or decompose the shuffles and the
9673 /// This is provided as a good fallback for many lowerings of non-single-input
9674 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9675 /// between splitting the shuffle into 128-bit components and stitching those
9676 /// back together vs. extracting the single-input shuffles and blending those
9678 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9679 SDValue V2, ArrayRef<int> Mask,
9680 SelectionDAG &DAG) {
9681 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9682 "lower single-input shuffles as it "
9683 "could then recurse on itself.");
9684 int Size = Mask.size();
9686 // If this can be modeled as a broadcast of two elements followed by a blend,
9687 // prefer that lowering. This is especially important because broadcasts can
9688 // often fold with memory operands.
9689 auto DoBothBroadcast = [&] {
9690 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9693 if (V2BroadcastIdx == -1)
9694 V2BroadcastIdx = M - Size;
9695 else if (M - Size != V2BroadcastIdx)
9697 } else if (M >= 0) {
9698 if (V1BroadcastIdx == -1)
9700 else if (M != V1BroadcastIdx)
9705 if (DoBothBroadcast())
9706 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9709 // If the inputs all stem from a single 128-bit lane of each input, then we
9710 // split them rather than blending because the split will decompose to
9711 // unusually few instructions.
9712 int LaneCount = VT.getSizeInBits() / 128;
9713 int LaneSize = Size / LaneCount;
9714 SmallBitVector LaneInputs[2];
9715 LaneInputs[0].resize(LaneCount, false);
9716 LaneInputs[1].resize(LaneCount, false);
9717 for (int i = 0; i < Size; ++i)
9719 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9720 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9721 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9723 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9724 // that the decomposed single-input shuffles don't end up here.
9725 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9728 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9729 /// a permutation and blend of those lanes.
9731 /// This essentially blends the out-of-lane inputs to each lane into the lane
9732 /// from a permuted copy of the vector. This lowering strategy results in four
9733 /// instructions in the worst case for a single-input cross lane shuffle which
9734 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9735 /// of. Special cases for each particular shuffle pattern should be handled
9736 /// prior to trying this lowering.
9737 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9738 SDValue V1, SDValue V2,
9740 SelectionDAG &DAG) {
9741 // FIXME: This should probably be generalized for 512-bit vectors as well.
9742 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9743 int LaneSize = Mask.size() / 2;
9745 // If there are only inputs from one 128-bit lane, splitting will in fact be
9746 // less expensive. The flags track wether the given lane contains an element
9747 // that crosses to another lane.
9748 bool LaneCrossing[2] = {false, false};
9749 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9750 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9751 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9752 if (!LaneCrossing[0] || !LaneCrossing[1])
9753 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9755 if (isSingleInputShuffleMask(Mask)) {
9756 SmallVector<int, 32> FlippedBlendMask;
9757 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9758 FlippedBlendMask.push_back(
9759 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9761 : Mask[i] % LaneSize +
9762 (i / LaneSize) * LaneSize + Size));
9764 // Flip the vector, and blend the results which should now be in-lane. The
9765 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9766 // 5 for the high source. The value 3 selects the high half of source 2 and
9767 // the value 2 selects the low half of source 2. We only use source 2 to
9768 // allow folding it into a memory operand.
9769 unsigned PERMMask = 3 | 2 << 4;
9770 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9771 V1, DAG.getConstant(PERMMask, MVT::i8));
9772 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9775 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9776 // will be handled by the above logic and a blend of the results, much like
9777 // other patterns in AVX.
9778 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9781 /// \brief Handle lowering 2-lane 128-bit shuffles.
9782 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9783 SDValue V2, ArrayRef<int> Mask,
9784 const X86Subtarget *Subtarget,
9785 SelectionDAG &DAG) {
9786 // Blends are faster and handle all the non-lane-crossing cases.
9787 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9791 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9792 VT.getVectorNumElements() / 2);
9793 // Check for patterns which can be matched with a single insert of a 128-bit
9795 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9796 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9797 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9798 DAG.getIntPtrConstant(0));
9799 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9800 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9801 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9803 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9804 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9805 DAG.getIntPtrConstant(0));
9806 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9807 DAG.getIntPtrConstant(2));
9808 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9811 // Otherwise form a 128-bit permutation.
9812 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9813 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9814 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9815 DAG.getConstant(PermMask, MVT::i8));
9818 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9820 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9821 /// isn't available.
9822 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9823 const X86Subtarget *Subtarget,
9824 SelectionDAG &DAG) {
9826 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9827 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9828 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9829 ArrayRef<int> Mask = SVOp->getMask();
9830 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9832 SmallVector<int, 4> WidenedMask;
9833 if (canWidenShuffleElements(Mask, WidenedMask))
9834 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9837 if (isSingleInputShuffleMask(Mask)) {
9838 // Check for being able to broadcast a single element.
9839 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
9840 Mask, Subtarget, DAG))
9843 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9844 // Non-half-crossing single input shuffles can be lowerid with an
9845 // interleaved permutation.
9846 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9847 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9848 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9849 DAG.getConstant(VPERMILPMask, MVT::i8));
9852 // With AVX2 we have direct support for this permutation.
9853 if (Subtarget->hasAVX2())
9854 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9855 getV4X86ShuffleImm8ForMask(Mask, DAG));
9857 // Otherwise, fall back.
9858 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9862 // X86 has dedicated unpack instructions that can handle specific blend
9863 // operations: UNPCKH and UNPCKL.
9864 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9865 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9866 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9867 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9869 // If we have a single input to the zero element, insert that into V1 if we
9870 // can do so cheaply.
9872 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9873 if (NumV2Elements == 1 && Mask[0] >= 4)
9874 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9875 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9878 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9882 // Check if the blend happens to exactly fit that of SHUFPD.
9883 if ((Mask[0] == -1 || Mask[0] < 2) &&
9884 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9885 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9886 (Mask[3] == -1 || Mask[3] >= 6)) {
9887 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9888 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9889 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9890 DAG.getConstant(SHUFPDMask, MVT::i8));
9892 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9893 (Mask[1] == -1 || Mask[1] < 2) &&
9894 (Mask[2] == -1 || Mask[2] >= 6) &&
9895 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9896 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9897 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9898 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9899 DAG.getConstant(SHUFPDMask, MVT::i8));
9902 // If we have AVX2 then we always want to lower with a blend because an v4 we
9903 // can fully permute the elements.
9904 if (Subtarget->hasAVX2())
9905 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9908 // Otherwise fall back on generic lowering.
9909 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9912 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9914 /// This routine is only called when we have AVX2 and thus a reasonable
9915 /// instruction set for v4i64 shuffling..
9916 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9917 const X86Subtarget *Subtarget,
9918 SelectionDAG &DAG) {
9920 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9921 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9922 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9923 ArrayRef<int> Mask = SVOp->getMask();
9924 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9925 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9927 SmallVector<int, 4> WidenedMask;
9928 if (canWidenShuffleElements(Mask, WidenedMask))
9929 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9932 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9936 // Check for being able to broadcast a single element.
9937 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
9938 Mask, Subtarget, DAG))
9941 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9942 // use lower latency instructions that will operate on both 128-bit lanes.
9943 SmallVector<int, 2> RepeatedMask;
9944 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9945 if (isSingleInputShuffleMask(Mask)) {
9946 int PSHUFDMask[] = {-1, -1, -1, -1};
9947 for (int i = 0; i < 2; ++i)
9948 if (RepeatedMask[i] >= 0) {
9949 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9950 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9953 ISD::BITCAST, DL, MVT::v4i64,
9954 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9955 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9956 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9959 // Use dedicated unpack instructions for masks that match their pattern.
9960 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9961 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9962 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9963 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9966 // AVX2 provides a direct instruction for permuting a single input across
9968 if (isSingleInputShuffleMask(Mask))
9969 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9970 getV4X86ShuffleImm8ForMask(Mask, DAG));
9972 // Otherwise fall back on generic blend lowering.
9973 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9977 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9979 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9980 /// isn't available.
9981 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9982 const X86Subtarget *Subtarget,
9983 SelectionDAG &DAG) {
9985 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9986 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9987 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9988 ArrayRef<int> Mask = SVOp->getMask();
9989 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9991 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9995 // Check for being able to broadcast a single element.
9996 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
9997 Mask, Subtarget, DAG))
10000 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10001 // options to efficiently lower the shuffle.
10002 SmallVector<int, 4> RepeatedMask;
10003 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10004 assert(RepeatedMask.size() == 4 &&
10005 "Repeated masks must be half the mask width!");
10006 if (isSingleInputShuffleMask(Mask))
10007 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10008 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10010 // Use dedicated unpack instructions for masks that match their pattern.
10011 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10012 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10013 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10014 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10016 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10017 // have already handled any direct blends. We also need to squash the
10018 // repeated mask into a simulated v4f32 mask.
10019 for (int i = 0; i < 4; ++i)
10020 if (RepeatedMask[i] >= 8)
10021 RepeatedMask[i] -= 4;
10022 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10025 // If we have a single input shuffle with different shuffle patterns in the
10026 // two 128-bit lanes use the variable mask to VPERMILPS.
10027 if (isSingleInputShuffleMask(Mask)) {
10028 SDValue VPermMask[8];
10029 for (int i = 0; i < 8; ++i)
10030 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10031 : DAG.getConstant(Mask[i], MVT::i32);
10032 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10033 return DAG.getNode(
10034 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10035 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10037 if (Subtarget->hasAVX2())
10038 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10039 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10040 DAG.getNode(ISD::BUILD_VECTOR, DL,
10041 MVT::v8i32, VPermMask)),
10044 // Otherwise, fall back.
10045 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10049 // If we have AVX2 then we always want to lower with a blend because at v8 we
10050 // can fully permute the elements.
10051 if (Subtarget->hasAVX2())
10052 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10055 // Otherwise fall back on generic lowering.
10056 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10059 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10061 /// This routine is only called when we have AVX2 and thus a reasonable
10062 /// instruction set for v8i32 shuffling..
10063 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10064 const X86Subtarget *Subtarget,
10065 SelectionDAG &DAG) {
10067 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10068 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10069 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10070 ArrayRef<int> Mask = SVOp->getMask();
10071 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10072 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10074 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10078 // Check for being able to broadcast a single element.
10079 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10080 Mask, Subtarget, DAG))
10083 // If the shuffle mask is repeated in each 128-bit lane we can use more
10084 // efficient instructions that mirror the shuffles across the two 128-bit
10086 SmallVector<int, 4> RepeatedMask;
10087 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10088 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10089 if (isSingleInputShuffleMask(Mask))
10090 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10091 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10093 // Use dedicated unpack instructions for masks that match their pattern.
10094 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10095 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10096 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10097 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10100 // If the shuffle patterns aren't repeated but it is a single input, directly
10101 // generate a cross-lane VPERMD instruction.
10102 if (isSingleInputShuffleMask(Mask)) {
10103 SDValue VPermMask[8];
10104 for (int i = 0; i < 8; ++i)
10105 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10106 : DAG.getConstant(Mask[i], MVT::i32);
10107 return DAG.getNode(
10108 X86ISD::VPERMV, DL, MVT::v8i32,
10109 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10112 // Otherwise fall back on generic blend lowering.
10113 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10117 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10119 /// This routine is only called when we have AVX2 and thus a reasonable
10120 /// instruction set for v16i16 shuffling..
10121 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10122 const X86Subtarget *Subtarget,
10123 SelectionDAG &DAG) {
10125 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10126 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10127 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10128 ArrayRef<int> Mask = SVOp->getMask();
10129 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10130 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10132 // Check for being able to broadcast a single element.
10133 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10134 Mask, Subtarget, DAG))
10137 // There are no generalized cross-lane shuffle operations available on i16
10139 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10140 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10143 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10147 // Use dedicated unpack instructions for masks that match their pattern.
10148 if (isShuffleEquivalent(Mask,
10149 // First 128-bit lane:
10150 0, 16, 1, 17, 2, 18, 3, 19,
10151 // Second 128-bit lane:
10152 8, 24, 9, 25, 10, 26, 11, 27))
10153 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10154 if (isShuffleEquivalent(Mask,
10155 // First 128-bit lane:
10156 4, 20, 5, 21, 6, 22, 7, 23,
10157 // Second 128-bit lane:
10158 12, 28, 13, 29, 14, 30, 15, 31))
10159 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10161 if (isSingleInputShuffleMask(Mask)) {
10162 SDValue PSHUFBMask[32];
10163 for (int i = 0; i < 16; ++i) {
10164 if (Mask[i] == -1) {
10165 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10169 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10170 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10171 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10172 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10174 return DAG.getNode(
10175 ISD::BITCAST, DL, MVT::v16i16,
10177 X86ISD::PSHUFB, DL, MVT::v32i8,
10178 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10179 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10182 // Otherwise fall back on generic lowering.
10183 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10186 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10188 /// This routine is only called when we have AVX2 and thus a reasonable
10189 /// instruction set for v32i8 shuffling..
10190 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10191 const X86Subtarget *Subtarget,
10192 SelectionDAG &DAG) {
10194 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10195 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10196 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10197 ArrayRef<int> Mask = SVOp->getMask();
10198 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10199 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10201 // Check for being able to broadcast a single element.
10202 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10203 Mask, Subtarget, DAG))
10206 // There are no generalized cross-lane shuffle operations available on i8
10208 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10209 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10212 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10216 // Use dedicated unpack instructions for masks that match their pattern.
10217 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10219 if (isShuffleEquivalent(
10221 // First 128-bit lane:
10222 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10223 // Second 128-bit lane:
10224 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10225 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10226 if (isShuffleEquivalent(
10228 // First 128-bit lane:
10229 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10230 // Second 128-bit lane:
10231 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10232 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10234 if (isSingleInputShuffleMask(Mask)) {
10235 SDValue PSHUFBMask[32];
10236 for (int i = 0; i < 32; ++i)
10239 ? DAG.getUNDEF(MVT::i8)
10240 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10242 return DAG.getNode(
10243 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10244 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10247 // Otherwise fall back on generic lowering.
10248 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10251 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10253 /// This routine either breaks down the specific type of a 256-bit x86 vector
10254 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10255 /// together based on the available instructions.
10256 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10257 MVT VT, const X86Subtarget *Subtarget,
10258 SelectionDAG &DAG) {
10260 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10261 ArrayRef<int> Mask = SVOp->getMask();
10263 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10264 // check for those subtargets here and avoid much of the subtarget querying in
10265 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10266 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10267 // floating point types there eventually, just immediately cast everything to
10268 // a float and operate entirely in that domain.
10269 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10270 int ElementBits = VT.getScalarSizeInBits();
10271 if (ElementBits < 32)
10272 // No floating point type available, decompose into 128-bit vectors.
10273 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10275 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10276 VT.getVectorNumElements());
10277 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10278 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10279 return DAG.getNode(ISD::BITCAST, DL, VT,
10280 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10283 switch (VT.SimpleTy) {
10285 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10287 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10289 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10291 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10293 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10295 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10298 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10302 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10303 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10304 const X86Subtarget *Subtarget,
10305 SelectionDAG &DAG) {
10307 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10308 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10309 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10310 ArrayRef<int> Mask = SVOp->getMask();
10311 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10313 // FIXME: Implement direct support for this type!
10314 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10317 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10318 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10319 const X86Subtarget *Subtarget,
10320 SelectionDAG &DAG) {
10322 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10323 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10324 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10325 ArrayRef<int> Mask = SVOp->getMask();
10326 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10328 // FIXME: Implement direct support for this type!
10329 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10332 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10333 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10334 const X86Subtarget *Subtarget,
10335 SelectionDAG &DAG) {
10337 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10338 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10339 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10340 ArrayRef<int> Mask = SVOp->getMask();
10341 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10343 // FIXME: Implement direct support for this type!
10344 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10347 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10348 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10349 const X86Subtarget *Subtarget,
10350 SelectionDAG &DAG) {
10352 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10353 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10354 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10355 ArrayRef<int> Mask = SVOp->getMask();
10356 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10358 // FIXME: Implement direct support for this type!
10359 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10362 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10363 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10364 const X86Subtarget *Subtarget,
10365 SelectionDAG &DAG) {
10367 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10368 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10369 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10370 ArrayRef<int> Mask = SVOp->getMask();
10371 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10372 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10374 // FIXME: Implement direct support for this type!
10375 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10378 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10379 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10380 const X86Subtarget *Subtarget,
10381 SelectionDAG &DAG) {
10383 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10384 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10385 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10386 ArrayRef<int> Mask = SVOp->getMask();
10387 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10388 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10390 // FIXME: Implement direct support for this type!
10391 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10394 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10396 /// This routine either breaks down the specific type of a 512-bit x86 vector
10397 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10398 /// together based on the available instructions.
10399 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10400 MVT VT, const X86Subtarget *Subtarget,
10401 SelectionDAG &DAG) {
10403 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10404 ArrayRef<int> Mask = SVOp->getMask();
10405 assert(Subtarget->hasAVX512() &&
10406 "Cannot lower 512-bit vectors w/ basic ISA!");
10408 // Check for being able to broadcast a single element.
10409 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10410 Mask, Subtarget, DAG))
10413 // Dispatch to each element type for lowering. If we don't have supprot for
10414 // specific element type shuffles at 512 bits, immediately split them and
10415 // lower them. Each lowering routine of a given type is allowed to assume that
10416 // the requisite ISA extensions for that element type are available.
10417 switch (VT.SimpleTy) {
10419 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10421 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10423 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10425 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10427 if (Subtarget->hasBWI())
10428 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10431 if (Subtarget->hasBWI())
10432 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10436 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10439 // Otherwise fall back on splitting.
10440 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10443 /// \brief Top-level lowering for x86 vector shuffles.
10445 /// This handles decomposition, canonicalization, and lowering of all x86
10446 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10447 /// above in helper routines. The canonicalization attempts to widen shuffles
10448 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10449 /// s.t. only one of the two inputs needs to be tested, etc.
10450 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10451 SelectionDAG &DAG) {
10452 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10453 ArrayRef<int> Mask = SVOp->getMask();
10454 SDValue V1 = Op.getOperand(0);
10455 SDValue V2 = Op.getOperand(1);
10456 MVT VT = Op.getSimpleValueType();
10457 int NumElements = VT.getVectorNumElements();
10460 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10462 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10463 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10464 if (V1IsUndef && V2IsUndef)
10465 return DAG.getUNDEF(VT);
10467 // When we create a shuffle node we put the UNDEF node to second operand,
10468 // but in some cases the first operand may be transformed to UNDEF.
10469 // In this case we should just commute the node.
10471 return DAG.getCommutedVectorShuffle(*SVOp);
10473 // Check for non-undef masks pointing at an undef vector and make the masks
10474 // undef as well. This makes it easier to match the shuffle based solely on
10478 if (M >= NumElements) {
10479 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10480 for (int &M : NewMask)
10481 if (M >= NumElements)
10483 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10486 // Try to collapse shuffles into using a vector type with fewer elements but
10487 // wider element types. We cap this to not form integers or floating point
10488 // elements wider than 64 bits, but it might be interesting to form i128
10489 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10490 SmallVector<int, 16> WidenedMask;
10491 if (VT.getScalarSizeInBits() < 64 &&
10492 canWidenShuffleElements(Mask, WidenedMask)) {
10493 MVT NewEltVT = VT.isFloatingPoint()
10494 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10495 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10496 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10497 // Make sure that the new vector type is legal. For example, v2f64 isn't
10499 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10500 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10501 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10502 return DAG.getNode(ISD::BITCAST, dl, VT,
10503 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10507 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10508 for (int M : SVOp->getMask())
10510 ++NumUndefElements;
10511 else if (M < NumElements)
10516 // Commute the shuffle as needed such that more elements come from V1 than
10517 // V2. This allows us to match the shuffle pattern strictly on how many
10518 // elements come from V1 without handling the symmetric cases.
10519 if (NumV2Elements > NumV1Elements)
10520 return DAG.getCommutedVectorShuffle(*SVOp);
10522 // When the number of V1 and V2 elements are the same, try to minimize the
10523 // number of uses of V2 in the low half of the vector. When that is tied,
10524 // ensure that the sum of indices for V1 is equal to or lower than the sum
10526 if (NumV1Elements == NumV2Elements) {
10527 int LowV1Elements = 0, LowV2Elements = 0;
10528 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10529 if (M >= NumElements)
10533 if (LowV2Elements > LowV1Elements) {
10534 return DAG.getCommutedVectorShuffle(*SVOp);
10535 } else if (LowV2Elements == LowV1Elements) {
10536 int SumV1Indices = 0, SumV2Indices = 0;
10537 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10538 if (SVOp->getMask()[i] >= NumElements)
10540 else if (SVOp->getMask()[i] >= 0)
10542 if (SumV2Indices < SumV1Indices)
10543 return DAG.getCommutedVectorShuffle(*SVOp);
10547 // For each vector width, delegate to a specialized lowering routine.
10548 if (VT.getSizeInBits() == 128)
10549 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10551 if (VT.getSizeInBits() == 256)
10552 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10554 // Force AVX-512 vectors to be scalarized for now.
10555 // FIXME: Implement AVX-512 support!
10556 if (VT.getSizeInBits() == 512)
10557 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10559 llvm_unreachable("Unimplemented!");
10563 //===----------------------------------------------------------------------===//
10564 // Legacy vector shuffle lowering
10566 // This code is the legacy code handling vector shuffles until the above
10567 // replaces its functionality and performance.
10568 //===----------------------------------------------------------------------===//
10570 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10571 bool hasInt256, unsigned *MaskOut = nullptr) {
10572 MVT EltVT = VT.getVectorElementType();
10574 // There is no blend with immediate in AVX-512.
10575 if (VT.is512BitVector())
10578 if (!hasSSE41 || EltVT == MVT::i8)
10580 if (!hasInt256 && VT == MVT::v16i16)
10583 unsigned MaskValue = 0;
10584 unsigned NumElems = VT.getVectorNumElements();
10585 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10586 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10587 unsigned NumElemsInLane = NumElems / NumLanes;
10589 // Blend for v16i16 should be symetric for the both lanes.
10590 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10592 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10593 int EltIdx = MaskVals[i];
10595 if ((EltIdx < 0 || EltIdx == (int)i) &&
10596 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10599 if (((unsigned)EltIdx == (i + NumElems)) &&
10600 (SndLaneEltIdx < 0 ||
10601 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10602 MaskValue |= (1 << i);
10608 *MaskOut = MaskValue;
10612 // Try to lower a shuffle node into a simple blend instruction.
10613 // This function assumes isBlendMask returns true for this
10614 // SuffleVectorSDNode
10615 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10616 unsigned MaskValue,
10617 const X86Subtarget *Subtarget,
10618 SelectionDAG &DAG) {
10619 MVT VT = SVOp->getSimpleValueType(0);
10620 MVT EltVT = VT.getVectorElementType();
10621 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10622 Subtarget->hasInt256() && "Trying to lower a "
10623 "VECTOR_SHUFFLE to a Blend but "
10624 "with the wrong mask"));
10625 SDValue V1 = SVOp->getOperand(0);
10626 SDValue V2 = SVOp->getOperand(1);
10628 unsigned NumElems = VT.getVectorNumElements();
10630 // Convert i32 vectors to floating point if it is not AVX2.
10631 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10633 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10634 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10636 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10637 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10640 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10641 DAG.getConstant(MaskValue, MVT::i32));
10642 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10645 /// In vector type \p VT, return true if the element at index \p InputIdx
10646 /// falls on a different 128-bit lane than \p OutputIdx.
10647 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10648 unsigned OutputIdx) {
10649 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10650 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10653 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10654 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10655 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10656 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10658 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10659 SelectionDAG &DAG) {
10660 MVT VT = V1.getSimpleValueType();
10661 assert(VT.is128BitVector() || VT.is256BitVector());
10663 MVT EltVT = VT.getVectorElementType();
10664 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10665 unsigned NumElts = VT.getVectorNumElements();
10667 SmallVector<SDValue, 32> PshufbMask;
10668 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10669 int InputIdx = MaskVals[OutputIdx];
10670 unsigned InputByteIdx;
10672 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10673 InputByteIdx = 0x80;
10675 // Cross lane is not allowed.
10676 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10678 InputByteIdx = InputIdx * EltSizeInBytes;
10679 // Index is an byte offset within the 128-bit lane.
10680 InputByteIdx &= 0xf;
10683 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10684 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10685 if (InputByteIdx != 0x80)
10690 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10692 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10693 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10694 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10697 // v8i16 shuffles - Prefer shuffles in the following order:
10698 // 1. [all] pshuflw, pshufhw, optional move
10699 // 2. [ssse3] 1 x pshufb
10700 // 3. [ssse3] 2 x pshufb + 1 x por
10701 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10703 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10704 SelectionDAG &DAG) {
10705 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10706 SDValue V1 = SVOp->getOperand(0);
10707 SDValue V2 = SVOp->getOperand(1);
10709 SmallVector<int, 8> MaskVals;
10711 // Determine if more than 1 of the words in each of the low and high quadwords
10712 // of the result come from the same quadword of one of the two inputs. Undef
10713 // mask values count as coming from any quadword, for better codegen.
10715 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10716 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10717 unsigned LoQuad[] = { 0, 0, 0, 0 };
10718 unsigned HiQuad[] = { 0, 0, 0, 0 };
10719 // Indices of quads used.
10720 std::bitset<4> InputQuads;
10721 for (unsigned i = 0; i < 8; ++i) {
10722 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10723 int EltIdx = SVOp->getMaskElt(i);
10724 MaskVals.push_back(EltIdx);
10732 ++Quad[EltIdx / 4];
10733 InputQuads.set(EltIdx / 4);
10736 int BestLoQuad = -1;
10737 unsigned MaxQuad = 1;
10738 for (unsigned i = 0; i < 4; ++i) {
10739 if (LoQuad[i] > MaxQuad) {
10741 MaxQuad = LoQuad[i];
10745 int BestHiQuad = -1;
10747 for (unsigned i = 0; i < 4; ++i) {
10748 if (HiQuad[i] > MaxQuad) {
10750 MaxQuad = HiQuad[i];
10754 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10755 // of the two input vectors, shuffle them into one input vector so only a
10756 // single pshufb instruction is necessary. If there are more than 2 input
10757 // quads, disable the next transformation since it does not help SSSE3.
10758 bool V1Used = InputQuads[0] || InputQuads[1];
10759 bool V2Used = InputQuads[2] || InputQuads[3];
10760 if (Subtarget->hasSSSE3()) {
10761 if (InputQuads.count() == 2 && V1Used && V2Used) {
10762 BestLoQuad = InputQuads[0] ? 0 : 1;
10763 BestHiQuad = InputQuads[2] ? 2 : 3;
10765 if (InputQuads.count() > 2) {
10771 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10772 // the shuffle mask. If a quad is scored as -1, that means that it contains
10773 // words from all 4 input quadwords.
10775 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10777 BestLoQuad < 0 ? 0 : BestLoQuad,
10778 BestHiQuad < 0 ? 1 : BestHiQuad
10780 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10781 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10782 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10783 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10785 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10786 // source words for the shuffle, to aid later transformations.
10787 bool AllWordsInNewV = true;
10788 bool InOrder[2] = { true, true };
10789 for (unsigned i = 0; i != 8; ++i) {
10790 int idx = MaskVals[i];
10792 InOrder[i/4] = false;
10793 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10795 AllWordsInNewV = false;
10799 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10800 if (AllWordsInNewV) {
10801 for (int i = 0; i != 8; ++i) {
10802 int idx = MaskVals[i];
10805 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10806 if ((idx != i) && idx < 4)
10808 if ((idx != i) && idx > 3)
10817 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10818 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10819 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10820 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10821 unsigned TargetMask = 0;
10822 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10823 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10824 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10825 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10826 getShufflePSHUFLWImmediate(SVOp);
10827 V1 = NewV.getOperand(0);
10828 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10832 // Promote splats to a larger type which usually leads to more efficient code.
10833 // FIXME: Is this true if pshufb is available?
10834 if (SVOp->isSplat())
10835 return PromoteSplat(SVOp, DAG);
10837 // If we have SSSE3, and all words of the result are from 1 input vector,
10838 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10839 // is present, fall back to case 4.
10840 if (Subtarget->hasSSSE3()) {
10841 SmallVector<SDValue,16> pshufbMask;
10843 // If we have elements from both input vectors, set the high bit of the
10844 // shuffle mask element to zero out elements that come from V2 in the V1
10845 // mask, and elements that come from V1 in the V2 mask, so that the two
10846 // results can be OR'd together.
10847 bool TwoInputs = V1Used && V2Used;
10848 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10850 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10852 // Calculate the shuffle mask for the second input, shuffle it, and
10853 // OR it with the first shuffled input.
10854 CommuteVectorShuffleMask(MaskVals, 8);
10855 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10856 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10857 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10860 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10861 // and update MaskVals with new element order.
10862 std::bitset<8> InOrder;
10863 if (BestLoQuad >= 0) {
10864 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10865 for (int i = 0; i != 4; ++i) {
10866 int idx = MaskVals[i];
10869 } else if ((idx / 4) == BestLoQuad) {
10870 MaskV[i] = idx & 3;
10874 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10877 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10878 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10879 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10880 NewV.getOperand(0),
10881 getShufflePSHUFLWImmediate(SVOp), DAG);
10885 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10886 // and update MaskVals with the new element order.
10887 if (BestHiQuad >= 0) {
10888 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10889 for (unsigned i = 4; i != 8; ++i) {
10890 int idx = MaskVals[i];
10893 } else if ((idx / 4) == BestHiQuad) {
10894 MaskV[i] = (idx & 3) + 4;
10898 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10901 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10902 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10903 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10904 NewV.getOperand(0),
10905 getShufflePSHUFHWImmediate(SVOp), DAG);
10909 // In case BestHi & BestLo were both -1, which means each quadword has a word
10910 // from each of the four input quadwords, calculate the InOrder bitvector now
10911 // before falling through to the insert/extract cleanup.
10912 if (BestLoQuad == -1 && BestHiQuad == -1) {
10914 for (int i = 0; i != 8; ++i)
10915 if (MaskVals[i] < 0 || MaskVals[i] == i)
10919 // The other elements are put in the right place using pextrw and pinsrw.
10920 for (unsigned i = 0; i != 8; ++i) {
10923 int EltIdx = MaskVals[i];
10926 SDValue ExtOp = (EltIdx < 8) ?
10927 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10928 DAG.getIntPtrConstant(EltIdx)) :
10929 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10930 DAG.getIntPtrConstant(EltIdx - 8));
10931 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10932 DAG.getIntPtrConstant(i));
10937 /// \brief v16i16 shuffles
10939 /// FIXME: We only support generation of a single pshufb currently. We can
10940 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10941 /// well (e.g 2 x pshufb + 1 x por).
10943 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10944 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10945 SDValue V1 = SVOp->getOperand(0);
10946 SDValue V2 = SVOp->getOperand(1);
10949 if (V2.getOpcode() != ISD::UNDEF)
10952 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10953 return getPSHUFB(MaskVals, V1, dl, DAG);
10956 // v16i8 shuffles - Prefer shuffles in the following order:
10957 // 1. [ssse3] 1 x pshufb
10958 // 2. [ssse3] 2 x pshufb + 1 x por
10959 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10960 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10961 const X86Subtarget* Subtarget,
10962 SelectionDAG &DAG) {
10963 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10964 SDValue V1 = SVOp->getOperand(0);
10965 SDValue V2 = SVOp->getOperand(1);
10967 ArrayRef<int> MaskVals = SVOp->getMask();
10969 // Promote splats to a larger type which usually leads to more efficient code.
10970 // FIXME: Is this true if pshufb is available?
10971 if (SVOp->isSplat())
10972 return PromoteSplat(SVOp, DAG);
10974 // If we have SSSE3, case 1 is generated when all result bytes come from
10975 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10976 // present, fall back to case 3.
10978 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10979 if (Subtarget->hasSSSE3()) {
10980 SmallVector<SDValue,16> pshufbMask;
10982 // If all result elements are from one input vector, then only translate
10983 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10985 // Otherwise, we have elements from both input vectors, and must zero out
10986 // elements that come from V2 in the first mask, and V1 in the second mask
10987 // so that we can OR them together.
10988 for (unsigned i = 0; i != 16; ++i) {
10989 int EltIdx = MaskVals[i];
10990 if (EltIdx < 0 || EltIdx >= 16)
10992 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10994 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10995 DAG.getNode(ISD::BUILD_VECTOR, dl,
10996 MVT::v16i8, pshufbMask));
10998 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10999 // the 2nd operand if it's undefined or zero.
11000 if (V2.getOpcode() == ISD::UNDEF ||
11001 ISD::isBuildVectorAllZeros(V2.getNode()))
11004 // Calculate the shuffle mask for the second input, shuffle it, and
11005 // OR it with the first shuffled input.
11006 pshufbMask.clear();
11007 for (unsigned i = 0; i != 16; ++i) {
11008 int EltIdx = MaskVals[i];
11009 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11010 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11012 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11013 DAG.getNode(ISD::BUILD_VECTOR, dl,
11014 MVT::v16i8, pshufbMask));
11015 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11018 // No SSSE3 - Calculate in place words and then fix all out of place words
11019 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11020 // the 16 different words that comprise the two doublequadword input vectors.
11021 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11022 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11024 for (int i = 0; i != 8; ++i) {
11025 int Elt0 = MaskVals[i*2];
11026 int Elt1 = MaskVals[i*2+1];
11028 // This word of the result is all undef, skip it.
11029 if (Elt0 < 0 && Elt1 < 0)
11032 // This word of the result is already in the correct place, skip it.
11033 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11036 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11037 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11040 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11041 // using a single extract together, load it and store it.
11042 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11043 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11044 DAG.getIntPtrConstant(Elt1 / 2));
11045 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11046 DAG.getIntPtrConstant(i));
11050 // If Elt1 is defined, extract it from the appropriate source. If the
11051 // source byte is not also odd, shift the extracted word left 8 bits
11052 // otherwise clear the bottom 8 bits if we need to do an or.
11054 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11055 DAG.getIntPtrConstant(Elt1 / 2));
11056 if ((Elt1 & 1) == 0)
11057 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11059 TLI.getShiftAmountTy(InsElt.getValueType())));
11060 else if (Elt0 >= 0)
11061 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11062 DAG.getConstant(0xFF00, MVT::i16));
11064 // If Elt0 is defined, extract it from the appropriate source. If the
11065 // source byte is not also even, shift the extracted word right 8 bits. If
11066 // Elt1 was also defined, OR the extracted values together before
11067 // inserting them in the result.
11069 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11070 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11071 if ((Elt0 & 1) != 0)
11072 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11074 TLI.getShiftAmountTy(InsElt0.getValueType())));
11075 else if (Elt1 >= 0)
11076 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11077 DAG.getConstant(0x00FF, MVT::i16));
11078 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11081 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11082 DAG.getIntPtrConstant(i));
11084 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11087 // v32i8 shuffles - Translate to VPSHUFB if possible.
11089 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11090 const X86Subtarget *Subtarget,
11091 SelectionDAG &DAG) {
11092 MVT VT = SVOp->getSimpleValueType(0);
11093 SDValue V1 = SVOp->getOperand(0);
11094 SDValue V2 = SVOp->getOperand(1);
11096 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11098 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11099 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11100 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11102 // VPSHUFB may be generated if
11103 // (1) one of input vector is undefined or zeroinitializer.
11104 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11105 // And (2) the mask indexes don't cross the 128-bit lane.
11106 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11107 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11110 if (V1IsAllZero && !V2IsAllZero) {
11111 CommuteVectorShuffleMask(MaskVals, 32);
11114 return getPSHUFB(MaskVals, V1, dl, DAG);
11117 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11118 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11119 /// done when every pair / quad of shuffle mask elements point to elements in
11120 /// the right sequence. e.g.
11121 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11123 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11124 SelectionDAG &DAG) {
11125 MVT VT = SVOp->getSimpleValueType(0);
11127 unsigned NumElems = VT.getVectorNumElements();
11130 switch (VT.SimpleTy) {
11131 default: llvm_unreachable("Unexpected!");
11134 return SDValue(SVOp, 0);
11135 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11136 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11137 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11138 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11139 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11140 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11143 SmallVector<int, 8> MaskVec;
11144 for (unsigned i = 0; i != NumElems; i += Scale) {
11146 for (unsigned j = 0; j != Scale; ++j) {
11147 int EltIdx = SVOp->getMaskElt(i+j);
11151 StartIdx = (EltIdx / Scale);
11152 if (EltIdx != (int)(StartIdx*Scale + j))
11155 MaskVec.push_back(StartIdx);
11158 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11159 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11160 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11163 /// getVZextMovL - Return a zero-extending vector move low node.
11165 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11166 SDValue SrcOp, SelectionDAG &DAG,
11167 const X86Subtarget *Subtarget, SDLoc dl) {
11168 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11169 LoadSDNode *LD = nullptr;
11170 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11171 LD = dyn_cast<LoadSDNode>(SrcOp);
11173 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11175 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11176 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11177 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11178 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11179 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11181 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11182 return DAG.getNode(ISD::BITCAST, dl, VT,
11183 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11184 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11186 SrcOp.getOperand(0)
11192 return DAG.getNode(ISD::BITCAST, dl, VT,
11193 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11194 DAG.getNode(ISD::BITCAST, dl,
11198 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11199 /// which could not be matched by any known target speficic shuffle
11201 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11203 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11204 if (NewOp.getNode())
11207 MVT VT = SVOp->getSimpleValueType(0);
11209 unsigned NumElems = VT.getVectorNumElements();
11210 unsigned NumLaneElems = NumElems / 2;
11213 MVT EltVT = VT.getVectorElementType();
11214 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11217 SmallVector<int, 16> Mask;
11218 for (unsigned l = 0; l < 2; ++l) {
11219 // Build a shuffle mask for the output, discovering on the fly which
11220 // input vectors to use as shuffle operands (recorded in InputUsed).
11221 // If building a suitable shuffle vector proves too hard, then bail
11222 // out with UseBuildVector set.
11223 bool UseBuildVector = false;
11224 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11225 unsigned LaneStart = l * NumLaneElems;
11226 for (unsigned i = 0; i != NumLaneElems; ++i) {
11227 // The mask element. This indexes into the input.
11228 int Idx = SVOp->getMaskElt(i+LaneStart);
11230 // the mask element does not index into any input vector.
11231 Mask.push_back(-1);
11235 // The input vector this mask element indexes into.
11236 int Input = Idx / NumLaneElems;
11238 // Turn the index into an offset from the start of the input vector.
11239 Idx -= Input * NumLaneElems;
11241 // Find or create a shuffle vector operand to hold this input.
11243 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11244 if (InputUsed[OpNo] == Input)
11245 // This input vector is already an operand.
11247 if (InputUsed[OpNo] < 0) {
11248 // Create a new operand for this input vector.
11249 InputUsed[OpNo] = Input;
11254 if (OpNo >= array_lengthof(InputUsed)) {
11255 // More than two input vectors used! Give up on trying to create a
11256 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11257 UseBuildVector = true;
11261 // Add the mask index for the new shuffle vector.
11262 Mask.push_back(Idx + OpNo * NumLaneElems);
11265 if (UseBuildVector) {
11266 SmallVector<SDValue, 16> SVOps;
11267 for (unsigned i = 0; i != NumLaneElems; ++i) {
11268 // The mask element. This indexes into the input.
11269 int Idx = SVOp->getMaskElt(i+LaneStart);
11271 SVOps.push_back(DAG.getUNDEF(EltVT));
11275 // The input vector this mask element indexes into.
11276 int Input = Idx / NumElems;
11278 // Turn the index into an offset from the start of the input vector.
11279 Idx -= Input * NumElems;
11281 // Extract the vector element by hand.
11282 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11283 SVOp->getOperand(Input),
11284 DAG.getIntPtrConstant(Idx)));
11287 // Construct the output using a BUILD_VECTOR.
11288 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11289 } else if (InputUsed[0] < 0) {
11290 // No input vectors were used! The result is undefined.
11291 Output[l] = DAG.getUNDEF(NVT);
11293 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11294 (InputUsed[0] % 2) * NumLaneElems,
11296 // If only one input was used, use an undefined vector for the other.
11297 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11298 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11299 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11300 // At least one input vector was used. Create a new shuffle vector.
11301 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11307 // Concatenate the result back
11308 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11311 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11312 /// 4 elements, and match them with several different shuffle types.
11314 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11315 SDValue V1 = SVOp->getOperand(0);
11316 SDValue V2 = SVOp->getOperand(1);
11318 MVT VT = SVOp->getSimpleValueType(0);
11320 assert(VT.is128BitVector() && "Unsupported vector size");
11322 std::pair<int, int> Locs[4];
11323 int Mask1[] = { -1, -1, -1, -1 };
11324 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11326 unsigned NumHi = 0;
11327 unsigned NumLo = 0;
11328 for (unsigned i = 0; i != 4; ++i) {
11329 int Idx = PermMask[i];
11331 Locs[i] = std::make_pair(-1, -1);
11333 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11335 Locs[i] = std::make_pair(0, NumLo);
11336 Mask1[NumLo] = Idx;
11339 Locs[i] = std::make_pair(1, NumHi);
11341 Mask1[2+NumHi] = Idx;
11347 if (NumLo <= 2 && NumHi <= 2) {
11348 // If no more than two elements come from either vector. This can be
11349 // implemented with two shuffles. First shuffle gather the elements.
11350 // The second shuffle, which takes the first shuffle as both of its
11351 // vector operands, put the elements into the right order.
11352 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11354 int Mask2[] = { -1, -1, -1, -1 };
11356 for (unsigned i = 0; i != 4; ++i)
11357 if (Locs[i].first != -1) {
11358 unsigned Idx = (i < 2) ? 0 : 4;
11359 Idx += Locs[i].first * 2 + Locs[i].second;
11363 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11366 if (NumLo == 3 || NumHi == 3) {
11367 // Otherwise, we must have three elements from one vector, call it X, and
11368 // one element from the other, call it Y. First, use a shufps to build an
11369 // intermediate vector with the one element from Y and the element from X
11370 // that will be in the same half in the final destination (the indexes don't
11371 // matter). Then, use a shufps to build the final vector, taking the half
11372 // containing the element from Y from the intermediate, and the other half
11375 // Normalize it so the 3 elements come from V1.
11376 CommuteVectorShuffleMask(PermMask, 4);
11380 // Find the element from V2.
11382 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11383 int Val = PermMask[HiIndex];
11390 Mask1[0] = PermMask[HiIndex];
11392 Mask1[2] = PermMask[HiIndex^1];
11394 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11396 if (HiIndex >= 2) {
11397 Mask1[0] = PermMask[0];
11398 Mask1[1] = PermMask[1];
11399 Mask1[2] = HiIndex & 1 ? 6 : 4;
11400 Mask1[3] = HiIndex & 1 ? 4 : 6;
11401 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11404 Mask1[0] = HiIndex & 1 ? 2 : 0;
11405 Mask1[1] = HiIndex & 1 ? 0 : 2;
11406 Mask1[2] = PermMask[2];
11407 Mask1[3] = PermMask[3];
11412 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11415 // Break it into (shuffle shuffle_hi, shuffle_lo).
11416 int LoMask[] = { -1, -1, -1, -1 };
11417 int HiMask[] = { -1, -1, -1, -1 };
11419 int *MaskPtr = LoMask;
11420 unsigned MaskIdx = 0;
11421 unsigned LoIdx = 0;
11422 unsigned HiIdx = 2;
11423 for (unsigned i = 0; i != 4; ++i) {
11430 int Idx = PermMask[i];
11432 Locs[i] = std::make_pair(-1, -1);
11433 } else if (Idx < 4) {
11434 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11435 MaskPtr[LoIdx] = Idx;
11438 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11439 MaskPtr[HiIdx] = Idx;
11444 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11445 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11446 int MaskOps[] = { -1, -1, -1, -1 };
11447 for (unsigned i = 0; i != 4; ++i)
11448 if (Locs[i].first != -1)
11449 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11450 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11453 static bool MayFoldVectorLoad(SDValue V) {
11454 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11455 V = V.getOperand(0);
11457 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11458 V = V.getOperand(0);
11459 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11460 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11461 // BUILD_VECTOR (load), undef
11462 V = V.getOperand(0);
11464 return MayFoldLoad(V);
11468 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11469 MVT VT = Op.getSimpleValueType();
11471 // Canonizalize to v2f64.
11472 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11473 return DAG.getNode(ISD::BITCAST, dl, VT,
11474 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11479 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11481 SDValue V1 = Op.getOperand(0);
11482 SDValue V2 = Op.getOperand(1);
11483 MVT VT = Op.getSimpleValueType();
11485 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11487 if (HasSSE2 && VT == MVT::v2f64)
11488 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11490 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11491 return DAG.getNode(ISD::BITCAST, dl, VT,
11492 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11493 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11494 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11498 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11499 SDValue V1 = Op.getOperand(0);
11500 SDValue V2 = Op.getOperand(1);
11501 MVT VT = Op.getSimpleValueType();
11503 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11504 "unsupported shuffle type");
11506 if (V2.getOpcode() == ISD::UNDEF)
11510 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11514 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11515 SDValue V1 = Op.getOperand(0);
11516 SDValue V2 = Op.getOperand(1);
11517 MVT VT = Op.getSimpleValueType();
11518 unsigned NumElems = VT.getVectorNumElements();
11520 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11521 // operand of these instructions is only memory, so check if there's a
11522 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11524 bool CanFoldLoad = false;
11526 // Trivial case, when V2 comes from a load.
11527 if (MayFoldVectorLoad(V2))
11528 CanFoldLoad = true;
11530 // When V1 is a load, it can be folded later into a store in isel, example:
11531 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11533 // (MOVLPSmr addr:$src1, VR128:$src2)
11534 // So, recognize this potential and also use MOVLPS or MOVLPD
11535 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11536 CanFoldLoad = true;
11538 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11540 if (HasSSE2 && NumElems == 2)
11541 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11544 // If we don't care about the second element, proceed to use movss.
11545 if (SVOp->getMaskElt(1) != -1)
11546 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11549 // movl and movlp will both match v2i64, but v2i64 is never matched by
11550 // movl earlier because we make it strict to avoid messing with the movlp load
11551 // folding logic (see the code above getMOVLP call). Match it here then,
11552 // this is horrible, but will stay like this until we move all shuffle
11553 // matching to x86 specific nodes. Note that for the 1st condition all
11554 // types are matched with movsd.
11556 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11557 // as to remove this logic from here, as much as possible
11558 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11559 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11560 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11563 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11565 // Invert the operand order and use SHUFPS to match it.
11566 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11567 getShuffleSHUFImmediate(SVOp), DAG);
11570 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11571 SelectionDAG &DAG) {
11573 MVT VT = Load->getSimpleValueType(0);
11574 MVT EVT = VT.getVectorElementType();
11575 SDValue Addr = Load->getOperand(1);
11576 SDValue NewAddr = DAG.getNode(
11577 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11578 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11581 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11582 DAG.getMachineFunction().getMachineMemOperand(
11583 Load->getMemOperand(), 0, EVT.getStoreSize()));
11587 // It is only safe to call this function if isINSERTPSMask is true for
11588 // this shufflevector mask.
11589 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11590 SelectionDAG &DAG) {
11591 // Generate an insertps instruction when inserting an f32 from memory onto a
11592 // v4f32 or when copying a member from one v4f32 to another.
11593 // We also use it for transferring i32 from one register to another,
11594 // since it simply copies the same bits.
11595 // If we're transferring an i32 from memory to a specific element in a
11596 // register, we output a generic DAG that will match the PINSRD
11598 MVT VT = SVOp->getSimpleValueType(0);
11599 MVT EVT = VT.getVectorElementType();
11600 SDValue V1 = SVOp->getOperand(0);
11601 SDValue V2 = SVOp->getOperand(1);
11602 auto Mask = SVOp->getMask();
11603 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11604 "unsupported vector type for insertps/pinsrd");
11606 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11607 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11608 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11612 unsigned DestIndex;
11616 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11619 // If we have 1 element from each vector, we have to check if we're
11620 // changing V1's element's place. If so, we're done. Otherwise, we
11621 // should assume we're changing V2's element's place and behave
11623 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11624 assert(DestIndex <= INT32_MAX && "truncated destination index");
11625 if (FromV1 == FromV2 &&
11626 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11630 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11633 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11634 "More than one element from V1 and from V2, or no elements from one "
11635 "of the vectors. This case should not have returned true from "
11640 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11643 // Get an index into the source vector in the range [0,4) (the mask is
11644 // in the range [0,8) because it can address V1 and V2)
11645 unsigned SrcIndex = Mask[DestIndex] % 4;
11646 if (MayFoldLoad(From)) {
11647 // Trivial case, when From comes from a load and is only used by the
11648 // shuffle. Make it use insertps from the vector that we need from that
11651 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11652 if (!NewLoad.getNode())
11655 if (EVT == MVT::f32) {
11656 // Create this as a scalar to vector to match the instruction pattern.
11657 SDValue LoadScalarToVector =
11658 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11659 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11660 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11662 } else { // EVT == MVT::i32
11663 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11664 // instruction, to match the PINSRD instruction, which loads an i32 to a
11665 // certain vector element.
11666 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11667 DAG.getConstant(DestIndex, MVT::i32));
11671 // Vector-element-to-vector
11672 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11673 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11676 // Reduce a vector shuffle to zext.
11677 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11678 SelectionDAG &DAG) {
11679 // PMOVZX is only available from SSE41.
11680 if (!Subtarget->hasSSE41())
11683 MVT VT = Op.getSimpleValueType();
11685 // Only AVX2 support 256-bit vector integer extending.
11686 if (!Subtarget->hasInt256() && VT.is256BitVector())
11689 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11691 SDValue V1 = Op.getOperand(0);
11692 SDValue V2 = Op.getOperand(1);
11693 unsigned NumElems = VT.getVectorNumElements();
11695 // Extending is an unary operation and the element type of the source vector
11696 // won't be equal to or larger than i64.
11697 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11698 VT.getVectorElementType() == MVT::i64)
11701 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11702 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11703 while ((1U << Shift) < NumElems) {
11704 if (SVOp->getMaskElt(1U << Shift) == 1)
11707 // The maximal ratio is 8, i.e. from i8 to i64.
11712 // Check the shuffle mask.
11713 unsigned Mask = (1U << Shift) - 1;
11714 for (unsigned i = 0; i != NumElems; ++i) {
11715 int EltIdx = SVOp->getMaskElt(i);
11716 if ((i & Mask) != 0 && EltIdx != -1)
11718 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11722 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11723 MVT NeVT = MVT::getIntegerVT(NBits);
11724 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11726 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11729 return DAG.getNode(ISD::BITCAST, DL, VT,
11730 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11733 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11734 SelectionDAG &DAG) {
11735 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11736 MVT VT = Op.getSimpleValueType();
11738 SDValue V1 = Op.getOperand(0);
11739 SDValue V2 = Op.getOperand(1);
11741 if (isZeroShuffle(SVOp))
11742 return getZeroVector(VT, Subtarget, DAG, dl);
11744 // Handle splat operations
11745 if (SVOp->isSplat()) {
11746 // Use vbroadcast whenever the splat comes from a foldable load
11747 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11748 if (Broadcast.getNode())
11752 // Check integer expanding shuffles.
11753 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11754 if (NewOp.getNode())
11757 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11759 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11760 VT == MVT::v32i8) {
11761 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11762 if (NewOp.getNode())
11763 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11764 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11765 // FIXME: Figure out a cleaner way to do this.
11766 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11767 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11768 if (NewOp.getNode()) {
11769 MVT NewVT = NewOp.getSimpleValueType();
11770 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11771 NewVT, true, false))
11772 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11775 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11776 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11777 if (NewOp.getNode()) {
11778 MVT NewVT = NewOp.getSimpleValueType();
11779 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11780 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11789 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11790 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11791 SDValue V1 = Op.getOperand(0);
11792 SDValue V2 = Op.getOperand(1);
11793 MVT VT = Op.getSimpleValueType();
11795 unsigned NumElems = VT.getVectorNumElements();
11796 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11797 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11798 bool V1IsSplat = false;
11799 bool V2IsSplat = false;
11800 bool HasSSE2 = Subtarget->hasSSE2();
11801 bool HasFp256 = Subtarget->hasFp256();
11802 bool HasInt256 = Subtarget->hasInt256();
11803 MachineFunction &MF = DAG.getMachineFunction();
11804 bool OptForSize = MF.getFunction()->getAttributes().
11805 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11807 // Check if we should use the experimental vector shuffle lowering. If so,
11808 // delegate completely to that code path.
11809 if (ExperimentalVectorShuffleLowering)
11810 return lowerVectorShuffle(Op, Subtarget, DAG);
11812 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11814 if (V1IsUndef && V2IsUndef)
11815 return DAG.getUNDEF(VT);
11817 // When we create a shuffle node we put the UNDEF node to second operand,
11818 // but in some cases the first operand may be transformed to UNDEF.
11819 // In this case we should just commute the node.
11821 return DAG.getCommutedVectorShuffle(*SVOp);
11823 // Vector shuffle lowering takes 3 steps:
11825 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11826 // narrowing and commutation of operands should be handled.
11827 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11829 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11830 // so the shuffle can be broken into other shuffles and the legalizer can
11831 // try the lowering again.
11833 // The general idea is that no vector_shuffle operation should be left to
11834 // be matched during isel, all of them must be converted to a target specific
11837 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11838 // narrowing and commutation of operands should be handled. The actual code
11839 // doesn't include all of those, work in progress...
11840 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11841 if (NewOp.getNode())
11844 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11846 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11847 // unpckh_undef). Only use pshufd if speed is more important than size.
11848 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11849 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11850 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11851 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11853 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11854 V2IsUndef && MayFoldVectorLoad(V1))
11855 return getMOVDDup(Op, dl, V1, DAG);
11857 if (isMOVHLPS_v_undef_Mask(M, VT))
11858 return getMOVHighToLow(Op, dl, DAG);
11860 // Use to match splats
11861 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11862 (VT == MVT::v2f64 || VT == MVT::v2i64))
11863 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11865 if (isPSHUFDMask(M, VT)) {
11866 // The actual implementation will match the mask in the if above and then
11867 // during isel it can match several different instructions, not only pshufd
11868 // as its name says, sad but true, emulate the behavior for now...
11869 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11870 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11872 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11874 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11875 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11877 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11878 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11881 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11885 if (isPALIGNRMask(M, VT, Subtarget))
11886 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11887 getShufflePALIGNRImmediate(SVOp),
11890 if (isVALIGNMask(M, VT, Subtarget))
11891 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11892 getShuffleVALIGNImmediate(SVOp),
11895 // Check if this can be converted into a logical shift.
11896 bool isLeft = false;
11897 unsigned ShAmt = 0;
11899 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11900 if (isShift && ShVal.hasOneUse()) {
11901 // If the shifted value has multiple uses, it may be cheaper to use
11902 // v_set0 + movlhps or movhlps, etc.
11903 MVT EltVT = VT.getVectorElementType();
11904 ShAmt *= EltVT.getSizeInBits();
11905 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11908 if (isMOVLMask(M, VT)) {
11909 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11910 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11911 if (!isMOVLPMask(M, VT)) {
11912 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11913 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11915 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11916 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11920 // FIXME: fold these into legal mask.
11921 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11922 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11924 if (isMOVHLPSMask(M, VT))
11925 return getMOVHighToLow(Op, dl, DAG);
11927 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11928 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11930 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11931 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11933 if (isMOVLPMask(M, VT))
11934 return getMOVLP(Op, dl, DAG, HasSSE2);
11936 if (ShouldXformToMOVHLPS(M, VT) ||
11937 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11938 return DAG.getCommutedVectorShuffle(*SVOp);
11941 // No better options. Use a vshldq / vsrldq.
11942 MVT EltVT = VT.getVectorElementType();
11943 ShAmt *= EltVT.getSizeInBits();
11944 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11947 bool Commuted = false;
11948 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11949 // 1,1,1,1 -> v8i16 though.
11950 BitVector UndefElements;
11951 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11952 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11954 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11955 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11958 // Canonicalize the splat or undef, if present, to be on the RHS.
11959 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11960 CommuteVectorShuffleMask(M, NumElems);
11962 std::swap(V1IsSplat, V2IsSplat);
11966 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11967 // Shuffling low element of v1 into undef, just return v1.
11970 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11971 // the instruction selector will not match, so get a canonical MOVL with
11972 // swapped operands to undo the commute.
11973 return getMOVL(DAG, dl, VT, V2, V1);
11976 if (isUNPCKLMask(M, VT, HasInt256))
11977 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11979 if (isUNPCKHMask(M, VT, HasInt256))
11980 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11983 // Normalize mask so all entries that point to V2 points to its first
11984 // element then try to match unpck{h|l} again. If match, return a
11985 // new vector_shuffle with the corrected mask.p
11986 SmallVector<int, 8> NewMask(M.begin(), M.end());
11987 NormalizeMask(NewMask, NumElems);
11988 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11989 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11990 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11991 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11995 // Commute is back and try unpck* again.
11996 // FIXME: this seems wrong.
11997 CommuteVectorShuffleMask(M, NumElems);
11999 std::swap(V1IsSplat, V2IsSplat);
12001 if (isUNPCKLMask(M, VT, HasInt256))
12002 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12004 if (isUNPCKHMask(M, VT, HasInt256))
12005 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12008 // Normalize the node to match x86 shuffle ops if needed
12009 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12010 return DAG.getCommutedVectorShuffle(*SVOp);
12012 // The checks below are all present in isShuffleMaskLegal, but they are
12013 // inlined here right now to enable us to directly emit target specific
12014 // nodes, and remove one by one until they don't return Op anymore.
12016 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12017 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12018 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12019 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12022 if (isPSHUFHWMask(M, VT, HasInt256))
12023 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12024 getShufflePSHUFHWImmediate(SVOp),
12027 if (isPSHUFLWMask(M, VT, HasInt256))
12028 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12029 getShufflePSHUFLWImmediate(SVOp),
12032 unsigned MaskValue;
12033 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12035 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12037 if (isSHUFPMask(M, VT))
12038 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12039 getShuffleSHUFImmediate(SVOp), DAG);
12041 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12042 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12043 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12044 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12046 //===--------------------------------------------------------------------===//
12047 // Generate target specific nodes for 128 or 256-bit shuffles only
12048 // supported in the AVX instruction set.
12051 // Handle VMOVDDUPY permutations
12052 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12053 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12055 // Handle VPERMILPS/D* permutations
12056 if (isVPERMILPMask(M, VT)) {
12057 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12058 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12059 getShuffleSHUFImmediate(SVOp), DAG);
12060 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12061 getShuffleSHUFImmediate(SVOp), DAG);
12065 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12066 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12067 Idx*(NumElems/2), DAG, dl);
12069 // Handle VPERM2F128/VPERM2I128 permutations
12070 if (isVPERM2X128Mask(M, VT, HasFp256))
12071 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12072 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12074 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12075 return getINSERTPS(SVOp, dl, DAG);
12078 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12079 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12081 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12082 VT.is512BitVector()) {
12083 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12084 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12085 SmallVector<SDValue, 16> permclMask;
12086 for (unsigned i = 0; i != NumElems; ++i) {
12087 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12090 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12092 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12093 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12094 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12095 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12096 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12099 //===--------------------------------------------------------------------===//
12100 // Since no target specific shuffle was selected for this generic one,
12101 // lower it into other known shuffles. FIXME: this isn't true yet, but
12102 // this is the plan.
12105 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12106 if (VT == MVT::v8i16) {
12107 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12108 if (NewOp.getNode())
12112 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12113 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12114 if (NewOp.getNode())
12118 if (VT == MVT::v16i8) {
12119 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12120 if (NewOp.getNode())
12124 if (VT == MVT::v32i8) {
12125 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12126 if (NewOp.getNode())
12130 // Handle all 128-bit wide vectors with 4 elements, and match them with
12131 // several different shuffle types.
12132 if (NumElems == 4 && VT.is128BitVector())
12133 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12135 // Handle general 256-bit shuffles
12136 if (VT.is256BitVector())
12137 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12142 // This function assumes its argument is a BUILD_VECTOR of constants or
12143 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12145 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12146 unsigned &MaskValue) {
12148 unsigned NumElems = BuildVector->getNumOperands();
12149 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12150 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12151 unsigned NumElemsInLane = NumElems / NumLanes;
12153 // Blend for v16i16 should be symetric for the both lanes.
12154 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12155 SDValue EltCond = BuildVector->getOperand(i);
12156 SDValue SndLaneEltCond =
12157 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12159 int Lane1Cond = -1, Lane2Cond = -1;
12160 if (isa<ConstantSDNode>(EltCond))
12161 Lane1Cond = !isZero(EltCond);
12162 if (isa<ConstantSDNode>(SndLaneEltCond))
12163 Lane2Cond = !isZero(SndLaneEltCond);
12165 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12166 // Lane1Cond != 0, means we want the first argument.
12167 // Lane1Cond == 0, means we want the second argument.
12168 // The encoding of this argument is 0 for the first argument, 1
12169 // for the second. Therefore, invert the condition.
12170 MaskValue |= !Lane1Cond << i;
12171 else if (Lane1Cond < 0)
12172 MaskValue |= !Lane2Cond << i;
12179 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12181 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12182 SelectionDAG &DAG) {
12183 SDValue Cond = Op.getOperand(0);
12184 SDValue LHS = Op.getOperand(1);
12185 SDValue RHS = Op.getOperand(2);
12187 MVT VT = Op.getSimpleValueType();
12188 MVT EltVT = VT.getVectorElementType();
12189 unsigned NumElems = VT.getVectorNumElements();
12191 // There is no blend with immediate in AVX-512.
12192 if (VT.is512BitVector())
12195 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12197 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12200 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12203 // Check the mask for BLEND and build the value.
12204 unsigned MaskValue = 0;
12205 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12208 // Convert i32 vectors to floating point if it is not AVX2.
12209 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12211 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12212 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12214 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12215 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12218 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12219 DAG.getConstant(MaskValue, MVT::i32));
12220 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12223 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12224 // A vselect where all conditions and data are constants can be optimized into
12225 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12226 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12227 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12228 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12231 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12232 if (BlendOp.getNode())
12235 // Some types for vselect were previously set to Expand, not Legal or
12236 // Custom. Return an empty SDValue so we fall-through to Expand, after
12237 // the Custom lowering phase.
12238 MVT VT = Op.getSimpleValueType();
12239 switch (VT.SimpleTy) {
12244 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12249 // We couldn't create a "Blend with immediate" node.
12250 // This node should still be legal, but we'll have to emit a blendv*
12255 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12256 MVT VT = Op.getSimpleValueType();
12259 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12262 if (VT.getSizeInBits() == 8) {
12263 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12264 Op.getOperand(0), Op.getOperand(1));
12265 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12266 DAG.getValueType(VT));
12267 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12270 if (VT.getSizeInBits() == 16) {
12271 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12272 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12274 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12275 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12276 DAG.getNode(ISD::BITCAST, dl,
12279 Op.getOperand(1)));
12280 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12281 Op.getOperand(0), Op.getOperand(1));
12282 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12283 DAG.getValueType(VT));
12284 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12287 if (VT == MVT::f32) {
12288 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12289 // the result back to FR32 register. It's only worth matching if the
12290 // result has a single use which is a store or a bitcast to i32. And in
12291 // the case of a store, it's not worth it if the index is a constant 0,
12292 // because a MOVSSmr can be used instead, which is smaller and faster.
12293 if (!Op.hasOneUse())
12295 SDNode *User = *Op.getNode()->use_begin();
12296 if ((User->getOpcode() != ISD::STORE ||
12297 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12298 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12299 (User->getOpcode() != ISD::BITCAST ||
12300 User->getValueType(0) != MVT::i32))
12302 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12303 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12306 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12309 if (VT == MVT::i32 || VT == MVT::i64) {
12310 // ExtractPS/pextrq works with constant index.
12311 if (isa<ConstantSDNode>(Op.getOperand(1)))
12317 /// Extract one bit from mask vector, like v16i1 or v8i1.
12318 /// AVX-512 feature.
12320 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12321 SDValue Vec = Op.getOperand(0);
12323 MVT VecVT = Vec.getSimpleValueType();
12324 SDValue Idx = Op.getOperand(1);
12325 MVT EltVT = Op.getSimpleValueType();
12327 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12329 // variable index can't be handled in mask registers,
12330 // extend vector to VR512
12331 if (!isa<ConstantSDNode>(Idx)) {
12332 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12333 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12334 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12335 ExtVT.getVectorElementType(), Ext, Idx);
12336 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12339 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12340 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12341 unsigned MaxSift = rc->getSize()*8 - 1;
12342 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12343 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12344 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12345 DAG.getConstant(MaxSift, MVT::i8));
12346 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12347 DAG.getIntPtrConstant(0));
12351 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12352 SelectionDAG &DAG) const {
12354 SDValue Vec = Op.getOperand(0);
12355 MVT VecVT = Vec.getSimpleValueType();
12356 SDValue Idx = Op.getOperand(1);
12358 if (Op.getSimpleValueType() == MVT::i1)
12359 return ExtractBitFromMaskVector(Op, DAG);
12361 if (!isa<ConstantSDNode>(Idx)) {
12362 if (VecVT.is512BitVector() ||
12363 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12364 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12367 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12368 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12369 MaskEltVT.getSizeInBits());
12371 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12372 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12373 getZeroVector(MaskVT, Subtarget, DAG, dl),
12374 Idx, DAG.getConstant(0, getPointerTy()));
12375 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12376 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12377 Perm, DAG.getConstant(0, getPointerTy()));
12382 // If this is a 256-bit vector result, first extract the 128-bit vector and
12383 // then extract the element from the 128-bit vector.
12384 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12386 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12387 // Get the 128-bit vector.
12388 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12389 MVT EltVT = VecVT.getVectorElementType();
12391 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12393 //if (IdxVal >= NumElems/2)
12394 // IdxVal -= NumElems/2;
12395 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12396 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12397 DAG.getConstant(IdxVal, MVT::i32));
12400 assert(VecVT.is128BitVector() && "Unexpected vector length");
12402 if (Subtarget->hasSSE41()) {
12403 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12408 MVT VT = Op.getSimpleValueType();
12409 // TODO: handle v16i8.
12410 if (VT.getSizeInBits() == 16) {
12411 SDValue Vec = Op.getOperand(0);
12412 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12414 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12415 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12416 DAG.getNode(ISD::BITCAST, dl,
12418 Op.getOperand(1)));
12419 // Transform it so it match pextrw which produces a 32-bit result.
12420 MVT EltVT = MVT::i32;
12421 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12422 Op.getOperand(0), Op.getOperand(1));
12423 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12424 DAG.getValueType(VT));
12425 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12428 if (VT.getSizeInBits() == 32) {
12429 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12433 // SHUFPS the element to the lowest double word, then movss.
12434 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12435 MVT VVT = Op.getOperand(0).getSimpleValueType();
12436 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12437 DAG.getUNDEF(VVT), Mask);
12438 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12439 DAG.getIntPtrConstant(0));
12442 if (VT.getSizeInBits() == 64) {
12443 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12444 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12445 // to match extract_elt for f64.
12446 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12450 // UNPCKHPD the element to the lowest double word, then movsd.
12451 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12452 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12453 int Mask[2] = { 1, -1 };
12454 MVT VVT = Op.getOperand(0).getSimpleValueType();
12455 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12456 DAG.getUNDEF(VVT), Mask);
12457 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12458 DAG.getIntPtrConstant(0));
12464 /// Insert one bit to mask vector, like v16i1 or v8i1.
12465 /// AVX-512 feature.
12467 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12469 SDValue Vec = Op.getOperand(0);
12470 SDValue Elt = Op.getOperand(1);
12471 SDValue Idx = Op.getOperand(2);
12472 MVT VecVT = Vec.getSimpleValueType();
12474 if (!isa<ConstantSDNode>(Idx)) {
12475 // Non constant index. Extend source and destination,
12476 // insert element and then truncate the result.
12477 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12478 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12479 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12480 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12481 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12482 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12485 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12486 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12487 if (Vec.getOpcode() == ISD::UNDEF)
12488 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12489 DAG.getConstant(IdxVal, MVT::i8));
12490 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12491 unsigned MaxSift = rc->getSize()*8 - 1;
12492 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12493 DAG.getConstant(MaxSift, MVT::i8));
12494 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12495 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12496 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12499 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12500 SelectionDAG &DAG) const {
12501 MVT VT = Op.getSimpleValueType();
12502 MVT EltVT = VT.getVectorElementType();
12504 if (EltVT == MVT::i1)
12505 return InsertBitToMaskVector(Op, DAG);
12508 SDValue N0 = Op.getOperand(0);
12509 SDValue N1 = Op.getOperand(1);
12510 SDValue N2 = Op.getOperand(2);
12511 if (!isa<ConstantSDNode>(N2))
12513 auto *N2C = cast<ConstantSDNode>(N2);
12514 unsigned IdxVal = N2C->getZExtValue();
12516 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12517 // into that, and then insert the subvector back into the result.
12518 if (VT.is256BitVector() || VT.is512BitVector()) {
12519 // Get the desired 128-bit vector half.
12520 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12522 // Insert the element into the desired half.
12523 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12524 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12526 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12527 DAG.getConstant(IdxIn128, MVT::i32));
12529 // Insert the changed part back to the 256-bit vector
12530 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12532 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12534 if (Subtarget->hasSSE41()) {
12535 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12537 if (VT == MVT::v8i16) {
12538 Opc = X86ISD::PINSRW;
12540 assert(VT == MVT::v16i8);
12541 Opc = X86ISD::PINSRB;
12544 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12546 if (N1.getValueType() != MVT::i32)
12547 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12548 if (N2.getValueType() != MVT::i32)
12549 N2 = DAG.getIntPtrConstant(IdxVal);
12550 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12553 if (EltVT == MVT::f32) {
12554 // Bits [7:6] of the constant are the source select. This will always be
12555 // zero here. The DAG Combiner may combine an extract_elt index into
12557 // bits. For example (insert (extract, 3), 2) could be matched by
12559 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12560 // Bits [5:4] of the constant are the destination select. This is the
12561 // value of the incoming immediate.
12562 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12563 // combine either bitwise AND or insert of float 0.0 to set these bits.
12564 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12565 // Create this as a scalar to vector..
12566 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12567 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12570 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12571 // PINSR* works with constant index.
12576 if (EltVT == MVT::i8)
12579 if (EltVT.getSizeInBits() == 16) {
12580 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12581 // as its second argument.
12582 if (N1.getValueType() != MVT::i32)
12583 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12584 if (N2.getValueType() != MVT::i32)
12585 N2 = DAG.getIntPtrConstant(IdxVal);
12586 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12591 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12593 MVT OpVT = Op.getSimpleValueType();
12595 // If this is a 256-bit vector result, first insert into a 128-bit
12596 // vector and then insert into the 256-bit vector.
12597 if (!OpVT.is128BitVector()) {
12598 // Insert into a 128-bit vector.
12599 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12600 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12601 OpVT.getVectorNumElements() / SizeFactor);
12603 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12605 // Insert the 128-bit vector.
12606 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12609 if (OpVT == MVT::v1i64 &&
12610 Op.getOperand(0).getValueType() == MVT::i64)
12611 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12613 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12614 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12615 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12616 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12619 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12620 // a simple subregister reference or explicit instructions to grab
12621 // upper bits of a vector.
12622 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12623 SelectionDAG &DAG) {
12625 SDValue In = Op.getOperand(0);
12626 SDValue Idx = Op.getOperand(1);
12627 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12628 MVT ResVT = Op.getSimpleValueType();
12629 MVT InVT = In.getSimpleValueType();
12631 if (Subtarget->hasFp256()) {
12632 if (ResVT.is128BitVector() &&
12633 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12634 isa<ConstantSDNode>(Idx)) {
12635 return Extract128BitVector(In, IdxVal, DAG, dl);
12637 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12638 isa<ConstantSDNode>(Idx)) {
12639 return Extract256BitVector(In, IdxVal, DAG, dl);
12645 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12646 // simple superregister reference or explicit instructions to insert
12647 // the upper bits of a vector.
12648 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12649 SelectionDAG &DAG) {
12650 if (Subtarget->hasFp256()) {
12651 SDLoc dl(Op.getNode());
12652 SDValue Vec = Op.getNode()->getOperand(0);
12653 SDValue SubVec = Op.getNode()->getOperand(1);
12654 SDValue Idx = Op.getNode()->getOperand(2);
12656 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12657 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12658 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12659 isa<ConstantSDNode>(Idx)) {
12660 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12661 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12664 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12665 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12666 isa<ConstantSDNode>(Idx)) {
12667 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12668 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12674 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12675 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12676 // one of the above mentioned nodes. It has to be wrapped because otherwise
12677 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12678 // be used to form addressing mode. These wrapped nodes will be selected
12681 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12682 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12684 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12685 // global base reg.
12686 unsigned char OpFlag = 0;
12687 unsigned WrapperKind = X86ISD::Wrapper;
12688 CodeModel::Model M = DAG.getTarget().getCodeModel();
12690 if (Subtarget->isPICStyleRIPRel() &&
12691 (M == CodeModel::Small || M == CodeModel::Kernel))
12692 WrapperKind = X86ISD::WrapperRIP;
12693 else if (Subtarget->isPICStyleGOT())
12694 OpFlag = X86II::MO_GOTOFF;
12695 else if (Subtarget->isPICStyleStubPIC())
12696 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12698 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12699 CP->getAlignment(),
12700 CP->getOffset(), OpFlag);
12702 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12703 // With PIC, the address is actually $g + Offset.
12705 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12706 DAG.getNode(X86ISD::GlobalBaseReg,
12707 SDLoc(), getPointerTy()),
12714 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12715 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12717 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12718 // global base reg.
12719 unsigned char OpFlag = 0;
12720 unsigned WrapperKind = X86ISD::Wrapper;
12721 CodeModel::Model M = DAG.getTarget().getCodeModel();
12723 if (Subtarget->isPICStyleRIPRel() &&
12724 (M == CodeModel::Small || M == CodeModel::Kernel))
12725 WrapperKind = X86ISD::WrapperRIP;
12726 else if (Subtarget->isPICStyleGOT())
12727 OpFlag = X86II::MO_GOTOFF;
12728 else if (Subtarget->isPICStyleStubPIC())
12729 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12731 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12734 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12736 // With PIC, the address is actually $g + Offset.
12738 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12739 DAG.getNode(X86ISD::GlobalBaseReg,
12740 SDLoc(), getPointerTy()),
12747 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12748 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12750 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12751 // global base reg.
12752 unsigned char OpFlag = 0;
12753 unsigned WrapperKind = X86ISD::Wrapper;
12754 CodeModel::Model M = DAG.getTarget().getCodeModel();
12756 if (Subtarget->isPICStyleRIPRel() &&
12757 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12758 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12759 OpFlag = X86II::MO_GOTPCREL;
12760 WrapperKind = X86ISD::WrapperRIP;
12761 } else if (Subtarget->isPICStyleGOT()) {
12762 OpFlag = X86II::MO_GOT;
12763 } else if (Subtarget->isPICStyleStubPIC()) {
12764 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12765 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12766 OpFlag = X86II::MO_DARWIN_NONLAZY;
12769 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12772 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12774 // With PIC, the address is actually $g + Offset.
12775 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12776 !Subtarget->is64Bit()) {
12777 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12778 DAG.getNode(X86ISD::GlobalBaseReg,
12779 SDLoc(), getPointerTy()),
12783 // For symbols that require a load from a stub to get the address, emit the
12785 if (isGlobalStubReference(OpFlag))
12786 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12787 MachinePointerInfo::getGOT(), false, false, false, 0);
12793 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12794 // Create the TargetBlockAddressAddress node.
12795 unsigned char OpFlags =
12796 Subtarget->ClassifyBlockAddressReference();
12797 CodeModel::Model M = DAG.getTarget().getCodeModel();
12798 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12799 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12801 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12804 if (Subtarget->isPICStyleRIPRel() &&
12805 (M == CodeModel::Small || M == CodeModel::Kernel))
12806 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12808 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12810 // With PIC, the address is actually $g + Offset.
12811 if (isGlobalRelativeToPICBase(OpFlags)) {
12812 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12813 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12821 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12822 int64_t Offset, SelectionDAG &DAG) const {
12823 // Create the TargetGlobalAddress node, folding in the constant
12824 // offset if it is legal.
12825 unsigned char OpFlags =
12826 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12827 CodeModel::Model M = DAG.getTarget().getCodeModel();
12829 if (OpFlags == X86II::MO_NO_FLAG &&
12830 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12831 // A direct static reference to a global.
12832 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12835 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12838 if (Subtarget->isPICStyleRIPRel() &&
12839 (M == CodeModel::Small || M == CodeModel::Kernel))
12840 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12842 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12844 // With PIC, the address is actually $g + Offset.
12845 if (isGlobalRelativeToPICBase(OpFlags)) {
12846 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12847 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12851 // For globals that require a load from a stub to get the address, emit the
12853 if (isGlobalStubReference(OpFlags))
12854 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12855 MachinePointerInfo::getGOT(), false, false, false, 0);
12857 // If there was a non-zero offset that we didn't fold, create an explicit
12858 // addition for it.
12860 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12861 DAG.getConstant(Offset, getPointerTy()));
12867 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12868 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12869 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12870 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12874 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12875 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12876 unsigned char OperandFlags, bool LocalDynamic = false) {
12877 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12878 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12880 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12881 GA->getValueType(0),
12885 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12889 SDValue Ops[] = { Chain, TGA, *InFlag };
12890 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12892 SDValue Ops[] = { Chain, TGA };
12893 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12896 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12897 MFI->setAdjustsStack(true);
12898 MFI->setHasCalls(true);
12900 SDValue Flag = Chain.getValue(1);
12901 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12904 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12906 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12909 SDLoc dl(GA); // ? function entry point might be better
12910 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12911 DAG.getNode(X86ISD::GlobalBaseReg,
12912 SDLoc(), PtrVT), InFlag);
12913 InFlag = Chain.getValue(1);
12915 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12918 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12920 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12922 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12923 X86::RAX, X86II::MO_TLSGD);
12926 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12932 // Get the start address of the TLS block for this module.
12933 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12934 .getInfo<X86MachineFunctionInfo>();
12935 MFI->incNumLocalDynamicTLSAccesses();
12939 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12940 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12943 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12944 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12945 InFlag = Chain.getValue(1);
12946 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12947 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12950 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12954 unsigned char OperandFlags = X86II::MO_DTPOFF;
12955 unsigned WrapperKind = X86ISD::Wrapper;
12956 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12957 GA->getValueType(0),
12958 GA->getOffset(), OperandFlags);
12959 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12961 // Add x@dtpoff with the base.
12962 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12965 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12966 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12967 const EVT PtrVT, TLSModel::Model model,
12968 bool is64Bit, bool isPIC) {
12971 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12972 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12973 is64Bit ? 257 : 256));
12975 SDValue ThreadPointer =
12976 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12977 MachinePointerInfo(Ptr), false, false, false, 0);
12979 unsigned char OperandFlags = 0;
12980 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12982 unsigned WrapperKind = X86ISD::Wrapper;
12983 if (model == TLSModel::LocalExec) {
12984 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12985 } else if (model == TLSModel::InitialExec) {
12987 OperandFlags = X86II::MO_GOTTPOFF;
12988 WrapperKind = X86ISD::WrapperRIP;
12990 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12993 llvm_unreachable("Unexpected model");
12996 // emit "addl x@ntpoff,%eax" (local exec)
12997 // or "addl x@indntpoff,%eax" (initial exec)
12998 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13000 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13001 GA->getOffset(), OperandFlags);
13002 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13004 if (model == TLSModel::InitialExec) {
13005 if (isPIC && !is64Bit) {
13006 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13007 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13011 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13012 MachinePointerInfo::getGOT(), false, false, false, 0);
13015 // The address of the thread local variable is the add of the thread
13016 // pointer with the offset of the variable.
13017 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13021 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13023 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13024 const GlobalValue *GV = GA->getGlobal();
13026 if (Subtarget->isTargetELF()) {
13027 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13030 case TLSModel::GeneralDynamic:
13031 if (Subtarget->is64Bit())
13032 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13033 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13034 case TLSModel::LocalDynamic:
13035 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13036 Subtarget->is64Bit());
13037 case TLSModel::InitialExec:
13038 case TLSModel::LocalExec:
13039 return LowerToTLSExecModel(
13040 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13041 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13043 llvm_unreachable("Unknown TLS model.");
13046 if (Subtarget->isTargetDarwin()) {
13047 // Darwin only has one model of TLS. Lower to that.
13048 unsigned char OpFlag = 0;
13049 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13050 X86ISD::WrapperRIP : X86ISD::Wrapper;
13052 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13053 // global base reg.
13054 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13055 !Subtarget->is64Bit();
13057 OpFlag = X86II::MO_TLVP_PIC_BASE;
13059 OpFlag = X86II::MO_TLVP;
13061 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13062 GA->getValueType(0),
13063 GA->getOffset(), OpFlag);
13064 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13066 // With PIC32, the address is actually $g + Offset.
13068 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13069 DAG.getNode(X86ISD::GlobalBaseReg,
13070 SDLoc(), getPointerTy()),
13073 // Lowering the machine isd will make sure everything is in the right
13075 SDValue Chain = DAG.getEntryNode();
13076 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13077 SDValue Args[] = { Chain, Offset };
13078 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13080 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13081 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13082 MFI->setAdjustsStack(true);
13084 // And our return value (tls address) is in the standard call return value
13086 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13087 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13088 Chain.getValue(1));
13091 if (Subtarget->isTargetKnownWindowsMSVC() ||
13092 Subtarget->isTargetWindowsGNU()) {
13093 // Just use the implicit TLS architecture
13094 // Need to generate someting similar to:
13095 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13097 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13098 // mov rcx, qword [rdx+rcx*8]
13099 // mov eax, .tls$:tlsvar
13100 // [rax+rcx] contains the address
13101 // Windows 64bit: gs:0x58
13102 // Windows 32bit: fs:__tls_array
13105 SDValue Chain = DAG.getEntryNode();
13107 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13108 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13109 // use its literal value of 0x2C.
13110 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13111 ? Type::getInt8PtrTy(*DAG.getContext(),
13113 : Type::getInt32PtrTy(*DAG.getContext(),
13117 Subtarget->is64Bit()
13118 ? DAG.getIntPtrConstant(0x58)
13119 : (Subtarget->isTargetWindowsGNU()
13120 ? DAG.getIntPtrConstant(0x2C)
13121 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13123 SDValue ThreadPointer =
13124 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13125 MachinePointerInfo(Ptr), false, false, false, 0);
13127 // Load the _tls_index variable
13128 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13129 if (Subtarget->is64Bit())
13130 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13131 IDX, MachinePointerInfo(), MVT::i32,
13132 false, false, false, 0);
13134 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13135 false, false, false, 0);
13137 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13139 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13141 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13142 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13143 false, false, false, 0);
13145 // Get the offset of start of .tls section
13146 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13147 GA->getValueType(0),
13148 GA->getOffset(), X86II::MO_SECREL);
13149 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13151 // The address of the thread local variable is the add of the thread
13152 // pointer with the offset of the variable.
13153 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13156 llvm_unreachable("TLS not implemented for this target.");
13159 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13160 /// and take a 2 x i32 value to shift plus a shift amount.
13161 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13162 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13163 MVT VT = Op.getSimpleValueType();
13164 unsigned VTBits = VT.getSizeInBits();
13166 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13167 SDValue ShOpLo = Op.getOperand(0);
13168 SDValue ShOpHi = Op.getOperand(1);
13169 SDValue ShAmt = Op.getOperand(2);
13170 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13171 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13173 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13174 DAG.getConstant(VTBits - 1, MVT::i8));
13175 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13176 DAG.getConstant(VTBits - 1, MVT::i8))
13177 : DAG.getConstant(0, VT);
13179 SDValue Tmp2, Tmp3;
13180 if (Op.getOpcode() == ISD::SHL_PARTS) {
13181 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13182 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13184 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13185 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13188 // If the shift amount is larger or equal than the width of a part we can't
13189 // rely on the results of shld/shrd. Insert a test and select the appropriate
13190 // values for large shift amounts.
13191 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13192 DAG.getConstant(VTBits, MVT::i8));
13193 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13194 AndNode, DAG.getConstant(0, MVT::i8));
13197 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13198 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13199 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13201 if (Op.getOpcode() == ISD::SHL_PARTS) {
13202 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13203 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13205 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13206 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13209 SDValue Ops[2] = { Lo, Hi };
13210 return DAG.getMergeValues(Ops, dl);
13213 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13214 SelectionDAG &DAG) const {
13215 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13218 if (SrcVT.isVector()) {
13219 if (SrcVT.getVectorElementType() == MVT::i1) {
13220 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13221 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13222 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13223 Op.getOperand(0)));
13228 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13229 "Unknown SINT_TO_FP to lower!");
13231 // These are really Legal; return the operand so the caller accepts it as
13233 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13235 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13236 Subtarget->is64Bit()) {
13240 unsigned Size = SrcVT.getSizeInBits()/8;
13241 MachineFunction &MF = DAG.getMachineFunction();
13242 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13243 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13244 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13246 MachinePointerInfo::getFixedStack(SSFI),
13248 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13251 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13253 SelectionDAG &DAG) const {
13257 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13259 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13261 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13263 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13265 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13266 MachineMemOperand *MMO;
13268 int SSFI = FI->getIndex();
13270 DAG.getMachineFunction()
13271 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13272 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13274 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13275 StackSlot = StackSlot.getOperand(1);
13277 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13278 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13280 Tys, Ops, SrcVT, MMO);
13283 Chain = Result.getValue(1);
13284 SDValue InFlag = Result.getValue(2);
13286 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13287 // shouldn't be necessary except that RFP cannot be live across
13288 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13289 MachineFunction &MF = DAG.getMachineFunction();
13290 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13291 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13292 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13293 Tys = DAG.getVTList(MVT::Other);
13295 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13297 MachineMemOperand *MMO =
13298 DAG.getMachineFunction()
13299 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13300 MachineMemOperand::MOStore, SSFISize, SSFISize);
13302 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13303 Ops, Op.getValueType(), MMO);
13304 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13305 MachinePointerInfo::getFixedStack(SSFI),
13306 false, false, false, 0);
13312 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13313 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13314 SelectionDAG &DAG) const {
13315 // This algorithm is not obvious. Here it is what we're trying to output:
13318 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13319 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13321 haddpd %xmm0, %xmm0
13323 pshufd $0x4e, %xmm0, %xmm1
13329 LLVMContext *Context = DAG.getContext();
13331 // Build some magic constants.
13332 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13333 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13334 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13336 SmallVector<Constant*,2> CV1;
13338 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13339 APInt(64, 0x4330000000000000ULL))));
13341 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13342 APInt(64, 0x4530000000000000ULL))));
13343 Constant *C1 = ConstantVector::get(CV1);
13344 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13346 // Load the 64-bit value into an XMM register.
13347 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13349 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13350 MachinePointerInfo::getConstantPool(),
13351 false, false, false, 16);
13352 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13353 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13356 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13357 MachinePointerInfo::getConstantPool(),
13358 false, false, false, 16);
13359 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13360 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13363 if (Subtarget->hasSSE3()) {
13364 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13365 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13367 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13368 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13370 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13371 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13375 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13376 DAG.getIntPtrConstant(0));
13379 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13380 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13381 SelectionDAG &DAG) const {
13383 // FP constant to bias correct the final result.
13384 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13387 // Load the 32-bit value into an XMM register.
13388 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13391 // Zero out the upper parts of the register.
13392 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13394 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13395 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13396 DAG.getIntPtrConstant(0));
13398 // Or the load with the bias.
13399 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13400 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13401 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13402 MVT::v2f64, Load)),
13403 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13404 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13405 MVT::v2f64, Bias)));
13406 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13407 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13408 DAG.getIntPtrConstant(0));
13410 // Subtract the bias.
13411 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13413 // Handle final rounding.
13414 EVT DestVT = Op.getValueType();
13416 if (DestVT.bitsLT(MVT::f64))
13417 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13418 DAG.getIntPtrConstant(0));
13419 if (DestVT.bitsGT(MVT::f64))
13420 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13422 // Handle final rounding.
13426 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13427 const X86Subtarget &Subtarget) {
13428 // The algorithm is the following:
13429 // #ifdef __SSE4_1__
13430 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13431 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13432 // (uint4) 0x53000000, 0xaa);
13434 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13435 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13437 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13438 // return (float4) lo + fhi;
13441 SDValue V = Op->getOperand(0);
13442 EVT VecIntVT = V.getValueType();
13443 bool Is128 = VecIntVT == MVT::v4i32;
13444 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13445 unsigned NumElts = VecIntVT.getVectorNumElements();
13446 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13447 "Unsupported custom type");
13448 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13450 // In the #idef/#else code, we have in common:
13451 // - The vector of constants:
13457 // Create the splat vector for 0x4b000000.
13458 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13459 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13460 CstLow, CstLow, CstLow, CstLow};
13461 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13462 makeArrayRef(&CstLowArray[0], NumElts));
13463 // Create the splat vector for 0x53000000.
13464 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13465 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13466 CstHigh, CstHigh, CstHigh, CstHigh};
13467 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13468 makeArrayRef(&CstHighArray[0], NumElts));
13470 // Create the right shift.
13471 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13472 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13473 CstShift, CstShift, CstShift, CstShift};
13474 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13475 makeArrayRef(&CstShiftArray[0], NumElts));
13476 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13479 if (Subtarget.hasSSE41()) {
13480 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13481 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13482 SDValue VecCstLowBitcast =
13483 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13484 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13485 // Low will be bitcasted right away, so do not bother bitcasting back to its
13487 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13488 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13489 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13490 // (uint4) 0x53000000, 0xaa);
13491 SDValue VecCstHighBitcast =
13492 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13493 SDValue VecShiftBitcast =
13494 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13495 // High will be bitcasted right away, so do not bother bitcasting back to
13496 // its original type.
13497 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13498 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13500 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13501 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13502 CstMask, CstMask, CstMask);
13503 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13504 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13505 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13507 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13508 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13511 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13512 SDValue CstFAdd = DAG.getConstantFP(
13513 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13514 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13515 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13516 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13517 makeArrayRef(&CstFAddArray[0], NumElts));
13519 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13520 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13522 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13523 // return (float4) lo + fhi;
13524 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13525 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13528 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13529 SelectionDAG &DAG) const {
13530 SDValue N0 = Op.getOperand(0);
13531 MVT SVT = N0.getSimpleValueType();
13534 switch (SVT.SimpleTy) {
13536 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13541 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13542 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13543 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13547 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13549 llvm_unreachable(nullptr);
13552 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13553 SelectionDAG &DAG) const {
13554 SDValue N0 = Op.getOperand(0);
13557 if (Op.getValueType().isVector())
13558 return lowerUINT_TO_FP_vec(Op, DAG);
13560 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13561 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13562 // the optimization here.
13563 if (DAG.SignBitIsZero(N0))
13564 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13566 MVT SrcVT = N0.getSimpleValueType();
13567 MVT DstVT = Op.getSimpleValueType();
13568 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13569 return LowerUINT_TO_FP_i64(Op, DAG);
13570 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13571 return LowerUINT_TO_FP_i32(Op, DAG);
13572 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13575 // Make a 64-bit buffer, and use it to build an FILD.
13576 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13577 if (SrcVT == MVT::i32) {
13578 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13579 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13580 getPointerTy(), StackSlot, WordOff);
13581 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13582 StackSlot, MachinePointerInfo(),
13584 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13585 OffsetSlot, MachinePointerInfo(),
13587 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13591 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13592 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13593 StackSlot, MachinePointerInfo(),
13595 // For i64 source, we need to add the appropriate power of 2 if the input
13596 // was negative. This is the same as the optimization in
13597 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13598 // we must be careful to do the computation in x87 extended precision, not
13599 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13600 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13601 MachineMemOperand *MMO =
13602 DAG.getMachineFunction()
13603 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13604 MachineMemOperand::MOLoad, 8, 8);
13606 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13607 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13608 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13611 APInt FF(32, 0x5F800000ULL);
13613 // Check whether the sign bit is set.
13614 SDValue SignSet = DAG.getSetCC(dl,
13615 getSetCCResultType(*DAG.getContext(), MVT::i64),
13616 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13619 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13620 SDValue FudgePtr = DAG.getConstantPool(
13621 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13624 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13625 SDValue Zero = DAG.getIntPtrConstant(0);
13626 SDValue Four = DAG.getIntPtrConstant(4);
13627 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13629 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13631 // Load the value out, extending it from f32 to f80.
13632 // FIXME: Avoid the extend by constructing the right constant pool?
13633 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13634 FudgePtr, MachinePointerInfo::getConstantPool(),
13635 MVT::f32, false, false, false, 4);
13636 // Extend everything to 80 bits to force it to be done on x87.
13637 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13638 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13641 std::pair<SDValue,SDValue>
13642 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13643 bool IsSigned, bool IsReplace) const {
13646 EVT DstTy = Op.getValueType();
13648 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13649 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13653 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13654 DstTy.getSimpleVT() >= MVT::i16 &&
13655 "Unknown FP_TO_INT to lower!");
13657 // These are really Legal.
13658 if (DstTy == MVT::i32 &&
13659 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13660 return std::make_pair(SDValue(), SDValue());
13661 if (Subtarget->is64Bit() &&
13662 DstTy == MVT::i64 &&
13663 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13664 return std::make_pair(SDValue(), SDValue());
13666 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13667 // stack slot, or into the FTOL runtime function.
13668 MachineFunction &MF = DAG.getMachineFunction();
13669 unsigned MemSize = DstTy.getSizeInBits()/8;
13670 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13671 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13674 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13675 Opc = X86ISD::WIN_FTOL;
13677 switch (DstTy.getSimpleVT().SimpleTy) {
13678 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13679 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13680 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13681 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13684 SDValue Chain = DAG.getEntryNode();
13685 SDValue Value = Op.getOperand(0);
13686 EVT TheVT = Op.getOperand(0).getValueType();
13687 // FIXME This causes a redundant load/store if the SSE-class value is already
13688 // in memory, such as if it is on the callstack.
13689 if (isScalarFPTypeInSSEReg(TheVT)) {
13690 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13691 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13692 MachinePointerInfo::getFixedStack(SSFI),
13694 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13696 Chain, StackSlot, DAG.getValueType(TheVT)
13699 MachineMemOperand *MMO =
13700 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13701 MachineMemOperand::MOLoad, MemSize, MemSize);
13702 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13703 Chain = Value.getValue(1);
13704 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13705 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13708 MachineMemOperand *MMO =
13709 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13710 MachineMemOperand::MOStore, MemSize, MemSize);
13712 if (Opc != X86ISD::WIN_FTOL) {
13713 // Build the FP_TO_INT*_IN_MEM
13714 SDValue Ops[] = { Chain, Value, StackSlot };
13715 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13717 return std::make_pair(FIST, StackSlot);
13719 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13720 DAG.getVTList(MVT::Other, MVT::Glue),
13722 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13723 MVT::i32, ftol.getValue(1));
13724 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13725 MVT::i32, eax.getValue(2));
13726 SDValue Ops[] = { eax, edx };
13727 SDValue pair = IsReplace
13728 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13729 : DAG.getMergeValues(Ops, DL);
13730 return std::make_pair(pair, SDValue());
13734 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13735 const X86Subtarget *Subtarget) {
13736 MVT VT = Op->getSimpleValueType(0);
13737 SDValue In = Op->getOperand(0);
13738 MVT InVT = In.getSimpleValueType();
13741 // Optimize vectors in AVX mode:
13744 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13745 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13746 // Concat upper and lower parts.
13749 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13750 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13751 // Concat upper and lower parts.
13754 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13755 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13756 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13759 if (Subtarget->hasInt256())
13760 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13762 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13763 SDValue Undef = DAG.getUNDEF(InVT);
13764 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13765 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13766 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13768 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13769 VT.getVectorNumElements()/2);
13771 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13772 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13774 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13777 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13778 SelectionDAG &DAG) {
13779 MVT VT = Op->getSimpleValueType(0);
13780 SDValue In = Op->getOperand(0);
13781 MVT InVT = In.getSimpleValueType();
13783 unsigned int NumElts = VT.getVectorNumElements();
13784 if (NumElts != 8 && NumElts != 16)
13787 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13788 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13790 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13791 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13792 // Now we have only mask extension
13793 assert(InVT.getVectorElementType() == MVT::i1);
13794 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13795 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13796 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13797 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13798 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13799 MachinePointerInfo::getConstantPool(),
13800 false, false, false, Alignment);
13802 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13803 if (VT.is512BitVector())
13805 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13808 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13809 SelectionDAG &DAG) {
13810 if (Subtarget->hasFp256()) {
13811 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13819 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13820 SelectionDAG &DAG) {
13822 MVT VT = Op.getSimpleValueType();
13823 SDValue In = Op.getOperand(0);
13824 MVT SVT = In.getSimpleValueType();
13826 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13827 return LowerZERO_EXTEND_AVX512(Op, DAG);
13829 if (Subtarget->hasFp256()) {
13830 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13835 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13836 VT.getVectorNumElements() != SVT.getVectorNumElements());
13840 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13842 MVT VT = Op.getSimpleValueType();
13843 SDValue In = Op.getOperand(0);
13844 MVT InVT = In.getSimpleValueType();
13846 if (VT == MVT::i1) {
13847 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13848 "Invalid scalar TRUNCATE operation");
13849 if (InVT.getSizeInBits() >= 32)
13851 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13852 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13854 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13855 "Invalid TRUNCATE operation");
13857 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13858 if (VT.getVectorElementType().getSizeInBits() >=8)
13859 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13861 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13862 unsigned NumElts = InVT.getVectorNumElements();
13863 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13864 if (InVT.getSizeInBits() < 512) {
13865 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13866 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13870 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13871 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13872 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13873 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13874 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13875 MachinePointerInfo::getConstantPool(),
13876 false, false, false, Alignment);
13877 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13878 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13879 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13882 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13883 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13884 if (Subtarget->hasInt256()) {
13885 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13886 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13887 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13889 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13890 DAG.getIntPtrConstant(0));
13893 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13894 DAG.getIntPtrConstant(0));
13895 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13896 DAG.getIntPtrConstant(2));
13897 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13898 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13899 static const int ShufMask[] = {0, 2, 4, 6};
13900 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13903 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13904 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13905 if (Subtarget->hasInt256()) {
13906 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13908 SmallVector<SDValue,32> pshufbMask;
13909 for (unsigned i = 0; i < 2; ++i) {
13910 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13911 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13912 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13913 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13914 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13915 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13916 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13917 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13918 for (unsigned j = 0; j < 8; ++j)
13919 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13921 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13922 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13923 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13925 static const int ShufMask[] = {0, 2, -1, -1};
13926 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13928 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13929 DAG.getIntPtrConstant(0));
13930 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13933 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13934 DAG.getIntPtrConstant(0));
13936 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13937 DAG.getIntPtrConstant(4));
13939 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13940 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13942 // The PSHUFB mask:
13943 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13944 -1, -1, -1, -1, -1, -1, -1, -1};
13946 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13947 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13948 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13950 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13951 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13953 // The MOVLHPS Mask:
13954 static const int ShufMask2[] = {0, 1, 4, 5};
13955 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13956 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13959 // Handle truncation of V256 to V128 using shuffles.
13960 if (!VT.is128BitVector() || !InVT.is256BitVector())
13963 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13965 unsigned NumElems = VT.getVectorNumElements();
13966 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13968 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13969 // Prepare truncation shuffle mask
13970 for (unsigned i = 0; i != NumElems; ++i)
13971 MaskVec[i] = i * 2;
13972 SDValue V = DAG.getVectorShuffle(NVT, DL,
13973 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13974 DAG.getUNDEF(NVT), &MaskVec[0]);
13975 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13976 DAG.getIntPtrConstant(0));
13979 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13980 SelectionDAG &DAG) const {
13981 assert(!Op.getSimpleValueType().isVector());
13983 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13984 /*IsSigned=*/ true, /*IsReplace=*/ false);
13985 SDValue FIST = Vals.first, StackSlot = Vals.second;
13986 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13987 if (!FIST.getNode()) return Op;
13989 if (StackSlot.getNode())
13990 // Load the result.
13991 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13992 FIST, StackSlot, MachinePointerInfo(),
13993 false, false, false, 0);
13995 // The node is the result.
13999 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14000 SelectionDAG &DAG) const {
14001 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14002 /*IsSigned=*/ false, /*IsReplace=*/ false);
14003 SDValue FIST = Vals.first, StackSlot = Vals.second;
14004 assert(FIST.getNode() && "Unexpected failure");
14006 if (StackSlot.getNode())
14007 // Load the result.
14008 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14009 FIST, StackSlot, MachinePointerInfo(),
14010 false, false, false, 0);
14012 // The node is the result.
14016 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14018 MVT VT = Op.getSimpleValueType();
14019 SDValue In = Op.getOperand(0);
14020 MVT SVT = In.getSimpleValueType();
14022 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14024 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14025 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14026 In, DAG.getUNDEF(SVT)));
14029 /// The only differences between FABS and FNEG are the mask and the logic op.
14030 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14031 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14032 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14033 "Wrong opcode for lowering FABS or FNEG.");
14035 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14037 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14038 // into an FNABS. We'll lower the FABS after that if it is still in use.
14040 for (SDNode *User : Op->uses())
14041 if (User->getOpcode() == ISD::FNEG)
14044 SDValue Op0 = Op.getOperand(0);
14045 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14048 MVT VT = Op.getSimpleValueType();
14049 // Assume scalar op for initialization; update for vector if needed.
14050 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14051 // generate a 16-byte vector constant and logic op even for the scalar case.
14052 // Using a 16-byte mask allows folding the load of the mask with
14053 // the logic op, so it can save (~4 bytes) on code size.
14055 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14056 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14057 // decide if we should generate a 16-byte constant mask when we only need 4 or
14058 // 8 bytes for the scalar case.
14059 if (VT.isVector()) {
14060 EltVT = VT.getVectorElementType();
14061 NumElts = VT.getVectorNumElements();
14064 unsigned EltBits = EltVT.getSizeInBits();
14065 LLVMContext *Context = DAG.getContext();
14066 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14068 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14069 Constant *C = ConstantInt::get(*Context, MaskElt);
14070 C = ConstantVector::getSplat(NumElts, C);
14071 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14072 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14073 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14074 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14075 MachinePointerInfo::getConstantPool(),
14076 false, false, false, Alignment);
14078 if (VT.isVector()) {
14079 // For a vector, cast operands to a vector type, perform the logic op,
14080 // and cast the result back to the original value type.
14081 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14082 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14083 SDValue Operand = IsFNABS ?
14084 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14085 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14086 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14087 return DAG.getNode(ISD::BITCAST, dl, VT,
14088 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14091 // If not vector, then scalar.
14092 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14093 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14094 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14097 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14098 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14099 LLVMContext *Context = DAG.getContext();
14100 SDValue Op0 = Op.getOperand(0);
14101 SDValue Op1 = Op.getOperand(1);
14103 MVT VT = Op.getSimpleValueType();
14104 MVT SrcVT = Op1.getSimpleValueType();
14106 // If second operand is smaller, extend it first.
14107 if (SrcVT.bitsLT(VT)) {
14108 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14111 // And if it is bigger, shrink it first.
14112 if (SrcVT.bitsGT(VT)) {
14113 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14117 // At this point the operands and the result should have the same
14118 // type, and that won't be f80 since that is not custom lowered.
14120 // First get the sign bit of second operand.
14121 SmallVector<Constant*,4> CV;
14122 if (SrcVT == MVT::f64) {
14123 const fltSemantics &Sem = APFloat::IEEEdouble;
14124 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14125 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14127 const fltSemantics &Sem = APFloat::IEEEsingle;
14128 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14129 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14130 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14131 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14133 Constant *C = ConstantVector::get(CV);
14134 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14135 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14136 MachinePointerInfo::getConstantPool(),
14137 false, false, false, 16);
14138 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14140 // Shift sign bit right or left if the two operands have different types.
14141 if (SrcVT.bitsGT(VT)) {
14142 // Op0 is MVT::f32, Op1 is MVT::f64.
14143 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14144 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14145 DAG.getConstant(32, MVT::i32));
14146 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14147 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14148 DAG.getIntPtrConstant(0));
14151 // Clear first operand sign bit.
14153 if (VT == MVT::f64) {
14154 const fltSemantics &Sem = APFloat::IEEEdouble;
14155 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14156 APInt(64, ~(1ULL << 63)))));
14157 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14159 const fltSemantics &Sem = APFloat::IEEEsingle;
14160 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14161 APInt(32, ~(1U << 31)))));
14162 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14163 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14164 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14166 C = ConstantVector::get(CV);
14167 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14168 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14169 MachinePointerInfo::getConstantPool(),
14170 false, false, false, 16);
14171 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14173 // Or the value with the sign bit.
14174 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14177 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14178 SDValue N0 = Op.getOperand(0);
14180 MVT VT = Op.getSimpleValueType();
14182 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14183 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14184 DAG.getConstant(1, VT));
14185 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14188 // Check whether an OR'd tree is PTEST-able.
14189 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14190 SelectionDAG &DAG) {
14191 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14193 if (!Subtarget->hasSSE41())
14196 if (!Op->hasOneUse())
14199 SDNode *N = Op.getNode();
14202 SmallVector<SDValue, 8> Opnds;
14203 DenseMap<SDValue, unsigned> VecInMap;
14204 SmallVector<SDValue, 8> VecIns;
14205 EVT VT = MVT::Other;
14207 // Recognize a special case where a vector is casted into wide integer to
14209 Opnds.push_back(N->getOperand(0));
14210 Opnds.push_back(N->getOperand(1));
14212 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14213 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14214 // BFS traverse all OR'd operands.
14215 if (I->getOpcode() == ISD::OR) {
14216 Opnds.push_back(I->getOperand(0));
14217 Opnds.push_back(I->getOperand(1));
14218 // Re-evaluate the number of nodes to be traversed.
14219 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14223 // Quit if a non-EXTRACT_VECTOR_ELT
14224 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14227 // Quit if without a constant index.
14228 SDValue Idx = I->getOperand(1);
14229 if (!isa<ConstantSDNode>(Idx))
14232 SDValue ExtractedFromVec = I->getOperand(0);
14233 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14234 if (M == VecInMap.end()) {
14235 VT = ExtractedFromVec.getValueType();
14236 // Quit if not 128/256-bit vector.
14237 if (!VT.is128BitVector() && !VT.is256BitVector())
14239 // Quit if not the same type.
14240 if (VecInMap.begin() != VecInMap.end() &&
14241 VT != VecInMap.begin()->first.getValueType())
14243 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14244 VecIns.push_back(ExtractedFromVec);
14246 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14249 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14250 "Not extracted from 128-/256-bit vector.");
14252 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14254 for (DenseMap<SDValue, unsigned>::const_iterator
14255 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14256 // Quit if not all elements are used.
14257 if (I->second != FullMask)
14261 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14263 // Cast all vectors into TestVT for PTEST.
14264 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14265 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14267 // If more than one full vectors are evaluated, OR them first before PTEST.
14268 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14269 // Each iteration will OR 2 nodes and append the result until there is only
14270 // 1 node left, i.e. the final OR'd value of all vectors.
14271 SDValue LHS = VecIns[Slot];
14272 SDValue RHS = VecIns[Slot + 1];
14273 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14276 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14277 VecIns.back(), VecIns.back());
14280 /// \brief return true if \c Op has a use that doesn't just read flags.
14281 static bool hasNonFlagsUse(SDValue Op) {
14282 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14284 SDNode *User = *UI;
14285 unsigned UOpNo = UI.getOperandNo();
14286 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14287 // Look pass truncate.
14288 UOpNo = User->use_begin().getOperandNo();
14289 User = *User->use_begin();
14292 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14293 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14299 /// Emit nodes that will be selected as "test Op0,Op0", or something
14301 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14302 SelectionDAG &DAG) const {
14303 if (Op.getValueType() == MVT::i1)
14304 // KORTEST instruction should be selected
14305 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14306 DAG.getConstant(0, Op.getValueType()));
14308 // CF and OF aren't always set the way we want. Determine which
14309 // of these we need.
14310 bool NeedCF = false;
14311 bool NeedOF = false;
14314 case X86::COND_A: case X86::COND_AE:
14315 case X86::COND_B: case X86::COND_BE:
14318 case X86::COND_G: case X86::COND_GE:
14319 case X86::COND_L: case X86::COND_LE:
14320 case X86::COND_O: case X86::COND_NO: {
14321 // Check if we really need to set the
14322 // Overflow flag. If NoSignedWrap is present
14323 // that is not actually needed.
14324 switch (Op->getOpcode()) {
14329 const BinaryWithFlagsSDNode *BinNode =
14330 cast<BinaryWithFlagsSDNode>(Op.getNode());
14331 if (BinNode->hasNoSignedWrap())
14341 // See if we can use the EFLAGS value from the operand instead of
14342 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14343 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14344 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14345 // Emit a CMP with 0, which is the TEST pattern.
14346 //if (Op.getValueType() == MVT::i1)
14347 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14348 // DAG.getConstant(0, MVT::i1));
14349 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14350 DAG.getConstant(0, Op.getValueType()));
14352 unsigned Opcode = 0;
14353 unsigned NumOperands = 0;
14355 // Truncate operations may prevent the merge of the SETCC instruction
14356 // and the arithmetic instruction before it. Attempt to truncate the operands
14357 // of the arithmetic instruction and use a reduced bit-width instruction.
14358 bool NeedTruncation = false;
14359 SDValue ArithOp = Op;
14360 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14361 SDValue Arith = Op->getOperand(0);
14362 // Both the trunc and the arithmetic op need to have one user each.
14363 if (Arith->hasOneUse())
14364 switch (Arith.getOpcode()) {
14371 NeedTruncation = true;
14377 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14378 // which may be the result of a CAST. We use the variable 'Op', which is the
14379 // non-casted variable when we check for possible users.
14380 switch (ArithOp.getOpcode()) {
14382 // Due to an isel shortcoming, be conservative if this add is likely to be
14383 // selected as part of a load-modify-store instruction. When the root node
14384 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14385 // uses of other nodes in the match, such as the ADD in this case. This
14386 // leads to the ADD being left around and reselected, with the result being
14387 // two adds in the output. Alas, even if none our users are stores, that
14388 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14389 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14390 // climbing the DAG back to the root, and it doesn't seem to be worth the
14392 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14393 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14394 if (UI->getOpcode() != ISD::CopyToReg &&
14395 UI->getOpcode() != ISD::SETCC &&
14396 UI->getOpcode() != ISD::STORE)
14399 if (ConstantSDNode *C =
14400 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14401 // An add of one will be selected as an INC.
14402 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14403 Opcode = X86ISD::INC;
14408 // An add of negative one (subtract of one) will be selected as a DEC.
14409 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14410 Opcode = X86ISD::DEC;
14416 // Otherwise use a regular EFLAGS-setting add.
14417 Opcode = X86ISD::ADD;
14422 // If we have a constant logical shift that's only used in a comparison
14423 // against zero turn it into an equivalent AND. This allows turning it into
14424 // a TEST instruction later.
14425 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14426 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14427 EVT VT = Op.getValueType();
14428 unsigned BitWidth = VT.getSizeInBits();
14429 unsigned ShAmt = Op->getConstantOperandVal(1);
14430 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14432 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14433 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14434 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14435 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14437 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14438 DAG.getConstant(Mask, VT));
14439 DAG.ReplaceAllUsesWith(Op, New);
14445 // If the primary and result isn't used, don't bother using X86ISD::AND,
14446 // because a TEST instruction will be better.
14447 if (!hasNonFlagsUse(Op))
14453 // Due to the ISEL shortcoming noted above, be conservative if this op is
14454 // likely to be selected as part of a load-modify-store instruction.
14455 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14456 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14457 if (UI->getOpcode() == ISD::STORE)
14460 // Otherwise use a regular EFLAGS-setting instruction.
14461 switch (ArithOp.getOpcode()) {
14462 default: llvm_unreachable("unexpected operator!");
14463 case ISD::SUB: Opcode = X86ISD::SUB; break;
14464 case ISD::XOR: Opcode = X86ISD::XOR; break;
14465 case ISD::AND: Opcode = X86ISD::AND; break;
14467 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14468 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14469 if (EFLAGS.getNode())
14472 Opcode = X86ISD::OR;
14486 return SDValue(Op.getNode(), 1);
14492 // If we found that truncation is beneficial, perform the truncation and
14494 if (NeedTruncation) {
14495 EVT VT = Op.getValueType();
14496 SDValue WideVal = Op->getOperand(0);
14497 EVT WideVT = WideVal.getValueType();
14498 unsigned ConvertedOp = 0;
14499 // Use a target machine opcode to prevent further DAGCombine
14500 // optimizations that may separate the arithmetic operations
14501 // from the setcc node.
14502 switch (WideVal.getOpcode()) {
14504 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14505 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14506 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14507 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14508 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14512 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14513 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14514 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14515 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14516 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14522 // Emit a CMP with 0, which is the TEST pattern.
14523 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14524 DAG.getConstant(0, Op.getValueType()));
14526 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14527 SmallVector<SDValue, 4> Ops;
14528 for (unsigned i = 0; i != NumOperands; ++i)
14529 Ops.push_back(Op.getOperand(i));
14531 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14532 DAG.ReplaceAllUsesWith(Op, New);
14533 return SDValue(New.getNode(), 1);
14536 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14538 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14539 SDLoc dl, SelectionDAG &DAG) const {
14540 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14541 if (C->getAPIntValue() == 0)
14542 return EmitTest(Op0, X86CC, dl, DAG);
14544 if (Op0.getValueType() == MVT::i1)
14545 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14548 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14549 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14550 // Do the comparison at i32 if it's smaller, besides the Atom case.
14551 // This avoids subregister aliasing issues. Keep the smaller reference
14552 // if we're optimizing for size, however, as that'll allow better folding
14553 // of memory operations.
14554 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14555 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14556 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14557 !Subtarget->isAtom()) {
14558 unsigned ExtendOp =
14559 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14560 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14561 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14563 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14564 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14565 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14567 return SDValue(Sub.getNode(), 1);
14569 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14572 /// Convert a comparison if required by the subtarget.
14573 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14574 SelectionDAG &DAG) const {
14575 // If the subtarget does not support the FUCOMI instruction, floating-point
14576 // comparisons have to be converted.
14577 if (Subtarget->hasCMov() ||
14578 Cmp.getOpcode() != X86ISD::CMP ||
14579 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14580 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14583 // The instruction selector will select an FUCOM instruction instead of
14584 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14585 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14586 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14588 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14589 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14590 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14591 DAG.getConstant(8, MVT::i8));
14592 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14593 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14596 /// The minimum architected relative accuracy is 2^-12. We need one
14597 /// Newton-Raphson step to have a good float result (24 bits of precision).
14598 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14599 DAGCombinerInfo &DCI,
14600 unsigned &RefinementSteps,
14601 bool &UseOneConstNR) const {
14602 // FIXME: We should use instruction latency models to calculate the cost of
14603 // each potential sequence, but this is very hard to do reliably because
14604 // at least Intel's Core* chips have variable timing based on the number of
14605 // significant digits in the divisor and/or sqrt operand.
14606 if (!Subtarget->useSqrtEst())
14609 EVT VT = Op.getValueType();
14611 // SSE1 has rsqrtss and rsqrtps.
14612 // TODO: Add support for AVX512 (v16f32).
14613 // It is likely not profitable to do this for f64 because a double-precision
14614 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14615 // instructions: convert to single, rsqrtss, convert back to double, refine
14616 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14617 // along with FMA, this could be a throughput win.
14618 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14619 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14620 RefinementSteps = 1;
14621 UseOneConstNR = false;
14622 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14627 /// The minimum architected relative accuracy is 2^-12. We need one
14628 /// Newton-Raphson step to have a good float result (24 bits of precision).
14629 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14630 DAGCombinerInfo &DCI,
14631 unsigned &RefinementSteps) const {
14632 // FIXME: We should use instruction latency models to calculate the cost of
14633 // each potential sequence, but this is very hard to do reliably because
14634 // at least Intel's Core* chips have variable timing based on the number of
14635 // significant digits in the divisor.
14636 if (!Subtarget->useReciprocalEst())
14639 EVT VT = Op.getValueType();
14641 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14642 // TODO: Add support for AVX512 (v16f32).
14643 // It is likely not profitable to do this for f64 because a double-precision
14644 // reciprocal estimate with refinement on x86 prior to FMA requires
14645 // 15 instructions: convert to single, rcpss, convert back to double, refine
14646 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14647 // along with FMA, this could be a throughput win.
14648 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14649 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14650 RefinementSteps = ReciprocalEstimateRefinementSteps;
14651 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14656 static bool isAllOnes(SDValue V) {
14657 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14658 return C && C->isAllOnesValue();
14661 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14662 /// if it's possible.
14663 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14664 SDLoc dl, SelectionDAG &DAG) const {
14665 SDValue Op0 = And.getOperand(0);
14666 SDValue Op1 = And.getOperand(1);
14667 if (Op0.getOpcode() == ISD::TRUNCATE)
14668 Op0 = Op0.getOperand(0);
14669 if (Op1.getOpcode() == ISD::TRUNCATE)
14670 Op1 = Op1.getOperand(0);
14673 if (Op1.getOpcode() == ISD::SHL)
14674 std::swap(Op0, Op1);
14675 if (Op0.getOpcode() == ISD::SHL) {
14676 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14677 if (And00C->getZExtValue() == 1) {
14678 // If we looked past a truncate, check that it's only truncating away
14680 unsigned BitWidth = Op0.getValueSizeInBits();
14681 unsigned AndBitWidth = And.getValueSizeInBits();
14682 if (BitWidth > AndBitWidth) {
14684 DAG.computeKnownBits(Op0, Zeros, Ones);
14685 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14689 RHS = Op0.getOperand(1);
14691 } else if (Op1.getOpcode() == ISD::Constant) {
14692 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14693 uint64_t AndRHSVal = AndRHS->getZExtValue();
14694 SDValue AndLHS = Op0;
14696 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14697 LHS = AndLHS.getOperand(0);
14698 RHS = AndLHS.getOperand(1);
14701 // Use BT if the immediate can't be encoded in a TEST instruction.
14702 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14704 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14708 if (LHS.getNode()) {
14709 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14710 // instruction. Since the shift amount is in-range-or-undefined, we know
14711 // that doing a bittest on the i32 value is ok. We extend to i32 because
14712 // the encoding for the i16 version is larger than the i32 version.
14713 // Also promote i16 to i32 for performance / code size reason.
14714 if (LHS.getValueType() == MVT::i8 ||
14715 LHS.getValueType() == MVT::i16)
14716 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14718 // If the operand types disagree, extend the shift amount to match. Since
14719 // BT ignores high bits (like shifts) we can use anyextend.
14720 if (LHS.getValueType() != RHS.getValueType())
14721 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14723 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14724 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14725 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14726 DAG.getConstant(Cond, MVT::i8), BT);
14732 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14734 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14739 // SSE Condition code mapping:
14748 switch (SetCCOpcode) {
14749 default: llvm_unreachable("Unexpected SETCC condition");
14751 case ISD::SETEQ: SSECC = 0; break;
14753 case ISD::SETGT: Swap = true; // Fallthrough
14755 case ISD::SETOLT: SSECC = 1; break;
14757 case ISD::SETGE: Swap = true; // Fallthrough
14759 case ISD::SETOLE: SSECC = 2; break;
14760 case ISD::SETUO: SSECC = 3; break;
14762 case ISD::SETNE: SSECC = 4; break;
14763 case ISD::SETULE: Swap = true; // Fallthrough
14764 case ISD::SETUGE: SSECC = 5; break;
14765 case ISD::SETULT: Swap = true; // Fallthrough
14766 case ISD::SETUGT: SSECC = 6; break;
14767 case ISD::SETO: SSECC = 7; break;
14769 case ISD::SETONE: SSECC = 8; break;
14772 std::swap(Op0, Op1);
14777 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14778 // ones, and then concatenate the result back.
14779 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14780 MVT VT = Op.getSimpleValueType();
14782 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14783 "Unsupported value type for operation");
14785 unsigned NumElems = VT.getVectorNumElements();
14787 SDValue CC = Op.getOperand(2);
14789 // Extract the LHS vectors
14790 SDValue LHS = Op.getOperand(0);
14791 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14792 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14794 // Extract the RHS vectors
14795 SDValue RHS = Op.getOperand(1);
14796 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14797 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14799 // Issue the operation on the smaller types and concatenate the result back
14800 MVT EltVT = VT.getVectorElementType();
14801 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14802 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14803 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14804 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14807 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14808 const X86Subtarget *Subtarget) {
14809 SDValue Op0 = Op.getOperand(0);
14810 SDValue Op1 = Op.getOperand(1);
14811 SDValue CC = Op.getOperand(2);
14812 MVT VT = Op.getSimpleValueType();
14815 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14816 Op.getValueType().getScalarType() == MVT::i1 &&
14817 "Cannot set masked compare for this operation");
14819 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14821 bool Unsigned = false;
14824 switch (SetCCOpcode) {
14825 default: llvm_unreachable("Unexpected SETCC condition");
14826 case ISD::SETNE: SSECC = 4; break;
14827 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14828 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14829 case ISD::SETLT: Swap = true; //fall-through
14830 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14831 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14832 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14833 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14834 case ISD::SETULE: Unsigned = true; //fall-through
14835 case ISD::SETLE: SSECC = 2; break;
14839 std::swap(Op0, Op1);
14841 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14842 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14843 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14844 DAG.getConstant(SSECC, MVT::i8));
14847 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14848 /// operand \p Op1. If non-trivial (for example because it's not constant)
14849 /// return an empty value.
14850 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14852 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14856 MVT VT = Op1.getSimpleValueType();
14857 MVT EVT = VT.getVectorElementType();
14858 unsigned n = VT.getVectorNumElements();
14859 SmallVector<SDValue, 8> ULTOp1;
14861 for (unsigned i = 0; i < n; ++i) {
14862 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14863 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14866 // Avoid underflow.
14867 APInt Val = Elt->getAPIntValue();
14871 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14874 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14877 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14878 SelectionDAG &DAG) {
14879 SDValue Op0 = Op.getOperand(0);
14880 SDValue Op1 = Op.getOperand(1);
14881 SDValue CC = Op.getOperand(2);
14882 MVT VT = Op.getSimpleValueType();
14883 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14884 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14889 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14890 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14893 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14894 unsigned Opc = X86ISD::CMPP;
14895 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14896 assert(VT.getVectorNumElements() <= 16);
14897 Opc = X86ISD::CMPM;
14899 // In the two special cases we can't handle, emit two comparisons.
14902 unsigned CombineOpc;
14903 if (SetCCOpcode == ISD::SETUEQ) {
14904 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14906 assert(SetCCOpcode == ISD::SETONE);
14907 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14910 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14911 DAG.getConstant(CC0, MVT::i8));
14912 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14913 DAG.getConstant(CC1, MVT::i8));
14914 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14916 // Handle all other FP comparisons here.
14917 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14918 DAG.getConstant(SSECC, MVT::i8));
14921 // Break 256-bit integer vector compare into smaller ones.
14922 if (VT.is256BitVector() && !Subtarget->hasInt256())
14923 return Lower256IntVSETCC(Op, DAG);
14925 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14926 EVT OpVT = Op1.getValueType();
14927 if (Subtarget->hasAVX512()) {
14928 if (Op1.getValueType().is512BitVector() ||
14929 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14930 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14931 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14933 // In AVX-512 architecture setcc returns mask with i1 elements,
14934 // But there is no compare instruction for i8 and i16 elements in KNL.
14935 // We are not talking about 512-bit operands in this case, these
14936 // types are illegal.
14938 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14939 OpVT.getVectorElementType().getSizeInBits() >= 8))
14940 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14941 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14944 // We are handling one of the integer comparisons here. Since SSE only has
14945 // GT and EQ comparisons for integer, swapping operands and multiple
14946 // operations may be required for some comparisons.
14948 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14949 bool Subus = false;
14951 switch (SetCCOpcode) {
14952 default: llvm_unreachable("Unexpected SETCC condition");
14953 case ISD::SETNE: Invert = true;
14954 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14955 case ISD::SETLT: Swap = true;
14956 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14957 case ISD::SETGE: Swap = true;
14958 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14959 Invert = true; break;
14960 case ISD::SETULT: Swap = true;
14961 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14962 FlipSigns = true; break;
14963 case ISD::SETUGE: Swap = true;
14964 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14965 FlipSigns = true; Invert = true; break;
14968 // Special case: Use min/max operations for SETULE/SETUGE
14969 MVT VET = VT.getVectorElementType();
14971 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14972 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14975 switch (SetCCOpcode) {
14977 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14978 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14981 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14984 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14985 if (!MinMax && hasSubus) {
14986 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14988 // t = psubus Op0, Op1
14989 // pcmpeq t, <0..0>
14990 switch (SetCCOpcode) {
14992 case ISD::SETULT: {
14993 // If the comparison is against a constant we can turn this into a
14994 // setule. With psubus, setule does not require a swap. This is
14995 // beneficial because the constant in the register is no longer
14996 // destructed as the destination so it can be hoisted out of a loop.
14997 // Only do this pre-AVX since vpcmp* is no longer destructive.
14998 if (Subtarget->hasAVX())
15000 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15001 if (ULEOp1.getNode()) {
15003 Subus = true; Invert = false; Swap = false;
15007 // Psubus is better than flip-sign because it requires no inversion.
15008 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15009 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15013 Opc = X86ISD::SUBUS;
15019 std::swap(Op0, Op1);
15021 // Check that the operation in question is available (most are plain SSE2,
15022 // but PCMPGTQ and PCMPEQQ have different requirements).
15023 if (VT == MVT::v2i64) {
15024 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15025 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15027 // First cast everything to the right type.
15028 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15029 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15031 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15032 // bits of the inputs before performing those operations. The lower
15033 // compare is always unsigned.
15036 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15038 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15039 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15040 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15041 Sign, Zero, Sign, Zero);
15043 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15044 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15046 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15047 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15048 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15050 // Create masks for only the low parts/high parts of the 64 bit integers.
15051 static const int MaskHi[] = { 1, 1, 3, 3 };
15052 static const int MaskLo[] = { 0, 0, 2, 2 };
15053 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15054 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15055 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15057 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15058 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15061 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15063 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15066 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15067 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15068 // pcmpeqd + pshufd + pand.
15069 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15071 // First cast everything to the right type.
15072 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15073 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15076 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15078 // Make sure the lower and upper halves are both all-ones.
15079 static const int Mask[] = { 1, 0, 3, 2 };
15080 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15081 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15084 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15086 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15090 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15091 // bits of the inputs before performing those operations.
15093 EVT EltVT = VT.getVectorElementType();
15094 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15095 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15096 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15099 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15101 // If the logical-not of the result is required, perform that now.
15103 Result = DAG.getNOT(dl, Result, VT);
15106 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15109 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15110 getZeroVector(VT, Subtarget, DAG, dl));
15115 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15117 MVT VT = Op.getSimpleValueType();
15119 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15121 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15122 && "SetCC type must be 8-bit or 1-bit integer");
15123 SDValue Op0 = Op.getOperand(0);
15124 SDValue Op1 = Op.getOperand(1);
15126 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15128 // Optimize to BT if possible.
15129 // Lower (X & (1 << N)) == 0 to BT(X, N).
15130 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15131 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15132 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15133 Op1.getOpcode() == ISD::Constant &&
15134 cast<ConstantSDNode>(Op1)->isNullValue() &&
15135 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15136 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15137 if (NewSetCC.getNode())
15141 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15143 if (Op1.getOpcode() == ISD::Constant &&
15144 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15145 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15146 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15148 // If the input is a setcc, then reuse the input setcc or use a new one with
15149 // the inverted condition.
15150 if (Op0.getOpcode() == X86ISD::SETCC) {
15151 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15152 bool Invert = (CC == ISD::SETNE) ^
15153 cast<ConstantSDNode>(Op1)->isNullValue();
15157 CCode = X86::GetOppositeBranchCondition(CCode);
15158 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15159 DAG.getConstant(CCode, MVT::i8),
15160 Op0.getOperand(1));
15162 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15166 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15167 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15168 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15170 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15171 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15174 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15175 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15176 if (X86CC == X86::COND_INVALID)
15179 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15180 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15181 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15182 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15184 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15188 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15189 static bool isX86LogicalCmp(SDValue Op) {
15190 unsigned Opc = Op.getNode()->getOpcode();
15191 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15192 Opc == X86ISD::SAHF)
15194 if (Op.getResNo() == 1 &&
15195 (Opc == X86ISD::ADD ||
15196 Opc == X86ISD::SUB ||
15197 Opc == X86ISD::ADC ||
15198 Opc == X86ISD::SBB ||
15199 Opc == X86ISD::SMUL ||
15200 Opc == X86ISD::UMUL ||
15201 Opc == X86ISD::INC ||
15202 Opc == X86ISD::DEC ||
15203 Opc == X86ISD::OR ||
15204 Opc == X86ISD::XOR ||
15205 Opc == X86ISD::AND))
15208 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15214 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15215 if (V.getOpcode() != ISD::TRUNCATE)
15218 SDValue VOp0 = V.getOperand(0);
15219 unsigned InBits = VOp0.getValueSizeInBits();
15220 unsigned Bits = V.getValueSizeInBits();
15221 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15224 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15225 bool addTest = true;
15226 SDValue Cond = Op.getOperand(0);
15227 SDValue Op1 = Op.getOperand(1);
15228 SDValue Op2 = Op.getOperand(2);
15230 EVT VT = Op1.getValueType();
15233 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15234 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15235 // sequence later on.
15236 if (Cond.getOpcode() == ISD::SETCC &&
15237 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15238 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15239 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15240 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15241 int SSECC = translateX86FSETCC(
15242 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15245 if (Subtarget->hasAVX512()) {
15246 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15247 DAG.getConstant(SSECC, MVT::i8));
15248 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15250 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15251 DAG.getConstant(SSECC, MVT::i8));
15252 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15253 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15254 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15258 if (Cond.getOpcode() == ISD::SETCC) {
15259 SDValue NewCond = LowerSETCC(Cond, DAG);
15260 if (NewCond.getNode())
15264 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15265 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15266 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15267 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15268 if (Cond.getOpcode() == X86ISD::SETCC &&
15269 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15270 isZero(Cond.getOperand(1).getOperand(1))) {
15271 SDValue Cmp = Cond.getOperand(1);
15273 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15275 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15276 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15277 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15279 SDValue CmpOp0 = Cmp.getOperand(0);
15280 // Apply further optimizations for special cases
15281 // (select (x != 0), -1, 0) -> neg & sbb
15282 // (select (x == 0), 0, -1) -> neg & sbb
15283 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15284 if (YC->isNullValue() &&
15285 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15286 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15287 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15288 DAG.getConstant(0, CmpOp0.getValueType()),
15290 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15291 DAG.getConstant(X86::COND_B, MVT::i8),
15292 SDValue(Neg.getNode(), 1));
15296 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15297 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15298 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15300 SDValue Res = // Res = 0 or -1.
15301 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15302 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15304 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15305 Res = DAG.getNOT(DL, Res, Res.getValueType());
15307 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15308 if (!N2C || !N2C->isNullValue())
15309 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15314 // Look past (and (setcc_carry (cmp ...)), 1).
15315 if (Cond.getOpcode() == ISD::AND &&
15316 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15317 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15318 if (C && C->getAPIntValue() == 1)
15319 Cond = Cond.getOperand(0);
15322 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15323 // setting operand in place of the X86ISD::SETCC.
15324 unsigned CondOpcode = Cond.getOpcode();
15325 if (CondOpcode == X86ISD::SETCC ||
15326 CondOpcode == X86ISD::SETCC_CARRY) {
15327 CC = Cond.getOperand(0);
15329 SDValue Cmp = Cond.getOperand(1);
15330 unsigned Opc = Cmp.getOpcode();
15331 MVT VT = Op.getSimpleValueType();
15333 bool IllegalFPCMov = false;
15334 if (VT.isFloatingPoint() && !VT.isVector() &&
15335 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15336 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15338 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15339 Opc == X86ISD::BT) { // FIXME
15343 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15344 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15345 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15346 Cond.getOperand(0).getValueType() != MVT::i8)) {
15347 SDValue LHS = Cond.getOperand(0);
15348 SDValue RHS = Cond.getOperand(1);
15349 unsigned X86Opcode;
15352 switch (CondOpcode) {
15353 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15354 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15355 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15356 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15357 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15358 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15359 default: llvm_unreachable("unexpected overflowing operator");
15361 if (CondOpcode == ISD::UMULO)
15362 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15365 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15367 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15369 if (CondOpcode == ISD::UMULO)
15370 Cond = X86Op.getValue(2);
15372 Cond = X86Op.getValue(1);
15374 CC = DAG.getConstant(X86Cond, MVT::i8);
15379 // Look pass the truncate if the high bits are known zero.
15380 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15381 Cond = Cond.getOperand(0);
15383 // We know the result of AND is compared against zero. Try to match
15385 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15386 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15387 if (NewSetCC.getNode()) {
15388 CC = NewSetCC.getOperand(0);
15389 Cond = NewSetCC.getOperand(1);
15396 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15397 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15400 // a < b ? -1 : 0 -> RES = ~setcc_carry
15401 // a < b ? 0 : -1 -> RES = setcc_carry
15402 // a >= b ? -1 : 0 -> RES = setcc_carry
15403 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15404 if (Cond.getOpcode() == X86ISD::SUB) {
15405 Cond = ConvertCmpIfNecessary(Cond, DAG);
15406 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15408 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15409 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15410 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15411 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15412 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15413 return DAG.getNOT(DL, Res, Res.getValueType());
15418 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15419 // widen the cmov and push the truncate through. This avoids introducing a new
15420 // branch during isel and doesn't add any extensions.
15421 if (Op.getValueType() == MVT::i8 &&
15422 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15423 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15424 if (T1.getValueType() == T2.getValueType() &&
15425 // Blacklist CopyFromReg to avoid partial register stalls.
15426 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15427 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15428 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15429 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15433 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15434 // condition is true.
15435 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15436 SDValue Ops[] = { Op2, Op1, CC, Cond };
15437 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15440 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15441 SelectionDAG &DAG) {
15442 MVT VT = Op->getSimpleValueType(0);
15443 SDValue In = Op->getOperand(0);
15444 MVT InVT = In.getSimpleValueType();
15445 MVT VTElt = VT.getVectorElementType();
15446 MVT InVTElt = InVT.getVectorElementType();
15450 if ((InVTElt == MVT::i1) &&
15451 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15452 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15454 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15455 VTElt.getSizeInBits() <= 16)) ||
15457 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15458 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15460 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15461 VTElt.getSizeInBits() >= 32))))
15462 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15464 unsigned int NumElts = VT.getVectorNumElements();
15466 if (NumElts != 8 && NumElts != 16)
15469 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15470 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15471 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15472 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15475 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15476 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15478 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15479 Constant *C = ConstantInt::get(*DAG.getContext(),
15480 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15482 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15483 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15484 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15485 MachinePointerInfo::getConstantPool(),
15486 false, false, false, Alignment);
15487 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15488 if (VT.is512BitVector())
15490 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15493 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15494 SelectionDAG &DAG) {
15495 MVT VT = Op->getSimpleValueType(0);
15496 SDValue In = Op->getOperand(0);
15497 MVT InVT = In.getSimpleValueType();
15500 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15501 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15503 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15504 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15505 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15508 if (Subtarget->hasInt256())
15509 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15511 // Optimize vectors in AVX mode
15512 // Sign extend v8i16 to v8i32 and
15515 // Divide input vector into two parts
15516 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15517 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15518 // concat the vectors to original VT
15520 unsigned NumElems = InVT.getVectorNumElements();
15521 SDValue Undef = DAG.getUNDEF(InVT);
15523 SmallVector<int,8> ShufMask1(NumElems, -1);
15524 for (unsigned i = 0; i != NumElems/2; ++i)
15527 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15529 SmallVector<int,8> ShufMask2(NumElems, -1);
15530 for (unsigned i = 0; i != NumElems/2; ++i)
15531 ShufMask2[i] = i + NumElems/2;
15533 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15535 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15536 VT.getVectorNumElements()/2);
15538 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15539 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15541 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15544 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15545 // may emit an illegal shuffle but the expansion is still better than scalar
15546 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15547 // we'll emit a shuffle and a arithmetic shift.
15548 // TODO: It is possible to support ZExt by zeroing the undef values during
15549 // the shuffle phase or after the shuffle.
15550 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15551 SelectionDAG &DAG) {
15552 MVT RegVT = Op.getSimpleValueType();
15553 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15554 assert(RegVT.isInteger() &&
15555 "We only custom lower integer vector sext loads.");
15557 // Nothing useful we can do without SSE2 shuffles.
15558 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15560 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15562 EVT MemVT = Ld->getMemoryVT();
15563 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15564 unsigned RegSz = RegVT.getSizeInBits();
15566 ISD::LoadExtType Ext = Ld->getExtensionType();
15568 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15569 && "Only anyext and sext are currently implemented.");
15570 assert(MemVT != RegVT && "Cannot extend to the same type");
15571 assert(MemVT.isVector() && "Must load a vector from memory");
15573 unsigned NumElems = RegVT.getVectorNumElements();
15574 unsigned MemSz = MemVT.getSizeInBits();
15575 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15577 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15578 // The only way in which we have a legal 256-bit vector result but not the
15579 // integer 256-bit operations needed to directly lower a sextload is if we
15580 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15581 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15582 // correctly legalized. We do this late to allow the canonical form of
15583 // sextload to persist throughout the rest of the DAG combiner -- it wants
15584 // to fold together any extensions it can, and so will fuse a sign_extend
15585 // of an sextload into a sextload targeting a wider value.
15587 if (MemSz == 128) {
15588 // Just switch this to a normal load.
15589 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15590 "it must be a legal 128-bit vector "
15592 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15593 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15594 Ld->isInvariant(), Ld->getAlignment());
15596 assert(MemSz < 128 &&
15597 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15598 // Do an sext load to a 128-bit vector type. We want to use the same
15599 // number of elements, but elements half as wide. This will end up being
15600 // recursively lowered by this routine, but will succeed as we definitely
15601 // have all the necessary features if we're using AVX1.
15603 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15604 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15606 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15607 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15608 Ld->isNonTemporal(), Ld->isInvariant(),
15609 Ld->getAlignment());
15612 // Replace chain users with the new chain.
15613 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15614 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15616 // Finally, do a normal sign-extend to the desired register.
15617 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15620 // All sizes must be a power of two.
15621 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15622 "Non-power-of-two elements are not custom lowered!");
15624 // Attempt to load the original value using scalar loads.
15625 // Find the largest scalar type that divides the total loaded size.
15626 MVT SclrLoadTy = MVT::i8;
15627 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15628 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15629 MVT Tp = (MVT::SimpleValueType)tp;
15630 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15635 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15636 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15638 SclrLoadTy = MVT::f64;
15640 // Calculate the number of scalar loads that we need to perform
15641 // in order to load our vector from memory.
15642 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15644 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15645 "Can only lower sext loads with a single scalar load!");
15647 unsigned loadRegZize = RegSz;
15648 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15651 // Represent our vector as a sequence of elements which are the
15652 // largest scalar that we can load.
15653 EVT LoadUnitVecVT = EVT::getVectorVT(
15654 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15656 // Represent the data using the same element type that is stored in
15657 // memory. In practice, we ''widen'' MemVT.
15659 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15660 loadRegZize / MemVT.getScalarType().getSizeInBits());
15662 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15663 "Invalid vector type");
15665 // We can't shuffle using an illegal type.
15666 assert(TLI.isTypeLegal(WideVecVT) &&
15667 "We only lower types that form legal widened vector types");
15669 SmallVector<SDValue, 8> Chains;
15670 SDValue Ptr = Ld->getBasePtr();
15671 SDValue Increment =
15672 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15673 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15675 for (unsigned i = 0; i < NumLoads; ++i) {
15676 // Perform a single load.
15677 SDValue ScalarLoad =
15678 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15679 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15680 Ld->getAlignment());
15681 Chains.push_back(ScalarLoad.getValue(1));
15682 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15683 // another round of DAGCombining.
15685 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15687 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15688 ScalarLoad, DAG.getIntPtrConstant(i));
15690 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15693 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15695 // Bitcast the loaded value to a vector of the original element type, in
15696 // the size of the target vector type.
15697 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15698 unsigned SizeRatio = RegSz / MemSz;
15700 if (Ext == ISD::SEXTLOAD) {
15701 // If we have SSE4.1, we can directly emit a VSEXT node.
15702 if (Subtarget->hasSSE41()) {
15703 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15704 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15708 // Otherwise we'll shuffle the small elements in the high bits of the
15709 // larger type and perform an arithmetic shift. If the shift is not legal
15710 // it's better to scalarize.
15711 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15712 "We can't implement a sext load without an arithmetic right shift!");
15714 // Redistribute the loaded elements into the different locations.
15715 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15716 for (unsigned i = 0; i != NumElems; ++i)
15717 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15719 SDValue Shuff = DAG.getVectorShuffle(
15720 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15722 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15724 // Build the arithmetic shift.
15725 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15726 MemVT.getVectorElementType().getSizeInBits();
15728 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15730 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15734 // Redistribute the loaded elements into the different locations.
15735 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15736 for (unsigned i = 0; i != NumElems; ++i)
15737 ShuffleVec[i * SizeRatio] = i;
15739 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15740 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15742 // Bitcast to the requested type.
15743 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15744 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15748 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15749 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15750 // from the AND / OR.
15751 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15752 Opc = Op.getOpcode();
15753 if (Opc != ISD::OR && Opc != ISD::AND)
15755 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15756 Op.getOperand(0).hasOneUse() &&
15757 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15758 Op.getOperand(1).hasOneUse());
15761 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15762 // 1 and that the SETCC node has a single use.
15763 static bool isXor1OfSetCC(SDValue Op) {
15764 if (Op.getOpcode() != ISD::XOR)
15766 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15767 if (N1C && N1C->getAPIntValue() == 1) {
15768 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15769 Op.getOperand(0).hasOneUse();
15774 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15775 bool addTest = true;
15776 SDValue Chain = Op.getOperand(0);
15777 SDValue Cond = Op.getOperand(1);
15778 SDValue Dest = Op.getOperand(2);
15781 bool Inverted = false;
15783 if (Cond.getOpcode() == ISD::SETCC) {
15784 // Check for setcc([su]{add,sub,mul}o == 0).
15785 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15786 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15787 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15788 Cond.getOperand(0).getResNo() == 1 &&
15789 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15790 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15791 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15792 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15793 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15794 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15796 Cond = Cond.getOperand(0);
15798 SDValue NewCond = LowerSETCC(Cond, DAG);
15799 if (NewCond.getNode())
15804 // FIXME: LowerXALUO doesn't handle these!!
15805 else if (Cond.getOpcode() == X86ISD::ADD ||
15806 Cond.getOpcode() == X86ISD::SUB ||
15807 Cond.getOpcode() == X86ISD::SMUL ||
15808 Cond.getOpcode() == X86ISD::UMUL)
15809 Cond = LowerXALUO(Cond, DAG);
15812 // Look pass (and (setcc_carry (cmp ...)), 1).
15813 if (Cond.getOpcode() == ISD::AND &&
15814 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15815 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15816 if (C && C->getAPIntValue() == 1)
15817 Cond = Cond.getOperand(0);
15820 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15821 // setting operand in place of the X86ISD::SETCC.
15822 unsigned CondOpcode = Cond.getOpcode();
15823 if (CondOpcode == X86ISD::SETCC ||
15824 CondOpcode == X86ISD::SETCC_CARRY) {
15825 CC = Cond.getOperand(0);
15827 SDValue Cmp = Cond.getOperand(1);
15828 unsigned Opc = Cmp.getOpcode();
15829 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15830 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15834 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15838 // These can only come from an arithmetic instruction with overflow,
15839 // e.g. SADDO, UADDO.
15840 Cond = Cond.getNode()->getOperand(1);
15846 CondOpcode = Cond.getOpcode();
15847 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15848 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15849 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15850 Cond.getOperand(0).getValueType() != MVT::i8)) {
15851 SDValue LHS = Cond.getOperand(0);
15852 SDValue RHS = Cond.getOperand(1);
15853 unsigned X86Opcode;
15856 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15857 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15859 switch (CondOpcode) {
15860 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15862 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15864 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15867 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15868 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15870 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15872 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15875 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15876 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15877 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15878 default: llvm_unreachable("unexpected overflowing operator");
15881 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15882 if (CondOpcode == ISD::UMULO)
15883 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15886 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15888 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15890 if (CondOpcode == ISD::UMULO)
15891 Cond = X86Op.getValue(2);
15893 Cond = X86Op.getValue(1);
15895 CC = DAG.getConstant(X86Cond, MVT::i8);
15899 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15900 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15901 if (CondOpc == ISD::OR) {
15902 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15903 // two branches instead of an explicit OR instruction with a
15905 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15906 isX86LogicalCmp(Cmp)) {
15907 CC = Cond.getOperand(0).getOperand(0);
15908 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15909 Chain, Dest, CC, Cmp);
15910 CC = Cond.getOperand(1).getOperand(0);
15914 } else { // ISD::AND
15915 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15916 // two branches instead of an explicit AND instruction with a
15917 // separate test. However, we only do this if this block doesn't
15918 // have a fall-through edge, because this requires an explicit
15919 // jmp when the condition is false.
15920 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15921 isX86LogicalCmp(Cmp) &&
15922 Op.getNode()->hasOneUse()) {
15923 X86::CondCode CCode =
15924 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15925 CCode = X86::GetOppositeBranchCondition(CCode);
15926 CC = DAG.getConstant(CCode, MVT::i8);
15927 SDNode *User = *Op.getNode()->use_begin();
15928 // Look for an unconditional branch following this conditional branch.
15929 // We need this because we need to reverse the successors in order
15930 // to implement FCMP_OEQ.
15931 if (User->getOpcode() == ISD::BR) {
15932 SDValue FalseBB = User->getOperand(1);
15934 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15935 assert(NewBR == User);
15939 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15940 Chain, Dest, CC, Cmp);
15941 X86::CondCode CCode =
15942 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15943 CCode = X86::GetOppositeBranchCondition(CCode);
15944 CC = DAG.getConstant(CCode, MVT::i8);
15950 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15951 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15952 // It should be transformed during dag combiner except when the condition
15953 // is set by a arithmetics with overflow node.
15954 X86::CondCode CCode =
15955 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15956 CCode = X86::GetOppositeBranchCondition(CCode);
15957 CC = DAG.getConstant(CCode, MVT::i8);
15958 Cond = Cond.getOperand(0).getOperand(1);
15960 } else if (Cond.getOpcode() == ISD::SETCC &&
15961 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15962 // For FCMP_OEQ, we can emit
15963 // two branches instead of an explicit AND instruction with a
15964 // separate test. However, we only do this if this block doesn't
15965 // have a fall-through edge, because this requires an explicit
15966 // jmp when the condition is false.
15967 if (Op.getNode()->hasOneUse()) {
15968 SDNode *User = *Op.getNode()->use_begin();
15969 // Look for an unconditional branch following this conditional branch.
15970 // We need this because we need to reverse the successors in order
15971 // to implement FCMP_OEQ.
15972 if (User->getOpcode() == ISD::BR) {
15973 SDValue FalseBB = User->getOperand(1);
15975 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15976 assert(NewBR == User);
15980 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15981 Cond.getOperand(0), Cond.getOperand(1));
15982 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15983 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15984 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15985 Chain, Dest, CC, Cmp);
15986 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15991 } else if (Cond.getOpcode() == ISD::SETCC &&
15992 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15993 // For FCMP_UNE, we can emit
15994 // two branches instead of an explicit AND instruction with a
15995 // separate test. However, we only do this if this block doesn't
15996 // have a fall-through edge, because this requires an explicit
15997 // jmp when the condition is false.
15998 if (Op.getNode()->hasOneUse()) {
15999 SDNode *User = *Op.getNode()->use_begin();
16000 // Look for an unconditional branch following this conditional branch.
16001 // We need this because we need to reverse the successors in order
16002 // to implement FCMP_UNE.
16003 if (User->getOpcode() == ISD::BR) {
16004 SDValue FalseBB = User->getOperand(1);
16006 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16007 assert(NewBR == User);
16010 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16011 Cond.getOperand(0), Cond.getOperand(1));
16012 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16013 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16014 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16015 Chain, Dest, CC, Cmp);
16016 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16026 // Look pass the truncate if the high bits are known zero.
16027 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16028 Cond = Cond.getOperand(0);
16030 // We know the result of AND is compared against zero. Try to match
16032 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16033 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16034 if (NewSetCC.getNode()) {
16035 CC = NewSetCC.getOperand(0);
16036 Cond = NewSetCC.getOperand(1);
16043 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16044 CC = DAG.getConstant(X86Cond, MVT::i8);
16045 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16047 Cond = ConvertCmpIfNecessary(Cond, DAG);
16048 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16049 Chain, Dest, CC, Cond);
16052 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16053 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16054 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16055 // that the guard pages used by the OS virtual memory manager are allocated in
16056 // correct sequence.
16058 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16059 SelectionDAG &DAG) const {
16060 MachineFunction &MF = DAG.getMachineFunction();
16061 bool SplitStack = MF.shouldSplitStack();
16062 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
16067 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16068 SDNode* Node = Op.getNode();
16070 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16071 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16072 " not tell us which reg is the stack pointer!");
16073 EVT VT = Node->getValueType(0);
16074 SDValue Tmp1 = SDValue(Node, 0);
16075 SDValue Tmp2 = SDValue(Node, 1);
16076 SDValue Tmp3 = Node->getOperand(2);
16077 SDValue Chain = Tmp1.getOperand(0);
16079 // Chain the dynamic stack allocation so that it doesn't modify the stack
16080 // pointer when other instructions are using the stack.
16081 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16084 SDValue Size = Tmp2.getOperand(1);
16085 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16086 Chain = SP.getValue(1);
16087 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16088 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16089 unsigned StackAlign = TFI.getStackAlignment();
16090 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16091 if (Align > StackAlign)
16092 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16093 DAG.getConstant(-(uint64_t)Align, VT));
16094 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16096 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16097 DAG.getIntPtrConstant(0, true), SDValue(),
16100 SDValue Ops[2] = { Tmp1, Tmp2 };
16101 return DAG.getMergeValues(Ops, dl);
16105 SDValue Chain = Op.getOperand(0);
16106 SDValue Size = Op.getOperand(1);
16107 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16108 EVT VT = Op.getNode()->getValueType(0);
16110 bool Is64Bit = Subtarget->is64Bit();
16111 EVT SPTy = getPointerTy();
16114 MachineRegisterInfo &MRI = MF.getRegInfo();
16117 // The 64 bit implementation of segmented stacks needs to clobber both r10
16118 // r11. This makes it impossible to use it along with nested parameters.
16119 const Function *F = MF.getFunction();
16121 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16123 if (I->hasNestAttr())
16124 report_fatal_error("Cannot use segmented stacks with functions that "
16125 "have nested arguments.");
16128 const TargetRegisterClass *AddrRegClass =
16129 getRegClassFor(getPointerTy());
16130 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16131 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16132 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16133 DAG.getRegister(Vreg, SPTy));
16134 SDValue Ops1[2] = { Value, Chain };
16135 return DAG.getMergeValues(Ops1, dl);
16138 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16140 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16141 Flag = Chain.getValue(1);
16142 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16144 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16146 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16147 DAG.getSubtarget().getRegisterInfo());
16148 unsigned SPReg = RegInfo->getStackRegister();
16149 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16150 Chain = SP.getValue(1);
16153 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16154 DAG.getConstant(-(uint64_t)Align, VT));
16155 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16158 SDValue Ops1[2] = { SP, Chain };
16159 return DAG.getMergeValues(Ops1, dl);
16163 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16164 MachineFunction &MF = DAG.getMachineFunction();
16165 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16167 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16170 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16171 // vastart just stores the address of the VarArgsFrameIndex slot into the
16172 // memory location argument.
16173 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16175 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16176 MachinePointerInfo(SV), false, false, 0);
16180 // gp_offset (0 - 6 * 8)
16181 // fp_offset (48 - 48 + 8 * 16)
16182 // overflow_arg_area (point to parameters coming in memory).
16184 SmallVector<SDValue, 8> MemOps;
16185 SDValue FIN = Op.getOperand(1);
16187 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16188 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16190 FIN, MachinePointerInfo(SV), false, false, 0);
16191 MemOps.push_back(Store);
16194 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16195 FIN, DAG.getIntPtrConstant(4));
16196 Store = DAG.getStore(Op.getOperand(0), DL,
16197 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16199 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16200 MemOps.push_back(Store);
16202 // Store ptr to overflow_arg_area
16203 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16204 FIN, DAG.getIntPtrConstant(4));
16205 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16207 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16208 MachinePointerInfo(SV, 8),
16210 MemOps.push_back(Store);
16212 // Store ptr to reg_save_area.
16213 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16214 FIN, DAG.getIntPtrConstant(8));
16215 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16217 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16218 MachinePointerInfo(SV, 16), false, false, 0);
16219 MemOps.push_back(Store);
16220 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16223 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16224 assert(Subtarget->is64Bit() &&
16225 "LowerVAARG only handles 64-bit va_arg!");
16226 assert((Subtarget->isTargetLinux() ||
16227 Subtarget->isTargetDarwin()) &&
16228 "Unhandled target in LowerVAARG");
16229 assert(Op.getNode()->getNumOperands() == 4);
16230 SDValue Chain = Op.getOperand(0);
16231 SDValue SrcPtr = Op.getOperand(1);
16232 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16233 unsigned Align = Op.getConstantOperandVal(3);
16236 EVT ArgVT = Op.getNode()->getValueType(0);
16237 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16238 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16241 // Decide which area this value should be read from.
16242 // TODO: Implement the AMD64 ABI in its entirety. This simple
16243 // selection mechanism works only for the basic types.
16244 if (ArgVT == MVT::f80) {
16245 llvm_unreachable("va_arg for f80 not yet implemented");
16246 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16247 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16248 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16249 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16251 llvm_unreachable("Unhandled argument type in LowerVAARG");
16254 if (ArgMode == 2) {
16255 // Sanity Check: Make sure using fp_offset makes sense.
16256 assert(!DAG.getTarget().Options.UseSoftFloat &&
16257 !(DAG.getMachineFunction()
16258 .getFunction()->getAttributes()
16259 .hasAttribute(AttributeSet::FunctionIndex,
16260 Attribute::NoImplicitFloat)) &&
16261 Subtarget->hasSSE1());
16264 // Insert VAARG_64 node into the DAG
16265 // VAARG_64 returns two values: Variable Argument Address, Chain
16266 SmallVector<SDValue, 11> InstOps;
16267 InstOps.push_back(Chain);
16268 InstOps.push_back(SrcPtr);
16269 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16270 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16271 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16272 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16273 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16274 VTs, InstOps, MVT::i64,
16275 MachinePointerInfo(SV),
16277 /*Volatile=*/false,
16279 /*WriteMem=*/true);
16280 Chain = VAARG.getValue(1);
16282 // Load the next argument and return it
16283 return DAG.getLoad(ArgVT, dl,
16286 MachinePointerInfo(),
16287 false, false, false, 0);
16290 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16291 SelectionDAG &DAG) {
16292 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16293 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16294 SDValue Chain = Op.getOperand(0);
16295 SDValue DstPtr = Op.getOperand(1);
16296 SDValue SrcPtr = Op.getOperand(2);
16297 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16298 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16301 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16302 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16304 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16307 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16308 // amount is a constant. Takes immediate version of shift as input.
16309 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16310 SDValue SrcOp, uint64_t ShiftAmt,
16311 SelectionDAG &DAG) {
16312 MVT ElementType = VT.getVectorElementType();
16314 // Fold this packed shift into its first operand if ShiftAmt is 0.
16318 // Check for ShiftAmt >= element width
16319 if (ShiftAmt >= ElementType.getSizeInBits()) {
16320 if (Opc == X86ISD::VSRAI)
16321 ShiftAmt = ElementType.getSizeInBits() - 1;
16323 return DAG.getConstant(0, VT);
16326 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16327 && "Unknown target vector shift-by-constant node");
16329 // Fold this packed vector shift into a build vector if SrcOp is a
16330 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16331 if (VT == SrcOp.getSimpleValueType() &&
16332 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16333 SmallVector<SDValue, 8> Elts;
16334 unsigned NumElts = SrcOp->getNumOperands();
16335 ConstantSDNode *ND;
16338 default: llvm_unreachable(nullptr);
16339 case X86ISD::VSHLI:
16340 for (unsigned i=0; i!=NumElts; ++i) {
16341 SDValue CurrentOp = SrcOp->getOperand(i);
16342 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16343 Elts.push_back(CurrentOp);
16346 ND = cast<ConstantSDNode>(CurrentOp);
16347 const APInt &C = ND->getAPIntValue();
16348 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16351 case X86ISD::VSRLI:
16352 for (unsigned i=0; i!=NumElts; ++i) {
16353 SDValue CurrentOp = SrcOp->getOperand(i);
16354 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16355 Elts.push_back(CurrentOp);
16358 ND = cast<ConstantSDNode>(CurrentOp);
16359 const APInt &C = ND->getAPIntValue();
16360 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16363 case X86ISD::VSRAI:
16364 for (unsigned i=0; i!=NumElts; ++i) {
16365 SDValue CurrentOp = SrcOp->getOperand(i);
16366 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16367 Elts.push_back(CurrentOp);
16370 ND = cast<ConstantSDNode>(CurrentOp);
16371 const APInt &C = ND->getAPIntValue();
16372 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16377 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16380 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16383 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16384 // may or may not be a constant. Takes immediate version of shift as input.
16385 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16386 SDValue SrcOp, SDValue ShAmt,
16387 SelectionDAG &DAG) {
16388 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16390 // Catch shift-by-constant.
16391 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16392 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16393 CShAmt->getZExtValue(), DAG);
16395 // Change opcode to non-immediate version
16397 default: llvm_unreachable("Unknown target vector shift node");
16398 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16399 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16400 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16403 // Need to build a vector containing shift amount
16404 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16407 ShOps[1] = DAG.getConstant(0, MVT::i32);
16408 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16409 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16411 // The return type has to be a 128-bit type with the same element
16412 // type as the input type.
16413 MVT EltVT = VT.getVectorElementType();
16414 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16416 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16417 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16420 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16421 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16422 /// necessary casting for \p Mask when lowering masking intrinsics.
16423 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16424 SDValue PreservedSrc,
16425 const X86Subtarget *Subtarget,
16426 SelectionDAG &DAG) {
16427 EVT VT = Op.getValueType();
16428 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16429 MVT::i1, VT.getVectorNumElements());
16430 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16431 Mask.getValueType().getSizeInBits());
16434 assert(MaskVT.isSimple() && "invalid mask type");
16436 if (isAllOnes(Mask))
16439 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16440 // are extracted by EXTRACT_SUBVECTOR.
16441 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16442 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16443 DAG.getIntPtrConstant(0));
16445 switch (Op.getOpcode()) {
16447 case X86ISD::PCMPEQM:
16448 case X86ISD::PCMPGTM:
16450 case X86ISD::CMPMU:
16451 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16453 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16454 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16455 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16458 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16460 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16461 case Intrinsic::x86_fma_vfmadd_ps:
16462 case Intrinsic::x86_fma_vfmadd_pd:
16463 case Intrinsic::x86_fma_vfmadd_ps_256:
16464 case Intrinsic::x86_fma_vfmadd_pd_256:
16465 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16466 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16467 return X86ISD::FMADD;
16468 case Intrinsic::x86_fma_vfmsub_ps:
16469 case Intrinsic::x86_fma_vfmsub_pd:
16470 case Intrinsic::x86_fma_vfmsub_ps_256:
16471 case Intrinsic::x86_fma_vfmsub_pd_256:
16472 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16473 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16474 return X86ISD::FMSUB;
16475 case Intrinsic::x86_fma_vfnmadd_ps:
16476 case Intrinsic::x86_fma_vfnmadd_pd:
16477 case Intrinsic::x86_fma_vfnmadd_ps_256:
16478 case Intrinsic::x86_fma_vfnmadd_pd_256:
16479 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16480 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16481 return X86ISD::FNMADD;
16482 case Intrinsic::x86_fma_vfnmsub_ps:
16483 case Intrinsic::x86_fma_vfnmsub_pd:
16484 case Intrinsic::x86_fma_vfnmsub_ps_256:
16485 case Intrinsic::x86_fma_vfnmsub_pd_256:
16486 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16487 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16488 return X86ISD::FNMSUB;
16489 case Intrinsic::x86_fma_vfmaddsub_ps:
16490 case Intrinsic::x86_fma_vfmaddsub_pd:
16491 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16492 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16493 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16494 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16495 return X86ISD::FMADDSUB;
16496 case Intrinsic::x86_fma_vfmsubadd_ps:
16497 case Intrinsic::x86_fma_vfmsubadd_pd:
16498 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16499 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16500 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16501 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16502 return X86ISD::FMSUBADD;
16506 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16507 SelectionDAG &DAG) {
16509 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16510 EVT VT = Op.getValueType();
16511 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16513 switch(IntrData->Type) {
16514 case INTR_TYPE_1OP:
16515 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16516 case INTR_TYPE_2OP:
16517 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16519 case INTR_TYPE_3OP:
16520 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16521 Op.getOperand(2), Op.getOperand(3));
16522 case INTR_TYPE_1OP_MASK_RM: {
16523 SDValue Src = Op.getOperand(1);
16524 SDValue Src0 = Op.getOperand(2);
16525 SDValue Mask = Op.getOperand(3);
16526 SDValue RoundingMode = Op.getOperand(4);
16527 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16529 Mask, Src0, Subtarget, DAG);
16533 case CMP_MASK_CC: {
16534 // Comparison intrinsics with masks.
16535 // Example of transformation:
16536 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16537 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16539 // (v8i1 (insert_subvector undef,
16540 // (v2i1 (and (PCMPEQM %a, %b),
16541 // (extract_subvector
16542 // (v8i1 (bitcast %mask)), 0))), 0))))
16543 EVT VT = Op.getOperand(1).getValueType();
16544 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16545 VT.getVectorNumElements());
16546 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16547 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16548 Mask.getValueType().getSizeInBits());
16550 if (IntrData->Type == CMP_MASK_CC) {
16551 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16552 Op.getOperand(2), Op.getOperand(3));
16554 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16555 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16558 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16559 DAG.getTargetConstant(0, MaskVT),
16561 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16562 DAG.getUNDEF(BitcastVT), CmpMask,
16563 DAG.getIntPtrConstant(0));
16564 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16566 case COMI: { // Comparison intrinsics
16567 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16568 SDValue LHS = Op.getOperand(1);
16569 SDValue RHS = Op.getOperand(2);
16570 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16571 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16572 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16573 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16574 DAG.getConstant(X86CC, MVT::i8), Cond);
16575 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16578 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16579 Op.getOperand(1), Op.getOperand(2), DAG);
16581 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16582 Op.getOperand(1), Op.getOperand(2), DAG),
16583 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);;
16590 default: return SDValue(); // Don't custom lower most intrinsics.
16592 // Arithmetic intrinsics.
16593 case Intrinsic::x86_sse2_pmulu_dq:
16594 case Intrinsic::x86_avx2_pmulu_dq:
16595 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16596 Op.getOperand(1), Op.getOperand(2));
16598 case Intrinsic::x86_sse41_pmuldq:
16599 case Intrinsic::x86_avx2_pmul_dq:
16600 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16601 Op.getOperand(1), Op.getOperand(2));
16603 case Intrinsic::x86_sse2_pmulhu_w:
16604 case Intrinsic::x86_avx2_pmulhu_w:
16605 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16606 Op.getOperand(1), Op.getOperand(2));
16608 case Intrinsic::x86_sse2_pmulh_w:
16609 case Intrinsic::x86_avx2_pmulh_w:
16610 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16611 Op.getOperand(1), Op.getOperand(2));
16613 // SSE/SSE2/AVX floating point max/min intrinsics.
16614 case Intrinsic::x86_sse_max_ps:
16615 case Intrinsic::x86_sse2_max_pd:
16616 case Intrinsic::x86_avx_max_ps_256:
16617 case Intrinsic::x86_avx_max_pd_256:
16618 case Intrinsic::x86_sse_min_ps:
16619 case Intrinsic::x86_sse2_min_pd:
16620 case Intrinsic::x86_avx_min_ps_256:
16621 case Intrinsic::x86_avx_min_pd_256: {
16624 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16625 case Intrinsic::x86_sse_max_ps:
16626 case Intrinsic::x86_sse2_max_pd:
16627 case Intrinsic::x86_avx_max_ps_256:
16628 case Intrinsic::x86_avx_max_pd_256:
16629 Opcode = X86ISD::FMAX;
16631 case Intrinsic::x86_sse_min_ps:
16632 case Intrinsic::x86_sse2_min_pd:
16633 case Intrinsic::x86_avx_min_ps_256:
16634 case Intrinsic::x86_avx_min_pd_256:
16635 Opcode = X86ISD::FMIN;
16638 return DAG.getNode(Opcode, dl, Op.getValueType(),
16639 Op.getOperand(1), Op.getOperand(2));
16642 // AVX2 variable shift intrinsics
16643 case Intrinsic::x86_avx2_psllv_d:
16644 case Intrinsic::x86_avx2_psllv_q:
16645 case Intrinsic::x86_avx2_psllv_d_256:
16646 case Intrinsic::x86_avx2_psllv_q_256:
16647 case Intrinsic::x86_avx2_psrlv_d:
16648 case Intrinsic::x86_avx2_psrlv_q:
16649 case Intrinsic::x86_avx2_psrlv_d_256:
16650 case Intrinsic::x86_avx2_psrlv_q_256:
16651 case Intrinsic::x86_avx2_psrav_d:
16652 case Intrinsic::x86_avx2_psrav_d_256: {
16655 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16656 case Intrinsic::x86_avx2_psllv_d:
16657 case Intrinsic::x86_avx2_psllv_q:
16658 case Intrinsic::x86_avx2_psllv_d_256:
16659 case Intrinsic::x86_avx2_psllv_q_256:
16662 case Intrinsic::x86_avx2_psrlv_d:
16663 case Intrinsic::x86_avx2_psrlv_q:
16664 case Intrinsic::x86_avx2_psrlv_d_256:
16665 case Intrinsic::x86_avx2_psrlv_q_256:
16668 case Intrinsic::x86_avx2_psrav_d:
16669 case Intrinsic::x86_avx2_psrav_d_256:
16673 return DAG.getNode(Opcode, dl, Op.getValueType(),
16674 Op.getOperand(1), Op.getOperand(2));
16677 case Intrinsic::x86_sse2_packssdw_128:
16678 case Intrinsic::x86_sse2_packsswb_128:
16679 case Intrinsic::x86_avx2_packssdw:
16680 case Intrinsic::x86_avx2_packsswb:
16681 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16682 Op.getOperand(1), Op.getOperand(2));
16684 case Intrinsic::x86_sse2_packuswb_128:
16685 case Intrinsic::x86_sse41_packusdw:
16686 case Intrinsic::x86_avx2_packuswb:
16687 case Intrinsic::x86_avx2_packusdw:
16688 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16689 Op.getOperand(1), Op.getOperand(2));
16691 case Intrinsic::x86_ssse3_pshuf_b_128:
16692 case Intrinsic::x86_avx2_pshuf_b:
16693 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16694 Op.getOperand(1), Op.getOperand(2));
16696 case Intrinsic::x86_sse2_pshuf_d:
16697 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16698 Op.getOperand(1), Op.getOperand(2));
16700 case Intrinsic::x86_sse2_pshufl_w:
16701 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16702 Op.getOperand(1), Op.getOperand(2));
16704 case Intrinsic::x86_sse2_pshufh_w:
16705 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16706 Op.getOperand(1), Op.getOperand(2));
16708 case Intrinsic::x86_ssse3_psign_b_128:
16709 case Intrinsic::x86_ssse3_psign_w_128:
16710 case Intrinsic::x86_ssse3_psign_d_128:
16711 case Intrinsic::x86_avx2_psign_b:
16712 case Intrinsic::x86_avx2_psign_w:
16713 case Intrinsic::x86_avx2_psign_d:
16714 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16715 Op.getOperand(1), Op.getOperand(2));
16717 case Intrinsic::x86_avx2_permd:
16718 case Intrinsic::x86_avx2_permps:
16719 // Operands intentionally swapped. Mask is last operand to intrinsic,
16720 // but second operand for node/instruction.
16721 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16722 Op.getOperand(2), Op.getOperand(1));
16724 case Intrinsic::x86_avx512_mask_valign_q_512:
16725 case Intrinsic::x86_avx512_mask_valign_d_512:
16726 // Vector source operands are swapped.
16727 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16728 Op.getValueType(), Op.getOperand(2),
16731 Op.getOperand(5), Op.getOperand(4),
16734 // ptest and testp intrinsics. The intrinsic these come from are designed to
16735 // return an integer value, not just an instruction so lower it to the ptest
16736 // or testp pattern and a setcc for the result.
16737 case Intrinsic::x86_sse41_ptestz:
16738 case Intrinsic::x86_sse41_ptestc:
16739 case Intrinsic::x86_sse41_ptestnzc:
16740 case Intrinsic::x86_avx_ptestz_256:
16741 case Intrinsic::x86_avx_ptestc_256:
16742 case Intrinsic::x86_avx_ptestnzc_256:
16743 case Intrinsic::x86_avx_vtestz_ps:
16744 case Intrinsic::x86_avx_vtestc_ps:
16745 case Intrinsic::x86_avx_vtestnzc_ps:
16746 case Intrinsic::x86_avx_vtestz_pd:
16747 case Intrinsic::x86_avx_vtestc_pd:
16748 case Intrinsic::x86_avx_vtestnzc_pd:
16749 case Intrinsic::x86_avx_vtestz_ps_256:
16750 case Intrinsic::x86_avx_vtestc_ps_256:
16751 case Intrinsic::x86_avx_vtestnzc_ps_256:
16752 case Intrinsic::x86_avx_vtestz_pd_256:
16753 case Intrinsic::x86_avx_vtestc_pd_256:
16754 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16755 bool IsTestPacked = false;
16758 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16759 case Intrinsic::x86_avx_vtestz_ps:
16760 case Intrinsic::x86_avx_vtestz_pd:
16761 case Intrinsic::x86_avx_vtestz_ps_256:
16762 case Intrinsic::x86_avx_vtestz_pd_256:
16763 IsTestPacked = true; // Fallthrough
16764 case Intrinsic::x86_sse41_ptestz:
16765 case Intrinsic::x86_avx_ptestz_256:
16767 X86CC = X86::COND_E;
16769 case Intrinsic::x86_avx_vtestc_ps:
16770 case Intrinsic::x86_avx_vtestc_pd:
16771 case Intrinsic::x86_avx_vtestc_ps_256:
16772 case Intrinsic::x86_avx_vtestc_pd_256:
16773 IsTestPacked = true; // Fallthrough
16774 case Intrinsic::x86_sse41_ptestc:
16775 case Intrinsic::x86_avx_ptestc_256:
16777 X86CC = X86::COND_B;
16779 case Intrinsic::x86_avx_vtestnzc_ps:
16780 case Intrinsic::x86_avx_vtestnzc_pd:
16781 case Intrinsic::x86_avx_vtestnzc_ps_256:
16782 case Intrinsic::x86_avx_vtestnzc_pd_256:
16783 IsTestPacked = true; // Fallthrough
16784 case Intrinsic::x86_sse41_ptestnzc:
16785 case Intrinsic::x86_avx_ptestnzc_256:
16787 X86CC = X86::COND_A;
16791 SDValue LHS = Op.getOperand(1);
16792 SDValue RHS = Op.getOperand(2);
16793 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16794 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16795 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16796 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16797 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16799 case Intrinsic::x86_avx512_kortestz_w:
16800 case Intrinsic::x86_avx512_kortestc_w: {
16801 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16802 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16803 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16804 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16805 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16806 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16807 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16810 case Intrinsic::x86_sse42_pcmpistria128:
16811 case Intrinsic::x86_sse42_pcmpestria128:
16812 case Intrinsic::x86_sse42_pcmpistric128:
16813 case Intrinsic::x86_sse42_pcmpestric128:
16814 case Intrinsic::x86_sse42_pcmpistrio128:
16815 case Intrinsic::x86_sse42_pcmpestrio128:
16816 case Intrinsic::x86_sse42_pcmpistris128:
16817 case Intrinsic::x86_sse42_pcmpestris128:
16818 case Intrinsic::x86_sse42_pcmpistriz128:
16819 case Intrinsic::x86_sse42_pcmpestriz128: {
16823 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16824 case Intrinsic::x86_sse42_pcmpistria128:
16825 Opcode = X86ISD::PCMPISTRI;
16826 X86CC = X86::COND_A;
16828 case Intrinsic::x86_sse42_pcmpestria128:
16829 Opcode = X86ISD::PCMPESTRI;
16830 X86CC = X86::COND_A;
16832 case Intrinsic::x86_sse42_pcmpistric128:
16833 Opcode = X86ISD::PCMPISTRI;
16834 X86CC = X86::COND_B;
16836 case Intrinsic::x86_sse42_pcmpestric128:
16837 Opcode = X86ISD::PCMPESTRI;
16838 X86CC = X86::COND_B;
16840 case Intrinsic::x86_sse42_pcmpistrio128:
16841 Opcode = X86ISD::PCMPISTRI;
16842 X86CC = X86::COND_O;
16844 case Intrinsic::x86_sse42_pcmpestrio128:
16845 Opcode = X86ISD::PCMPESTRI;
16846 X86CC = X86::COND_O;
16848 case Intrinsic::x86_sse42_pcmpistris128:
16849 Opcode = X86ISD::PCMPISTRI;
16850 X86CC = X86::COND_S;
16852 case Intrinsic::x86_sse42_pcmpestris128:
16853 Opcode = X86ISD::PCMPESTRI;
16854 X86CC = X86::COND_S;
16856 case Intrinsic::x86_sse42_pcmpistriz128:
16857 Opcode = X86ISD::PCMPISTRI;
16858 X86CC = X86::COND_E;
16860 case Intrinsic::x86_sse42_pcmpestriz128:
16861 Opcode = X86ISD::PCMPESTRI;
16862 X86CC = X86::COND_E;
16865 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16866 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16867 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16868 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16869 DAG.getConstant(X86CC, MVT::i8),
16870 SDValue(PCMP.getNode(), 1));
16871 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16874 case Intrinsic::x86_sse42_pcmpistri128:
16875 case Intrinsic::x86_sse42_pcmpestri128: {
16877 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16878 Opcode = X86ISD::PCMPISTRI;
16880 Opcode = X86ISD::PCMPESTRI;
16882 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16883 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16884 return DAG.getNode(Opcode, dl, VTs, NewOps);
16887 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16888 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16889 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16890 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16891 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16892 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16893 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16894 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16895 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16896 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16897 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16898 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16899 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16900 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16901 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16902 dl, Op.getValueType(),
16906 Op.getOperand(4), Op.getOperand(1),
16912 case Intrinsic::x86_fma_vfmadd_ps:
16913 case Intrinsic::x86_fma_vfmadd_pd:
16914 case Intrinsic::x86_fma_vfmsub_ps:
16915 case Intrinsic::x86_fma_vfmsub_pd:
16916 case Intrinsic::x86_fma_vfnmadd_ps:
16917 case Intrinsic::x86_fma_vfnmadd_pd:
16918 case Intrinsic::x86_fma_vfnmsub_ps:
16919 case Intrinsic::x86_fma_vfnmsub_pd:
16920 case Intrinsic::x86_fma_vfmaddsub_ps:
16921 case Intrinsic::x86_fma_vfmaddsub_pd:
16922 case Intrinsic::x86_fma_vfmsubadd_ps:
16923 case Intrinsic::x86_fma_vfmsubadd_pd:
16924 case Intrinsic::x86_fma_vfmadd_ps_256:
16925 case Intrinsic::x86_fma_vfmadd_pd_256:
16926 case Intrinsic::x86_fma_vfmsub_ps_256:
16927 case Intrinsic::x86_fma_vfmsub_pd_256:
16928 case Intrinsic::x86_fma_vfnmadd_ps_256:
16929 case Intrinsic::x86_fma_vfnmadd_pd_256:
16930 case Intrinsic::x86_fma_vfnmsub_ps_256:
16931 case Intrinsic::x86_fma_vfnmsub_pd_256:
16932 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16933 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16934 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16935 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16936 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16937 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16941 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16942 SDValue Src, SDValue Mask, SDValue Base,
16943 SDValue Index, SDValue ScaleOp, SDValue Chain,
16944 const X86Subtarget * Subtarget) {
16946 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16947 assert(C && "Invalid scale type");
16948 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16949 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16950 Index.getSimpleValueType().getVectorNumElements());
16952 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16954 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16956 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16957 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16958 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16959 SDValue Segment = DAG.getRegister(0, MVT::i32);
16960 if (Src.getOpcode() == ISD::UNDEF)
16961 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16962 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16963 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16964 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16965 return DAG.getMergeValues(RetOps, dl);
16968 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16969 SDValue Src, SDValue Mask, SDValue Base,
16970 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16972 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16973 assert(C && "Invalid scale type");
16974 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16975 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16976 SDValue Segment = DAG.getRegister(0, MVT::i32);
16977 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16978 Index.getSimpleValueType().getVectorNumElements());
16980 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16982 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16984 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16985 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16986 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16987 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16988 return SDValue(Res, 1);
16991 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16992 SDValue Mask, SDValue Base, SDValue Index,
16993 SDValue ScaleOp, SDValue Chain) {
16995 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16996 assert(C && "Invalid scale type");
16997 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16998 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16999 SDValue Segment = DAG.getRegister(0, MVT::i32);
17001 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17003 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17005 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17007 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17008 //SDVTList VTs = DAG.getVTList(MVT::Other);
17009 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17010 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17011 return SDValue(Res, 0);
17014 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17015 // read performance monitor counters (x86_rdpmc).
17016 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17017 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17018 SmallVectorImpl<SDValue> &Results) {
17019 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17020 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17023 // The ECX register is used to select the index of the performance counter
17025 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17027 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17029 // Reads the content of a 64-bit performance counter and returns it in the
17030 // registers EDX:EAX.
17031 if (Subtarget->is64Bit()) {
17032 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17033 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17036 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17037 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17040 Chain = HI.getValue(1);
17042 if (Subtarget->is64Bit()) {
17043 // The EAX register is loaded with the low-order 32 bits. The EDX register
17044 // is loaded with the supported high-order bits of the counter.
17045 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17046 DAG.getConstant(32, MVT::i8));
17047 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17048 Results.push_back(Chain);
17052 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17053 SDValue Ops[] = { LO, HI };
17054 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17055 Results.push_back(Pair);
17056 Results.push_back(Chain);
17059 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17060 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17061 // also used to custom lower READCYCLECOUNTER nodes.
17062 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17063 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17064 SmallVectorImpl<SDValue> &Results) {
17065 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17066 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17069 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17070 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17071 // and the EAX register is loaded with the low-order 32 bits.
17072 if (Subtarget->is64Bit()) {
17073 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17074 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17077 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17078 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17081 SDValue Chain = HI.getValue(1);
17083 if (Opcode == X86ISD::RDTSCP_DAG) {
17084 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17086 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17087 // the ECX register. Add 'ecx' explicitly to the chain.
17088 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17090 // Explicitly store the content of ECX at the location passed in input
17091 // to the 'rdtscp' intrinsic.
17092 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17093 MachinePointerInfo(), false, false, 0);
17096 if (Subtarget->is64Bit()) {
17097 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17098 // the EAX register is loaded with the low-order 32 bits.
17099 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17100 DAG.getConstant(32, MVT::i8));
17101 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17102 Results.push_back(Chain);
17106 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17107 SDValue Ops[] = { LO, HI };
17108 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17109 Results.push_back(Pair);
17110 Results.push_back(Chain);
17113 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17114 SelectionDAG &DAG) {
17115 SmallVector<SDValue, 2> Results;
17117 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17119 return DAG.getMergeValues(Results, DL);
17123 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17124 SelectionDAG &DAG) {
17125 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17127 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17132 switch(IntrData->Type) {
17134 llvm_unreachable("Unknown Intrinsic Type");
17138 // Emit the node with the right value type.
17139 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17140 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17142 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17143 // Otherwise return the value from Rand, which is always 0, casted to i32.
17144 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17145 DAG.getConstant(1, Op->getValueType(1)),
17146 DAG.getConstant(X86::COND_B, MVT::i32),
17147 SDValue(Result.getNode(), 1) };
17148 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17149 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17152 // Return { result, isValid, chain }.
17153 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17154 SDValue(Result.getNode(), 2));
17157 //gather(v1, mask, index, base, scale);
17158 SDValue Chain = Op.getOperand(0);
17159 SDValue Src = Op.getOperand(2);
17160 SDValue Base = Op.getOperand(3);
17161 SDValue Index = Op.getOperand(4);
17162 SDValue Mask = Op.getOperand(5);
17163 SDValue Scale = Op.getOperand(6);
17164 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17168 //scatter(base, mask, index, v1, scale);
17169 SDValue Chain = Op.getOperand(0);
17170 SDValue Base = Op.getOperand(2);
17171 SDValue Mask = Op.getOperand(3);
17172 SDValue Index = Op.getOperand(4);
17173 SDValue Src = Op.getOperand(5);
17174 SDValue Scale = Op.getOperand(6);
17175 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17178 SDValue Hint = Op.getOperand(6);
17180 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17181 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17182 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17183 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17184 SDValue Chain = Op.getOperand(0);
17185 SDValue Mask = Op.getOperand(2);
17186 SDValue Index = Op.getOperand(3);
17187 SDValue Base = Op.getOperand(4);
17188 SDValue Scale = Op.getOperand(5);
17189 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17191 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17193 SmallVector<SDValue, 2> Results;
17194 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17195 return DAG.getMergeValues(Results, dl);
17197 // Read Performance Monitoring Counters.
17199 SmallVector<SDValue, 2> Results;
17200 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17201 return DAG.getMergeValues(Results, dl);
17203 // XTEST intrinsics.
17205 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17206 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17207 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17208 DAG.getConstant(X86::COND_NE, MVT::i8),
17210 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17211 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17212 Ret, SDValue(InTrans.getNode(), 1));
17216 SmallVector<SDValue, 2> Results;
17217 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17218 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17219 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17220 DAG.getConstant(-1, MVT::i8));
17221 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17222 Op.getOperand(4), GenCF.getValue(1));
17223 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17224 Op.getOperand(5), MachinePointerInfo(),
17226 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17227 DAG.getConstant(X86::COND_B, MVT::i8),
17229 Results.push_back(SetCC);
17230 Results.push_back(Store);
17231 return DAG.getMergeValues(Results, dl);
17236 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17237 SelectionDAG &DAG) const {
17238 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17239 MFI->setReturnAddressIsTaken(true);
17241 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17244 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17246 EVT PtrVT = getPointerTy();
17249 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17250 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17251 DAG.getSubtarget().getRegisterInfo());
17252 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17253 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17254 DAG.getNode(ISD::ADD, dl, PtrVT,
17255 FrameAddr, Offset),
17256 MachinePointerInfo(), false, false, false, 0);
17259 // Just load the return address.
17260 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17261 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17262 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17265 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17266 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17267 MFI->setFrameAddressIsTaken(true);
17269 EVT VT = Op.getValueType();
17270 SDLoc dl(Op); // FIXME probably not meaningful
17271 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17272 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17273 DAG.getSubtarget().getRegisterInfo());
17274 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17275 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17276 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17277 "Invalid Frame Register!");
17278 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17280 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17281 MachinePointerInfo(),
17282 false, false, false, 0);
17286 // FIXME? Maybe this could be a TableGen attribute on some registers and
17287 // this table could be generated automatically from RegInfo.
17288 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17290 unsigned Reg = StringSwitch<unsigned>(RegName)
17291 .Case("esp", X86::ESP)
17292 .Case("rsp", X86::RSP)
17296 report_fatal_error("Invalid register name global variable");
17299 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17300 SelectionDAG &DAG) const {
17301 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17302 DAG.getSubtarget().getRegisterInfo());
17303 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17306 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17307 SDValue Chain = Op.getOperand(0);
17308 SDValue Offset = Op.getOperand(1);
17309 SDValue Handler = Op.getOperand(2);
17312 EVT PtrVT = getPointerTy();
17313 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17314 DAG.getSubtarget().getRegisterInfo());
17315 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17316 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17317 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17318 "Invalid Frame Register!");
17319 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17320 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17322 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17323 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17324 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17325 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17327 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17329 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17330 DAG.getRegister(StoreAddrReg, PtrVT));
17333 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17334 SelectionDAG &DAG) const {
17336 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17337 DAG.getVTList(MVT::i32, MVT::Other),
17338 Op.getOperand(0), Op.getOperand(1));
17341 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17342 SelectionDAG &DAG) const {
17344 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17345 Op.getOperand(0), Op.getOperand(1));
17348 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17349 return Op.getOperand(0);
17352 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17353 SelectionDAG &DAG) const {
17354 SDValue Root = Op.getOperand(0);
17355 SDValue Trmp = Op.getOperand(1); // trampoline
17356 SDValue FPtr = Op.getOperand(2); // nested function
17357 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17360 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17361 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17363 if (Subtarget->is64Bit()) {
17364 SDValue OutChains[6];
17366 // Large code-model.
17367 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17368 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17370 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17371 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17373 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17375 // Load the pointer to the nested function into R11.
17376 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17377 SDValue Addr = Trmp;
17378 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17379 Addr, MachinePointerInfo(TrmpAddr),
17382 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17383 DAG.getConstant(2, MVT::i64));
17384 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17385 MachinePointerInfo(TrmpAddr, 2),
17388 // Load the 'nest' parameter value into R10.
17389 // R10 is specified in X86CallingConv.td
17390 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17391 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17392 DAG.getConstant(10, MVT::i64));
17393 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17394 Addr, MachinePointerInfo(TrmpAddr, 10),
17397 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17398 DAG.getConstant(12, MVT::i64));
17399 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17400 MachinePointerInfo(TrmpAddr, 12),
17403 // Jump to the nested function.
17404 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17405 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17406 DAG.getConstant(20, MVT::i64));
17407 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17408 Addr, MachinePointerInfo(TrmpAddr, 20),
17411 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17412 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17413 DAG.getConstant(22, MVT::i64));
17414 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17415 MachinePointerInfo(TrmpAddr, 22),
17418 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17420 const Function *Func =
17421 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17422 CallingConv::ID CC = Func->getCallingConv();
17427 llvm_unreachable("Unsupported calling convention");
17428 case CallingConv::C:
17429 case CallingConv::X86_StdCall: {
17430 // Pass 'nest' parameter in ECX.
17431 // Must be kept in sync with X86CallingConv.td
17432 NestReg = X86::ECX;
17434 // Check that ECX wasn't needed by an 'inreg' parameter.
17435 FunctionType *FTy = Func->getFunctionType();
17436 const AttributeSet &Attrs = Func->getAttributes();
17438 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17439 unsigned InRegCount = 0;
17442 for (FunctionType::param_iterator I = FTy->param_begin(),
17443 E = FTy->param_end(); I != E; ++I, ++Idx)
17444 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17445 // FIXME: should only count parameters that are lowered to integers.
17446 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17448 if (InRegCount > 2) {
17449 report_fatal_error("Nest register in use - reduce number of inreg"
17455 case CallingConv::X86_FastCall:
17456 case CallingConv::X86_ThisCall:
17457 case CallingConv::Fast:
17458 // Pass 'nest' parameter in EAX.
17459 // Must be kept in sync with X86CallingConv.td
17460 NestReg = X86::EAX;
17464 SDValue OutChains[4];
17465 SDValue Addr, Disp;
17467 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17468 DAG.getConstant(10, MVT::i32));
17469 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17471 // This is storing the opcode for MOV32ri.
17472 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17473 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17474 OutChains[0] = DAG.getStore(Root, dl,
17475 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17476 Trmp, MachinePointerInfo(TrmpAddr),
17479 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17480 DAG.getConstant(1, MVT::i32));
17481 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17482 MachinePointerInfo(TrmpAddr, 1),
17485 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17486 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17487 DAG.getConstant(5, MVT::i32));
17488 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17489 MachinePointerInfo(TrmpAddr, 5),
17492 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17493 DAG.getConstant(6, MVT::i32));
17494 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17495 MachinePointerInfo(TrmpAddr, 6),
17498 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17502 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17503 SelectionDAG &DAG) const {
17505 The rounding mode is in bits 11:10 of FPSR, and has the following
17507 00 Round to nearest
17512 FLT_ROUNDS, on the other hand, expects the following:
17519 To perform the conversion, we do:
17520 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17523 MachineFunction &MF = DAG.getMachineFunction();
17524 const TargetMachine &TM = MF.getTarget();
17525 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17526 unsigned StackAlignment = TFI.getStackAlignment();
17527 MVT VT = Op.getSimpleValueType();
17530 // Save FP Control Word to stack slot
17531 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17532 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17534 MachineMemOperand *MMO =
17535 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17536 MachineMemOperand::MOStore, 2, 2);
17538 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17539 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17540 DAG.getVTList(MVT::Other),
17541 Ops, MVT::i16, MMO);
17543 // Load FP Control Word from stack slot
17544 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17545 MachinePointerInfo(), false, false, false, 0);
17547 // Transform as necessary
17549 DAG.getNode(ISD::SRL, DL, MVT::i16,
17550 DAG.getNode(ISD::AND, DL, MVT::i16,
17551 CWD, DAG.getConstant(0x800, MVT::i16)),
17552 DAG.getConstant(11, MVT::i8));
17554 DAG.getNode(ISD::SRL, DL, MVT::i16,
17555 DAG.getNode(ISD::AND, DL, MVT::i16,
17556 CWD, DAG.getConstant(0x400, MVT::i16)),
17557 DAG.getConstant(9, MVT::i8));
17560 DAG.getNode(ISD::AND, DL, MVT::i16,
17561 DAG.getNode(ISD::ADD, DL, MVT::i16,
17562 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17563 DAG.getConstant(1, MVT::i16)),
17564 DAG.getConstant(3, MVT::i16));
17566 return DAG.getNode((VT.getSizeInBits() < 16 ?
17567 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17570 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17571 MVT VT = Op.getSimpleValueType();
17573 unsigned NumBits = VT.getSizeInBits();
17576 Op = Op.getOperand(0);
17577 if (VT == MVT::i8) {
17578 // Zero extend to i32 since there is not an i8 bsr.
17580 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17583 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17584 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17585 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17587 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17590 DAG.getConstant(NumBits+NumBits-1, OpVT),
17591 DAG.getConstant(X86::COND_E, MVT::i8),
17594 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17596 // Finally xor with NumBits-1.
17597 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17600 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17604 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17605 MVT VT = Op.getSimpleValueType();
17607 unsigned NumBits = VT.getSizeInBits();
17610 Op = Op.getOperand(0);
17611 if (VT == MVT::i8) {
17612 // Zero extend to i32 since there is not an i8 bsr.
17614 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17617 // Issue a bsr (scan bits in reverse).
17618 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17619 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17621 // And xor with NumBits-1.
17622 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17625 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17629 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17630 MVT VT = Op.getSimpleValueType();
17631 unsigned NumBits = VT.getSizeInBits();
17633 Op = Op.getOperand(0);
17635 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17636 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17637 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17639 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17642 DAG.getConstant(NumBits, VT),
17643 DAG.getConstant(X86::COND_E, MVT::i8),
17646 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17649 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17650 // ones, and then concatenate the result back.
17651 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17652 MVT VT = Op.getSimpleValueType();
17654 assert(VT.is256BitVector() && VT.isInteger() &&
17655 "Unsupported value type for operation");
17657 unsigned NumElems = VT.getVectorNumElements();
17660 // Extract the LHS vectors
17661 SDValue LHS = Op.getOperand(0);
17662 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17663 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17665 // Extract the RHS vectors
17666 SDValue RHS = Op.getOperand(1);
17667 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17668 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17670 MVT EltVT = VT.getVectorElementType();
17671 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17673 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17674 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17675 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17678 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17679 assert(Op.getSimpleValueType().is256BitVector() &&
17680 Op.getSimpleValueType().isInteger() &&
17681 "Only handle AVX 256-bit vector integer operation");
17682 return Lower256IntArith(Op, DAG);
17685 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17686 assert(Op.getSimpleValueType().is256BitVector() &&
17687 Op.getSimpleValueType().isInteger() &&
17688 "Only handle AVX 256-bit vector integer operation");
17689 return Lower256IntArith(Op, DAG);
17692 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17693 SelectionDAG &DAG) {
17695 MVT VT = Op.getSimpleValueType();
17697 // Decompose 256-bit ops into smaller 128-bit ops.
17698 if (VT.is256BitVector() && !Subtarget->hasInt256())
17699 return Lower256IntArith(Op, DAG);
17701 SDValue A = Op.getOperand(0);
17702 SDValue B = Op.getOperand(1);
17704 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17705 if (VT == MVT::v4i32) {
17706 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17707 "Should not custom lower when pmuldq is available!");
17709 // Extract the odd parts.
17710 static const int UnpackMask[] = { 1, -1, 3, -1 };
17711 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17712 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17714 // Multiply the even parts.
17715 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17716 // Now multiply odd parts.
17717 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17719 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17720 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17722 // Merge the two vectors back together with a shuffle. This expands into 2
17724 static const int ShufMask[] = { 0, 4, 2, 6 };
17725 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17728 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17729 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17731 // Ahi = psrlqi(a, 32);
17732 // Bhi = psrlqi(b, 32);
17734 // AloBlo = pmuludq(a, b);
17735 // AloBhi = pmuludq(a, Bhi);
17736 // AhiBlo = pmuludq(Ahi, b);
17738 // AloBhi = psllqi(AloBhi, 32);
17739 // AhiBlo = psllqi(AhiBlo, 32);
17740 // return AloBlo + AloBhi + AhiBlo;
17742 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17743 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17745 // Bit cast to 32-bit vectors for MULUDQ
17746 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17747 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17748 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17749 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17750 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17751 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17753 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17754 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17755 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17757 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17758 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17760 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17761 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17764 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17765 assert(Subtarget->isTargetWin64() && "Unexpected target");
17766 EVT VT = Op.getValueType();
17767 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17768 "Unexpected return type for lowering");
17772 switch (Op->getOpcode()) {
17773 default: llvm_unreachable("Unexpected request for libcall!");
17774 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17775 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17776 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17777 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17778 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17779 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17783 SDValue InChain = DAG.getEntryNode();
17785 TargetLowering::ArgListTy Args;
17786 TargetLowering::ArgListEntry Entry;
17787 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17788 EVT ArgVT = Op->getOperand(i).getValueType();
17789 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17790 "Unexpected argument type for lowering");
17791 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17792 Entry.Node = StackPtr;
17793 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17795 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17796 Entry.Ty = PointerType::get(ArgTy,0);
17797 Entry.isSExt = false;
17798 Entry.isZExt = false;
17799 Args.push_back(Entry);
17802 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17805 TargetLowering::CallLoweringInfo CLI(DAG);
17806 CLI.setDebugLoc(dl).setChain(InChain)
17807 .setCallee(getLibcallCallingConv(LC),
17808 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17809 Callee, std::move(Args), 0)
17810 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17812 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17813 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17816 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17817 SelectionDAG &DAG) {
17818 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17819 EVT VT = Op0.getValueType();
17822 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17823 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17825 // PMULxD operations multiply each even value (starting at 0) of LHS with
17826 // the related value of RHS and produce a widen result.
17827 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17828 // => <2 x i64> <ae|cg>
17830 // In other word, to have all the results, we need to perform two PMULxD:
17831 // 1. one with the even values.
17832 // 2. one with the odd values.
17833 // To achieve #2, with need to place the odd values at an even position.
17835 // Place the odd value at an even position (basically, shift all values 1
17836 // step to the left):
17837 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17838 // <a|b|c|d> => <b|undef|d|undef>
17839 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17840 // <e|f|g|h> => <f|undef|h|undef>
17841 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17843 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17845 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17846 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17848 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17849 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17850 // => <2 x i64> <ae|cg>
17851 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17852 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17853 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17854 // => <2 x i64> <bf|dh>
17855 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17856 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17858 // Shuffle it back into the right order.
17859 SDValue Highs, Lows;
17860 if (VT == MVT::v8i32) {
17861 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17862 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17863 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17864 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17866 const int HighMask[] = {1, 5, 3, 7};
17867 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17868 const int LowMask[] = {0, 4, 2, 6};
17869 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17872 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17873 // unsigned multiply.
17874 if (IsSigned && !Subtarget->hasSSE41()) {
17876 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17877 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17878 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17879 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17880 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17882 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17883 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17886 // The first result of MUL_LOHI is actually the low value, followed by the
17888 SDValue Ops[] = {Lows, Highs};
17889 return DAG.getMergeValues(Ops, dl);
17892 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17893 const X86Subtarget *Subtarget) {
17894 MVT VT = Op.getSimpleValueType();
17896 SDValue R = Op.getOperand(0);
17897 SDValue Amt = Op.getOperand(1);
17899 // Optimize shl/srl/sra with constant shift amount.
17900 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17901 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17902 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17904 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17905 (Subtarget->hasInt256() &&
17906 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17907 (Subtarget->hasAVX512() &&
17908 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17909 if (Op.getOpcode() == ISD::SHL)
17910 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17912 if (Op.getOpcode() == ISD::SRL)
17913 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17915 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17916 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17920 if (VT == MVT::v16i8) {
17921 if (Op.getOpcode() == ISD::SHL) {
17922 // Make a large shift.
17923 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17924 MVT::v8i16, R, ShiftAmt,
17926 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17927 // Zero out the rightmost bits.
17928 SmallVector<SDValue, 16> V(16,
17929 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17931 return DAG.getNode(ISD::AND, dl, VT, SHL,
17932 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17934 if (Op.getOpcode() == ISD::SRL) {
17935 // Make a large shift.
17936 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17937 MVT::v8i16, R, ShiftAmt,
17939 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17940 // Zero out the leftmost bits.
17941 SmallVector<SDValue, 16> V(16,
17942 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17944 return DAG.getNode(ISD::AND, dl, VT, SRL,
17945 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17947 if (Op.getOpcode() == ISD::SRA) {
17948 if (ShiftAmt == 7) {
17949 // R s>> 7 === R s< 0
17950 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17951 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17954 // R s>> a === ((R u>> a) ^ m) - m
17955 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17956 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17958 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17959 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17960 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17963 llvm_unreachable("Unknown shift opcode.");
17966 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17967 if (Op.getOpcode() == ISD::SHL) {
17968 // Make a large shift.
17969 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17970 MVT::v16i16, R, ShiftAmt,
17972 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17973 // Zero out the rightmost bits.
17974 SmallVector<SDValue, 32> V(32,
17975 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17977 return DAG.getNode(ISD::AND, dl, VT, SHL,
17978 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17980 if (Op.getOpcode() == ISD::SRL) {
17981 // Make a large shift.
17982 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17983 MVT::v16i16, R, ShiftAmt,
17985 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17986 // Zero out the leftmost bits.
17987 SmallVector<SDValue, 32> V(32,
17988 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17990 return DAG.getNode(ISD::AND, dl, VT, SRL,
17991 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17993 if (Op.getOpcode() == ISD::SRA) {
17994 if (ShiftAmt == 7) {
17995 // R s>> 7 === R s< 0
17996 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17997 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18000 // R s>> a === ((R u>> a) ^ m) - m
18001 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18002 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18004 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18005 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18006 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18009 llvm_unreachable("Unknown shift opcode.");
18014 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18015 if (!Subtarget->is64Bit() &&
18016 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18017 Amt.getOpcode() == ISD::BITCAST &&
18018 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18019 Amt = Amt.getOperand(0);
18020 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18021 VT.getVectorNumElements();
18022 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18023 uint64_t ShiftAmt = 0;
18024 for (unsigned i = 0; i != Ratio; ++i) {
18025 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18029 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18031 // Check remaining shift amounts.
18032 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18033 uint64_t ShAmt = 0;
18034 for (unsigned j = 0; j != Ratio; ++j) {
18035 ConstantSDNode *C =
18036 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18040 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18042 if (ShAmt != ShiftAmt)
18045 switch (Op.getOpcode()) {
18047 llvm_unreachable("Unknown shift opcode!");
18049 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18052 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18055 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18063 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18064 const X86Subtarget* Subtarget) {
18065 MVT VT = Op.getSimpleValueType();
18067 SDValue R = Op.getOperand(0);
18068 SDValue Amt = Op.getOperand(1);
18070 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18071 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18072 (Subtarget->hasInt256() &&
18073 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18074 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18075 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18077 EVT EltVT = VT.getVectorElementType();
18079 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18080 unsigned NumElts = VT.getVectorNumElements();
18082 for (i = 0; i != NumElts; ++i) {
18083 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
18087 for (j = i; j != NumElts; ++j) {
18088 SDValue Arg = Amt.getOperand(j);
18089 if (Arg.getOpcode() == ISD::UNDEF) continue;
18090 if (Arg != Amt.getOperand(i))
18093 if (i != NumElts && j == NumElts)
18094 BaseShAmt = Amt.getOperand(i);
18096 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18097 Amt = Amt.getOperand(0);
18098 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18099 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18100 SDValue InVec = Amt.getOperand(0);
18101 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18102 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18104 for (; i != NumElts; ++i) {
18105 SDValue Arg = InVec.getOperand(i);
18106 if (Arg.getOpcode() == ISD::UNDEF) continue;
18110 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18111 if (ConstantSDNode *C =
18112 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18113 unsigned SplatIdx =
18114 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18115 if (C->getZExtValue() == SplatIdx)
18116 BaseShAmt = InVec.getOperand(1);
18119 if (!BaseShAmt.getNode())
18120 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18121 DAG.getIntPtrConstant(0));
18125 if (BaseShAmt.getNode()) {
18126 if (EltVT.bitsGT(MVT::i32))
18127 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18128 else if (EltVT.bitsLT(MVT::i32))
18129 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18131 switch (Op.getOpcode()) {
18133 llvm_unreachable("Unknown shift opcode!");
18135 switch (VT.SimpleTy) {
18136 default: return SDValue();
18145 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18148 switch (VT.SimpleTy) {
18149 default: return SDValue();
18156 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18159 switch (VT.SimpleTy) {
18160 default: return SDValue();
18169 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18175 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18176 if (!Subtarget->is64Bit() &&
18177 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18178 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18179 Amt.getOpcode() == ISD::BITCAST &&
18180 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18181 Amt = Amt.getOperand(0);
18182 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18183 VT.getVectorNumElements();
18184 std::vector<SDValue> Vals(Ratio);
18185 for (unsigned i = 0; i != Ratio; ++i)
18186 Vals[i] = Amt.getOperand(i);
18187 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18188 for (unsigned j = 0; j != Ratio; ++j)
18189 if (Vals[j] != Amt.getOperand(i + j))
18192 switch (Op.getOpcode()) {
18194 llvm_unreachable("Unknown shift opcode!");
18196 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18198 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18200 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18207 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18208 SelectionDAG &DAG) {
18209 MVT VT = Op.getSimpleValueType();
18211 SDValue R = Op.getOperand(0);
18212 SDValue Amt = Op.getOperand(1);
18215 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18216 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18218 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18222 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18226 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18228 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18229 if (Subtarget->hasInt256()) {
18230 if (Op.getOpcode() == ISD::SRL &&
18231 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18232 VT == MVT::v4i64 || VT == MVT::v8i32))
18234 if (Op.getOpcode() == ISD::SHL &&
18235 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18236 VT == MVT::v4i64 || VT == MVT::v8i32))
18238 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18242 // If possible, lower this packed shift into a vector multiply instead of
18243 // expanding it into a sequence of scalar shifts.
18244 // Do this only if the vector shift count is a constant build_vector.
18245 if (Op.getOpcode() == ISD::SHL &&
18246 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18247 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18248 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18249 SmallVector<SDValue, 8> Elts;
18250 EVT SVT = VT.getScalarType();
18251 unsigned SVTBits = SVT.getSizeInBits();
18252 const APInt &One = APInt(SVTBits, 1);
18253 unsigned NumElems = VT.getVectorNumElements();
18255 for (unsigned i=0; i !=NumElems; ++i) {
18256 SDValue Op = Amt->getOperand(i);
18257 if (Op->getOpcode() == ISD::UNDEF) {
18258 Elts.push_back(Op);
18262 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18263 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18264 uint64_t ShAmt = C.getZExtValue();
18265 if (ShAmt >= SVTBits) {
18266 Elts.push_back(DAG.getUNDEF(SVT));
18269 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18271 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18272 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18275 // Lower SHL with variable shift amount.
18276 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18277 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18279 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18280 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18281 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18282 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18285 // If possible, lower this shift as a sequence of two shifts by
18286 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18288 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18290 // Could be rewritten as:
18291 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18293 // The advantage is that the two shifts from the example would be
18294 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18295 // the vector shift into four scalar shifts plus four pairs of vector
18297 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18298 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18299 unsigned TargetOpcode = X86ISD::MOVSS;
18300 bool CanBeSimplified;
18301 // The splat value for the first packed shift (the 'X' from the example).
18302 SDValue Amt1 = Amt->getOperand(0);
18303 // The splat value for the second packed shift (the 'Y' from the example).
18304 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18305 Amt->getOperand(2);
18307 // See if it is possible to replace this node with a sequence of
18308 // two shifts followed by a MOVSS/MOVSD
18309 if (VT == MVT::v4i32) {
18310 // Check if it is legal to use a MOVSS.
18311 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18312 Amt2 == Amt->getOperand(3);
18313 if (!CanBeSimplified) {
18314 // Otherwise, check if we can still simplify this node using a MOVSD.
18315 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18316 Amt->getOperand(2) == Amt->getOperand(3);
18317 TargetOpcode = X86ISD::MOVSD;
18318 Amt2 = Amt->getOperand(2);
18321 // Do similar checks for the case where the machine value type
18323 CanBeSimplified = Amt1 == Amt->getOperand(1);
18324 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18325 CanBeSimplified = Amt2 == Amt->getOperand(i);
18327 if (!CanBeSimplified) {
18328 TargetOpcode = X86ISD::MOVSD;
18329 CanBeSimplified = true;
18330 Amt2 = Amt->getOperand(4);
18331 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18332 CanBeSimplified = Amt1 == Amt->getOperand(i);
18333 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18334 CanBeSimplified = Amt2 == Amt->getOperand(j);
18338 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18339 isa<ConstantSDNode>(Amt2)) {
18340 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18341 EVT CastVT = MVT::v4i32;
18343 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18344 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18346 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18347 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18348 if (TargetOpcode == X86ISD::MOVSD)
18349 CastVT = MVT::v2i64;
18350 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18351 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18352 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18354 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18358 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18359 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18362 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18363 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18365 // Turn 'a' into a mask suitable for VSELECT
18366 SDValue VSelM = DAG.getConstant(0x80, VT);
18367 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18368 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18370 SDValue CM1 = DAG.getConstant(0x0f, VT);
18371 SDValue CM2 = DAG.getConstant(0x3f, VT);
18373 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18374 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18375 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18376 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18377 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18380 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18381 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18382 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18384 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18385 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18386 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18387 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18388 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18391 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18392 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18393 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18395 // return VSELECT(r, r+r, a);
18396 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18397 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18401 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18402 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18403 // solution better.
18404 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18405 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18407 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18408 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18409 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18410 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18411 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18414 // Decompose 256-bit shifts into smaller 128-bit shifts.
18415 if (VT.is256BitVector()) {
18416 unsigned NumElems = VT.getVectorNumElements();
18417 MVT EltVT = VT.getVectorElementType();
18418 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18420 // Extract the two vectors
18421 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18422 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18424 // Recreate the shift amount vectors
18425 SDValue Amt1, Amt2;
18426 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18427 // Constant shift amount
18428 SmallVector<SDValue, 4> Amt1Csts;
18429 SmallVector<SDValue, 4> Amt2Csts;
18430 for (unsigned i = 0; i != NumElems/2; ++i)
18431 Amt1Csts.push_back(Amt->getOperand(i));
18432 for (unsigned i = NumElems/2; i != NumElems; ++i)
18433 Amt2Csts.push_back(Amt->getOperand(i));
18435 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18436 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18438 // Variable shift amount
18439 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18440 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18443 // Issue new vector shifts for the smaller types
18444 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18445 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18447 // Concatenate the result back
18448 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18454 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18455 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18456 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18457 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18458 // has only one use.
18459 SDNode *N = Op.getNode();
18460 SDValue LHS = N->getOperand(0);
18461 SDValue RHS = N->getOperand(1);
18462 unsigned BaseOp = 0;
18465 switch (Op.getOpcode()) {
18466 default: llvm_unreachable("Unknown ovf instruction!");
18468 // A subtract of one will be selected as a INC. Note that INC doesn't
18469 // set CF, so we can't do this for UADDO.
18470 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18472 BaseOp = X86ISD::INC;
18473 Cond = X86::COND_O;
18476 BaseOp = X86ISD::ADD;
18477 Cond = X86::COND_O;
18480 BaseOp = X86ISD::ADD;
18481 Cond = X86::COND_B;
18484 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18485 // set CF, so we can't do this for USUBO.
18486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18488 BaseOp = X86ISD::DEC;
18489 Cond = X86::COND_O;
18492 BaseOp = X86ISD::SUB;
18493 Cond = X86::COND_O;
18496 BaseOp = X86ISD::SUB;
18497 Cond = X86::COND_B;
18500 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18501 Cond = X86::COND_O;
18503 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18504 if (N->getValueType(0) == MVT::i8) {
18505 BaseOp = X86ISD::UMUL8;
18506 Cond = X86::COND_O;
18509 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18511 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18514 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18515 DAG.getConstant(X86::COND_O, MVT::i32),
18516 SDValue(Sum.getNode(), 2));
18518 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18522 // Also sets EFLAGS.
18523 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18524 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18527 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18528 DAG.getConstant(Cond, MVT::i32),
18529 SDValue(Sum.getNode(), 1));
18531 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18534 // Sign extension of the low part of vector elements. This may be used either
18535 // when sign extend instructions are not available or if the vector element
18536 // sizes already match the sign-extended size. If the vector elements are in
18537 // their pre-extended size and sign extend instructions are available, that will
18538 // be handled by LowerSIGN_EXTEND.
18539 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18540 SelectionDAG &DAG) const {
18542 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18543 MVT VT = Op.getSimpleValueType();
18545 if (!Subtarget->hasSSE2() || !VT.isVector())
18548 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18549 ExtraVT.getScalarType().getSizeInBits();
18551 switch (VT.SimpleTy) {
18552 default: return SDValue();
18555 if (!Subtarget->hasFp256())
18557 if (!Subtarget->hasInt256()) {
18558 // needs to be split
18559 unsigned NumElems = VT.getVectorNumElements();
18561 // Extract the LHS vectors
18562 SDValue LHS = Op.getOperand(0);
18563 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18564 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18566 MVT EltVT = VT.getVectorElementType();
18567 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18569 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18570 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18571 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18573 SDValue Extra = DAG.getValueType(ExtraVT);
18575 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18576 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18578 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18583 SDValue Op0 = Op.getOperand(0);
18585 // This is a sign extension of some low part of vector elements without
18586 // changing the size of the vector elements themselves:
18587 // Shift-Left + Shift-Right-Algebraic.
18588 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18590 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18596 /// Returns true if the operand type is exactly twice the native width, and
18597 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18598 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18599 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18600 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18601 const X86Subtarget &Subtarget =
18602 getTargetMachine().getSubtarget<X86Subtarget>();
18603 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18606 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18607 else if (OpWidth == 128)
18608 return Subtarget.hasCmpxchg16b();
18613 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18614 return needsCmpXchgNb(SI->getValueOperand()->getType());
18617 // Note: this turns large loads into lock cmpxchg8b/16b.
18618 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18619 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18620 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18621 return needsCmpXchgNb(PTy->getElementType());
18624 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18625 const X86Subtarget &Subtarget =
18626 getTargetMachine().getSubtarget<X86Subtarget>();
18627 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18628 const Type *MemType = AI->getType();
18630 // If the operand is too big, we must see if cmpxchg8/16b is available
18631 // and default to library calls otherwise.
18632 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18633 return needsCmpXchgNb(MemType);
18635 AtomicRMWInst::BinOp Op = AI->getOperation();
18638 llvm_unreachable("Unknown atomic operation");
18639 case AtomicRMWInst::Xchg:
18640 case AtomicRMWInst::Add:
18641 case AtomicRMWInst::Sub:
18642 // It's better to use xadd, xsub or xchg for these in all cases.
18644 case AtomicRMWInst::Or:
18645 case AtomicRMWInst::And:
18646 case AtomicRMWInst::Xor:
18647 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18648 // prefix to a normal instruction for these operations.
18649 return !AI->use_empty();
18650 case AtomicRMWInst::Nand:
18651 case AtomicRMWInst::Max:
18652 case AtomicRMWInst::Min:
18653 case AtomicRMWInst::UMax:
18654 case AtomicRMWInst::UMin:
18655 // These always require a non-trivial set of data operations on x86. We must
18656 // use a cmpxchg loop.
18661 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18662 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18663 // no-sse2). There isn't any reason to disable it if the target processor
18665 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18669 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18670 const X86Subtarget &Subtarget =
18671 getTargetMachine().getSubtarget<X86Subtarget>();
18672 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18673 const Type *MemType = AI->getType();
18674 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18675 // there is no benefit in turning such RMWs into loads, and it is actually
18676 // harmful as it introduces a mfence.
18677 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18680 auto Builder = IRBuilder<>(AI);
18681 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18682 auto SynchScope = AI->getSynchScope();
18683 // We must restrict the ordering to avoid generating loads with Release or
18684 // ReleaseAcquire orderings.
18685 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18686 auto Ptr = AI->getPointerOperand();
18688 // Before the load we need a fence. Here is an example lifted from
18689 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18692 // x.store(1, relaxed);
18693 // r1 = y.fetch_add(0, release);
18695 // y.fetch_add(42, acquire);
18696 // r2 = x.load(relaxed);
18697 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18698 // lowered to just a load without a fence. A mfence flushes the store buffer,
18699 // making the optimization clearly correct.
18700 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18701 // otherwise, we might be able to be more agressive on relaxed idempotent
18702 // rmw. In practice, they do not look useful, so we don't try to be
18703 // especially clever.
18704 if (SynchScope == SingleThread) {
18705 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18706 // the IR level, so we must wrap it in an intrinsic.
18708 } else if (hasMFENCE(Subtarget)) {
18709 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18710 Intrinsic::x86_sse2_mfence);
18711 Builder.CreateCall(MFence);
18713 // FIXME: it might make sense to use a locked operation here but on a
18714 // different cache-line to prevent cache-line bouncing. In practice it
18715 // is probably a small win, and x86 processors without mfence are rare
18716 // enough that we do not bother.
18720 // Finally we can emit the atomic load.
18721 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18722 AI->getType()->getPrimitiveSizeInBits());
18723 Loaded->setAtomic(Order, SynchScope);
18724 AI->replaceAllUsesWith(Loaded);
18725 AI->eraseFromParent();
18729 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18730 SelectionDAG &DAG) {
18732 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18733 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18734 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18735 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18737 // The only fence that needs an instruction is a sequentially-consistent
18738 // cross-thread fence.
18739 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18740 if (hasMFENCE(*Subtarget))
18741 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18743 SDValue Chain = Op.getOperand(0);
18744 SDValue Zero = DAG.getConstant(0, MVT::i32);
18746 DAG.getRegister(X86::ESP, MVT::i32), // Base
18747 DAG.getTargetConstant(1, MVT::i8), // Scale
18748 DAG.getRegister(0, MVT::i32), // Index
18749 DAG.getTargetConstant(0, MVT::i32), // Disp
18750 DAG.getRegister(0, MVT::i32), // Segment.
18754 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18755 return SDValue(Res, 0);
18758 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18759 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18762 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18763 SelectionDAG &DAG) {
18764 MVT T = Op.getSimpleValueType();
18768 switch(T.SimpleTy) {
18769 default: llvm_unreachable("Invalid value type!");
18770 case MVT::i8: Reg = X86::AL; size = 1; break;
18771 case MVT::i16: Reg = X86::AX; size = 2; break;
18772 case MVT::i32: Reg = X86::EAX; size = 4; break;
18774 assert(Subtarget->is64Bit() && "Node not type legal!");
18775 Reg = X86::RAX; size = 8;
18778 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18779 Op.getOperand(2), SDValue());
18780 SDValue Ops[] = { cpIn.getValue(0),
18783 DAG.getTargetConstant(size, MVT::i8),
18784 cpIn.getValue(1) };
18785 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18786 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18787 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18791 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18792 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18793 MVT::i32, cpOut.getValue(2));
18794 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18795 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18797 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18798 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18799 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18803 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18804 SelectionDAG &DAG) {
18805 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18806 MVT DstVT = Op.getSimpleValueType();
18808 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18809 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18810 if (DstVT != MVT::f64)
18811 // This conversion needs to be expanded.
18814 SDValue InVec = Op->getOperand(0);
18816 unsigned NumElts = SrcVT.getVectorNumElements();
18817 EVT SVT = SrcVT.getVectorElementType();
18819 // Widen the vector in input in the case of MVT::v2i32.
18820 // Example: from MVT::v2i32 to MVT::v4i32.
18821 SmallVector<SDValue, 16> Elts;
18822 for (unsigned i = 0, e = NumElts; i != e; ++i)
18823 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18824 DAG.getIntPtrConstant(i)));
18826 // Explicitly mark the extra elements as Undef.
18827 SDValue Undef = DAG.getUNDEF(SVT);
18828 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18829 Elts.push_back(Undef);
18831 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18832 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18833 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18834 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18835 DAG.getIntPtrConstant(0));
18838 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18839 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18840 assert((DstVT == MVT::i64 ||
18841 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18842 "Unexpected custom BITCAST");
18843 // i64 <=> MMX conversions are Legal.
18844 if (SrcVT==MVT::i64 && DstVT.isVector())
18846 if (DstVT==MVT::i64 && SrcVT.isVector())
18848 // MMX <=> MMX conversions are Legal.
18849 if (SrcVT.isVector() && DstVT.isVector())
18851 // All other conversions need to be expanded.
18855 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18856 SDNode *Node = Op.getNode();
18858 EVT T = Node->getValueType(0);
18859 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18860 DAG.getConstant(0, T), Node->getOperand(2));
18861 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18862 cast<AtomicSDNode>(Node)->getMemoryVT(),
18863 Node->getOperand(0),
18864 Node->getOperand(1), negOp,
18865 cast<AtomicSDNode>(Node)->getMemOperand(),
18866 cast<AtomicSDNode>(Node)->getOrdering(),
18867 cast<AtomicSDNode>(Node)->getSynchScope());
18870 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18871 SDNode *Node = Op.getNode();
18873 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18875 // Convert seq_cst store -> xchg
18876 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18877 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18878 // (The only way to get a 16-byte store is cmpxchg16b)
18879 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18880 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18881 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18882 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18883 cast<AtomicSDNode>(Node)->getMemoryVT(),
18884 Node->getOperand(0),
18885 Node->getOperand(1), Node->getOperand(2),
18886 cast<AtomicSDNode>(Node)->getMemOperand(),
18887 cast<AtomicSDNode>(Node)->getOrdering(),
18888 cast<AtomicSDNode>(Node)->getSynchScope());
18889 return Swap.getValue(1);
18891 // Other atomic stores have a simple pattern.
18895 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18896 EVT VT = Op.getNode()->getSimpleValueType(0);
18898 // Let legalize expand this if it isn't a legal type yet.
18899 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18902 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18905 bool ExtraOp = false;
18906 switch (Op.getOpcode()) {
18907 default: llvm_unreachable("Invalid code");
18908 case ISD::ADDC: Opc = X86ISD::ADD; break;
18909 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18910 case ISD::SUBC: Opc = X86ISD::SUB; break;
18911 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18915 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18917 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18918 Op.getOperand(1), Op.getOperand(2));
18921 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18922 SelectionDAG &DAG) {
18923 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18925 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18926 // which returns the values as { float, float } (in XMM0) or
18927 // { double, double } (which is returned in XMM0, XMM1).
18929 SDValue Arg = Op.getOperand(0);
18930 EVT ArgVT = Arg.getValueType();
18931 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18933 TargetLowering::ArgListTy Args;
18934 TargetLowering::ArgListEntry Entry;
18938 Entry.isSExt = false;
18939 Entry.isZExt = false;
18940 Args.push_back(Entry);
18942 bool isF64 = ArgVT == MVT::f64;
18943 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18944 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18945 // the results are returned via SRet in memory.
18946 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18947 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18948 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18950 Type *RetTy = isF64
18951 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18952 : (Type*)VectorType::get(ArgTy, 4);
18954 TargetLowering::CallLoweringInfo CLI(DAG);
18955 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18956 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18958 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18961 // Returned in xmm0 and xmm1.
18962 return CallResult.first;
18964 // Returned in bits 0:31 and 32:64 xmm0.
18965 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18966 CallResult.first, DAG.getIntPtrConstant(0));
18967 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18968 CallResult.first, DAG.getIntPtrConstant(1));
18969 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18970 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18973 /// LowerOperation - Provide custom lowering hooks for some operations.
18975 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18976 switch (Op.getOpcode()) {
18977 default: llvm_unreachable("Should not custom lower this!");
18978 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18979 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18980 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18981 return LowerCMP_SWAP(Op, Subtarget, DAG);
18982 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18983 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18984 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18985 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18986 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18987 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18988 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18989 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18990 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18991 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18992 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18993 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18994 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18995 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18996 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18997 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18998 case ISD::SHL_PARTS:
18999 case ISD::SRA_PARTS:
19000 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19001 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19002 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19003 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19004 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19005 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19006 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19007 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19008 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19009 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19010 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19012 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19013 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19014 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19015 case ISD::SETCC: return LowerSETCC(Op, DAG);
19016 case ISD::SELECT: return LowerSELECT(Op, DAG);
19017 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19018 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19019 case ISD::VASTART: return LowerVASTART(Op, DAG);
19020 case ISD::VAARG: return LowerVAARG(Op, DAG);
19021 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19022 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19023 case ISD::INTRINSIC_VOID:
19024 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19025 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19026 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19027 case ISD::FRAME_TO_ARGS_OFFSET:
19028 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19029 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19030 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19031 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19032 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19033 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19034 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19035 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19036 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19037 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19038 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19039 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19040 case ISD::UMUL_LOHI:
19041 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19044 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19050 case ISD::UMULO: return LowerXALUO(Op, DAG);
19051 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19052 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19056 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19057 case ISD::ADD: return LowerADD(Op, DAG);
19058 case ISD::SUB: return LowerSUB(Op, DAG);
19059 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19063 /// ReplaceNodeResults - Replace a node with an illegal result type
19064 /// with a new node built out of custom code.
19065 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19066 SmallVectorImpl<SDValue>&Results,
19067 SelectionDAG &DAG) const {
19069 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19070 switch (N->getOpcode()) {
19072 llvm_unreachable("Do not know how to custom type legalize this operation!");
19073 case ISD::SIGN_EXTEND_INREG:
19078 // We don't want to expand or promote these.
19085 case ISD::UDIVREM: {
19086 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19087 Results.push_back(V);
19090 case ISD::FP_TO_SINT:
19091 case ISD::FP_TO_UINT: {
19092 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19094 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19097 std::pair<SDValue,SDValue> Vals =
19098 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19099 SDValue FIST = Vals.first, StackSlot = Vals.second;
19100 if (FIST.getNode()) {
19101 EVT VT = N->getValueType(0);
19102 // Return a load from the stack slot.
19103 if (StackSlot.getNode())
19104 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19105 MachinePointerInfo(),
19106 false, false, false, 0));
19108 Results.push_back(FIST);
19112 case ISD::UINT_TO_FP: {
19113 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19114 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19115 N->getValueType(0) != MVT::v2f32)
19117 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19119 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19121 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19122 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19123 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19124 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19125 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19126 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19129 case ISD::FP_ROUND: {
19130 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19132 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19133 Results.push_back(V);
19136 case ISD::INTRINSIC_W_CHAIN: {
19137 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19139 default : llvm_unreachable("Do not know how to custom type "
19140 "legalize this intrinsic operation!");
19141 case Intrinsic::x86_rdtsc:
19142 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19144 case Intrinsic::x86_rdtscp:
19145 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19147 case Intrinsic::x86_rdpmc:
19148 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19151 case ISD::READCYCLECOUNTER: {
19152 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19155 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19156 EVT T = N->getValueType(0);
19157 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19158 bool Regs64bit = T == MVT::i128;
19159 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19160 SDValue cpInL, cpInH;
19161 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19162 DAG.getConstant(0, HalfT));
19163 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19164 DAG.getConstant(1, HalfT));
19165 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19166 Regs64bit ? X86::RAX : X86::EAX,
19168 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19169 Regs64bit ? X86::RDX : X86::EDX,
19170 cpInH, cpInL.getValue(1));
19171 SDValue swapInL, swapInH;
19172 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19173 DAG.getConstant(0, HalfT));
19174 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19175 DAG.getConstant(1, HalfT));
19176 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19177 Regs64bit ? X86::RBX : X86::EBX,
19178 swapInL, cpInH.getValue(1));
19179 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19180 Regs64bit ? X86::RCX : X86::ECX,
19181 swapInH, swapInL.getValue(1));
19182 SDValue Ops[] = { swapInH.getValue(0),
19184 swapInH.getValue(1) };
19185 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19186 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19187 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19188 X86ISD::LCMPXCHG8_DAG;
19189 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19190 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19191 Regs64bit ? X86::RAX : X86::EAX,
19192 HalfT, Result.getValue(1));
19193 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19194 Regs64bit ? X86::RDX : X86::EDX,
19195 HalfT, cpOutL.getValue(2));
19196 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19198 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19199 MVT::i32, cpOutH.getValue(2));
19201 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19202 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19203 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19205 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19206 Results.push_back(Success);
19207 Results.push_back(EFLAGS.getValue(1));
19210 case ISD::ATOMIC_SWAP:
19211 case ISD::ATOMIC_LOAD_ADD:
19212 case ISD::ATOMIC_LOAD_SUB:
19213 case ISD::ATOMIC_LOAD_AND:
19214 case ISD::ATOMIC_LOAD_OR:
19215 case ISD::ATOMIC_LOAD_XOR:
19216 case ISD::ATOMIC_LOAD_NAND:
19217 case ISD::ATOMIC_LOAD_MIN:
19218 case ISD::ATOMIC_LOAD_MAX:
19219 case ISD::ATOMIC_LOAD_UMIN:
19220 case ISD::ATOMIC_LOAD_UMAX:
19221 case ISD::ATOMIC_LOAD: {
19222 // Delegate to generic TypeLegalization. Situations we can really handle
19223 // should have already been dealt with by AtomicExpandPass.cpp.
19226 case ISD::BITCAST: {
19227 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19228 EVT DstVT = N->getValueType(0);
19229 EVT SrcVT = N->getOperand(0)->getValueType(0);
19231 if (SrcVT != MVT::f64 ||
19232 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19235 unsigned NumElts = DstVT.getVectorNumElements();
19236 EVT SVT = DstVT.getVectorElementType();
19237 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19238 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19239 MVT::v2f64, N->getOperand(0));
19240 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19242 if (ExperimentalVectorWideningLegalization) {
19243 // If we are legalizing vectors by widening, we already have the desired
19244 // legal vector type, just return it.
19245 Results.push_back(ToVecInt);
19249 SmallVector<SDValue, 8> Elts;
19250 for (unsigned i = 0, e = NumElts; i != e; ++i)
19251 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19252 ToVecInt, DAG.getIntPtrConstant(i)));
19254 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19259 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19261 default: return nullptr;
19262 case X86ISD::BSF: return "X86ISD::BSF";
19263 case X86ISD::BSR: return "X86ISD::BSR";
19264 case X86ISD::SHLD: return "X86ISD::SHLD";
19265 case X86ISD::SHRD: return "X86ISD::SHRD";
19266 case X86ISD::FAND: return "X86ISD::FAND";
19267 case X86ISD::FANDN: return "X86ISD::FANDN";
19268 case X86ISD::FOR: return "X86ISD::FOR";
19269 case X86ISD::FXOR: return "X86ISD::FXOR";
19270 case X86ISD::FSRL: return "X86ISD::FSRL";
19271 case X86ISD::FILD: return "X86ISD::FILD";
19272 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19273 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19274 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19275 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19276 case X86ISD::FLD: return "X86ISD::FLD";
19277 case X86ISD::FST: return "X86ISD::FST";
19278 case X86ISD::CALL: return "X86ISD::CALL";
19279 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19280 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19281 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19282 case X86ISD::BT: return "X86ISD::BT";
19283 case X86ISD::CMP: return "X86ISD::CMP";
19284 case X86ISD::COMI: return "X86ISD::COMI";
19285 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19286 case X86ISD::CMPM: return "X86ISD::CMPM";
19287 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19288 case X86ISD::SETCC: return "X86ISD::SETCC";
19289 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19290 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19291 case X86ISD::CMOV: return "X86ISD::CMOV";
19292 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19293 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19294 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19295 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19296 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19297 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19298 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19299 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19300 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19301 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19302 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19303 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19304 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19305 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19306 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19307 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19308 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19309 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19310 case X86ISD::HADD: return "X86ISD::HADD";
19311 case X86ISD::HSUB: return "X86ISD::HSUB";
19312 case X86ISD::FHADD: return "X86ISD::FHADD";
19313 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19314 case X86ISD::UMAX: return "X86ISD::UMAX";
19315 case X86ISD::UMIN: return "X86ISD::UMIN";
19316 case X86ISD::SMAX: return "X86ISD::SMAX";
19317 case X86ISD::SMIN: return "X86ISD::SMIN";
19318 case X86ISD::FMAX: return "X86ISD::FMAX";
19319 case X86ISD::FMIN: return "X86ISD::FMIN";
19320 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19321 case X86ISD::FMINC: return "X86ISD::FMINC";
19322 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19323 case X86ISD::FRCP: return "X86ISD::FRCP";
19324 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19325 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19326 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19327 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19328 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19329 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19330 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19331 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19332 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19333 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19334 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19335 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19336 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19337 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19338 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19339 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19340 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19341 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19342 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19343 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19344 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19345 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19346 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19347 case X86ISD::VSHL: return "X86ISD::VSHL";
19348 case X86ISD::VSRL: return "X86ISD::VSRL";
19349 case X86ISD::VSRA: return "X86ISD::VSRA";
19350 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19351 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19352 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19353 case X86ISD::CMPP: return "X86ISD::CMPP";
19354 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19355 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19356 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19357 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19358 case X86ISD::ADD: return "X86ISD::ADD";
19359 case X86ISD::SUB: return "X86ISD::SUB";
19360 case X86ISD::ADC: return "X86ISD::ADC";
19361 case X86ISD::SBB: return "X86ISD::SBB";
19362 case X86ISD::SMUL: return "X86ISD::SMUL";
19363 case X86ISD::UMUL: return "X86ISD::UMUL";
19364 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19365 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19366 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19367 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19368 case X86ISD::INC: return "X86ISD::INC";
19369 case X86ISD::DEC: return "X86ISD::DEC";
19370 case X86ISD::OR: return "X86ISD::OR";
19371 case X86ISD::XOR: return "X86ISD::XOR";
19372 case X86ISD::AND: return "X86ISD::AND";
19373 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19374 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19375 case X86ISD::PTEST: return "X86ISD::PTEST";
19376 case X86ISD::TESTP: return "X86ISD::TESTP";
19377 case X86ISD::TESTM: return "X86ISD::TESTM";
19378 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19379 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19380 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19381 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19382 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19383 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19384 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19385 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19386 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19387 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19388 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19389 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19390 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19391 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19392 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19393 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19394 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19395 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19396 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19397 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19398 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19399 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19400 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19401 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19402 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19403 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19404 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19405 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19406 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19407 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19408 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19409 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19410 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19411 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19412 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19413 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19414 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19415 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19416 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19417 case X86ISD::SAHF: return "X86ISD::SAHF";
19418 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19419 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19420 case X86ISD::FMADD: return "X86ISD::FMADD";
19421 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19422 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19423 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19424 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19425 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19426 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19427 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19428 case X86ISD::XTEST: return "X86ISD::XTEST";
19432 // isLegalAddressingMode - Return true if the addressing mode represented
19433 // by AM is legal for this target, for a load/store of the specified type.
19434 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19436 // X86 supports extremely general addressing modes.
19437 CodeModel::Model M = getTargetMachine().getCodeModel();
19438 Reloc::Model R = getTargetMachine().getRelocationModel();
19440 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19441 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19446 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19448 // If a reference to this global requires an extra load, we can't fold it.
19449 if (isGlobalStubReference(GVFlags))
19452 // If BaseGV requires a register for the PIC base, we cannot also have a
19453 // BaseReg specified.
19454 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19457 // If lower 4G is not available, then we must use rip-relative addressing.
19458 if ((M != CodeModel::Small || R != Reloc::Static) &&
19459 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19463 switch (AM.Scale) {
19469 // These scales always work.
19474 // These scales are formed with basereg+scalereg. Only accept if there is
19479 default: // Other stuff never works.
19486 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19487 unsigned Bits = Ty->getScalarSizeInBits();
19489 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19490 // particularly cheaper than those without.
19494 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19495 // variable shifts just as cheap as scalar ones.
19496 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19499 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19500 // fully general vector.
19504 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19505 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19507 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19508 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19509 return NumBits1 > NumBits2;
19512 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19513 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19516 if (!isTypeLegal(EVT::getEVT(Ty1)))
19519 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19521 // Assuming the caller doesn't have a zeroext or signext return parameter,
19522 // truncation all the way down to i1 is valid.
19526 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19527 return isInt<32>(Imm);
19530 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19531 // Can also use sub to handle negated immediates.
19532 return isInt<32>(Imm);
19535 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19536 if (!VT1.isInteger() || !VT2.isInteger())
19538 unsigned NumBits1 = VT1.getSizeInBits();
19539 unsigned NumBits2 = VT2.getSizeInBits();
19540 return NumBits1 > NumBits2;
19543 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19544 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19545 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19548 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19549 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19550 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19553 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19554 EVT VT1 = Val.getValueType();
19555 if (isZExtFree(VT1, VT2))
19558 if (Val.getOpcode() != ISD::LOAD)
19561 if (!VT1.isSimple() || !VT1.isInteger() ||
19562 !VT2.isSimple() || !VT2.isInteger())
19565 switch (VT1.getSimpleVT().SimpleTy) {
19570 // X86 has 8, 16, and 32-bit zero-extending loads.
19578 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19579 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19582 VT = VT.getScalarType();
19584 if (!VT.isSimple())
19587 switch (VT.getSimpleVT().SimpleTy) {
19598 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19599 // i16 instructions are longer (0x66 prefix) and potentially slower.
19600 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19603 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19604 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19605 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19606 /// are assumed to be legal.
19608 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19610 if (!VT.isSimple())
19613 MVT SVT = VT.getSimpleVT();
19615 // Very little shuffling can be done for 64-bit vectors right now.
19616 if (VT.getSizeInBits() == 64)
19619 // If this is a single-input shuffle with no 128 bit lane crossings we can
19620 // lower it into pshufb.
19621 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19622 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19623 bool isLegal = true;
19624 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19625 if (M[I] >= (int)SVT.getVectorNumElements() ||
19626 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19635 // FIXME: blends, shifts.
19636 return (SVT.getVectorNumElements() == 2 ||
19637 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19638 isMOVLMask(M, SVT) ||
19639 isMOVHLPSMask(M, SVT) ||
19640 isSHUFPMask(M, SVT) ||
19641 isPSHUFDMask(M, SVT) ||
19642 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19643 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19644 isPALIGNRMask(M, SVT, Subtarget) ||
19645 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19646 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19647 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19648 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19649 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19650 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19654 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19656 if (!VT.isSimple())
19659 MVT SVT = VT.getSimpleVT();
19660 unsigned NumElts = SVT.getVectorNumElements();
19661 // FIXME: This collection of masks seems suspect.
19664 if (NumElts == 4 && SVT.is128BitVector()) {
19665 return (isMOVLMask(Mask, SVT) ||
19666 isCommutedMOVLMask(Mask, SVT, true) ||
19667 isSHUFPMask(Mask, SVT) ||
19668 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19669 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19670 Subtarget->hasInt256()));
19675 //===----------------------------------------------------------------------===//
19676 // X86 Scheduler Hooks
19677 //===----------------------------------------------------------------------===//
19679 /// Utility function to emit xbegin specifying the start of an RTM region.
19680 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19681 const TargetInstrInfo *TII) {
19682 DebugLoc DL = MI->getDebugLoc();
19684 const BasicBlock *BB = MBB->getBasicBlock();
19685 MachineFunction::iterator I = MBB;
19688 // For the v = xbegin(), we generate
19699 MachineBasicBlock *thisMBB = MBB;
19700 MachineFunction *MF = MBB->getParent();
19701 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19702 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19703 MF->insert(I, mainMBB);
19704 MF->insert(I, sinkMBB);
19706 // Transfer the remainder of BB and its successor edges to sinkMBB.
19707 sinkMBB->splice(sinkMBB->begin(), MBB,
19708 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19709 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19713 // # fallthrough to mainMBB
19714 // # abortion to sinkMBB
19715 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19716 thisMBB->addSuccessor(mainMBB);
19717 thisMBB->addSuccessor(sinkMBB);
19721 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19722 mainMBB->addSuccessor(sinkMBB);
19725 // EAX is live into the sinkMBB
19726 sinkMBB->addLiveIn(X86::EAX);
19727 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19728 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19731 MI->eraseFromParent();
19735 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19736 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19737 // in the .td file.
19738 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19739 const TargetInstrInfo *TII) {
19741 switch (MI->getOpcode()) {
19742 default: llvm_unreachable("illegal opcode!");
19743 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19744 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19745 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19746 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19747 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19748 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19749 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19750 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19753 DebugLoc dl = MI->getDebugLoc();
19754 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19756 unsigned NumArgs = MI->getNumOperands();
19757 for (unsigned i = 1; i < NumArgs; ++i) {
19758 MachineOperand &Op = MI->getOperand(i);
19759 if (!(Op.isReg() && Op.isImplicit()))
19760 MIB.addOperand(Op);
19762 if (MI->hasOneMemOperand())
19763 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19765 BuildMI(*BB, MI, dl,
19766 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19767 .addReg(X86::XMM0);
19769 MI->eraseFromParent();
19773 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19774 // defs in an instruction pattern
19775 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19776 const TargetInstrInfo *TII) {
19778 switch (MI->getOpcode()) {
19779 default: llvm_unreachable("illegal opcode!");
19780 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19781 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19782 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19783 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19784 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19785 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19786 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19787 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19790 DebugLoc dl = MI->getDebugLoc();
19791 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19793 unsigned NumArgs = MI->getNumOperands(); // remove the results
19794 for (unsigned i = 1; i < NumArgs; ++i) {
19795 MachineOperand &Op = MI->getOperand(i);
19796 if (!(Op.isReg() && Op.isImplicit()))
19797 MIB.addOperand(Op);
19799 if (MI->hasOneMemOperand())
19800 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19802 BuildMI(*BB, MI, dl,
19803 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19806 MI->eraseFromParent();
19810 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19811 const TargetInstrInfo *TII,
19812 const X86Subtarget* Subtarget) {
19813 DebugLoc dl = MI->getDebugLoc();
19815 // Address into RAX/EAX, other two args into ECX, EDX.
19816 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19817 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19818 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19819 for (int i = 0; i < X86::AddrNumOperands; ++i)
19820 MIB.addOperand(MI->getOperand(i));
19822 unsigned ValOps = X86::AddrNumOperands;
19823 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19824 .addReg(MI->getOperand(ValOps).getReg());
19825 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19826 .addReg(MI->getOperand(ValOps+1).getReg());
19828 // The instruction doesn't actually take any operands though.
19829 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19831 MI->eraseFromParent(); // The pseudo is gone now.
19835 MachineBasicBlock *
19836 X86TargetLowering::EmitVAARG64WithCustomInserter(
19838 MachineBasicBlock *MBB) const {
19839 // Emit va_arg instruction on X86-64.
19841 // Operands to this pseudo-instruction:
19842 // 0 ) Output : destination address (reg)
19843 // 1-5) Input : va_list address (addr, i64mem)
19844 // 6 ) ArgSize : Size (in bytes) of vararg type
19845 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19846 // 8 ) Align : Alignment of type
19847 // 9 ) EFLAGS (implicit-def)
19849 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19850 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19852 unsigned DestReg = MI->getOperand(0).getReg();
19853 MachineOperand &Base = MI->getOperand(1);
19854 MachineOperand &Scale = MI->getOperand(2);
19855 MachineOperand &Index = MI->getOperand(3);
19856 MachineOperand &Disp = MI->getOperand(4);
19857 MachineOperand &Segment = MI->getOperand(5);
19858 unsigned ArgSize = MI->getOperand(6).getImm();
19859 unsigned ArgMode = MI->getOperand(7).getImm();
19860 unsigned Align = MI->getOperand(8).getImm();
19862 // Memory Reference
19863 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19864 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19865 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19867 // Machine Information
19868 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19869 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19870 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19871 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19872 DebugLoc DL = MI->getDebugLoc();
19874 // struct va_list {
19877 // i64 overflow_area (address)
19878 // i64 reg_save_area (address)
19880 // sizeof(va_list) = 24
19881 // alignment(va_list) = 8
19883 unsigned TotalNumIntRegs = 6;
19884 unsigned TotalNumXMMRegs = 8;
19885 bool UseGPOffset = (ArgMode == 1);
19886 bool UseFPOffset = (ArgMode == 2);
19887 unsigned MaxOffset = TotalNumIntRegs * 8 +
19888 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19890 /* Align ArgSize to a multiple of 8 */
19891 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19892 bool NeedsAlign = (Align > 8);
19894 MachineBasicBlock *thisMBB = MBB;
19895 MachineBasicBlock *overflowMBB;
19896 MachineBasicBlock *offsetMBB;
19897 MachineBasicBlock *endMBB;
19899 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19900 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19901 unsigned OffsetReg = 0;
19903 if (!UseGPOffset && !UseFPOffset) {
19904 // If we only pull from the overflow region, we don't create a branch.
19905 // We don't need to alter control flow.
19906 OffsetDestReg = 0; // unused
19907 OverflowDestReg = DestReg;
19909 offsetMBB = nullptr;
19910 overflowMBB = thisMBB;
19913 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19914 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19915 // If not, pull from overflow_area. (branch to overflowMBB)
19920 // offsetMBB overflowMBB
19925 // Registers for the PHI in endMBB
19926 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19927 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19929 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19930 MachineFunction *MF = MBB->getParent();
19931 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19932 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19933 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19935 MachineFunction::iterator MBBIter = MBB;
19938 // Insert the new basic blocks
19939 MF->insert(MBBIter, offsetMBB);
19940 MF->insert(MBBIter, overflowMBB);
19941 MF->insert(MBBIter, endMBB);
19943 // Transfer the remainder of MBB and its successor edges to endMBB.
19944 endMBB->splice(endMBB->begin(), thisMBB,
19945 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19946 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19948 // Make offsetMBB and overflowMBB successors of thisMBB
19949 thisMBB->addSuccessor(offsetMBB);
19950 thisMBB->addSuccessor(overflowMBB);
19952 // endMBB is a successor of both offsetMBB and overflowMBB
19953 offsetMBB->addSuccessor(endMBB);
19954 overflowMBB->addSuccessor(endMBB);
19956 // Load the offset value into a register
19957 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19958 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19962 .addDisp(Disp, UseFPOffset ? 4 : 0)
19963 .addOperand(Segment)
19964 .setMemRefs(MMOBegin, MMOEnd);
19966 // Check if there is enough room left to pull this argument.
19967 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19969 .addImm(MaxOffset + 8 - ArgSizeA8);
19971 // Branch to "overflowMBB" if offset >= max
19972 // Fall through to "offsetMBB" otherwise
19973 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19974 .addMBB(overflowMBB);
19977 // In offsetMBB, emit code to use the reg_save_area.
19979 assert(OffsetReg != 0);
19981 // Read the reg_save_area address.
19982 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19983 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19988 .addOperand(Segment)
19989 .setMemRefs(MMOBegin, MMOEnd);
19991 // Zero-extend the offset
19992 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19993 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19996 .addImm(X86::sub_32bit);
19998 // Add the offset to the reg_save_area to get the final address.
19999 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20000 .addReg(OffsetReg64)
20001 .addReg(RegSaveReg);
20003 // Compute the offset for the next argument
20004 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20005 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20007 .addImm(UseFPOffset ? 16 : 8);
20009 // Store it back into the va_list.
20010 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20014 .addDisp(Disp, UseFPOffset ? 4 : 0)
20015 .addOperand(Segment)
20016 .addReg(NextOffsetReg)
20017 .setMemRefs(MMOBegin, MMOEnd);
20020 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20025 // Emit code to use overflow area
20028 // Load the overflow_area address into a register.
20029 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20030 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20035 .addOperand(Segment)
20036 .setMemRefs(MMOBegin, MMOEnd);
20038 // If we need to align it, do so. Otherwise, just copy the address
20039 // to OverflowDestReg.
20041 // Align the overflow address
20042 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20043 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20045 // aligned_addr = (addr + (align-1)) & ~(align-1)
20046 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20047 .addReg(OverflowAddrReg)
20050 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20052 .addImm(~(uint64_t)(Align-1));
20054 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20055 .addReg(OverflowAddrReg);
20058 // Compute the next overflow address after this argument.
20059 // (the overflow address should be kept 8-byte aligned)
20060 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20061 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20062 .addReg(OverflowDestReg)
20063 .addImm(ArgSizeA8);
20065 // Store the new overflow address.
20066 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20071 .addOperand(Segment)
20072 .addReg(NextAddrReg)
20073 .setMemRefs(MMOBegin, MMOEnd);
20075 // If we branched, emit the PHI to the front of endMBB.
20077 BuildMI(*endMBB, endMBB->begin(), DL,
20078 TII->get(X86::PHI), DestReg)
20079 .addReg(OffsetDestReg).addMBB(offsetMBB)
20080 .addReg(OverflowDestReg).addMBB(overflowMBB);
20083 // Erase the pseudo instruction
20084 MI->eraseFromParent();
20089 MachineBasicBlock *
20090 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20092 MachineBasicBlock *MBB) const {
20093 // Emit code to save XMM registers to the stack. The ABI says that the
20094 // number of registers to save is given in %al, so it's theoretically
20095 // possible to do an indirect jump trick to avoid saving all of them,
20096 // however this code takes a simpler approach and just executes all
20097 // of the stores if %al is non-zero. It's less code, and it's probably
20098 // easier on the hardware branch predictor, and stores aren't all that
20099 // expensive anyway.
20101 // Create the new basic blocks. One block contains all the XMM stores,
20102 // and one block is the final destination regardless of whether any
20103 // stores were performed.
20104 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20105 MachineFunction *F = MBB->getParent();
20106 MachineFunction::iterator MBBIter = MBB;
20108 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20109 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20110 F->insert(MBBIter, XMMSaveMBB);
20111 F->insert(MBBIter, EndMBB);
20113 // Transfer the remainder of MBB and its successor edges to EndMBB.
20114 EndMBB->splice(EndMBB->begin(), MBB,
20115 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20116 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20118 // The original block will now fall through to the XMM save block.
20119 MBB->addSuccessor(XMMSaveMBB);
20120 // The XMMSaveMBB will fall through to the end block.
20121 XMMSaveMBB->addSuccessor(EndMBB);
20123 // Now add the instructions.
20124 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20125 DebugLoc DL = MI->getDebugLoc();
20127 unsigned CountReg = MI->getOperand(0).getReg();
20128 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20129 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20131 if (!Subtarget->isTargetWin64()) {
20132 // If %al is 0, branch around the XMM save block.
20133 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20134 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20135 MBB->addSuccessor(EndMBB);
20138 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20139 // that was just emitted, but clearly shouldn't be "saved".
20140 assert((MI->getNumOperands() <= 3 ||
20141 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20142 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20143 && "Expected last argument to be EFLAGS");
20144 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20145 // In the XMM save block, save all the XMM argument registers.
20146 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20147 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20148 MachineMemOperand *MMO =
20149 F->getMachineMemOperand(
20150 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20151 MachineMemOperand::MOStore,
20152 /*Size=*/16, /*Align=*/16);
20153 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20154 .addFrameIndex(RegSaveFrameIndex)
20155 .addImm(/*Scale=*/1)
20156 .addReg(/*IndexReg=*/0)
20157 .addImm(/*Disp=*/Offset)
20158 .addReg(/*Segment=*/0)
20159 .addReg(MI->getOperand(i).getReg())
20160 .addMemOperand(MMO);
20163 MI->eraseFromParent(); // The pseudo instruction is gone now.
20168 // The EFLAGS operand of SelectItr might be missing a kill marker
20169 // because there were multiple uses of EFLAGS, and ISel didn't know
20170 // which to mark. Figure out whether SelectItr should have had a
20171 // kill marker, and set it if it should. Returns the correct kill
20173 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20174 MachineBasicBlock* BB,
20175 const TargetRegisterInfo* TRI) {
20176 // Scan forward through BB for a use/def of EFLAGS.
20177 MachineBasicBlock::iterator miI(std::next(SelectItr));
20178 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20179 const MachineInstr& mi = *miI;
20180 if (mi.readsRegister(X86::EFLAGS))
20182 if (mi.definesRegister(X86::EFLAGS))
20183 break; // Should have kill-flag - update below.
20186 // If we hit the end of the block, check whether EFLAGS is live into a
20188 if (miI == BB->end()) {
20189 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20190 sEnd = BB->succ_end();
20191 sItr != sEnd; ++sItr) {
20192 MachineBasicBlock* succ = *sItr;
20193 if (succ->isLiveIn(X86::EFLAGS))
20198 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20199 // out. SelectMI should have a kill flag on EFLAGS.
20200 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20204 MachineBasicBlock *
20205 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20206 MachineBasicBlock *BB) const {
20207 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20208 DebugLoc DL = MI->getDebugLoc();
20210 // To "insert" a SELECT_CC instruction, we actually have to insert the
20211 // diamond control-flow pattern. The incoming instruction knows the
20212 // destination vreg to set, the condition code register to branch on, the
20213 // true/false values to select between, and a branch opcode to use.
20214 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20215 MachineFunction::iterator It = BB;
20221 // cmpTY ccX, r1, r2
20223 // fallthrough --> copy0MBB
20224 MachineBasicBlock *thisMBB = BB;
20225 MachineFunction *F = BB->getParent();
20226 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20227 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20228 F->insert(It, copy0MBB);
20229 F->insert(It, sinkMBB);
20231 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20232 // live into the sink and copy blocks.
20233 const TargetRegisterInfo *TRI =
20234 BB->getParent()->getSubtarget().getRegisterInfo();
20235 if (!MI->killsRegister(X86::EFLAGS) &&
20236 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20237 copy0MBB->addLiveIn(X86::EFLAGS);
20238 sinkMBB->addLiveIn(X86::EFLAGS);
20241 // Transfer the remainder of BB and its successor edges to sinkMBB.
20242 sinkMBB->splice(sinkMBB->begin(), BB,
20243 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20244 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20246 // Add the true and fallthrough blocks as its successors.
20247 BB->addSuccessor(copy0MBB);
20248 BB->addSuccessor(sinkMBB);
20250 // Create the conditional branch instruction.
20252 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20253 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20256 // %FalseValue = ...
20257 // # fallthrough to sinkMBB
20258 copy0MBB->addSuccessor(sinkMBB);
20261 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20263 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20264 TII->get(X86::PHI), MI->getOperand(0).getReg())
20265 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20266 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20268 MI->eraseFromParent(); // The pseudo instruction is gone now.
20272 MachineBasicBlock *
20273 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20274 MachineBasicBlock *BB) const {
20275 MachineFunction *MF = BB->getParent();
20276 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20277 DebugLoc DL = MI->getDebugLoc();
20278 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20280 assert(MF->shouldSplitStack());
20282 const bool Is64Bit = Subtarget->is64Bit();
20283 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20285 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20286 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20289 // ... [Till the alloca]
20290 // If stacklet is not large enough, jump to mallocMBB
20293 // Allocate by subtracting from RSP
20294 // Jump to continueMBB
20297 // Allocate by call to runtime
20301 // [rest of original BB]
20304 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20305 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20306 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20308 MachineRegisterInfo &MRI = MF->getRegInfo();
20309 const TargetRegisterClass *AddrRegClass =
20310 getRegClassFor(getPointerTy());
20312 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20313 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20314 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20315 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20316 sizeVReg = MI->getOperand(1).getReg(),
20317 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20319 MachineFunction::iterator MBBIter = BB;
20322 MF->insert(MBBIter, bumpMBB);
20323 MF->insert(MBBIter, mallocMBB);
20324 MF->insert(MBBIter, continueMBB);
20326 continueMBB->splice(continueMBB->begin(), BB,
20327 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20328 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20330 // Add code to the main basic block to check if the stack limit has been hit,
20331 // and if so, jump to mallocMBB otherwise to bumpMBB.
20332 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20333 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20334 .addReg(tmpSPVReg).addReg(sizeVReg);
20335 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20336 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20337 .addReg(SPLimitVReg);
20338 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20340 // bumpMBB simply decreases the stack pointer, since we know the current
20341 // stacklet has enough space.
20342 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20343 .addReg(SPLimitVReg);
20344 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20345 .addReg(SPLimitVReg);
20346 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20348 // Calls into a routine in libgcc to allocate more space from the heap.
20349 const uint32_t *RegMask = MF->getTarget()
20350 .getSubtargetImpl()
20351 ->getRegisterInfo()
20352 ->getCallPreservedMask(CallingConv::C);
20354 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20356 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20357 .addExternalSymbol("__morestack_allocate_stack_space")
20358 .addRegMask(RegMask)
20359 .addReg(X86::RDI, RegState::Implicit)
20360 .addReg(X86::RAX, RegState::ImplicitDefine);
20361 } else if (Is64Bit) {
20362 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20364 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20365 .addExternalSymbol("__morestack_allocate_stack_space")
20366 .addRegMask(RegMask)
20367 .addReg(X86::EDI, RegState::Implicit)
20368 .addReg(X86::EAX, RegState::ImplicitDefine);
20370 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20372 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20373 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20374 .addExternalSymbol("__morestack_allocate_stack_space")
20375 .addRegMask(RegMask)
20376 .addReg(X86::EAX, RegState::ImplicitDefine);
20380 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20383 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20384 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20385 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20387 // Set up the CFG correctly.
20388 BB->addSuccessor(bumpMBB);
20389 BB->addSuccessor(mallocMBB);
20390 mallocMBB->addSuccessor(continueMBB);
20391 bumpMBB->addSuccessor(continueMBB);
20393 // Take care of the PHI nodes.
20394 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20395 MI->getOperand(0).getReg())
20396 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20397 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20399 // Delete the original pseudo instruction.
20400 MI->eraseFromParent();
20403 return continueMBB;
20406 MachineBasicBlock *
20407 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20408 MachineBasicBlock *BB) const {
20409 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20410 DebugLoc DL = MI->getDebugLoc();
20412 assert(!Subtarget->isTargetMacho());
20414 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20415 // non-trivial part is impdef of ESP.
20417 if (Subtarget->isTargetWin64()) {
20418 if (Subtarget->isTargetCygMing()) {
20419 // ___chkstk(Mingw64):
20420 // Clobbers R10, R11, RAX and EFLAGS.
20422 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20423 .addExternalSymbol("___chkstk")
20424 .addReg(X86::RAX, RegState::Implicit)
20425 .addReg(X86::RSP, RegState::Implicit)
20426 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20427 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20428 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20430 // __chkstk(MSVCRT): does not update stack pointer.
20431 // Clobbers R10, R11 and EFLAGS.
20432 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20433 .addExternalSymbol("__chkstk")
20434 .addReg(X86::RAX, RegState::Implicit)
20435 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20436 // RAX has the offset to be subtracted from RSP.
20437 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20442 const char *StackProbeSymbol =
20443 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
20445 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20446 .addExternalSymbol(StackProbeSymbol)
20447 .addReg(X86::EAX, RegState::Implicit)
20448 .addReg(X86::ESP, RegState::Implicit)
20449 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20450 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20451 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20454 MI->eraseFromParent(); // The pseudo instruction is gone now.
20458 MachineBasicBlock *
20459 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20460 MachineBasicBlock *BB) const {
20461 // This is pretty easy. We're taking the value that we received from
20462 // our load from the relocation, sticking it in either RDI (x86-64)
20463 // or EAX and doing an indirect call. The return value will then
20464 // be in the normal return register.
20465 MachineFunction *F = BB->getParent();
20466 const X86InstrInfo *TII =
20467 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20468 DebugLoc DL = MI->getDebugLoc();
20470 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20471 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20473 // Get a register mask for the lowered call.
20474 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20475 // proper register mask.
20476 const uint32_t *RegMask = F->getTarget()
20477 .getSubtargetImpl()
20478 ->getRegisterInfo()
20479 ->getCallPreservedMask(CallingConv::C);
20480 if (Subtarget->is64Bit()) {
20481 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20482 TII->get(X86::MOV64rm), X86::RDI)
20484 .addImm(0).addReg(0)
20485 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20486 MI->getOperand(3).getTargetFlags())
20488 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20489 addDirectMem(MIB, X86::RDI);
20490 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20491 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20492 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20493 TII->get(X86::MOV32rm), X86::EAX)
20495 .addImm(0).addReg(0)
20496 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20497 MI->getOperand(3).getTargetFlags())
20499 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20500 addDirectMem(MIB, X86::EAX);
20501 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20503 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20504 TII->get(X86::MOV32rm), X86::EAX)
20505 .addReg(TII->getGlobalBaseReg(F))
20506 .addImm(0).addReg(0)
20507 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20508 MI->getOperand(3).getTargetFlags())
20510 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20511 addDirectMem(MIB, X86::EAX);
20512 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20515 MI->eraseFromParent(); // The pseudo instruction is gone now.
20519 MachineBasicBlock *
20520 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20521 MachineBasicBlock *MBB) const {
20522 DebugLoc DL = MI->getDebugLoc();
20523 MachineFunction *MF = MBB->getParent();
20524 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20525 MachineRegisterInfo &MRI = MF->getRegInfo();
20527 const BasicBlock *BB = MBB->getBasicBlock();
20528 MachineFunction::iterator I = MBB;
20531 // Memory Reference
20532 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20533 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20536 unsigned MemOpndSlot = 0;
20538 unsigned CurOp = 0;
20540 DstReg = MI->getOperand(CurOp++).getReg();
20541 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20542 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20543 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20544 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20546 MemOpndSlot = CurOp;
20548 MVT PVT = getPointerTy();
20549 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20550 "Invalid Pointer Size!");
20552 // For v = setjmp(buf), we generate
20555 // buf[LabelOffset] = restoreMBB
20556 // SjLjSetup restoreMBB
20562 // v = phi(main, restore)
20567 MachineBasicBlock *thisMBB = MBB;
20568 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20569 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20570 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20571 MF->insert(I, mainMBB);
20572 MF->insert(I, sinkMBB);
20573 MF->push_back(restoreMBB);
20575 MachineInstrBuilder MIB;
20577 // Transfer the remainder of BB and its successor edges to sinkMBB.
20578 sinkMBB->splice(sinkMBB->begin(), MBB,
20579 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20580 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20583 unsigned PtrStoreOpc = 0;
20584 unsigned LabelReg = 0;
20585 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20586 Reloc::Model RM = MF->getTarget().getRelocationModel();
20587 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20588 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20590 // Prepare IP either in reg or imm.
20591 if (!UseImmLabel) {
20592 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20593 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20594 LabelReg = MRI.createVirtualRegister(PtrRC);
20595 if (Subtarget->is64Bit()) {
20596 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20600 .addMBB(restoreMBB)
20603 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20604 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20605 .addReg(XII->getGlobalBaseReg(MF))
20608 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20612 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20614 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20615 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20616 if (i == X86::AddrDisp)
20617 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20619 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20622 MIB.addReg(LabelReg);
20624 MIB.addMBB(restoreMBB);
20625 MIB.setMemRefs(MMOBegin, MMOEnd);
20627 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20628 .addMBB(restoreMBB);
20630 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20631 MF->getSubtarget().getRegisterInfo());
20632 MIB.addRegMask(RegInfo->getNoPreservedMask());
20633 thisMBB->addSuccessor(mainMBB);
20634 thisMBB->addSuccessor(restoreMBB);
20638 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20639 mainMBB->addSuccessor(sinkMBB);
20642 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20643 TII->get(X86::PHI), DstReg)
20644 .addReg(mainDstReg).addMBB(mainMBB)
20645 .addReg(restoreDstReg).addMBB(restoreMBB);
20648 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20649 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20650 restoreMBB->addSuccessor(sinkMBB);
20652 MI->eraseFromParent();
20656 MachineBasicBlock *
20657 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20658 MachineBasicBlock *MBB) const {
20659 DebugLoc DL = MI->getDebugLoc();
20660 MachineFunction *MF = MBB->getParent();
20661 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20662 MachineRegisterInfo &MRI = MF->getRegInfo();
20664 // Memory Reference
20665 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20666 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20668 MVT PVT = getPointerTy();
20669 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20670 "Invalid Pointer Size!");
20672 const TargetRegisterClass *RC =
20673 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20674 unsigned Tmp = MRI.createVirtualRegister(RC);
20675 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20676 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20677 MF->getSubtarget().getRegisterInfo());
20678 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20679 unsigned SP = RegInfo->getStackRegister();
20681 MachineInstrBuilder MIB;
20683 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20684 const int64_t SPOffset = 2 * PVT.getStoreSize();
20686 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20687 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20690 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20691 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20692 MIB.addOperand(MI->getOperand(i));
20693 MIB.setMemRefs(MMOBegin, MMOEnd);
20695 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20696 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20697 if (i == X86::AddrDisp)
20698 MIB.addDisp(MI->getOperand(i), LabelOffset);
20700 MIB.addOperand(MI->getOperand(i));
20702 MIB.setMemRefs(MMOBegin, MMOEnd);
20704 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20705 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20706 if (i == X86::AddrDisp)
20707 MIB.addDisp(MI->getOperand(i), SPOffset);
20709 MIB.addOperand(MI->getOperand(i));
20711 MIB.setMemRefs(MMOBegin, MMOEnd);
20713 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20715 MI->eraseFromParent();
20719 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20720 // accumulator loops. Writing back to the accumulator allows the coalescer
20721 // to remove extra copies in the loop.
20722 MachineBasicBlock *
20723 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20724 MachineBasicBlock *MBB) const {
20725 MachineOperand &AddendOp = MI->getOperand(3);
20727 // Bail out early if the addend isn't a register - we can't switch these.
20728 if (!AddendOp.isReg())
20731 MachineFunction &MF = *MBB->getParent();
20732 MachineRegisterInfo &MRI = MF.getRegInfo();
20734 // Check whether the addend is defined by a PHI:
20735 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20736 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20737 if (!AddendDef.isPHI())
20740 // Look for the following pattern:
20742 // %addend = phi [%entry, 0], [%loop, %result]
20744 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20748 // %addend = phi [%entry, 0], [%loop, %result]
20750 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20752 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20753 assert(AddendDef.getOperand(i).isReg());
20754 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20755 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20756 if (&PHISrcInst == MI) {
20757 // Found a matching instruction.
20758 unsigned NewFMAOpc = 0;
20759 switch (MI->getOpcode()) {
20760 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20761 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20762 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20763 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20764 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20765 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20766 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20767 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20768 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20769 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20770 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20771 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20772 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20773 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20774 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20775 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20776 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20777 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20778 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20779 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20781 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20782 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20783 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20784 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20785 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20786 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20787 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20788 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20789 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20790 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20791 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20792 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20793 default: llvm_unreachable("Unrecognized FMA variant.");
20796 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20797 MachineInstrBuilder MIB =
20798 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20799 .addOperand(MI->getOperand(0))
20800 .addOperand(MI->getOperand(3))
20801 .addOperand(MI->getOperand(2))
20802 .addOperand(MI->getOperand(1));
20803 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20804 MI->eraseFromParent();
20811 MachineBasicBlock *
20812 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20813 MachineBasicBlock *BB) const {
20814 switch (MI->getOpcode()) {
20815 default: llvm_unreachable("Unexpected instr type to insert");
20816 case X86::TAILJMPd64:
20817 case X86::TAILJMPr64:
20818 case X86::TAILJMPm64:
20819 llvm_unreachable("TAILJMP64 would not be touched here.");
20820 case X86::TCRETURNdi64:
20821 case X86::TCRETURNri64:
20822 case X86::TCRETURNmi64:
20824 case X86::WIN_ALLOCA:
20825 return EmitLoweredWinAlloca(MI, BB);
20826 case X86::SEG_ALLOCA_32:
20827 case X86::SEG_ALLOCA_64:
20828 return EmitLoweredSegAlloca(MI, BB);
20829 case X86::TLSCall_32:
20830 case X86::TLSCall_64:
20831 return EmitLoweredTLSCall(MI, BB);
20832 case X86::CMOV_GR8:
20833 case X86::CMOV_FR32:
20834 case X86::CMOV_FR64:
20835 case X86::CMOV_V4F32:
20836 case X86::CMOV_V2F64:
20837 case X86::CMOV_V2I64:
20838 case X86::CMOV_V8F32:
20839 case X86::CMOV_V4F64:
20840 case X86::CMOV_V4I64:
20841 case X86::CMOV_V16F32:
20842 case X86::CMOV_V8F64:
20843 case X86::CMOV_V8I64:
20844 case X86::CMOV_GR16:
20845 case X86::CMOV_GR32:
20846 case X86::CMOV_RFP32:
20847 case X86::CMOV_RFP64:
20848 case X86::CMOV_RFP80:
20849 return EmitLoweredSelect(MI, BB);
20851 case X86::FP32_TO_INT16_IN_MEM:
20852 case X86::FP32_TO_INT32_IN_MEM:
20853 case X86::FP32_TO_INT64_IN_MEM:
20854 case X86::FP64_TO_INT16_IN_MEM:
20855 case X86::FP64_TO_INT32_IN_MEM:
20856 case X86::FP64_TO_INT64_IN_MEM:
20857 case X86::FP80_TO_INT16_IN_MEM:
20858 case X86::FP80_TO_INT32_IN_MEM:
20859 case X86::FP80_TO_INT64_IN_MEM: {
20860 MachineFunction *F = BB->getParent();
20861 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20862 DebugLoc DL = MI->getDebugLoc();
20864 // Change the floating point control register to use "round towards zero"
20865 // mode when truncating to an integer value.
20866 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20867 addFrameReference(BuildMI(*BB, MI, DL,
20868 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20870 // Load the old value of the high byte of the control word...
20872 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20873 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20876 // Set the high part to be round to zero...
20877 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20880 // Reload the modified control word now...
20881 addFrameReference(BuildMI(*BB, MI, DL,
20882 TII->get(X86::FLDCW16m)), CWFrameIdx);
20884 // Restore the memory image of control word to original value
20885 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20888 // Get the X86 opcode to use.
20890 switch (MI->getOpcode()) {
20891 default: llvm_unreachable("illegal opcode!");
20892 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20893 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20894 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20895 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20896 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20897 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20898 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20899 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20900 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20904 MachineOperand &Op = MI->getOperand(0);
20906 AM.BaseType = X86AddressMode::RegBase;
20907 AM.Base.Reg = Op.getReg();
20909 AM.BaseType = X86AddressMode::FrameIndexBase;
20910 AM.Base.FrameIndex = Op.getIndex();
20912 Op = MI->getOperand(1);
20914 AM.Scale = Op.getImm();
20915 Op = MI->getOperand(2);
20917 AM.IndexReg = Op.getImm();
20918 Op = MI->getOperand(3);
20919 if (Op.isGlobal()) {
20920 AM.GV = Op.getGlobal();
20922 AM.Disp = Op.getImm();
20924 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20925 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20927 // Reload the original control word now.
20928 addFrameReference(BuildMI(*BB, MI, DL,
20929 TII->get(X86::FLDCW16m)), CWFrameIdx);
20931 MI->eraseFromParent(); // The pseudo instruction is gone now.
20934 // String/text processing lowering.
20935 case X86::PCMPISTRM128REG:
20936 case X86::VPCMPISTRM128REG:
20937 case X86::PCMPISTRM128MEM:
20938 case X86::VPCMPISTRM128MEM:
20939 case X86::PCMPESTRM128REG:
20940 case X86::VPCMPESTRM128REG:
20941 case X86::PCMPESTRM128MEM:
20942 case X86::VPCMPESTRM128MEM:
20943 assert(Subtarget->hasSSE42() &&
20944 "Target must have SSE4.2 or AVX features enabled");
20945 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20947 // String/text processing lowering.
20948 case X86::PCMPISTRIREG:
20949 case X86::VPCMPISTRIREG:
20950 case X86::PCMPISTRIMEM:
20951 case X86::VPCMPISTRIMEM:
20952 case X86::PCMPESTRIREG:
20953 case X86::VPCMPESTRIREG:
20954 case X86::PCMPESTRIMEM:
20955 case X86::VPCMPESTRIMEM:
20956 assert(Subtarget->hasSSE42() &&
20957 "Target must have SSE4.2 or AVX features enabled");
20958 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20960 // Thread synchronization.
20962 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20967 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20969 case X86::VASTART_SAVE_XMM_REGS:
20970 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20972 case X86::VAARG_64:
20973 return EmitVAARG64WithCustomInserter(MI, BB);
20975 case X86::EH_SjLj_SetJmp32:
20976 case X86::EH_SjLj_SetJmp64:
20977 return emitEHSjLjSetJmp(MI, BB);
20979 case X86::EH_SjLj_LongJmp32:
20980 case X86::EH_SjLj_LongJmp64:
20981 return emitEHSjLjLongJmp(MI, BB);
20983 case TargetOpcode::STACKMAP:
20984 case TargetOpcode::PATCHPOINT:
20985 return emitPatchPoint(MI, BB);
20987 case X86::VFMADDPDr213r:
20988 case X86::VFMADDPSr213r:
20989 case X86::VFMADDSDr213r:
20990 case X86::VFMADDSSr213r:
20991 case X86::VFMSUBPDr213r:
20992 case X86::VFMSUBPSr213r:
20993 case X86::VFMSUBSDr213r:
20994 case X86::VFMSUBSSr213r:
20995 case X86::VFNMADDPDr213r:
20996 case X86::VFNMADDPSr213r:
20997 case X86::VFNMADDSDr213r:
20998 case X86::VFNMADDSSr213r:
20999 case X86::VFNMSUBPDr213r:
21000 case X86::VFNMSUBPSr213r:
21001 case X86::VFNMSUBSDr213r:
21002 case X86::VFNMSUBSSr213r:
21003 case X86::VFMADDSUBPDr213r:
21004 case X86::VFMADDSUBPSr213r:
21005 case X86::VFMSUBADDPDr213r:
21006 case X86::VFMSUBADDPSr213r:
21007 case X86::VFMADDPDr213rY:
21008 case X86::VFMADDPSr213rY:
21009 case X86::VFMSUBPDr213rY:
21010 case X86::VFMSUBPSr213rY:
21011 case X86::VFNMADDPDr213rY:
21012 case X86::VFNMADDPSr213rY:
21013 case X86::VFNMSUBPDr213rY:
21014 case X86::VFNMSUBPSr213rY:
21015 case X86::VFMADDSUBPDr213rY:
21016 case X86::VFMADDSUBPSr213rY:
21017 case X86::VFMSUBADDPDr213rY:
21018 case X86::VFMSUBADDPSr213rY:
21019 return emitFMA3Instr(MI, BB);
21023 //===----------------------------------------------------------------------===//
21024 // X86 Optimization Hooks
21025 //===----------------------------------------------------------------------===//
21027 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21030 const SelectionDAG &DAG,
21031 unsigned Depth) const {
21032 unsigned BitWidth = KnownZero.getBitWidth();
21033 unsigned Opc = Op.getOpcode();
21034 assert((Opc >= ISD::BUILTIN_OP_END ||
21035 Opc == ISD::INTRINSIC_WO_CHAIN ||
21036 Opc == ISD::INTRINSIC_W_CHAIN ||
21037 Opc == ISD::INTRINSIC_VOID) &&
21038 "Should use MaskedValueIsZero if you don't know whether Op"
21039 " is a target node!");
21041 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21055 // These nodes' second result is a boolean.
21056 if (Op.getResNo() == 0)
21059 case X86ISD::SETCC:
21060 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21062 case ISD::INTRINSIC_WO_CHAIN: {
21063 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21064 unsigned NumLoBits = 0;
21067 case Intrinsic::x86_sse_movmsk_ps:
21068 case Intrinsic::x86_avx_movmsk_ps_256:
21069 case Intrinsic::x86_sse2_movmsk_pd:
21070 case Intrinsic::x86_avx_movmsk_pd_256:
21071 case Intrinsic::x86_mmx_pmovmskb:
21072 case Intrinsic::x86_sse2_pmovmskb_128:
21073 case Intrinsic::x86_avx2_pmovmskb: {
21074 // High bits of movmskp{s|d}, pmovmskb are known zero.
21076 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21077 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21078 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21079 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21080 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21081 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21082 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21083 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21085 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21094 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21096 const SelectionDAG &,
21097 unsigned Depth) const {
21098 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21099 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21100 return Op.getValueType().getScalarType().getSizeInBits();
21106 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21107 /// node is a GlobalAddress + offset.
21108 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21109 const GlobalValue* &GA,
21110 int64_t &Offset) const {
21111 if (N->getOpcode() == X86ISD::Wrapper) {
21112 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21113 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21114 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21118 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21121 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21122 /// same as extracting the high 128-bit part of 256-bit vector and then
21123 /// inserting the result into the low part of a new 256-bit vector
21124 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21125 EVT VT = SVOp->getValueType(0);
21126 unsigned NumElems = VT.getVectorNumElements();
21128 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21129 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21130 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21131 SVOp->getMaskElt(j) >= 0)
21137 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21138 /// same as extracting the low 128-bit part of 256-bit vector and then
21139 /// inserting the result into the high part of a new 256-bit vector
21140 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21141 EVT VT = SVOp->getValueType(0);
21142 unsigned NumElems = VT.getVectorNumElements();
21144 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21145 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21146 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21147 SVOp->getMaskElt(j) >= 0)
21153 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21154 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21155 TargetLowering::DAGCombinerInfo &DCI,
21156 const X86Subtarget* Subtarget) {
21158 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21159 SDValue V1 = SVOp->getOperand(0);
21160 SDValue V2 = SVOp->getOperand(1);
21161 EVT VT = SVOp->getValueType(0);
21162 unsigned NumElems = VT.getVectorNumElements();
21164 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21165 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21169 // V UNDEF BUILD_VECTOR UNDEF
21171 // CONCAT_VECTOR CONCAT_VECTOR
21174 // RESULT: V + zero extended
21176 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21177 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21178 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21181 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21184 // To match the shuffle mask, the first half of the mask should
21185 // be exactly the first vector, and all the rest a splat with the
21186 // first element of the second one.
21187 for (unsigned i = 0; i != NumElems/2; ++i)
21188 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21189 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21192 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21193 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21194 if (Ld->hasNUsesOfValue(1, 0)) {
21195 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21196 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21198 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21200 Ld->getPointerInfo(),
21201 Ld->getAlignment(),
21202 false/*isVolatile*/, true/*ReadMem*/,
21203 false/*WriteMem*/);
21205 // Make sure the newly-created LOAD is in the same position as Ld in
21206 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21207 // and update uses of Ld's output chain to use the TokenFactor.
21208 if (Ld->hasAnyUseOfValue(1)) {
21209 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21210 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21211 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21212 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21213 SDValue(ResNode.getNode(), 1));
21216 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21220 // Emit a zeroed vector and insert the desired subvector on its
21222 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21223 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21224 return DCI.CombineTo(N, InsV);
21227 //===--------------------------------------------------------------------===//
21228 // Combine some shuffles into subvector extracts and inserts:
21231 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21232 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21233 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21234 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21235 return DCI.CombineTo(N, InsV);
21238 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21239 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21240 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21241 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21242 return DCI.CombineTo(N, InsV);
21248 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21251 /// This is the leaf of the recursive combinine below. When we have found some
21252 /// chain of single-use x86 shuffle instructions and accumulated the combined
21253 /// shuffle mask represented by them, this will try to pattern match that mask
21254 /// into either a single instruction if there is a special purpose instruction
21255 /// for this operation, or into a PSHUFB instruction which is a fully general
21256 /// instruction but should only be used to replace chains over a certain depth.
21257 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21258 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21259 TargetLowering::DAGCombinerInfo &DCI,
21260 const X86Subtarget *Subtarget) {
21261 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21263 // Find the operand that enters the chain. Note that multiple uses are OK
21264 // here, we're not going to remove the operand we find.
21265 SDValue Input = Op.getOperand(0);
21266 while (Input.getOpcode() == ISD::BITCAST)
21267 Input = Input.getOperand(0);
21269 MVT VT = Input.getSimpleValueType();
21270 MVT RootVT = Root.getSimpleValueType();
21273 // Just remove no-op shuffle masks.
21274 if (Mask.size() == 1) {
21275 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21280 // Use the float domain if the operand type is a floating point type.
21281 bool FloatDomain = VT.isFloatingPoint();
21283 // For floating point shuffles, we don't have free copies in the shuffle
21284 // instructions or the ability to load as part of the instruction, so
21285 // canonicalize their shuffles to UNPCK or MOV variants.
21287 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21288 // vectors because it can have a load folded into it that UNPCK cannot. This
21289 // doesn't preclude something switching to the shorter encoding post-RA.
21291 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21292 bool Lo = Mask.equals(0, 0);
21295 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21296 // is no slower than UNPCKLPD but has the option to fold the input operand
21297 // into even an unaligned memory load.
21298 if (Lo && Subtarget->hasSSE3()) {
21299 Shuffle = X86ISD::MOVDDUP;
21300 ShuffleVT = MVT::v2f64;
21302 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21303 // than the UNPCK variants.
21304 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21305 ShuffleVT = MVT::v4f32;
21307 if (Depth == 1 && Root->getOpcode() == Shuffle)
21308 return false; // Nothing to do!
21309 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21310 DCI.AddToWorklist(Op.getNode());
21311 if (Shuffle == X86ISD::MOVDDUP)
21312 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21314 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21315 DCI.AddToWorklist(Op.getNode());
21316 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21320 if (Subtarget->hasSSE3() &&
21321 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21322 bool Lo = Mask.equals(0, 0, 2, 2);
21323 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21324 MVT ShuffleVT = MVT::v4f32;
21325 if (Depth == 1 && Root->getOpcode() == Shuffle)
21326 return false; // Nothing to do!
21327 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21328 DCI.AddToWorklist(Op.getNode());
21329 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21330 DCI.AddToWorklist(Op.getNode());
21331 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21335 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21336 bool Lo = Mask.equals(0, 0, 1, 1);
21337 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21338 MVT ShuffleVT = MVT::v4f32;
21339 if (Depth == 1 && Root->getOpcode() == Shuffle)
21340 return false; // Nothing to do!
21341 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21342 DCI.AddToWorklist(Op.getNode());
21343 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21344 DCI.AddToWorklist(Op.getNode());
21345 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21351 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21352 // variants as none of these have single-instruction variants that are
21353 // superior to the UNPCK formulation.
21354 if (!FloatDomain &&
21355 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21356 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21357 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21358 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21360 bool Lo = Mask[0] == 0;
21361 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21362 if (Depth == 1 && Root->getOpcode() == Shuffle)
21363 return false; // Nothing to do!
21365 switch (Mask.size()) {
21367 ShuffleVT = MVT::v8i16;
21370 ShuffleVT = MVT::v16i8;
21373 llvm_unreachable("Impossible mask size!");
21375 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21376 DCI.AddToWorklist(Op.getNode());
21377 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21378 DCI.AddToWorklist(Op.getNode());
21379 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21384 // Don't try to re-form single instruction chains under any circumstances now
21385 // that we've done encoding canonicalization for them.
21389 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21390 // can replace them with a single PSHUFB instruction profitably. Intel's
21391 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21392 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21393 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21394 SmallVector<SDValue, 16> PSHUFBMask;
21395 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21396 int Ratio = 16 / Mask.size();
21397 for (unsigned i = 0; i < 16; ++i) {
21398 if (Mask[i / Ratio] == SM_SentinelUndef) {
21399 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21402 int M = Mask[i / Ratio] != SM_SentinelZero
21403 ? Ratio * Mask[i / Ratio] + i % Ratio
21405 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21407 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21408 DCI.AddToWorklist(Op.getNode());
21409 SDValue PSHUFBMaskOp =
21410 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21411 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21412 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21413 DCI.AddToWorklist(Op.getNode());
21414 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21419 // Failed to find any combines.
21423 /// \brief Fully generic combining of x86 shuffle instructions.
21425 /// This should be the last combine run over the x86 shuffle instructions. Once
21426 /// they have been fully optimized, this will recursively consider all chains
21427 /// of single-use shuffle instructions, build a generic model of the cumulative
21428 /// shuffle operation, and check for simpler instructions which implement this
21429 /// operation. We use this primarily for two purposes:
21431 /// 1) Collapse generic shuffles to specialized single instructions when
21432 /// equivalent. In most cases, this is just an encoding size win, but
21433 /// sometimes we will collapse multiple generic shuffles into a single
21434 /// special-purpose shuffle.
21435 /// 2) Look for sequences of shuffle instructions with 3 or more total
21436 /// instructions, and replace them with the slightly more expensive SSSE3
21437 /// PSHUFB instruction if available. We do this as the last combining step
21438 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21439 /// a suitable short sequence of other instructions. The PHUFB will either
21440 /// use a register or have to read from memory and so is slightly (but only
21441 /// slightly) more expensive than the other shuffle instructions.
21443 /// Because this is inherently a quadratic operation (for each shuffle in
21444 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21445 /// This should never be an issue in practice as the shuffle lowering doesn't
21446 /// produce sequences of more than 8 instructions.
21448 /// FIXME: We will currently miss some cases where the redundant shuffling
21449 /// would simplify under the threshold for PSHUFB formation because of
21450 /// combine-ordering. To fix this, we should do the redundant instruction
21451 /// combining in this recursive walk.
21452 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21453 ArrayRef<int> RootMask,
21454 int Depth, bool HasPSHUFB,
21456 TargetLowering::DAGCombinerInfo &DCI,
21457 const X86Subtarget *Subtarget) {
21458 // Bound the depth of our recursive combine because this is ultimately
21459 // quadratic in nature.
21463 // Directly rip through bitcasts to find the underlying operand.
21464 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21465 Op = Op.getOperand(0);
21467 MVT VT = Op.getSimpleValueType();
21468 if (!VT.isVector())
21469 return false; // Bail if we hit a non-vector.
21470 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21471 // version should be added.
21472 if (VT.getSizeInBits() != 128)
21475 assert(Root.getSimpleValueType().isVector() &&
21476 "Shuffles operate on vector types!");
21477 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21478 "Can only combine shuffles of the same vector register size.");
21480 if (!isTargetShuffle(Op.getOpcode()))
21482 SmallVector<int, 16> OpMask;
21484 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21485 // We only can combine unary shuffles which we can decode the mask for.
21486 if (!HaveMask || !IsUnary)
21489 assert(VT.getVectorNumElements() == OpMask.size() &&
21490 "Different mask size from vector size!");
21491 assert(((RootMask.size() > OpMask.size() &&
21492 RootMask.size() % OpMask.size() == 0) ||
21493 (OpMask.size() > RootMask.size() &&
21494 OpMask.size() % RootMask.size() == 0) ||
21495 OpMask.size() == RootMask.size()) &&
21496 "The smaller number of elements must divide the larger.");
21497 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21498 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21499 assert(((RootRatio == 1 && OpRatio == 1) ||
21500 (RootRatio == 1) != (OpRatio == 1)) &&
21501 "Must not have a ratio for both incoming and op masks!");
21503 SmallVector<int, 16> Mask;
21504 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21506 // Merge this shuffle operation's mask into our accumulated mask. Note that
21507 // this shuffle's mask will be the first applied to the input, followed by the
21508 // root mask to get us all the way to the root value arrangement. The reason
21509 // for this order is that we are recursing up the operation chain.
21510 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21511 int RootIdx = i / RootRatio;
21512 if (RootMask[RootIdx] < 0) {
21513 // This is a zero or undef lane, we're done.
21514 Mask.push_back(RootMask[RootIdx]);
21518 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21519 int OpIdx = RootMaskedIdx / OpRatio;
21520 if (OpMask[OpIdx] < 0) {
21521 // The incoming lanes are zero or undef, it doesn't matter which ones we
21523 Mask.push_back(OpMask[OpIdx]);
21527 // Ok, we have non-zero lanes, map them through.
21528 Mask.push_back(OpMask[OpIdx] * OpRatio +
21529 RootMaskedIdx % OpRatio);
21532 // See if we can recurse into the operand to combine more things.
21533 switch (Op.getOpcode()) {
21534 case X86ISD::PSHUFB:
21536 case X86ISD::PSHUFD:
21537 case X86ISD::PSHUFHW:
21538 case X86ISD::PSHUFLW:
21539 if (Op.getOperand(0).hasOneUse() &&
21540 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21541 HasPSHUFB, DAG, DCI, Subtarget))
21545 case X86ISD::UNPCKL:
21546 case X86ISD::UNPCKH:
21547 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21548 // We can't check for single use, we have to check that this shuffle is the only user.
21549 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21550 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21551 HasPSHUFB, DAG, DCI, Subtarget))
21556 // Minor canonicalization of the accumulated shuffle mask to make it easier
21557 // to match below. All this does is detect masks with squential pairs of
21558 // elements, and shrink them to the half-width mask. It does this in a loop
21559 // so it will reduce the size of the mask to the minimal width mask which
21560 // performs an equivalent shuffle.
21561 SmallVector<int, 16> WidenedMask;
21562 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21563 Mask = std::move(WidenedMask);
21564 WidenedMask.clear();
21567 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21571 /// \brief Get the PSHUF-style mask from PSHUF node.
21573 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21574 /// PSHUF-style masks that can be reused with such instructions.
21575 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21576 SmallVector<int, 4> Mask;
21578 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21582 switch (N.getOpcode()) {
21583 case X86ISD::PSHUFD:
21585 case X86ISD::PSHUFLW:
21588 case X86ISD::PSHUFHW:
21589 Mask.erase(Mask.begin(), Mask.begin() + 4);
21590 for (int &M : Mask)
21594 llvm_unreachable("No valid shuffle instruction found!");
21598 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21600 /// We walk up the chain and look for a combinable shuffle, skipping over
21601 /// shuffles that we could hoist this shuffle's transformation past without
21602 /// altering anything.
21604 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21606 TargetLowering::DAGCombinerInfo &DCI) {
21607 assert(N.getOpcode() == X86ISD::PSHUFD &&
21608 "Called with something other than an x86 128-bit half shuffle!");
21611 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21612 // of the shuffles in the chain so that we can form a fresh chain to replace
21614 SmallVector<SDValue, 8> Chain;
21615 SDValue V = N.getOperand(0);
21616 for (; V.hasOneUse(); V = V.getOperand(0)) {
21617 switch (V.getOpcode()) {
21619 return SDValue(); // Nothing combined!
21622 // Skip bitcasts as we always know the type for the target specific
21626 case X86ISD::PSHUFD:
21627 // Found another dword shuffle.
21630 case X86ISD::PSHUFLW:
21631 // Check that the low words (being shuffled) are the identity in the
21632 // dword shuffle, and the high words are self-contained.
21633 if (Mask[0] != 0 || Mask[1] != 1 ||
21634 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21637 Chain.push_back(V);
21640 case X86ISD::PSHUFHW:
21641 // Check that the high words (being shuffled) are the identity in the
21642 // dword shuffle, and the low words are self-contained.
21643 if (Mask[2] != 2 || Mask[3] != 3 ||
21644 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21647 Chain.push_back(V);
21650 case X86ISD::UNPCKL:
21651 case X86ISD::UNPCKH:
21652 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21653 // shuffle into a preceding word shuffle.
21654 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21657 // Search for a half-shuffle which we can combine with.
21658 unsigned CombineOp =
21659 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21660 if (V.getOperand(0) != V.getOperand(1) ||
21661 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21663 Chain.push_back(V);
21664 V = V.getOperand(0);
21666 switch (V.getOpcode()) {
21668 return SDValue(); // Nothing to combine.
21670 case X86ISD::PSHUFLW:
21671 case X86ISD::PSHUFHW:
21672 if (V.getOpcode() == CombineOp)
21675 Chain.push_back(V);
21679 V = V.getOperand(0);
21683 } while (V.hasOneUse());
21686 // Break out of the loop if we break out of the switch.
21690 if (!V.hasOneUse())
21691 // We fell out of the loop without finding a viable combining instruction.
21694 // Merge this node's mask and our incoming mask.
21695 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21696 for (int &M : Mask)
21698 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21699 getV4X86ShuffleImm8ForMask(Mask, DAG));
21701 // Rebuild the chain around this new shuffle.
21702 while (!Chain.empty()) {
21703 SDValue W = Chain.pop_back_val();
21705 if (V.getValueType() != W.getOperand(0).getValueType())
21706 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21708 switch (W.getOpcode()) {
21710 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21712 case X86ISD::UNPCKL:
21713 case X86ISD::UNPCKH:
21714 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21717 case X86ISD::PSHUFD:
21718 case X86ISD::PSHUFLW:
21719 case X86ISD::PSHUFHW:
21720 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21724 if (V.getValueType() != N.getValueType())
21725 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21727 // Return the new chain to replace N.
21731 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21733 /// We walk up the chain, skipping shuffles of the other half and looking
21734 /// through shuffles which switch halves trying to find a shuffle of the same
21735 /// pair of dwords.
21736 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21738 TargetLowering::DAGCombinerInfo &DCI) {
21740 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21741 "Called with something other than an x86 128-bit half shuffle!");
21743 unsigned CombineOpcode = N.getOpcode();
21745 // Walk up a single-use chain looking for a combinable shuffle.
21746 SDValue V = N.getOperand(0);
21747 for (; V.hasOneUse(); V = V.getOperand(0)) {
21748 switch (V.getOpcode()) {
21750 return false; // Nothing combined!
21753 // Skip bitcasts as we always know the type for the target specific
21757 case X86ISD::PSHUFLW:
21758 case X86ISD::PSHUFHW:
21759 if (V.getOpcode() == CombineOpcode)
21762 // Other-half shuffles are no-ops.
21765 // Break out of the loop if we break out of the switch.
21769 if (!V.hasOneUse())
21770 // We fell out of the loop without finding a viable combining instruction.
21773 // Combine away the bottom node as its shuffle will be accumulated into
21774 // a preceding shuffle.
21775 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21777 // Record the old value.
21780 // Merge this node's mask and our incoming mask (adjusted to account for all
21781 // the pshufd instructions encountered).
21782 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21783 for (int &M : Mask)
21785 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21786 getV4X86ShuffleImm8ForMask(Mask, DAG));
21788 // Check that the shuffles didn't cancel each other out. If not, we need to
21789 // combine to the new one.
21791 // Replace the combinable shuffle with the combined one, updating all users
21792 // so that we re-evaluate the chain here.
21793 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21798 /// \brief Try to combine x86 target specific shuffles.
21799 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21800 TargetLowering::DAGCombinerInfo &DCI,
21801 const X86Subtarget *Subtarget) {
21803 MVT VT = N.getSimpleValueType();
21804 SmallVector<int, 4> Mask;
21806 switch (N.getOpcode()) {
21807 case X86ISD::PSHUFD:
21808 case X86ISD::PSHUFLW:
21809 case X86ISD::PSHUFHW:
21810 Mask = getPSHUFShuffleMask(N);
21811 assert(Mask.size() == 4);
21817 // Nuke no-op shuffles that show up after combining.
21818 if (isNoopShuffleMask(Mask))
21819 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21821 // Look for simplifications involving one or two shuffle instructions.
21822 SDValue V = N.getOperand(0);
21823 switch (N.getOpcode()) {
21826 case X86ISD::PSHUFLW:
21827 case X86ISD::PSHUFHW:
21828 assert(VT == MVT::v8i16);
21831 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21832 return SDValue(); // We combined away this shuffle, so we're done.
21834 // See if this reduces to a PSHUFD which is no more expensive and can
21835 // combine with more operations. Note that it has to at least flip the
21836 // dwords as otherwise it would have been removed as a no-op.
21837 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21838 int DMask[] = {0, 1, 2, 3};
21839 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21840 DMask[DOffset + 0] = DOffset + 1;
21841 DMask[DOffset + 1] = DOffset + 0;
21842 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21843 DCI.AddToWorklist(V.getNode());
21844 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21845 getV4X86ShuffleImm8ForMask(DMask, DAG));
21846 DCI.AddToWorklist(V.getNode());
21847 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21850 // Look for shuffle patterns which can be implemented as a single unpack.
21851 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21852 // only works when we have a PSHUFD followed by two half-shuffles.
21853 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21854 (V.getOpcode() == X86ISD::PSHUFLW ||
21855 V.getOpcode() == X86ISD::PSHUFHW) &&
21856 V.getOpcode() != N.getOpcode() &&
21858 SDValue D = V.getOperand(0);
21859 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21860 D = D.getOperand(0);
21861 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21862 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21863 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21864 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21865 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21867 for (int i = 0; i < 4; ++i) {
21868 WordMask[i + NOffset] = Mask[i] + NOffset;
21869 WordMask[i + VOffset] = VMask[i] + VOffset;
21871 // Map the word mask through the DWord mask.
21873 for (int i = 0; i < 8; ++i)
21874 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21875 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21876 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21877 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21878 std::begin(UnpackLoMask)) ||
21879 std::equal(std::begin(MappedMask), std::end(MappedMask),
21880 std::begin(UnpackHiMask))) {
21881 // We can replace all three shuffles with an unpack.
21882 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21883 DCI.AddToWorklist(V.getNode());
21884 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21886 DL, MVT::v8i16, V, V);
21893 case X86ISD::PSHUFD:
21894 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21903 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21905 /// We combine this directly on the abstract vector shuffle nodes so it is
21906 /// easier to generically match. We also insert dummy vector shuffle nodes for
21907 /// the operands which explicitly discard the lanes which are unused by this
21908 /// operation to try to flow through the rest of the combiner the fact that
21909 /// they're unused.
21910 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21912 EVT VT = N->getValueType(0);
21914 // We only handle target-independent shuffles.
21915 // FIXME: It would be easy and harmless to use the target shuffle mask
21916 // extraction tool to support more.
21917 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21920 auto *SVN = cast<ShuffleVectorSDNode>(N);
21921 ArrayRef<int> Mask = SVN->getMask();
21922 SDValue V1 = N->getOperand(0);
21923 SDValue V2 = N->getOperand(1);
21925 // We require the first shuffle operand to be the SUB node, and the second to
21926 // be the ADD node.
21927 // FIXME: We should support the commuted patterns.
21928 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21931 // If there are other uses of these operations we can't fold them.
21932 if (!V1->hasOneUse() || !V2->hasOneUse())
21935 // Ensure that both operations have the same operands. Note that we can
21936 // commute the FADD operands.
21937 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21938 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21939 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21942 // We're looking for blends between FADD and FSUB nodes. We insist on these
21943 // nodes being lined up in a specific expected pattern.
21944 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21945 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21946 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21949 // Only specific types are legal at this point, assert so we notice if and
21950 // when these change.
21951 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21952 VT == MVT::v4f64) &&
21953 "Unknown vector type encountered!");
21955 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21958 /// PerformShuffleCombine - Performs several different shuffle combines.
21959 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21960 TargetLowering::DAGCombinerInfo &DCI,
21961 const X86Subtarget *Subtarget) {
21963 SDValue N0 = N->getOperand(0);
21964 SDValue N1 = N->getOperand(1);
21965 EVT VT = N->getValueType(0);
21967 // Don't create instructions with illegal types after legalize types has run.
21968 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21969 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21972 // If we have legalized the vector types, look for blends of FADD and FSUB
21973 // nodes that we can fuse into an ADDSUB node.
21974 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21975 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21978 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21979 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21980 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21981 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21983 // During Type Legalization, when promoting illegal vector types,
21984 // the backend might introduce new shuffle dag nodes and bitcasts.
21986 // This code performs the following transformation:
21987 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21988 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21990 // We do this only if both the bitcast and the BINOP dag nodes have
21991 // one use. Also, perform this transformation only if the new binary
21992 // operation is legal. This is to avoid introducing dag nodes that
21993 // potentially need to be further expanded (or custom lowered) into a
21994 // less optimal sequence of dag nodes.
21995 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21996 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21997 N0.getOpcode() == ISD::BITCAST) {
21998 SDValue BC0 = N0.getOperand(0);
21999 EVT SVT = BC0.getValueType();
22000 unsigned Opcode = BC0.getOpcode();
22001 unsigned NumElts = VT.getVectorNumElements();
22003 if (BC0.hasOneUse() && SVT.isVector() &&
22004 SVT.getVectorNumElements() * 2 == NumElts &&
22005 TLI.isOperationLegal(Opcode, VT)) {
22006 bool CanFold = false;
22018 unsigned SVTNumElts = SVT.getVectorNumElements();
22019 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22020 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22021 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22022 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22023 CanFold = SVOp->getMaskElt(i) < 0;
22026 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22027 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22028 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22029 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22034 // Only handle 128 wide vector from here on.
22035 if (!VT.is128BitVector())
22038 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22039 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22040 // consecutive, non-overlapping, and in the right order.
22041 SmallVector<SDValue, 16> Elts;
22042 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22043 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22045 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22049 if (isTargetShuffle(N->getOpcode())) {
22051 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22052 if (Shuffle.getNode())
22055 // Try recursively combining arbitrary sequences of x86 shuffle
22056 // instructions into higher-order shuffles. We do this after combining
22057 // specific PSHUF instruction sequences into their minimal form so that we
22058 // can evaluate how many specialized shuffle instructions are involved in
22059 // a particular chain.
22060 SmallVector<int, 1> NonceMask; // Just a placeholder.
22061 NonceMask.push_back(0);
22062 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22063 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22065 return SDValue(); // This routine will use CombineTo to replace N.
22071 /// PerformTruncateCombine - Converts truncate operation to
22072 /// a sequence of vector shuffle operations.
22073 /// It is possible when we truncate 256-bit vector to 128-bit vector
22074 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22075 TargetLowering::DAGCombinerInfo &DCI,
22076 const X86Subtarget *Subtarget) {
22080 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22081 /// specific shuffle of a load can be folded into a single element load.
22082 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22083 /// shuffles have been custom lowered so we need to handle those here.
22084 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22085 TargetLowering::DAGCombinerInfo &DCI) {
22086 if (DCI.isBeforeLegalizeOps())
22089 SDValue InVec = N->getOperand(0);
22090 SDValue EltNo = N->getOperand(1);
22092 if (!isa<ConstantSDNode>(EltNo))
22095 EVT OriginalVT = InVec.getValueType();
22097 if (InVec.getOpcode() == ISD::BITCAST) {
22098 // Don't duplicate a load with other uses.
22099 if (!InVec.hasOneUse())
22101 EVT BCVT = InVec.getOperand(0).getValueType();
22102 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22104 InVec = InVec.getOperand(0);
22107 EVT CurrentVT = InVec.getValueType();
22109 if (!isTargetShuffle(InVec.getOpcode()))
22112 // Don't duplicate a load with other uses.
22113 if (!InVec.hasOneUse())
22116 SmallVector<int, 16> ShuffleMask;
22118 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22119 ShuffleMask, UnaryShuffle))
22122 // Select the input vector, guarding against out of range extract vector.
22123 unsigned NumElems = CurrentVT.getVectorNumElements();
22124 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22125 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22126 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22127 : InVec.getOperand(1);
22129 // If inputs to shuffle are the same for both ops, then allow 2 uses
22130 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22132 if (LdNode.getOpcode() == ISD::BITCAST) {
22133 // Don't duplicate a load with other uses.
22134 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22137 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22138 LdNode = LdNode.getOperand(0);
22141 if (!ISD::isNormalLoad(LdNode.getNode()))
22144 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22146 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22149 EVT EltVT = N->getValueType(0);
22150 // If there's a bitcast before the shuffle, check if the load type and
22151 // alignment is valid.
22152 unsigned Align = LN0->getAlignment();
22153 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22154 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22155 EltVT.getTypeForEVT(*DAG.getContext()));
22157 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22160 // All checks match so transform back to vector_shuffle so that DAG combiner
22161 // can finish the job
22164 // Create shuffle node taking into account the case that its a unary shuffle
22165 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22166 : InVec.getOperand(1);
22167 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22168 InVec.getOperand(0), Shuffle,
22170 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22171 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22175 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22176 /// generation and convert it from being a bunch of shuffles and extracts
22177 /// to a simple store and scalar loads to extract the elements.
22178 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22179 TargetLowering::DAGCombinerInfo &DCI) {
22180 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22181 if (NewOp.getNode())
22184 SDValue InputVector = N->getOperand(0);
22186 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22187 // from mmx to v2i32 has a single usage.
22188 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22189 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22190 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22191 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22192 N->getValueType(0),
22193 InputVector.getNode()->getOperand(0));
22195 // Only operate on vectors of 4 elements, where the alternative shuffling
22196 // gets to be more expensive.
22197 if (InputVector.getValueType() != MVT::v4i32)
22200 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22201 // single use which is a sign-extend or zero-extend, and all elements are
22203 SmallVector<SDNode *, 4> Uses;
22204 unsigned ExtractedElements = 0;
22205 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22206 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22207 if (UI.getUse().getResNo() != InputVector.getResNo())
22210 SDNode *Extract = *UI;
22211 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22214 if (Extract->getValueType(0) != MVT::i32)
22216 if (!Extract->hasOneUse())
22218 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22219 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22221 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22224 // Record which element was extracted.
22225 ExtractedElements |=
22226 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22228 Uses.push_back(Extract);
22231 // If not all the elements were used, this may not be worthwhile.
22232 if (ExtractedElements != 15)
22235 // Ok, we've now decided to do the transformation.
22236 SDLoc dl(InputVector);
22238 // Store the value to a temporary stack slot.
22239 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22240 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22241 MachinePointerInfo(), false, false, 0);
22243 // Replace each use (extract) with a load of the appropriate element.
22244 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22245 UE = Uses.end(); UI != UE; ++UI) {
22246 SDNode *Extract = *UI;
22248 // cOMpute the element's address.
22249 SDValue Idx = Extract->getOperand(1);
22251 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22252 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22254 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22256 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22257 StackPtr, OffsetVal);
22259 // Load the scalar.
22260 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22261 ScalarAddr, MachinePointerInfo(),
22262 false, false, false, 0);
22264 // Replace the exact with the load.
22265 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22268 // The replacement was made in place; don't return anything.
22272 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22273 static std::pair<unsigned, bool>
22274 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22275 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22276 if (!VT.isVector())
22277 return std::make_pair(0, false);
22279 bool NeedSplit = false;
22280 switch (VT.getSimpleVT().SimpleTy) {
22281 default: return std::make_pair(0, false);
22285 if (!Subtarget->hasAVX2())
22287 if (!Subtarget->hasAVX())
22288 return std::make_pair(0, false);
22293 if (!Subtarget->hasSSE2())
22294 return std::make_pair(0, false);
22297 // SSE2 has only a small subset of the operations.
22298 bool hasUnsigned = Subtarget->hasSSE41() ||
22299 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22300 bool hasSigned = Subtarget->hasSSE41() ||
22301 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22303 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22306 // Check for x CC y ? x : y.
22307 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22308 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22313 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22316 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22319 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22322 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22324 // Check for x CC y ? y : x -- a min/max with reversed arms.
22325 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22326 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22331 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22334 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22337 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22340 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22344 return std::make_pair(Opc, NeedSplit);
22348 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22349 const X86Subtarget *Subtarget) {
22351 SDValue Cond = N->getOperand(0);
22352 SDValue LHS = N->getOperand(1);
22353 SDValue RHS = N->getOperand(2);
22355 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22356 SDValue CondSrc = Cond->getOperand(0);
22357 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22358 Cond = CondSrc->getOperand(0);
22361 MVT VT = N->getSimpleValueType(0);
22362 MVT EltVT = VT.getVectorElementType();
22363 unsigned NumElems = VT.getVectorNumElements();
22364 // There is no blend with immediate in AVX-512.
22365 if (VT.is512BitVector())
22368 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
22370 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
22373 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22376 // A vselect where all conditions and data are constants can be optimized into
22377 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22378 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22379 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22382 unsigned MaskValue = 0;
22383 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22386 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22387 for (unsigned i = 0; i < NumElems; ++i) {
22388 // Be sure we emit undef where we can.
22389 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22390 ShuffleMask[i] = -1;
22392 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22395 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22398 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22400 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22401 TargetLowering::DAGCombinerInfo &DCI,
22402 const X86Subtarget *Subtarget) {
22404 SDValue Cond = N->getOperand(0);
22405 // Get the LHS/RHS of the select.
22406 SDValue LHS = N->getOperand(1);
22407 SDValue RHS = N->getOperand(2);
22408 EVT VT = LHS.getValueType();
22409 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22411 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22412 // instructions match the semantics of the common C idiom x<y?x:y but not
22413 // x<=y?x:y, because of how they handle negative zero (which can be
22414 // ignored in unsafe-math mode).
22415 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22416 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22417 (Subtarget->hasSSE2() ||
22418 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22419 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22421 unsigned Opcode = 0;
22422 // Check for x CC y ? x : y.
22423 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22424 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22428 // Converting this to a min would handle NaNs incorrectly, and swapping
22429 // the operands would cause it to handle comparisons between positive
22430 // and negative zero incorrectly.
22431 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22432 if (!DAG.getTarget().Options.UnsafeFPMath &&
22433 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22435 std::swap(LHS, RHS);
22437 Opcode = X86ISD::FMIN;
22440 // Converting this to a min would handle comparisons between positive
22441 // and negative zero incorrectly.
22442 if (!DAG.getTarget().Options.UnsafeFPMath &&
22443 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22445 Opcode = X86ISD::FMIN;
22448 // Converting this to a min would handle both negative zeros and NaNs
22449 // incorrectly, but we can swap the operands to fix both.
22450 std::swap(LHS, RHS);
22454 Opcode = X86ISD::FMIN;
22458 // Converting this to a max would handle comparisons between positive
22459 // and negative zero incorrectly.
22460 if (!DAG.getTarget().Options.UnsafeFPMath &&
22461 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22463 Opcode = X86ISD::FMAX;
22466 // Converting this to a max would handle NaNs incorrectly, and swapping
22467 // the operands would cause it to handle comparisons between positive
22468 // and negative zero incorrectly.
22469 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22470 if (!DAG.getTarget().Options.UnsafeFPMath &&
22471 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22473 std::swap(LHS, RHS);
22475 Opcode = X86ISD::FMAX;
22478 // Converting this to a max would handle both negative zeros and NaNs
22479 // incorrectly, but we can swap the operands to fix both.
22480 std::swap(LHS, RHS);
22484 Opcode = X86ISD::FMAX;
22487 // Check for x CC y ? y : x -- a min/max with reversed arms.
22488 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22489 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22493 // Converting this to a min would handle comparisons between positive
22494 // and negative zero incorrectly, and swapping the operands would
22495 // cause it to handle NaNs incorrectly.
22496 if (!DAG.getTarget().Options.UnsafeFPMath &&
22497 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22498 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22500 std::swap(LHS, RHS);
22502 Opcode = X86ISD::FMIN;
22505 // Converting this to a min would handle NaNs incorrectly.
22506 if (!DAG.getTarget().Options.UnsafeFPMath &&
22507 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22509 Opcode = X86ISD::FMIN;
22512 // Converting this to a min would handle both negative zeros and NaNs
22513 // incorrectly, but we can swap the operands to fix both.
22514 std::swap(LHS, RHS);
22518 Opcode = X86ISD::FMIN;
22522 // Converting this to a max would handle NaNs incorrectly.
22523 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22525 Opcode = X86ISD::FMAX;
22528 // Converting this to a max would handle comparisons between positive
22529 // and negative zero incorrectly, and swapping the operands would
22530 // cause it to handle NaNs incorrectly.
22531 if (!DAG.getTarget().Options.UnsafeFPMath &&
22532 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22533 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22535 std::swap(LHS, RHS);
22537 Opcode = X86ISD::FMAX;
22540 // Converting this to a max would handle both negative zeros and NaNs
22541 // incorrectly, but we can swap the operands to fix both.
22542 std::swap(LHS, RHS);
22546 Opcode = X86ISD::FMAX;
22552 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22555 EVT CondVT = Cond.getValueType();
22556 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22557 CondVT.getVectorElementType() == MVT::i1) {
22558 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22559 // lowering on KNL. In this case we convert it to
22560 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22561 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22562 // Since SKX these selects have a proper lowering.
22563 EVT OpVT = LHS.getValueType();
22564 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22565 (OpVT.getVectorElementType() == MVT::i8 ||
22566 OpVT.getVectorElementType() == MVT::i16) &&
22567 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22568 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22569 DCI.AddToWorklist(Cond.getNode());
22570 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22573 // If this is a select between two integer constants, try to do some
22575 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22576 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22577 // Don't do this for crazy integer types.
22578 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22579 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22580 // so that TrueC (the true value) is larger than FalseC.
22581 bool NeedsCondInvert = false;
22583 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22584 // Efficiently invertible.
22585 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22586 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22587 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22588 NeedsCondInvert = true;
22589 std::swap(TrueC, FalseC);
22592 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22593 if (FalseC->getAPIntValue() == 0 &&
22594 TrueC->getAPIntValue().isPowerOf2()) {
22595 if (NeedsCondInvert) // Invert the condition if needed.
22596 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22597 DAG.getConstant(1, Cond.getValueType()));
22599 // Zero extend the condition if needed.
22600 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22602 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22603 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22604 DAG.getConstant(ShAmt, MVT::i8));
22607 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22608 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22609 if (NeedsCondInvert) // Invert the condition if needed.
22610 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22611 DAG.getConstant(1, Cond.getValueType()));
22613 // Zero extend the condition if needed.
22614 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22615 FalseC->getValueType(0), Cond);
22616 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22617 SDValue(FalseC, 0));
22620 // Optimize cases that will turn into an LEA instruction. This requires
22621 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22622 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22623 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22624 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22626 bool isFastMultiplier = false;
22628 switch ((unsigned char)Diff) {
22630 case 1: // result = add base, cond
22631 case 2: // result = lea base( , cond*2)
22632 case 3: // result = lea base(cond, cond*2)
22633 case 4: // result = lea base( , cond*4)
22634 case 5: // result = lea base(cond, cond*4)
22635 case 8: // result = lea base( , cond*8)
22636 case 9: // result = lea base(cond, cond*8)
22637 isFastMultiplier = true;
22642 if (isFastMultiplier) {
22643 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22644 if (NeedsCondInvert) // Invert the condition if needed.
22645 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22646 DAG.getConstant(1, Cond.getValueType()));
22648 // Zero extend the condition if needed.
22649 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22651 // Scale the condition by the difference.
22653 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22654 DAG.getConstant(Diff, Cond.getValueType()));
22656 // Add the base if non-zero.
22657 if (FalseC->getAPIntValue() != 0)
22658 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22659 SDValue(FalseC, 0));
22666 // Canonicalize max and min:
22667 // (x > y) ? x : y -> (x >= y) ? x : y
22668 // (x < y) ? x : y -> (x <= y) ? x : y
22669 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22670 // the need for an extra compare
22671 // against zero. e.g.
22672 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22674 // testl %edi, %edi
22676 // cmovgl %edi, %eax
22680 // cmovsl %eax, %edi
22681 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22682 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22683 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22684 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22689 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22690 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22691 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22692 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22697 // Early exit check
22698 if (!TLI.isTypeLegal(VT))
22701 // Match VSELECTs into subs with unsigned saturation.
22702 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22703 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22704 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22705 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22706 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22708 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22709 // left side invert the predicate to simplify logic below.
22711 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22713 CC = ISD::getSetCCInverse(CC, true);
22714 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22718 if (Other.getNode() && Other->getNumOperands() == 2 &&
22719 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22720 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22721 SDValue CondRHS = Cond->getOperand(1);
22723 // Look for a general sub with unsigned saturation first.
22724 // x >= y ? x-y : 0 --> subus x, y
22725 // x > y ? x-y : 0 --> subus x, y
22726 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22727 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22728 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22730 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22731 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22732 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22733 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22734 // If the RHS is a constant we have to reverse the const
22735 // canonicalization.
22736 // x > C-1 ? x+-C : 0 --> subus x, C
22737 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22738 CondRHSConst->getAPIntValue() ==
22739 (-OpRHSConst->getAPIntValue() - 1))
22740 return DAG.getNode(
22741 X86ISD::SUBUS, DL, VT, OpLHS,
22742 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22744 // Another special case: If C was a sign bit, the sub has been
22745 // canonicalized into a xor.
22746 // FIXME: Would it be better to use computeKnownBits to determine
22747 // whether it's safe to decanonicalize the xor?
22748 // x s< 0 ? x^C : 0 --> subus x, C
22749 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22750 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22751 OpRHSConst->getAPIntValue().isSignBit())
22752 // Note that we have to rebuild the RHS constant here to ensure we
22753 // don't rely on particular values of undef lanes.
22754 return DAG.getNode(
22755 X86ISD::SUBUS, DL, VT, OpLHS,
22756 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22761 // Try to match a min/max vector operation.
22762 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22763 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22764 unsigned Opc = ret.first;
22765 bool NeedSplit = ret.second;
22767 if (Opc && NeedSplit) {
22768 unsigned NumElems = VT.getVectorNumElements();
22769 // Extract the LHS vectors
22770 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22771 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22773 // Extract the RHS vectors
22774 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22775 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22777 // Create min/max for each subvector
22778 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22779 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22781 // Merge the result
22782 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22784 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22787 // Simplify vector selection if condition value type matches vselect
22789 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22790 assert(Cond.getValueType().isVector() &&
22791 "vector select expects a vector selector!");
22793 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22794 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22796 // Try invert the condition if true value is not all 1s and false value
22798 if (!TValIsAllOnes && !FValIsAllZeros &&
22799 // Check if the selector will be produced by CMPP*/PCMP*
22800 Cond.getOpcode() == ISD::SETCC &&
22801 // Check if SETCC has already been promoted
22802 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
22803 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22804 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22806 if (TValIsAllZeros || FValIsAllOnes) {
22807 SDValue CC = Cond.getOperand(2);
22808 ISD::CondCode NewCC =
22809 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22810 Cond.getOperand(0).getValueType().isInteger());
22811 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22812 std::swap(LHS, RHS);
22813 TValIsAllOnes = FValIsAllOnes;
22814 FValIsAllZeros = TValIsAllZeros;
22818 if (TValIsAllOnes || FValIsAllZeros) {
22821 if (TValIsAllOnes && FValIsAllZeros)
22823 else if (TValIsAllOnes)
22824 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22825 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22826 else if (FValIsAllZeros)
22827 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22828 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22830 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22834 // Try to fold this VSELECT into a MOVSS/MOVSD
22835 if (N->getOpcode() == ISD::VSELECT &&
22836 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22837 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22838 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22839 bool CanFold = false;
22840 unsigned NumElems = Cond.getNumOperands();
22844 if (isZero(Cond.getOperand(0))) {
22847 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22848 // fold (vselect <0,-1> -> (movsd A, B)
22849 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22850 CanFold = isAllOnes(Cond.getOperand(i));
22851 } else if (isAllOnes(Cond.getOperand(0))) {
22855 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22856 // fold (vselect <-1,0> -> (movsd B, A)
22857 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22858 CanFold = isZero(Cond.getOperand(i));
22862 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22863 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22864 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22867 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22868 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22869 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22870 // (v2i64 (bitcast B)))))
22872 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22873 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22874 // (v2f64 (bitcast B)))))
22876 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22877 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22878 // (v2i64 (bitcast A)))))
22880 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22881 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22882 // (v2f64 (bitcast A)))))
22884 CanFold = (isZero(Cond.getOperand(0)) &&
22885 isZero(Cond.getOperand(1)) &&
22886 isAllOnes(Cond.getOperand(2)) &&
22887 isAllOnes(Cond.getOperand(3)));
22889 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22890 isAllOnes(Cond.getOperand(1)) &&
22891 isZero(Cond.getOperand(2)) &&
22892 isZero(Cond.getOperand(3))) {
22894 std::swap(LHS, RHS);
22898 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22899 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22900 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22901 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22903 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22909 // If we know that this node is legal then we know that it is going to be
22910 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22911 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22912 // to simplify previous instructions.
22913 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22914 !DCI.isBeforeLegalize() &&
22915 // We explicitly check against v8i16 and v16i16 because, although
22916 // they're marked as Custom, they might only be legal when Cond is a
22917 // build_vector of constants. This will be taken care in a later
22919 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22920 VT != MVT::v8i16) &&
22921 // Don't optimize vector of constants. Those are handled by
22922 // the generic code and all the bits must be properly set for
22923 // the generic optimizer.
22924 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
22925 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22927 // Don't optimize vector selects that map to mask-registers.
22931 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22932 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22934 APInt KnownZero, KnownOne;
22935 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22936 DCI.isBeforeLegalizeOps());
22937 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22938 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22940 // If we changed the computation somewhere in the DAG, this change
22941 // will affect all users of Cond.
22942 // Make sure it is fine and update all the nodes so that we do not
22943 // use the generic VSELECT anymore. Otherwise, we may perform
22944 // wrong optimizations as we messed up with the actual expectation
22945 // for the vector boolean values.
22946 if (Cond != TLO.Old) {
22947 // Check all uses of that condition operand to check whether it will be
22948 // consumed by non-BLEND instructions, which may depend on all bits are
22950 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22952 if (I->getOpcode() != ISD::VSELECT)
22953 // TODO: Add other opcodes eventually lowered into BLEND.
22956 // Update all the users of the condition, before committing the change,
22957 // so that the VSELECT optimizations that expect the correct vector
22958 // boolean value will not be triggered.
22959 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22961 DAG.ReplaceAllUsesOfValueWith(
22963 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22964 Cond, I->getOperand(1), I->getOperand(2)));
22965 DCI.CommitTargetLoweringOpt(TLO);
22968 // At this point, only Cond is changed. Change the condition
22969 // just for N to keep the opportunity to optimize all other
22970 // users their own way.
22971 DAG.ReplaceAllUsesOfValueWith(
22973 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22974 TLO.New, N->getOperand(1), N->getOperand(2)));
22979 // We should generate an X86ISD::BLENDI from a vselect if its argument
22980 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22981 // constants. This specific pattern gets generated when we split a
22982 // selector for a 512 bit vector in a machine without AVX512 (but with
22983 // 256-bit vectors), during legalization:
22985 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22987 // Iff we find this pattern and the build_vectors are built from
22988 // constants, we translate the vselect into a shuffle_vector that we
22989 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22990 if ((N->getOpcode() == ISD::VSELECT ||
22991 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
22992 !DCI.isBeforeLegalize()) {
22993 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22994 if (Shuffle.getNode())
23001 // Check whether a boolean test is testing a boolean value generated by
23002 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23005 // Simplify the following patterns:
23006 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23007 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23008 // to (Op EFLAGS Cond)
23010 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23011 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23012 // to (Op EFLAGS !Cond)
23014 // where Op could be BRCOND or CMOV.
23016 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23017 // Quit if not CMP and SUB with its value result used.
23018 if (Cmp.getOpcode() != X86ISD::CMP &&
23019 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23022 // Quit if not used as a boolean value.
23023 if (CC != X86::COND_E && CC != X86::COND_NE)
23026 // Check CMP operands. One of them should be 0 or 1 and the other should be
23027 // an SetCC or extended from it.
23028 SDValue Op1 = Cmp.getOperand(0);
23029 SDValue Op2 = Cmp.getOperand(1);
23032 const ConstantSDNode* C = nullptr;
23033 bool needOppositeCond = (CC == X86::COND_E);
23034 bool checkAgainstTrue = false; // Is it a comparison against 1?
23036 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23038 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23040 else // Quit if all operands are not constants.
23043 if (C->getZExtValue() == 1) {
23044 needOppositeCond = !needOppositeCond;
23045 checkAgainstTrue = true;
23046 } else if (C->getZExtValue() != 0)
23047 // Quit if the constant is neither 0 or 1.
23050 bool truncatedToBoolWithAnd = false;
23051 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23052 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23053 SetCC.getOpcode() == ISD::TRUNCATE ||
23054 SetCC.getOpcode() == ISD::AND) {
23055 if (SetCC.getOpcode() == ISD::AND) {
23057 ConstantSDNode *CS;
23058 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23059 CS->getZExtValue() == 1)
23061 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23062 CS->getZExtValue() == 1)
23066 SetCC = SetCC.getOperand(OpIdx);
23067 truncatedToBoolWithAnd = true;
23069 SetCC = SetCC.getOperand(0);
23072 switch (SetCC.getOpcode()) {
23073 case X86ISD::SETCC_CARRY:
23074 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23075 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23076 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23077 // truncated to i1 using 'and'.
23078 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23080 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23081 "Invalid use of SETCC_CARRY!");
23083 case X86ISD::SETCC:
23084 // Set the condition code or opposite one if necessary.
23085 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23086 if (needOppositeCond)
23087 CC = X86::GetOppositeBranchCondition(CC);
23088 return SetCC.getOperand(1);
23089 case X86ISD::CMOV: {
23090 // Check whether false/true value has canonical one, i.e. 0 or 1.
23091 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23092 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23093 // Quit if true value is not a constant.
23096 // Quit if false value is not a constant.
23098 SDValue Op = SetCC.getOperand(0);
23099 // Skip 'zext' or 'trunc' node.
23100 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23101 Op.getOpcode() == ISD::TRUNCATE)
23102 Op = Op.getOperand(0);
23103 // A special case for rdrand/rdseed, where 0 is set if false cond is
23105 if ((Op.getOpcode() != X86ISD::RDRAND &&
23106 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23109 // Quit if false value is not the constant 0 or 1.
23110 bool FValIsFalse = true;
23111 if (FVal && FVal->getZExtValue() != 0) {
23112 if (FVal->getZExtValue() != 1)
23114 // If FVal is 1, opposite cond is needed.
23115 needOppositeCond = !needOppositeCond;
23116 FValIsFalse = false;
23118 // Quit if TVal is not the constant opposite of FVal.
23119 if (FValIsFalse && TVal->getZExtValue() != 1)
23121 if (!FValIsFalse && TVal->getZExtValue() != 0)
23123 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23124 if (needOppositeCond)
23125 CC = X86::GetOppositeBranchCondition(CC);
23126 return SetCC.getOperand(3);
23133 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23134 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23135 TargetLowering::DAGCombinerInfo &DCI,
23136 const X86Subtarget *Subtarget) {
23139 // If the flag operand isn't dead, don't touch this CMOV.
23140 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23143 SDValue FalseOp = N->getOperand(0);
23144 SDValue TrueOp = N->getOperand(1);
23145 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23146 SDValue Cond = N->getOperand(3);
23148 if (CC == X86::COND_E || CC == X86::COND_NE) {
23149 switch (Cond.getOpcode()) {
23153 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23154 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23155 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23161 Flags = checkBoolTestSetCCCombine(Cond, CC);
23162 if (Flags.getNode() &&
23163 // Extra check as FCMOV only supports a subset of X86 cond.
23164 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23165 SDValue Ops[] = { FalseOp, TrueOp,
23166 DAG.getConstant(CC, MVT::i8), Flags };
23167 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23170 // If this is a select between two integer constants, try to do some
23171 // optimizations. Note that the operands are ordered the opposite of SELECT
23173 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23174 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23175 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23176 // larger than FalseC (the false value).
23177 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23178 CC = X86::GetOppositeBranchCondition(CC);
23179 std::swap(TrueC, FalseC);
23180 std::swap(TrueOp, FalseOp);
23183 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23184 // This is efficient for any integer data type (including i8/i16) and
23186 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23187 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23188 DAG.getConstant(CC, MVT::i8), Cond);
23190 // Zero extend the condition if needed.
23191 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23193 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23194 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23195 DAG.getConstant(ShAmt, MVT::i8));
23196 if (N->getNumValues() == 2) // Dead flag value?
23197 return DCI.CombineTo(N, Cond, SDValue());
23201 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23202 // for any integer data type, including i8/i16.
23203 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23204 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23205 DAG.getConstant(CC, MVT::i8), Cond);
23207 // Zero extend the condition if needed.
23208 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23209 FalseC->getValueType(0), Cond);
23210 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23211 SDValue(FalseC, 0));
23213 if (N->getNumValues() == 2) // Dead flag value?
23214 return DCI.CombineTo(N, Cond, SDValue());
23218 // Optimize cases that will turn into an LEA instruction. This requires
23219 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23220 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23221 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23222 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23224 bool isFastMultiplier = false;
23226 switch ((unsigned char)Diff) {
23228 case 1: // result = add base, cond
23229 case 2: // result = lea base( , cond*2)
23230 case 3: // result = lea base(cond, cond*2)
23231 case 4: // result = lea base( , cond*4)
23232 case 5: // result = lea base(cond, cond*4)
23233 case 8: // result = lea base( , cond*8)
23234 case 9: // result = lea base(cond, cond*8)
23235 isFastMultiplier = true;
23240 if (isFastMultiplier) {
23241 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23242 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23243 DAG.getConstant(CC, MVT::i8), Cond);
23244 // Zero extend the condition if needed.
23245 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23247 // Scale the condition by the difference.
23249 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23250 DAG.getConstant(Diff, Cond.getValueType()));
23252 // Add the base if non-zero.
23253 if (FalseC->getAPIntValue() != 0)
23254 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23255 SDValue(FalseC, 0));
23256 if (N->getNumValues() == 2) // Dead flag value?
23257 return DCI.CombineTo(N, Cond, SDValue());
23264 // Handle these cases:
23265 // (select (x != c), e, c) -> select (x != c), e, x),
23266 // (select (x == c), c, e) -> select (x == c), x, e)
23267 // where the c is an integer constant, and the "select" is the combination
23268 // of CMOV and CMP.
23270 // The rationale for this change is that the conditional-move from a constant
23271 // needs two instructions, however, conditional-move from a register needs
23272 // only one instruction.
23274 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23275 // some instruction-combining opportunities. This opt needs to be
23276 // postponed as late as possible.
23278 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23279 // the DCI.xxxx conditions are provided to postpone the optimization as
23280 // late as possible.
23282 ConstantSDNode *CmpAgainst = nullptr;
23283 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23284 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23285 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23287 if (CC == X86::COND_NE &&
23288 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23289 CC = X86::GetOppositeBranchCondition(CC);
23290 std::swap(TrueOp, FalseOp);
23293 if (CC == X86::COND_E &&
23294 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23295 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23296 DAG.getConstant(CC, MVT::i8), Cond };
23297 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23305 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23306 const X86Subtarget *Subtarget) {
23307 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23309 default: return SDValue();
23310 // SSE/AVX/AVX2 blend intrinsics.
23311 case Intrinsic::x86_avx2_pblendvb:
23312 case Intrinsic::x86_avx2_pblendw:
23313 case Intrinsic::x86_avx2_pblendd_128:
23314 case Intrinsic::x86_avx2_pblendd_256:
23315 // Don't try to simplify this intrinsic if we don't have AVX2.
23316 if (!Subtarget->hasAVX2())
23319 case Intrinsic::x86_avx_blend_pd_256:
23320 case Intrinsic::x86_avx_blend_ps_256:
23321 case Intrinsic::x86_avx_blendv_pd_256:
23322 case Intrinsic::x86_avx_blendv_ps_256:
23323 // Don't try to simplify this intrinsic if we don't have AVX.
23324 if (!Subtarget->hasAVX())
23327 case Intrinsic::x86_sse41_pblendw:
23328 case Intrinsic::x86_sse41_blendpd:
23329 case Intrinsic::x86_sse41_blendps:
23330 case Intrinsic::x86_sse41_blendvps:
23331 case Intrinsic::x86_sse41_blendvpd:
23332 case Intrinsic::x86_sse41_pblendvb: {
23333 SDValue Op0 = N->getOperand(1);
23334 SDValue Op1 = N->getOperand(2);
23335 SDValue Mask = N->getOperand(3);
23337 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23338 if (!Subtarget->hasSSE41())
23341 // fold (blend A, A, Mask) -> A
23344 // fold (blend A, B, allZeros) -> A
23345 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23347 // fold (blend A, B, allOnes) -> B
23348 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23351 // Simplify the case where the mask is a constant i32 value.
23352 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23353 if (C->isNullValue())
23355 if (C->isAllOnesValue())
23362 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23363 case Intrinsic::x86_sse2_psrai_w:
23364 case Intrinsic::x86_sse2_psrai_d:
23365 case Intrinsic::x86_avx2_psrai_w:
23366 case Intrinsic::x86_avx2_psrai_d:
23367 case Intrinsic::x86_sse2_psra_w:
23368 case Intrinsic::x86_sse2_psra_d:
23369 case Intrinsic::x86_avx2_psra_w:
23370 case Intrinsic::x86_avx2_psra_d: {
23371 SDValue Op0 = N->getOperand(1);
23372 SDValue Op1 = N->getOperand(2);
23373 EVT VT = Op0.getValueType();
23374 assert(VT.isVector() && "Expected a vector type!");
23376 if (isa<BuildVectorSDNode>(Op1))
23377 Op1 = Op1.getOperand(0);
23379 if (!isa<ConstantSDNode>(Op1))
23382 EVT SVT = VT.getVectorElementType();
23383 unsigned SVTBits = SVT.getSizeInBits();
23385 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23386 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23387 uint64_t ShAmt = C.getZExtValue();
23389 // Don't try to convert this shift into a ISD::SRA if the shift
23390 // count is bigger than or equal to the element size.
23391 if (ShAmt >= SVTBits)
23394 // Trivial case: if the shift count is zero, then fold this
23395 // into the first operand.
23399 // Replace this packed shift intrinsic with a target independent
23401 SDValue Splat = DAG.getConstant(C, VT);
23402 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23407 /// PerformMulCombine - Optimize a single multiply with constant into two
23408 /// in order to implement it with two cheaper instructions, e.g.
23409 /// LEA + SHL, LEA + LEA.
23410 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23411 TargetLowering::DAGCombinerInfo &DCI) {
23412 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23415 EVT VT = N->getValueType(0);
23416 if (VT != MVT::i64)
23419 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23422 uint64_t MulAmt = C->getZExtValue();
23423 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23426 uint64_t MulAmt1 = 0;
23427 uint64_t MulAmt2 = 0;
23428 if ((MulAmt % 9) == 0) {
23430 MulAmt2 = MulAmt / 9;
23431 } else if ((MulAmt % 5) == 0) {
23433 MulAmt2 = MulAmt / 5;
23434 } else if ((MulAmt % 3) == 0) {
23436 MulAmt2 = MulAmt / 3;
23439 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23442 if (isPowerOf2_64(MulAmt2) &&
23443 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23444 // If second multiplifer is pow2, issue it first. We want the multiply by
23445 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23447 std::swap(MulAmt1, MulAmt2);
23450 if (isPowerOf2_64(MulAmt1))
23451 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23452 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23454 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23455 DAG.getConstant(MulAmt1, VT));
23457 if (isPowerOf2_64(MulAmt2))
23458 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23459 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23461 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23462 DAG.getConstant(MulAmt2, VT));
23464 // Do not add new nodes to DAG combiner worklist.
23465 DCI.CombineTo(N, NewMul, false);
23470 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23471 SDValue N0 = N->getOperand(0);
23472 SDValue N1 = N->getOperand(1);
23473 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23474 EVT VT = N0.getValueType();
23476 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23477 // since the result of setcc_c is all zero's or all ones.
23478 if (VT.isInteger() && !VT.isVector() &&
23479 N1C && N0.getOpcode() == ISD::AND &&
23480 N0.getOperand(1).getOpcode() == ISD::Constant) {
23481 SDValue N00 = N0.getOperand(0);
23482 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23483 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23484 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23485 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23486 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23487 APInt ShAmt = N1C->getAPIntValue();
23488 Mask = Mask.shl(ShAmt);
23490 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23491 N00, DAG.getConstant(Mask, VT));
23495 // Hardware support for vector shifts is sparse which makes us scalarize the
23496 // vector operations in many cases. Also, on sandybridge ADD is faster than
23498 // (shl V, 1) -> add V,V
23499 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23500 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23501 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23502 // We shift all of the values by one. In many cases we do not have
23503 // hardware support for this operation. This is better expressed as an ADD
23505 if (N1SplatC->getZExtValue() == 1)
23506 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23512 /// \brief Returns a vector of 0s if the node in input is a vector logical
23513 /// shift by a constant amount which is known to be bigger than or equal
23514 /// to the vector element size in bits.
23515 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23516 const X86Subtarget *Subtarget) {
23517 EVT VT = N->getValueType(0);
23519 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23520 (!Subtarget->hasInt256() ||
23521 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23524 SDValue Amt = N->getOperand(1);
23526 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23527 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23528 APInt ShiftAmt = AmtSplat->getAPIntValue();
23529 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23531 // SSE2/AVX2 logical shifts always return a vector of 0s
23532 // if the shift amount is bigger than or equal to
23533 // the element size. The constant shift amount will be
23534 // encoded as a 8-bit immediate.
23535 if (ShiftAmt.trunc(8).uge(MaxAmount))
23536 return getZeroVector(VT, Subtarget, DAG, DL);
23542 /// PerformShiftCombine - Combine shifts.
23543 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23544 TargetLowering::DAGCombinerInfo &DCI,
23545 const X86Subtarget *Subtarget) {
23546 if (N->getOpcode() == ISD::SHL) {
23547 SDValue V = PerformSHLCombine(N, DAG);
23548 if (V.getNode()) return V;
23551 if (N->getOpcode() != ISD::SRA) {
23552 // Try to fold this logical shift into a zero vector.
23553 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23554 if (V.getNode()) return V;
23560 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23561 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23562 // and friends. Likewise for OR -> CMPNEQSS.
23563 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23564 TargetLowering::DAGCombinerInfo &DCI,
23565 const X86Subtarget *Subtarget) {
23568 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23569 // we're requiring SSE2 for both.
23570 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23571 SDValue N0 = N->getOperand(0);
23572 SDValue N1 = N->getOperand(1);
23573 SDValue CMP0 = N0->getOperand(1);
23574 SDValue CMP1 = N1->getOperand(1);
23577 // The SETCCs should both refer to the same CMP.
23578 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23581 SDValue CMP00 = CMP0->getOperand(0);
23582 SDValue CMP01 = CMP0->getOperand(1);
23583 EVT VT = CMP00.getValueType();
23585 if (VT == MVT::f32 || VT == MVT::f64) {
23586 bool ExpectingFlags = false;
23587 // Check for any users that want flags:
23588 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23589 !ExpectingFlags && UI != UE; ++UI)
23590 switch (UI->getOpcode()) {
23595 ExpectingFlags = true;
23597 case ISD::CopyToReg:
23598 case ISD::SIGN_EXTEND:
23599 case ISD::ZERO_EXTEND:
23600 case ISD::ANY_EXTEND:
23604 if (!ExpectingFlags) {
23605 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23606 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23608 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23609 X86::CondCode tmp = cc0;
23614 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23615 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23616 // FIXME: need symbolic constants for these magic numbers.
23617 // See X86ATTInstPrinter.cpp:printSSECC().
23618 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23619 if (Subtarget->hasAVX512()) {
23620 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23621 CMP01, DAG.getConstant(x86cc, MVT::i8));
23622 if (N->getValueType(0) != MVT::i1)
23623 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23627 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23628 CMP00.getValueType(), CMP00, CMP01,
23629 DAG.getConstant(x86cc, MVT::i8));
23631 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23632 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23634 if (is64BitFP && !Subtarget->is64Bit()) {
23635 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23636 // 64-bit integer, since that's not a legal type. Since
23637 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23638 // bits, but can do this little dance to extract the lowest 32 bits
23639 // and work with those going forward.
23640 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23642 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23644 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23645 Vector32, DAG.getIntPtrConstant(0));
23649 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23650 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23651 DAG.getConstant(1, IntVT));
23652 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23653 return OneBitOfTruth;
23661 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23662 /// so it can be folded inside ANDNP.
23663 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23664 EVT VT = N->getValueType(0);
23666 // Match direct AllOnes for 128 and 256-bit vectors
23667 if (ISD::isBuildVectorAllOnes(N))
23670 // Look through a bit convert.
23671 if (N->getOpcode() == ISD::BITCAST)
23672 N = N->getOperand(0).getNode();
23674 // Sometimes the operand may come from a insert_subvector building a 256-bit
23676 if (VT.is256BitVector() &&
23677 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23678 SDValue V1 = N->getOperand(0);
23679 SDValue V2 = N->getOperand(1);
23681 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23682 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23683 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23684 ISD::isBuildVectorAllOnes(V2.getNode()))
23691 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23692 // register. In most cases we actually compare or select YMM-sized registers
23693 // and mixing the two types creates horrible code. This method optimizes
23694 // some of the transition sequences.
23695 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23696 TargetLowering::DAGCombinerInfo &DCI,
23697 const X86Subtarget *Subtarget) {
23698 EVT VT = N->getValueType(0);
23699 if (!VT.is256BitVector())
23702 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23703 N->getOpcode() == ISD::ZERO_EXTEND ||
23704 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23706 SDValue Narrow = N->getOperand(0);
23707 EVT NarrowVT = Narrow->getValueType(0);
23708 if (!NarrowVT.is128BitVector())
23711 if (Narrow->getOpcode() != ISD::XOR &&
23712 Narrow->getOpcode() != ISD::AND &&
23713 Narrow->getOpcode() != ISD::OR)
23716 SDValue N0 = Narrow->getOperand(0);
23717 SDValue N1 = Narrow->getOperand(1);
23720 // The Left side has to be a trunc.
23721 if (N0.getOpcode() != ISD::TRUNCATE)
23724 // The type of the truncated inputs.
23725 EVT WideVT = N0->getOperand(0)->getValueType(0);
23729 // The right side has to be a 'trunc' or a constant vector.
23730 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23731 ConstantSDNode *RHSConstSplat = nullptr;
23732 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23733 RHSConstSplat = RHSBV->getConstantSplatNode();
23734 if (!RHSTrunc && !RHSConstSplat)
23737 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23739 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23742 // Set N0 and N1 to hold the inputs to the new wide operation.
23743 N0 = N0->getOperand(0);
23744 if (RHSConstSplat) {
23745 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23746 SDValue(RHSConstSplat, 0));
23747 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23748 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23749 } else if (RHSTrunc) {
23750 N1 = N1->getOperand(0);
23753 // Generate the wide operation.
23754 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23755 unsigned Opcode = N->getOpcode();
23757 case ISD::ANY_EXTEND:
23759 case ISD::ZERO_EXTEND: {
23760 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23761 APInt Mask = APInt::getAllOnesValue(InBits);
23762 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23763 return DAG.getNode(ISD::AND, DL, VT,
23764 Op, DAG.getConstant(Mask, VT));
23766 case ISD::SIGN_EXTEND:
23767 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23768 Op, DAG.getValueType(NarrowVT));
23770 llvm_unreachable("Unexpected opcode");
23774 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23775 TargetLowering::DAGCombinerInfo &DCI,
23776 const X86Subtarget *Subtarget) {
23777 EVT VT = N->getValueType(0);
23778 if (DCI.isBeforeLegalizeOps())
23781 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23785 // Create BEXTR instructions
23786 // BEXTR is ((X >> imm) & (2**size-1))
23787 if (VT == MVT::i32 || VT == MVT::i64) {
23788 SDValue N0 = N->getOperand(0);
23789 SDValue N1 = N->getOperand(1);
23792 // Check for BEXTR.
23793 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23794 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23795 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23796 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23797 if (MaskNode && ShiftNode) {
23798 uint64_t Mask = MaskNode->getZExtValue();
23799 uint64_t Shift = ShiftNode->getZExtValue();
23800 if (isMask_64(Mask)) {
23801 uint64_t MaskSize = CountPopulation_64(Mask);
23802 if (Shift + MaskSize <= VT.getSizeInBits())
23803 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23804 DAG.getConstant(Shift | (MaskSize << 8), VT));
23812 // Want to form ANDNP nodes:
23813 // 1) In the hopes of then easily combining them with OR and AND nodes
23814 // to form PBLEND/PSIGN.
23815 // 2) To match ANDN packed intrinsics
23816 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23819 SDValue N0 = N->getOperand(0);
23820 SDValue N1 = N->getOperand(1);
23823 // Check LHS for vnot
23824 if (N0.getOpcode() == ISD::XOR &&
23825 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23826 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23827 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23829 // Check RHS for vnot
23830 if (N1.getOpcode() == ISD::XOR &&
23831 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23832 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23833 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23838 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23839 TargetLowering::DAGCombinerInfo &DCI,
23840 const X86Subtarget *Subtarget) {
23841 if (DCI.isBeforeLegalizeOps())
23844 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23848 SDValue N0 = N->getOperand(0);
23849 SDValue N1 = N->getOperand(1);
23850 EVT VT = N->getValueType(0);
23852 // look for psign/blend
23853 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23854 if (!Subtarget->hasSSSE3() ||
23855 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23858 // Canonicalize pandn to RHS
23859 if (N0.getOpcode() == X86ISD::ANDNP)
23861 // or (and (m, y), (pandn m, x))
23862 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23863 SDValue Mask = N1.getOperand(0);
23864 SDValue X = N1.getOperand(1);
23866 if (N0.getOperand(0) == Mask)
23867 Y = N0.getOperand(1);
23868 if (N0.getOperand(1) == Mask)
23869 Y = N0.getOperand(0);
23871 // Check to see if the mask appeared in both the AND and ANDNP and
23875 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23876 // Look through mask bitcast.
23877 if (Mask.getOpcode() == ISD::BITCAST)
23878 Mask = Mask.getOperand(0);
23879 if (X.getOpcode() == ISD::BITCAST)
23880 X = X.getOperand(0);
23881 if (Y.getOpcode() == ISD::BITCAST)
23882 Y = Y.getOperand(0);
23884 EVT MaskVT = Mask.getValueType();
23886 // Validate that the Mask operand is a vector sra node.
23887 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23888 // there is no psrai.b
23889 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23890 unsigned SraAmt = ~0;
23891 if (Mask.getOpcode() == ISD::SRA) {
23892 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23893 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23894 SraAmt = AmtConst->getZExtValue();
23895 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23896 SDValue SraC = Mask.getOperand(1);
23897 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23899 if ((SraAmt + 1) != EltBits)
23904 // Now we know we at least have a plendvb with the mask val. See if
23905 // we can form a psignb/w/d.
23906 // psign = x.type == y.type == mask.type && y = sub(0, x);
23907 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23908 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23909 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23910 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23911 "Unsupported VT for PSIGN");
23912 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23913 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23915 // PBLENDVB only available on SSE 4.1
23916 if (!Subtarget->hasSSE41())
23919 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23921 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23922 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23923 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23924 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23925 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23929 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23932 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23933 MachineFunction &MF = DAG.getMachineFunction();
23934 bool OptForSize = MF.getFunction()->getAttributes().
23935 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23937 // SHLD/SHRD instructions have lower register pressure, but on some
23938 // platforms they have higher latency than the equivalent
23939 // series of shifts/or that would otherwise be generated.
23940 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23941 // have higher latencies and we are not optimizing for size.
23942 if (!OptForSize && Subtarget->isSHLDSlow())
23945 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23947 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23949 if (!N0.hasOneUse() || !N1.hasOneUse())
23952 SDValue ShAmt0 = N0.getOperand(1);
23953 if (ShAmt0.getValueType() != MVT::i8)
23955 SDValue ShAmt1 = N1.getOperand(1);
23956 if (ShAmt1.getValueType() != MVT::i8)
23958 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23959 ShAmt0 = ShAmt0.getOperand(0);
23960 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23961 ShAmt1 = ShAmt1.getOperand(0);
23964 unsigned Opc = X86ISD::SHLD;
23965 SDValue Op0 = N0.getOperand(0);
23966 SDValue Op1 = N1.getOperand(0);
23967 if (ShAmt0.getOpcode() == ISD::SUB) {
23968 Opc = X86ISD::SHRD;
23969 std::swap(Op0, Op1);
23970 std::swap(ShAmt0, ShAmt1);
23973 unsigned Bits = VT.getSizeInBits();
23974 if (ShAmt1.getOpcode() == ISD::SUB) {
23975 SDValue Sum = ShAmt1.getOperand(0);
23976 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23977 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23978 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23979 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23980 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23981 return DAG.getNode(Opc, DL, VT,
23983 DAG.getNode(ISD::TRUNCATE, DL,
23986 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23987 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23989 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23990 return DAG.getNode(Opc, DL, VT,
23991 N0.getOperand(0), N1.getOperand(0),
23992 DAG.getNode(ISD::TRUNCATE, DL,
23999 // Generate NEG and CMOV for integer abs.
24000 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24001 EVT VT = N->getValueType(0);
24003 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24004 // 8-bit integer abs to NEG and CMOV.
24005 if (VT.isInteger() && VT.getSizeInBits() == 8)
24008 SDValue N0 = N->getOperand(0);
24009 SDValue N1 = N->getOperand(1);
24012 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24013 // and change it to SUB and CMOV.
24014 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24015 N0.getOpcode() == ISD::ADD &&
24016 N0.getOperand(1) == N1 &&
24017 N1.getOpcode() == ISD::SRA &&
24018 N1.getOperand(0) == N0.getOperand(0))
24019 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24020 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24021 // Generate SUB & CMOV.
24022 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24023 DAG.getConstant(0, VT), N0.getOperand(0));
24025 SDValue Ops[] = { N0.getOperand(0), Neg,
24026 DAG.getConstant(X86::COND_GE, MVT::i8),
24027 SDValue(Neg.getNode(), 1) };
24028 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24033 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24034 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24035 TargetLowering::DAGCombinerInfo &DCI,
24036 const X86Subtarget *Subtarget) {
24037 if (DCI.isBeforeLegalizeOps())
24040 if (Subtarget->hasCMov()) {
24041 SDValue RV = performIntegerAbsCombine(N, DAG);
24049 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24050 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24051 TargetLowering::DAGCombinerInfo &DCI,
24052 const X86Subtarget *Subtarget) {
24053 LoadSDNode *Ld = cast<LoadSDNode>(N);
24054 EVT RegVT = Ld->getValueType(0);
24055 EVT MemVT = Ld->getMemoryVT();
24057 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24059 // On Sandybridge unaligned 256bit loads are inefficient.
24060 ISD::LoadExtType Ext = Ld->getExtensionType();
24061 unsigned Alignment = Ld->getAlignment();
24062 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24063 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
24064 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24065 unsigned NumElems = RegVT.getVectorNumElements();
24069 SDValue Ptr = Ld->getBasePtr();
24070 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24072 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24074 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24075 Ld->getPointerInfo(), Ld->isVolatile(),
24076 Ld->isNonTemporal(), Ld->isInvariant(),
24078 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24079 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24080 Ld->getPointerInfo(), Ld->isVolatile(),
24081 Ld->isNonTemporal(), Ld->isInvariant(),
24082 std::min(16U, Alignment));
24083 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24085 Load2.getValue(1));
24087 SDValue NewVec = DAG.getUNDEF(RegVT);
24088 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24089 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24090 return DCI.CombineTo(N, NewVec, TF, true);
24096 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24097 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24098 const X86Subtarget *Subtarget) {
24099 StoreSDNode *St = cast<StoreSDNode>(N);
24100 EVT VT = St->getValue().getValueType();
24101 EVT StVT = St->getMemoryVT();
24103 SDValue StoredVal = St->getOperand(1);
24104 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24106 // If we are saving a concatenation of two XMM registers, perform two stores.
24107 // On Sandy Bridge, 256-bit memory operations are executed by two
24108 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
24109 // memory operation.
24110 unsigned Alignment = St->getAlignment();
24111 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24112 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
24113 StVT == VT && !IsAligned) {
24114 unsigned NumElems = VT.getVectorNumElements();
24118 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24119 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24121 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24122 SDValue Ptr0 = St->getBasePtr();
24123 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24125 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24126 St->getPointerInfo(), St->isVolatile(),
24127 St->isNonTemporal(), Alignment);
24128 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24129 St->getPointerInfo(), St->isVolatile(),
24130 St->isNonTemporal(),
24131 std::min(16U, Alignment));
24132 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24135 // Optimize trunc store (of multiple scalars) to shuffle and store.
24136 // First, pack all of the elements in one place. Next, store to memory
24137 // in fewer chunks.
24138 if (St->isTruncatingStore() && VT.isVector()) {
24139 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24140 unsigned NumElems = VT.getVectorNumElements();
24141 assert(StVT != VT && "Cannot truncate to the same type");
24142 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24143 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24145 // From, To sizes and ElemCount must be pow of two
24146 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24147 // We are going to use the original vector elt for storing.
24148 // Accumulated smaller vector elements must be a multiple of the store size.
24149 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24151 unsigned SizeRatio = FromSz / ToSz;
24153 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24155 // Create a type on which we perform the shuffle
24156 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24157 StVT.getScalarType(), NumElems*SizeRatio);
24159 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24161 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24162 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24163 for (unsigned i = 0; i != NumElems; ++i)
24164 ShuffleVec[i] = i * SizeRatio;
24166 // Can't shuffle using an illegal type.
24167 if (!TLI.isTypeLegal(WideVecVT))
24170 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24171 DAG.getUNDEF(WideVecVT),
24173 // At this point all of the data is stored at the bottom of the
24174 // register. We now need to save it to mem.
24176 // Find the largest store unit
24177 MVT StoreType = MVT::i8;
24178 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24179 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24180 MVT Tp = (MVT::SimpleValueType)tp;
24181 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24185 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24186 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24187 (64 <= NumElems * ToSz))
24188 StoreType = MVT::f64;
24190 // Bitcast the original vector into a vector of store-size units
24191 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24192 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24193 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24194 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24195 SmallVector<SDValue, 8> Chains;
24196 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24197 TLI.getPointerTy());
24198 SDValue Ptr = St->getBasePtr();
24200 // Perform one or more big stores into memory.
24201 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24202 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24203 StoreType, ShuffWide,
24204 DAG.getIntPtrConstant(i));
24205 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24206 St->getPointerInfo(), St->isVolatile(),
24207 St->isNonTemporal(), St->getAlignment());
24208 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24209 Chains.push_back(Ch);
24212 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24215 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24216 // the FP state in cases where an emms may be missing.
24217 // A preferable solution to the general problem is to figure out the right
24218 // places to insert EMMS. This qualifies as a quick hack.
24220 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24221 if (VT.getSizeInBits() != 64)
24224 const Function *F = DAG.getMachineFunction().getFunction();
24225 bool NoImplicitFloatOps = F->getAttributes().
24226 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24227 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24228 && Subtarget->hasSSE2();
24229 if ((VT.isVector() ||
24230 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24231 isa<LoadSDNode>(St->getValue()) &&
24232 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24233 St->getChain().hasOneUse() && !St->isVolatile()) {
24234 SDNode* LdVal = St->getValue().getNode();
24235 LoadSDNode *Ld = nullptr;
24236 int TokenFactorIndex = -1;
24237 SmallVector<SDValue, 8> Ops;
24238 SDNode* ChainVal = St->getChain().getNode();
24239 // Must be a store of a load. We currently handle two cases: the load
24240 // is a direct child, and it's under an intervening TokenFactor. It is
24241 // possible to dig deeper under nested TokenFactors.
24242 if (ChainVal == LdVal)
24243 Ld = cast<LoadSDNode>(St->getChain());
24244 else if (St->getValue().hasOneUse() &&
24245 ChainVal->getOpcode() == ISD::TokenFactor) {
24246 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24247 if (ChainVal->getOperand(i).getNode() == LdVal) {
24248 TokenFactorIndex = i;
24249 Ld = cast<LoadSDNode>(St->getValue());
24251 Ops.push_back(ChainVal->getOperand(i));
24255 if (!Ld || !ISD::isNormalLoad(Ld))
24258 // If this is not the MMX case, i.e. we are just turning i64 load/store
24259 // into f64 load/store, avoid the transformation if there are multiple
24260 // uses of the loaded value.
24261 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24266 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24267 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24269 if (Subtarget->is64Bit() || F64IsLegal) {
24270 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24271 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24272 Ld->getPointerInfo(), Ld->isVolatile(),
24273 Ld->isNonTemporal(), Ld->isInvariant(),
24274 Ld->getAlignment());
24275 SDValue NewChain = NewLd.getValue(1);
24276 if (TokenFactorIndex != -1) {
24277 Ops.push_back(NewChain);
24278 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24280 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24281 St->getPointerInfo(),
24282 St->isVolatile(), St->isNonTemporal(),
24283 St->getAlignment());
24286 // Otherwise, lower to two pairs of 32-bit loads / stores.
24287 SDValue LoAddr = Ld->getBasePtr();
24288 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24289 DAG.getConstant(4, MVT::i32));
24291 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24292 Ld->getPointerInfo(),
24293 Ld->isVolatile(), Ld->isNonTemporal(),
24294 Ld->isInvariant(), Ld->getAlignment());
24295 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24296 Ld->getPointerInfo().getWithOffset(4),
24297 Ld->isVolatile(), Ld->isNonTemporal(),
24299 MinAlign(Ld->getAlignment(), 4));
24301 SDValue NewChain = LoLd.getValue(1);
24302 if (TokenFactorIndex != -1) {
24303 Ops.push_back(LoLd);
24304 Ops.push_back(HiLd);
24305 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24308 LoAddr = St->getBasePtr();
24309 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24310 DAG.getConstant(4, MVT::i32));
24312 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24313 St->getPointerInfo(),
24314 St->isVolatile(), St->isNonTemporal(),
24315 St->getAlignment());
24316 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24317 St->getPointerInfo().getWithOffset(4),
24319 St->isNonTemporal(),
24320 MinAlign(St->getAlignment(), 4));
24321 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24326 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24327 /// and return the operands for the horizontal operation in LHS and RHS. A
24328 /// horizontal operation performs the binary operation on successive elements
24329 /// of its first operand, then on successive elements of its second operand,
24330 /// returning the resulting values in a vector. For example, if
24331 /// A = < float a0, float a1, float a2, float a3 >
24333 /// B = < float b0, float b1, float b2, float b3 >
24334 /// then the result of doing a horizontal operation on A and B is
24335 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24336 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24337 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24338 /// set to A, RHS to B, and the routine returns 'true'.
24339 /// Note that the binary operation should have the property that if one of the
24340 /// operands is UNDEF then the result is UNDEF.
24341 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24342 // Look for the following pattern: if
24343 // A = < float a0, float a1, float a2, float a3 >
24344 // B = < float b0, float b1, float b2, float b3 >
24346 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24347 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24348 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24349 // which is A horizontal-op B.
24351 // At least one of the operands should be a vector shuffle.
24352 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24353 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24356 MVT VT = LHS.getSimpleValueType();
24358 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24359 "Unsupported vector type for horizontal add/sub");
24361 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24362 // operate independently on 128-bit lanes.
24363 unsigned NumElts = VT.getVectorNumElements();
24364 unsigned NumLanes = VT.getSizeInBits()/128;
24365 unsigned NumLaneElts = NumElts / NumLanes;
24366 assert((NumLaneElts % 2 == 0) &&
24367 "Vector type should have an even number of elements in each lane");
24368 unsigned HalfLaneElts = NumLaneElts/2;
24370 // View LHS in the form
24371 // LHS = VECTOR_SHUFFLE A, B, LMask
24372 // If LHS is not a shuffle then pretend it is the shuffle
24373 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24374 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24377 SmallVector<int, 16> LMask(NumElts);
24378 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24379 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24380 A = LHS.getOperand(0);
24381 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24382 B = LHS.getOperand(1);
24383 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24384 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24386 if (LHS.getOpcode() != ISD::UNDEF)
24388 for (unsigned i = 0; i != NumElts; ++i)
24392 // Likewise, view RHS in the form
24393 // RHS = VECTOR_SHUFFLE C, D, RMask
24395 SmallVector<int, 16> RMask(NumElts);
24396 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24397 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24398 C = RHS.getOperand(0);
24399 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24400 D = RHS.getOperand(1);
24401 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24402 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24404 if (RHS.getOpcode() != ISD::UNDEF)
24406 for (unsigned i = 0; i != NumElts; ++i)
24410 // Check that the shuffles are both shuffling the same vectors.
24411 if (!(A == C && B == D) && !(A == D && B == C))
24414 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24415 if (!A.getNode() && !B.getNode())
24418 // If A and B occur in reverse order in RHS, then "swap" them (which means
24419 // rewriting the mask).
24421 CommuteVectorShuffleMask(RMask, NumElts);
24423 // At this point LHS and RHS are equivalent to
24424 // LHS = VECTOR_SHUFFLE A, B, LMask
24425 // RHS = VECTOR_SHUFFLE A, B, RMask
24426 // Check that the masks correspond to performing a horizontal operation.
24427 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24428 for (unsigned i = 0; i != NumLaneElts; ++i) {
24429 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24431 // Ignore any UNDEF components.
24432 if (LIdx < 0 || RIdx < 0 ||
24433 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24434 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24437 // Check that successive elements are being operated on. If not, this is
24438 // not a horizontal operation.
24439 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24440 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24441 if (!(LIdx == Index && RIdx == Index + 1) &&
24442 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24447 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24448 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24452 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24453 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24454 const X86Subtarget *Subtarget) {
24455 EVT VT = N->getValueType(0);
24456 SDValue LHS = N->getOperand(0);
24457 SDValue RHS = N->getOperand(1);
24459 // Try to synthesize horizontal adds from adds of shuffles.
24460 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24461 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24462 isHorizontalBinOp(LHS, RHS, true))
24463 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24467 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24468 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24469 const X86Subtarget *Subtarget) {
24470 EVT VT = N->getValueType(0);
24471 SDValue LHS = N->getOperand(0);
24472 SDValue RHS = N->getOperand(1);
24474 // Try to synthesize horizontal subs from subs of shuffles.
24475 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24476 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24477 isHorizontalBinOp(LHS, RHS, false))
24478 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24482 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24483 /// X86ISD::FXOR nodes.
24484 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24485 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24486 // F[X]OR(0.0, x) -> x
24487 // F[X]OR(x, 0.0) -> x
24488 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24489 if (C->getValueAPF().isPosZero())
24490 return N->getOperand(1);
24491 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24492 if (C->getValueAPF().isPosZero())
24493 return N->getOperand(0);
24497 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24498 /// X86ISD::FMAX nodes.
24499 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24500 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24502 // Only perform optimizations if UnsafeMath is used.
24503 if (!DAG.getTarget().Options.UnsafeFPMath)
24506 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24507 // into FMINC and FMAXC, which are Commutative operations.
24508 unsigned NewOp = 0;
24509 switch (N->getOpcode()) {
24510 default: llvm_unreachable("unknown opcode");
24511 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24512 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24515 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24516 N->getOperand(0), N->getOperand(1));
24519 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24520 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24521 // FAND(0.0, x) -> 0.0
24522 // FAND(x, 0.0) -> 0.0
24523 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24524 if (C->getValueAPF().isPosZero())
24525 return N->getOperand(0);
24526 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24527 if (C->getValueAPF().isPosZero())
24528 return N->getOperand(1);
24532 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24533 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24534 // FANDN(x, 0.0) -> 0.0
24535 // FANDN(0.0, x) -> x
24536 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24537 if (C->getValueAPF().isPosZero())
24538 return N->getOperand(1);
24539 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24540 if (C->getValueAPF().isPosZero())
24541 return N->getOperand(1);
24545 static SDValue PerformBTCombine(SDNode *N,
24547 TargetLowering::DAGCombinerInfo &DCI) {
24548 // BT ignores high bits in the bit index operand.
24549 SDValue Op1 = N->getOperand(1);
24550 if (Op1.hasOneUse()) {
24551 unsigned BitWidth = Op1.getValueSizeInBits();
24552 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24553 APInt KnownZero, KnownOne;
24554 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24555 !DCI.isBeforeLegalizeOps());
24556 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24557 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24558 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24559 DCI.CommitTargetLoweringOpt(TLO);
24564 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24565 SDValue Op = N->getOperand(0);
24566 if (Op.getOpcode() == ISD::BITCAST)
24567 Op = Op.getOperand(0);
24568 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24569 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24570 VT.getVectorElementType().getSizeInBits() ==
24571 OpVT.getVectorElementType().getSizeInBits()) {
24572 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24577 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24578 const X86Subtarget *Subtarget) {
24579 EVT VT = N->getValueType(0);
24580 if (!VT.isVector())
24583 SDValue N0 = N->getOperand(0);
24584 SDValue N1 = N->getOperand(1);
24585 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24588 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24589 // both SSE and AVX2 since there is no sign-extended shift right
24590 // operation on a vector with 64-bit elements.
24591 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24592 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24593 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24594 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24595 SDValue N00 = N0.getOperand(0);
24597 // EXTLOAD has a better solution on AVX2,
24598 // it may be replaced with X86ISD::VSEXT node.
24599 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24600 if (!ISD::isNormalLoad(N00.getNode()))
24603 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24604 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24606 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24612 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24613 TargetLowering::DAGCombinerInfo &DCI,
24614 const X86Subtarget *Subtarget) {
24615 SDValue N0 = N->getOperand(0);
24616 EVT VT = N->getValueType(0);
24618 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24619 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24620 // This exposes the sext to the sdivrem lowering, so that it directly extends
24621 // from AH (which we otherwise need to do contortions to access).
24622 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24623 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24625 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24626 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24627 N0.getOperand(0), N0.getOperand(1));
24628 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24629 return R.getValue(1);
24632 if (!DCI.isBeforeLegalizeOps())
24635 if (!Subtarget->hasFp256())
24638 if (VT.isVector() && VT.getSizeInBits() == 256) {
24639 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24647 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24648 const X86Subtarget* Subtarget) {
24650 EVT VT = N->getValueType(0);
24652 // Let legalize expand this if it isn't a legal type yet.
24653 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24656 EVT ScalarVT = VT.getScalarType();
24657 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24658 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24661 SDValue A = N->getOperand(0);
24662 SDValue B = N->getOperand(1);
24663 SDValue C = N->getOperand(2);
24665 bool NegA = (A.getOpcode() == ISD::FNEG);
24666 bool NegB = (B.getOpcode() == ISD::FNEG);
24667 bool NegC = (C.getOpcode() == ISD::FNEG);
24669 // Negative multiplication when NegA xor NegB
24670 bool NegMul = (NegA != NegB);
24672 A = A.getOperand(0);
24674 B = B.getOperand(0);
24676 C = C.getOperand(0);
24680 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24682 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24684 return DAG.getNode(Opcode, dl, VT, A, B, C);
24687 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24688 TargetLowering::DAGCombinerInfo &DCI,
24689 const X86Subtarget *Subtarget) {
24690 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24691 // (and (i32 x86isd::setcc_carry), 1)
24692 // This eliminates the zext. This transformation is necessary because
24693 // ISD::SETCC is always legalized to i8.
24695 SDValue N0 = N->getOperand(0);
24696 EVT VT = N->getValueType(0);
24698 if (N0.getOpcode() == ISD::AND &&
24700 N0.getOperand(0).hasOneUse()) {
24701 SDValue N00 = N0.getOperand(0);
24702 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24703 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24704 if (!C || C->getZExtValue() != 1)
24706 return DAG.getNode(ISD::AND, dl, VT,
24707 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24708 N00.getOperand(0), N00.getOperand(1)),
24709 DAG.getConstant(1, VT));
24713 if (N0.getOpcode() == ISD::TRUNCATE &&
24715 N0.getOperand(0).hasOneUse()) {
24716 SDValue N00 = N0.getOperand(0);
24717 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24718 return DAG.getNode(ISD::AND, dl, VT,
24719 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24720 N00.getOperand(0), N00.getOperand(1)),
24721 DAG.getConstant(1, VT));
24724 if (VT.is256BitVector()) {
24725 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24730 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24731 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24732 // This exposes the zext to the udivrem lowering, so that it directly extends
24733 // from AH (which we otherwise need to do contortions to access).
24734 if (N0.getOpcode() == ISD::UDIVREM &&
24735 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24736 (VT == MVT::i32 || VT == MVT::i64)) {
24737 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24738 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24739 N0.getOperand(0), N0.getOperand(1));
24740 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24741 return R.getValue(1);
24747 // Optimize x == -y --> x+y == 0
24748 // x != -y --> x+y != 0
24749 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24750 const X86Subtarget* Subtarget) {
24751 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24752 SDValue LHS = N->getOperand(0);
24753 SDValue RHS = N->getOperand(1);
24754 EVT VT = N->getValueType(0);
24757 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24758 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24759 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24760 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24761 LHS.getValueType(), RHS, LHS.getOperand(1));
24762 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24763 addV, DAG.getConstant(0, addV.getValueType()), CC);
24765 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24766 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24767 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24768 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24769 RHS.getValueType(), LHS, RHS.getOperand(1));
24770 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24771 addV, DAG.getConstant(0, addV.getValueType()), CC);
24774 if (VT.getScalarType() == MVT::i1) {
24775 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24776 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24777 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24778 if (!IsSEXT0 && !IsVZero0)
24780 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24781 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24782 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24784 if (!IsSEXT1 && !IsVZero1)
24787 if (IsSEXT0 && IsVZero1) {
24788 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24789 if (CC == ISD::SETEQ)
24790 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24791 return LHS.getOperand(0);
24793 if (IsSEXT1 && IsVZero0) {
24794 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24795 if (CC == ISD::SETEQ)
24796 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24797 return RHS.getOperand(0);
24804 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24805 const X86Subtarget *Subtarget) {
24807 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24808 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24809 "X86insertps is only defined for v4x32");
24811 SDValue Ld = N->getOperand(1);
24812 if (MayFoldLoad(Ld)) {
24813 // Extract the countS bits from the immediate so we can get the proper
24814 // address when narrowing the vector load to a specific element.
24815 // When the second source op is a memory address, interps doesn't use
24816 // countS and just gets an f32 from that address.
24817 unsigned DestIndex =
24818 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24819 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24823 // Create this as a scalar to vector to match the instruction pattern.
24824 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24825 // countS bits are ignored when loading from memory on insertps, which
24826 // means we don't need to explicitly set them to 0.
24827 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24828 LoadScalarToVector, N->getOperand(2));
24831 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24832 // as "sbb reg,reg", since it can be extended without zext and produces
24833 // an all-ones bit which is more useful than 0/1 in some cases.
24834 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24837 return DAG.getNode(ISD::AND, DL, VT,
24838 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24839 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24840 DAG.getConstant(1, VT));
24841 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24842 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24843 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24844 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24847 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24848 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24849 TargetLowering::DAGCombinerInfo &DCI,
24850 const X86Subtarget *Subtarget) {
24852 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24853 SDValue EFLAGS = N->getOperand(1);
24855 if (CC == X86::COND_A) {
24856 // Try to convert COND_A into COND_B in an attempt to facilitate
24857 // materializing "setb reg".
24859 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24860 // cannot take an immediate as its first operand.
24862 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24863 EFLAGS.getValueType().isInteger() &&
24864 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24865 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24866 EFLAGS.getNode()->getVTList(),
24867 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24868 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24869 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24873 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24874 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24876 if (CC == X86::COND_B)
24877 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24881 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24882 if (Flags.getNode()) {
24883 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24884 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24890 // Optimize branch condition evaluation.
24892 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24893 TargetLowering::DAGCombinerInfo &DCI,
24894 const X86Subtarget *Subtarget) {
24896 SDValue Chain = N->getOperand(0);
24897 SDValue Dest = N->getOperand(1);
24898 SDValue EFLAGS = N->getOperand(3);
24899 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24903 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24904 if (Flags.getNode()) {
24905 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24906 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24913 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24914 SelectionDAG &DAG) {
24915 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24916 // optimize away operation when it's from a constant.
24918 // The general transformation is:
24919 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24920 // AND(VECTOR_CMP(x,y), constant2)
24921 // constant2 = UNARYOP(constant)
24923 // Early exit if this isn't a vector operation, the operand of the
24924 // unary operation isn't a bitwise AND, or if the sizes of the operations
24925 // aren't the same.
24926 EVT VT = N->getValueType(0);
24927 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24928 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24929 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24932 // Now check that the other operand of the AND is a constant. We could
24933 // make the transformation for non-constant splats as well, but it's unclear
24934 // that would be a benefit as it would not eliminate any operations, just
24935 // perform one more step in scalar code before moving to the vector unit.
24936 if (BuildVectorSDNode *BV =
24937 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24938 // Bail out if the vector isn't a constant.
24939 if (!BV->isConstant())
24942 // Everything checks out. Build up the new and improved node.
24944 EVT IntVT = BV->getValueType(0);
24945 // Create a new constant of the appropriate type for the transformed
24947 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24948 // The AND node needs bitcasts to/from an integer vector type around it.
24949 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24950 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24951 N->getOperand(0)->getOperand(0), MaskConst);
24952 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24959 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24960 const X86TargetLowering *XTLI) {
24961 // First try to optimize away the conversion entirely when it's
24962 // conditionally from a constant. Vectors only.
24963 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24964 if (Res != SDValue())
24967 // Now move on to more general possibilities.
24968 SDValue Op0 = N->getOperand(0);
24969 EVT InVT = Op0->getValueType(0);
24971 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24972 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24974 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24975 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24976 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24979 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24980 // a 32-bit target where SSE doesn't support i64->FP operations.
24981 if (Op0.getOpcode() == ISD::LOAD) {
24982 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24983 EVT VT = Ld->getValueType(0);
24984 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24985 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24986 !XTLI->getSubtarget()->is64Bit() &&
24988 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24989 Ld->getChain(), Op0, DAG);
24990 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24997 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24998 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24999 X86TargetLowering::DAGCombinerInfo &DCI) {
25000 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25001 // the result is either zero or one (depending on the input carry bit).
25002 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25003 if (X86::isZeroNode(N->getOperand(0)) &&
25004 X86::isZeroNode(N->getOperand(1)) &&
25005 // We don't have a good way to replace an EFLAGS use, so only do this when
25007 SDValue(N, 1).use_empty()) {
25009 EVT VT = N->getValueType(0);
25010 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25011 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25012 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25013 DAG.getConstant(X86::COND_B,MVT::i8),
25015 DAG.getConstant(1, VT));
25016 return DCI.CombineTo(N, Res1, CarryOut);
25022 // fold (add Y, (sete X, 0)) -> adc 0, Y
25023 // (add Y, (setne X, 0)) -> sbb -1, Y
25024 // (sub (sete X, 0), Y) -> sbb 0, Y
25025 // (sub (setne X, 0), Y) -> adc -1, Y
25026 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25029 // Look through ZExts.
25030 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25031 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25034 SDValue SetCC = Ext.getOperand(0);
25035 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25038 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25039 if (CC != X86::COND_E && CC != X86::COND_NE)
25042 SDValue Cmp = SetCC.getOperand(1);
25043 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25044 !X86::isZeroNode(Cmp.getOperand(1)) ||
25045 !Cmp.getOperand(0).getValueType().isInteger())
25048 SDValue CmpOp0 = Cmp.getOperand(0);
25049 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25050 DAG.getConstant(1, CmpOp0.getValueType()));
25052 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25053 if (CC == X86::COND_NE)
25054 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25055 DL, OtherVal.getValueType(), OtherVal,
25056 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25057 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25058 DL, OtherVal.getValueType(), OtherVal,
25059 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25062 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25063 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25064 const X86Subtarget *Subtarget) {
25065 EVT VT = N->getValueType(0);
25066 SDValue Op0 = N->getOperand(0);
25067 SDValue Op1 = N->getOperand(1);
25069 // Try to synthesize horizontal adds from adds of shuffles.
25070 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25071 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25072 isHorizontalBinOp(Op0, Op1, true))
25073 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25075 return OptimizeConditionalInDecrement(N, DAG);
25078 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25079 const X86Subtarget *Subtarget) {
25080 SDValue Op0 = N->getOperand(0);
25081 SDValue Op1 = N->getOperand(1);
25083 // X86 can't encode an immediate LHS of a sub. See if we can push the
25084 // negation into a preceding instruction.
25085 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25086 // If the RHS of the sub is a XOR with one use and a constant, invert the
25087 // immediate. Then add one to the LHS of the sub so we can turn
25088 // X-Y -> X+~Y+1, saving one register.
25089 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25090 isa<ConstantSDNode>(Op1.getOperand(1))) {
25091 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25092 EVT VT = Op0.getValueType();
25093 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25095 DAG.getConstant(~XorC, VT));
25096 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25097 DAG.getConstant(C->getAPIntValue()+1, VT));
25101 // Try to synthesize horizontal adds from adds of shuffles.
25102 EVT VT = N->getValueType(0);
25103 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25104 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25105 isHorizontalBinOp(Op0, Op1, true))
25106 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25108 return OptimizeConditionalInDecrement(N, DAG);
25111 /// performVZEXTCombine - Performs build vector combines
25112 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25113 TargetLowering::DAGCombinerInfo &DCI,
25114 const X86Subtarget *Subtarget) {
25116 MVT VT = N->getSimpleValueType(0);
25117 SDValue Op = N->getOperand(0);
25118 MVT OpVT = Op.getSimpleValueType();
25119 MVT OpEltVT = OpVT.getVectorElementType();
25120 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25122 // (vzext (bitcast (vzext (x)) -> (vzext x)
25124 while (V.getOpcode() == ISD::BITCAST)
25125 V = V.getOperand(0);
25127 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25128 MVT InnerVT = V.getSimpleValueType();
25129 MVT InnerEltVT = InnerVT.getVectorElementType();
25131 // If the element sizes match exactly, we can just do one larger vzext. This
25132 // is always an exact type match as vzext operates on integer types.
25133 if (OpEltVT == InnerEltVT) {
25134 assert(OpVT == InnerVT && "Types must match for vzext!");
25135 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25138 // The only other way we can combine them is if only a single element of the
25139 // inner vzext is used in the input to the outer vzext.
25140 if (InnerEltVT.getSizeInBits() < InputBits)
25143 // In this case, the inner vzext is completely dead because we're going to
25144 // only look at bits inside of the low element. Just do the outer vzext on
25145 // a bitcast of the input to the inner.
25146 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25147 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25150 // Check if we can bypass extracting and re-inserting an element of an input
25151 // vector. Essentialy:
25152 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25153 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25154 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25155 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25156 SDValue ExtractedV = V.getOperand(0);
25157 SDValue OrigV = ExtractedV.getOperand(0);
25158 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25159 if (ExtractIdx->getZExtValue() == 0) {
25160 MVT OrigVT = OrigV.getSimpleValueType();
25161 // Extract a subvector if necessary...
25162 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25163 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25164 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25165 OrigVT.getVectorNumElements() / Ratio);
25166 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25167 DAG.getIntPtrConstant(0));
25169 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25170 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25177 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25178 DAGCombinerInfo &DCI) const {
25179 SelectionDAG &DAG = DCI.DAG;
25180 switch (N->getOpcode()) {
25182 case ISD::EXTRACT_VECTOR_ELT:
25183 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25186 case X86ISD::SHRUNKBLEND:
25187 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25188 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25189 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25190 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25191 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25192 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25195 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25196 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25197 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25198 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25199 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25200 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25201 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25202 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25203 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25205 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25207 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25208 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25209 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25210 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25211 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25212 case ISD::ANY_EXTEND:
25213 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25214 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25215 case ISD::SIGN_EXTEND_INREG:
25216 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25217 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25218 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25219 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25220 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25221 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25222 case X86ISD::SHUFP: // Handle all target specific shuffles
25223 case X86ISD::PALIGNR:
25224 case X86ISD::UNPCKH:
25225 case X86ISD::UNPCKL:
25226 case X86ISD::MOVHLPS:
25227 case X86ISD::MOVLHPS:
25228 case X86ISD::PSHUFB:
25229 case X86ISD::PSHUFD:
25230 case X86ISD::PSHUFHW:
25231 case X86ISD::PSHUFLW:
25232 case X86ISD::MOVSS:
25233 case X86ISD::MOVSD:
25234 case X86ISD::VPERMILPI:
25235 case X86ISD::VPERM2X128:
25236 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25237 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25238 case ISD::INTRINSIC_WO_CHAIN:
25239 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25240 case X86ISD::INSERTPS:
25241 return PerformINSERTPSCombine(N, DAG, Subtarget);
25242 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25248 /// isTypeDesirableForOp - Return true if the target has native support for
25249 /// the specified value type and it is 'desirable' to use the type for the
25250 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25251 /// instruction encodings are longer and some i16 instructions are slow.
25252 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25253 if (!isTypeLegal(VT))
25255 if (VT != MVT::i16)
25262 case ISD::SIGN_EXTEND:
25263 case ISD::ZERO_EXTEND:
25264 case ISD::ANY_EXTEND:
25277 /// IsDesirableToPromoteOp - This method query the target whether it is
25278 /// beneficial for dag combiner to promote the specified node. If true, it
25279 /// should return the desired promotion type by reference.
25280 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25281 EVT VT = Op.getValueType();
25282 if (VT != MVT::i16)
25285 bool Promote = false;
25286 bool Commute = false;
25287 switch (Op.getOpcode()) {
25290 LoadSDNode *LD = cast<LoadSDNode>(Op);
25291 // If the non-extending load has a single use and it's not live out, then it
25292 // might be folded.
25293 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25294 Op.hasOneUse()*/) {
25295 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25296 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25297 // The only case where we'd want to promote LOAD (rather then it being
25298 // promoted as an operand is when it's only use is liveout.
25299 if (UI->getOpcode() != ISD::CopyToReg)
25306 case ISD::SIGN_EXTEND:
25307 case ISD::ZERO_EXTEND:
25308 case ISD::ANY_EXTEND:
25313 SDValue N0 = Op.getOperand(0);
25314 // Look out for (store (shl (load), x)).
25315 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25328 SDValue N0 = Op.getOperand(0);
25329 SDValue N1 = Op.getOperand(1);
25330 if (!Commute && MayFoldLoad(N1))
25332 // Avoid disabling potential load folding opportunities.
25333 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25335 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25345 //===----------------------------------------------------------------------===//
25346 // X86 Inline Assembly Support
25347 //===----------------------------------------------------------------------===//
25350 // Helper to match a string separated by whitespace.
25351 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25352 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25354 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25355 StringRef piece(*args[i]);
25356 if (!s.startswith(piece)) // Check if the piece matches.
25359 s = s.substr(piece.size());
25360 StringRef::size_type pos = s.find_first_not_of(" \t");
25361 if (pos == 0) // We matched a prefix.
25369 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25372 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25374 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25375 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25376 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25377 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25379 if (AsmPieces.size() == 3)
25381 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25388 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25389 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25391 std::string AsmStr = IA->getAsmString();
25393 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25394 if (!Ty || Ty->getBitWidth() % 16 != 0)
25397 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25398 SmallVector<StringRef, 4> AsmPieces;
25399 SplitString(AsmStr, AsmPieces, ";\n");
25401 switch (AsmPieces.size()) {
25402 default: return false;
25404 // FIXME: this should verify that we are targeting a 486 or better. If not,
25405 // we will turn this bswap into something that will be lowered to logical
25406 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25407 // lower so don't worry about this.
25409 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25410 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25411 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25412 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25413 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25414 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25415 // No need to check constraints, nothing other than the equivalent of
25416 // "=r,0" would be valid here.
25417 return IntrinsicLowering::LowerToByteSwap(CI);
25420 // rorw $$8, ${0:w} --> llvm.bswap.i16
25421 if (CI->getType()->isIntegerTy(16) &&
25422 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25423 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25424 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25426 const std::string &ConstraintsStr = IA->getConstraintString();
25427 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25428 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25429 if (clobbersFlagRegisters(AsmPieces))
25430 return IntrinsicLowering::LowerToByteSwap(CI);
25434 if (CI->getType()->isIntegerTy(32) &&
25435 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25436 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25437 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25438 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25440 const std::string &ConstraintsStr = IA->getConstraintString();
25441 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25442 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25443 if (clobbersFlagRegisters(AsmPieces))
25444 return IntrinsicLowering::LowerToByteSwap(CI);
25447 if (CI->getType()->isIntegerTy(64)) {
25448 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25449 if (Constraints.size() >= 2 &&
25450 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25451 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25452 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25453 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25454 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25455 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25456 return IntrinsicLowering::LowerToByteSwap(CI);
25464 /// getConstraintType - Given a constraint letter, return the type of
25465 /// constraint it is for this target.
25466 X86TargetLowering::ConstraintType
25467 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25468 if (Constraint.size() == 1) {
25469 switch (Constraint[0]) {
25480 return C_RegisterClass;
25504 return TargetLowering::getConstraintType(Constraint);
25507 /// Examine constraint type and operand type and determine a weight value.
25508 /// This object must already have been set up with the operand type
25509 /// and the current alternative constraint selected.
25510 TargetLowering::ConstraintWeight
25511 X86TargetLowering::getSingleConstraintMatchWeight(
25512 AsmOperandInfo &info, const char *constraint) const {
25513 ConstraintWeight weight = CW_Invalid;
25514 Value *CallOperandVal = info.CallOperandVal;
25515 // If we don't have a value, we can't do a match,
25516 // but allow it at the lowest weight.
25517 if (!CallOperandVal)
25519 Type *type = CallOperandVal->getType();
25520 // Look at the constraint type.
25521 switch (*constraint) {
25523 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25534 if (CallOperandVal->getType()->isIntegerTy())
25535 weight = CW_SpecificReg;
25540 if (type->isFloatingPointTy())
25541 weight = CW_SpecificReg;
25544 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25545 weight = CW_SpecificReg;
25549 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25550 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25551 weight = CW_Register;
25554 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25555 if (C->getZExtValue() <= 31)
25556 weight = CW_Constant;
25560 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25561 if (C->getZExtValue() <= 63)
25562 weight = CW_Constant;
25566 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25567 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25568 weight = CW_Constant;
25572 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25573 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25574 weight = CW_Constant;
25578 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25579 if (C->getZExtValue() <= 3)
25580 weight = CW_Constant;
25584 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25585 if (C->getZExtValue() <= 0xff)
25586 weight = CW_Constant;
25591 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25592 weight = CW_Constant;
25596 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25597 if ((C->getSExtValue() >= -0x80000000LL) &&
25598 (C->getSExtValue() <= 0x7fffffffLL))
25599 weight = CW_Constant;
25603 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25604 if (C->getZExtValue() <= 0xffffffff)
25605 weight = CW_Constant;
25612 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25613 /// with another that has more specific requirements based on the type of the
25614 /// corresponding operand.
25615 const char *X86TargetLowering::
25616 LowerXConstraint(EVT ConstraintVT) const {
25617 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25618 // 'f' like normal targets.
25619 if (ConstraintVT.isFloatingPoint()) {
25620 if (Subtarget->hasSSE2())
25622 if (Subtarget->hasSSE1())
25626 return TargetLowering::LowerXConstraint(ConstraintVT);
25629 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25630 /// vector. If it is invalid, don't add anything to Ops.
25631 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25632 std::string &Constraint,
25633 std::vector<SDValue>&Ops,
25634 SelectionDAG &DAG) const {
25637 // Only support length 1 constraints for now.
25638 if (Constraint.length() > 1) return;
25640 char ConstraintLetter = Constraint[0];
25641 switch (ConstraintLetter) {
25644 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25645 if (C->getZExtValue() <= 31) {
25646 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25652 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25653 if (C->getZExtValue() <= 63) {
25654 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25660 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25661 if (isInt<8>(C->getSExtValue())) {
25662 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25668 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25669 if (C->getZExtValue() <= 255) {
25670 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25676 // 32-bit signed value
25677 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25678 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25679 C->getSExtValue())) {
25680 // Widen to 64 bits here to get it sign extended.
25681 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25684 // FIXME gcc accepts some relocatable values here too, but only in certain
25685 // memory models; it's complicated.
25690 // 32-bit unsigned value
25691 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25692 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25693 C->getZExtValue())) {
25694 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25698 // FIXME gcc accepts some relocatable values here too, but only in certain
25699 // memory models; it's complicated.
25703 // Literal immediates are always ok.
25704 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25705 // Widen to 64 bits here to get it sign extended.
25706 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25710 // In any sort of PIC mode addresses need to be computed at runtime by
25711 // adding in a register or some sort of table lookup. These can't
25712 // be used as immediates.
25713 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25716 // If we are in non-pic codegen mode, we allow the address of a global (with
25717 // an optional displacement) to be used with 'i'.
25718 GlobalAddressSDNode *GA = nullptr;
25719 int64_t Offset = 0;
25721 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25723 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25724 Offset += GA->getOffset();
25726 } else if (Op.getOpcode() == ISD::ADD) {
25727 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25728 Offset += C->getZExtValue();
25729 Op = Op.getOperand(0);
25732 } else if (Op.getOpcode() == ISD::SUB) {
25733 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25734 Offset += -C->getZExtValue();
25735 Op = Op.getOperand(0);
25740 // Otherwise, this isn't something we can handle, reject it.
25744 const GlobalValue *GV = GA->getGlobal();
25745 // If we require an extra load to get this address, as in PIC mode, we
25746 // can't accept it.
25747 if (isGlobalStubReference(
25748 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25751 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25752 GA->getValueType(0), Offset);
25757 if (Result.getNode()) {
25758 Ops.push_back(Result);
25761 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25764 std::pair<unsigned, const TargetRegisterClass*>
25765 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25767 // First, see if this is a constraint that directly corresponds to an LLVM
25769 if (Constraint.size() == 1) {
25770 // GCC Constraint Letters
25771 switch (Constraint[0]) {
25773 // TODO: Slight differences here in allocation order and leaving
25774 // RIP in the class. Do they matter any more here than they do
25775 // in the normal allocation?
25776 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25777 if (Subtarget->is64Bit()) {
25778 if (VT == MVT::i32 || VT == MVT::f32)
25779 return std::make_pair(0U, &X86::GR32RegClass);
25780 if (VT == MVT::i16)
25781 return std::make_pair(0U, &X86::GR16RegClass);
25782 if (VT == MVT::i8 || VT == MVT::i1)
25783 return std::make_pair(0U, &X86::GR8RegClass);
25784 if (VT == MVT::i64 || VT == MVT::f64)
25785 return std::make_pair(0U, &X86::GR64RegClass);
25788 // 32-bit fallthrough
25789 case 'Q': // Q_REGS
25790 if (VT == MVT::i32 || VT == MVT::f32)
25791 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25792 if (VT == MVT::i16)
25793 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25794 if (VT == MVT::i8 || VT == MVT::i1)
25795 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25796 if (VT == MVT::i64)
25797 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25799 case 'r': // GENERAL_REGS
25800 case 'l': // INDEX_REGS
25801 if (VT == MVT::i8 || VT == MVT::i1)
25802 return std::make_pair(0U, &X86::GR8RegClass);
25803 if (VT == MVT::i16)
25804 return std::make_pair(0U, &X86::GR16RegClass);
25805 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25806 return std::make_pair(0U, &X86::GR32RegClass);
25807 return std::make_pair(0U, &X86::GR64RegClass);
25808 case 'R': // LEGACY_REGS
25809 if (VT == MVT::i8 || VT == MVT::i1)
25810 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25811 if (VT == MVT::i16)
25812 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25813 if (VT == MVT::i32 || !Subtarget->is64Bit())
25814 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25815 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25816 case 'f': // FP Stack registers.
25817 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25818 // value to the correct fpstack register class.
25819 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25820 return std::make_pair(0U, &X86::RFP32RegClass);
25821 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25822 return std::make_pair(0U, &X86::RFP64RegClass);
25823 return std::make_pair(0U, &X86::RFP80RegClass);
25824 case 'y': // MMX_REGS if MMX allowed.
25825 if (!Subtarget->hasMMX()) break;
25826 return std::make_pair(0U, &X86::VR64RegClass);
25827 case 'Y': // SSE_REGS if SSE2 allowed
25828 if (!Subtarget->hasSSE2()) break;
25830 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25831 if (!Subtarget->hasSSE1()) break;
25833 switch (VT.SimpleTy) {
25835 // Scalar SSE types.
25838 return std::make_pair(0U, &X86::FR32RegClass);
25841 return std::make_pair(0U, &X86::FR64RegClass);
25849 return std::make_pair(0U, &X86::VR128RegClass);
25857 return std::make_pair(0U, &X86::VR256RegClass);
25862 return std::make_pair(0U, &X86::VR512RegClass);
25868 // Use the default implementation in TargetLowering to convert the register
25869 // constraint into a member of a register class.
25870 std::pair<unsigned, const TargetRegisterClass*> Res;
25871 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25873 // Not found as a standard register?
25875 // Map st(0) -> st(7) -> ST0
25876 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25877 tolower(Constraint[1]) == 's' &&
25878 tolower(Constraint[2]) == 't' &&
25879 Constraint[3] == '(' &&
25880 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25881 Constraint[5] == ')' &&
25882 Constraint[6] == '}') {
25884 Res.first = X86::FP0+Constraint[4]-'0';
25885 Res.second = &X86::RFP80RegClass;
25889 // GCC allows "st(0)" to be called just plain "st".
25890 if (StringRef("{st}").equals_lower(Constraint)) {
25891 Res.first = X86::FP0;
25892 Res.second = &X86::RFP80RegClass;
25897 if (StringRef("{flags}").equals_lower(Constraint)) {
25898 Res.first = X86::EFLAGS;
25899 Res.second = &X86::CCRRegClass;
25903 // 'A' means EAX + EDX.
25904 if (Constraint == "A") {
25905 Res.first = X86::EAX;
25906 Res.second = &X86::GR32_ADRegClass;
25912 // Otherwise, check to see if this is a register class of the wrong value
25913 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25914 // turn into {ax},{dx}.
25915 if (Res.second->hasType(VT))
25916 return Res; // Correct type already, nothing to do.
25918 // All of the single-register GCC register classes map their values onto
25919 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25920 // really want an 8-bit or 32-bit register, map to the appropriate register
25921 // class and return the appropriate register.
25922 if (Res.second == &X86::GR16RegClass) {
25923 if (VT == MVT::i8 || VT == MVT::i1) {
25924 unsigned DestReg = 0;
25925 switch (Res.first) {
25927 case X86::AX: DestReg = X86::AL; break;
25928 case X86::DX: DestReg = X86::DL; break;
25929 case X86::CX: DestReg = X86::CL; break;
25930 case X86::BX: DestReg = X86::BL; break;
25933 Res.first = DestReg;
25934 Res.second = &X86::GR8RegClass;
25936 } else if (VT == MVT::i32 || VT == MVT::f32) {
25937 unsigned DestReg = 0;
25938 switch (Res.first) {
25940 case X86::AX: DestReg = X86::EAX; break;
25941 case X86::DX: DestReg = X86::EDX; break;
25942 case X86::CX: DestReg = X86::ECX; break;
25943 case X86::BX: DestReg = X86::EBX; break;
25944 case X86::SI: DestReg = X86::ESI; break;
25945 case X86::DI: DestReg = X86::EDI; break;
25946 case X86::BP: DestReg = X86::EBP; break;
25947 case X86::SP: DestReg = X86::ESP; break;
25950 Res.first = DestReg;
25951 Res.second = &X86::GR32RegClass;
25953 } else if (VT == MVT::i64 || VT == MVT::f64) {
25954 unsigned DestReg = 0;
25955 switch (Res.first) {
25957 case X86::AX: DestReg = X86::RAX; break;
25958 case X86::DX: DestReg = X86::RDX; break;
25959 case X86::CX: DestReg = X86::RCX; break;
25960 case X86::BX: DestReg = X86::RBX; break;
25961 case X86::SI: DestReg = X86::RSI; break;
25962 case X86::DI: DestReg = X86::RDI; break;
25963 case X86::BP: DestReg = X86::RBP; break;
25964 case X86::SP: DestReg = X86::RSP; break;
25967 Res.first = DestReg;
25968 Res.second = &X86::GR64RegClass;
25971 } else if (Res.second == &X86::FR32RegClass ||
25972 Res.second == &X86::FR64RegClass ||
25973 Res.second == &X86::VR128RegClass ||
25974 Res.second == &X86::VR256RegClass ||
25975 Res.second == &X86::FR32XRegClass ||
25976 Res.second == &X86::FR64XRegClass ||
25977 Res.second == &X86::VR128XRegClass ||
25978 Res.second == &X86::VR256XRegClass ||
25979 Res.second == &X86::VR512RegClass) {
25980 // Handle references to XMM physical registers that got mapped into the
25981 // wrong class. This can happen with constraints like {xmm0} where the
25982 // target independent register mapper will just pick the first match it can
25983 // find, ignoring the required type.
25985 if (VT == MVT::f32 || VT == MVT::i32)
25986 Res.second = &X86::FR32RegClass;
25987 else if (VT == MVT::f64 || VT == MVT::i64)
25988 Res.second = &X86::FR64RegClass;
25989 else if (X86::VR128RegClass.hasType(VT))
25990 Res.second = &X86::VR128RegClass;
25991 else if (X86::VR256RegClass.hasType(VT))
25992 Res.second = &X86::VR256RegClass;
25993 else if (X86::VR512RegClass.hasType(VT))
25994 Res.second = &X86::VR512RegClass;
26000 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26002 // Scaling factors are not free at all.
26003 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26004 // will take 2 allocations in the out of order engine instead of 1
26005 // for plain addressing mode, i.e. inst (reg1).
26007 // vaddps (%rsi,%drx), %ymm0, %ymm1
26008 // Requires two allocations (one for the load, one for the computation)
26010 // vaddps (%rsi), %ymm0, %ymm1
26011 // Requires just 1 allocation, i.e., freeing allocations for other operations
26012 // and having less micro operations to execute.
26014 // For some X86 architectures, this is even worse because for instance for
26015 // stores, the complex addressing mode forces the instruction to use the
26016 // "load" ports instead of the dedicated "store" port.
26017 // E.g., on Haswell:
26018 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26019 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26020 if (isLegalAddressingMode(AM, Ty))
26021 // Scale represents reg2 * scale, thus account for 1
26022 // as soon as we use a second register.
26023 return AM.Scale != 0;
26027 bool X86TargetLowering::isTargetFTOL() const {
26028 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();