1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit bounday. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
171 unsigned IdxVal, SelectionDAG &DAG,
173 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
174 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
177 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
178 unsigned IdxVal, SelectionDAG &DAG,
180 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
181 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
184 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
185 /// instructions. This is used because creating CONCAT_VECTOR nodes of
186 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
187 /// large BUILD_VECTORS.
188 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
189 unsigned NumElems, SelectionDAG &DAG,
191 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
192 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
195 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
196 unsigned NumElems, SelectionDAG &DAG,
198 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
199 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
202 // FIXME: This should stop caching the target machine as soon as
203 // we can remove resetOperationActions et al.
204 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
205 : TargetLowering(TM) {
206 Subtarget = &TM.getSubtarget<X86Subtarget>();
207 X86ScalarSSEf64 = Subtarget->hasSSE2();
208 X86ScalarSSEf32 = Subtarget->hasSSE1();
209 TD = getDataLayout();
211 resetOperationActions();
214 void X86TargetLowering::resetOperationActions() {
215 const TargetMachine &TM = getTargetMachine();
216 static bool FirstTimeThrough = true;
218 // If none of the target options have changed, then we don't need to reset the
219 // operation actions.
220 if (!FirstTimeThrough && TO == TM.Options) return;
222 if (!FirstTimeThrough) {
223 // Reinitialize the actions.
225 FirstTimeThrough = false;
230 // Set up the TargetLowering object.
231 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
233 // X86 is weird, it always uses i8 for shift amounts and setcc results.
234 setBooleanContents(ZeroOrOneBooleanContent);
235 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
236 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
238 // For 64-bit since we have so many registers use the ILP scheduler, for
239 // 32-bit code use the register pressure specific scheduling.
240 // For Atom, always use ILP scheduling.
241 if (Subtarget->isAtom())
242 setSchedulingPreference(Sched::ILP);
243 else if (Subtarget->is64Bit())
244 setSchedulingPreference(Sched::ILP);
246 setSchedulingPreference(Sched::RegPressure);
247 const X86RegisterInfo *RegInfo =
248 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
249 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
251 // Bypass expensive divides on Atom when compiling with O2
252 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
253 addBypassSlowDiv(32, 8);
254 if (Subtarget->is64Bit())
255 addBypassSlowDiv(64, 16);
258 if (Subtarget->isTargetKnownWindowsMSVC()) {
259 // Setup Windows compiler runtime calls.
260 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
261 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
262 setLibcallName(RTLIB::SREM_I64, "_allrem");
263 setLibcallName(RTLIB::UREM_I64, "_aullrem");
264 setLibcallName(RTLIB::MUL_I64, "_allmul");
265 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
266 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
268 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
269 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
271 // The _ftol2 runtime function has an unusual calling conv, which
272 // is modeled by a special pseudo-instruction.
273 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
274 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
275 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
276 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
279 if (Subtarget->isTargetDarwin()) {
280 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
281 setUseUnderscoreSetJmp(false);
282 setUseUnderscoreLongJmp(false);
283 } else if (Subtarget->isTargetWindowsGNU()) {
284 // MS runtime is weird: it exports _setjmp, but longjmp!
285 setUseUnderscoreSetJmp(true);
286 setUseUnderscoreLongJmp(false);
288 setUseUnderscoreSetJmp(true);
289 setUseUnderscoreLongJmp(true);
292 // Set up the register classes.
293 addRegisterClass(MVT::i8, &X86::GR8RegClass);
294 addRegisterClass(MVT::i16, &X86::GR16RegClass);
295 addRegisterClass(MVT::i32, &X86::GR32RegClass);
296 if (Subtarget->is64Bit())
297 addRegisterClass(MVT::i64, &X86::GR64RegClass);
299 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
301 // We don't accept any truncstore of integer registers.
302 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
303 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
304 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
305 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
306 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
307 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
309 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
311 // SETOEQ and SETUNE require checking two conditions.
312 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
313 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
314 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
315 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
316 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
317 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
319 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
321 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
322 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
325 if (Subtarget->is64Bit()) {
326 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 } else if (!TM.Options.UseSoftFloat) {
329 // We have an algorithm for SSE2->double, and we turn this into a
330 // 64-bit FILD followed by conditional FADD for other targets.
331 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
332 // We have an algorithm for SSE2, and we turn this into a 64-bit
333 // FILD for other targets.
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
337 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
339 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
342 if (!TM.Options.UseSoftFloat) {
343 // SSE has no i16 to fp conversion, only i32
344 if (X86ScalarSSEf32) {
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
346 // f32 and f64 cases are Legal, f80 case is not
347 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
357 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
358 // are Legal, f80 is custom lowered.
359 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
360 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
362 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
364 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
367 if (X86ScalarSSEf32) {
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
369 // f32 and f64 cases are Legal, f80 case is not
370 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
376 // Handle FP_TO_UINT by promoting the destination to a larger signed
378 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
379 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
382 if (Subtarget->is64Bit()) {
383 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
384 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
385 } else if (!TM.Options.UseSoftFloat) {
386 // Since AVX is a superset of SSE3, only check for SSE here.
387 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
388 // Expand FP_TO_UINT into a select.
389 // FIXME: We would like to use a Custom expander here eventually to do
390 // the optimal thing for SSE vs. the default expansion in the legalizer.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
393 // With SSE3 we can use fisttpll to convert to a signed i64; without
394 // SSE, we're stuck with a fistpll.
395 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
398 if (isTargetFTOL()) {
399 // Use the _ftol2 runtime function, which has a pseudo-instruction
400 // to handle its weird calling convention.
401 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
404 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
405 if (!X86ScalarSSEf64) {
406 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
407 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
408 if (Subtarget->is64Bit()) {
409 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
410 // Without SSE, i64->f64 goes through memory.
411 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
415 // Scalar integer divide and remainder are lowered to use operations that
416 // produce two results, to match the available instructions. This exposes
417 // the two-result form to trivial CSE, which is able to combine x/y and x%y
418 // into a single instruction.
420 // Scalar integer multiply-high is also lowered to use two-result
421 // operations, to match the available instructions. However, plain multiply
422 // (low) operations are left as Legal, as there are single-result
423 // instructions for this in x86. Using the two-result multiply instructions
424 // when both high and low results are needed must be arranged by dagcombine.
425 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
427 setOperationAction(ISD::MULHS, VT, Expand);
428 setOperationAction(ISD::MULHU, VT, Expand);
429 setOperationAction(ISD::SDIV, VT, Expand);
430 setOperationAction(ISD::UDIV, VT, Expand);
431 setOperationAction(ISD::SREM, VT, Expand);
432 setOperationAction(ISD::UREM, VT, Expand);
434 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
435 setOperationAction(ISD::ADDC, VT, Custom);
436 setOperationAction(ISD::ADDE, VT, Custom);
437 setOperationAction(ISD::SUBC, VT, Custom);
438 setOperationAction(ISD::SUBE, VT, Custom);
441 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
442 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
443 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
444 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
445 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
446 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
447 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
448 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
449 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
456 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
457 if (Subtarget->is64Bit())
458 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
461 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
462 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
463 setOperationAction(ISD::FREM , MVT::f32 , Expand);
464 setOperationAction(ISD::FREM , MVT::f64 , Expand);
465 setOperationAction(ISD::FREM , MVT::f80 , Expand);
466 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
468 // Promote the i8 variants and force them on up to i32 which has a shorter
470 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
471 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
473 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
474 if (Subtarget->hasBMI()) {
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
476 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
477 if (Subtarget->is64Bit())
478 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
480 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
481 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
482 if (Subtarget->is64Bit())
483 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
486 if (Subtarget->hasLZCNT()) {
487 // When promoting the i8 variants, force them to i32 for a shorter
489 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
490 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
492 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
494 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
495 if (Subtarget->is64Bit())
496 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
498 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
499 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
500 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
504 if (Subtarget->is64Bit()) {
505 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
510 // Special handling for half-precision floating point conversions.
511 // If we don't have F16C support, then lower half float conversions
512 // into library calls.
513 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
514 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
515 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
518 // There's never any support for operations beyond MVT::f32.
519 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
520 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
521 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
522 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
524 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
525 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
527 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
529 if (Subtarget->hasPOPCNT()) {
530 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
532 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
533 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
534 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
535 if (Subtarget->is64Bit())
536 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
539 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
541 if (!Subtarget->hasMOVBE())
542 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
544 // These should be promoted to a larger select which is supported.
545 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
546 // X86 wants to expand cmov itself.
547 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
548 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
549 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
550 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
552 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
553 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
555 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
556 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
558 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
559 if (Subtarget->is64Bit()) {
560 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
563 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
564 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
565 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
566 // support continuation, user-level threading, and etc.. As a result, no
567 // other SjLj exception interfaces are implemented and please don't build
568 // your own exception handling based on them.
569 // LLVM/Clang supports zero-cost DWARF exception handling.
570 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
571 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
574 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
575 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
576 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
577 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
578 if (Subtarget->is64Bit())
579 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
580 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
581 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
582 if (Subtarget->is64Bit()) {
583 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
584 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
585 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
586 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
587 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
589 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
590 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
591 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
592 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
593 if (Subtarget->is64Bit()) {
594 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
595 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
596 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
599 if (Subtarget->hasSSE1())
600 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
602 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
604 // Expand certain atomics
605 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
607 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
608 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
609 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
612 if (Subtarget->hasCmpxchg16b()) {
613 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
616 // FIXME - use subtarget debug flags
617 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
618 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
619 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
622 if (Subtarget->is64Bit()) {
623 setExceptionPointerRegister(X86::RAX);
624 setExceptionSelectorRegister(X86::RDX);
626 setExceptionPointerRegister(X86::EAX);
627 setExceptionSelectorRegister(X86::EDX);
629 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
630 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
632 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
633 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
635 setOperationAction(ISD::TRAP, MVT::Other, Legal);
636 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
638 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
639 setOperationAction(ISD::VASTART , MVT::Other, Custom);
640 setOperationAction(ISD::VAEND , MVT::Other, Expand);
641 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
642 // TargetInfo::X86_64ABIBuiltinVaList
643 setOperationAction(ISD::VAARG , MVT::Other, Custom);
644 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
646 // TargetInfo::CharPtrBuiltinVaList
647 setOperationAction(ISD::VAARG , MVT::Other, Expand);
648 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
651 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
652 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
654 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
656 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
657 // f32 and f64 use SSE.
658 // Set up the FP register classes.
659 addRegisterClass(MVT::f32, &X86::FR32RegClass);
660 addRegisterClass(MVT::f64, &X86::FR64RegClass);
662 // Use ANDPD to simulate FABS.
663 setOperationAction(ISD::FABS , MVT::f64, Custom);
664 setOperationAction(ISD::FABS , MVT::f32, Custom);
666 // Use XORP to simulate FNEG.
667 setOperationAction(ISD::FNEG , MVT::f64, Custom);
668 setOperationAction(ISD::FNEG , MVT::f32, Custom);
670 // Use ANDPD and ORPD to simulate FCOPYSIGN.
671 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
672 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
674 // Lower this to FGETSIGNx86 plus an AND.
675 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
676 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
678 // We don't support sin/cos/fmod
679 setOperationAction(ISD::FSIN , MVT::f64, Expand);
680 setOperationAction(ISD::FCOS , MVT::f64, Expand);
681 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
682 setOperationAction(ISD::FSIN , MVT::f32, Expand);
683 setOperationAction(ISD::FCOS , MVT::f32, Expand);
684 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
686 // Expand FP immediates into loads from the stack, except for the special
688 addLegalFPImmediate(APFloat(+0.0)); // xorpd
689 addLegalFPImmediate(APFloat(+0.0f)); // xorps
690 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
691 // Use SSE for f32, x87 for f64.
692 // Set up the FP register classes.
693 addRegisterClass(MVT::f32, &X86::FR32RegClass);
694 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
696 // Use ANDPS to simulate FABS.
697 setOperationAction(ISD::FABS , MVT::f32, Custom);
699 // Use XORP to simulate FNEG.
700 setOperationAction(ISD::FNEG , MVT::f32, Custom);
702 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
704 // Use ANDPS and ORPS to simulate FCOPYSIGN.
705 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
706 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
708 // We don't support sin/cos/fmod
709 setOperationAction(ISD::FSIN , MVT::f32, Expand);
710 setOperationAction(ISD::FCOS , MVT::f32, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
713 // Special cases we handle for FP constants.
714 addLegalFPImmediate(APFloat(+0.0f)); // xorps
715 addLegalFPImmediate(APFloat(+0.0)); // FLD0
716 addLegalFPImmediate(APFloat(+1.0)); // FLD1
717 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
718 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
720 if (!TM.Options.UnsafeFPMath) {
721 setOperationAction(ISD::FSIN , MVT::f64, Expand);
722 setOperationAction(ISD::FCOS , MVT::f64, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
725 } else if (!TM.Options.UseSoftFloat) {
726 // f32 and f64 in x87.
727 // Set up the FP register classes.
728 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
729 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
731 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
732 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
733 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
734 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
736 if (!TM.Options.UnsafeFPMath) {
737 setOperationAction(ISD::FSIN , MVT::f64, Expand);
738 setOperationAction(ISD::FSIN , MVT::f32, Expand);
739 setOperationAction(ISD::FCOS , MVT::f64, Expand);
740 setOperationAction(ISD::FCOS , MVT::f32, Expand);
741 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
742 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
744 addLegalFPImmediate(APFloat(+0.0)); // FLD0
745 addLegalFPImmediate(APFloat(+1.0)); // FLD1
746 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
747 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
748 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
749 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
750 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
751 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
754 // We don't support FMA.
755 setOperationAction(ISD::FMA, MVT::f64, Expand);
756 setOperationAction(ISD::FMA, MVT::f32, Expand);
758 // Long double always uses X87.
759 if (!TM.Options.UseSoftFloat) {
760 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
761 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
762 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
764 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
765 addLegalFPImmediate(TmpFlt); // FLD0
767 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
770 APFloat TmpFlt2(+1.0);
771 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
773 addLegalFPImmediate(TmpFlt2); // FLD1
774 TmpFlt2.changeSign();
775 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
778 if (!TM.Options.UnsafeFPMath) {
779 setOperationAction(ISD::FSIN , MVT::f80, Expand);
780 setOperationAction(ISD::FCOS , MVT::f80, Expand);
781 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
784 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
785 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
786 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
787 setOperationAction(ISD::FRINT, MVT::f80, Expand);
788 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
789 setOperationAction(ISD::FMA, MVT::f80, Expand);
792 // Always use a library call for pow.
793 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
794 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
795 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
797 setOperationAction(ISD::FLOG, MVT::f80, Expand);
798 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
799 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
800 setOperationAction(ISD::FEXP, MVT::f80, Expand);
801 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
802 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
803 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
805 // First set operation action for all vector types to either promote
806 // (for widening) or expand (for scalarization). Then we will selectively
807 // turn on ones that can be effectively codegen'd.
808 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
809 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
810 MVT VT = (MVT::SimpleValueType)i;
811 setOperationAction(ISD::ADD , VT, Expand);
812 setOperationAction(ISD::SUB , VT, Expand);
813 setOperationAction(ISD::FADD, VT, Expand);
814 setOperationAction(ISD::FNEG, VT, Expand);
815 setOperationAction(ISD::FSUB, VT, Expand);
816 setOperationAction(ISD::MUL , VT, Expand);
817 setOperationAction(ISD::FMUL, VT, Expand);
818 setOperationAction(ISD::SDIV, VT, Expand);
819 setOperationAction(ISD::UDIV, VT, Expand);
820 setOperationAction(ISD::FDIV, VT, Expand);
821 setOperationAction(ISD::SREM, VT, Expand);
822 setOperationAction(ISD::UREM, VT, Expand);
823 setOperationAction(ISD::LOAD, VT, Expand);
824 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
825 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
826 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
827 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
828 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
829 setOperationAction(ISD::FABS, VT, Expand);
830 setOperationAction(ISD::FSIN, VT, Expand);
831 setOperationAction(ISD::FSINCOS, VT, Expand);
832 setOperationAction(ISD::FCOS, VT, Expand);
833 setOperationAction(ISD::FSINCOS, VT, Expand);
834 setOperationAction(ISD::FREM, VT, Expand);
835 setOperationAction(ISD::FMA, VT, Expand);
836 setOperationAction(ISD::FPOWI, VT, Expand);
837 setOperationAction(ISD::FSQRT, VT, Expand);
838 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
839 setOperationAction(ISD::FFLOOR, VT, Expand);
840 setOperationAction(ISD::FCEIL, VT, Expand);
841 setOperationAction(ISD::FTRUNC, VT, Expand);
842 setOperationAction(ISD::FRINT, VT, Expand);
843 setOperationAction(ISD::FNEARBYINT, VT, Expand);
844 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
845 setOperationAction(ISD::MULHS, VT, Expand);
846 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
847 setOperationAction(ISD::MULHU, VT, Expand);
848 setOperationAction(ISD::SDIVREM, VT, Expand);
849 setOperationAction(ISD::UDIVREM, VT, Expand);
850 setOperationAction(ISD::FPOW, VT, Expand);
851 setOperationAction(ISD::CTPOP, VT, Expand);
852 setOperationAction(ISD::CTTZ, VT, Expand);
853 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
854 setOperationAction(ISD::CTLZ, VT, Expand);
855 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
856 setOperationAction(ISD::SHL, VT, Expand);
857 setOperationAction(ISD::SRA, VT, Expand);
858 setOperationAction(ISD::SRL, VT, Expand);
859 setOperationAction(ISD::ROTL, VT, Expand);
860 setOperationAction(ISD::ROTR, VT, Expand);
861 setOperationAction(ISD::BSWAP, VT, Expand);
862 setOperationAction(ISD::SETCC, VT, Expand);
863 setOperationAction(ISD::FLOG, VT, Expand);
864 setOperationAction(ISD::FLOG2, VT, Expand);
865 setOperationAction(ISD::FLOG10, VT, Expand);
866 setOperationAction(ISD::FEXP, VT, Expand);
867 setOperationAction(ISD::FEXP2, VT, Expand);
868 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
869 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
870 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
871 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
872 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
873 setOperationAction(ISD::TRUNCATE, VT, Expand);
874 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
875 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
876 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
877 setOperationAction(ISD::VSELECT, VT, Expand);
878 setOperationAction(ISD::SELECT_CC, VT, Expand);
879 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
880 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
881 setTruncStoreAction(VT,
882 (MVT::SimpleValueType)InnerVT, Expand);
883 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
884 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
886 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
887 // we have to deal with them whether we ask for Expansion or not. Setting
888 // Expand causes its own optimisation problems though, so leave them legal.
889 if (VT.getVectorElementType() == MVT::i1)
890 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
893 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
894 // with -msoft-float, disable use of MMX as well.
895 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
896 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
897 // No operations on x86mmx supported, everything uses intrinsics.
900 // MMX-sized vectors (other than x86mmx) are expected to be expanded
901 // into smaller operations.
902 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
903 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
904 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
905 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
906 setOperationAction(ISD::AND, MVT::v8i8, Expand);
907 setOperationAction(ISD::AND, MVT::v4i16, Expand);
908 setOperationAction(ISD::AND, MVT::v2i32, Expand);
909 setOperationAction(ISD::AND, MVT::v1i64, Expand);
910 setOperationAction(ISD::OR, MVT::v8i8, Expand);
911 setOperationAction(ISD::OR, MVT::v4i16, Expand);
912 setOperationAction(ISD::OR, MVT::v2i32, Expand);
913 setOperationAction(ISD::OR, MVT::v1i64, Expand);
914 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
915 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
916 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
917 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
918 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
921 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
922 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
923 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
924 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
925 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
926 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
927 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
928 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
929 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
930 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
932 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
933 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
935 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
936 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
937 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
938 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
939 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
940 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
941 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
942 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
943 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
944 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
945 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
946 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
947 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
950 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
951 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
953 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
954 // registers cannot be used even for integer operations.
955 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
956 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
957 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
958 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
960 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
961 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
962 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
963 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
964 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
965 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
966 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
967 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
968 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
969 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
970 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
971 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
972 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
973 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
974 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
975 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
976 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
977 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
978 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
979 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
980 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
981 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
983 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
984 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
985 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
986 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
988 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
989 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
994 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
995 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
996 MVT VT = (MVT::SimpleValueType)i;
997 // Do not attempt to custom lower non-power-of-2 vectors
998 if (!isPowerOf2_32(VT.getVectorNumElements()))
1000 // Do not attempt to custom lower non-128-bit vectors
1001 if (!VT.is128BitVector())
1003 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1004 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1008 // We support custom legalizing of sext and anyext loads for specific
1009 // memory vector types which we can load as a scalar (or sequence of
1010 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1011 // loads these must work with a single scalar load.
1012 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1013 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1014 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1015 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1017 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1018 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1022 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1023 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1024 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1025 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1026 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1027 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1029 if (Subtarget->is64Bit()) {
1030 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1031 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1034 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1035 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1036 MVT VT = (MVT::SimpleValueType)i;
1038 // Do not attempt to promote non-128-bit vectors
1039 if (!VT.is128BitVector())
1042 setOperationAction(ISD::AND, VT, Promote);
1043 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1044 setOperationAction(ISD::OR, VT, Promote);
1045 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1046 setOperationAction(ISD::XOR, VT, Promote);
1047 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1048 setOperationAction(ISD::LOAD, VT, Promote);
1049 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1050 setOperationAction(ISD::SELECT, VT, Promote);
1051 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1054 // Custom lower v2i64 and v2f64 selects.
1055 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1056 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1057 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1058 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1060 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1061 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1063 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1064 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1065 // As there is no 64-bit GPR available, we need build a special custom
1066 // sequence to convert from v2i32 to v2f32.
1067 if (!Subtarget->is64Bit())
1068 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1070 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1071 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1073 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1075 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1076 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1077 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1080 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1081 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1082 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1083 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1084 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1085 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1086 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1087 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1088 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1089 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1090 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1092 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1093 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1094 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1095 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1098 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1099 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1100 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1101 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1103 // FIXME: Do we need to handle scalar-to-vector here?
1104 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1106 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1107 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1108 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1109 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1110 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1111 // There is no BLENDI for byte vectors. We don't need to custom lower
1112 // some vselects for now.
1113 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1115 // SSE41 brings specific instructions for doing vector sign extend even in
1116 // cases where we don't have SRA.
1117 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1118 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1119 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1121 // i8 and i16 vectors are custom because the source register and source
1122 // source memory operand types are not the same width. f32 vectors are
1123 // custom since the immediate controlling the insert encodes additional
1125 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1128 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1130 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1133 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1135 // FIXME: these should be Legal, but that's only for the case where
1136 // the index is constant. For now custom expand to deal with that.
1137 if (Subtarget->is64Bit()) {
1138 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1143 if (Subtarget->hasSSE2()) {
1144 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1145 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1147 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1148 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1150 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1151 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1153 // In the customized shift lowering, the legal cases in AVX2 will be
1155 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1156 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1158 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1159 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1161 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1164 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1165 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1172 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1173 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1174 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1176 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1187 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1189 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1200 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1202 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1203 // even though v8i16 is a legal type.
1204 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1205 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1206 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1208 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1209 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1210 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1212 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1213 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1215 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1217 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1218 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1220 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1223 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1224 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1226 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1229 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1231 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1233 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1235 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1236 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1237 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1238 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1240 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1241 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1242 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1243 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1244 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1245 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1246 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1247 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1248 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1249 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1250 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1251 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1253 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1254 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1255 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1256 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1257 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1258 setOperationAction(ISD::FMA, MVT::f32, Legal);
1259 setOperationAction(ISD::FMA, MVT::f64, Legal);
1262 if (Subtarget->hasInt256()) {
1263 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1264 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1265 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1266 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1268 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1269 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1270 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1271 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1273 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1274 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1275 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1276 // Don't lower v32i8 because there is no 128-bit byte mul
1278 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1279 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1280 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1281 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1283 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1284 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1286 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1287 // when we have a 256bit-wide blend with immediate.
1288 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1290 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1291 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1292 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1293 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1295 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1296 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1297 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1298 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1300 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1301 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1302 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1303 // Don't lower v32i8 because there is no 128-bit byte mul
1306 // In the customized shift lowering, the legal cases in AVX2 will be
1308 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1309 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1311 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1312 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1314 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1316 // Custom lower several nodes for 256-bit types.
1317 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1318 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1319 MVT VT = (MVT::SimpleValueType)i;
1321 // Extract subvector is special because the value type
1322 // (result) is 128-bit but the source is 256-bit wide.
1323 if (VT.is128BitVector())
1324 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1326 // Do not attempt to custom lower other non-256-bit vectors
1327 if (!VT.is256BitVector())
1330 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1331 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1334 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1335 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1336 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1339 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1340 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1341 MVT VT = (MVT::SimpleValueType)i;
1343 // Do not attempt to promote non-256-bit vectors
1344 if (!VT.is256BitVector())
1347 setOperationAction(ISD::AND, VT, Promote);
1348 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1349 setOperationAction(ISD::OR, VT, Promote);
1350 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1351 setOperationAction(ISD::XOR, VT, Promote);
1352 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1353 setOperationAction(ISD::LOAD, VT, Promote);
1354 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1355 setOperationAction(ISD::SELECT, VT, Promote);
1356 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1360 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1361 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1362 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1363 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1364 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1366 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1367 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1368 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1370 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1371 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1372 setOperationAction(ISD::XOR, MVT::i1, Legal);
1373 setOperationAction(ISD::OR, MVT::i1, Legal);
1374 setOperationAction(ISD::AND, MVT::i1, Legal);
1375 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1376 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1377 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1378 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1379 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1380 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1382 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1383 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1384 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1385 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1386 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1387 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1389 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1390 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1391 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1392 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1393 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1394 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1395 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1398 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1399 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1400 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1401 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1402 if (Subtarget->is64Bit()) {
1403 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1404 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1408 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1409 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1410 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1411 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1412 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1414 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1415 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1417 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1420 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1421 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1423 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1429 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1437 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1444 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1445 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1447 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1449 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1451 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1453 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1455 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1459 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1460 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1462 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1463 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1465 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1467 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1468 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1470 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1471 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1473 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1476 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1477 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1478 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1480 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1481 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1483 if (Subtarget->hasCDI()) {
1484 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1485 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1488 // Custom lower several nodes.
1489 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1490 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1491 MVT VT = (MVT::SimpleValueType)i;
1493 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1494 // Extract subvector is special because the value type
1495 // (result) is 256/128-bit but the source is 512-bit wide.
1496 if (VT.is128BitVector() || VT.is256BitVector())
1497 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1499 if (VT.getVectorElementType() == MVT::i1)
1500 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1502 // Do not attempt to custom lower other non-512-bit vectors
1503 if (!VT.is512BitVector())
1506 if ( EltSize >= 32) {
1507 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1508 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1509 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1510 setOperationAction(ISD::VSELECT, VT, Legal);
1511 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1512 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1513 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1516 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1517 MVT VT = (MVT::SimpleValueType)i;
1519 // Do not attempt to promote non-256-bit vectors
1520 if (!VT.is512BitVector())
1523 setOperationAction(ISD::SELECT, VT, Promote);
1524 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1528 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1529 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1530 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1532 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1533 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1535 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1536 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1537 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1538 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1540 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1541 const MVT VT = (MVT::SimpleValueType)i;
1543 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1545 // Do not attempt to promote non-256-bit vectors
1546 if (!VT.is512BitVector())
1549 if ( EltSize < 32) {
1550 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1551 setOperationAction(ISD::VSELECT, VT, Legal);
1556 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1557 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1558 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1560 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1561 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1562 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1598 if (!Subtarget->is64Bit()) {
1599 // These libcalls are not available in 32-bit.
1600 setLibcallName(RTLIB::SHL_I128, nullptr);
1601 setLibcallName(RTLIB::SRL_I128, nullptr);
1602 setLibcallName(RTLIB::SRA_I128, nullptr);
1605 // Combine sin / cos into one node or libcall if possible.
1606 if (Subtarget->hasSinCos()) {
1607 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1608 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1609 if (Subtarget->isTargetDarwin()) {
1610 // For MacOSX, we don't want to the normal expansion of a libcall to
1611 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1613 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1614 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1618 if (Subtarget->isTargetWin64()) {
1619 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1620 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1621 setOperationAction(ISD::SREM, MVT::i128, Custom);
1622 setOperationAction(ISD::UREM, MVT::i128, Custom);
1623 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1624 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1627 // We have target-specific dag combine patterns for the following nodes:
1628 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1629 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1630 setTargetDAGCombine(ISD::VSELECT);
1631 setTargetDAGCombine(ISD::SELECT);
1632 setTargetDAGCombine(ISD::SHL);
1633 setTargetDAGCombine(ISD::SRA);
1634 setTargetDAGCombine(ISD::SRL);
1635 setTargetDAGCombine(ISD::OR);
1636 setTargetDAGCombine(ISD::AND);
1637 setTargetDAGCombine(ISD::ADD);
1638 setTargetDAGCombine(ISD::FADD);
1639 setTargetDAGCombine(ISD::FSUB);
1640 setTargetDAGCombine(ISD::FMA);
1641 setTargetDAGCombine(ISD::SUB);
1642 setTargetDAGCombine(ISD::LOAD);
1643 setTargetDAGCombine(ISD::STORE);
1644 setTargetDAGCombine(ISD::ZERO_EXTEND);
1645 setTargetDAGCombine(ISD::ANY_EXTEND);
1646 setTargetDAGCombine(ISD::SIGN_EXTEND);
1647 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1648 setTargetDAGCombine(ISD::TRUNCATE);
1649 setTargetDAGCombine(ISD::SINT_TO_FP);
1650 setTargetDAGCombine(ISD::SETCC);
1651 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1652 setTargetDAGCombine(ISD::BUILD_VECTOR);
1653 if (Subtarget->is64Bit())
1654 setTargetDAGCombine(ISD::MUL);
1655 setTargetDAGCombine(ISD::XOR);
1657 computeRegisterProperties();
1659 // On Darwin, -Os means optimize for size without hurting performance,
1660 // do not reduce the limit.
1661 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1662 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1663 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1664 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1665 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1666 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1667 setPrefLoopAlignment(4); // 2^4 bytes.
1669 // Predictable cmov don't hurt on atom because it's in-order.
1670 PredictableSelectIsExpensive = !Subtarget->isAtom();
1672 setPrefFunctionAlignment(4); // 2^4 bytes.
1674 verifyIntrinsicTables();
1677 // This has so far only been implemented for 64-bit MachO.
1678 bool X86TargetLowering::useLoadStackGuardNode() const {
1679 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1680 Subtarget->is64Bit();
1683 TargetLoweringBase::LegalizeTypeAction
1684 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1685 if (ExperimentalVectorWideningLegalization &&
1686 VT.getVectorNumElements() != 1 &&
1687 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1688 return TypeWidenVector;
1690 return TargetLoweringBase::getPreferredVectorAction(VT);
1693 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1695 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1697 const unsigned NumElts = VT.getVectorNumElements();
1698 const EVT EltVT = VT.getVectorElementType();
1699 if (VT.is512BitVector()) {
1700 if (Subtarget->hasAVX512())
1701 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1702 EltVT == MVT::f32 || EltVT == MVT::f64)
1704 case 8: return MVT::v8i1;
1705 case 16: return MVT::v16i1;
1707 if (Subtarget->hasBWI())
1708 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1710 case 32: return MVT::v32i1;
1711 case 64: return MVT::v64i1;
1715 if (VT.is256BitVector() || VT.is128BitVector()) {
1716 if (Subtarget->hasVLX())
1717 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1718 EltVT == MVT::f32 || EltVT == MVT::f64)
1720 case 2: return MVT::v2i1;
1721 case 4: return MVT::v4i1;
1722 case 8: return MVT::v8i1;
1724 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1725 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1727 case 8: return MVT::v8i1;
1728 case 16: return MVT::v16i1;
1729 case 32: return MVT::v32i1;
1733 return VT.changeVectorElementTypeToInteger();
1736 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1737 /// the desired ByVal argument alignment.
1738 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1741 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1742 if (VTy->getBitWidth() == 128)
1744 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1745 unsigned EltAlign = 0;
1746 getMaxByValAlign(ATy->getElementType(), EltAlign);
1747 if (EltAlign > MaxAlign)
1748 MaxAlign = EltAlign;
1749 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1750 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1751 unsigned EltAlign = 0;
1752 getMaxByValAlign(STy->getElementType(i), EltAlign);
1753 if (EltAlign > MaxAlign)
1754 MaxAlign = EltAlign;
1761 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1762 /// function arguments in the caller parameter area. For X86, aggregates
1763 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1764 /// are at 4-byte boundaries.
1765 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1766 if (Subtarget->is64Bit()) {
1767 // Max of 8 and alignment of type.
1768 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1775 if (Subtarget->hasSSE1())
1776 getMaxByValAlign(Ty, Align);
1780 /// getOptimalMemOpType - Returns the target specific optimal type for load
1781 /// and store operations as a result of memset, memcpy, and memmove
1782 /// lowering. If DstAlign is zero that means it's safe to destination
1783 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1784 /// means there isn't a need to check it against alignment requirement,
1785 /// probably because the source does not need to be loaded. If 'IsMemset' is
1786 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1787 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1788 /// source is constant so it does not need to be loaded.
1789 /// It returns EVT::Other if the type should be determined using generic
1790 /// target-independent logic.
1792 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1793 unsigned DstAlign, unsigned SrcAlign,
1794 bool IsMemset, bool ZeroMemset,
1796 MachineFunction &MF) const {
1797 const Function *F = MF.getFunction();
1798 if ((!IsMemset || ZeroMemset) &&
1799 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1800 Attribute::NoImplicitFloat)) {
1802 (Subtarget->isUnalignedMemAccessFast() ||
1803 ((DstAlign == 0 || DstAlign >= 16) &&
1804 (SrcAlign == 0 || SrcAlign >= 16)))) {
1806 if (Subtarget->hasInt256())
1808 if (Subtarget->hasFp256())
1811 if (Subtarget->hasSSE2())
1813 if (Subtarget->hasSSE1())
1815 } else if (!MemcpyStrSrc && Size >= 8 &&
1816 !Subtarget->is64Bit() &&
1817 Subtarget->hasSSE2()) {
1818 // Do not use f64 to lower memcpy if source is string constant. It's
1819 // better to use i32 to avoid the loads.
1823 if (Subtarget->is64Bit() && Size >= 8)
1828 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1830 return X86ScalarSSEf32;
1831 else if (VT == MVT::f64)
1832 return X86ScalarSSEf64;
1837 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1842 *Fast = Subtarget->isUnalignedMemAccessFast();
1846 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1847 /// current function. The returned value is a member of the
1848 /// MachineJumpTableInfo::JTEntryKind enum.
1849 unsigned X86TargetLowering::getJumpTableEncoding() const {
1850 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1852 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1853 Subtarget->isPICStyleGOT())
1854 return MachineJumpTableInfo::EK_Custom32;
1856 // Otherwise, use the normal jump table encoding heuristics.
1857 return TargetLowering::getJumpTableEncoding();
1861 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1862 const MachineBasicBlock *MBB,
1863 unsigned uid,MCContext &Ctx) const{
1864 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1865 Subtarget->isPICStyleGOT());
1866 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1868 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1869 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1872 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1874 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1875 SelectionDAG &DAG) const {
1876 if (!Subtarget->is64Bit())
1877 // This doesn't have SDLoc associated with it, but is not really the
1878 // same as a Register.
1879 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1883 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1884 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1886 const MCExpr *X86TargetLowering::
1887 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1888 MCContext &Ctx) const {
1889 // X86-64 uses RIP relative addressing based on the jump table label.
1890 if (Subtarget->isPICStyleRIPRel())
1891 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1893 // Otherwise, the reference is relative to the PIC base.
1894 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1897 // FIXME: Why this routine is here? Move to RegInfo!
1898 std::pair<const TargetRegisterClass*, uint8_t>
1899 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1900 const TargetRegisterClass *RRC = nullptr;
1902 switch (VT.SimpleTy) {
1904 return TargetLowering::findRepresentativeClass(VT);
1905 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1906 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1909 RRC = &X86::VR64RegClass;
1911 case MVT::f32: case MVT::f64:
1912 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1913 case MVT::v4f32: case MVT::v2f64:
1914 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1916 RRC = &X86::VR128RegClass;
1919 return std::make_pair(RRC, Cost);
1922 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1923 unsigned &Offset) const {
1924 if (!Subtarget->isTargetLinux())
1927 if (Subtarget->is64Bit()) {
1928 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1930 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1942 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1943 unsigned DestAS) const {
1944 assert(SrcAS != DestAS && "Expected different address spaces!");
1946 return SrcAS < 256 && DestAS < 256;
1949 //===----------------------------------------------------------------------===//
1950 // Return Value Calling Convention Implementation
1951 //===----------------------------------------------------------------------===//
1953 #include "X86GenCallingConv.inc"
1956 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1957 MachineFunction &MF, bool isVarArg,
1958 const SmallVectorImpl<ISD::OutputArg> &Outs,
1959 LLVMContext &Context) const {
1960 SmallVector<CCValAssign, 16> RVLocs;
1961 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1962 return CCInfo.CheckReturn(Outs, RetCC_X86);
1965 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1966 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1971 X86TargetLowering::LowerReturn(SDValue Chain,
1972 CallingConv::ID CallConv, bool isVarArg,
1973 const SmallVectorImpl<ISD::OutputArg> &Outs,
1974 const SmallVectorImpl<SDValue> &OutVals,
1975 SDLoc dl, SelectionDAG &DAG) const {
1976 MachineFunction &MF = DAG.getMachineFunction();
1977 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1979 SmallVector<CCValAssign, 16> RVLocs;
1980 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1981 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1984 SmallVector<SDValue, 6> RetOps;
1985 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1986 // Operand #1 = Bytes To Pop
1987 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1990 // Copy the result values into the output registers.
1991 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1992 CCValAssign &VA = RVLocs[i];
1993 assert(VA.isRegLoc() && "Can only return in registers!");
1994 SDValue ValToCopy = OutVals[i];
1995 EVT ValVT = ValToCopy.getValueType();
1997 // Promote values to the appropriate types
1998 if (VA.getLocInfo() == CCValAssign::SExt)
1999 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2000 else if (VA.getLocInfo() == CCValAssign::ZExt)
2001 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2002 else if (VA.getLocInfo() == CCValAssign::AExt)
2003 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2004 else if (VA.getLocInfo() == CCValAssign::BCvt)
2005 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2007 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2008 "Unexpected FP-extend for return value.");
2010 // If this is x86-64, and we disabled SSE, we can't return FP values,
2011 // or SSE or MMX vectors.
2012 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2013 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2014 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2015 report_fatal_error("SSE register return with SSE disabled");
2017 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2018 // llvm-gcc has never done it right and no one has noticed, so this
2019 // should be OK for now.
2020 if (ValVT == MVT::f64 &&
2021 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2022 report_fatal_error("SSE2 register return with SSE2 disabled");
2024 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2025 // the RET instruction and handled by the FP Stackifier.
2026 if (VA.getLocReg() == X86::FP0 ||
2027 VA.getLocReg() == X86::FP1) {
2028 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2029 // change the value to the FP stack register class.
2030 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2031 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2032 RetOps.push_back(ValToCopy);
2033 // Don't emit a copytoreg.
2037 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2038 // which is returned in RAX / RDX.
2039 if (Subtarget->is64Bit()) {
2040 if (ValVT == MVT::x86mmx) {
2041 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2042 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2043 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2045 // If we don't have SSE2 available, convert to v4f32 so the generated
2046 // register is legal.
2047 if (!Subtarget->hasSSE2())
2048 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2053 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2054 Flag = Chain.getValue(1);
2055 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2058 // The x86-64 ABIs require that for returning structs by value we copy
2059 // the sret argument into %rax/%eax (depending on ABI) for the return.
2060 // Win32 requires us to put the sret argument to %eax as well.
2061 // We saved the argument into a virtual register in the entry block,
2062 // so now we copy the value out and into %rax/%eax.
2063 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2064 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2065 MachineFunction &MF = DAG.getMachineFunction();
2066 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2067 unsigned Reg = FuncInfo->getSRetReturnReg();
2069 "SRetReturnReg should have been set in LowerFormalArguments().");
2070 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2073 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2074 X86::RAX : X86::EAX;
2075 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2076 Flag = Chain.getValue(1);
2078 // RAX/EAX now acts like a return value.
2079 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2082 RetOps[0] = Chain; // Update chain.
2084 // Add the flag if we have it.
2086 RetOps.push_back(Flag);
2088 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2091 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2092 if (N->getNumValues() != 1)
2094 if (!N->hasNUsesOfValue(1, 0))
2097 SDValue TCChain = Chain;
2098 SDNode *Copy = *N->use_begin();
2099 if (Copy->getOpcode() == ISD::CopyToReg) {
2100 // If the copy has a glue operand, we conservatively assume it isn't safe to
2101 // perform a tail call.
2102 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2104 TCChain = Copy->getOperand(0);
2105 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2108 bool HasRet = false;
2109 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2111 if (UI->getOpcode() != X86ISD::RET_FLAG)
2113 // If we are returning more than one value, we can definitely
2114 // not make a tail call see PR19530
2115 if (UI->getNumOperands() > 4)
2117 if (UI->getNumOperands() == 4 &&
2118 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2131 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2132 ISD::NodeType ExtendKind) const {
2134 // TODO: Is this also valid on 32-bit?
2135 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2136 ReturnMVT = MVT::i8;
2138 ReturnMVT = MVT::i32;
2140 EVT MinVT = getRegisterType(Context, ReturnMVT);
2141 return VT.bitsLT(MinVT) ? MinVT : VT;
2144 /// LowerCallResult - Lower the result values of a call into the
2145 /// appropriate copies out of appropriate physical registers.
2148 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2149 CallingConv::ID CallConv, bool isVarArg,
2150 const SmallVectorImpl<ISD::InputArg> &Ins,
2151 SDLoc dl, SelectionDAG &DAG,
2152 SmallVectorImpl<SDValue> &InVals) const {
2154 // Assign locations to each value returned by this call.
2155 SmallVector<CCValAssign, 16> RVLocs;
2156 bool Is64Bit = Subtarget->is64Bit();
2157 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2159 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2161 // Copy all of the result registers out of their specified physreg.
2162 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2163 CCValAssign &VA = RVLocs[i];
2164 EVT CopyVT = VA.getValVT();
2166 // If this is x86-64, and we disabled SSE, we can't return FP values
2167 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2168 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2169 report_fatal_error("SSE register return with SSE disabled");
2172 // If we prefer to use the value in xmm registers, copy it out as f80 and
2173 // use a truncate to move it from fp stack reg to xmm reg.
2174 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2175 isScalarFPTypeInSSEReg(VA.getValVT()))
2178 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2179 CopyVT, InFlag).getValue(1);
2180 SDValue Val = Chain.getValue(0);
2182 if (CopyVT != VA.getValVT())
2183 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2184 // This truncation won't change the value.
2185 DAG.getIntPtrConstant(1));
2187 InFlag = Chain.getValue(2);
2188 InVals.push_back(Val);
2194 //===----------------------------------------------------------------------===//
2195 // C & StdCall & Fast Calling Convention implementation
2196 //===----------------------------------------------------------------------===//
2197 // StdCall calling convention seems to be standard for many Windows' API
2198 // routines and around. It differs from C calling convention just a little:
2199 // callee should clean up the stack, not caller. Symbols should be also
2200 // decorated in some fancy way :) It doesn't support any vector arguments.
2201 // For info on fast calling convention see Fast Calling Convention (tail call)
2202 // implementation LowerX86_32FastCCCallTo.
2204 /// CallIsStructReturn - Determines whether a call uses struct return
2206 enum StructReturnType {
2211 static StructReturnType
2212 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2214 return NotStructReturn;
2216 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2217 if (!Flags.isSRet())
2218 return NotStructReturn;
2219 if (Flags.isInReg())
2220 return RegStructReturn;
2221 return StackStructReturn;
2224 /// ArgsAreStructReturn - Determines whether a function uses struct
2225 /// return semantics.
2226 static StructReturnType
2227 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2229 return NotStructReturn;
2231 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2232 if (!Flags.isSRet())
2233 return NotStructReturn;
2234 if (Flags.isInReg())
2235 return RegStructReturn;
2236 return StackStructReturn;
2239 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2240 /// by "Src" to address "Dst" with size and alignment information specified by
2241 /// the specific parameter attribute. The copy will be passed as a byval
2242 /// function parameter.
2244 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2245 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2247 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2249 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2250 /*isVolatile*/false, /*AlwaysInline=*/true,
2251 MachinePointerInfo(), MachinePointerInfo());
2254 /// IsTailCallConvention - Return true if the calling convention is one that
2255 /// supports tail call optimization.
2256 static bool IsTailCallConvention(CallingConv::ID CC) {
2257 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2258 CC == CallingConv::HiPE);
2261 /// \brief Return true if the calling convention is a C calling convention.
2262 static bool IsCCallConvention(CallingConv::ID CC) {
2263 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2264 CC == CallingConv::X86_64_SysV);
2267 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2268 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2272 CallingConv::ID CalleeCC = CS.getCallingConv();
2273 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2279 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2280 /// a tailcall target by changing its ABI.
2281 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2282 bool GuaranteedTailCallOpt) {
2283 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2287 X86TargetLowering::LowerMemArgument(SDValue Chain,
2288 CallingConv::ID CallConv,
2289 const SmallVectorImpl<ISD::InputArg> &Ins,
2290 SDLoc dl, SelectionDAG &DAG,
2291 const CCValAssign &VA,
2292 MachineFrameInfo *MFI,
2294 // Create the nodes corresponding to a load from this parameter slot.
2295 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2296 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2297 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2298 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2301 // If value is passed by pointer we have address passed instead of the value
2303 if (VA.getLocInfo() == CCValAssign::Indirect)
2304 ValVT = VA.getLocVT();
2306 ValVT = VA.getValVT();
2308 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2309 // changed with more analysis.
2310 // In case of tail call optimization mark all arguments mutable. Since they
2311 // could be overwritten by lowering of arguments in case of a tail call.
2312 if (Flags.isByVal()) {
2313 unsigned Bytes = Flags.getByValSize();
2314 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2315 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2316 return DAG.getFrameIndex(FI, getPointerTy());
2318 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2319 VA.getLocMemOffset(), isImmutable);
2320 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2321 return DAG.getLoad(ValVT, dl, Chain, FIN,
2322 MachinePointerInfo::getFixedStack(FI),
2323 false, false, false, 0);
2327 // FIXME: Get this from tablegen.
2328 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2329 const X86Subtarget *Subtarget) {
2330 assert(Subtarget->is64Bit());
2332 if (Subtarget->isCallingConvWin64(CallConv)) {
2333 static const MCPhysReg GPR64ArgRegsWin64[] = {
2334 X86::RCX, X86::RDX, X86::R8, X86::R9
2336 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2339 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2340 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2342 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2345 // FIXME: Get this from tablegen.
2346 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2347 CallingConv::ID CallConv,
2348 const X86Subtarget *Subtarget) {
2349 assert(Subtarget->is64Bit());
2350 if (Subtarget->isCallingConvWin64(CallConv)) {
2351 // The XMM registers which might contain var arg parameters are shadowed
2352 // in their paired GPR. So we only need to save the GPR to their home
2354 // TODO: __vectorcall will change this.
2358 const Function *Fn = MF.getFunction();
2359 bool NoImplicitFloatOps = Fn->getAttributes().
2360 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2361 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2362 "SSE register cannot be used when SSE is disabled!");
2363 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2364 !Subtarget->hasSSE1())
2365 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2369 static const MCPhysReg XMMArgRegs64Bit[] = {
2370 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2371 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2373 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2377 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2378 CallingConv::ID CallConv,
2380 const SmallVectorImpl<ISD::InputArg> &Ins,
2383 SmallVectorImpl<SDValue> &InVals)
2385 MachineFunction &MF = DAG.getMachineFunction();
2386 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2388 const Function* Fn = MF.getFunction();
2389 if (Fn->hasExternalLinkage() &&
2390 Subtarget->isTargetCygMing() &&
2391 Fn->getName() == "main")
2392 FuncInfo->setForceFramePointer(true);
2394 MachineFrameInfo *MFI = MF.getFrameInfo();
2395 bool Is64Bit = Subtarget->is64Bit();
2396 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2398 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2399 "Var args not supported with calling convention fastcc, ghc or hipe");
2401 // Assign locations to all of the incoming arguments.
2402 SmallVector<CCValAssign, 16> ArgLocs;
2403 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2405 // Allocate shadow area for Win64
2407 CCInfo.AllocateStack(32, 8);
2409 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2411 unsigned LastVal = ~0U;
2413 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2414 CCValAssign &VA = ArgLocs[i];
2415 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2417 assert(VA.getValNo() != LastVal &&
2418 "Don't support value assigned to multiple locs yet");
2420 LastVal = VA.getValNo();
2422 if (VA.isRegLoc()) {
2423 EVT RegVT = VA.getLocVT();
2424 const TargetRegisterClass *RC;
2425 if (RegVT == MVT::i32)
2426 RC = &X86::GR32RegClass;
2427 else if (Is64Bit && RegVT == MVT::i64)
2428 RC = &X86::GR64RegClass;
2429 else if (RegVT == MVT::f32)
2430 RC = &X86::FR32RegClass;
2431 else if (RegVT == MVT::f64)
2432 RC = &X86::FR64RegClass;
2433 else if (RegVT.is512BitVector())
2434 RC = &X86::VR512RegClass;
2435 else if (RegVT.is256BitVector())
2436 RC = &X86::VR256RegClass;
2437 else if (RegVT.is128BitVector())
2438 RC = &X86::VR128RegClass;
2439 else if (RegVT == MVT::x86mmx)
2440 RC = &X86::VR64RegClass;
2441 else if (RegVT == MVT::i1)
2442 RC = &X86::VK1RegClass;
2443 else if (RegVT == MVT::v8i1)
2444 RC = &X86::VK8RegClass;
2445 else if (RegVT == MVT::v16i1)
2446 RC = &X86::VK16RegClass;
2447 else if (RegVT == MVT::v32i1)
2448 RC = &X86::VK32RegClass;
2449 else if (RegVT == MVT::v64i1)
2450 RC = &X86::VK64RegClass;
2452 llvm_unreachable("Unknown argument type!");
2454 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2455 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2457 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2458 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2460 if (VA.getLocInfo() == CCValAssign::SExt)
2461 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2462 DAG.getValueType(VA.getValVT()));
2463 else if (VA.getLocInfo() == CCValAssign::ZExt)
2464 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::BCvt)
2467 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2469 if (VA.isExtInLoc()) {
2470 // Handle MMX values passed in XMM regs.
2471 if (RegVT.isVector())
2472 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2474 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2477 assert(VA.isMemLoc());
2478 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2481 // If value is passed via pointer - do a load.
2482 if (VA.getLocInfo() == CCValAssign::Indirect)
2483 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2484 MachinePointerInfo(), false, false, false, 0);
2486 InVals.push_back(ArgValue);
2489 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2490 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2491 // The x86-64 ABIs require that for returning structs by value we copy
2492 // the sret argument into %rax/%eax (depending on ABI) for the return.
2493 // Win32 requires us to put the sret argument to %eax as well.
2494 // Save the argument into a virtual register so that we can access it
2495 // from the return points.
2496 if (Ins[i].Flags.isSRet()) {
2497 unsigned Reg = FuncInfo->getSRetReturnReg();
2499 MVT PtrTy = getPointerTy();
2500 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2501 FuncInfo->setSRetReturnReg(Reg);
2503 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2504 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2510 unsigned StackSize = CCInfo.getNextStackOffset();
2511 // Align stack specially for tail calls.
2512 if (FuncIsMadeTailCallSafe(CallConv,
2513 MF.getTarget().Options.GuaranteedTailCallOpt))
2514 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2516 // If the function takes variable number of arguments, make a frame index for
2517 // the start of the first vararg value... for expansion of llvm.va_start. We
2518 // can skip this if there are no va_start calls.
2519 if (MFI->hasVAStart() &&
2520 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2521 CallConv != CallingConv::X86_ThisCall))) {
2522 FuncInfo->setVarArgsFrameIndex(
2523 MFI->CreateFixedObject(1, StackSize, true));
2526 // 64-bit calling conventions support varargs and register parameters, so we
2527 // have to do extra work to spill them in the prologue or forward them to
2529 if (Is64Bit && isVarArg &&
2530 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2531 // Find the first unallocated argument registers.
2532 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2533 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2534 unsigned NumIntRegs =
2535 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2536 unsigned NumXMMRegs =
2537 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2538 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2539 "SSE register cannot be used when SSE is disabled!");
2541 // Gather all the live in physical registers.
2542 SmallVector<SDValue, 6> LiveGPRs;
2543 SmallVector<SDValue, 8> LiveXMMRegs;
2545 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2546 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2548 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2550 if (!ArgXMMs.empty()) {
2551 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2552 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2553 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2554 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2555 LiveXMMRegs.push_back(
2556 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2560 // Store them to the va_list returned by va_start.
2561 if (MFI->hasVAStart()) {
2563 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2564 // Get to the caller-allocated home save location. Add 8 to account
2565 // for the return address.
2566 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2567 FuncInfo->setRegSaveFrameIndex(
2568 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2569 // Fixup to set vararg frame on shadow area (4 x i64).
2571 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2573 // For X86-64, if there are vararg parameters that are passed via
2574 // registers, then we must store them to their spots on the stack so
2575 // they may be loaded by deferencing the result of va_next.
2576 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2577 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2578 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2579 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2582 // Store the integer parameter registers.
2583 SmallVector<SDValue, 8> MemOps;
2584 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2586 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2587 for (SDValue Val : LiveGPRs) {
2588 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2589 DAG.getIntPtrConstant(Offset));
2591 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2592 MachinePointerInfo::getFixedStack(
2593 FuncInfo->getRegSaveFrameIndex(), Offset),
2595 MemOps.push_back(Store);
2599 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2600 // Now store the XMM (fp + vector) parameter registers.
2601 SmallVector<SDValue, 12> SaveXMMOps;
2602 SaveXMMOps.push_back(Chain);
2603 SaveXMMOps.push_back(ALVal);
2604 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2605 FuncInfo->getRegSaveFrameIndex()));
2606 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2607 FuncInfo->getVarArgsFPOffset()));
2608 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2610 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2611 MVT::Other, SaveXMMOps));
2614 if (!MemOps.empty())
2615 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2617 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2618 // to the liveout set on a musttail call.
2619 assert(MFI->hasMustTailInVarArgFunc());
2620 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2621 typedef X86MachineFunctionInfo::Forward Forward;
2623 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2625 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2626 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2627 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2630 if (!ArgXMMs.empty()) {
2632 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2633 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2634 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2636 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2638 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2639 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2641 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2647 // Some CCs need callee pop.
2648 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2649 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2650 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2652 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2653 // If this is an sret function, the return should pop the hidden pointer.
2654 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2655 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2656 argsAreStructReturn(Ins) == StackStructReturn)
2657 FuncInfo->setBytesToPopOnReturn(4);
2661 // RegSaveFrameIndex is X86-64 only.
2662 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2663 if (CallConv == CallingConv::X86_FastCall ||
2664 CallConv == CallingConv::X86_ThisCall)
2665 // fastcc functions can't have varargs.
2666 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2669 FuncInfo->setArgumentStackSize(StackSize);
2675 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2676 SDValue StackPtr, SDValue Arg,
2677 SDLoc dl, SelectionDAG &DAG,
2678 const CCValAssign &VA,
2679 ISD::ArgFlagsTy Flags) const {
2680 unsigned LocMemOffset = VA.getLocMemOffset();
2681 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2682 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2683 if (Flags.isByVal())
2684 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2686 return DAG.getStore(Chain, dl, Arg, PtrOff,
2687 MachinePointerInfo::getStack(LocMemOffset),
2691 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2692 /// optimization is performed and it is required.
2694 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2695 SDValue &OutRetAddr, SDValue Chain,
2696 bool IsTailCall, bool Is64Bit,
2697 int FPDiff, SDLoc dl) const {
2698 // Adjust the Return address stack slot.
2699 EVT VT = getPointerTy();
2700 OutRetAddr = getReturnAddressFrameIndex(DAG);
2702 // Load the "old" Return address.
2703 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2704 false, false, false, 0);
2705 return SDValue(OutRetAddr.getNode(), 1);
2708 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2709 /// optimization is performed and it is required (FPDiff!=0).
2710 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2711 SDValue Chain, SDValue RetAddrFrIdx,
2712 EVT PtrVT, unsigned SlotSize,
2713 int FPDiff, SDLoc dl) {
2714 // Store the return address to the appropriate stack slot.
2715 if (!FPDiff) return Chain;
2716 // Calculate the new stack slot for the return address.
2717 int NewReturnAddrFI =
2718 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2720 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2721 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2722 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2728 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2729 SmallVectorImpl<SDValue> &InVals) const {
2730 SelectionDAG &DAG = CLI.DAG;
2732 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2733 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2734 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2735 SDValue Chain = CLI.Chain;
2736 SDValue Callee = CLI.Callee;
2737 CallingConv::ID CallConv = CLI.CallConv;
2738 bool &isTailCall = CLI.IsTailCall;
2739 bool isVarArg = CLI.IsVarArg;
2741 MachineFunction &MF = DAG.getMachineFunction();
2742 bool Is64Bit = Subtarget->is64Bit();
2743 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2744 StructReturnType SR = callIsStructReturn(Outs);
2745 bool IsSibcall = false;
2746 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2748 if (MF.getTarget().Options.DisableTailCalls)
2751 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2753 // Force this to be a tail call. The verifier rules are enough to ensure
2754 // that we can lower this successfully without moving the return address
2757 } else if (isTailCall) {
2758 // Check if it's really possible to do a tail call.
2759 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2760 isVarArg, SR != NotStructReturn,
2761 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2762 Outs, OutVals, Ins, DAG);
2764 // Sibcalls are automatically detected tailcalls which do not require
2766 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2773 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2774 "Var args not supported with calling convention fastcc, ghc or hipe");
2776 // Analyze operands of the call, assigning locations to each operand.
2777 SmallVector<CCValAssign, 16> ArgLocs;
2778 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2780 // Allocate shadow area for Win64
2782 CCInfo.AllocateStack(32, 8);
2784 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2786 // Get a count of how many bytes are to be pushed on the stack.
2787 unsigned NumBytes = CCInfo.getNextStackOffset();
2789 // This is a sibcall. The memory operands are available in caller's
2790 // own caller's stack.
2792 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2793 IsTailCallConvention(CallConv))
2794 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2797 if (isTailCall && !IsSibcall && !IsMustTail) {
2798 // Lower arguments at fp - stackoffset + fpdiff.
2799 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2801 FPDiff = NumBytesCallerPushed - NumBytes;
2803 // Set the delta of movement of the returnaddr stackslot.
2804 // But only set if delta is greater than previous delta.
2805 if (FPDiff < X86Info->getTCReturnAddrDelta())
2806 X86Info->setTCReturnAddrDelta(FPDiff);
2809 unsigned NumBytesToPush = NumBytes;
2810 unsigned NumBytesToPop = NumBytes;
2812 // If we have an inalloca argument, all stack space has already been allocated
2813 // for us and be right at the top of the stack. We don't support multiple
2814 // arguments passed in memory when using inalloca.
2815 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2817 if (!ArgLocs.back().isMemLoc())
2818 report_fatal_error("cannot use inalloca attribute on a register "
2820 if (ArgLocs.back().getLocMemOffset() != 0)
2821 report_fatal_error("any parameter with the inalloca attribute must be "
2822 "the only memory argument");
2826 Chain = DAG.getCALLSEQ_START(
2827 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2829 SDValue RetAddrFrIdx;
2830 // Load return address for tail calls.
2831 if (isTailCall && FPDiff)
2832 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2833 Is64Bit, FPDiff, dl);
2835 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2836 SmallVector<SDValue, 8> MemOpChains;
2839 // Walk the register/memloc assignments, inserting copies/loads. In the case
2840 // of tail call optimization arguments are handle later.
2841 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2842 DAG.getSubtarget().getRegisterInfo());
2843 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2844 // Skip inalloca arguments, they have already been written.
2845 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2846 if (Flags.isInAlloca())
2849 CCValAssign &VA = ArgLocs[i];
2850 EVT RegVT = VA.getLocVT();
2851 SDValue Arg = OutVals[i];
2852 bool isByVal = Flags.isByVal();
2854 // Promote the value if needed.
2855 switch (VA.getLocInfo()) {
2856 default: llvm_unreachable("Unknown loc info!");
2857 case CCValAssign::Full: break;
2858 case CCValAssign::SExt:
2859 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2861 case CCValAssign::ZExt:
2862 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::AExt:
2865 if (RegVT.is128BitVector()) {
2866 // Special case: passing MMX values in XMM registers.
2867 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2868 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2869 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2871 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2873 case CCValAssign::BCvt:
2874 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2876 case CCValAssign::Indirect: {
2877 // Store the argument.
2878 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2879 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2880 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2881 MachinePointerInfo::getFixedStack(FI),
2888 if (VA.isRegLoc()) {
2889 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2890 if (isVarArg && IsWin64) {
2891 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2892 // shadow reg if callee is a varargs function.
2893 unsigned ShadowReg = 0;
2894 switch (VA.getLocReg()) {
2895 case X86::XMM0: ShadowReg = X86::RCX; break;
2896 case X86::XMM1: ShadowReg = X86::RDX; break;
2897 case X86::XMM2: ShadowReg = X86::R8; break;
2898 case X86::XMM3: ShadowReg = X86::R9; break;
2901 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2903 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2904 assert(VA.isMemLoc());
2905 if (!StackPtr.getNode())
2906 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2908 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2909 dl, DAG, VA, Flags));
2913 if (!MemOpChains.empty())
2914 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2916 if (Subtarget->isPICStyleGOT()) {
2917 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2920 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2921 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2923 // If we are tail calling and generating PIC/GOT style code load the
2924 // address of the callee into ECX. The value in ecx is used as target of
2925 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2926 // for tail calls on PIC/GOT architectures. Normally we would just put the
2927 // address of GOT into ebx and then call target@PLT. But for tail calls
2928 // ebx would be restored (since ebx is callee saved) before jumping to the
2931 // Note: The actual moving to ECX is done further down.
2932 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2933 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2934 !G->getGlobal()->hasProtectedVisibility())
2935 Callee = LowerGlobalAddress(Callee, DAG);
2936 else if (isa<ExternalSymbolSDNode>(Callee))
2937 Callee = LowerExternalSymbol(Callee, DAG);
2941 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2942 // From AMD64 ABI document:
2943 // For calls that may call functions that use varargs or stdargs
2944 // (prototype-less calls or calls to functions containing ellipsis (...) in
2945 // the declaration) %al is used as hidden argument to specify the number
2946 // of SSE registers used. The contents of %al do not need to match exactly
2947 // the number of registers, but must be an ubound on the number of SSE
2948 // registers used and is in the range 0 - 8 inclusive.
2950 // Count the number of XMM registers allocated.
2951 static const MCPhysReg XMMArgRegs[] = {
2952 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2953 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2955 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2956 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2957 && "SSE registers cannot be used when SSE is disabled");
2959 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2960 DAG.getConstant(NumXMMRegs, MVT::i8)));
2963 if (Is64Bit && isVarArg && IsMustTail) {
2964 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2965 for (const auto &F : Forwards) {
2966 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2967 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2971 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2972 // don't need this because the eligibility check rejects calls that require
2973 // shuffling arguments passed in memory.
2974 if (!IsSibcall && isTailCall) {
2975 // Force all the incoming stack arguments to be loaded from the stack
2976 // before any new outgoing arguments are stored to the stack, because the
2977 // outgoing stack slots may alias the incoming argument stack slots, and
2978 // the alias isn't otherwise explicit. This is slightly more conservative
2979 // than necessary, because it means that each store effectively depends
2980 // on every argument instead of just those arguments it would clobber.
2981 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2983 SmallVector<SDValue, 8> MemOpChains2;
2986 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2987 CCValAssign &VA = ArgLocs[i];
2990 assert(VA.isMemLoc());
2991 SDValue Arg = OutVals[i];
2992 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2993 // Skip inalloca arguments. They don't require any work.
2994 if (Flags.isInAlloca())
2996 // Create frame index.
2997 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2998 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2999 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3000 FIN = DAG.getFrameIndex(FI, getPointerTy());
3002 if (Flags.isByVal()) {
3003 // Copy relative to framepointer.
3004 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3005 if (!StackPtr.getNode())
3006 StackPtr = DAG.getCopyFromReg(Chain, dl,
3007 RegInfo->getStackRegister(),
3009 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3011 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3015 // Store relative to framepointer.
3016 MemOpChains2.push_back(
3017 DAG.getStore(ArgChain, dl, Arg, FIN,
3018 MachinePointerInfo::getFixedStack(FI),
3023 if (!MemOpChains2.empty())
3024 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3026 // Store the return address to the appropriate stack slot.
3027 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3028 getPointerTy(), RegInfo->getSlotSize(),
3032 // Build a sequence of copy-to-reg nodes chained together with token chain
3033 // and flag operands which copy the outgoing args into registers.
3035 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3036 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3037 RegsToPass[i].second, InFlag);
3038 InFlag = Chain.getValue(1);
3041 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3042 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3043 // In the 64-bit large code model, we have to make all calls
3044 // through a register, since the call instruction's 32-bit
3045 // pc-relative offset may not be large enough to hold the whole
3047 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3048 // If the callee is a GlobalAddress node (quite common, every direct call
3049 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3052 // We should use extra load for direct calls to dllimported functions in
3054 const GlobalValue *GV = G->getGlobal();
3055 if (!GV->hasDLLImportStorageClass()) {
3056 unsigned char OpFlags = 0;
3057 bool ExtraLoad = false;
3058 unsigned WrapperKind = ISD::DELETED_NODE;
3060 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3061 // external symbols most go through the PLT in PIC mode. If the symbol
3062 // has hidden or protected visibility, or if it is static or local, then
3063 // we don't need to use the PLT - we can directly call it.
3064 if (Subtarget->isTargetELF() &&
3065 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3066 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3067 OpFlags = X86II::MO_PLT;
3068 } else if (Subtarget->isPICStyleStubAny() &&
3069 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3070 (!Subtarget->getTargetTriple().isMacOSX() ||
3071 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3072 // PC-relative references to external symbols should go through $stub,
3073 // unless we're building with the leopard linker or later, which
3074 // automatically synthesizes these stubs.
3075 OpFlags = X86II::MO_DARWIN_STUB;
3076 } else if (Subtarget->isPICStyleRIPRel() &&
3077 isa<Function>(GV) &&
3078 cast<Function>(GV)->getAttributes().
3079 hasAttribute(AttributeSet::FunctionIndex,
3080 Attribute::NonLazyBind)) {
3081 // If the function is marked as non-lazy, generate an indirect call
3082 // which loads from the GOT directly. This avoids runtime overhead
3083 // at the cost of eager binding (and one extra byte of encoding).
3084 OpFlags = X86II::MO_GOTPCREL;
3085 WrapperKind = X86ISD::WrapperRIP;
3089 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3090 G->getOffset(), OpFlags);
3092 // Add a wrapper if needed.
3093 if (WrapperKind != ISD::DELETED_NODE)
3094 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3095 // Add extra indirection if needed.
3097 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3098 MachinePointerInfo::getGOT(),
3099 false, false, false, 0);
3101 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3102 unsigned char OpFlags = 0;
3104 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3105 // external symbols should go through the PLT.
3106 if (Subtarget->isTargetELF() &&
3107 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3108 OpFlags = X86II::MO_PLT;
3109 } else if (Subtarget->isPICStyleStubAny() &&
3110 (!Subtarget->getTargetTriple().isMacOSX() ||
3111 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3112 // PC-relative references to external symbols should go through $stub,
3113 // unless we're building with the leopard linker or later, which
3114 // automatically synthesizes these stubs.
3115 OpFlags = X86II::MO_DARWIN_STUB;
3118 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3120 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3121 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3122 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3125 // Returns a chain & a flag for retval copy to use.
3126 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3127 SmallVector<SDValue, 8> Ops;
3129 if (!IsSibcall && isTailCall) {
3130 Chain = DAG.getCALLSEQ_END(Chain,
3131 DAG.getIntPtrConstant(NumBytesToPop, true),
3132 DAG.getIntPtrConstant(0, true), InFlag, dl);
3133 InFlag = Chain.getValue(1);
3136 Ops.push_back(Chain);
3137 Ops.push_back(Callee);
3140 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3142 // Add argument registers to the end of the list so that they are known live
3144 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3145 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3146 RegsToPass[i].second.getValueType()));
3148 // Add a register mask operand representing the call-preserved registers.
3149 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3150 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3151 assert(Mask && "Missing call preserved mask for calling convention");
3152 Ops.push_back(DAG.getRegisterMask(Mask));
3154 if (InFlag.getNode())
3155 Ops.push_back(InFlag);
3159 //// If this is the first return lowered for this function, add the regs
3160 //// to the liveout set for the function.
3161 // This isn't right, although it's probably harmless on x86; liveouts
3162 // should be computed from returns not tail calls. Consider a void
3163 // function making a tail call to a function returning int.
3164 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3167 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3168 InFlag = Chain.getValue(1);
3170 // Create the CALLSEQ_END node.
3171 unsigned NumBytesForCalleeToPop;
3172 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3173 DAG.getTarget().Options.GuaranteedTailCallOpt))
3174 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3175 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3176 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3177 SR == StackStructReturn)
3178 // If this is a call to a struct-return function, the callee
3179 // pops the hidden struct pointer, so we have to push it back.
3180 // This is common for Darwin/X86, Linux & Mingw32 targets.
3181 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3182 NumBytesForCalleeToPop = 4;
3184 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3186 // Returns a flag for retval copy to use.
3188 Chain = DAG.getCALLSEQ_END(Chain,
3189 DAG.getIntPtrConstant(NumBytesToPop, true),
3190 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3193 InFlag = Chain.getValue(1);
3196 // Handle result values, copying them out of physregs into vregs that we
3198 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3199 Ins, dl, DAG, InVals);
3202 //===----------------------------------------------------------------------===//
3203 // Fast Calling Convention (tail call) implementation
3204 //===----------------------------------------------------------------------===//
3206 // Like std call, callee cleans arguments, convention except that ECX is
3207 // reserved for storing the tail called function address. Only 2 registers are
3208 // free for argument passing (inreg). Tail call optimization is performed
3210 // * tailcallopt is enabled
3211 // * caller/callee are fastcc
3212 // On X86_64 architecture with GOT-style position independent code only local
3213 // (within module) calls are supported at the moment.
3214 // To keep the stack aligned according to platform abi the function
3215 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3216 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3217 // If a tail called function callee has more arguments than the caller the
3218 // caller needs to make sure that there is room to move the RETADDR to. This is
3219 // achieved by reserving an area the size of the argument delta right after the
3220 // original RETADDR, but before the saved framepointer or the spilled registers
3221 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3233 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3234 /// for a 16 byte align requirement.
3236 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3237 SelectionDAG& DAG) const {
3238 MachineFunction &MF = DAG.getMachineFunction();
3239 const TargetMachine &TM = MF.getTarget();
3240 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3241 TM.getSubtargetImpl()->getRegisterInfo());
3242 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3243 unsigned StackAlignment = TFI.getStackAlignment();
3244 uint64_t AlignMask = StackAlignment - 1;
3245 int64_t Offset = StackSize;
3246 unsigned SlotSize = RegInfo->getSlotSize();
3247 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3248 // Number smaller than 12 so just add the difference.
3249 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3251 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3252 Offset = ((~AlignMask) & Offset) + StackAlignment +
3253 (StackAlignment-SlotSize);
3258 /// MatchingStackOffset - Return true if the given stack call argument is
3259 /// already available in the same position (relatively) of the caller's
3260 /// incoming argument stack.
3262 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3263 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3264 const X86InstrInfo *TII) {
3265 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3267 if (Arg.getOpcode() == ISD::CopyFromReg) {
3268 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3269 if (!TargetRegisterInfo::isVirtualRegister(VR))
3271 MachineInstr *Def = MRI->getVRegDef(VR);
3274 if (!Flags.isByVal()) {
3275 if (!TII->isLoadFromStackSlot(Def, FI))
3278 unsigned Opcode = Def->getOpcode();
3279 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3280 Def->getOperand(1).isFI()) {
3281 FI = Def->getOperand(1).getIndex();
3282 Bytes = Flags.getByValSize();
3286 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3287 if (Flags.isByVal())
3288 // ByVal argument is passed in as a pointer but it's now being
3289 // dereferenced. e.g.
3290 // define @foo(%struct.X* %A) {
3291 // tail call @bar(%struct.X* byval %A)
3294 SDValue Ptr = Ld->getBasePtr();
3295 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3298 FI = FINode->getIndex();
3299 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3300 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3301 FI = FINode->getIndex();
3302 Bytes = Flags.getByValSize();
3306 assert(FI != INT_MAX);
3307 if (!MFI->isFixedObjectIndex(FI))
3309 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3312 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3313 /// for tail call optimization. Targets which want to do tail call
3314 /// optimization should implement this function.
3316 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3317 CallingConv::ID CalleeCC,
3319 bool isCalleeStructRet,
3320 bool isCallerStructRet,
3322 const SmallVectorImpl<ISD::OutputArg> &Outs,
3323 const SmallVectorImpl<SDValue> &OutVals,
3324 const SmallVectorImpl<ISD::InputArg> &Ins,
3325 SelectionDAG &DAG) const {
3326 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3329 // If -tailcallopt is specified, make fastcc functions tail-callable.
3330 const MachineFunction &MF = DAG.getMachineFunction();
3331 const Function *CallerF = MF.getFunction();
3333 // If the function return type is x86_fp80 and the callee return type is not,
3334 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3335 // perform a tailcall optimization here.
3336 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3339 CallingConv::ID CallerCC = CallerF->getCallingConv();
3340 bool CCMatch = CallerCC == CalleeCC;
3341 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3342 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3344 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3345 if (IsTailCallConvention(CalleeCC) && CCMatch)
3350 // Look for obvious safe cases to perform tail call optimization that do not
3351 // require ABI changes. This is what gcc calls sibcall.
3353 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3354 // emit a special epilogue.
3355 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3356 DAG.getSubtarget().getRegisterInfo());
3357 if (RegInfo->needsStackRealignment(MF))
3360 // Also avoid sibcall optimization if either caller or callee uses struct
3361 // return semantics.
3362 if (isCalleeStructRet || isCallerStructRet)
3365 // An stdcall/thiscall caller is expected to clean up its arguments; the
3366 // callee isn't going to do that.
3367 // FIXME: this is more restrictive than needed. We could produce a tailcall
3368 // when the stack adjustment matches. For example, with a thiscall that takes
3369 // only one argument.
3370 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3371 CallerCC == CallingConv::X86_ThisCall))
3374 // Do not sibcall optimize vararg calls unless all arguments are passed via
3376 if (isVarArg && !Outs.empty()) {
3378 // Optimizing for varargs on Win64 is unlikely to be safe without
3379 // additional testing.
3380 if (IsCalleeWin64 || IsCallerWin64)
3383 SmallVector<CCValAssign, 16> ArgLocs;
3384 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3387 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3388 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3389 if (!ArgLocs[i].isRegLoc())
3393 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3394 // stack. Therefore, if it's not used by the call it is not safe to optimize
3395 // this into a sibcall.
3396 bool Unused = false;
3397 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3404 SmallVector<CCValAssign, 16> RVLocs;
3405 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3407 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3408 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3409 CCValAssign &VA = RVLocs[i];
3410 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3415 // If the calling conventions do not match, then we'd better make sure the
3416 // results are returned in the same way as what the caller expects.
3418 SmallVector<CCValAssign, 16> RVLocs1;
3419 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3421 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3423 SmallVector<CCValAssign, 16> RVLocs2;
3424 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3426 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3428 if (RVLocs1.size() != RVLocs2.size())
3430 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3431 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3433 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3435 if (RVLocs1[i].isRegLoc()) {
3436 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3439 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3445 // If the callee takes no arguments then go on to check the results of the
3447 if (!Outs.empty()) {
3448 // Check if stack adjustment is needed. For now, do not do this if any
3449 // argument is passed on the stack.
3450 SmallVector<CCValAssign, 16> ArgLocs;
3451 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3454 // Allocate shadow area for Win64
3456 CCInfo.AllocateStack(32, 8);
3458 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3459 if (CCInfo.getNextStackOffset()) {
3460 MachineFunction &MF = DAG.getMachineFunction();
3461 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3464 // Check if the arguments are already laid out in the right way as
3465 // the caller's fixed stack objects.
3466 MachineFrameInfo *MFI = MF.getFrameInfo();
3467 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3468 const X86InstrInfo *TII =
3469 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3470 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3471 CCValAssign &VA = ArgLocs[i];
3472 SDValue Arg = OutVals[i];
3473 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3474 if (VA.getLocInfo() == CCValAssign::Indirect)
3476 if (!VA.isRegLoc()) {
3477 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3484 // If the tailcall address may be in a register, then make sure it's
3485 // possible to register allocate for it. In 32-bit, the call address can
3486 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3487 // callee-saved registers are restored. These happen to be the same
3488 // registers used to pass 'inreg' arguments so watch out for those.
3489 if (!Subtarget->is64Bit() &&
3490 ((!isa<GlobalAddressSDNode>(Callee) &&
3491 !isa<ExternalSymbolSDNode>(Callee)) ||
3492 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3493 unsigned NumInRegs = 0;
3494 // In PIC we need an extra register to formulate the address computation
3496 unsigned MaxInRegs =
3497 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3499 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3500 CCValAssign &VA = ArgLocs[i];
3503 unsigned Reg = VA.getLocReg();
3506 case X86::EAX: case X86::EDX: case X86::ECX:
3507 if (++NumInRegs == MaxInRegs)
3519 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3520 const TargetLibraryInfo *libInfo) const {
3521 return X86::createFastISel(funcInfo, libInfo);
3524 //===----------------------------------------------------------------------===//
3525 // Other Lowering Hooks
3526 //===----------------------------------------------------------------------===//
3528 static bool MayFoldLoad(SDValue Op) {
3529 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3532 static bool MayFoldIntoStore(SDValue Op) {
3533 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3536 static bool isTargetShuffle(unsigned Opcode) {
3538 default: return false;
3539 case X86ISD::BLENDI:
3540 case X86ISD::PSHUFB:
3541 case X86ISD::PSHUFD:
3542 case X86ISD::PSHUFHW:
3543 case X86ISD::PSHUFLW:
3545 case X86ISD::PALIGNR:
3546 case X86ISD::MOVLHPS:
3547 case X86ISD::MOVLHPD:
3548 case X86ISD::MOVHLPS:
3549 case X86ISD::MOVLPS:
3550 case X86ISD::MOVLPD:
3551 case X86ISD::MOVSHDUP:
3552 case X86ISD::MOVSLDUP:
3553 case X86ISD::MOVDDUP:
3556 case X86ISD::UNPCKL:
3557 case X86ISD::UNPCKH:
3558 case X86ISD::VPERMILPI:
3559 case X86ISD::VPERM2X128:
3560 case X86ISD::VPERMI:
3565 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3566 SDValue V1, SelectionDAG &DAG) {
3568 default: llvm_unreachable("Unknown x86 shuffle node");
3569 case X86ISD::MOVSHDUP:
3570 case X86ISD::MOVSLDUP:
3571 case X86ISD::MOVDDUP:
3572 return DAG.getNode(Opc, dl, VT, V1);
3576 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3577 SDValue V1, unsigned TargetMask,
3578 SelectionDAG &DAG) {
3580 default: llvm_unreachable("Unknown x86 shuffle node");
3581 case X86ISD::PSHUFD:
3582 case X86ISD::PSHUFHW:
3583 case X86ISD::PSHUFLW:
3584 case X86ISD::VPERMILPI:
3585 case X86ISD::VPERMI:
3586 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3590 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3591 SDValue V1, SDValue V2, unsigned TargetMask,
3592 SelectionDAG &DAG) {
3594 default: llvm_unreachable("Unknown x86 shuffle node");
3595 case X86ISD::PALIGNR:
3596 case X86ISD::VALIGN:
3598 case X86ISD::VPERM2X128:
3599 return DAG.getNode(Opc, dl, VT, V1, V2,
3600 DAG.getConstant(TargetMask, MVT::i8));
3604 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3605 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3607 default: llvm_unreachable("Unknown x86 shuffle node");
3608 case X86ISD::MOVLHPS:
3609 case X86ISD::MOVLHPD:
3610 case X86ISD::MOVHLPS:
3611 case X86ISD::MOVLPS:
3612 case X86ISD::MOVLPD:
3615 case X86ISD::UNPCKL:
3616 case X86ISD::UNPCKH:
3617 return DAG.getNode(Opc, dl, VT, V1, V2);
3621 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3622 MachineFunction &MF = DAG.getMachineFunction();
3623 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3624 DAG.getSubtarget().getRegisterInfo());
3625 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3626 int ReturnAddrIndex = FuncInfo->getRAIndex();
3628 if (ReturnAddrIndex == 0) {
3629 // Set up a frame object for the return address.
3630 unsigned SlotSize = RegInfo->getSlotSize();
3631 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3634 FuncInfo->setRAIndex(ReturnAddrIndex);
3637 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3640 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3641 bool hasSymbolicDisplacement) {
3642 // Offset should fit into 32 bit immediate field.
3643 if (!isInt<32>(Offset))
3646 // If we don't have a symbolic displacement - we don't have any extra
3648 if (!hasSymbolicDisplacement)
3651 // FIXME: Some tweaks might be needed for medium code model.
3652 if (M != CodeModel::Small && M != CodeModel::Kernel)
3655 // For small code model we assume that latest object is 16MB before end of 31
3656 // bits boundary. We may also accept pretty large negative constants knowing
3657 // that all objects are in the positive half of address space.
3658 if (M == CodeModel::Small && Offset < 16*1024*1024)
3661 // For kernel code model we know that all object resist in the negative half
3662 // of 32bits address space. We may not accept negative offsets, since they may
3663 // be just off and we may accept pretty large positive ones.
3664 if (M == CodeModel::Kernel && Offset > 0)
3670 /// isCalleePop - Determines whether the callee is required to pop its
3671 /// own arguments. Callee pop is necessary to support tail calls.
3672 bool X86::isCalleePop(CallingConv::ID CallingConv,
3673 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3674 switch (CallingConv) {
3677 case CallingConv::X86_StdCall:
3678 case CallingConv::X86_FastCall:
3679 case CallingConv::X86_ThisCall:
3681 case CallingConv::Fast:
3682 case CallingConv::GHC:
3683 case CallingConv::HiPE:
3690 /// \brief Return true if the condition is an unsigned comparison operation.
3691 static bool isX86CCUnsigned(unsigned X86CC) {
3693 default: llvm_unreachable("Invalid integer condition!");
3694 case X86::COND_E: return true;
3695 case X86::COND_G: return false;
3696 case X86::COND_GE: return false;
3697 case X86::COND_L: return false;
3698 case X86::COND_LE: return false;
3699 case X86::COND_NE: return true;
3700 case X86::COND_B: return true;
3701 case X86::COND_A: return true;
3702 case X86::COND_BE: return true;
3703 case X86::COND_AE: return true;
3705 llvm_unreachable("covered switch fell through?!");
3708 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3709 /// specific condition code, returning the condition code and the LHS/RHS of the
3710 /// comparison to make.
3711 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3712 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3714 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3715 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3716 // X > -1 -> X == 0, jump !sign.
3717 RHS = DAG.getConstant(0, RHS.getValueType());
3718 return X86::COND_NS;
3720 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3721 // X < 0 -> X == 0, jump on sign.
3724 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3726 RHS = DAG.getConstant(0, RHS.getValueType());
3727 return X86::COND_LE;
3731 switch (SetCCOpcode) {
3732 default: llvm_unreachable("Invalid integer condition!");
3733 case ISD::SETEQ: return X86::COND_E;
3734 case ISD::SETGT: return X86::COND_G;
3735 case ISD::SETGE: return X86::COND_GE;
3736 case ISD::SETLT: return X86::COND_L;
3737 case ISD::SETLE: return X86::COND_LE;
3738 case ISD::SETNE: return X86::COND_NE;
3739 case ISD::SETULT: return X86::COND_B;
3740 case ISD::SETUGT: return X86::COND_A;
3741 case ISD::SETULE: return X86::COND_BE;
3742 case ISD::SETUGE: return X86::COND_AE;
3746 // First determine if it is required or is profitable to flip the operands.
3748 // If LHS is a foldable load, but RHS is not, flip the condition.
3749 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3750 !ISD::isNON_EXTLoad(RHS.getNode())) {
3751 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3752 std::swap(LHS, RHS);
3755 switch (SetCCOpcode) {
3761 std::swap(LHS, RHS);
3765 // On a floating point condition, the flags are set as follows:
3767 // 0 | 0 | 0 | X > Y
3768 // 0 | 0 | 1 | X < Y
3769 // 1 | 0 | 0 | X == Y
3770 // 1 | 1 | 1 | unordered
3771 switch (SetCCOpcode) {
3772 default: llvm_unreachable("Condcode should be pre-legalized away");
3774 case ISD::SETEQ: return X86::COND_E;
3775 case ISD::SETOLT: // flipped
3777 case ISD::SETGT: return X86::COND_A;
3778 case ISD::SETOLE: // flipped
3780 case ISD::SETGE: return X86::COND_AE;
3781 case ISD::SETUGT: // flipped
3783 case ISD::SETLT: return X86::COND_B;
3784 case ISD::SETUGE: // flipped
3786 case ISD::SETLE: return X86::COND_BE;
3788 case ISD::SETNE: return X86::COND_NE;
3789 case ISD::SETUO: return X86::COND_P;
3790 case ISD::SETO: return X86::COND_NP;
3792 case ISD::SETUNE: return X86::COND_INVALID;
3796 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3797 /// code. Current x86 isa includes the following FP cmov instructions:
3798 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3799 static bool hasFPCMov(unsigned X86CC) {
3815 /// isFPImmLegal - Returns true if the target can instruction select the
3816 /// specified FP immediate natively. If false, the legalizer will
3817 /// materialize the FP immediate as a load from a constant pool.
3818 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3819 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3820 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3826 /// \brief Returns true if it is beneficial to convert a load of a constant
3827 /// to just the constant itself.
3828 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3830 assert(Ty->isIntegerTy());
3832 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3833 if (BitSize == 0 || BitSize > 64)
3838 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3839 /// the specified range (L, H].
3840 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3841 return (Val < 0) || (Val >= Low && Val < Hi);
3844 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3845 /// specified value.
3846 static bool isUndefOrEqual(int Val, int CmpVal) {
3847 return (Val < 0 || Val == CmpVal);
3850 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3851 /// from position Pos and ending in Pos+Size, falls within the specified
3852 /// sequential range (L, L+Pos]. or is undef.
3853 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3854 unsigned Pos, unsigned Size, int Low) {
3855 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3856 if (!isUndefOrEqual(Mask[i], Low))
3861 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3862 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3863 /// operand - by default will match for first operand.
3864 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3865 bool TestSecondOperand = false) {
3866 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3867 VT != MVT::v2f64 && VT != MVT::v2i64)
3870 unsigned NumElems = VT.getVectorNumElements();
3871 unsigned Lo = TestSecondOperand ? NumElems : 0;
3872 unsigned Hi = Lo + NumElems;
3874 for (unsigned i = 0; i < NumElems; ++i)
3875 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3881 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3882 /// is suitable for input to PSHUFHW.
3883 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3884 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3887 // Lower quadword copied in order or undef.
3888 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3891 // Upper quadword shuffled.
3892 for (unsigned i = 4; i != 8; ++i)
3893 if (!isUndefOrInRange(Mask[i], 4, 8))
3896 if (VT == MVT::v16i16) {
3897 // Lower quadword copied in order or undef.
3898 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3901 // Upper quadword shuffled.
3902 for (unsigned i = 12; i != 16; ++i)
3903 if (!isUndefOrInRange(Mask[i], 12, 16))
3910 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3911 /// is suitable for input to PSHUFLW.
3912 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3913 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3916 // Upper quadword copied in order.
3917 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3920 // Lower quadword shuffled.
3921 for (unsigned i = 0; i != 4; ++i)
3922 if (!isUndefOrInRange(Mask[i], 0, 4))
3925 if (VT == MVT::v16i16) {
3926 // Upper quadword copied in order.
3927 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3930 // Lower quadword shuffled.
3931 for (unsigned i = 8; i != 12; ++i)
3932 if (!isUndefOrInRange(Mask[i], 8, 12))
3939 /// \brief Return true if the mask specifies a shuffle of elements that is
3940 /// suitable for input to intralane (palignr) or interlane (valign) vector
3942 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3943 unsigned NumElts = VT.getVectorNumElements();
3944 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3945 unsigned NumLaneElts = NumElts/NumLanes;
3947 // Do not handle 64-bit element shuffles with palignr.
3948 if (NumLaneElts == 2)
3951 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3953 for (i = 0; i != NumLaneElts; ++i) {
3958 // Lane is all undef, go to next lane
3959 if (i == NumLaneElts)
3962 int Start = Mask[i+l];
3964 // Make sure its in this lane in one of the sources
3965 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3966 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3969 // If not lane 0, then we must match lane 0
3970 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3973 // Correct second source to be contiguous with first source
3974 if (Start >= (int)NumElts)
3975 Start -= NumElts - NumLaneElts;
3977 // Make sure we're shifting in the right direction.
3978 if (Start <= (int)(i+l))
3983 // Check the rest of the elements to see if they are consecutive.
3984 for (++i; i != NumLaneElts; ++i) {
3985 int Idx = Mask[i+l];
3987 // Make sure its in this lane
3988 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3989 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3992 // If not lane 0, then we must match lane 0
3993 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3996 if (Idx >= (int)NumElts)
3997 Idx -= NumElts - NumLaneElts;
3999 if (!isUndefOrEqual(Idx, Start+i))
4008 /// \brief Return true if the node specifies a shuffle of elements that is
4009 /// suitable for input to PALIGNR.
4010 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4011 const X86Subtarget *Subtarget) {
4012 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4013 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4014 VT.is512BitVector())
4015 // FIXME: Add AVX512BW.
4018 return isAlignrMask(Mask, VT, false);
4021 /// \brief Return true if the node specifies a shuffle of elements that is
4022 /// suitable for input to VALIGN.
4023 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4024 const X86Subtarget *Subtarget) {
4025 // FIXME: Add AVX512VL.
4026 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4028 return isAlignrMask(Mask, VT, true);
4031 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4032 /// the two vector operands have swapped position.
4033 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4034 unsigned NumElems) {
4035 for (unsigned i = 0; i != NumElems; ++i) {
4039 else if (idx < (int)NumElems)
4040 Mask[i] = idx + NumElems;
4042 Mask[i] = idx - NumElems;
4046 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4047 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4048 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4049 /// reverse of what x86 shuffles want.
4050 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4052 unsigned NumElems = VT.getVectorNumElements();
4053 unsigned NumLanes = VT.getSizeInBits()/128;
4054 unsigned NumLaneElems = NumElems/NumLanes;
4056 if (NumLaneElems != 2 && NumLaneElems != 4)
4059 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4060 bool symetricMaskRequired =
4061 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4063 // VSHUFPSY divides the resulting vector into 4 chunks.
4064 // The sources are also splitted into 4 chunks, and each destination
4065 // chunk must come from a different source chunk.
4067 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4068 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4070 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4071 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4073 // VSHUFPDY divides the resulting vector into 4 chunks.
4074 // The sources are also splitted into 4 chunks, and each destination
4075 // chunk must come from a different source chunk.
4077 // SRC1 => X3 X2 X1 X0
4078 // SRC2 => Y3 Y2 Y1 Y0
4080 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4082 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4083 unsigned HalfLaneElems = NumLaneElems/2;
4084 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4085 for (unsigned i = 0; i != NumLaneElems; ++i) {
4086 int Idx = Mask[i+l];
4087 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4088 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4090 // For VSHUFPSY, the mask of the second half must be the same as the
4091 // first but with the appropriate offsets. This works in the same way as
4092 // VPERMILPS works with masks.
4093 if (!symetricMaskRequired || Idx < 0)
4095 if (MaskVal[i] < 0) {
4096 MaskVal[i] = Idx - l;
4099 if ((signed)(Idx - l) != MaskVal[i])
4107 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4108 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4109 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4110 if (!VT.is128BitVector())
4113 unsigned NumElems = VT.getVectorNumElements();
4118 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4119 return isUndefOrEqual(Mask[0], 6) &&
4120 isUndefOrEqual(Mask[1], 7) &&
4121 isUndefOrEqual(Mask[2], 2) &&
4122 isUndefOrEqual(Mask[3], 3);
4125 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4126 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4128 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4129 if (!VT.is128BitVector())
4132 unsigned NumElems = VT.getVectorNumElements();
4137 return isUndefOrEqual(Mask[0], 2) &&
4138 isUndefOrEqual(Mask[1], 3) &&
4139 isUndefOrEqual(Mask[2], 2) &&
4140 isUndefOrEqual(Mask[3], 3);
4143 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4144 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4145 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4146 if (!VT.is128BitVector())
4149 unsigned NumElems = VT.getVectorNumElements();
4151 if (NumElems != 2 && NumElems != 4)
4154 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4155 if (!isUndefOrEqual(Mask[i], i + NumElems))
4158 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4159 if (!isUndefOrEqual(Mask[i], i))
4165 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4166 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4167 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4168 if (!VT.is128BitVector())
4171 unsigned NumElems = VT.getVectorNumElements();
4173 if (NumElems != 2 && NumElems != 4)
4176 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4177 if (!isUndefOrEqual(Mask[i], i))
4180 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4181 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4187 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4188 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4189 /// i. e: If all but one element come from the same vector.
4190 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4191 // TODO: Deal with AVX's VINSERTPS
4192 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4195 unsigned CorrectPosV1 = 0;
4196 unsigned CorrectPosV2 = 0;
4197 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4198 if (Mask[i] == -1) {
4206 else if (Mask[i] == i + 4)
4210 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4211 // We have 3 elements (undefs count as elements from any vector) from one
4212 // vector, and one from another.
4219 // Some special combinations that can be optimized.
4222 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4223 SelectionDAG &DAG) {
4224 MVT VT = SVOp->getSimpleValueType(0);
4227 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4230 ArrayRef<int> Mask = SVOp->getMask();
4232 // These are the special masks that may be optimized.
4233 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4234 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4235 bool MatchEvenMask = true;
4236 bool MatchOddMask = true;
4237 for (int i=0; i<8; ++i) {
4238 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4239 MatchEvenMask = false;
4240 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4241 MatchOddMask = false;
4244 if (!MatchEvenMask && !MatchOddMask)
4247 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4249 SDValue Op0 = SVOp->getOperand(0);
4250 SDValue Op1 = SVOp->getOperand(1);
4252 if (MatchEvenMask) {
4253 // Shift the second operand right to 32 bits.
4254 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4255 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4257 // Shift the first operand left to 32 bits.
4258 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4259 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4261 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4262 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4265 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4266 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4267 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4268 bool HasInt256, bool V2IsSplat = false) {
4270 assert(VT.getSizeInBits() >= 128 &&
4271 "Unsupported vector type for unpckl");
4273 unsigned NumElts = VT.getVectorNumElements();
4274 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4275 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4278 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4279 "Unsupported vector type for unpckh");
4281 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4282 unsigned NumLanes = VT.getSizeInBits()/128;
4283 unsigned NumLaneElts = NumElts/NumLanes;
4285 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4286 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4287 int BitI = Mask[l+i];
4288 int BitI1 = Mask[l+i+1];
4289 if (!isUndefOrEqual(BitI, j))
4292 if (!isUndefOrEqual(BitI1, NumElts))
4295 if (!isUndefOrEqual(BitI1, j + NumElts))
4304 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4305 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4306 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4307 bool HasInt256, bool V2IsSplat = false) {
4308 assert(VT.getSizeInBits() >= 128 &&
4309 "Unsupported vector type for unpckh");
4311 unsigned NumElts = VT.getVectorNumElements();
4312 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4313 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4316 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4317 "Unsupported vector type for unpckh");
4319 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4320 unsigned NumLanes = VT.getSizeInBits()/128;
4321 unsigned NumLaneElts = NumElts/NumLanes;
4323 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4324 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4325 int BitI = Mask[l+i];
4326 int BitI1 = Mask[l+i+1];
4327 if (!isUndefOrEqual(BitI, j))
4330 if (isUndefOrEqual(BitI1, NumElts))
4333 if (!isUndefOrEqual(BitI1, j+NumElts))
4341 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4342 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4344 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4345 unsigned NumElts = VT.getVectorNumElements();
4346 bool Is256BitVec = VT.is256BitVector();
4348 if (VT.is512BitVector())
4350 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4351 "Unsupported vector type for unpckh");
4353 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4354 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4357 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4358 // FIXME: Need a better way to get rid of this, there's no latency difference
4359 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4360 // the former later. We should also remove the "_undef" special mask.
4361 if (NumElts == 4 && Is256BitVec)
4364 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4365 // independently on 128-bit lanes.
4366 unsigned NumLanes = VT.getSizeInBits()/128;
4367 unsigned NumLaneElts = NumElts/NumLanes;
4369 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4370 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4371 int BitI = Mask[l+i];
4372 int BitI1 = Mask[l+i+1];
4374 if (!isUndefOrEqual(BitI, j))
4376 if (!isUndefOrEqual(BitI1, j))
4384 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4385 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4387 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4388 unsigned NumElts = VT.getVectorNumElements();
4390 if (VT.is512BitVector())
4393 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4394 "Unsupported vector type for unpckh");
4396 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4397 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4400 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4401 // independently on 128-bit lanes.
4402 unsigned NumLanes = VT.getSizeInBits()/128;
4403 unsigned NumLaneElts = NumElts/NumLanes;
4405 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4406 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4407 int BitI = Mask[l+i];
4408 int BitI1 = Mask[l+i+1];
4409 if (!isUndefOrEqual(BitI, j))
4411 if (!isUndefOrEqual(BitI1, j))
4418 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4419 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4420 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4421 if (!VT.is512BitVector())
4424 unsigned NumElts = VT.getVectorNumElements();
4425 unsigned HalfSize = NumElts/2;
4426 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4427 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4432 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4433 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4441 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4442 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4443 /// MOVSD, and MOVD, i.e. setting the lowest element.
4444 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4445 if (VT.getVectorElementType().getSizeInBits() < 32)
4447 if (!VT.is128BitVector())
4450 unsigned NumElts = VT.getVectorNumElements();
4452 if (!isUndefOrEqual(Mask[0], NumElts))
4455 for (unsigned i = 1; i != NumElts; ++i)
4456 if (!isUndefOrEqual(Mask[i], i))
4462 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4463 /// as permutations between 128-bit chunks or halves. As an example: this
4465 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4466 /// The first half comes from the second half of V1 and the second half from the
4467 /// the second half of V2.
4468 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4469 if (!HasFp256 || !VT.is256BitVector())
4472 // The shuffle result is divided into half A and half B. In total the two
4473 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4474 // B must come from C, D, E or F.
4475 unsigned HalfSize = VT.getVectorNumElements()/2;
4476 bool MatchA = false, MatchB = false;
4478 // Check if A comes from one of C, D, E, F.
4479 for (unsigned Half = 0; Half != 4; ++Half) {
4480 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4486 // Check if B comes from one of C, D, E, F.
4487 for (unsigned Half = 0; Half != 4; ++Half) {
4488 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4494 return MatchA && MatchB;
4497 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4498 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4499 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4500 MVT VT = SVOp->getSimpleValueType(0);
4502 unsigned HalfSize = VT.getVectorNumElements()/2;
4504 unsigned FstHalf = 0, SndHalf = 0;
4505 for (unsigned i = 0; i < HalfSize; ++i) {
4506 if (SVOp->getMaskElt(i) > 0) {
4507 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4511 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4512 if (SVOp->getMaskElt(i) > 0) {
4513 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4518 return (FstHalf | (SndHalf << 4));
4521 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4522 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4523 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4527 unsigned NumElts = VT.getVectorNumElements();
4529 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4530 for (unsigned i = 0; i != NumElts; ++i) {
4533 Imm8 |= Mask[i] << (i*2);
4538 unsigned LaneSize = 4;
4539 SmallVector<int, 4> MaskVal(LaneSize, -1);
4541 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4542 for (unsigned i = 0; i != LaneSize; ++i) {
4543 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4547 if (MaskVal[i] < 0) {
4548 MaskVal[i] = Mask[i+l] - l;
4549 Imm8 |= MaskVal[i] << (i*2);
4552 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4559 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4560 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4561 /// Note that VPERMIL mask matching is different depending whether theunderlying
4562 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4563 /// to the same elements of the low, but to the higher half of the source.
4564 /// In VPERMILPD the two lanes could be shuffled independently of each other
4565 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4566 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4567 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4568 if (VT.getSizeInBits() < 256 || EltSize < 32)
4570 bool symetricMaskRequired = (EltSize == 32);
4571 unsigned NumElts = VT.getVectorNumElements();
4573 unsigned NumLanes = VT.getSizeInBits()/128;
4574 unsigned LaneSize = NumElts/NumLanes;
4575 // 2 or 4 elements in one lane
4577 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4578 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4579 for (unsigned i = 0; i != LaneSize; ++i) {
4580 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4582 if (symetricMaskRequired) {
4583 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4584 ExpectedMaskVal[i] = Mask[i+l] - l;
4587 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4595 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4596 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4597 /// element of vector 2 and the other elements to come from vector 1 in order.
4598 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4599 bool V2IsSplat = false, bool V2IsUndef = false) {
4600 if (!VT.is128BitVector())
4603 unsigned NumOps = VT.getVectorNumElements();
4604 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4607 if (!isUndefOrEqual(Mask[0], 0))
4610 for (unsigned i = 1; i != NumOps; ++i)
4611 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4612 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4613 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4619 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4620 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4621 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4622 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4623 const X86Subtarget *Subtarget) {
4624 if (!Subtarget->hasSSE3())
4627 unsigned NumElems = VT.getVectorNumElements();
4629 if ((VT.is128BitVector() && NumElems != 4) ||
4630 (VT.is256BitVector() && NumElems != 8) ||
4631 (VT.is512BitVector() && NumElems != 16))
4634 // "i+1" is the value the indexed mask element must have
4635 for (unsigned i = 0; i != NumElems; i += 2)
4636 if (!isUndefOrEqual(Mask[i], i+1) ||
4637 !isUndefOrEqual(Mask[i+1], i+1))
4643 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4644 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4645 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4646 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4647 const X86Subtarget *Subtarget) {
4648 if (!Subtarget->hasSSE3())
4651 unsigned NumElems = VT.getVectorNumElements();
4653 if ((VT.is128BitVector() && NumElems != 4) ||
4654 (VT.is256BitVector() && NumElems != 8) ||
4655 (VT.is512BitVector() && NumElems != 16))
4658 // "i" is the value the indexed mask element must have
4659 for (unsigned i = 0; i != NumElems; i += 2)
4660 if (!isUndefOrEqual(Mask[i], i) ||
4661 !isUndefOrEqual(Mask[i+1], i))
4667 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4668 /// specifies a shuffle of elements that is suitable for input to 256-bit
4669 /// version of MOVDDUP.
4670 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4671 if (!HasFp256 || !VT.is256BitVector())
4674 unsigned NumElts = VT.getVectorNumElements();
4678 for (unsigned i = 0; i != NumElts/2; ++i)
4679 if (!isUndefOrEqual(Mask[i], 0))
4681 for (unsigned i = NumElts/2; i != NumElts; ++i)
4682 if (!isUndefOrEqual(Mask[i], NumElts/2))
4687 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4688 /// specifies a shuffle of elements that is suitable for input to 128-bit
4689 /// version of MOVDDUP.
4690 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4691 if (!VT.is128BitVector())
4694 unsigned e = VT.getVectorNumElements() / 2;
4695 for (unsigned i = 0; i != e; ++i)
4696 if (!isUndefOrEqual(Mask[i], i))
4698 for (unsigned i = 0; i != e; ++i)
4699 if (!isUndefOrEqual(Mask[e+i], i))
4704 /// isVEXTRACTIndex - Return true if the specified
4705 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4706 /// suitable for instruction that extract 128 or 256 bit vectors
4707 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4708 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4709 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4712 // The index should be aligned on a vecWidth-bit boundary.
4714 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4716 MVT VT = N->getSimpleValueType(0);
4717 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4718 bool Result = (Index * ElSize) % vecWidth == 0;
4723 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4724 /// operand specifies a subvector insert that is suitable for input to
4725 /// insertion of 128 or 256-bit subvectors
4726 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4727 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4728 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4730 // The index should be aligned on a vecWidth-bit boundary.
4732 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4734 MVT VT = N->getSimpleValueType(0);
4735 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4736 bool Result = (Index * ElSize) % vecWidth == 0;
4741 bool X86::isVINSERT128Index(SDNode *N) {
4742 return isVINSERTIndex(N, 128);
4745 bool X86::isVINSERT256Index(SDNode *N) {
4746 return isVINSERTIndex(N, 256);
4749 bool X86::isVEXTRACT128Index(SDNode *N) {
4750 return isVEXTRACTIndex(N, 128);
4753 bool X86::isVEXTRACT256Index(SDNode *N) {
4754 return isVEXTRACTIndex(N, 256);
4757 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4758 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4759 /// Handles 128-bit and 256-bit.
4760 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4761 MVT VT = N->getSimpleValueType(0);
4763 assert((VT.getSizeInBits() >= 128) &&
4764 "Unsupported vector type for PSHUF/SHUFP");
4766 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4767 // independently on 128-bit lanes.
4768 unsigned NumElts = VT.getVectorNumElements();
4769 unsigned NumLanes = VT.getSizeInBits()/128;
4770 unsigned NumLaneElts = NumElts/NumLanes;
4772 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4773 "Only supports 2, 4 or 8 elements per lane");
4775 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4777 for (unsigned i = 0; i != NumElts; ++i) {
4778 int Elt = N->getMaskElt(i);
4779 if (Elt < 0) continue;
4780 Elt &= NumLaneElts - 1;
4781 unsigned ShAmt = (i << Shift) % 8;
4782 Mask |= Elt << ShAmt;
4788 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4789 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4790 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4791 MVT VT = N->getSimpleValueType(0);
4793 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4794 "Unsupported vector type for PSHUFHW");
4796 unsigned NumElts = VT.getVectorNumElements();
4799 for (unsigned l = 0; l != NumElts; l += 8) {
4800 // 8 nodes per lane, but we only care about the last 4.
4801 for (unsigned i = 0; i < 4; ++i) {
4802 int Elt = N->getMaskElt(l+i+4);
4803 if (Elt < 0) continue;
4804 Elt &= 0x3; // only 2-bits.
4805 Mask |= Elt << (i * 2);
4812 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4813 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4814 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4815 MVT VT = N->getSimpleValueType(0);
4817 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4818 "Unsupported vector type for PSHUFHW");
4820 unsigned NumElts = VT.getVectorNumElements();
4823 for (unsigned l = 0; l != NumElts; l += 8) {
4824 // 8 nodes per lane, but we only care about the first 4.
4825 for (unsigned i = 0; i < 4; ++i) {
4826 int Elt = N->getMaskElt(l+i);
4827 if (Elt < 0) continue;
4828 Elt &= 0x3; // only 2-bits
4829 Mask |= Elt << (i * 2);
4836 /// \brief Return the appropriate immediate to shuffle the specified
4837 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4838 /// VALIGN (if Interlane is true) instructions.
4839 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4841 MVT VT = SVOp->getSimpleValueType(0);
4842 unsigned EltSize = InterLane ? 1 :
4843 VT.getVectorElementType().getSizeInBits() >> 3;
4845 unsigned NumElts = VT.getVectorNumElements();
4846 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4847 unsigned NumLaneElts = NumElts/NumLanes;
4851 for (i = 0; i != NumElts; ++i) {
4852 Val = SVOp->getMaskElt(i);
4856 if (Val >= (int)NumElts)
4857 Val -= NumElts - NumLaneElts;
4859 assert(Val - i > 0 && "PALIGNR imm should be positive");
4860 return (Val - i) * EltSize;
4863 /// \brief Return the appropriate immediate to shuffle the specified
4864 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4865 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4866 return getShuffleAlignrImmediate(SVOp, false);
4869 /// \brief Return the appropriate immediate to shuffle the specified
4870 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4871 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4872 return getShuffleAlignrImmediate(SVOp, true);
4876 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4877 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4878 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4879 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4882 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4884 MVT VecVT = N->getOperand(0).getSimpleValueType();
4885 MVT ElVT = VecVT.getVectorElementType();
4887 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4888 return Index / NumElemsPerChunk;
4891 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4892 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4893 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4894 llvm_unreachable("Illegal insert subvector for VINSERT");
4897 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4899 MVT VecVT = N->getSimpleValueType(0);
4900 MVT ElVT = VecVT.getVectorElementType();
4902 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4903 return Index / NumElemsPerChunk;
4906 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4907 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4908 /// and VINSERTI128 instructions.
4909 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4910 return getExtractVEXTRACTImmediate(N, 128);
4913 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4914 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4915 /// and VINSERTI64x4 instructions.
4916 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4917 return getExtractVEXTRACTImmediate(N, 256);
4920 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4921 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4922 /// and VINSERTI128 instructions.
4923 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4924 return getInsertVINSERTImmediate(N, 128);
4927 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4928 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4929 /// and VINSERTI64x4 instructions.
4930 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4931 return getInsertVINSERTImmediate(N, 256);
4934 /// isZero - Returns true if Elt is a constant integer zero
4935 static bool isZero(SDValue V) {
4936 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4937 return C && C->isNullValue();
4940 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4942 bool X86::isZeroNode(SDValue Elt) {
4945 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4946 return CFP->getValueAPF().isPosZero();
4950 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4951 /// match movhlps. The lower half elements should come from upper half of
4952 /// V1 (and in order), and the upper half elements should come from the upper
4953 /// half of V2 (and in order).
4954 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4955 if (!VT.is128BitVector())
4957 if (VT.getVectorNumElements() != 4)
4959 for (unsigned i = 0, e = 2; i != e; ++i)
4960 if (!isUndefOrEqual(Mask[i], i+2))
4962 for (unsigned i = 2; i != 4; ++i)
4963 if (!isUndefOrEqual(Mask[i], i+4))
4968 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4969 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4971 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4972 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4974 N = N->getOperand(0).getNode();
4975 if (!ISD::isNON_EXTLoad(N))
4978 *LD = cast<LoadSDNode>(N);
4982 // Test whether the given value is a vector value which will be legalized
4984 static bool WillBeConstantPoolLoad(SDNode *N) {
4985 if (N->getOpcode() != ISD::BUILD_VECTOR)
4988 // Check for any non-constant elements.
4989 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4990 switch (N->getOperand(i).getNode()->getOpcode()) {
4992 case ISD::ConstantFP:
4999 // Vectors of all-zeros and all-ones are materialized with special
5000 // instructions rather than being loaded.
5001 return !ISD::isBuildVectorAllZeros(N) &&
5002 !ISD::isBuildVectorAllOnes(N);
5005 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5006 /// match movlp{s|d}. The lower half elements should come from lower half of
5007 /// V1 (and in order), and the upper half elements should come from the upper
5008 /// half of V2 (and in order). And since V1 will become the source of the
5009 /// MOVLP, it must be either a vector load or a scalar load to vector.
5010 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5011 ArrayRef<int> Mask, MVT VT) {
5012 if (!VT.is128BitVector())
5015 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5017 // Is V2 is a vector load, don't do this transformation. We will try to use
5018 // load folding shufps op.
5019 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5022 unsigned NumElems = VT.getVectorNumElements();
5024 if (NumElems != 2 && NumElems != 4)
5026 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5027 if (!isUndefOrEqual(Mask[i], i))
5029 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5030 if (!isUndefOrEqual(Mask[i], i+NumElems))
5035 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5036 /// to an zero vector.
5037 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5038 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5039 SDValue V1 = N->getOperand(0);
5040 SDValue V2 = N->getOperand(1);
5041 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5042 for (unsigned i = 0; i != NumElems; ++i) {
5043 int Idx = N->getMaskElt(i);
5044 if (Idx >= (int)NumElems) {
5045 unsigned Opc = V2.getOpcode();
5046 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5048 if (Opc != ISD::BUILD_VECTOR ||
5049 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5051 } else if (Idx >= 0) {
5052 unsigned Opc = V1.getOpcode();
5053 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5055 if (Opc != ISD::BUILD_VECTOR ||
5056 !X86::isZeroNode(V1.getOperand(Idx)))
5063 /// getZeroVector - Returns a vector of specified type with all zero elements.
5065 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5066 SelectionDAG &DAG, SDLoc dl) {
5067 assert(VT.isVector() && "Expected a vector type");
5069 // Always build SSE zero vectors as <4 x i32> bitcasted
5070 // to their dest type. This ensures they get CSE'd.
5072 if (VT.is128BitVector()) { // SSE
5073 if (Subtarget->hasSSE2()) { // SSE2
5074 SDValue Cst = DAG.getConstant(0, MVT::i32);
5075 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5077 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5080 } else if (VT.is256BitVector()) { // AVX
5081 if (Subtarget->hasInt256()) { // AVX2
5082 SDValue Cst = DAG.getConstant(0, MVT::i32);
5083 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5086 // 256-bit logic and arithmetic instructions in AVX are all
5087 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5088 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5089 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5092 } else if (VT.is512BitVector()) { // AVX-512
5093 SDValue Cst = DAG.getConstant(0, MVT::i32);
5094 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5095 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5096 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5097 } else if (VT.getScalarType() == MVT::i1) {
5098 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5099 SDValue Cst = DAG.getConstant(0, MVT::i1);
5100 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5101 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5103 llvm_unreachable("Unexpected vector type");
5105 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5108 /// getOnesVector - Returns a vector of specified type with all bits set.
5109 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5110 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5111 /// Then bitcast to their original type, ensuring they get CSE'd.
5112 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5114 assert(VT.isVector() && "Expected a vector type");
5116 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5118 if (VT.is256BitVector()) {
5119 if (HasInt256) { // AVX2
5120 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5123 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5124 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5126 } else if (VT.is128BitVector()) {
5127 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5129 llvm_unreachable("Unexpected vector type");
5131 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5134 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5135 /// that point to V2 points to its first element.
5136 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5137 for (unsigned i = 0; i != NumElems; ++i) {
5138 if (Mask[i] > (int)NumElems) {
5144 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5145 /// operation of specified width.
5146 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5148 unsigned NumElems = VT.getVectorNumElements();
5149 SmallVector<int, 8> Mask;
5150 Mask.push_back(NumElems);
5151 for (unsigned i = 1; i != NumElems; ++i)
5153 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5156 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5157 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5159 unsigned NumElems = VT.getVectorNumElements();
5160 SmallVector<int, 8> Mask;
5161 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5163 Mask.push_back(i + NumElems);
5165 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5168 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5169 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5171 unsigned NumElems = VT.getVectorNumElements();
5172 SmallVector<int, 8> Mask;
5173 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5174 Mask.push_back(i + Half);
5175 Mask.push_back(i + NumElems + Half);
5177 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5180 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5181 // a generic shuffle instruction because the target has no such instructions.
5182 // Generate shuffles which repeat i16 and i8 several times until they can be
5183 // represented by v4f32 and then be manipulated by target suported shuffles.
5184 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5185 MVT VT = V.getSimpleValueType();
5186 int NumElems = VT.getVectorNumElements();
5189 while (NumElems > 4) {
5190 if (EltNo < NumElems/2) {
5191 V = getUnpackl(DAG, dl, VT, V, V);
5193 V = getUnpackh(DAG, dl, VT, V, V);
5194 EltNo -= NumElems/2;
5201 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5202 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5203 MVT VT = V.getSimpleValueType();
5206 if (VT.is128BitVector()) {
5207 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5208 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5209 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5211 } else if (VT.is256BitVector()) {
5212 // To use VPERMILPS to splat scalars, the second half of indicies must
5213 // refer to the higher part, which is a duplication of the lower one,
5214 // because VPERMILPS can only handle in-lane permutations.
5215 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5216 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5218 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5219 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5222 llvm_unreachable("Vector size not supported");
5224 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5227 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5228 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5229 MVT SrcVT = SV->getSimpleValueType(0);
5230 SDValue V1 = SV->getOperand(0);
5233 int EltNo = SV->getSplatIndex();
5234 int NumElems = SrcVT.getVectorNumElements();
5235 bool Is256BitVec = SrcVT.is256BitVector();
5237 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5238 "Unknown how to promote splat for type");
5240 // Extract the 128-bit part containing the splat element and update
5241 // the splat element index when it refers to the higher register.
5243 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5244 if (EltNo >= NumElems/2)
5245 EltNo -= NumElems/2;
5248 // All i16 and i8 vector types can't be used directly by a generic shuffle
5249 // instruction because the target has no such instruction. Generate shuffles
5250 // which repeat i16 and i8 several times until they fit in i32, and then can
5251 // be manipulated by target suported shuffles.
5252 MVT EltVT = SrcVT.getVectorElementType();
5253 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5254 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5256 // Recreate the 256-bit vector and place the same 128-bit vector
5257 // into the low and high part. This is necessary because we want
5258 // to use VPERM* to shuffle the vectors
5260 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5263 return getLegalSplat(DAG, V1, EltNo);
5266 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5267 /// vector of zero or undef vector. This produces a shuffle where the low
5268 /// element of V2 is swizzled into the zero/undef vector, landing at element
5269 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5270 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5272 const X86Subtarget *Subtarget,
5273 SelectionDAG &DAG) {
5274 MVT VT = V2.getSimpleValueType();
5276 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5277 unsigned NumElems = VT.getVectorNumElements();
5278 SmallVector<int, 16> MaskVec;
5279 for (unsigned i = 0; i != NumElems; ++i)
5280 // If this is the insertion idx, put the low elt of V2 here.
5281 MaskVec.push_back(i == Idx ? NumElems : i);
5282 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5285 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5286 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5287 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5288 /// shuffles which use a single input multiple times, and in those cases it will
5289 /// adjust the mask to only have indices within that single input.
5290 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5291 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5292 unsigned NumElems = VT.getVectorNumElements();
5296 bool IsFakeUnary = false;
5297 switch(N->getOpcode()) {
5298 case X86ISD::BLENDI:
5299 ImmN = N->getOperand(N->getNumOperands()-1);
5300 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5303 ImmN = N->getOperand(N->getNumOperands()-1);
5304 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5305 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5307 case X86ISD::UNPCKH:
5308 DecodeUNPCKHMask(VT, Mask);
5309 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5311 case X86ISD::UNPCKL:
5312 DecodeUNPCKLMask(VT, Mask);
5313 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5315 case X86ISD::MOVHLPS:
5316 DecodeMOVHLPSMask(NumElems, Mask);
5317 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5319 case X86ISD::MOVLHPS:
5320 DecodeMOVLHPSMask(NumElems, Mask);
5321 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5323 case X86ISD::PALIGNR:
5324 ImmN = N->getOperand(N->getNumOperands()-1);
5325 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFD:
5328 case X86ISD::VPERMILPI:
5329 ImmN = N->getOperand(N->getNumOperands()-1);
5330 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5333 case X86ISD::PSHUFHW:
5334 ImmN = N->getOperand(N->getNumOperands()-1);
5335 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5338 case X86ISD::PSHUFLW:
5339 ImmN = N->getOperand(N->getNumOperands()-1);
5340 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5343 case X86ISD::PSHUFB: {
5345 SDValue MaskNode = N->getOperand(1);
5346 while (MaskNode->getOpcode() == ISD::BITCAST)
5347 MaskNode = MaskNode->getOperand(0);
5349 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5350 // If we have a build-vector, then things are easy.
5351 EVT VT = MaskNode.getValueType();
5352 assert(VT.isVector() &&
5353 "Can't produce a non-vector with a build_vector!");
5354 if (!VT.isInteger())
5357 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5359 SmallVector<uint64_t, 32> RawMask;
5360 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5361 SDValue Op = MaskNode->getOperand(i);
5362 if (Op->getOpcode() == ISD::UNDEF) {
5363 RawMask.push_back((uint64_t)SM_SentinelUndef);
5366 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5369 APInt MaskElement = CN->getAPIntValue();
5371 // We now have to decode the element which could be any integer size and
5372 // extract each byte of it.
5373 for (int j = 0; j < NumBytesPerElement; ++j) {
5374 // Note that this is x86 and so always little endian: the low byte is
5375 // the first byte of the mask.
5376 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5377 MaskElement = MaskElement.lshr(8);
5380 DecodePSHUFBMask(RawMask, Mask);
5384 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5388 SDValue Ptr = MaskLoad->getBasePtr();
5389 if (Ptr->getOpcode() == X86ISD::Wrapper)
5390 Ptr = Ptr->getOperand(0);
5392 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5393 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5396 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5397 // FIXME: Support AVX-512 here.
5398 Type *Ty = C->getType();
5399 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5400 Ty->getVectorNumElements() != 32))
5403 DecodePSHUFBMask(C, Mask);
5409 case X86ISD::VPERMI:
5410 ImmN = N->getOperand(N->getNumOperands()-1);
5411 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5415 case X86ISD::MOVSD: {
5416 // The index 0 always comes from the first element of the second source,
5417 // this is why MOVSS and MOVSD are used in the first place. The other
5418 // elements come from the other positions of the first source vector
5419 Mask.push_back(NumElems);
5420 for (unsigned i = 1; i != NumElems; ++i) {
5425 case X86ISD::VPERM2X128:
5426 ImmN = N->getOperand(N->getNumOperands()-1);
5427 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5428 if (Mask.empty()) return false;
5430 case X86ISD::MOVSLDUP:
5431 DecodeMOVSLDUPMask(VT, Mask);
5433 case X86ISD::MOVSHDUP:
5434 DecodeMOVSHDUPMask(VT, Mask);
5436 case X86ISD::MOVDDUP:
5437 case X86ISD::MOVLHPD:
5438 case X86ISD::MOVLPD:
5439 case X86ISD::MOVLPS:
5440 // Not yet implemented
5442 default: llvm_unreachable("unknown target shuffle node");
5445 // If we have a fake unary shuffle, the shuffle mask is spread across two
5446 // inputs that are actually the same node. Re-map the mask to always point
5447 // into the first input.
5450 if (M >= (int)Mask.size())
5456 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5457 /// element of the result of the vector shuffle.
5458 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5461 return SDValue(); // Limit search depth.
5463 SDValue V = SDValue(N, 0);
5464 EVT VT = V.getValueType();
5465 unsigned Opcode = V.getOpcode();
5467 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5468 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5469 int Elt = SV->getMaskElt(Index);
5472 return DAG.getUNDEF(VT.getVectorElementType());
5474 unsigned NumElems = VT.getVectorNumElements();
5475 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5476 : SV->getOperand(1);
5477 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5480 // Recurse into target specific vector shuffles to find scalars.
5481 if (isTargetShuffle(Opcode)) {
5482 MVT ShufVT = V.getSimpleValueType();
5483 unsigned NumElems = ShufVT.getVectorNumElements();
5484 SmallVector<int, 16> ShuffleMask;
5487 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5490 int Elt = ShuffleMask[Index];
5492 return DAG.getUNDEF(ShufVT.getVectorElementType());
5494 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5496 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5500 // Actual nodes that may contain scalar elements
5501 if (Opcode == ISD::BITCAST) {
5502 V = V.getOperand(0);
5503 EVT SrcVT = V.getValueType();
5504 unsigned NumElems = VT.getVectorNumElements();
5506 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5510 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5511 return (Index == 0) ? V.getOperand(0)
5512 : DAG.getUNDEF(VT.getVectorElementType());
5514 if (V.getOpcode() == ISD::BUILD_VECTOR)
5515 return V.getOperand(Index);
5520 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5521 /// shuffle operation which come from a consecutively from a zero. The
5522 /// search can start in two different directions, from left or right.
5523 /// We count undefs as zeros until PreferredNum is reached.
5524 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5525 unsigned NumElems, bool ZerosFromLeft,
5527 unsigned PreferredNum = -1U) {
5528 unsigned NumZeros = 0;
5529 for (unsigned i = 0; i != NumElems; ++i) {
5530 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5531 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5535 if (X86::isZeroNode(Elt))
5537 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5538 NumZeros = std::min(NumZeros + 1, PreferredNum);
5546 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5547 /// correspond consecutively to elements from one of the vector operands,
5548 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5550 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5551 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5552 unsigned NumElems, unsigned &OpNum) {
5553 bool SeenV1 = false;
5554 bool SeenV2 = false;
5556 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5557 int Idx = SVOp->getMaskElt(i);
5558 // Ignore undef indicies
5562 if (Idx < (int)NumElems)
5567 // Only accept consecutive elements from the same vector
5568 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5572 OpNum = SeenV1 ? 0 : 1;
5576 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5577 /// logical left shift of a vector.
5578 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5579 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5581 SVOp->getSimpleValueType(0).getVectorNumElements();
5582 unsigned NumZeros = getNumOfConsecutiveZeros(
5583 SVOp, NumElems, false /* check zeros from right */, DAG,
5584 SVOp->getMaskElt(0));
5590 // Considering the elements in the mask that are not consecutive zeros,
5591 // check if they consecutively come from only one of the source vectors.
5593 // V1 = {X, A, B, C} 0
5595 // vector_shuffle V1, V2 <1, 2, 3, X>
5597 if (!isShuffleMaskConsecutive(SVOp,
5598 0, // Mask Start Index
5599 NumElems-NumZeros, // Mask End Index(exclusive)
5600 NumZeros, // Where to start looking in the src vector
5601 NumElems, // Number of elements in vector
5602 OpSrc)) // Which source operand ?
5607 ShVal = SVOp->getOperand(OpSrc);
5611 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5612 /// logical left shift of a vector.
5613 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5614 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5616 SVOp->getSimpleValueType(0).getVectorNumElements();
5617 unsigned NumZeros = getNumOfConsecutiveZeros(
5618 SVOp, NumElems, true /* check zeros from left */, DAG,
5619 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5625 // Considering the elements in the mask that are not consecutive zeros,
5626 // check if they consecutively come from only one of the source vectors.
5628 // 0 { A, B, X, X } = V2
5630 // vector_shuffle V1, V2 <X, X, 4, 5>
5632 if (!isShuffleMaskConsecutive(SVOp,
5633 NumZeros, // Mask Start Index
5634 NumElems, // Mask End Index(exclusive)
5635 0, // Where to start looking in the src vector
5636 NumElems, // Number of elements in vector
5637 OpSrc)) // Which source operand ?
5642 ShVal = SVOp->getOperand(OpSrc);
5646 /// isVectorShift - Returns true if the shuffle can be implemented as a
5647 /// logical left or right shift of a vector.
5648 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5649 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5650 // Although the logic below support any bitwidth size, there are no
5651 // shift instructions which handle more than 128-bit vectors.
5652 if (!SVOp->getSimpleValueType(0).is128BitVector())
5655 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5656 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5662 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5664 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5665 unsigned NumNonZero, unsigned NumZero,
5667 const X86Subtarget* Subtarget,
5668 const TargetLowering &TLI) {
5675 for (unsigned i = 0; i < 16; ++i) {
5676 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5677 if (ThisIsNonZero && First) {
5679 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5681 V = DAG.getUNDEF(MVT::v8i16);
5686 SDValue ThisElt, LastElt;
5687 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5688 if (LastIsNonZero) {
5689 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5690 MVT::i16, Op.getOperand(i-1));
5692 if (ThisIsNonZero) {
5693 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5694 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5695 ThisElt, DAG.getConstant(8, MVT::i8));
5697 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5701 if (ThisElt.getNode())
5702 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5703 DAG.getIntPtrConstant(i/2));
5707 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5710 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5712 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5713 unsigned NumNonZero, unsigned NumZero,
5715 const X86Subtarget* Subtarget,
5716 const TargetLowering &TLI) {
5723 for (unsigned i = 0; i < 8; ++i) {
5724 bool isNonZero = (NonZeros & (1 << i)) != 0;
5728 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5730 V = DAG.getUNDEF(MVT::v8i16);
5733 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5734 MVT::v8i16, V, Op.getOperand(i),
5735 DAG.getIntPtrConstant(i));
5742 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5743 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5744 unsigned NonZeros, unsigned NumNonZero,
5745 unsigned NumZero, SelectionDAG &DAG,
5746 const X86Subtarget *Subtarget,
5747 const TargetLowering &TLI) {
5748 // We know there's at least one non-zero element
5749 unsigned FirstNonZeroIdx = 0;
5750 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5751 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5752 X86::isZeroNode(FirstNonZero)) {
5754 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5757 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5758 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5761 SDValue V = FirstNonZero.getOperand(0);
5762 MVT VVT = V.getSimpleValueType();
5763 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5766 unsigned FirstNonZeroDst =
5767 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5768 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5769 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5770 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5772 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5773 SDValue Elem = Op.getOperand(Idx);
5774 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5777 // TODO: What else can be here? Deal with it.
5778 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5781 // TODO: Some optimizations are still possible here
5782 // ex: Getting one element from a vector, and the rest from another.
5783 if (Elem.getOperand(0) != V)
5786 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5789 else if (IncorrectIdx == -1U) {
5793 // There was already one element with an incorrect index.
5794 // We can't optimize this case to an insertps.
5798 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5800 EVT VT = Op.getSimpleValueType();
5801 unsigned ElementMoveMask = 0;
5802 if (IncorrectIdx == -1U)
5803 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5805 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5807 SDValue InsertpsMask =
5808 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5809 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5815 /// getVShift - Return a vector logical shift node.
5817 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5818 unsigned NumBits, SelectionDAG &DAG,
5819 const TargetLowering &TLI, SDLoc dl) {
5820 assert(VT.is128BitVector() && "Unknown type for VShift");
5821 EVT ShVT = MVT::v2i64;
5822 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5823 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5824 return DAG.getNode(ISD::BITCAST, dl, VT,
5825 DAG.getNode(Opc, dl, ShVT, SrcOp,
5826 DAG.getConstant(NumBits,
5827 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5831 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5833 // Check if the scalar load can be widened into a vector load. And if
5834 // the address is "base + cst" see if the cst can be "absorbed" into
5835 // the shuffle mask.
5836 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5837 SDValue Ptr = LD->getBasePtr();
5838 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5840 EVT PVT = LD->getValueType(0);
5841 if (PVT != MVT::i32 && PVT != MVT::f32)
5846 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5847 FI = FINode->getIndex();
5849 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5850 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5851 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5852 Offset = Ptr.getConstantOperandVal(1);
5853 Ptr = Ptr.getOperand(0);
5858 // FIXME: 256-bit vector instructions don't require a strict alignment,
5859 // improve this code to support it better.
5860 unsigned RequiredAlign = VT.getSizeInBits()/8;
5861 SDValue Chain = LD->getChain();
5862 // Make sure the stack object alignment is at least 16 or 32.
5863 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5864 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5865 if (MFI->isFixedObjectIndex(FI)) {
5866 // Can't change the alignment. FIXME: It's possible to compute
5867 // the exact stack offset and reference FI + adjust offset instead.
5868 // If someone *really* cares about this. That's the way to implement it.
5871 MFI->setObjectAlignment(FI, RequiredAlign);
5875 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5876 // Ptr + (Offset & ~15).
5879 if ((Offset % RequiredAlign) & 3)
5881 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5883 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5884 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5886 int EltNo = (Offset - StartOffset) >> 2;
5887 unsigned NumElems = VT.getVectorNumElements();
5889 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5890 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5891 LD->getPointerInfo().getWithOffset(StartOffset),
5892 false, false, false, 0);
5894 SmallVector<int, 8> Mask;
5895 for (unsigned i = 0; i != NumElems; ++i)
5896 Mask.push_back(EltNo);
5898 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5904 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5905 /// vector of type 'VT', see if the elements can be replaced by a single large
5906 /// load which has the same value as a build_vector whose operands are 'elts'.
5908 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5910 /// FIXME: we'd also like to handle the case where the last elements are zero
5911 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5912 /// There's even a handy isZeroNode for that purpose.
5913 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5914 SDLoc &DL, SelectionDAG &DAG,
5915 bool isAfterLegalize) {
5916 EVT EltVT = VT.getVectorElementType();
5917 unsigned NumElems = Elts.size();
5919 LoadSDNode *LDBase = nullptr;
5920 unsigned LastLoadedElt = -1U;
5922 // For each element in the initializer, see if we've found a load or an undef.
5923 // If we don't find an initial load element, or later load elements are
5924 // non-consecutive, bail out.
5925 for (unsigned i = 0; i < NumElems; ++i) {
5926 SDValue Elt = Elts[i];
5928 if (!Elt.getNode() ||
5929 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5932 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5934 LDBase = cast<LoadSDNode>(Elt.getNode());
5938 if (Elt.getOpcode() == ISD::UNDEF)
5941 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5942 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5947 // If we have found an entire vector of loads and undefs, then return a large
5948 // load of the entire vector width starting at the base pointer. If we found
5949 // consecutive loads for the low half, generate a vzext_load node.
5950 if (LastLoadedElt == NumElems - 1) {
5952 if (isAfterLegalize &&
5953 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5956 SDValue NewLd = SDValue();
5958 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5959 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5960 LDBase->getPointerInfo(),
5961 LDBase->isVolatile(), LDBase->isNonTemporal(),
5962 LDBase->isInvariant(), 0);
5963 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5964 LDBase->getPointerInfo(),
5965 LDBase->isVolatile(), LDBase->isNonTemporal(),
5966 LDBase->isInvariant(), LDBase->getAlignment());
5968 if (LDBase->hasAnyUseOfValue(1)) {
5969 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5971 SDValue(NewLd.getNode(), 1));
5972 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5973 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5974 SDValue(NewLd.getNode(), 1));
5979 if (NumElems == 4 && LastLoadedElt == 1 &&
5980 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5981 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5982 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5984 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5985 LDBase->getPointerInfo(),
5986 LDBase->getAlignment(),
5987 false/*isVolatile*/, true/*ReadMem*/,
5990 // Make sure the newly-created LOAD is in the same position as LDBase in
5991 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5992 // update uses of LDBase's output chain to use the TokenFactor.
5993 if (LDBase->hasAnyUseOfValue(1)) {
5994 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5995 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5996 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5997 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5998 SDValue(ResNode.getNode(), 1));
6001 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6006 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6007 /// to generate a splat value for the following cases:
6008 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6009 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6010 /// a scalar load, or a constant.
6011 /// The VBROADCAST node is returned when a pattern is found,
6012 /// or SDValue() otherwise.
6013 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6014 SelectionDAG &DAG) {
6015 // VBROADCAST requires AVX.
6016 // TODO: Splats could be generated for non-AVX CPUs using SSE
6017 // instructions, but there's less potential gain for only 128-bit vectors.
6018 if (!Subtarget->hasAVX())
6021 MVT VT = Op.getSimpleValueType();
6024 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6025 "Unsupported vector type for broadcast.");
6030 switch (Op.getOpcode()) {
6032 // Unknown pattern found.
6035 case ISD::BUILD_VECTOR: {
6036 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6037 BitVector UndefElements;
6038 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6040 // We need a splat of a single value to use broadcast, and it doesn't
6041 // make any sense if the value is only in one element of the vector.
6042 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6046 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6047 Ld.getOpcode() == ISD::ConstantFP);
6049 // Make sure that all of the users of a non-constant load are from the
6050 // BUILD_VECTOR node.
6051 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6056 case ISD::VECTOR_SHUFFLE: {
6057 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6059 // Shuffles must have a splat mask where the first element is
6061 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6064 SDValue Sc = Op.getOperand(0);
6065 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6066 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6068 if (!Subtarget->hasInt256())
6071 // Use the register form of the broadcast instruction available on AVX2.
6072 if (VT.getSizeInBits() >= 256)
6073 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6074 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6077 Ld = Sc.getOperand(0);
6078 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6079 Ld.getOpcode() == ISD::ConstantFP);
6081 // The scalar_to_vector node and the suspected
6082 // load node must have exactly one user.
6083 // Constants may have multiple users.
6085 // AVX-512 has register version of the broadcast
6086 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6087 Ld.getValueType().getSizeInBits() >= 32;
6088 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6095 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6096 bool IsGE256 = (VT.getSizeInBits() >= 256);
6098 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6099 // instruction to save 8 or more bytes of constant pool data.
6100 // TODO: If multiple splats are generated to load the same constant,
6101 // it may be detrimental to overall size. There needs to be a way to detect
6102 // that condition to know if this is truly a size win.
6103 const Function *F = DAG.getMachineFunction().getFunction();
6104 bool OptForSize = F->getAttributes().
6105 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6107 // Handle broadcasting a single constant scalar from the constant pool
6109 // On Sandybridge (no AVX2), it is still better to load a constant vector
6110 // from the constant pool and not to broadcast it from a scalar.
6111 // But override that restriction when optimizing for size.
6112 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6113 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6114 EVT CVT = Ld.getValueType();
6115 assert(!CVT.isVector() && "Must not broadcast a vector type");
6117 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6118 // For size optimization, also splat v2f64 and v2i64, and for size opt
6119 // with AVX2, also splat i8 and i16.
6120 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6121 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6122 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6123 const Constant *C = nullptr;
6124 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6125 C = CI->getConstantIntValue();
6126 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6127 C = CF->getConstantFPValue();
6129 assert(C && "Invalid constant type");
6131 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6132 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6133 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6134 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6135 MachinePointerInfo::getConstantPool(),
6136 false, false, false, Alignment);
6138 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6142 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6144 // Handle AVX2 in-register broadcasts.
6145 if (!IsLoad && Subtarget->hasInt256() &&
6146 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6147 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6149 // The scalar source must be a normal load.
6153 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6154 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6156 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6157 // double since there is no vbroadcastsd xmm
6158 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6159 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6160 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6163 // Unsupported broadcast.
6167 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6168 /// underlying vector and index.
6170 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6172 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6174 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6175 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6178 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6180 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6182 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6183 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6186 // In this case the vector is the extract_subvector expression and the index
6187 // is 2, as specified by the shuffle.
6188 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6189 SDValue ShuffleVec = SVOp->getOperand(0);
6190 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6191 assert(ShuffleVecVT.getVectorElementType() ==
6192 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6194 int ShuffleIdx = SVOp->getMaskElt(Idx);
6195 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6196 ExtractedFromVec = ShuffleVec;
6202 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6203 MVT VT = Op.getSimpleValueType();
6205 // Skip if insert_vec_elt is not supported.
6206 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6207 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6211 unsigned NumElems = Op.getNumOperands();
6215 SmallVector<unsigned, 4> InsertIndices;
6216 SmallVector<int, 8> Mask(NumElems, -1);
6218 for (unsigned i = 0; i != NumElems; ++i) {
6219 unsigned Opc = Op.getOperand(i).getOpcode();
6221 if (Opc == ISD::UNDEF)
6224 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6225 // Quit if more than 1 elements need inserting.
6226 if (InsertIndices.size() > 1)
6229 InsertIndices.push_back(i);
6233 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6234 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6235 // Quit if non-constant index.
6236 if (!isa<ConstantSDNode>(ExtIdx))
6238 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6240 // Quit if extracted from vector of different type.
6241 if (ExtractedFromVec.getValueType() != VT)
6244 if (!VecIn1.getNode())
6245 VecIn1 = ExtractedFromVec;
6246 else if (VecIn1 != ExtractedFromVec) {
6247 if (!VecIn2.getNode())
6248 VecIn2 = ExtractedFromVec;
6249 else if (VecIn2 != ExtractedFromVec)
6250 // Quit if more than 2 vectors to shuffle
6254 if (ExtractedFromVec == VecIn1)
6256 else if (ExtractedFromVec == VecIn2)
6257 Mask[i] = Idx + NumElems;
6260 if (!VecIn1.getNode())
6263 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6264 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6265 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6266 unsigned Idx = InsertIndices[i];
6267 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6268 DAG.getIntPtrConstant(Idx));
6274 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6276 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6278 MVT VT = Op.getSimpleValueType();
6279 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6280 "Unexpected type in LowerBUILD_VECTORvXi1!");
6283 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6284 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6285 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6286 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6289 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6290 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6291 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6292 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6295 bool AllContants = true;
6296 uint64_t Immediate = 0;
6297 int NonConstIdx = -1;
6298 bool IsSplat = true;
6299 unsigned NumNonConsts = 0;
6300 unsigned NumConsts = 0;
6301 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6302 SDValue In = Op.getOperand(idx);
6303 if (In.getOpcode() == ISD::UNDEF)
6305 if (!isa<ConstantSDNode>(In)) {
6306 AllContants = false;
6312 if (cast<ConstantSDNode>(In)->getZExtValue())
6313 Immediate |= (1ULL << idx);
6315 if (In != Op.getOperand(0))
6320 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6321 DAG.getConstant(Immediate, MVT::i16));
6322 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6323 DAG.getIntPtrConstant(0));
6326 if (NumNonConsts == 1 && NonConstIdx != 0) {
6329 SDValue VecAsImm = DAG.getConstant(Immediate,
6330 MVT::getIntegerVT(VT.getSizeInBits()));
6331 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6334 DstVec = DAG.getUNDEF(VT);
6335 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6336 Op.getOperand(NonConstIdx),
6337 DAG.getIntPtrConstant(NonConstIdx));
6339 if (!IsSplat && (NonConstIdx != 0))
6340 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6341 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6344 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6345 DAG.getConstant(-1, SelectVT),
6346 DAG.getConstant(0, SelectVT));
6348 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6349 DAG.getConstant((Immediate | 1), SelectVT),
6350 DAG.getConstant(Immediate, SelectVT));
6351 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6354 /// \brief Return true if \p N implements a horizontal binop and return the
6355 /// operands for the horizontal binop into V0 and V1.
6357 /// This is a helper function of PerformBUILD_VECTORCombine.
6358 /// This function checks that the build_vector \p N in input implements a
6359 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6360 /// operation to match.
6361 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6362 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6363 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6366 /// This function only analyzes elements of \p N whose indices are
6367 /// in range [BaseIdx, LastIdx).
6368 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6370 unsigned BaseIdx, unsigned LastIdx,
6371 SDValue &V0, SDValue &V1) {
6372 EVT VT = N->getValueType(0);
6374 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6375 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6376 "Invalid Vector in input!");
6378 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6379 bool CanFold = true;
6380 unsigned ExpectedVExtractIdx = BaseIdx;
6381 unsigned NumElts = LastIdx - BaseIdx;
6382 V0 = DAG.getUNDEF(VT);
6383 V1 = DAG.getUNDEF(VT);
6385 // Check if N implements a horizontal binop.
6386 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6387 SDValue Op = N->getOperand(i + BaseIdx);
6390 if (Op->getOpcode() == ISD::UNDEF) {
6391 // Update the expected vector extract index.
6392 if (i * 2 == NumElts)
6393 ExpectedVExtractIdx = BaseIdx;
6394 ExpectedVExtractIdx += 2;
6398 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6403 SDValue Op0 = Op.getOperand(0);
6404 SDValue Op1 = Op.getOperand(1);
6406 // Try to match the following pattern:
6407 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6408 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6409 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6410 Op0.getOperand(0) == Op1.getOperand(0) &&
6411 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6412 isa<ConstantSDNode>(Op1.getOperand(1)));
6416 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6417 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6419 if (i * 2 < NumElts) {
6420 if (V0.getOpcode() == ISD::UNDEF)
6421 V0 = Op0.getOperand(0);
6423 if (V1.getOpcode() == ISD::UNDEF)
6424 V1 = Op0.getOperand(0);
6425 if (i * 2 == NumElts)
6426 ExpectedVExtractIdx = BaseIdx;
6429 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6430 if (I0 == ExpectedVExtractIdx)
6431 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6432 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6433 // Try to match the following dag sequence:
6434 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6435 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6439 ExpectedVExtractIdx += 2;
6445 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6446 /// a concat_vector.
6448 /// This is a helper function of PerformBUILD_VECTORCombine.
6449 /// This function expects two 256-bit vectors called V0 and V1.
6450 /// At first, each vector is split into two separate 128-bit vectors.
6451 /// Then, the resulting 128-bit vectors are used to implement two
6452 /// horizontal binary operations.
6454 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6456 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6457 /// the two new horizontal binop.
6458 /// When Mode is set, the first horizontal binop dag node would take as input
6459 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6460 /// horizontal binop dag node would take as input the lower 128-bit of V1
6461 /// and the upper 128-bit of V1.
6463 /// HADD V0_LO, V0_HI
6464 /// HADD V1_LO, V1_HI
6466 /// Otherwise, the first horizontal binop dag node takes as input the lower
6467 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6468 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6470 /// HADD V0_LO, V1_LO
6471 /// HADD V0_HI, V1_HI
6473 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6474 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6475 /// the upper 128-bits of the result.
6476 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6477 SDLoc DL, SelectionDAG &DAG,
6478 unsigned X86Opcode, bool Mode,
6479 bool isUndefLO, bool isUndefHI) {
6480 EVT VT = V0.getValueType();
6481 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6482 "Invalid nodes in input!");
6484 unsigned NumElts = VT.getVectorNumElements();
6485 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6486 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6487 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6488 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6489 EVT NewVT = V0_LO.getValueType();
6491 SDValue LO = DAG.getUNDEF(NewVT);
6492 SDValue HI = DAG.getUNDEF(NewVT);
6495 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6496 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6497 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6498 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6499 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6501 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6502 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6503 V1_LO->getOpcode() != ISD::UNDEF))
6504 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6506 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6507 V1_HI->getOpcode() != ISD::UNDEF))
6508 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6511 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6514 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6515 /// sequence of 'vadd + vsub + blendi'.
6516 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6517 const X86Subtarget *Subtarget) {
6519 EVT VT = BV->getValueType(0);
6520 unsigned NumElts = VT.getVectorNumElements();
6521 SDValue InVec0 = DAG.getUNDEF(VT);
6522 SDValue InVec1 = DAG.getUNDEF(VT);
6524 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6525 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6527 // Odd-numbered elements in the input build vector are obtained from
6528 // adding two integer/float elements.
6529 // Even-numbered elements in the input build vector are obtained from
6530 // subtracting two integer/float elements.
6531 unsigned ExpectedOpcode = ISD::FSUB;
6532 unsigned NextExpectedOpcode = ISD::FADD;
6533 bool AddFound = false;
6534 bool SubFound = false;
6536 for (unsigned i = 0, e = NumElts; i != e; i++) {
6537 SDValue Op = BV->getOperand(i);
6539 // Skip 'undef' values.
6540 unsigned Opcode = Op.getOpcode();
6541 if (Opcode == ISD::UNDEF) {
6542 std::swap(ExpectedOpcode, NextExpectedOpcode);
6546 // Early exit if we found an unexpected opcode.
6547 if (Opcode != ExpectedOpcode)
6550 SDValue Op0 = Op.getOperand(0);
6551 SDValue Op1 = Op.getOperand(1);
6553 // Try to match the following pattern:
6554 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6555 // Early exit if we cannot match that sequence.
6556 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6557 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6558 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6559 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6560 Op0.getOperand(1) != Op1.getOperand(1))
6563 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6567 // We found a valid add/sub node. Update the information accordingly.
6573 // Update InVec0 and InVec1.
6574 if (InVec0.getOpcode() == ISD::UNDEF)
6575 InVec0 = Op0.getOperand(0);
6576 if (InVec1.getOpcode() == ISD::UNDEF)
6577 InVec1 = Op1.getOperand(0);
6579 // Make sure that operands in input to each add/sub node always
6580 // come from a same pair of vectors.
6581 if (InVec0 != Op0.getOperand(0)) {
6582 if (ExpectedOpcode == ISD::FSUB)
6585 // FADD is commutable. Try to commute the operands
6586 // and then test again.
6587 std::swap(Op0, Op1);
6588 if (InVec0 != Op0.getOperand(0))
6592 if (InVec1 != Op1.getOperand(0))
6595 // Update the pair of expected opcodes.
6596 std::swap(ExpectedOpcode, NextExpectedOpcode);
6599 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6600 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6601 InVec1.getOpcode() != ISD::UNDEF)
6602 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6607 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6608 const X86Subtarget *Subtarget) {
6610 EVT VT = N->getValueType(0);
6611 unsigned NumElts = VT.getVectorNumElements();
6612 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6613 SDValue InVec0, InVec1;
6615 // Try to match an ADDSUB.
6616 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6617 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6618 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6619 if (Value.getNode())
6623 // Try to match horizontal ADD/SUB.
6624 unsigned NumUndefsLO = 0;
6625 unsigned NumUndefsHI = 0;
6626 unsigned Half = NumElts/2;
6628 // Count the number of UNDEF operands in the build_vector in input.
6629 for (unsigned i = 0, e = Half; i != e; ++i)
6630 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6633 for (unsigned i = Half, e = NumElts; i != e; ++i)
6634 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6637 // Early exit if this is either a build_vector of all UNDEFs or all the
6638 // operands but one are UNDEF.
6639 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6642 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6643 // Try to match an SSE3 float HADD/HSUB.
6644 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6645 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6647 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6648 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6649 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6650 // Try to match an SSSE3 integer HADD/HSUB.
6651 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6652 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6654 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6655 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6658 if (!Subtarget->hasAVX())
6661 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6662 // Try to match an AVX horizontal add/sub of packed single/double
6663 // precision floating point values from 256-bit vectors.
6664 SDValue InVec2, InVec3;
6665 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6666 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6667 ((InVec0.getOpcode() == ISD::UNDEF ||
6668 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6669 ((InVec1.getOpcode() == ISD::UNDEF ||
6670 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6671 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6673 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6674 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6675 ((InVec0.getOpcode() == ISD::UNDEF ||
6676 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6677 ((InVec1.getOpcode() == ISD::UNDEF ||
6678 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6679 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6680 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6681 // Try to match an AVX2 horizontal add/sub of signed integers.
6682 SDValue InVec2, InVec3;
6684 bool CanFold = true;
6686 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6687 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6688 ((InVec0.getOpcode() == ISD::UNDEF ||
6689 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6690 ((InVec1.getOpcode() == ISD::UNDEF ||
6691 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6692 X86Opcode = X86ISD::HADD;
6693 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6694 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6695 ((InVec0.getOpcode() == ISD::UNDEF ||
6696 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6697 ((InVec1.getOpcode() == ISD::UNDEF ||
6698 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6699 X86Opcode = X86ISD::HSUB;
6704 // Fold this build_vector into a single horizontal add/sub.
6705 // Do this only if the target has AVX2.
6706 if (Subtarget->hasAVX2())
6707 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6709 // Do not try to expand this build_vector into a pair of horizontal
6710 // add/sub if we can emit a pair of scalar add/sub.
6711 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6714 // Convert this build_vector into a pair of horizontal binop followed by
6716 bool isUndefLO = NumUndefsLO == Half;
6717 bool isUndefHI = NumUndefsHI == Half;
6718 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6719 isUndefLO, isUndefHI);
6723 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6724 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6726 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6727 X86Opcode = X86ISD::HADD;
6728 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6729 X86Opcode = X86ISD::HSUB;
6730 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6731 X86Opcode = X86ISD::FHADD;
6732 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6733 X86Opcode = X86ISD::FHSUB;
6737 // Don't try to expand this build_vector into a pair of horizontal add/sub
6738 // if we can simply emit a pair of scalar add/sub.
6739 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6742 // Convert this build_vector into two horizontal add/sub followed by
6744 bool isUndefLO = NumUndefsLO == Half;
6745 bool isUndefHI = NumUndefsHI == Half;
6746 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6747 isUndefLO, isUndefHI);
6754 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6757 MVT VT = Op.getSimpleValueType();
6758 MVT ExtVT = VT.getVectorElementType();
6759 unsigned NumElems = Op.getNumOperands();
6761 // Generate vectors for predicate vectors.
6762 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6763 return LowerBUILD_VECTORvXi1(Op, DAG);
6765 // Vectors containing all zeros can be matched by pxor and xorps later
6766 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6767 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6768 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6769 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6772 return getZeroVector(VT, Subtarget, DAG, dl);
6775 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6776 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6777 // vpcmpeqd on 256-bit vectors.
6778 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6779 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6782 if (!VT.is512BitVector())
6783 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6786 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6787 if (Broadcast.getNode())
6790 unsigned EVTBits = ExtVT.getSizeInBits();
6792 unsigned NumZero = 0;
6793 unsigned NumNonZero = 0;
6794 unsigned NonZeros = 0;
6795 bool IsAllConstants = true;
6796 SmallSet<SDValue, 8> Values;
6797 for (unsigned i = 0; i < NumElems; ++i) {
6798 SDValue Elt = Op.getOperand(i);
6799 if (Elt.getOpcode() == ISD::UNDEF)
6802 if (Elt.getOpcode() != ISD::Constant &&
6803 Elt.getOpcode() != ISD::ConstantFP)
6804 IsAllConstants = false;
6805 if (X86::isZeroNode(Elt))
6808 NonZeros |= (1 << i);
6813 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6814 if (NumNonZero == 0)
6815 return DAG.getUNDEF(VT);
6817 // Special case for single non-zero, non-undef, element.
6818 if (NumNonZero == 1) {
6819 unsigned Idx = countTrailingZeros(NonZeros);
6820 SDValue Item = Op.getOperand(Idx);
6822 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6823 // the value are obviously zero, truncate the value to i32 and do the
6824 // insertion that way. Only do this if the value is non-constant or if the
6825 // value is a constant being inserted into element 0. It is cheaper to do
6826 // a constant pool load than it is to do a movd + shuffle.
6827 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6828 (!IsAllConstants || Idx == 0)) {
6829 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6831 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6832 EVT VecVT = MVT::v4i32;
6833 unsigned VecElts = 4;
6835 // Truncate the value (which may itself be a constant) to i32, and
6836 // convert it to a vector with movd (S2V+shuffle to zero extend).
6837 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6838 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6840 // If using the new shuffle lowering, just directly insert this.
6841 if (ExperimentalVectorShuffleLowering)
6843 ISD::BITCAST, dl, VT,
6844 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6846 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6848 // Now we have our 32-bit value zero extended in the low element of
6849 // a vector. If Idx != 0, swizzle it into place.
6851 SmallVector<int, 4> Mask;
6852 Mask.push_back(Idx);
6853 for (unsigned i = 1; i != VecElts; ++i)
6855 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6858 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6862 // If we have a constant or non-constant insertion into the low element of
6863 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6864 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6865 // depending on what the source datatype is.
6868 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6870 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6871 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6872 if (VT.is256BitVector() || VT.is512BitVector()) {
6873 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6874 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6875 Item, DAG.getIntPtrConstant(0));
6877 assert(VT.is128BitVector() && "Expected an SSE value type!");
6878 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6879 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6880 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6883 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6884 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6885 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6886 if (VT.is256BitVector()) {
6887 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6888 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6890 assert(VT.is128BitVector() && "Expected an SSE value type!");
6891 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6893 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6897 // Is it a vector logical left shift?
6898 if (NumElems == 2 && Idx == 1 &&
6899 X86::isZeroNode(Op.getOperand(0)) &&
6900 !X86::isZeroNode(Op.getOperand(1))) {
6901 unsigned NumBits = VT.getSizeInBits();
6902 return getVShift(true, VT,
6903 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6904 VT, Op.getOperand(1)),
6905 NumBits/2, DAG, *this, dl);
6908 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6911 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6912 // is a non-constant being inserted into an element other than the low one,
6913 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6914 // movd/movss) to move this into the low element, then shuffle it into
6916 if (EVTBits == 32) {
6917 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6919 // If using the new shuffle lowering, just directly insert this.
6920 if (ExperimentalVectorShuffleLowering)
6921 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6923 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6924 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6925 SmallVector<int, 8> MaskVec;
6926 for (unsigned i = 0; i != NumElems; ++i)
6927 MaskVec.push_back(i == Idx ? 0 : 1);
6928 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6932 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6933 if (Values.size() == 1) {
6934 if (EVTBits == 32) {
6935 // Instead of a shuffle like this:
6936 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6937 // Check if it's possible to issue this instead.
6938 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6939 unsigned Idx = countTrailingZeros(NonZeros);
6940 SDValue Item = Op.getOperand(Idx);
6941 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6942 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6947 // A vector full of immediates; various special cases are already
6948 // handled, so this is best done with a single constant-pool load.
6952 // For AVX-length vectors, build the individual 128-bit pieces and use
6953 // shuffles to put them in place.
6954 if (VT.is256BitVector() || VT.is512BitVector()) {
6955 SmallVector<SDValue, 64> V;
6956 for (unsigned i = 0; i != NumElems; ++i)
6957 V.push_back(Op.getOperand(i));
6959 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6961 // Build both the lower and upper subvector.
6962 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6963 makeArrayRef(&V[0], NumElems/2));
6964 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6965 makeArrayRef(&V[NumElems / 2], NumElems/2));
6967 // Recreate the wider vector with the lower and upper part.
6968 if (VT.is256BitVector())
6969 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6970 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6973 // Let legalizer expand 2-wide build_vectors.
6974 if (EVTBits == 64) {
6975 if (NumNonZero == 1) {
6976 // One half is zero or undef.
6977 unsigned Idx = countTrailingZeros(NonZeros);
6978 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6979 Op.getOperand(Idx));
6980 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6985 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6986 if (EVTBits == 8 && NumElems == 16) {
6987 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6989 if (V.getNode()) return V;
6992 if (EVTBits == 16 && NumElems == 8) {
6993 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6995 if (V.getNode()) return V;
6998 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6999 if (EVTBits == 32 && NumElems == 4) {
7000 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
7001 NumZero, DAG, Subtarget, *this);
7006 // If element VT is == 32 bits, turn it into a number of shuffles.
7007 SmallVector<SDValue, 8> V(NumElems);
7008 if (NumElems == 4 && NumZero > 0) {
7009 for (unsigned i = 0; i < 4; ++i) {
7010 bool isZero = !(NonZeros & (1 << i));
7012 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7014 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7017 for (unsigned i = 0; i < 2; ++i) {
7018 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7021 V[i] = V[i*2]; // Must be a zero vector.
7024 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7027 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7030 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7035 bool Reverse1 = (NonZeros & 0x3) == 2;
7036 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7040 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7041 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7043 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7046 if (Values.size() > 1 && VT.is128BitVector()) {
7047 // Check for a build vector of consecutive loads.
7048 for (unsigned i = 0; i < NumElems; ++i)
7049 V[i] = Op.getOperand(i);
7051 // Check for elements which are consecutive loads.
7052 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7056 // Check for a build vector from mostly shuffle plus few inserting.
7057 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7061 // For SSE 4.1, use insertps to put the high elements into the low element.
7062 if (getSubtarget()->hasSSE41()) {
7064 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7065 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7067 Result = DAG.getUNDEF(VT);
7069 for (unsigned i = 1; i < NumElems; ++i) {
7070 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7071 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7072 Op.getOperand(i), DAG.getIntPtrConstant(i));
7077 // Otherwise, expand into a number of unpckl*, start by extending each of
7078 // our (non-undef) elements to the full vector width with the element in the
7079 // bottom slot of the vector (which generates no code for SSE).
7080 for (unsigned i = 0; i < NumElems; ++i) {
7081 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7082 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7084 V[i] = DAG.getUNDEF(VT);
7087 // Next, we iteratively mix elements, e.g. for v4f32:
7088 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7089 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7090 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7091 unsigned EltStride = NumElems >> 1;
7092 while (EltStride != 0) {
7093 for (unsigned i = 0; i < EltStride; ++i) {
7094 // If V[i+EltStride] is undef and this is the first round of mixing,
7095 // then it is safe to just drop this shuffle: V[i] is already in the
7096 // right place, the one element (since it's the first round) being
7097 // inserted as undef can be dropped. This isn't safe for successive
7098 // rounds because they will permute elements within both vectors.
7099 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7100 EltStride == NumElems/2)
7103 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7112 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7113 // to create 256-bit vectors from two other 128-bit ones.
7114 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7116 MVT ResVT = Op.getSimpleValueType();
7118 assert((ResVT.is256BitVector() ||
7119 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7121 SDValue V1 = Op.getOperand(0);
7122 SDValue V2 = Op.getOperand(1);
7123 unsigned NumElems = ResVT.getVectorNumElements();
7124 if(ResVT.is256BitVector())
7125 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7127 if (Op.getNumOperands() == 4) {
7128 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7129 ResVT.getVectorNumElements()/2);
7130 SDValue V3 = Op.getOperand(2);
7131 SDValue V4 = Op.getOperand(3);
7132 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7133 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7135 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7138 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7139 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7140 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7141 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7142 Op.getNumOperands() == 4)));
7144 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7145 // from two other 128-bit ones.
7147 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7148 return LowerAVXCONCAT_VECTORS(Op, DAG);
7152 //===----------------------------------------------------------------------===//
7153 // Vector shuffle lowering
7155 // This is an experimental code path for lowering vector shuffles on x86. It is
7156 // designed to handle arbitrary vector shuffles and blends, gracefully
7157 // degrading performance as necessary. It works hard to recognize idiomatic
7158 // shuffles and lower them to optimal instruction patterns without leaving
7159 // a framework that allows reasonably efficient handling of all vector shuffle
7161 //===----------------------------------------------------------------------===//
7163 /// \brief Tiny helper function to identify a no-op mask.
7165 /// This is a somewhat boring predicate function. It checks whether the mask
7166 /// array input, which is assumed to be a single-input shuffle mask of the kind
7167 /// used by the X86 shuffle instructions (not a fully general
7168 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7169 /// in-place shuffle are 'no-op's.
7170 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7171 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7172 if (Mask[i] != -1 && Mask[i] != i)
7177 /// \brief Helper function to classify a mask as a single-input mask.
7179 /// This isn't a generic single-input test because in the vector shuffle
7180 /// lowering we canonicalize single inputs to be the first input operand. This
7181 /// means we can more quickly test for a single input by only checking whether
7182 /// an input from the second operand exists. We also assume that the size of
7183 /// mask corresponds to the size of the input vectors which isn't true in the
7184 /// fully general case.
7185 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7187 if (M >= (int)Mask.size())
7192 /// \brief Test whether there are elements crossing 128-bit lanes in this
7195 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7196 /// and we routinely test for these.
7197 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7198 int LaneSize = 128 / VT.getScalarSizeInBits();
7199 int Size = Mask.size();
7200 for (int i = 0; i < Size; ++i)
7201 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7206 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7208 /// This checks a shuffle mask to see if it is performing the same
7209 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7210 /// that it is also not lane-crossing. It may however involve a blend from the
7211 /// same lane of a second vector.
7213 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7214 /// non-trivial to compute in the face of undef lanes. The representation is
7215 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7216 /// entries from both V1 and V2 inputs to the wider mask.
7218 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7219 SmallVectorImpl<int> &RepeatedMask) {
7220 int LaneSize = 128 / VT.getScalarSizeInBits();
7221 RepeatedMask.resize(LaneSize, -1);
7222 int Size = Mask.size();
7223 for (int i = 0; i < Size; ++i) {
7226 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7227 // This entry crosses lanes, so there is no way to model this shuffle.
7230 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7231 if (RepeatedMask[i % LaneSize] == -1)
7232 // This is the first non-undef entry in this slot of a 128-bit lane.
7233 RepeatedMask[i % LaneSize] =
7234 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7235 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7236 // Found a mismatch with the repeated mask.
7242 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7243 // 2013 will allow us to use it as a non-type template parameter.
7246 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7248 /// See its documentation for details.
7249 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7250 if (Mask.size() != Args.size())
7252 for (int i = 0, e = Mask.size(); i < e; ++i) {
7253 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7254 if (Mask[i] != -1 && Mask[i] != *Args[i])
7262 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7265 /// This is a fast way to test a shuffle mask against a fixed pattern:
7267 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7269 /// It returns true if the mask is exactly as wide as the argument list, and
7270 /// each element of the mask is either -1 (signifying undef) or the value given
7271 /// in the argument.
7272 static const VariadicFunction1<
7273 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7275 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7277 /// This helper function produces an 8-bit shuffle immediate corresponding to
7278 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7279 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7282 /// NB: We rely heavily on "undef" masks preserving the input lane.
7283 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7284 SelectionDAG &DAG) {
7285 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7286 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7287 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7288 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7289 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7292 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7293 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7294 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7295 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7296 return DAG.getConstant(Imm, MVT::i8);
7299 /// \brief Try to emit a blend instruction for a shuffle.
7301 /// This doesn't do any checks for the availability of instructions for blending
7302 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7303 /// be matched in the backend with the type given. What it does check for is
7304 /// that the shuffle mask is in fact a blend.
7305 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7306 SDValue V2, ArrayRef<int> Mask,
7307 const X86Subtarget *Subtarget,
7308 SelectionDAG &DAG) {
7310 unsigned BlendMask = 0;
7311 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7312 if (Mask[i] >= Size) {
7313 if (Mask[i] != i + Size)
7314 return SDValue(); // Shuffled V2 input!
7315 BlendMask |= 1u << i;
7318 if (Mask[i] >= 0 && Mask[i] != i)
7319 return SDValue(); // Shuffled V1 input!
7321 switch (VT.SimpleTy) {
7326 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7327 DAG.getConstant(BlendMask, MVT::i8));
7331 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7335 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7336 // that instruction.
7337 if (Subtarget->hasAVX2()) {
7338 // Scale the blend by the number of 32-bit dwords per element.
7339 int Scale = VT.getScalarSizeInBits() / 32;
7341 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7342 if (Mask[i] >= Size)
7343 for (int j = 0; j < Scale; ++j)
7344 BlendMask |= 1u << (i * Scale + j);
7346 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7347 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7348 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7349 return DAG.getNode(ISD::BITCAST, DL, VT,
7350 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7351 DAG.getConstant(BlendMask, MVT::i8)));
7355 // For integer shuffles we need to expand the mask and cast the inputs to
7356 // v8i16s prior to blending.
7357 int Scale = 8 / VT.getVectorNumElements();
7359 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7360 if (Mask[i] >= Size)
7361 for (int j = 0; j < Scale; ++j)
7362 BlendMask |= 1u << (i * Scale + j);
7364 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7365 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7366 return DAG.getNode(ISD::BITCAST, DL, VT,
7367 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7368 DAG.getConstant(BlendMask, MVT::i8)));
7372 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7373 SmallVector<int, 8> RepeatedMask;
7374 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7375 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7376 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7378 for (int i = 0; i < 8; ++i)
7379 if (RepeatedMask[i] >= 16)
7380 BlendMask |= 1u << i;
7381 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7382 DAG.getConstant(BlendMask, MVT::i8));
7387 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7388 // Scale the blend by the number of bytes per element.
7389 int Scale = VT.getScalarSizeInBits() / 8;
7390 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7392 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7393 // mix of LLVM's code generator and the x86 backend. We tell the code
7394 // generator that boolean values in the elements of an x86 vector register
7395 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7396 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7397 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7398 // of the element (the remaining are ignored) and 0 in that high bit would
7399 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7400 // the LLVM model for boolean values in vector elements gets the relevant
7401 // bit set, it is set backwards and over constrained relative to x86's
7403 SDValue VSELECTMask[32];
7404 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7405 for (int j = 0; j < Scale; ++j)
7406 VSELECTMask[Scale * i + j] =
7407 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7408 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7410 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7411 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7413 ISD::BITCAST, DL, VT,
7414 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7415 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7420 llvm_unreachable("Not a supported integer vector type!");
7424 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7425 /// unblended shuffles followed by an unshuffled blend.
7427 /// This matches the extremely common pattern for handling combined
7428 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7430 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7434 SelectionDAG &DAG) {
7435 // Shuffle the input elements into the desired positions in V1 and V2 and
7436 // blend them together.
7437 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7438 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7439 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7440 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7441 if (Mask[i] >= 0 && Mask[i] < Size) {
7442 V1Mask[i] = Mask[i];
7444 } else if (Mask[i] >= Size) {
7445 V2Mask[i] = Mask[i] - Size;
7446 BlendMask[i] = i + Size;
7449 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7450 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7451 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7454 /// \brief Try to lower a vector shuffle as a byte rotation.
7456 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7457 /// byte-rotation of the concatenation of two vectors. This routine will
7458 /// try to generically lower a vector shuffle through such an instruction. It
7459 /// does not check for the availability of PALIGNR-based lowerings, only the
7460 /// applicability of this strategy to the given mask. This matches shuffle
7461 /// vectors that look like:
7463 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7465 /// Essentially it concatenates V1 and V2, shifts right by some number of
7466 /// elements, and takes the low elements as the result. Note that while this is
7467 /// specified as a *right shift* because x86 is little-endian, it is a *left
7468 /// rotate* of the vector lanes.
7470 /// Note that this only handles 128-bit vector widths currently.
7471 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7474 SelectionDAG &DAG) {
7475 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7477 // We need to detect various ways of spelling a rotation:
7478 // [11, 12, 13, 14, 15, 0, 1, 2]
7479 // [-1, 12, 13, 14, -1, -1, 1, -1]
7480 // [-1, -1, -1, -1, -1, -1, 1, 2]
7481 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7482 // [-1, 4, 5, 6, -1, -1, 9, -1]
7483 // [-1, 4, 5, 6, -1, -1, -1, -1]
7486 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7489 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7491 // Based on the mod-Size value of this mask element determine where
7492 // a rotated vector would have started.
7493 int StartIdx = i - (Mask[i] % Size);
7495 // The identity rotation isn't interesting, stop.
7498 // If we found the tail of a vector the rotation must be the missing
7499 // front. If we found the head of a vector, it must be how much of the head.
7500 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7503 Rotation = CandidateRotation;
7504 else if (Rotation != CandidateRotation)
7505 // The rotations don't match, so we can't match this mask.
7508 // Compute which value this mask is pointing at.
7509 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7511 // Compute which of the two target values this index should be assigned to.
7512 // This reflects whether the high elements are remaining or the low elements
7514 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7516 // Either set up this value if we've not encountered it before, or check
7517 // that it remains consistent.
7520 else if (TargetV != MaskV)
7521 // This may be a rotation, but it pulls from the inputs in some
7522 // unsupported interleaving.
7526 // Check that we successfully analyzed the mask, and normalize the results.
7527 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7528 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7534 // Cast the inputs to v16i8 to match PALIGNR.
7535 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7536 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7538 assert(VT.getSizeInBits() == 128 &&
7539 "Rotate-based lowering only supports 128-bit lowering!");
7540 assert(Mask.size() <= 16 &&
7541 "Can shuffle at most 16 bytes in a 128-bit vector!");
7542 // The actual rotate instruction rotates bytes, so we need to scale the
7543 // rotation based on how many bytes are in the vector.
7544 int Scale = 16 / Mask.size();
7546 return DAG.getNode(ISD::BITCAST, DL, VT,
7547 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7548 DAG.getConstant(Rotation * Scale, MVT::i8)));
7551 /// \brief Compute whether each element of a shuffle is zeroable.
7553 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7554 /// Either it is an undef element in the shuffle mask, the element of the input
7555 /// referenced is undef, or the element of the input referenced is known to be
7556 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7557 /// as many lanes with this technique as possible to simplify the remaining
7559 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7560 SDValue V1, SDValue V2) {
7561 SmallBitVector Zeroable(Mask.size(), false);
7563 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7564 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7566 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7568 // Handle the easy cases.
7569 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7574 // If this is an index into a build_vector node, dig out the input value and
7576 SDValue V = M < Size ? V1 : V2;
7577 if (V.getOpcode() != ISD::BUILD_VECTOR)
7580 SDValue Input = V.getOperand(M % Size);
7581 // The UNDEF opcode check really should be dead code here, but not quite
7582 // worth asserting on (it isn't invalid, just unexpected).
7583 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7590 /// \brief Lower a vector shuffle as a zero or any extension.
7592 /// Given a specific number of elements, element bit width, and extension
7593 /// stride, produce either a zero or any extension based on the available
7594 /// features of the subtarget.
7595 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7596 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7597 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7598 assert(Scale > 1 && "Need a scale to extend.");
7599 int EltBits = VT.getSizeInBits() / NumElements;
7600 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7601 "Only 8, 16, and 32 bit elements can be extended.");
7602 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7604 // Found a valid zext mask! Try various lowering strategies based on the
7605 // input type and available ISA extensions.
7606 if (Subtarget->hasSSE41()) {
7607 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7608 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7609 NumElements / Scale);
7610 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7611 return DAG.getNode(ISD::BITCAST, DL, VT,
7612 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7615 // For any extends we can cheat for larger element sizes and use shuffle
7616 // instructions that can fold with a load and/or copy.
7617 if (AnyExt && EltBits == 32) {
7618 int PSHUFDMask[4] = {0, -1, 1, -1};
7620 ISD::BITCAST, DL, VT,
7621 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7622 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7623 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7625 if (AnyExt && EltBits == 16 && Scale > 2) {
7626 int PSHUFDMask[4] = {0, -1, 0, -1};
7627 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7628 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7629 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7630 int PSHUFHWMask[4] = {1, -1, -1, -1};
7632 ISD::BITCAST, DL, VT,
7633 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7634 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7635 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7638 // If this would require more than 2 unpack instructions to expand, use
7639 // pshufb when available. We can only use more than 2 unpack instructions
7640 // when zero extending i8 elements which also makes it easier to use pshufb.
7641 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7642 assert(NumElements == 16 && "Unexpected byte vector width!");
7643 SDValue PSHUFBMask[16];
7644 for (int i = 0; i < 16; ++i)
7646 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7647 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7648 return DAG.getNode(ISD::BITCAST, DL, VT,
7649 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7650 DAG.getNode(ISD::BUILD_VECTOR, DL,
7651 MVT::v16i8, PSHUFBMask)));
7654 // Otherwise emit a sequence of unpacks.
7656 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7657 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7658 : getZeroVector(InputVT, Subtarget, DAG, DL);
7659 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7660 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7664 } while (Scale > 1);
7665 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7668 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7670 /// This routine will try to do everything in its power to cleverly lower
7671 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7672 /// check for the profitability of this lowering, it tries to aggressively
7673 /// match this pattern. It will use all of the micro-architectural details it
7674 /// can to emit an efficient lowering. It handles both blends with all-zero
7675 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7676 /// masking out later).
7678 /// The reason we have dedicated lowering for zext-style shuffles is that they
7679 /// are both incredibly common and often quite performance sensitive.
7680 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7681 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7682 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7683 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7685 int Bits = VT.getSizeInBits();
7686 int NumElements = Mask.size();
7688 // Define a helper function to check a particular ext-scale and lower to it if
7690 auto Lower = [&](int Scale) -> SDValue {
7693 for (int i = 0; i < NumElements; ++i) {
7695 continue; // Valid anywhere but doesn't tell us anything.
7696 if (i % Scale != 0) {
7697 // Each of the extend elements needs to be zeroable.
7701 // We no lorger are in the anyext case.
7706 // Each of the base elements needs to be consecutive indices into the
7707 // same input vector.
7708 SDValue V = Mask[i] < NumElements ? V1 : V2;
7711 else if (InputV != V)
7712 return SDValue(); // Flip-flopping inputs.
7714 if (Mask[i] % NumElements != i / Scale)
7715 return SDValue(); // Non-consecutive strided elemenst.
7718 // If we fail to find an input, we have a zero-shuffle which should always
7719 // have already been handled.
7720 // FIXME: Maybe handle this here in case during blending we end up with one?
7724 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7725 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7728 // The widest scale possible for extending is to a 64-bit integer.
7729 assert(Bits % 64 == 0 &&
7730 "The number of bits in a vector must be divisible by 64 on x86!");
7731 int NumExtElements = Bits / 64;
7733 // Each iteration, try extending the elements half as much, but into twice as
7735 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7736 assert(NumElements % NumExtElements == 0 &&
7737 "The input vector size must be divisble by the extended size.");
7738 if (SDValue V = Lower(NumElements / NumExtElements))
7742 // No viable ext lowering found.
7746 /// \brief Try to get a scalar value for a specific element of a vector.
7748 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7749 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7750 SelectionDAG &DAG) {
7751 MVT VT = V.getSimpleValueType();
7752 MVT EltVT = VT.getVectorElementType();
7753 while (V.getOpcode() == ISD::BITCAST)
7754 V = V.getOperand(0);
7755 // If the bitcasts shift the element size, we can't extract an equivalent
7757 MVT NewVT = V.getSimpleValueType();
7758 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7761 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7762 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7763 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7768 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7770 /// This is particularly important because the set of instructions varies
7771 /// significantly based on whether the operand is a load or not.
7772 static bool isShuffleFoldableLoad(SDValue V) {
7773 while (V.getOpcode() == ISD::BITCAST)
7774 V = V.getOperand(0);
7776 return ISD::isNON_EXTLoad(V.getNode());
7779 /// \brief Try to lower insertion of a single element into a zero vector.
7781 /// This is a common pattern that we have especially efficient patterns to lower
7782 /// across all subtarget feature sets.
7783 static SDValue lowerVectorShuffleAsElementInsertion(
7784 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7785 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7786 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7788 MVT EltVT = VT.getVectorElementType();
7790 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7791 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7793 bool IsV1Zeroable = true;
7794 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7795 if (i != V2Index && !Zeroable[i]) {
7796 IsV1Zeroable = false;
7800 // Check for a single input from a SCALAR_TO_VECTOR node.
7801 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7802 // all the smarts here sunk into that routine. However, the current
7803 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7804 // vector shuffle lowering is dead.
7805 if (SDValue V2S = getScalarValueForVectorElement(
7806 V2, Mask[V2Index] - Mask.size(), DAG)) {
7807 // We need to zext the scalar if it is smaller than an i32.
7808 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7809 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7810 // Using zext to expand a narrow element won't work for non-zero
7815 // Zero-extend directly to i32.
7817 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7819 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7820 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7821 EltVT == MVT::i16) {
7822 // Either not inserting from the low element of the input or the input
7823 // element size is too small to use VZEXT_MOVL to clear the high bits.
7827 if (!IsV1Zeroable) {
7828 // If V1 can't be treated as a zero vector we have fewer options to lower
7829 // this. We can't support integer vectors or non-zero targets cheaply, and
7830 // the V1 elements can't be permuted in any way.
7831 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7832 if (!VT.isFloatingPoint() || V2Index != 0)
7834 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7835 V1Mask[V2Index] = -1;
7836 if (!isNoopShuffleMask(V1Mask))
7838 // This is essentially a special case blend operation, but if we have
7839 // general purpose blend operations, they are always faster. Bail and let
7840 // the rest of the lowering handle these as blends.
7841 if (Subtarget->hasSSE41())
7844 // Otherwise, use MOVSD or MOVSS.
7845 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7846 "Only two types of floating point element types to handle!");
7847 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7851 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7853 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7856 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7857 // the desired position. Otherwise it is more efficient to do a vector
7858 // shift left. We know that we can do a vector shift left because all
7859 // the inputs are zero.
7860 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7861 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7862 V2Shuffle[V2Index] = 0;
7863 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7865 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7867 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7869 V2Index * EltVT.getSizeInBits(),
7870 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7871 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7877 /// \brief Try to lower broadcast of a single element.
7879 /// For convenience, this code also bundles all of the subtarget feature set
7880 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7881 /// a convenient way to factor it out.
7882 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
7884 const X86Subtarget *Subtarget,
7885 SelectionDAG &DAG) {
7886 if (!Subtarget->hasAVX())
7888 if (VT.isInteger() && !Subtarget->hasAVX2())
7891 // Check that the mask is a broadcast.
7892 int BroadcastIdx = -1;
7894 if (M >= 0 && BroadcastIdx == -1)
7896 else if (M >= 0 && M != BroadcastIdx)
7899 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7900 "a sorted mask where the broadcast "
7903 // Go up the chain of (vector) values to try and find a scalar load that
7904 // we can combine with the broadcast.
7906 switch (V.getOpcode()) {
7907 case ISD::CONCAT_VECTORS: {
7908 int OperandSize = Mask.size() / V.getNumOperands();
7909 V = V.getOperand(BroadcastIdx / OperandSize);
7910 BroadcastIdx %= OperandSize;
7914 case ISD::INSERT_SUBVECTOR: {
7915 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7916 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7920 int BeginIdx = (int)ConstantIdx->getZExtValue();
7922 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7923 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7924 BroadcastIdx -= BeginIdx;
7935 // Check if this is a broadcast of a scalar. We special case lowering
7936 // for scalars so that we can more effectively fold with loads.
7937 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7938 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7939 V = V.getOperand(BroadcastIdx);
7941 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
7943 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7945 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7946 // We can't broadcast from a vector register w/o AVX2, and we can only
7947 // broadcast from the zero-element of a vector register.
7951 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7954 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7956 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7957 /// support for floating point shuffles but not integer shuffles. These
7958 /// instructions will incur a domain crossing penalty on some chips though so
7959 /// it is better to avoid lowering through this for integer vectors where
7961 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7962 const X86Subtarget *Subtarget,
7963 SelectionDAG &DAG) {
7965 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7966 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7967 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7968 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7969 ArrayRef<int> Mask = SVOp->getMask();
7970 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7972 if (isSingleInputShuffleMask(Mask)) {
7973 // Straight shuffle of a single input vector. Simulate this by using the
7974 // single input as both of the "inputs" to this instruction..
7975 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7977 if (Subtarget->hasAVX()) {
7978 // If we have AVX, we can use VPERMILPS which will allow folding a load
7979 // into the shuffle.
7980 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7981 DAG.getConstant(SHUFPDMask, MVT::i8));
7984 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7985 DAG.getConstant(SHUFPDMask, MVT::i8));
7987 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7988 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7990 // Use dedicated unpack instructions for masks that match their pattern.
7991 if (isShuffleEquivalent(Mask, 0, 2))
7992 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7993 if (isShuffleEquivalent(Mask, 1, 3))
7994 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7996 // If we have a single input, insert that into V1 if we can do so cheaply.
7997 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7998 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7999 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8001 // Try inverting the insertion since for v2 masks it is easy to do and we
8002 // can't reliably sort the mask one way or the other.
8003 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8004 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8005 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8006 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8010 // Try to use one of the special instruction patterns to handle two common
8011 // blend patterns if a zero-blend above didn't work.
8012 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8013 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8014 // We can either use a special instruction to load over the low double or
8015 // to move just the low double.
8017 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8019 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8021 if (Subtarget->hasSSE41())
8022 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8026 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8027 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8028 DAG.getConstant(SHUFPDMask, MVT::i8));
8031 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8033 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8034 /// the integer unit to minimize domain crossing penalties. However, for blends
8035 /// it falls back to the floating point shuffle operation with appropriate bit
8037 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8038 const X86Subtarget *Subtarget,
8039 SelectionDAG &DAG) {
8041 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8042 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8043 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8044 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8045 ArrayRef<int> Mask = SVOp->getMask();
8046 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8048 if (isSingleInputShuffleMask(Mask)) {
8049 // Check for being able to broadcast a single element.
8050 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8051 Mask, Subtarget, DAG))
8054 // Straight shuffle of a single input vector. For everything from SSE2
8055 // onward this has a single fast instruction with no scary immediates.
8056 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8057 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8058 int WidenedMask[4] = {
8059 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8060 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8062 ISD::BITCAST, DL, MVT::v2i64,
8063 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8064 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8067 // If we have a single input from V2 insert that into V1 if we can do so
8069 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8070 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8071 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8073 // Try inverting the insertion since for v2 masks it is easy to do and we
8074 // can't reliably sort the mask one way or the other.
8075 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8076 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8077 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8078 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8082 // Use dedicated unpack instructions for masks that match their pattern.
8083 if (isShuffleEquivalent(Mask, 0, 2))
8084 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8085 if (isShuffleEquivalent(Mask, 1, 3))
8086 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8088 if (Subtarget->hasSSE41())
8089 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8093 // Try to use rotation instructions if available.
8094 if (Subtarget->hasSSSE3())
8095 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8096 DL, MVT::v2i64, V1, V2, Mask, DAG))
8099 // We implement this with SHUFPD which is pretty lame because it will likely
8100 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8101 // However, all the alternatives are still more cycles and newer chips don't
8102 // have this problem. It would be really nice if x86 had better shuffles here.
8103 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8104 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8105 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8106 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8109 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8111 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8112 /// It makes no assumptions about whether this is the *best* lowering, it simply
8114 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8115 ArrayRef<int> Mask, SDValue V1,
8116 SDValue V2, SelectionDAG &DAG) {
8117 SDValue LowV = V1, HighV = V2;
8118 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8121 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8123 if (NumV2Elements == 1) {
8125 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8128 // Compute the index adjacent to V2Index and in the same half by toggling
8130 int V2AdjIndex = V2Index ^ 1;
8132 if (Mask[V2AdjIndex] == -1) {
8133 // Handles all the cases where we have a single V2 element and an undef.
8134 // This will only ever happen in the high lanes because we commute the
8135 // vector otherwise.
8137 std::swap(LowV, HighV);
8138 NewMask[V2Index] -= 4;
8140 // Handle the case where the V2 element ends up adjacent to a V1 element.
8141 // To make this work, blend them together as the first step.
8142 int V1Index = V2AdjIndex;
8143 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8144 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8145 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8147 // Now proceed to reconstruct the final blend as we have the necessary
8148 // high or low half formed.
8155 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8156 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8158 } else if (NumV2Elements == 2) {
8159 if (Mask[0] < 4 && Mask[1] < 4) {
8160 // Handle the easy case where we have V1 in the low lanes and V2 in the
8164 } else if (Mask[2] < 4 && Mask[3] < 4) {
8165 // We also handle the reversed case because this utility may get called
8166 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8167 // arrange things in the right direction.
8173 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8174 // trying to place elements directly, just blend them and set up the final
8175 // shuffle to place them.
8177 // The first two blend mask elements are for V1, the second two are for
8179 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8180 Mask[2] < 4 ? Mask[2] : Mask[3],
8181 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8182 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8183 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8184 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8186 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8189 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8190 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8191 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8192 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8195 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8196 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8199 /// \brief Lower 4-lane 32-bit floating point shuffles.
8201 /// Uses instructions exclusively from the floating point unit to minimize
8202 /// domain crossing penalties, as these are sufficient to implement all v4f32
8204 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8205 const X86Subtarget *Subtarget,
8206 SelectionDAG &DAG) {
8208 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8209 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8210 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8211 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8212 ArrayRef<int> Mask = SVOp->getMask();
8213 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8216 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8218 if (NumV2Elements == 0) {
8219 // Check for being able to broadcast a single element.
8220 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8221 Mask, Subtarget, DAG))
8224 if (Subtarget->hasAVX()) {
8225 // If we have AVX, we can use VPERMILPS which will allow folding a load
8226 // into the shuffle.
8227 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8228 getV4X86ShuffleImm8ForMask(Mask, DAG));
8231 // Otherwise, use a straight shuffle of a single input vector. We pass the
8232 // input vector to both operands to simulate this with a SHUFPS.
8233 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8234 getV4X86ShuffleImm8ForMask(Mask, DAG));
8237 // Use dedicated unpack instructions for masks that match their pattern.
8238 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8239 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8240 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8241 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8243 // There are special ways we can lower some single-element blends. However, we
8244 // have custom ways we can lower more complex single-element blends below that
8245 // we defer to if both this and BLENDPS fail to match, so restrict this to
8246 // when the V2 input is targeting element 0 of the mask -- that is the fast
8248 if (NumV2Elements == 1 && Mask[0] >= 4)
8249 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8250 Mask, Subtarget, DAG))
8253 if (Subtarget->hasSSE41())
8254 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8258 // Check for whether we can use INSERTPS to perform the blend. We only use
8259 // INSERTPS when the V1 elements are already in the correct locations
8260 // because otherwise we can just always use two SHUFPS instructions which
8261 // are much smaller to encode than a SHUFPS and an INSERTPS.
8262 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8264 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8267 // When using INSERTPS we can zero any lane of the destination. Collect
8268 // the zero inputs into a mask and drop them from the lanes of V1 which
8269 // actually need to be present as inputs to the INSERTPS.
8270 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8272 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8273 bool InsertNeedsShuffle = false;
8275 for (int i = 0; i < 4; ++i)
8279 } else if (Mask[i] != i) {
8280 InsertNeedsShuffle = true;
8285 // We don't want to use INSERTPS or other insertion techniques if it will
8286 // require shuffling anyways.
8287 if (!InsertNeedsShuffle) {
8288 // If all of V1 is zeroable, replace it with undef.
8289 if ((ZMask | 1 << V2Index) == 0xF)
8290 V1 = DAG.getUNDEF(MVT::v4f32);
8292 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8293 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8295 // Insert the V2 element into the desired position.
8296 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8297 DAG.getConstant(InsertPSMask, MVT::i8));
8301 // Otherwise fall back to a SHUFPS lowering strategy.
8302 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8305 /// \brief Lower 4-lane i32 vector shuffles.
8307 /// We try to handle these with integer-domain shuffles where we can, but for
8308 /// blends we use the floating point domain blend instructions.
8309 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8310 const X86Subtarget *Subtarget,
8311 SelectionDAG &DAG) {
8313 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8314 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8315 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8316 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8317 ArrayRef<int> Mask = SVOp->getMask();
8318 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8320 // Whenever we can lower this as a zext, that instruction is strictly faster
8321 // than any alternative. It also allows us to fold memory operands into the
8322 // shuffle in many cases.
8323 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8324 Mask, Subtarget, DAG))
8328 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8330 if (NumV2Elements == 0) {
8331 // Check for being able to broadcast a single element.
8332 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8333 Mask, Subtarget, DAG))
8336 // Straight shuffle of a single input vector. For everything from SSE2
8337 // onward this has a single fast instruction with no scary immediates.
8338 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8339 // but we aren't actually going to use the UNPCK instruction because doing
8340 // so prevents folding a load into this instruction or making a copy.
8341 const int UnpackLoMask[] = {0, 0, 1, 1};
8342 const int UnpackHiMask[] = {2, 2, 3, 3};
8343 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8344 Mask = UnpackLoMask;
8345 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8346 Mask = UnpackHiMask;
8348 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8349 getV4X86ShuffleImm8ForMask(Mask, DAG));
8352 // There are special ways we can lower some single-element blends.
8353 if (NumV2Elements == 1)
8354 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8355 Mask, Subtarget, DAG))
8358 // Use dedicated unpack instructions for masks that match their pattern.
8359 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8360 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8361 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8362 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8364 if (Subtarget->hasSSE41())
8365 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8369 // Try to use rotation instructions if available.
8370 if (Subtarget->hasSSSE3())
8371 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8372 DL, MVT::v4i32, V1, V2, Mask, DAG))
8375 // We implement this with SHUFPS because it can blend from two vectors.
8376 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8377 // up the inputs, bypassing domain shift penalties that we would encur if we
8378 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8380 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8381 DAG.getVectorShuffle(
8383 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8384 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8387 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8388 /// shuffle lowering, and the most complex part.
8390 /// The lowering strategy is to try to form pairs of input lanes which are
8391 /// targeted at the same half of the final vector, and then use a dword shuffle
8392 /// to place them onto the right half, and finally unpack the paired lanes into
8393 /// their final position.
8395 /// The exact breakdown of how to form these dword pairs and align them on the
8396 /// correct sides is really tricky. See the comments within the function for
8397 /// more of the details.
8398 static SDValue lowerV8I16SingleInputVectorShuffle(
8399 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8400 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8401 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8402 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8403 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8405 SmallVector<int, 4> LoInputs;
8406 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8407 [](int M) { return M >= 0; });
8408 std::sort(LoInputs.begin(), LoInputs.end());
8409 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8410 SmallVector<int, 4> HiInputs;
8411 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8412 [](int M) { return M >= 0; });
8413 std::sort(HiInputs.begin(), HiInputs.end());
8414 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8416 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8417 int NumHToL = LoInputs.size() - NumLToL;
8419 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8420 int NumHToH = HiInputs.size() - NumLToH;
8421 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8422 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8423 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8424 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8426 // Check for being able to broadcast a single element.
8427 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8428 Mask, Subtarget, DAG))
8431 // Use dedicated unpack instructions for masks that match their pattern.
8432 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8433 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8434 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8435 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8437 // Try to use rotation instructions if available.
8438 if (Subtarget->hasSSSE3())
8439 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8440 DL, MVT::v8i16, V, V, Mask, DAG))
8443 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8444 // such inputs we can swap two of the dwords across the half mark and end up
8445 // with <=2 inputs to each half in each half. Once there, we can fall through
8446 // to the generic code below. For example:
8448 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8449 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8451 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8452 // and an existing 2-into-2 on the other half. In this case we may have to
8453 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8454 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8455 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8456 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8457 // half than the one we target for fixing) will be fixed when we re-enter this
8458 // path. We will also combine away any sequence of PSHUFD instructions that
8459 // result into a single instruction. Here is an example of the tricky case:
8461 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8462 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8464 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8466 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8467 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8469 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8470 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8472 // The result is fine to be handled by the generic logic.
8473 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8474 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8475 int AOffset, int BOffset) {
8476 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8477 "Must call this with A having 3 or 1 inputs from the A half.");
8478 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8479 "Must call this with B having 1 or 3 inputs from the B half.");
8480 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8481 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8483 // Compute the index of dword with only one word among the three inputs in
8484 // a half by taking the sum of the half with three inputs and subtracting
8485 // the sum of the actual three inputs. The difference is the remaining
8488 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8489 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8490 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8491 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8492 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8493 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8494 int TripleNonInputIdx =
8495 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8496 TripleDWord = TripleNonInputIdx / 2;
8498 // We use xor with one to compute the adjacent DWord to whichever one the
8500 OneInputDWord = (OneInput / 2) ^ 1;
8502 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8503 // and BToA inputs. If there is also such a problem with the BToB and AToB
8504 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8505 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8506 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8507 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8508 // Compute how many inputs will be flipped by swapping these DWords. We
8510 // to balance this to ensure we don't form a 3-1 shuffle in the other
8512 int NumFlippedAToBInputs =
8513 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8514 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8515 int NumFlippedBToBInputs =
8516 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8517 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8518 if ((NumFlippedAToBInputs == 1 &&
8519 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8520 (NumFlippedBToBInputs == 1 &&
8521 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8522 // We choose whether to fix the A half or B half based on whether that
8523 // half has zero flipped inputs. At zero, we may not be able to fix it
8524 // with that half. We also bias towards fixing the B half because that
8525 // will more commonly be the high half, and we have to bias one way.
8526 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8527 ArrayRef<int> Inputs) {
8528 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8529 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8530 PinnedIdx ^ 1) != Inputs.end();
8531 // Determine whether the free index is in the flipped dword or the
8532 // unflipped dword based on where the pinned index is. We use this bit
8533 // in an xor to conditionally select the adjacent dword.
8534 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8535 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8536 FixFreeIdx) != Inputs.end();
8537 if (IsFixIdxInput == IsFixFreeIdxInput)
8539 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8540 FixFreeIdx) != Inputs.end();
8541 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8542 "We need to be changing the number of flipped inputs!");
8543 int PSHUFHalfMask[] = {0, 1, 2, 3};
8544 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8545 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8547 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8550 if (M != -1 && M == FixIdx)
8552 else if (M != -1 && M == FixFreeIdx)
8555 if (NumFlippedBToBInputs != 0) {
8557 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8558 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8560 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8562 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8563 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8568 int PSHUFDMask[] = {0, 1, 2, 3};
8569 PSHUFDMask[ADWord] = BDWord;
8570 PSHUFDMask[BDWord] = ADWord;
8571 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8572 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8573 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8574 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8576 // Adjust the mask to match the new locations of A and B.
8578 if (M != -1 && M/2 == ADWord)
8579 M = 2 * BDWord + M % 2;
8580 else if (M != -1 && M/2 == BDWord)
8581 M = 2 * ADWord + M % 2;
8583 // Recurse back into this routine to re-compute state now that this isn't
8584 // a 3 and 1 problem.
8585 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8588 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8589 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8590 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8591 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8593 // At this point there are at most two inputs to the low and high halves from
8594 // each half. That means the inputs can always be grouped into dwords and
8595 // those dwords can then be moved to the correct half with a dword shuffle.
8596 // We use at most one low and one high word shuffle to collect these paired
8597 // inputs into dwords, and finally a dword shuffle to place them.
8598 int PSHUFLMask[4] = {-1, -1, -1, -1};
8599 int PSHUFHMask[4] = {-1, -1, -1, -1};
8600 int PSHUFDMask[4] = {-1, -1, -1, -1};
8602 // First fix the masks for all the inputs that are staying in their
8603 // original halves. This will then dictate the targets of the cross-half
8605 auto fixInPlaceInputs =
8606 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8607 MutableArrayRef<int> SourceHalfMask,
8608 MutableArrayRef<int> HalfMask, int HalfOffset) {
8609 if (InPlaceInputs.empty())
8611 if (InPlaceInputs.size() == 1) {
8612 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8613 InPlaceInputs[0] - HalfOffset;
8614 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8617 if (IncomingInputs.empty()) {
8618 // Just fix all of the in place inputs.
8619 for (int Input : InPlaceInputs) {
8620 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8621 PSHUFDMask[Input / 2] = Input / 2;
8626 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8627 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8628 InPlaceInputs[0] - HalfOffset;
8629 // Put the second input next to the first so that they are packed into
8630 // a dword. We find the adjacent index by toggling the low bit.
8631 int AdjIndex = InPlaceInputs[0] ^ 1;
8632 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8633 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8634 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8636 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8637 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8639 // Now gather the cross-half inputs and place them into a free dword of
8640 // their target half.
8641 // FIXME: This operation could almost certainly be simplified dramatically to
8642 // look more like the 3-1 fixing operation.
8643 auto moveInputsToRightHalf = [&PSHUFDMask](
8644 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8645 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8646 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8648 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8649 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8651 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8653 int LowWord = Word & ~1;
8654 int HighWord = Word | 1;
8655 return isWordClobbered(SourceHalfMask, LowWord) ||
8656 isWordClobbered(SourceHalfMask, HighWord);
8659 if (IncomingInputs.empty())
8662 if (ExistingInputs.empty()) {
8663 // Map any dwords with inputs from them into the right half.
8664 for (int Input : IncomingInputs) {
8665 // If the source half mask maps over the inputs, turn those into
8666 // swaps and use the swapped lane.
8667 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8668 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8669 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8670 Input - SourceOffset;
8671 // We have to swap the uses in our half mask in one sweep.
8672 for (int &M : HalfMask)
8673 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8675 else if (M == Input)
8676 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8678 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8679 Input - SourceOffset &&
8680 "Previous placement doesn't match!");
8682 // Note that this correctly re-maps both when we do a swap and when
8683 // we observe the other side of the swap above. We rely on that to
8684 // avoid swapping the members of the input list directly.
8685 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8688 // Map the input's dword into the correct half.
8689 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8690 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8692 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8694 "Previous placement doesn't match!");
8697 // And just directly shift any other-half mask elements to be same-half
8698 // as we will have mirrored the dword containing the element into the
8699 // same position within that half.
8700 for (int &M : HalfMask)
8701 if (M >= SourceOffset && M < SourceOffset + 4) {
8702 M = M - SourceOffset + DestOffset;
8703 assert(M >= 0 && "This should never wrap below zero!");
8708 // Ensure we have the input in a viable dword of its current half. This
8709 // is particularly tricky because the original position may be clobbered
8710 // by inputs being moved and *staying* in that half.
8711 if (IncomingInputs.size() == 1) {
8712 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8713 int InputFixed = std::find(std::begin(SourceHalfMask),
8714 std::end(SourceHalfMask), -1) -
8715 std::begin(SourceHalfMask) + SourceOffset;
8716 SourceHalfMask[InputFixed - SourceOffset] =
8717 IncomingInputs[0] - SourceOffset;
8718 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8720 IncomingInputs[0] = InputFixed;
8722 } else if (IncomingInputs.size() == 2) {
8723 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8724 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8725 // We have two non-adjacent or clobbered inputs we need to extract from
8726 // the source half. To do this, we need to map them into some adjacent
8727 // dword slot in the source mask.
8728 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8729 IncomingInputs[1] - SourceOffset};
8731 // If there is a free slot in the source half mask adjacent to one of
8732 // the inputs, place the other input in it. We use (Index XOR 1) to
8733 // compute an adjacent index.
8734 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8735 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8736 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8737 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8738 InputsFixed[1] = InputsFixed[0] ^ 1;
8739 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8740 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8741 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8742 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8743 InputsFixed[0] = InputsFixed[1] ^ 1;
8744 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8745 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8746 // The two inputs are in the same DWord but it is clobbered and the
8747 // adjacent DWord isn't used at all. Move both inputs to the free
8749 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8750 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8751 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8752 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8754 // The only way we hit this point is if there is no clobbering
8755 // (because there are no off-half inputs to this half) and there is no
8756 // free slot adjacent to one of the inputs. In this case, we have to
8757 // swap an input with a non-input.
8758 for (int i = 0; i < 4; ++i)
8759 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8760 "We can't handle any clobbers here!");
8761 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8762 "Cannot have adjacent inputs here!");
8764 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8765 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8767 // We also have to update the final source mask in this case because
8768 // it may need to undo the above swap.
8769 for (int &M : FinalSourceHalfMask)
8770 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8771 M = InputsFixed[1] + SourceOffset;
8772 else if (M == InputsFixed[1] + SourceOffset)
8773 M = (InputsFixed[0] ^ 1) + SourceOffset;
8775 InputsFixed[1] = InputsFixed[0] ^ 1;
8778 // Point everything at the fixed inputs.
8779 for (int &M : HalfMask)
8780 if (M == IncomingInputs[0])
8781 M = InputsFixed[0] + SourceOffset;
8782 else if (M == IncomingInputs[1])
8783 M = InputsFixed[1] + SourceOffset;
8785 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8786 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8789 llvm_unreachable("Unhandled input size!");
8792 // Now hoist the DWord down to the right half.
8793 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8794 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8795 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8796 for (int &M : HalfMask)
8797 for (int Input : IncomingInputs)
8799 M = FreeDWord * 2 + Input % 2;
8801 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8802 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8803 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8804 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8806 // Now enact all the shuffles we've computed to move the inputs into their
8808 if (!isNoopShuffleMask(PSHUFLMask))
8809 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8810 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8811 if (!isNoopShuffleMask(PSHUFHMask))
8812 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8813 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8814 if (!isNoopShuffleMask(PSHUFDMask))
8815 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8816 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8817 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8818 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8820 // At this point, each half should contain all its inputs, and we can then
8821 // just shuffle them into their final position.
8822 assert(std::count_if(LoMask.begin(), LoMask.end(),
8823 [](int M) { return M >= 4; }) == 0 &&
8824 "Failed to lift all the high half inputs to the low mask!");
8825 assert(std::count_if(HiMask.begin(), HiMask.end(),
8826 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8827 "Failed to lift all the low half inputs to the high mask!");
8829 // Do a half shuffle for the low mask.
8830 if (!isNoopShuffleMask(LoMask))
8831 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8832 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8834 // Do a half shuffle with the high mask after shifting its values down.
8835 for (int &M : HiMask)
8838 if (!isNoopShuffleMask(HiMask))
8839 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8840 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8845 /// \brief Detect whether the mask pattern should be lowered through
8848 /// This essentially tests whether viewing the mask as an interleaving of two
8849 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8850 /// lowering it through interleaving is a significantly better strategy.
8851 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8852 int NumEvenInputs[2] = {0, 0};
8853 int NumOddInputs[2] = {0, 0};
8854 int NumLoInputs[2] = {0, 0};
8855 int NumHiInputs[2] = {0, 0};
8856 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8860 int InputIdx = Mask[i] >= Size;
8863 ++NumLoInputs[InputIdx];
8865 ++NumHiInputs[InputIdx];
8868 ++NumEvenInputs[InputIdx];
8870 ++NumOddInputs[InputIdx];
8873 // The minimum number of cross-input results for both the interleaved and
8874 // split cases. If interleaving results in fewer cross-input results, return
8876 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8877 NumEvenInputs[0] + NumOddInputs[1]);
8878 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8879 NumLoInputs[0] + NumHiInputs[1]);
8880 return InterleavedCrosses < SplitCrosses;
8883 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8885 /// This strategy only works when the inputs from each vector fit into a single
8886 /// half of that vector, and generally there are not so many inputs as to leave
8887 /// the in-place shuffles required highly constrained (and thus expensive). It
8888 /// shifts all the inputs into a single side of both input vectors and then
8889 /// uses an unpack to interleave these inputs in a single vector. At that
8890 /// point, we will fall back on the generic single input shuffle lowering.
8891 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8893 MutableArrayRef<int> Mask,
8894 const X86Subtarget *Subtarget,
8895 SelectionDAG &DAG) {
8896 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8897 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8898 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8899 for (int i = 0; i < 8; ++i)
8900 if (Mask[i] >= 0 && Mask[i] < 4)
8901 LoV1Inputs.push_back(i);
8902 else if (Mask[i] >= 4 && Mask[i] < 8)
8903 HiV1Inputs.push_back(i);
8904 else if (Mask[i] >= 8 && Mask[i] < 12)
8905 LoV2Inputs.push_back(i);
8906 else if (Mask[i] >= 12)
8907 HiV2Inputs.push_back(i);
8909 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8910 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8913 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8914 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8915 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8917 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8918 HiV1Inputs.size() + HiV2Inputs.size();
8920 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8921 ArrayRef<int> HiInputs, bool MoveToLo,
8923 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8924 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8925 if (BadInputs.empty())
8928 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8929 int MoveOffset = MoveToLo ? 0 : 4;
8931 if (GoodInputs.empty()) {
8932 for (int BadInput : BadInputs) {
8933 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8934 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8937 if (GoodInputs.size() == 2) {
8938 // If the low inputs are spread across two dwords, pack them into
8940 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8941 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8942 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8943 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8945 // Otherwise pin the good inputs.
8946 for (int GoodInput : GoodInputs)
8947 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8950 if (BadInputs.size() == 2) {
8951 // If we have two bad inputs then there may be either one or two good
8952 // inputs fixed in place. Find a fixed input, and then find the *other*
8953 // two adjacent indices by using modular arithmetic.
8955 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8956 [](int M) { return M >= 0; }) -
8957 std::begin(MoveMask);
8959 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8960 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8961 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8962 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8963 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8964 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8965 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8967 assert(BadInputs.size() == 1 && "All sizes handled");
8968 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8969 std::end(MoveMask), -1) -
8970 std::begin(MoveMask);
8971 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8972 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8976 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8979 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8981 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8984 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8985 // cross-half traffic in the final shuffle.
8987 // Munge the mask to be a single-input mask after the unpack merges the
8991 M = 2 * (M % 4) + (M / 8);
8993 return DAG.getVectorShuffle(
8994 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8995 DL, MVT::v8i16, V1, V2),
8996 DAG.getUNDEF(MVT::v8i16), Mask);
8999 /// \brief Generic lowering of 8-lane i16 shuffles.
9001 /// This handles both single-input shuffles and combined shuffle/blends with
9002 /// two inputs. The single input shuffles are immediately delegated to
9003 /// a dedicated lowering routine.
9005 /// The blends are lowered in one of three fundamental ways. If there are few
9006 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9007 /// of the input is significantly cheaper when lowered as an interleaving of
9008 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9009 /// halves of the inputs separately (making them have relatively few inputs)
9010 /// and then concatenate them.
9011 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9012 const X86Subtarget *Subtarget,
9013 SelectionDAG &DAG) {
9015 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9016 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9017 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9018 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9019 ArrayRef<int> OrigMask = SVOp->getMask();
9020 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9021 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9022 MutableArrayRef<int> Mask(MaskStorage);
9024 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9026 // Whenever we can lower this as a zext, that instruction is strictly faster
9027 // than any alternative.
9028 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9029 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9032 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9033 auto isV2 = [](int M) { return M >= 8; };
9035 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9036 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9038 if (NumV2Inputs == 0)
9039 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9041 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9042 "to be V1-input shuffles.");
9044 // There are special ways we can lower some single-element blends.
9045 if (NumV2Inputs == 1)
9046 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9047 Mask, Subtarget, DAG))
9050 // Use dedicated unpack instructions for masks that match their pattern.
9051 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9052 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9053 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9054 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9056 if (Subtarget->hasSSE41())
9057 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9061 // Try to use rotation instructions if available.
9062 if (Subtarget->hasSSSE3())
9063 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9064 DL, MVT::v8i16, V1, V2, Mask, DAG))
9067 if (NumV1Inputs + NumV2Inputs <= 4)
9068 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9070 // Check whether an interleaving lowering is likely to be more efficient.
9071 // This isn't perfect but it is a strong heuristic that tends to work well on
9072 // the kinds of shuffles that show up in practice.
9074 // FIXME: Handle 1x, 2x, and 4x interleaving.
9075 if (shouldLowerAsInterleaving(Mask)) {
9076 // FIXME: Figure out whether we should pack these into the low or high
9079 int EMask[8], OMask[8];
9080 for (int i = 0; i < 4; ++i) {
9081 EMask[i] = Mask[2*i];
9082 OMask[i] = Mask[2*i + 1];
9087 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9088 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9090 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9093 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9094 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9096 for (int i = 0; i < 4; ++i) {
9097 LoBlendMask[i] = Mask[i];
9098 HiBlendMask[i] = Mask[i + 4];
9101 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9102 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9103 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9104 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9106 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9107 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9110 /// \brief Check whether a compaction lowering can be done by dropping even
9111 /// elements and compute how many times even elements must be dropped.
9113 /// This handles shuffles which take every Nth element where N is a power of
9114 /// two. Example shuffle masks:
9116 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9117 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9118 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9119 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9120 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9121 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9123 /// Any of these lanes can of course be undef.
9125 /// This routine only supports N <= 3.
9126 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9129 /// \returns N above, or the number of times even elements must be dropped if
9130 /// there is such a number. Otherwise returns zero.
9131 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9132 // Figure out whether we're looping over two inputs or just one.
9133 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9135 // The modulus for the shuffle vector entries is based on whether this is
9136 // a single input or not.
9137 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9138 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9139 "We should only be called with masks with a power-of-2 size!");
9141 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9143 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9144 // and 2^3 simultaneously. This is because we may have ambiguity with
9145 // partially undef inputs.
9146 bool ViableForN[3] = {true, true, true};
9148 for (int i = 0, e = Mask.size(); i < e; ++i) {
9149 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9154 bool IsAnyViable = false;
9155 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9156 if (ViableForN[j]) {
9159 // The shuffle mask must be equal to (i * 2^N) % M.
9160 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9163 ViableForN[j] = false;
9165 // Early exit if we exhaust the possible powers of two.
9170 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9174 // Return 0 as there is no viable power of two.
9178 /// \brief Generic lowering of v16i8 shuffles.
9180 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9181 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9182 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9183 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9185 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9186 const X86Subtarget *Subtarget,
9187 SelectionDAG &DAG) {
9189 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9190 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9191 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9192 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9193 ArrayRef<int> OrigMask = SVOp->getMask();
9194 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9196 // Try to use rotation instructions if available.
9197 if (Subtarget->hasSSSE3())
9198 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9199 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9202 // Try to use a zext lowering.
9203 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9204 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9207 int MaskStorage[16] = {
9208 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9209 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9210 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9211 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9212 MutableArrayRef<int> Mask(MaskStorage);
9213 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9214 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9217 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9219 // For single-input shuffles, there are some nicer lowering tricks we can use.
9220 if (NumV2Elements == 0) {
9221 // Check for being able to broadcast a single element.
9222 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9223 Mask, Subtarget, DAG))
9226 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9227 // Notably, this handles splat and partial-splat shuffles more efficiently.
9228 // However, it only makes sense if the pre-duplication shuffle simplifies
9229 // things significantly. Currently, this means we need to be able to
9230 // express the pre-duplication shuffle as an i16 shuffle.
9232 // FIXME: We should check for other patterns which can be widened into an
9233 // i16 shuffle as well.
9234 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9235 for (int i = 0; i < 16; i += 2)
9236 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9241 auto tryToWidenViaDuplication = [&]() -> SDValue {
9242 if (!canWidenViaDuplication(Mask))
9244 SmallVector<int, 4> LoInputs;
9245 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9246 [](int M) { return M >= 0 && M < 8; });
9247 std::sort(LoInputs.begin(), LoInputs.end());
9248 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9250 SmallVector<int, 4> HiInputs;
9251 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9252 [](int M) { return M >= 8; });
9253 std::sort(HiInputs.begin(), HiInputs.end());
9254 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9257 bool TargetLo = LoInputs.size() >= HiInputs.size();
9258 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9259 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9261 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9262 SmallDenseMap<int, int, 8> LaneMap;
9263 for (int I : InPlaceInputs) {
9264 PreDupI16Shuffle[I/2] = I/2;
9267 int j = TargetLo ? 0 : 4, je = j + 4;
9268 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9269 // Check if j is already a shuffle of this input. This happens when
9270 // there are two adjacent bytes after we move the low one.
9271 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9272 // If we haven't yet mapped the input, search for a slot into which
9274 while (j < je && PreDupI16Shuffle[j] != -1)
9278 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9281 // Map this input with the i16 shuffle.
9282 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9285 // Update the lane map based on the mapping we ended up with.
9286 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9289 ISD::BITCAST, DL, MVT::v16i8,
9290 DAG.getVectorShuffle(MVT::v8i16, DL,
9291 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9292 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9294 // Unpack the bytes to form the i16s that will be shuffled into place.
9295 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9296 MVT::v16i8, V1, V1);
9298 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9299 for (int i = 0; i < 16; ++i)
9300 if (Mask[i] != -1) {
9301 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9302 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9303 if (PostDupI16Shuffle[i / 2] == -1)
9304 PostDupI16Shuffle[i / 2] = MappedMask;
9306 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9307 "Conflicting entrties in the original shuffle!");
9310 ISD::BITCAST, DL, MVT::v16i8,
9311 DAG.getVectorShuffle(MVT::v8i16, DL,
9312 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9313 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9315 if (SDValue V = tryToWidenViaDuplication())
9319 // Check whether an interleaving lowering is likely to be more efficient.
9320 // This isn't perfect but it is a strong heuristic that tends to work well on
9321 // the kinds of shuffles that show up in practice.
9323 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9324 if (shouldLowerAsInterleaving(Mask)) {
9325 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9326 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9328 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9329 return (M >= 8 && M < 16) || M >= 24;
9331 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9332 -1, -1, -1, -1, -1, -1, -1, -1};
9333 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9334 -1, -1, -1, -1, -1, -1, -1, -1};
9335 bool UnpackLo = NumLoHalf >= NumHiHalf;
9336 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9337 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9338 for (int i = 0; i < 8; ++i) {
9339 TargetEMask[i] = Mask[2 * i];
9340 TargetOMask[i] = Mask[2 * i + 1];
9343 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9344 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9346 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9347 MVT::v16i8, Evens, Odds);
9350 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9351 // with PSHUFB. It is important to do this before we attempt to generate any
9352 // blends but after all of the single-input lowerings. If the single input
9353 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9354 // want to preserve that and we can DAG combine any longer sequences into
9355 // a PSHUFB in the end. But once we start blending from multiple inputs,
9356 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9357 // and there are *very* few patterns that would actually be faster than the
9358 // PSHUFB approach because of its ability to zero lanes.
9360 // FIXME: The only exceptions to the above are blends which are exact
9361 // interleavings with direct instructions supporting them. We currently don't
9362 // handle those well here.
9363 if (Subtarget->hasSSSE3()) {
9366 for (int i = 0; i < 16; ++i)
9367 if (Mask[i] == -1) {
9368 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9370 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9372 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9374 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9375 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9376 if (isSingleInputShuffleMask(Mask))
9377 return V1; // Single inputs are easy.
9379 // Otherwise, blend the two.
9380 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9381 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9382 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9385 // There are special ways we can lower some single-element blends.
9386 if (NumV2Elements == 1)
9387 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9388 Mask, Subtarget, DAG))
9391 // Check whether a compaction lowering can be done. This handles shuffles
9392 // which take every Nth element for some even N. See the helper function for
9395 // We special case these as they can be particularly efficiently handled with
9396 // the PACKUSB instruction on x86 and they show up in common patterns of
9397 // rearranging bytes to truncate wide elements.
9398 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9399 // NumEvenDrops is the power of two stride of the elements. Another way of
9400 // thinking about it is that we need to drop the even elements this many
9401 // times to get the original input.
9402 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9404 // First we need to zero all the dropped bytes.
9405 assert(NumEvenDrops <= 3 &&
9406 "No support for dropping even elements more than 3 times.");
9407 // We use the mask type to pick which bytes are preserved based on how many
9408 // elements are dropped.
9409 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9410 SDValue ByteClearMask =
9411 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9412 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9413 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9415 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9417 // Now pack things back together.
9418 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9419 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9420 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9421 for (int i = 1; i < NumEvenDrops; ++i) {
9422 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9423 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9429 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9430 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9431 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9432 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9434 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9435 MutableArrayRef<int> V1HalfBlendMask,
9436 MutableArrayRef<int> V2HalfBlendMask) {
9437 for (int i = 0; i < 8; ++i)
9438 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9439 V1HalfBlendMask[i] = HalfMask[i];
9441 } else if (HalfMask[i] >= 16) {
9442 V2HalfBlendMask[i] = HalfMask[i] - 16;
9443 HalfMask[i] = i + 8;
9446 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9447 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9449 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9451 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9452 MutableArrayRef<int> HiBlendMask) {
9454 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9455 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9457 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9458 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9459 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9460 [](int M) { return M >= 0 && M % 2 == 1; })) {
9461 // Use a mask to drop the high bytes.
9462 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9463 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9464 DAG.getConstant(0x00FF, MVT::v8i16));
9466 // This will be a single vector shuffle instead of a blend so nuke V2.
9467 V2 = DAG.getUNDEF(MVT::v8i16);
9469 // Squash the masks to point directly into V1.
9470 for (int &M : LoBlendMask)
9473 for (int &M : HiBlendMask)
9477 // Otherwise just unpack the low half of V into V1 and the high half into
9478 // V2 so that we can blend them as i16s.
9479 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9480 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9481 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9482 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9485 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9486 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9487 return std::make_pair(BlendedLo, BlendedHi);
9489 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9490 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9491 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9493 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9494 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9496 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9499 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9501 /// This routine breaks down the specific type of 128-bit shuffle and
9502 /// dispatches to the lowering routines accordingly.
9503 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9504 MVT VT, const X86Subtarget *Subtarget,
9505 SelectionDAG &DAG) {
9506 switch (VT.SimpleTy) {
9508 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9510 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9512 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9514 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9516 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9518 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9521 llvm_unreachable("Unimplemented!");
9525 /// \brief Helper function to test whether a shuffle mask could be
9526 /// simplified by widening the elements being shuffled.
9528 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9529 /// leaves it in an unspecified state.
9531 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9532 /// shuffle masks. The latter have the special property of a '-2' representing
9533 /// a zero-ed lane of a vector.
9534 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9535 SmallVectorImpl<int> &WidenedMask) {
9536 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9537 // If both elements are undef, its trivial.
9538 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9539 WidenedMask.push_back(SM_SentinelUndef);
9543 // Check for an undef mask and a mask value properly aligned to fit with
9544 // a pair of values. If we find such a case, use the non-undef mask's value.
9545 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9546 WidenedMask.push_back(Mask[i + 1] / 2);
9549 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9550 WidenedMask.push_back(Mask[i] / 2);
9554 // When zeroing, we need to spread the zeroing across both lanes to widen.
9555 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9556 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9557 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9558 WidenedMask.push_back(SM_SentinelZero);
9564 // Finally check if the two mask values are adjacent and aligned with
9566 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9567 WidenedMask.push_back(Mask[i] / 2);
9571 // Otherwise we can't safely widen the elements used in this shuffle.
9574 assert(WidenedMask.size() == Mask.size() / 2 &&
9575 "Incorrect size of mask after widening the elements!");
9580 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9582 /// This routine just extracts two subvectors, shuffles them independently, and
9583 /// then concatenates them back together. This should work effectively with all
9584 /// AVX vector shuffle types.
9585 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9586 SDValue V2, ArrayRef<int> Mask,
9587 SelectionDAG &DAG) {
9588 assert(VT.getSizeInBits() >= 256 &&
9589 "Only for 256-bit or wider vector shuffles!");
9590 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9591 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9593 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9594 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9596 int NumElements = VT.getVectorNumElements();
9597 int SplitNumElements = NumElements / 2;
9598 MVT ScalarVT = VT.getScalarType();
9599 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9601 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9602 DAG.getIntPtrConstant(0));
9603 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9604 DAG.getIntPtrConstant(SplitNumElements));
9605 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9606 DAG.getIntPtrConstant(0));
9607 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9608 DAG.getIntPtrConstant(SplitNumElements));
9610 // Now create two 4-way blends of these half-width vectors.
9611 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9612 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9613 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9614 for (int i = 0; i < SplitNumElements; ++i) {
9615 int M = HalfMask[i];
9616 if (M >= NumElements) {
9617 if (M >= NumElements + SplitNumElements)
9621 V2BlendMask.push_back(M - NumElements);
9622 V1BlendMask.push_back(-1);
9623 BlendMask.push_back(SplitNumElements + i);
9624 } else if (M >= 0) {
9625 if (M >= SplitNumElements)
9629 V2BlendMask.push_back(-1);
9630 V1BlendMask.push_back(M);
9631 BlendMask.push_back(i);
9633 V2BlendMask.push_back(-1);
9634 V1BlendMask.push_back(-1);
9635 BlendMask.push_back(-1);
9639 // Because the lowering happens after all combining takes place, we need to
9640 // manually combine these blend masks as much as possible so that we create
9641 // a minimal number of high-level vector shuffle nodes.
9643 // First try just blending the halves of V1 or V2.
9644 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9645 return DAG.getUNDEF(SplitVT);
9646 if (!UseLoV2 && !UseHiV2)
9647 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9648 if (!UseLoV1 && !UseHiV1)
9649 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9651 SDValue V1Blend, V2Blend;
9652 if (UseLoV1 && UseHiV1) {
9654 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9656 // We only use half of V1 so map the usage down into the final blend mask.
9657 V1Blend = UseLoV1 ? LoV1 : HiV1;
9658 for (int i = 0; i < SplitNumElements; ++i)
9659 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9660 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9662 if (UseLoV2 && UseHiV2) {
9664 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9666 // We only use half of V2 so map the usage down into the final blend mask.
9667 V2Blend = UseLoV2 ? LoV2 : HiV2;
9668 for (int i = 0; i < SplitNumElements; ++i)
9669 if (BlendMask[i] >= SplitNumElements)
9670 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9672 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9674 SDValue Lo = HalfBlend(LoMask);
9675 SDValue Hi = HalfBlend(HiMask);
9676 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9679 /// \brief Either split a vector in halves or decompose the shuffles and the
9682 /// This is provided as a good fallback for many lowerings of non-single-input
9683 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9684 /// between splitting the shuffle into 128-bit components and stitching those
9685 /// back together vs. extracting the single-input shuffles and blending those
9687 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9688 SDValue V2, ArrayRef<int> Mask,
9689 SelectionDAG &DAG) {
9690 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9691 "lower single-input shuffles as it "
9692 "could then recurse on itself.");
9693 int Size = Mask.size();
9695 // If this can be modeled as a broadcast of two elements followed by a blend,
9696 // prefer that lowering. This is especially important because broadcasts can
9697 // often fold with memory operands.
9698 auto DoBothBroadcast = [&] {
9699 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9702 if (V2BroadcastIdx == -1)
9703 V2BroadcastIdx = M - Size;
9704 else if (M - Size != V2BroadcastIdx)
9706 } else if (M >= 0) {
9707 if (V1BroadcastIdx == -1)
9709 else if (M != V1BroadcastIdx)
9714 if (DoBothBroadcast())
9715 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9718 // If the inputs all stem from a single 128-bit lane of each input, then we
9719 // split them rather than blending because the split will decompose to
9720 // unusually few instructions.
9721 int LaneCount = VT.getSizeInBits() / 128;
9722 int LaneSize = Size / LaneCount;
9723 SmallBitVector LaneInputs[2];
9724 LaneInputs[0].resize(LaneCount, false);
9725 LaneInputs[1].resize(LaneCount, false);
9726 for (int i = 0; i < Size; ++i)
9728 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9729 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9730 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9732 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9733 // that the decomposed single-input shuffles don't end up here.
9734 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9737 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9738 /// a permutation and blend of those lanes.
9740 /// This essentially blends the out-of-lane inputs to each lane into the lane
9741 /// from a permuted copy of the vector. This lowering strategy results in four
9742 /// instructions in the worst case for a single-input cross lane shuffle which
9743 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9744 /// of. Special cases for each particular shuffle pattern should be handled
9745 /// prior to trying this lowering.
9746 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9747 SDValue V1, SDValue V2,
9749 SelectionDAG &DAG) {
9750 // FIXME: This should probably be generalized for 512-bit vectors as well.
9751 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9752 int LaneSize = Mask.size() / 2;
9754 // If there are only inputs from one 128-bit lane, splitting will in fact be
9755 // less expensive. The flags track wether the given lane contains an element
9756 // that crosses to another lane.
9757 bool LaneCrossing[2] = {false, false};
9758 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9759 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9760 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9761 if (!LaneCrossing[0] || !LaneCrossing[1])
9762 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9764 if (isSingleInputShuffleMask(Mask)) {
9765 SmallVector<int, 32> FlippedBlendMask;
9766 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9767 FlippedBlendMask.push_back(
9768 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9770 : Mask[i] % LaneSize +
9771 (i / LaneSize) * LaneSize + Size));
9773 // Flip the vector, and blend the results which should now be in-lane. The
9774 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9775 // 5 for the high source. The value 3 selects the high half of source 2 and
9776 // the value 2 selects the low half of source 2. We only use source 2 to
9777 // allow folding it into a memory operand.
9778 unsigned PERMMask = 3 | 2 << 4;
9779 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9780 V1, DAG.getConstant(PERMMask, MVT::i8));
9781 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9784 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9785 // will be handled by the above logic and a blend of the results, much like
9786 // other patterns in AVX.
9787 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9790 /// \brief Handle lowering 2-lane 128-bit shuffles.
9791 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9792 SDValue V2, ArrayRef<int> Mask,
9793 const X86Subtarget *Subtarget,
9794 SelectionDAG &DAG) {
9795 // Blends are faster and handle all the non-lane-crossing cases.
9796 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9800 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9801 VT.getVectorNumElements() / 2);
9802 // Check for patterns which can be matched with a single insert of a 128-bit
9804 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9805 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9806 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9807 DAG.getIntPtrConstant(0));
9808 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9809 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9810 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9812 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9813 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9814 DAG.getIntPtrConstant(0));
9815 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9816 DAG.getIntPtrConstant(2));
9817 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9820 // Otherwise form a 128-bit permutation.
9821 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9822 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9823 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9824 DAG.getConstant(PermMask, MVT::i8));
9827 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9829 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9830 /// isn't available.
9831 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9832 const X86Subtarget *Subtarget,
9833 SelectionDAG &DAG) {
9835 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9836 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9837 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9838 ArrayRef<int> Mask = SVOp->getMask();
9839 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9841 SmallVector<int, 4> WidenedMask;
9842 if (canWidenShuffleElements(Mask, WidenedMask))
9843 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9846 if (isSingleInputShuffleMask(Mask)) {
9847 // Check for being able to broadcast a single element.
9848 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
9849 Mask, Subtarget, DAG))
9852 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9853 // Non-half-crossing single input shuffles can be lowerid with an
9854 // interleaved permutation.
9855 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9856 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9857 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9858 DAG.getConstant(VPERMILPMask, MVT::i8));
9861 // With AVX2 we have direct support for this permutation.
9862 if (Subtarget->hasAVX2())
9863 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9864 getV4X86ShuffleImm8ForMask(Mask, DAG));
9866 // Otherwise, fall back.
9867 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9871 // X86 has dedicated unpack instructions that can handle specific blend
9872 // operations: UNPCKH and UNPCKL.
9873 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9874 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9875 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9876 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9878 // If we have a single input to the zero element, insert that into V1 if we
9879 // can do so cheaply.
9881 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9882 if (NumV2Elements == 1 && Mask[0] >= 4)
9883 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9884 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9887 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9891 // Check if the blend happens to exactly fit that of SHUFPD.
9892 if ((Mask[0] == -1 || Mask[0] < 2) &&
9893 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9894 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9895 (Mask[3] == -1 || Mask[3] >= 6)) {
9896 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9897 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9898 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9899 DAG.getConstant(SHUFPDMask, MVT::i8));
9901 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9902 (Mask[1] == -1 || Mask[1] < 2) &&
9903 (Mask[2] == -1 || Mask[2] >= 6) &&
9904 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9905 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9906 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9907 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9908 DAG.getConstant(SHUFPDMask, MVT::i8));
9911 // If we have AVX2 then we always want to lower with a blend because an v4 we
9912 // can fully permute the elements.
9913 if (Subtarget->hasAVX2())
9914 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9917 // Otherwise fall back on generic lowering.
9918 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9921 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9923 /// This routine is only called when we have AVX2 and thus a reasonable
9924 /// instruction set for v4i64 shuffling..
9925 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9926 const X86Subtarget *Subtarget,
9927 SelectionDAG &DAG) {
9929 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9930 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9931 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9932 ArrayRef<int> Mask = SVOp->getMask();
9933 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9934 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9936 SmallVector<int, 4> WidenedMask;
9937 if (canWidenShuffleElements(Mask, WidenedMask))
9938 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9941 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9945 // Check for being able to broadcast a single element.
9946 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
9947 Mask, Subtarget, DAG))
9950 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9951 // use lower latency instructions that will operate on both 128-bit lanes.
9952 SmallVector<int, 2> RepeatedMask;
9953 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9954 if (isSingleInputShuffleMask(Mask)) {
9955 int PSHUFDMask[] = {-1, -1, -1, -1};
9956 for (int i = 0; i < 2; ++i)
9957 if (RepeatedMask[i] >= 0) {
9958 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9959 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9962 ISD::BITCAST, DL, MVT::v4i64,
9963 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9964 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9965 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9968 // Use dedicated unpack instructions for masks that match their pattern.
9969 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9970 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9971 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9972 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9975 // AVX2 provides a direct instruction for permuting a single input across
9977 if (isSingleInputShuffleMask(Mask))
9978 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9979 getV4X86ShuffleImm8ForMask(Mask, DAG));
9981 // Otherwise fall back on generic blend lowering.
9982 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9986 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9988 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9989 /// isn't available.
9990 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9991 const X86Subtarget *Subtarget,
9992 SelectionDAG &DAG) {
9994 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9995 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9996 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9997 ArrayRef<int> Mask = SVOp->getMask();
9998 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10000 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10004 // Check for being able to broadcast a single element.
10005 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10006 Mask, Subtarget, DAG))
10009 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10010 // options to efficiently lower the shuffle.
10011 SmallVector<int, 4> RepeatedMask;
10012 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10013 assert(RepeatedMask.size() == 4 &&
10014 "Repeated masks must be half the mask width!");
10015 if (isSingleInputShuffleMask(Mask))
10016 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10017 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10019 // Use dedicated unpack instructions for masks that match their pattern.
10020 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10021 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10022 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10023 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10025 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10026 // have already handled any direct blends. We also need to squash the
10027 // repeated mask into a simulated v4f32 mask.
10028 for (int i = 0; i < 4; ++i)
10029 if (RepeatedMask[i] >= 8)
10030 RepeatedMask[i] -= 4;
10031 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10034 // If we have a single input shuffle with different shuffle patterns in the
10035 // two 128-bit lanes use the variable mask to VPERMILPS.
10036 if (isSingleInputShuffleMask(Mask)) {
10037 SDValue VPermMask[8];
10038 for (int i = 0; i < 8; ++i)
10039 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10040 : DAG.getConstant(Mask[i], MVT::i32);
10041 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10042 return DAG.getNode(
10043 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10044 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10046 if (Subtarget->hasAVX2())
10047 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10048 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10049 DAG.getNode(ISD::BUILD_VECTOR, DL,
10050 MVT::v8i32, VPermMask)),
10053 // Otherwise, fall back.
10054 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10058 // If we have AVX2 then we always want to lower with a blend because at v8 we
10059 // can fully permute the elements.
10060 if (Subtarget->hasAVX2())
10061 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10064 // Otherwise fall back on generic lowering.
10065 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10068 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10070 /// This routine is only called when we have AVX2 and thus a reasonable
10071 /// instruction set for v8i32 shuffling..
10072 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10073 const X86Subtarget *Subtarget,
10074 SelectionDAG &DAG) {
10076 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10077 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10078 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10079 ArrayRef<int> Mask = SVOp->getMask();
10080 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10081 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10083 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10087 // Check for being able to broadcast a single element.
10088 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10089 Mask, Subtarget, DAG))
10092 // If the shuffle mask is repeated in each 128-bit lane we can use more
10093 // efficient instructions that mirror the shuffles across the two 128-bit
10095 SmallVector<int, 4> RepeatedMask;
10096 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10097 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10098 if (isSingleInputShuffleMask(Mask))
10099 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10100 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10102 // Use dedicated unpack instructions for masks that match their pattern.
10103 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10104 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10105 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10106 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10109 // If the shuffle patterns aren't repeated but it is a single input, directly
10110 // generate a cross-lane VPERMD instruction.
10111 if (isSingleInputShuffleMask(Mask)) {
10112 SDValue VPermMask[8];
10113 for (int i = 0; i < 8; ++i)
10114 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10115 : DAG.getConstant(Mask[i], MVT::i32);
10116 return DAG.getNode(
10117 X86ISD::VPERMV, DL, MVT::v8i32,
10118 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10121 // Otherwise fall back on generic blend lowering.
10122 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10126 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10128 /// This routine is only called when we have AVX2 and thus a reasonable
10129 /// instruction set for v16i16 shuffling..
10130 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10131 const X86Subtarget *Subtarget,
10132 SelectionDAG &DAG) {
10134 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10135 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10136 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10137 ArrayRef<int> Mask = SVOp->getMask();
10138 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10139 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10141 // Check for being able to broadcast a single element.
10142 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10143 Mask, Subtarget, DAG))
10146 // There are no generalized cross-lane shuffle operations available on i16
10148 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10149 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10152 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10156 // Use dedicated unpack instructions for masks that match their pattern.
10157 if (isShuffleEquivalent(Mask,
10158 // First 128-bit lane:
10159 0, 16, 1, 17, 2, 18, 3, 19,
10160 // Second 128-bit lane:
10161 8, 24, 9, 25, 10, 26, 11, 27))
10162 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10163 if (isShuffleEquivalent(Mask,
10164 // First 128-bit lane:
10165 4, 20, 5, 21, 6, 22, 7, 23,
10166 // Second 128-bit lane:
10167 12, 28, 13, 29, 14, 30, 15, 31))
10168 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10170 if (isSingleInputShuffleMask(Mask)) {
10171 SDValue PSHUFBMask[32];
10172 for (int i = 0; i < 16; ++i) {
10173 if (Mask[i] == -1) {
10174 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10178 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10179 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10180 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10181 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10183 return DAG.getNode(
10184 ISD::BITCAST, DL, MVT::v16i16,
10186 X86ISD::PSHUFB, DL, MVT::v32i8,
10187 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10188 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10191 // Otherwise fall back on generic lowering.
10192 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10195 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10197 /// This routine is only called when we have AVX2 and thus a reasonable
10198 /// instruction set for v32i8 shuffling..
10199 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10200 const X86Subtarget *Subtarget,
10201 SelectionDAG &DAG) {
10203 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10204 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10205 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10206 ArrayRef<int> Mask = SVOp->getMask();
10207 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10208 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10210 // Check for being able to broadcast a single element.
10211 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10212 Mask, Subtarget, DAG))
10215 // There are no generalized cross-lane shuffle operations available on i8
10217 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10218 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10221 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10225 // Use dedicated unpack instructions for masks that match their pattern.
10226 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10228 if (isShuffleEquivalent(
10230 // First 128-bit lane:
10231 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10232 // Second 128-bit lane:
10233 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10234 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10235 if (isShuffleEquivalent(
10237 // First 128-bit lane:
10238 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10239 // Second 128-bit lane:
10240 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10241 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10243 if (isSingleInputShuffleMask(Mask)) {
10244 SDValue PSHUFBMask[32];
10245 for (int i = 0; i < 32; ++i)
10248 ? DAG.getUNDEF(MVT::i8)
10249 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10251 return DAG.getNode(
10252 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10253 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10256 // Otherwise fall back on generic lowering.
10257 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10260 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10262 /// This routine either breaks down the specific type of a 256-bit x86 vector
10263 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10264 /// together based on the available instructions.
10265 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10266 MVT VT, const X86Subtarget *Subtarget,
10267 SelectionDAG &DAG) {
10269 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10270 ArrayRef<int> Mask = SVOp->getMask();
10272 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10273 // check for those subtargets here and avoid much of the subtarget querying in
10274 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10275 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10276 // floating point types there eventually, just immediately cast everything to
10277 // a float and operate entirely in that domain.
10278 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10279 int ElementBits = VT.getScalarSizeInBits();
10280 if (ElementBits < 32)
10281 // No floating point type available, decompose into 128-bit vectors.
10282 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10284 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10285 VT.getVectorNumElements());
10286 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10287 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10288 return DAG.getNode(ISD::BITCAST, DL, VT,
10289 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10292 switch (VT.SimpleTy) {
10294 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10296 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10298 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10300 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10302 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10304 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10307 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10311 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10312 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10313 const X86Subtarget *Subtarget,
10314 SelectionDAG &DAG) {
10316 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10317 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10318 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10319 ArrayRef<int> Mask = SVOp->getMask();
10320 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10322 // FIXME: Implement direct support for this type!
10323 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10326 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10327 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10328 const X86Subtarget *Subtarget,
10329 SelectionDAG &DAG) {
10331 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10332 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10333 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10334 ArrayRef<int> Mask = SVOp->getMask();
10335 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10337 // FIXME: Implement direct support for this type!
10338 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10341 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10342 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10343 const X86Subtarget *Subtarget,
10344 SelectionDAG &DAG) {
10346 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10347 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10348 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10349 ArrayRef<int> Mask = SVOp->getMask();
10350 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10352 // FIXME: Implement direct support for this type!
10353 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10356 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10357 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10358 const X86Subtarget *Subtarget,
10359 SelectionDAG &DAG) {
10361 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10362 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10363 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10364 ArrayRef<int> Mask = SVOp->getMask();
10365 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10367 // FIXME: Implement direct support for this type!
10368 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10371 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10372 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10373 const X86Subtarget *Subtarget,
10374 SelectionDAG &DAG) {
10376 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10377 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10378 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10379 ArrayRef<int> Mask = SVOp->getMask();
10380 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10381 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10383 // FIXME: Implement direct support for this type!
10384 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10387 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10388 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10389 const X86Subtarget *Subtarget,
10390 SelectionDAG &DAG) {
10392 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10393 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10394 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10395 ArrayRef<int> Mask = SVOp->getMask();
10396 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10397 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10399 // FIXME: Implement direct support for this type!
10400 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10403 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10405 /// This routine either breaks down the specific type of a 512-bit x86 vector
10406 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10407 /// together based on the available instructions.
10408 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10409 MVT VT, const X86Subtarget *Subtarget,
10410 SelectionDAG &DAG) {
10412 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10413 ArrayRef<int> Mask = SVOp->getMask();
10414 assert(Subtarget->hasAVX512() &&
10415 "Cannot lower 512-bit vectors w/ basic ISA!");
10417 // Check for being able to broadcast a single element.
10418 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10419 Mask, Subtarget, DAG))
10422 // Dispatch to each element type for lowering. If we don't have supprot for
10423 // specific element type shuffles at 512 bits, immediately split them and
10424 // lower them. Each lowering routine of a given type is allowed to assume that
10425 // the requisite ISA extensions for that element type are available.
10426 switch (VT.SimpleTy) {
10428 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10430 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10432 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10434 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10436 if (Subtarget->hasBWI())
10437 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10440 if (Subtarget->hasBWI())
10441 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10445 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10448 // Otherwise fall back on splitting.
10449 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10452 /// \brief Top-level lowering for x86 vector shuffles.
10454 /// This handles decomposition, canonicalization, and lowering of all x86
10455 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10456 /// above in helper routines. The canonicalization attempts to widen shuffles
10457 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10458 /// s.t. only one of the two inputs needs to be tested, etc.
10459 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10460 SelectionDAG &DAG) {
10461 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10462 ArrayRef<int> Mask = SVOp->getMask();
10463 SDValue V1 = Op.getOperand(0);
10464 SDValue V2 = Op.getOperand(1);
10465 MVT VT = Op.getSimpleValueType();
10466 int NumElements = VT.getVectorNumElements();
10469 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10471 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10472 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10473 if (V1IsUndef && V2IsUndef)
10474 return DAG.getUNDEF(VT);
10476 // When we create a shuffle node we put the UNDEF node to second operand,
10477 // but in some cases the first operand may be transformed to UNDEF.
10478 // In this case we should just commute the node.
10480 return DAG.getCommutedVectorShuffle(*SVOp);
10482 // Check for non-undef masks pointing at an undef vector and make the masks
10483 // undef as well. This makes it easier to match the shuffle based solely on
10487 if (M >= NumElements) {
10488 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10489 for (int &M : NewMask)
10490 if (M >= NumElements)
10492 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10495 // Try to collapse shuffles into using a vector type with fewer elements but
10496 // wider element types. We cap this to not form integers or floating point
10497 // elements wider than 64 bits, but it might be interesting to form i128
10498 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10499 SmallVector<int, 16> WidenedMask;
10500 if (VT.getScalarSizeInBits() < 64 &&
10501 canWidenShuffleElements(Mask, WidenedMask)) {
10502 MVT NewEltVT = VT.isFloatingPoint()
10503 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10504 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10505 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10506 // Make sure that the new vector type is legal. For example, v2f64 isn't
10508 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10509 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10510 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10511 return DAG.getNode(ISD::BITCAST, dl, VT,
10512 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10516 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10517 for (int M : SVOp->getMask())
10519 ++NumUndefElements;
10520 else if (M < NumElements)
10525 // Commute the shuffle as needed such that more elements come from V1 than
10526 // V2. This allows us to match the shuffle pattern strictly on how many
10527 // elements come from V1 without handling the symmetric cases.
10528 if (NumV2Elements > NumV1Elements)
10529 return DAG.getCommutedVectorShuffle(*SVOp);
10531 // When the number of V1 and V2 elements are the same, try to minimize the
10532 // number of uses of V2 in the low half of the vector. When that is tied,
10533 // ensure that the sum of indices for V1 is equal to or lower than the sum
10535 if (NumV1Elements == NumV2Elements) {
10536 int LowV1Elements = 0, LowV2Elements = 0;
10537 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10538 if (M >= NumElements)
10542 if (LowV2Elements > LowV1Elements) {
10543 return DAG.getCommutedVectorShuffle(*SVOp);
10544 } else if (LowV2Elements == LowV1Elements) {
10545 int SumV1Indices = 0, SumV2Indices = 0;
10546 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10547 if (SVOp->getMask()[i] >= NumElements)
10549 else if (SVOp->getMask()[i] >= 0)
10551 if (SumV2Indices < SumV1Indices)
10552 return DAG.getCommutedVectorShuffle(*SVOp);
10556 // For each vector width, delegate to a specialized lowering routine.
10557 if (VT.getSizeInBits() == 128)
10558 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10560 if (VT.getSizeInBits() == 256)
10561 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10563 // Force AVX-512 vectors to be scalarized for now.
10564 // FIXME: Implement AVX-512 support!
10565 if (VT.getSizeInBits() == 512)
10566 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10568 llvm_unreachable("Unimplemented!");
10572 //===----------------------------------------------------------------------===//
10573 // Legacy vector shuffle lowering
10575 // This code is the legacy code handling vector shuffles until the above
10576 // replaces its functionality and performance.
10577 //===----------------------------------------------------------------------===//
10579 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10580 bool hasInt256, unsigned *MaskOut = nullptr) {
10581 MVT EltVT = VT.getVectorElementType();
10583 // There is no blend with immediate in AVX-512.
10584 if (VT.is512BitVector())
10587 if (!hasSSE41 || EltVT == MVT::i8)
10589 if (!hasInt256 && VT == MVT::v16i16)
10592 unsigned MaskValue = 0;
10593 unsigned NumElems = VT.getVectorNumElements();
10594 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10595 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10596 unsigned NumElemsInLane = NumElems / NumLanes;
10598 // Blend for v16i16 should be symetric for the both lanes.
10599 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10601 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10602 int EltIdx = MaskVals[i];
10604 if ((EltIdx < 0 || EltIdx == (int)i) &&
10605 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10608 if (((unsigned)EltIdx == (i + NumElems)) &&
10609 (SndLaneEltIdx < 0 ||
10610 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10611 MaskValue |= (1 << i);
10617 *MaskOut = MaskValue;
10621 // Try to lower a shuffle node into a simple blend instruction.
10622 // This function assumes isBlendMask returns true for this
10623 // SuffleVectorSDNode
10624 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10625 unsigned MaskValue,
10626 const X86Subtarget *Subtarget,
10627 SelectionDAG &DAG) {
10628 MVT VT = SVOp->getSimpleValueType(0);
10629 MVT EltVT = VT.getVectorElementType();
10630 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10631 Subtarget->hasInt256() && "Trying to lower a "
10632 "VECTOR_SHUFFLE to a Blend but "
10633 "with the wrong mask"));
10634 SDValue V1 = SVOp->getOperand(0);
10635 SDValue V2 = SVOp->getOperand(1);
10637 unsigned NumElems = VT.getVectorNumElements();
10639 // Convert i32 vectors to floating point if it is not AVX2.
10640 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10642 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10643 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10645 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10646 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10649 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10650 DAG.getConstant(MaskValue, MVT::i32));
10651 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10654 /// In vector type \p VT, return true if the element at index \p InputIdx
10655 /// falls on a different 128-bit lane than \p OutputIdx.
10656 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10657 unsigned OutputIdx) {
10658 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10659 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10662 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10663 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10664 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10665 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10667 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10668 SelectionDAG &DAG) {
10669 MVT VT = V1.getSimpleValueType();
10670 assert(VT.is128BitVector() || VT.is256BitVector());
10672 MVT EltVT = VT.getVectorElementType();
10673 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10674 unsigned NumElts = VT.getVectorNumElements();
10676 SmallVector<SDValue, 32> PshufbMask;
10677 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10678 int InputIdx = MaskVals[OutputIdx];
10679 unsigned InputByteIdx;
10681 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10682 InputByteIdx = 0x80;
10684 // Cross lane is not allowed.
10685 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10687 InputByteIdx = InputIdx * EltSizeInBytes;
10688 // Index is an byte offset within the 128-bit lane.
10689 InputByteIdx &= 0xf;
10692 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10693 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10694 if (InputByteIdx != 0x80)
10699 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10701 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10702 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10703 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10706 // v8i16 shuffles - Prefer shuffles in the following order:
10707 // 1. [all] pshuflw, pshufhw, optional move
10708 // 2. [ssse3] 1 x pshufb
10709 // 3. [ssse3] 2 x pshufb + 1 x por
10710 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10712 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10713 SelectionDAG &DAG) {
10714 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10715 SDValue V1 = SVOp->getOperand(0);
10716 SDValue V2 = SVOp->getOperand(1);
10718 SmallVector<int, 8> MaskVals;
10720 // Determine if more than 1 of the words in each of the low and high quadwords
10721 // of the result come from the same quadword of one of the two inputs. Undef
10722 // mask values count as coming from any quadword, for better codegen.
10724 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10725 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10726 unsigned LoQuad[] = { 0, 0, 0, 0 };
10727 unsigned HiQuad[] = { 0, 0, 0, 0 };
10728 // Indices of quads used.
10729 std::bitset<4> InputQuads;
10730 for (unsigned i = 0; i < 8; ++i) {
10731 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10732 int EltIdx = SVOp->getMaskElt(i);
10733 MaskVals.push_back(EltIdx);
10741 ++Quad[EltIdx / 4];
10742 InputQuads.set(EltIdx / 4);
10745 int BestLoQuad = -1;
10746 unsigned MaxQuad = 1;
10747 for (unsigned i = 0; i < 4; ++i) {
10748 if (LoQuad[i] > MaxQuad) {
10750 MaxQuad = LoQuad[i];
10754 int BestHiQuad = -1;
10756 for (unsigned i = 0; i < 4; ++i) {
10757 if (HiQuad[i] > MaxQuad) {
10759 MaxQuad = HiQuad[i];
10763 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10764 // of the two input vectors, shuffle them into one input vector so only a
10765 // single pshufb instruction is necessary. If there are more than 2 input
10766 // quads, disable the next transformation since it does not help SSSE3.
10767 bool V1Used = InputQuads[0] || InputQuads[1];
10768 bool V2Used = InputQuads[2] || InputQuads[3];
10769 if (Subtarget->hasSSSE3()) {
10770 if (InputQuads.count() == 2 && V1Used && V2Used) {
10771 BestLoQuad = InputQuads[0] ? 0 : 1;
10772 BestHiQuad = InputQuads[2] ? 2 : 3;
10774 if (InputQuads.count() > 2) {
10780 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10781 // the shuffle mask. If a quad is scored as -1, that means that it contains
10782 // words from all 4 input quadwords.
10784 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10786 BestLoQuad < 0 ? 0 : BestLoQuad,
10787 BestHiQuad < 0 ? 1 : BestHiQuad
10789 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10790 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10791 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10792 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10794 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10795 // source words for the shuffle, to aid later transformations.
10796 bool AllWordsInNewV = true;
10797 bool InOrder[2] = { true, true };
10798 for (unsigned i = 0; i != 8; ++i) {
10799 int idx = MaskVals[i];
10801 InOrder[i/4] = false;
10802 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10804 AllWordsInNewV = false;
10808 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10809 if (AllWordsInNewV) {
10810 for (int i = 0; i != 8; ++i) {
10811 int idx = MaskVals[i];
10814 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10815 if ((idx != i) && idx < 4)
10817 if ((idx != i) && idx > 3)
10826 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10827 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10828 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10829 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10830 unsigned TargetMask = 0;
10831 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10832 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10833 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10834 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10835 getShufflePSHUFLWImmediate(SVOp);
10836 V1 = NewV.getOperand(0);
10837 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10841 // Promote splats to a larger type which usually leads to more efficient code.
10842 // FIXME: Is this true if pshufb is available?
10843 if (SVOp->isSplat())
10844 return PromoteSplat(SVOp, DAG);
10846 // If we have SSSE3, and all words of the result are from 1 input vector,
10847 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10848 // is present, fall back to case 4.
10849 if (Subtarget->hasSSSE3()) {
10850 SmallVector<SDValue,16> pshufbMask;
10852 // If we have elements from both input vectors, set the high bit of the
10853 // shuffle mask element to zero out elements that come from V2 in the V1
10854 // mask, and elements that come from V1 in the V2 mask, so that the two
10855 // results can be OR'd together.
10856 bool TwoInputs = V1Used && V2Used;
10857 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10859 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10861 // Calculate the shuffle mask for the second input, shuffle it, and
10862 // OR it with the first shuffled input.
10863 CommuteVectorShuffleMask(MaskVals, 8);
10864 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10865 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10866 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10869 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10870 // and update MaskVals with new element order.
10871 std::bitset<8> InOrder;
10872 if (BestLoQuad >= 0) {
10873 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10874 for (int i = 0; i != 4; ++i) {
10875 int idx = MaskVals[i];
10878 } else if ((idx / 4) == BestLoQuad) {
10879 MaskV[i] = idx & 3;
10883 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10886 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10887 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10888 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10889 NewV.getOperand(0),
10890 getShufflePSHUFLWImmediate(SVOp), DAG);
10894 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10895 // and update MaskVals with the new element order.
10896 if (BestHiQuad >= 0) {
10897 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10898 for (unsigned i = 4; i != 8; ++i) {
10899 int idx = MaskVals[i];
10902 } else if ((idx / 4) == BestHiQuad) {
10903 MaskV[i] = (idx & 3) + 4;
10907 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10910 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10911 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10912 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10913 NewV.getOperand(0),
10914 getShufflePSHUFHWImmediate(SVOp), DAG);
10918 // In case BestHi & BestLo were both -1, which means each quadword has a word
10919 // from each of the four input quadwords, calculate the InOrder bitvector now
10920 // before falling through to the insert/extract cleanup.
10921 if (BestLoQuad == -1 && BestHiQuad == -1) {
10923 for (int i = 0; i != 8; ++i)
10924 if (MaskVals[i] < 0 || MaskVals[i] == i)
10928 // The other elements are put in the right place using pextrw and pinsrw.
10929 for (unsigned i = 0; i != 8; ++i) {
10932 int EltIdx = MaskVals[i];
10935 SDValue ExtOp = (EltIdx < 8) ?
10936 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10937 DAG.getIntPtrConstant(EltIdx)) :
10938 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10939 DAG.getIntPtrConstant(EltIdx - 8));
10940 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10941 DAG.getIntPtrConstant(i));
10946 /// \brief v16i16 shuffles
10948 /// FIXME: We only support generation of a single pshufb currently. We can
10949 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10950 /// well (e.g 2 x pshufb + 1 x por).
10952 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10953 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10954 SDValue V1 = SVOp->getOperand(0);
10955 SDValue V2 = SVOp->getOperand(1);
10958 if (V2.getOpcode() != ISD::UNDEF)
10961 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10962 return getPSHUFB(MaskVals, V1, dl, DAG);
10965 // v16i8 shuffles - Prefer shuffles in the following order:
10966 // 1. [ssse3] 1 x pshufb
10967 // 2. [ssse3] 2 x pshufb + 1 x por
10968 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10969 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10970 const X86Subtarget* Subtarget,
10971 SelectionDAG &DAG) {
10972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10973 SDValue V1 = SVOp->getOperand(0);
10974 SDValue V2 = SVOp->getOperand(1);
10976 ArrayRef<int> MaskVals = SVOp->getMask();
10978 // Promote splats to a larger type which usually leads to more efficient code.
10979 // FIXME: Is this true if pshufb is available?
10980 if (SVOp->isSplat())
10981 return PromoteSplat(SVOp, DAG);
10983 // If we have SSSE3, case 1 is generated when all result bytes come from
10984 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10985 // present, fall back to case 3.
10987 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10988 if (Subtarget->hasSSSE3()) {
10989 SmallVector<SDValue,16> pshufbMask;
10991 // If all result elements are from one input vector, then only translate
10992 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10994 // Otherwise, we have elements from both input vectors, and must zero out
10995 // elements that come from V2 in the first mask, and V1 in the second mask
10996 // so that we can OR them together.
10997 for (unsigned i = 0; i != 16; ++i) {
10998 int EltIdx = MaskVals[i];
10999 if (EltIdx < 0 || EltIdx >= 16)
11001 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11003 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11004 DAG.getNode(ISD::BUILD_VECTOR, dl,
11005 MVT::v16i8, pshufbMask));
11007 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11008 // the 2nd operand if it's undefined or zero.
11009 if (V2.getOpcode() == ISD::UNDEF ||
11010 ISD::isBuildVectorAllZeros(V2.getNode()))
11013 // Calculate the shuffle mask for the second input, shuffle it, and
11014 // OR it with the first shuffled input.
11015 pshufbMask.clear();
11016 for (unsigned i = 0; i != 16; ++i) {
11017 int EltIdx = MaskVals[i];
11018 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11019 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11021 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11022 DAG.getNode(ISD::BUILD_VECTOR, dl,
11023 MVT::v16i8, pshufbMask));
11024 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11027 // No SSSE3 - Calculate in place words and then fix all out of place words
11028 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11029 // the 16 different words that comprise the two doublequadword input vectors.
11030 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11031 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11033 for (int i = 0; i != 8; ++i) {
11034 int Elt0 = MaskVals[i*2];
11035 int Elt1 = MaskVals[i*2+1];
11037 // This word of the result is all undef, skip it.
11038 if (Elt0 < 0 && Elt1 < 0)
11041 // This word of the result is already in the correct place, skip it.
11042 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11045 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11046 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11049 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11050 // using a single extract together, load it and store it.
11051 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11052 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11053 DAG.getIntPtrConstant(Elt1 / 2));
11054 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11055 DAG.getIntPtrConstant(i));
11059 // If Elt1 is defined, extract it from the appropriate source. If the
11060 // source byte is not also odd, shift the extracted word left 8 bits
11061 // otherwise clear the bottom 8 bits if we need to do an or.
11063 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11064 DAG.getIntPtrConstant(Elt1 / 2));
11065 if ((Elt1 & 1) == 0)
11066 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11068 TLI.getShiftAmountTy(InsElt.getValueType())));
11069 else if (Elt0 >= 0)
11070 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11071 DAG.getConstant(0xFF00, MVT::i16));
11073 // If Elt0 is defined, extract it from the appropriate source. If the
11074 // source byte is not also even, shift the extracted word right 8 bits. If
11075 // Elt1 was also defined, OR the extracted values together before
11076 // inserting them in the result.
11078 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11079 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11080 if ((Elt0 & 1) != 0)
11081 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11083 TLI.getShiftAmountTy(InsElt0.getValueType())));
11084 else if (Elt1 >= 0)
11085 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11086 DAG.getConstant(0x00FF, MVT::i16));
11087 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11090 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11091 DAG.getIntPtrConstant(i));
11093 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11096 // v32i8 shuffles - Translate to VPSHUFB if possible.
11098 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11099 const X86Subtarget *Subtarget,
11100 SelectionDAG &DAG) {
11101 MVT VT = SVOp->getSimpleValueType(0);
11102 SDValue V1 = SVOp->getOperand(0);
11103 SDValue V2 = SVOp->getOperand(1);
11105 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11107 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11108 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11109 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11111 // VPSHUFB may be generated if
11112 // (1) one of input vector is undefined or zeroinitializer.
11113 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11114 // And (2) the mask indexes don't cross the 128-bit lane.
11115 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11116 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11119 if (V1IsAllZero && !V2IsAllZero) {
11120 CommuteVectorShuffleMask(MaskVals, 32);
11123 return getPSHUFB(MaskVals, V1, dl, DAG);
11126 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11127 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11128 /// done when every pair / quad of shuffle mask elements point to elements in
11129 /// the right sequence. e.g.
11130 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11132 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11133 SelectionDAG &DAG) {
11134 MVT VT = SVOp->getSimpleValueType(0);
11136 unsigned NumElems = VT.getVectorNumElements();
11139 switch (VT.SimpleTy) {
11140 default: llvm_unreachable("Unexpected!");
11143 return SDValue(SVOp, 0);
11144 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11145 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11146 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11147 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11148 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11149 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11152 SmallVector<int, 8> MaskVec;
11153 for (unsigned i = 0; i != NumElems; i += Scale) {
11155 for (unsigned j = 0; j != Scale; ++j) {
11156 int EltIdx = SVOp->getMaskElt(i+j);
11160 StartIdx = (EltIdx / Scale);
11161 if (EltIdx != (int)(StartIdx*Scale + j))
11164 MaskVec.push_back(StartIdx);
11167 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11168 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11169 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11172 /// getVZextMovL - Return a zero-extending vector move low node.
11174 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11175 SDValue SrcOp, SelectionDAG &DAG,
11176 const X86Subtarget *Subtarget, SDLoc dl) {
11177 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11178 LoadSDNode *LD = nullptr;
11179 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11180 LD = dyn_cast<LoadSDNode>(SrcOp);
11182 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11184 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11185 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11186 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11187 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11188 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11190 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11191 return DAG.getNode(ISD::BITCAST, dl, VT,
11192 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11193 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11195 SrcOp.getOperand(0)
11201 return DAG.getNode(ISD::BITCAST, dl, VT,
11202 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11203 DAG.getNode(ISD::BITCAST, dl,
11207 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11208 /// which could not be matched by any known target speficic shuffle
11210 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11212 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11213 if (NewOp.getNode())
11216 MVT VT = SVOp->getSimpleValueType(0);
11218 unsigned NumElems = VT.getVectorNumElements();
11219 unsigned NumLaneElems = NumElems / 2;
11222 MVT EltVT = VT.getVectorElementType();
11223 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11226 SmallVector<int, 16> Mask;
11227 for (unsigned l = 0; l < 2; ++l) {
11228 // Build a shuffle mask for the output, discovering on the fly which
11229 // input vectors to use as shuffle operands (recorded in InputUsed).
11230 // If building a suitable shuffle vector proves too hard, then bail
11231 // out with UseBuildVector set.
11232 bool UseBuildVector = false;
11233 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11234 unsigned LaneStart = l * NumLaneElems;
11235 for (unsigned i = 0; i != NumLaneElems; ++i) {
11236 // The mask element. This indexes into the input.
11237 int Idx = SVOp->getMaskElt(i+LaneStart);
11239 // the mask element does not index into any input vector.
11240 Mask.push_back(-1);
11244 // The input vector this mask element indexes into.
11245 int Input = Idx / NumLaneElems;
11247 // Turn the index into an offset from the start of the input vector.
11248 Idx -= Input * NumLaneElems;
11250 // Find or create a shuffle vector operand to hold this input.
11252 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11253 if (InputUsed[OpNo] == Input)
11254 // This input vector is already an operand.
11256 if (InputUsed[OpNo] < 0) {
11257 // Create a new operand for this input vector.
11258 InputUsed[OpNo] = Input;
11263 if (OpNo >= array_lengthof(InputUsed)) {
11264 // More than two input vectors used! Give up on trying to create a
11265 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11266 UseBuildVector = true;
11270 // Add the mask index for the new shuffle vector.
11271 Mask.push_back(Idx + OpNo * NumLaneElems);
11274 if (UseBuildVector) {
11275 SmallVector<SDValue, 16> SVOps;
11276 for (unsigned i = 0; i != NumLaneElems; ++i) {
11277 // The mask element. This indexes into the input.
11278 int Idx = SVOp->getMaskElt(i+LaneStart);
11280 SVOps.push_back(DAG.getUNDEF(EltVT));
11284 // The input vector this mask element indexes into.
11285 int Input = Idx / NumElems;
11287 // Turn the index into an offset from the start of the input vector.
11288 Idx -= Input * NumElems;
11290 // Extract the vector element by hand.
11291 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11292 SVOp->getOperand(Input),
11293 DAG.getIntPtrConstant(Idx)));
11296 // Construct the output using a BUILD_VECTOR.
11297 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11298 } else if (InputUsed[0] < 0) {
11299 // No input vectors were used! The result is undefined.
11300 Output[l] = DAG.getUNDEF(NVT);
11302 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11303 (InputUsed[0] % 2) * NumLaneElems,
11305 // If only one input was used, use an undefined vector for the other.
11306 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11307 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11308 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11309 // At least one input vector was used. Create a new shuffle vector.
11310 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11316 // Concatenate the result back
11317 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11320 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11321 /// 4 elements, and match them with several different shuffle types.
11323 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11324 SDValue V1 = SVOp->getOperand(0);
11325 SDValue V2 = SVOp->getOperand(1);
11327 MVT VT = SVOp->getSimpleValueType(0);
11329 assert(VT.is128BitVector() && "Unsupported vector size");
11331 std::pair<int, int> Locs[4];
11332 int Mask1[] = { -1, -1, -1, -1 };
11333 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11335 unsigned NumHi = 0;
11336 unsigned NumLo = 0;
11337 for (unsigned i = 0; i != 4; ++i) {
11338 int Idx = PermMask[i];
11340 Locs[i] = std::make_pair(-1, -1);
11342 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11344 Locs[i] = std::make_pair(0, NumLo);
11345 Mask1[NumLo] = Idx;
11348 Locs[i] = std::make_pair(1, NumHi);
11350 Mask1[2+NumHi] = Idx;
11356 if (NumLo <= 2 && NumHi <= 2) {
11357 // If no more than two elements come from either vector. This can be
11358 // implemented with two shuffles. First shuffle gather the elements.
11359 // The second shuffle, which takes the first shuffle as both of its
11360 // vector operands, put the elements into the right order.
11361 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11363 int Mask2[] = { -1, -1, -1, -1 };
11365 for (unsigned i = 0; i != 4; ++i)
11366 if (Locs[i].first != -1) {
11367 unsigned Idx = (i < 2) ? 0 : 4;
11368 Idx += Locs[i].first * 2 + Locs[i].second;
11372 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11375 if (NumLo == 3 || NumHi == 3) {
11376 // Otherwise, we must have three elements from one vector, call it X, and
11377 // one element from the other, call it Y. First, use a shufps to build an
11378 // intermediate vector with the one element from Y and the element from X
11379 // that will be in the same half in the final destination (the indexes don't
11380 // matter). Then, use a shufps to build the final vector, taking the half
11381 // containing the element from Y from the intermediate, and the other half
11384 // Normalize it so the 3 elements come from V1.
11385 CommuteVectorShuffleMask(PermMask, 4);
11389 // Find the element from V2.
11391 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11392 int Val = PermMask[HiIndex];
11399 Mask1[0] = PermMask[HiIndex];
11401 Mask1[2] = PermMask[HiIndex^1];
11403 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11405 if (HiIndex >= 2) {
11406 Mask1[0] = PermMask[0];
11407 Mask1[1] = PermMask[1];
11408 Mask1[2] = HiIndex & 1 ? 6 : 4;
11409 Mask1[3] = HiIndex & 1 ? 4 : 6;
11410 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11413 Mask1[0] = HiIndex & 1 ? 2 : 0;
11414 Mask1[1] = HiIndex & 1 ? 0 : 2;
11415 Mask1[2] = PermMask[2];
11416 Mask1[3] = PermMask[3];
11421 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11424 // Break it into (shuffle shuffle_hi, shuffle_lo).
11425 int LoMask[] = { -1, -1, -1, -1 };
11426 int HiMask[] = { -1, -1, -1, -1 };
11428 int *MaskPtr = LoMask;
11429 unsigned MaskIdx = 0;
11430 unsigned LoIdx = 0;
11431 unsigned HiIdx = 2;
11432 for (unsigned i = 0; i != 4; ++i) {
11439 int Idx = PermMask[i];
11441 Locs[i] = std::make_pair(-1, -1);
11442 } else if (Idx < 4) {
11443 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11444 MaskPtr[LoIdx] = Idx;
11447 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11448 MaskPtr[HiIdx] = Idx;
11453 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11454 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11455 int MaskOps[] = { -1, -1, -1, -1 };
11456 for (unsigned i = 0; i != 4; ++i)
11457 if (Locs[i].first != -1)
11458 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11459 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11462 static bool MayFoldVectorLoad(SDValue V) {
11463 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11464 V = V.getOperand(0);
11466 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11467 V = V.getOperand(0);
11468 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11469 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11470 // BUILD_VECTOR (load), undef
11471 V = V.getOperand(0);
11473 return MayFoldLoad(V);
11477 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11478 MVT VT = Op.getSimpleValueType();
11480 // Canonizalize to v2f64.
11481 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11482 return DAG.getNode(ISD::BITCAST, dl, VT,
11483 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11488 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11490 SDValue V1 = Op.getOperand(0);
11491 SDValue V2 = Op.getOperand(1);
11492 MVT VT = Op.getSimpleValueType();
11494 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11496 if (HasSSE2 && VT == MVT::v2f64)
11497 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11499 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11500 return DAG.getNode(ISD::BITCAST, dl, VT,
11501 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11502 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11503 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11507 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11508 SDValue V1 = Op.getOperand(0);
11509 SDValue V2 = Op.getOperand(1);
11510 MVT VT = Op.getSimpleValueType();
11512 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11513 "unsupported shuffle type");
11515 if (V2.getOpcode() == ISD::UNDEF)
11519 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11523 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11524 SDValue V1 = Op.getOperand(0);
11525 SDValue V2 = Op.getOperand(1);
11526 MVT VT = Op.getSimpleValueType();
11527 unsigned NumElems = VT.getVectorNumElements();
11529 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11530 // operand of these instructions is only memory, so check if there's a
11531 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11533 bool CanFoldLoad = false;
11535 // Trivial case, when V2 comes from a load.
11536 if (MayFoldVectorLoad(V2))
11537 CanFoldLoad = true;
11539 // When V1 is a load, it can be folded later into a store in isel, example:
11540 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11542 // (MOVLPSmr addr:$src1, VR128:$src2)
11543 // So, recognize this potential and also use MOVLPS or MOVLPD
11544 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11545 CanFoldLoad = true;
11547 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11549 if (HasSSE2 && NumElems == 2)
11550 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11553 // If we don't care about the second element, proceed to use movss.
11554 if (SVOp->getMaskElt(1) != -1)
11555 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11558 // movl and movlp will both match v2i64, but v2i64 is never matched by
11559 // movl earlier because we make it strict to avoid messing with the movlp load
11560 // folding logic (see the code above getMOVLP call). Match it here then,
11561 // this is horrible, but will stay like this until we move all shuffle
11562 // matching to x86 specific nodes. Note that for the 1st condition all
11563 // types are matched with movsd.
11565 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11566 // as to remove this logic from here, as much as possible
11567 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11568 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11569 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11572 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11574 // Invert the operand order and use SHUFPS to match it.
11575 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11576 getShuffleSHUFImmediate(SVOp), DAG);
11579 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11580 SelectionDAG &DAG) {
11582 MVT VT = Load->getSimpleValueType(0);
11583 MVT EVT = VT.getVectorElementType();
11584 SDValue Addr = Load->getOperand(1);
11585 SDValue NewAddr = DAG.getNode(
11586 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11587 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11590 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11591 DAG.getMachineFunction().getMachineMemOperand(
11592 Load->getMemOperand(), 0, EVT.getStoreSize()));
11596 // It is only safe to call this function if isINSERTPSMask is true for
11597 // this shufflevector mask.
11598 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11599 SelectionDAG &DAG) {
11600 // Generate an insertps instruction when inserting an f32 from memory onto a
11601 // v4f32 or when copying a member from one v4f32 to another.
11602 // We also use it for transferring i32 from one register to another,
11603 // since it simply copies the same bits.
11604 // If we're transferring an i32 from memory to a specific element in a
11605 // register, we output a generic DAG that will match the PINSRD
11607 MVT VT = SVOp->getSimpleValueType(0);
11608 MVT EVT = VT.getVectorElementType();
11609 SDValue V1 = SVOp->getOperand(0);
11610 SDValue V2 = SVOp->getOperand(1);
11611 auto Mask = SVOp->getMask();
11612 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11613 "unsupported vector type for insertps/pinsrd");
11615 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11616 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11617 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11621 unsigned DestIndex;
11625 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11628 // If we have 1 element from each vector, we have to check if we're
11629 // changing V1's element's place. If so, we're done. Otherwise, we
11630 // should assume we're changing V2's element's place and behave
11632 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11633 assert(DestIndex <= INT32_MAX && "truncated destination index");
11634 if (FromV1 == FromV2 &&
11635 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11639 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11642 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11643 "More than one element from V1 and from V2, or no elements from one "
11644 "of the vectors. This case should not have returned true from "
11649 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11652 // Get an index into the source vector in the range [0,4) (the mask is
11653 // in the range [0,8) because it can address V1 and V2)
11654 unsigned SrcIndex = Mask[DestIndex] % 4;
11655 if (MayFoldLoad(From)) {
11656 // Trivial case, when From comes from a load and is only used by the
11657 // shuffle. Make it use insertps from the vector that we need from that
11660 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11661 if (!NewLoad.getNode())
11664 if (EVT == MVT::f32) {
11665 // Create this as a scalar to vector to match the instruction pattern.
11666 SDValue LoadScalarToVector =
11667 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11668 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11669 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11671 } else { // EVT == MVT::i32
11672 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11673 // instruction, to match the PINSRD instruction, which loads an i32 to a
11674 // certain vector element.
11675 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11676 DAG.getConstant(DestIndex, MVT::i32));
11680 // Vector-element-to-vector
11681 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11682 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11685 // Reduce a vector shuffle to zext.
11686 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11687 SelectionDAG &DAG) {
11688 // PMOVZX is only available from SSE41.
11689 if (!Subtarget->hasSSE41())
11692 MVT VT = Op.getSimpleValueType();
11694 // Only AVX2 support 256-bit vector integer extending.
11695 if (!Subtarget->hasInt256() && VT.is256BitVector())
11698 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11700 SDValue V1 = Op.getOperand(0);
11701 SDValue V2 = Op.getOperand(1);
11702 unsigned NumElems = VT.getVectorNumElements();
11704 // Extending is an unary operation and the element type of the source vector
11705 // won't be equal to or larger than i64.
11706 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11707 VT.getVectorElementType() == MVT::i64)
11710 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11711 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11712 while ((1U << Shift) < NumElems) {
11713 if (SVOp->getMaskElt(1U << Shift) == 1)
11716 // The maximal ratio is 8, i.e. from i8 to i64.
11721 // Check the shuffle mask.
11722 unsigned Mask = (1U << Shift) - 1;
11723 for (unsigned i = 0; i != NumElems; ++i) {
11724 int EltIdx = SVOp->getMaskElt(i);
11725 if ((i & Mask) != 0 && EltIdx != -1)
11727 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11731 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11732 MVT NeVT = MVT::getIntegerVT(NBits);
11733 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11735 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11738 return DAG.getNode(ISD::BITCAST, DL, VT,
11739 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11742 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11743 SelectionDAG &DAG) {
11744 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11745 MVT VT = Op.getSimpleValueType();
11747 SDValue V1 = Op.getOperand(0);
11748 SDValue V2 = Op.getOperand(1);
11750 if (isZeroShuffle(SVOp))
11751 return getZeroVector(VT, Subtarget, DAG, dl);
11753 // Handle splat operations
11754 if (SVOp->isSplat()) {
11755 // Use vbroadcast whenever the splat comes from a foldable load
11756 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11757 if (Broadcast.getNode())
11761 // Check integer expanding shuffles.
11762 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11763 if (NewOp.getNode())
11766 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11768 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11769 VT == MVT::v32i8) {
11770 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11771 if (NewOp.getNode())
11772 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11773 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11774 // FIXME: Figure out a cleaner way to do this.
11775 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11776 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11777 if (NewOp.getNode()) {
11778 MVT NewVT = NewOp.getSimpleValueType();
11779 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11780 NewVT, true, false))
11781 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11784 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11785 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11786 if (NewOp.getNode()) {
11787 MVT NewVT = NewOp.getSimpleValueType();
11788 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11789 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11798 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11799 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11800 SDValue V1 = Op.getOperand(0);
11801 SDValue V2 = Op.getOperand(1);
11802 MVT VT = Op.getSimpleValueType();
11804 unsigned NumElems = VT.getVectorNumElements();
11805 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11806 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11807 bool V1IsSplat = false;
11808 bool V2IsSplat = false;
11809 bool HasSSE2 = Subtarget->hasSSE2();
11810 bool HasFp256 = Subtarget->hasFp256();
11811 bool HasInt256 = Subtarget->hasInt256();
11812 MachineFunction &MF = DAG.getMachineFunction();
11813 bool OptForSize = MF.getFunction()->getAttributes().
11814 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11816 // Check if we should use the experimental vector shuffle lowering. If so,
11817 // delegate completely to that code path.
11818 if (ExperimentalVectorShuffleLowering)
11819 return lowerVectorShuffle(Op, Subtarget, DAG);
11821 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11823 if (V1IsUndef && V2IsUndef)
11824 return DAG.getUNDEF(VT);
11826 // When we create a shuffle node we put the UNDEF node to second operand,
11827 // but in some cases the first operand may be transformed to UNDEF.
11828 // In this case we should just commute the node.
11830 return DAG.getCommutedVectorShuffle(*SVOp);
11832 // Vector shuffle lowering takes 3 steps:
11834 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11835 // narrowing and commutation of operands should be handled.
11836 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11838 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11839 // so the shuffle can be broken into other shuffles and the legalizer can
11840 // try the lowering again.
11842 // The general idea is that no vector_shuffle operation should be left to
11843 // be matched during isel, all of them must be converted to a target specific
11846 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11847 // narrowing and commutation of operands should be handled. The actual code
11848 // doesn't include all of those, work in progress...
11849 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11850 if (NewOp.getNode())
11853 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11855 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11856 // unpckh_undef). Only use pshufd if speed is more important than size.
11857 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11858 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11859 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11860 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11862 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11863 V2IsUndef && MayFoldVectorLoad(V1))
11864 return getMOVDDup(Op, dl, V1, DAG);
11866 if (isMOVHLPS_v_undef_Mask(M, VT))
11867 return getMOVHighToLow(Op, dl, DAG);
11869 // Use to match splats
11870 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11871 (VT == MVT::v2f64 || VT == MVT::v2i64))
11872 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11874 if (isPSHUFDMask(M, VT)) {
11875 // The actual implementation will match the mask in the if above and then
11876 // during isel it can match several different instructions, not only pshufd
11877 // as its name says, sad but true, emulate the behavior for now...
11878 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11879 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11881 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11883 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11884 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11886 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11887 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11890 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11894 if (isPALIGNRMask(M, VT, Subtarget))
11895 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11896 getShufflePALIGNRImmediate(SVOp),
11899 if (isVALIGNMask(M, VT, Subtarget))
11900 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11901 getShuffleVALIGNImmediate(SVOp),
11904 // Check if this can be converted into a logical shift.
11905 bool isLeft = false;
11906 unsigned ShAmt = 0;
11908 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11909 if (isShift && ShVal.hasOneUse()) {
11910 // If the shifted value has multiple uses, it may be cheaper to use
11911 // v_set0 + movlhps or movhlps, etc.
11912 MVT EltVT = VT.getVectorElementType();
11913 ShAmt *= EltVT.getSizeInBits();
11914 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11917 if (isMOVLMask(M, VT)) {
11918 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11919 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11920 if (!isMOVLPMask(M, VT)) {
11921 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11922 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11924 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11925 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11929 // FIXME: fold these into legal mask.
11930 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11931 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11933 if (isMOVHLPSMask(M, VT))
11934 return getMOVHighToLow(Op, dl, DAG);
11936 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11937 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11939 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11940 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11942 if (isMOVLPMask(M, VT))
11943 return getMOVLP(Op, dl, DAG, HasSSE2);
11945 if (ShouldXformToMOVHLPS(M, VT) ||
11946 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11947 return DAG.getCommutedVectorShuffle(*SVOp);
11950 // No better options. Use a vshldq / vsrldq.
11951 MVT EltVT = VT.getVectorElementType();
11952 ShAmt *= EltVT.getSizeInBits();
11953 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11956 bool Commuted = false;
11957 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11958 // 1,1,1,1 -> v8i16 though.
11959 BitVector UndefElements;
11960 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11961 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11963 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11964 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11967 // Canonicalize the splat or undef, if present, to be on the RHS.
11968 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11969 CommuteVectorShuffleMask(M, NumElems);
11971 std::swap(V1IsSplat, V2IsSplat);
11975 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11976 // Shuffling low element of v1 into undef, just return v1.
11979 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11980 // the instruction selector will not match, so get a canonical MOVL with
11981 // swapped operands to undo the commute.
11982 return getMOVL(DAG, dl, VT, V2, V1);
11985 if (isUNPCKLMask(M, VT, HasInt256))
11986 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11988 if (isUNPCKHMask(M, VT, HasInt256))
11989 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11992 // Normalize mask so all entries that point to V2 points to its first
11993 // element then try to match unpck{h|l} again. If match, return a
11994 // new vector_shuffle with the corrected mask.p
11995 SmallVector<int, 8> NewMask(M.begin(), M.end());
11996 NormalizeMask(NewMask, NumElems);
11997 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11998 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11999 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12000 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12004 // Commute is back and try unpck* again.
12005 // FIXME: this seems wrong.
12006 CommuteVectorShuffleMask(M, NumElems);
12008 std::swap(V1IsSplat, V2IsSplat);
12010 if (isUNPCKLMask(M, VT, HasInt256))
12011 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12013 if (isUNPCKHMask(M, VT, HasInt256))
12014 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12017 // Normalize the node to match x86 shuffle ops if needed
12018 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12019 return DAG.getCommutedVectorShuffle(*SVOp);
12021 // The checks below are all present in isShuffleMaskLegal, but they are
12022 // inlined here right now to enable us to directly emit target specific
12023 // nodes, and remove one by one until they don't return Op anymore.
12025 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12026 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12027 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12028 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12031 if (isPSHUFHWMask(M, VT, HasInt256))
12032 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12033 getShufflePSHUFHWImmediate(SVOp),
12036 if (isPSHUFLWMask(M, VT, HasInt256))
12037 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12038 getShufflePSHUFLWImmediate(SVOp),
12041 unsigned MaskValue;
12042 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12044 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12046 if (isSHUFPMask(M, VT))
12047 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12048 getShuffleSHUFImmediate(SVOp), DAG);
12050 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12051 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12052 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12053 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12055 //===--------------------------------------------------------------------===//
12056 // Generate target specific nodes for 128 or 256-bit shuffles only
12057 // supported in the AVX instruction set.
12060 // Handle VMOVDDUPY permutations
12061 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12062 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12064 // Handle VPERMILPS/D* permutations
12065 if (isVPERMILPMask(M, VT)) {
12066 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12067 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12068 getShuffleSHUFImmediate(SVOp), DAG);
12069 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12070 getShuffleSHUFImmediate(SVOp), DAG);
12074 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12075 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12076 Idx*(NumElems/2), DAG, dl);
12078 // Handle VPERM2F128/VPERM2I128 permutations
12079 if (isVPERM2X128Mask(M, VT, HasFp256))
12080 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12081 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12083 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12084 return getINSERTPS(SVOp, dl, DAG);
12087 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12088 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12090 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12091 VT.is512BitVector()) {
12092 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12093 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12094 SmallVector<SDValue, 16> permclMask;
12095 for (unsigned i = 0; i != NumElems; ++i) {
12096 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12099 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12101 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12102 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12103 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12104 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12105 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12108 //===--------------------------------------------------------------------===//
12109 // Since no target specific shuffle was selected for this generic one,
12110 // lower it into other known shuffles. FIXME: this isn't true yet, but
12111 // this is the plan.
12114 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12115 if (VT == MVT::v8i16) {
12116 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12117 if (NewOp.getNode())
12121 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12122 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12123 if (NewOp.getNode())
12127 if (VT == MVT::v16i8) {
12128 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12129 if (NewOp.getNode())
12133 if (VT == MVT::v32i8) {
12134 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12135 if (NewOp.getNode())
12139 // Handle all 128-bit wide vectors with 4 elements, and match them with
12140 // several different shuffle types.
12141 if (NumElems == 4 && VT.is128BitVector())
12142 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12144 // Handle general 256-bit shuffles
12145 if (VT.is256BitVector())
12146 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12151 // This function assumes its argument is a BUILD_VECTOR of constants or
12152 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12154 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12155 unsigned &MaskValue) {
12157 unsigned NumElems = BuildVector->getNumOperands();
12158 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12159 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12160 unsigned NumElemsInLane = NumElems / NumLanes;
12162 // Blend for v16i16 should be symetric for the both lanes.
12163 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12164 SDValue EltCond = BuildVector->getOperand(i);
12165 SDValue SndLaneEltCond =
12166 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12168 int Lane1Cond = -1, Lane2Cond = -1;
12169 if (isa<ConstantSDNode>(EltCond))
12170 Lane1Cond = !isZero(EltCond);
12171 if (isa<ConstantSDNode>(SndLaneEltCond))
12172 Lane2Cond = !isZero(SndLaneEltCond);
12174 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12175 // Lane1Cond != 0, means we want the first argument.
12176 // Lane1Cond == 0, means we want the second argument.
12177 // The encoding of this argument is 0 for the first argument, 1
12178 // for the second. Therefore, invert the condition.
12179 MaskValue |= !Lane1Cond << i;
12180 else if (Lane1Cond < 0)
12181 MaskValue |= !Lane2Cond << i;
12188 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12190 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12191 SelectionDAG &DAG) {
12192 SDValue Cond = Op.getOperand(0);
12193 SDValue LHS = Op.getOperand(1);
12194 SDValue RHS = Op.getOperand(2);
12196 MVT VT = Op.getSimpleValueType();
12197 MVT EltVT = VT.getVectorElementType();
12198 unsigned NumElems = VT.getVectorNumElements();
12200 // There is no blend with immediate in AVX-512.
12201 if (VT.is512BitVector())
12204 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12206 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12209 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12212 // Check the mask for BLEND and build the value.
12213 unsigned MaskValue = 0;
12214 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12217 // Convert i32 vectors to floating point if it is not AVX2.
12218 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12220 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12221 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12223 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12224 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12227 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12228 DAG.getConstant(MaskValue, MVT::i32));
12229 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12232 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12233 // A vselect where all conditions and data are constants can be optimized into
12234 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12235 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12236 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12237 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12240 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12241 if (BlendOp.getNode())
12244 // Some types for vselect were previously set to Expand, not Legal or
12245 // Custom. Return an empty SDValue so we fall-through to Expand, after
12246 // the Custom lowering phase.
12247 MVT VT = Op.getSimpleValueType();
12248 switch (VT.SimpleTy) {
12253 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12258 // We couldn't create a "Blend with immediate" node.
12259 // This node should still be legal, but we'll have to emit a blendv*
12264 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12265 MVT VT = Op.getSimpleValueType();
12268 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12271 if (VT.getSizeInBits() == 8) {
12272 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12273 Op.getOperand(0), Op.getOperand(1));
12274 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12275 DAG.getValueType(VT));
12276 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12279 if (VT.getSizeInBits() == 16) {
12280 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12281 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12283 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12284 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12285 DAG.getNode(ISD::BITCAST, dl,
12288 Op.getOperand(1)));
12289 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12290 Op.getOperand(0), Op.getOperand(1));
12291 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12292 DAG.getValueType(VT));
12293 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12296 if (VT == MVT::f32) {
12297 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12298 // the result back to FR32 register. It's only worth matching if the
12299 // result has a single use which is a store or a bitcast to i32. And in
12300 // the case of a store, it's not worth it if the index is a constant 0,
12301 // because a MOVSSmr can be used instead, which is smaller and faster.
12302 if (!Op.hasOneUse())
12304 SDNode *User = *Op.getNode()->use_begin();
12305 if ((User->getOpcode() != ISD::STORE ||
12306 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12307 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12308 (User->getOpcode() != ISD::BITCAST ||
12309 User->getValueType(0) != MVT::i32))
12311 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12312 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12315 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12318 if (VT == MVT::i32 || VT == MVT::i64) {
12319 // ExtractPS/pextrq works with constant index.
12320 if (isa<ConstantSDNode>(Op.getOperand(1)))
12326 /// Extract one bit from mask vector, like v16i1 or v8i1.
12327 /// AVX-512 feature.
12329 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12330 SDValue Vec = Op.getOperand(0);
12332 MVT VecVT = Vec.getSimpleValueType();
12333 SDValue Idx = Op.getOperand(1);
12334 MVT EltVT = Op.getSimpleValueType();
12336 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12338 // variable index can't be handled in mask registers,
12339 // extend vector to VR512
12340 if (!isa<ConstantSDNode>(Idx)) {
12341 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12342 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12343 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12344 ExtVT.getVectorElementType(), Ext, Idx);
12345 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12348 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12349 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12350 unsigned MaxSift = rc->getSize()*8 - 1;
12351 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12352 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12353 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12354 DAG.getConstant(MaxSift, MVT::i8));
12355 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12356 DAG.getIntPtrConstant(0));
12360 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12361 SelectionDAG &DAG) const {
12363 SDValue Vec = Op.getOperand(0);
12364 MVT VecVT = Vec.getSimpleValueType();
12365 SDValue Idx = Op.getOperand(1);
12367 if (Op.getSimpleValueType() == MVT::i1)
12368 return ExtractBitFromMaskVector(Op, DAG);
12370 if (!isa<ConstantSDNode>(Idx)) {
12371 if (VecVT.is512BitVector() ||
12372 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12373 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12376 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12377 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12378 MaskEltVT.getSizeInBits());
12380 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12381 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12382 getZeroVector(MaskVT, Subtarget, DAG, dl),
12383 Idx, DAG.getConstant(0, getPointerTy()));
12384 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12385 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12386 Perm, DAG.getConstant(0, getPointerTy()));
12391 // If this is a 256-bit vector result, first extract the 128-bit vector and
12392 // then extract the element from the 128-bit vector.
12393 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12395 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12396 // Get the 128-bit vector.
12397 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12398 MVT EltVT = VecVT.getVectorElementType();
12400 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12402 //if (IdxVal >= NumElems/2)
12403 // IdxVal -= NumElems/2;
12404 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12405 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12406 DAG.getConstant(IdxVal, MVT::i32));
12409 assert(VecVT.is128BitVector() && "Unexpected vector length");
12411 if (Subtarget->hasSSE41()) {
12412 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12417 MVT VT = Op.getSimpleValueType();
12418 // TODO: handle v16i8.
12419 if (VT.getSizeInBits() == 16) {
12420 SDValue Vec = Op.getOperand(0);
12421 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12423 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12424 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12425 DAG.getNode(ISD::BITCAST, dl,
12427 Op.getOperand(1)));
12428 // Transform it so it match pextrw which produces a 32-bit result.
12429 MVT EltVT = MVT::i32;
12430 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12431 Op.getOperand(0), Op.getOperand(1));
12432 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12433 DAG.getValueType(VT));
12434 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12437 if (VT.getSizeInBits() == 32) {
12438 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12442 // SHUFPS the element to the lowest double word, then movss.
12443 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12444 MVT VVT = Op.getOperand(0).getSimpleValueType();
12445 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12446 DAG.getUNDEF(VVT), Mask);
12447 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12448 DAG.getIntPtrConstant(0));
12451 if (VT.getSizeInBits() == 64) {
12452 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12453 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12454 // to match extract_elt for f64.
12455 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12459 // UNPCKHPD the element to the lowest double word, then movsd.
12460 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12461 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12462 int Mask[2] = { 1, -1 };
12463 MVT VVT = Op.getOperand(0).getSimpleValueType();
12464 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12465 DAG.getUNDEF(VVT), Mask);
12466 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12467 DAG.getIntPtrConstant(0));
12473 /// Insert one bit to mask vector, like v16i1 or v8i1.
12474 /// AVX-512 feature.
12476 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12478 SDValue Vec = Op.getOperand(0);
12479 SDValue Elt = Op.getOperand(1);
12480 SDValue Idx = Op.getOperand(2);
12481 MVT VecVT = Vec.getSimpleValueType();
12483 if (!isa<ConstantSDNode>(Idx)) {
12484 // Non constant index. Extend source and destination,
12485 // insert element and then truncate the result.
12486 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12487 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12488 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12489 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12490 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12491 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12494 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12495 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12496 if (Vec.getOpcode() == ISD::UNDEF)
12497 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12498 DAG.getConstant(IdxVal, MVT::i8));
12499 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12500 unsigned MaxSift = rc->getSize()*8 - 1;
12501 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12502 DAG.getConstant(MaxSift, MVT::i8));
12503 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12504 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12505 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12508 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12509 SelectionDAG &DAG) const {
12510 MVT VT = Op.getSimpleValueType();
12511 MVT EltVT = VT.getVectorElementType();
12513 if (EltVT == MVT::i1)
12514 return InsertBitToMaskVector(Op, DAG);
12517 SDValue N0 = Op.getOperand(0);
12518 SDValue N1 = Op.getOperand(1);
12519 SDValue N2 = Op.getOperand(2);
12520 if (!isa<ConstantSDNode>(N2))
12522 auto *N2C = cast<ConstantSDNode>(N2);
12523 unsigned IdxVal = N2C->getZExtValue();
12525 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12526 // into that, and then insert the subvector back into the result.
12527 if (VT.is256BitVector() || VT.is512BitVector()) {
12528 // Get the desired 128-bit vector half.
12529 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12531 // Insert the element into the desired half.
12532 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12533 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12535 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12536 DAG.getConstant(IdxIn128, MVT::i32));
12538 // Insert the changed part back to the 256-bit vector
12539 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12541 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12543 if (Subtarget->hasSSE41()) {
12544 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12546 if (VT == MVT::v8i16) {
12547 Opc = X86ISD::PINSRW;
12549 assert(VT == MVT::v16i8);
12550 Opc = X86ISD::PINSRB;
12553 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12555 if (N1.getValueType() != MVT::i32)
12556 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12557 if (N2.getValueType() != MVT::i32)
12558 N2 = DAG.getIntPtrConstant(IdxVal);
12559 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12562 if (EltVT == MVT::f32) {
12563 // Bits [7:6] of the constant are the source select. This will always be
12564 // zero here. The DAG Combiner may combine an extract_elt index into
12566 // bits. For example (insert (extract, 3), 2) could be matched by
12568 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12569 // Bits [5:4] of the constant are the destination select. This is the
12570 // value of the incoming immediate.
12571 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12572 // combine either bitwise AND or insert of float 0.0 to set these bits.
12573 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12574 // Create this as a scalar to vector..
12575 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12576 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12579 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12580 // PINSR* works with constant index.
12585 if (EltVT == MVT::i8)
12588 if (EltVT.getSizeInBits() == 16) {
12589 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12590 // as its second argument.
12591 if (N1.getValueType() != MVT::i32)
12592 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12593 if (N2.getValueType() != MVT::i32)
12594 N2 = DAG.getIntPtrConstant(IdxVal);
12595 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12600 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12602 MVT OpVT = Op.getSimpleValueType();
12604 // If this is a 256-bit vector result, first insert into a 128-bit
12605 // vector and then insert into the 256-bit vector.
12606 if (!OpVT.is128BitVector()) {
12607 // Insert into a 128-bit vector.
12608 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12609 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12610 OpVT.getVectorNumElements() / SizeFactor);
12612 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12614 // Insert the 128-bit vector.
12615 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12618 if (OpVT == MVT::v1i64 &&
12619 Op.getOperand(0).getValueType() == MVT::i64)
12620 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12622 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12623 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12624 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12625 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12628 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12629 // a simple subregister reference or explicit instructions to grab
12630 // upper bits of a vector.
12631 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12632 SelectionDAG &DAG) {
12634 SDValue In = Op.getOperand(0);
12635 SDValue Idx = Op.getOperand(1);
12636 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12637 MVT ResVT = Op.getSimpleValueType();
12638 MVT InVT = In.getSimpleValueType();
12640 if (Subtarget->hasFp256()) {
12641 if (ResVT.is128BitVector() &&
12642 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12643 isa<ConstantSDNode>(Idx)) {
12644 return Extract128BitVector(In, IdxVal, DAG, dl);
12646 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12647 isa<ConstantSDNode>(Idx)) {
12648 return Extract256BitVector(In, IdxVal, DAG, dl);
12654 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12655 // simple superregister reference or explicit instructions to insert
12656 // the upper bits of a vector.
12657 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12658 SelectionDAG &DAG) {
12659 if (Subtarget->hasFp256()) {
12660 SDLoc dl(Op.getNode());
12661 SDValue Vec = Op.getNode()->getOperand(0);
12662 SDValue SubVec = Op.getNode()->getOperand(1);
12663 SDValue Idx = Op.getNode()->getOperand(2);
12665 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12666 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12667 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12668 isa<ConstantSDNode>(Idx)) {
12669 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12670 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12673 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12674 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12675 isa<ConstantSDNode>(Idx)) {
12676 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12677 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12683 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12684 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12685 // one of the above mentioned nodes. It has to be wrapped because otherwise
12686 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12687 // be used to form addressing mode. These wrapped nodes will be selected
12690 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12691 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12693 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12694 // global base reg.
12695 unsigned char OpFlag = 0;
12696 unsigned WrapperKind = X86ISD::Wrapper;
12697 CodeModel::Model M = DAG.getTarget().getCodeModel();
12699 if (Subtarget->isPICStyleRIPRel() &&
12700 (M == CodeModel::Small || M == CodeModel::Kernel))
12701 WrapperKind = X86ISD::WrapperRIP;
12702 else if (Subtarget->isPICStyleGOT())
12703 OpFlag = X86II::MO_GOTOFF;
12704 else if (Subtarget->isPICStyleStubPIC())
12705 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12707 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12708 CP->getAlignment(),
12709 CP->getOffset(), OpFlag);
12711 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12712 // With PIC, the address is actually $g + Offset.
12714 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12715 DAG.getNode(X86ISD::GlobalBaseReg,
12716 SDLoc(), getPointerTy()),
12723 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12724 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12726 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12727 // global base reg.
12728 unsigned char OpFlag = 0;
12729 unsigned WrapperKind = X86ISD::Wrapper;
12730 CodeModel::Model M = DAG.getTarget().getCodeModel();
12732 if (Subtarget->isPICStyleRIPRel() &&
12733 (M == CodeModel::Small || M == CodeModel::Kernel))
12734 WrapperKind = X86ISD::WrapperRIP;
12735 else if (Subtarget->isPICStyleGOT())
12736 OpFlag = X86II::MO_GOTOFF;
12737 else if (Subtarget->isPICStyleStubPIC())
12738 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12740 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12743 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12745 // With PIC, the address is actually $g + Offset.
12747 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12748 DAG.getNode(X86ISD::GlobalBaseReg,
12749 SDLoc(), getPointerTy()),
12756 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12757 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12759 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12760 // global base reg.
12761 unsigned char OpFlag = 0;
12762 unsigned WrapperKind = X86ISD::Wrapper;
12763 CodeModel::Model M = DAG.getTarget().getCodeModel();
12765 if (Subtarget->isPICStyleRIPRel() &&
12766 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12767 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12768 OpFlag = X86II::MO_GOTPCREL;
12769 WrapperKind = X86ISD::WrapperRIP;
12770 } else if (Subtarget->isPICStyleGOT()) {
12771 OpFlag = X86II::MO_GOT;
12772 } else if (Subtarget->isPICStyleStubPIC()) {
12773 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12774 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12775 OpFlag = X86II::MO_DARWIN_NONLAZY;
12778 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12781 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12783 // With PIC, the address is actually $g + Offset.
12784 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12785 !Subtarget->is64Bit()) {
12786 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12787 DAG.getNode(X86ISD::GlobalBaseReg,
12788 SDLoc(), getPointerTy()),
12792 // For symbols that require a load from a stub to get the address, emit the
12794 if (isGlobalStubReference(OpFlag))
12795 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12796 MachinePointerInfo::getGOT(), false, false, false, 0);
12802 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12803 // Create the TargetBlockAddressAddress node.
12804 unsigned char OpFlags =
12805 Subtarget->ClassifyBlockAddressReference();
12806 CodeModel::Model M = DAG.getTarget().getCodeModel();
12807 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12808 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12810 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12813 if (Subtarget->isPICStyleRIPRel() &&
12814 (M == CodeModel::Small || M == CodeModel::Kernel))
12815 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12817 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12819 // With PIC, the address is actually $g + Offset.
12820 if (isGlobalRelativeToPICBase(OpFlags)) {
12821 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12822 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12830 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12831 int64_t Offset, SelectionDAG &DAG) const {
12832 // Create the TargetGlobalAddress node, folding in the constant
12833 // offset if it is legal.
12834 unsigned char OpFlags =
12835 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12836 CodeModel::Model M = DAG.getTarget().getCodeModel();
12838 if (OpFlags == X86II::MO_NO_FLAG &&
12839 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12840 // A direct static reference to a global.
12841 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12844 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12847 if (Subtarget->isPICStyleRIPRel() &&
12848 (M == CodeModel::Small || M == CodeModel::Kernel))
12849 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12851 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12853 // With PIC, the address is actually $g + Offset.
12854 if (isGlobalRelativeToPICBase(OpFlags)) {
12855 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12856 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12860 // For globals that require a load from a stub to get the address, emit the
12862 if (isGlobalStubReference(OpFlags))
12863 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12864 MachinePointerInfo::getGOT(), false, false, false, 0);
12866 // If there was a non-zero offset that we didn't fold, create an explicit
12867 // addition for it.
12869 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12870 DAG.getConstant(Offset, getPointerTy()));
12876 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12877 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12878 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12879 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12883 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12884 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12885 unsigned char OperandFlags, bool LocalDynamic = false) {
12886 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12887 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12889 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12890 GA->getValueType(0),
12894 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12898 SDValue Ops[] = { Chain, TGA, *InFlag };
12899 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12901 SDValue Ops[] = { Chain, TGA };
12902 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12905 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12906 MFI->setAdjustsStack(true);
12907 MFI->setHasCalls(true);
12909 SDValue Flag = Chain.getValue(1);
12910 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12913 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12915 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12918 SDLoc dl(GA); // ? function entry point might be better
12919 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12920 DAG.getNode(X86ISD::GlobalBaseReg,
12921 SDLoc(), PtrVT), InFlag);
12922 InFlag = Chain.getValue(1);
12924 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12927 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12929 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12931 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12932 X86::RAX, X86II::MO_TLSGD);
12935 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12941 // Get the start address of the TLS block for this module.
12942 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12943 .getInfo<X86MachineFunctionInfo>();
12944 MFI->incNumLocalDynamicTLSAccesses();
12948 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12949 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12952 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12953 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12954 InFlag = Chain.getValue(1);
12955 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12956 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12959 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12963 unsigned char OperandFlags = X86II::MO_DTPOFF;
12964 unsigned WrapperKind = X86ISD::Wrapper;
12965 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12966 GA->getValueType(0),
12967 GA->getOffset(), OperandFlags);
12968 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12970 // Add x@dtpoff with the base.
12971 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12974 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12975 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12976 const EVT PtrVT, TLSModel::Model model,
12977 bool is64Bit, bool isPIC) {
12980 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12981 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12982 is64Bit ? 257 : 256));
12984 SDValue ThreadPointer =
12985 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12986 MachinePointerInfo(Ptr), false, false, false, 0);
12988 unsigned char OperandFlags = 0;
12989 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12991 unsigned WrapperKind = X86ISD::Wrapper;
12992 if (model == TLSModel::LocalExec) {
12993 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12994 } else if (model == TLSModel::InitialExec) {
12996 OperandFlags = X86II::MO_GOTTPOFF;
12997 WrapperKind = X86ISD::WrapperRIP;
12999 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13002 llvm_unreachable("Unexpected model");
13005 // emit "addl x@ntpoff,%eax" (local exec)
13006 // or "addl x@indntpoff,%eax" (initial exec)
13007 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13009 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13010 GA->getOffset(), OperandFlags);
13011 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13013 if (model == TLSModel::InitialExec) {
13014 if (isPIC && !is64Bit) {
13015 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13016 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13020 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13021 MachinePointerInfo::getGOT(), false, false, false, 0);
13024 // The address of the thread local variable is the add of the thread
13025 // pointer with the offset of the variable.
13026 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13030 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13032 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13033 const GlobalValue *GV = GA->getGlobal();
13035 if (Subtarget->isTargetELF()) {
13036 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13039 case TLSModel::GeneralDynamic:
13040 if (Subtarget->is64Bit())
13041 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13042 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13043 case TLSModel::LocalDynamic:
13044 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13045 Subtarget->is64Bit());
13046 case TLSModel::InitialExec:
13047 case TLSModel::LocalExec:
13048 return LowerToTLSExecModel(
13049 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13050 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13052 llvm_unreachable("Unknown TLS model.");
13055 if (Subtarget->isTargetDarwin()) {
13056 // Darwin only has one model of TLS. Lower to that.
13057 unsigned char OpFlag = 0;
13058 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13059 X86ISD::WrapperRIP : X86ISD::Wrapper;
13061 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13062 // global base reg.
13063 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13064 !Subtarget->is64Bit();
13066 OpFlag = X86II::MO_TLVP_PIC_BASE;
13068 OpFlag = X86II::MO_TLVP;
13070 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13071 GA->getValueType(0),
13072 GA->getOffset(), OpFlag);
13073 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13075 // With PIC32, the address is actually $g + Offset.
13077 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13078 DAG.getNode(X86ISD::GlobalBaseReg,
13079 SDLoc(), getPointerTy()),
13082 // Lowering the machine isd will make sure everything is in the right
13084 SDValue Chain = DAG.getEntryNode();
13085 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13086 SDValue Args[] = { Chain, Offset };
13087 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13089 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13090 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13091 MFI->setAdjustsStack(true);
13093 // And our return value (tls address) is in the standard call return value
13095 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13096 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13097 Chain.getValue(1));
13100 if (Subtarget->isTargetKnownWindowsMSVC() ||
13101 Subtarget->isTargetWindowsGNU()) {
13102 // Just use the implicit TLS architecture
13103 // Need to generate someting similar to:
13104 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13106 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13107 // mov rcx, qword [rdx+rcx*8]
13108 // mov eax, .tls$:tlsvar
13109 // [rax+rcx] contains the address
13110 // Windows 64bit: gs:0x58
13111 // Windows 32bit: fs:__tls_array
13114 SDValue Chain = DAG.getEntryNode();
13116 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13117 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13118 // use its literal value of 0x2C.
13119 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13120 ? Type::getInt8PtrTy(*DAG.getContext(),
13122 : Type::getInt32PtrTy(*DAG.getContext(),
13126 Subtarget->is64Bit()
13127 ? DAG.getIntPtrConstant(0x58)
13128 : (Subtarget->isTargetWindowsGNU()
13129 ? DAG.getIntPtrConstant(0x2C)
13130 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13132 SDValue ThreadPointer =
13133 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13134 MachinePointerInfo(Ptr), false, false, false, 0);
13136 // Load the _tls_index variable
13137 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13138 if (Subtarget->is64Bit())
13139 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13140 IDX, MachinePointerInfo(), MVT::i32,
13141 false, false, false, 0);
13143 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13144 false, false, false, 0);
13146 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13148 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13150 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13151 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13152 false, false, false, 0);
13154 // Get the offset of start of .tls section
13155 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13156 GA->getValueType(0),
13157 GA->getOffset(), X86II::MO_SECREL);
13158 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13160 // The address of the thread local variable is the add of the thread
13161 // pointer with the offset of the variable.
13162 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13165 llvm_unreachable("TLS not implemented for this target.");
13168 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13169 /// and take a 2 x i32 value to shift plus a shift amount.
13170 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13171 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13172 MVT VT = Op.getSimpleValueType();
13173 unsigned VTBits = VT.getSizeInBits();
13175 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13176 SDValue ShOpLo = Op.getOperand(0);
13177 SDValue ShOpHi = Op.getOperand(1);
13178 SDValue ShAmt = Op.getOperand(2);
13179 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13180 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13182 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13183 DAG.getConstant(VTBits - 1, MVT::i8));
13184 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13185 DAG.getConstant(VTBits - 1, MVT::i8))
13186 : DAG.getConstant(0, VT);
13188 SDValue Tmp2, Tmp3;
13189 if (Op.getOpcode() == ISD::SHL_PARTS) {
13190 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13191 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13193 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13194 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13197 // If the shift amount is larger or equal than the width of a part we can't
13198 // rely on the results of shld/shrd. Insert a test and select the appropriate
13199 // values for large shift amounts.
13200 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13201 DAG.getConstant(VTBits, MVT::i8));
13202 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13203 AndNode, DAG.getConstant(0, MVT::i8));
13206 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13207 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13208 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13210 if (Op.getOpcode() == ISD::SHL_PARTS) {
13211 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13212 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13214 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13215 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13218 SDValue Ops[2] = { Lo, Hi };
13219 return DAG.getMergeValues(Ops, dl);
13222 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13223 SelectionDAG &DAG) const {
13224 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13227 if (SrcVT.isVector()) {
13228 if (SrcVT.getVectorElementType() == MVT::i1) {
13229 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13230 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13231 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13232 Op.getOperand(0)));
13237 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13238 "Unknown SINT_TO_FP to lower!");
13240 // These are really Legal; return the operand so the caller accepts it as
13242 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13244 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13245 Subtarget->is64Bit()) {
13249 unsigned Size = SrcVT.getSizeInBits()/8;
13250 MachineFunction &MF = DAG.getMachineFunction();
13251 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13252 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13253 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13255 MachinePointerInfo::getFixedStack(SSFI),
13257 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13260 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13262 SelectionDAG &DAG) const {
13266 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13268 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13270 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13272 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13274 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13275 MachineMemOperand *MMO;
13277 int SSFI = FI->getIndex();
13279 DAG.getMachineFunction()
13280 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13281 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13283 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13284 StackSlot = StackSlot.getOperand(1);
13286 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13287 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13289 Tys, Ops, SrcVT, MMO);
13292 Chain = Result.getValue(1);
13293 SDValue InFlag = Result.getValue(2);
13295 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13296 // shouldn't be necessary except that RFP cannot be live across
13297 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13298 MachineFunction &MF = DAG.getMachineFunction();
13299 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13300 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13301 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13302 Tys = DAG.getVTList(MVT::Other);
13304 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13306 MachineMemOperand *MMO =
13307 DAG.getMachineFunction()
13308 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13309 MachineMemOperand::MOStore, SSFISize, SSFISize);
13311 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13312 Ops, Op.getValueType(), MMO);
13313 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13314 MachinePointerInfo::getFixedStack(SSFI),
13315 false, false, false, 0);
13321 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13322 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13323 SelectionDAG &DAG) const {
13324 // This algorithm is not obvious. Here it is what we're trying to output:
13327 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13328 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13330 haddpd %xmm0, %xmm0
13332 pshufd $0x4e, %xmm0, %xmm1
13338 LLVMContext *Context = DAG.getContext();
13340 // Build some magic constants.
13341 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13342 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13343 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13345 SmallVector<Constant*,2> CV1;
13347 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13348 APInt(64, 0x4330000000000000ULL))));
13350 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13351 APInt(64, 0x4530000000000000ULL))));
13352 Constant *C1 = ConstantVector::get(CV1);
13353 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13355 // Load the 64-bit value into an XMM register.
13356 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13358 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13359 MachinePointerInfo::getConstantPool(),
13360 false, false, false, 16);
13361 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13362 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13365 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13366 MachinePointerInfo::getConstantPool(),
13367 false, false, false, 16);
13368 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13369 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13372 if (Subtarget->hasSSE3()) {
13373 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13374 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13376 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13377 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13379 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13380 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13384 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13385 DAG.getIntPtrConstant(0));
13388 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13389 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13390 SelectionDAG &DAG) const {
13392 // FP constant to bias correct the final result.
13393 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13396 // Load the 32-bit value into an XMM register.
13397 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13400 // Zero out the upper parts of the register.
13401 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13403 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13404 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13405 DAG.getIntPtrConstant(0));
13407 // Or the load with the bias.
13408 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13409 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13410 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13411 MVT::v2f64, Load)),
13412 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13413 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13414 MVT::v2f64, Bias)));
13415 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13416 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13417 DAG.getIntPtrConstant(0));
13419 // Subtract the bias.
13420 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13422 // Handle final rounding.
13423 EVT DestVT = Op.getValueType();
13425 if (DestVT.bitsLT(MVT::f64))
13426 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13427 DAG.getIntPtrConstant(0));
13428 if (DestVT.bitsGT(MVT::f64))
13429 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13431 // Handle final rounding.
13435 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13436 const X86Subtarget &Subtarget) {
13437 // The algorithm is the following:
13438 // #ifdef __SSE4_1__
13439 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13440 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13441 // (uint4) 0x53000000, 0xaa);
13443 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13444 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13446 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13447 // return (float4) lo + fhi;
13450 SDValue V = Op->getOperand(0);
13451 EVT VecIntVT = V.getValueType();
13452 bool Is128 = VecIntVT == MVT::v4i32;
13453 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13454 unsigned NumElts = VecIntVT.getVectorNumElements();
13455 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13456 "Unsupported custom type");
13457 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13459 // In the #idef/#else code, we have in common:
13460 // - The vector of constants:
13466 // Create the splat vector for 0x4b000000.
13467 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13468 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13469 CstLow, CstLow, CstLow, CstLow};
13470 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13471 makeArrayRef(&CstLowArray[0], NumElts));
13472 // Create the splat vector for 0x53000000.
13473 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13474 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13475 CstHigh, CstHigh, CstHigh, CstHigh};
13476 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13477 makeArrayRef(&CstHighArray[0], NumElts));
13479 // Create the right shift.
13480 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13481 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13482 CstShift, CstShift, CstShift, CstShift};
13483 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13484 makeArrayRef(&CstShiftArray[0], NumElts));
13485 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13488 if (Subtarget.hasSSE41()) {
13489 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13490 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13491 SDValue VecCstLowBitcast =
13492 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13493 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13494 // Low will be bitcasted right away, so do not bother bitcasting back to its
13496 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13497 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13498 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13499 // (uint4) 0x53000000, 0xaa);
13500 SDValue VecCstHighBitcast =
13501 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13502 SDValue VecShiftBitcast =
13503 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13504 // High will be bitcasted right away, so do not bother bitcasting back to
13505 // its original type.
13506 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13507 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13509 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13510 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13511 CstMask, CstMask, CstMask);
13512 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13513 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13514 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13516 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13517 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13520 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13521 SDValue CstFAdd = DAG.getConstantFP(
13522 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13523 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13524 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13525 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13526 makeArrayRef(&CstFAddArray[0], NumElts));
13528 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13529 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13531 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13532 // return (float4) lo + fhi;
13533 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13534 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13537 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13538 SelectionDAG &DAG) const {
13539 SDValue N0 = Op.getOperand(0);
13540 MVT SVT = N0.getSimpleValueType();
13543 switch (SVT.SimpleTy) {
13545 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13550 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13551 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13552 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13556 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13558 llvm_unreachable(nullptr);
13561 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13562 SelectionDAG &DAG) const {
13563 SDValue N0 = Op.getOperand(0);
13566 if (Op.getValueType().isVector())
13567 return lowerUINT_TO_FP_vec(Op, DAG);
13569 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13570 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13571 // the optimization here.
13572 if (DAG.SignBitIsZero(N0))
13573 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13575 MVT SrcVT = N0.getSimpleValueType();
13576 MVT DstVT = Op.getSimpleValueType();
13577 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13578 return LowerUINT_TO_FP_i64(Op, DAG);
13579 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13580 return LowerUINT_TO_FP_i32(Op, DAG);
13581 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13584 // Make a 64-bit buffer, and use it to build an FILD.
13585 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13586 if (SrcVT == MVT::i32) {
13587 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13588 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13589 getPointerTy(), StackSlot, WordOff);
13590 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13591 StackSlot, MachinePointerInfo(),
13593 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13594 OffsetSlot, MachinePointerInfo(),
13596 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13600 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13601 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13602 StackSlot, MachinePointerInfo(),
13604 // For i64 source, we need to add the appropriate power of 2 if the input
13605 // was negative. This is the same as the optimization in
13606 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13607 // we must be careful to do the computation in x87 extended precision, not
13608 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13609 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13610 MachineMemOperand *MMO =
13611 DAG.getMachineFunction()
13612 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13613 MachineMemOperand::MOLoad, 8, 8);
13615 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13616 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13617 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13620 APInt FF(32, 0x5F800000ULL);
13622 // Check whether the sign bit is set.
13623 SDValue SignSet = DAG.getSetCC(dl,
13624 getSetCCResultType(*DAG.getContext(), MVT::i64),
13625 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13628 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13629 SDValue FudgePtr = DAG.getConstantPool(
13630 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13633 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13634 SDValue Zero = DAG.getIntPtrConstant(0);
13635 SDValue Four = DAG.getIntPtrConstant(4);
13636 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13638 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13640 // Load the value out, extending it from f32 to f80.
13641 // FIXME: Avoid the extend by constructing the right constant pool?
13642 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13643 FudgePtr, MachinePointerInfo::getConstantPool(),
13644 MVT::f32, false, false, false, 4);
13645 // Extend everything to 80 bits to force it to be done on x87.
13646 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13647 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13650 std::pair<SDValue,SDValue>
13651 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13652 bool IsSigned, bool IsReplace) const {
13655 EVT DstTy = Op.getValueType();
13657 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13658 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13662 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13663 DstTy.getSimpleVT() >= MVT::i16 &&
13664 "Unknown FP_TO_INT to lower!");
13666 // These are really Legal.
13667 if (DstTy == MVT::i32 &&
13668 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13669 return std::make_pair(SDValue(), SDValue());
13670 if (Subtarget->is64Bit() &&
13671 DstTy == MVT::i64 &&
13672 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13673 return std::make_pair(SDValue(), SDValue());
13675 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13676 // stack slot, or into the FTOL runtime function.
13677 MachineFunction &MF = DAG.getMachineFunction();
13678 unsigned MemSize = DstTy.getSizeInBits()/8;
13679 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13680 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13683 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13684 Opc = X86ISD::WIN_FTOL;
13686 switch (DstTy.getSimpleVT().SimpleTy) {
13687 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13688 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13689 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13690 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13693 SDValue Chain = DAG.getEntryNode();
13694 SDValue Value = Op.getOperand(0);
13695 EVT TheVT = Op.getOperand(0).getValueType();
13696 // FIXME This causes a redundant load/store if the SSE-class value is already
13697 // in memory, such as if it is on the callstack.
13698 if (isScalarFPTypeInSSEReg(TheVT)) {
13699 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13700 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13701 MachinePointerInfo::getFixedStack(SSFI),
13703 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13705 Chain, StackSlot, DAG.getValueType(TheVT)
13708 MachineMemOperand *MMO =
13709 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13710 MachineMemOperand::MOLoad, MemSize, MemSize);
13711 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13712 Chain = Value.getValue(1);
13713 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13714 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13717 MachineMemOperand *MMO =
13718 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13719 MachineMemOperand::MOStore, MemSize, MemSize);
13721 if (Opc != X86ISD::WIN_FTOL) {
13722 // Build the FP_TO_INT*_IN_MEM
13723 SDValue Ops[] = { Chain, Value, StackSlot };
13724 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13726 return std::make_pair(FIST, StackSlot);
13728 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13729 DAG.getVTList(MVT::Other, MVT::Glue),
13731 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13732 MVT::i32, ftol.getValue(1));
13733 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13734 MVT::i32, eax.getValue(2));
13735 SDValue Ops[] = { eax, edx };
13736 SDValue pair = IsReplace
13737 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13738 : DAG.getMergeValues(Ops, DL);
13739 return std::make_pair(pair, SDValue());
13743 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13744 const X86Subtarget *Subtarget) {
13745 MVT VT = Op->getSimpleValueType(0);
13746 SDValue In = Op->getOperand(0);
13747 MVT InVT = In.getSimpleValueType();
13750 // Optimize vectors in AVX mode:
13753 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13754 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13755 // Concat upper and lower parts.
13758 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13759 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13760 // Concat upper and lower parts.
13763 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13764 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13765 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13768 if (Subtarget->hasInt256())
13769 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13771 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13772 SDValue Undef = DAG.getUNDEF(InVT);
13773 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13774 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13775 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13777 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13778 VT.getVectorNumElements()/2);
13780 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13781 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13783 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13786 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13787 SelectionDAG &DAG) {
13788 MVT VT = Op->getSimpleValueType(0);
13789 SDValue In = Op->getOperand(0);
13790 MVT InVT = In.getSimpleValueType();
13792 unsigned int NumElts = VT.getVectorNumElements();
13793 if (NumElts != 8 && NumElts != 16)
13796 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13797 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13799 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13800 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13801 // Now we have only mask extension
13802 assert(InVT.getVectorElementType() == MVT::i1);
13803 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13804 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13805 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13806 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13807 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13808 MachinePointerInfo::getConstantPool(),
13809 false, false, false, Alignment);
13811 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13812 if (VT.is512BitVector())
13814 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13817 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13818 SelectionDAG &DAG) {
13819 if (Subtarget->hasFp256()) {
13820 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13828 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13829 SelectionDAG &DAG) {
13831 MVT VT = Op.getSimpleValueType();
13832 SDValue In = Op.getOperand(0);
13833 MVT SVT = In.getSimpleValueType();
13835 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13836 return LowerZERO_EXTEND_AVX512(Op, DAG);
13838 if (Subtarget->hasFp256()) {
13839 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13844 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13845 VT.getVectorNumElements() != SVT.getVectorNumElements());
13849 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13851 MVT VT = Op.getSimpleValueType();
13852 SDValue In = Op.getOperand(0);
13853 MVT InVT = In.getSimpleValueType();
13855 if (VT == MVT::i1) {
13856 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13857 "Invalid scalar TRUNCATE operation");
13858 if (InVT.getSizeInBits() >= 32)
13860 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13861 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13863 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13864 "Invalid TRUNCATE operation");
13866 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13867 if (VT.getVectorElementType().getSizeInBits() >=8)
13868 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13870 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13871 unsigned NumElts = InVT.getVectorNumElements();
13872 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13873 if (InVT.getSizeInBits() < 512) {
13874 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13875 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13879 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13880 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13881 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13882 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13883 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13884 MachinePointerInfo::getConstantPool(),
13885 false, false, false, Alignment);
13886 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13887 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13888 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13891 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13892 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13893 if (Subtarget->hasInt256()) {
13894 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13895 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13896 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13898 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13899 DAG.getIntPtrConstant(0));
13902 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13903 DAG.getIntPtrConstant(0));
13904 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13905 DAG.getIntPtrConstant(2));
13906 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13907 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13908 static const int ShufMask[] = {0, 2, 4, 6};
13909 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13912 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13913 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13914 if (Subtarget->hasInt256()) {
13915 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13917 SmallVector<SDValue,32> pshufbMask;
13918 for (unsigned i = 0; i < 2; ++i) {
13919 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13920 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13921 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13922 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13923 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13924 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13925 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13926 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13927 for (unsigned j = 0; j < 8; ++j)
13928 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13930 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13931 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13932 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13934 static const int ShufMask[] = {0, 2, -1, -1};
13935 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13937 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13938 DAG.getIntPtrConstant(0));
13939 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13942 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13943 DAG.getIntPtrConstant(0));
13945 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13946 DAG.getIntPtrConstant(4));
13948 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13949 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13951 // The PSHUFB mask:
13952 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13953 -1, -1, -1, -1, -1, -1, -1, -1};
13955 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13956 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13957 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13959 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13960 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13962 // The MOVLHPS Mask:
13963 static const int ShufMask2[] = {0, 1, 4, 5};
13964 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13965 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13968 // Handle truncation of V256 to V128 using shuffles.
13969 if (!VT.is128BitVector() || !InVT.is256BitVector())
13972 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13974 unsigned NumElems = VT.getVectorNumElements();
13975 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13977 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13978 // Prepare truncation shuffle mask
13979 for (unsigned i = 0; i != NumElems; ++i)
13980 MaskVec[i] = i * 2;
13981 SDValue V = DAG.getVectorShuffle(NVT, DL,
13982 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13983 DAG.getUNDEF(NVT), &MaskVec[0]);
13984 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13985 DAG.getIntPtrConstant(0));
13988 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13989 SelectionDAG &DAG) const {
13990 assert(!Op.getSimpleValueType().isVector());
13992 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13993 /*IsSigned=*/ true, /*IsReplace=*/ false);
13994 SDValue FIST = Vals.first, StackSlot = Vals.second;
13995 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13996 if (!FIST.getNode()) return Op;
13998 if (StackSlot.getNode())
13999 // Load the result.
14000 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14001 FIST, StackSlot, MachinePointerInfo(),
14002 false, false, false, 0);
14004 // The node is the result.
14008 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14009 SelectionDAG &DAG) const {
14010 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14011 /*IsSigned=*/ false, /*IsReplace=*/ false);
14012 SDValue FIST = Vals.first, StackSlot = Vals.second;
14013 assert(FIST.getNode() && "Unexpected failure");
14015 if (StackSlot.getNode())
14016 // Load the result.
14017 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14018 FIST, StackSlot, MachinePointerInfo(),
14019 false, false, false, 0);
14021 // The node is the result.
14025 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14027 MVT VT = Op.getSimpleValueType();
14028 SDValue In = Op.getOperand(0);
14029 MVT SVT = In.getSimpleValueType();
14031 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14033 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14034 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14035 In, DAG.getUNDEF(SVT)));
14038 /// The only differences between FABS and FNEG are the mask and the logic op.
14039 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14040 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14041 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14042 "Wrong opcode for lowering FABS or FNEG.");
14044 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14046 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14047 // into an FNABS. We'll lower the FABS after that if it is still in use.
14049 for (SDNode *User : Op->uses())
14050 if (User->getOpcode() == ISD::FNEG)
14053 SDValue Op0 = Op.getOperand(0);
14054 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14057 MVT VT = Op.getSimpleValueType();
14058 // Assume scalar op for initialization; update for vector if needed.
14059 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14060 // generate a 16-byte vector constant and logic op even for the scalar case.
14061 // Using a 16-byte mask allows folding the load of the mask with
14062 // the logic op, so it can save (~4 bytes) on code size.
14064 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14065 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14066 // decide if we should generate a 16-byte constant mask when we only need 4 or
14067 // 8 bytes for the scalar case.
14068 if (VT.isVector()) {
14069 EltVT = VT.getVectorElementType();
14070 NumElts = VT.getVectorNumElements();
14073 unsigned EltBits = EltVT.getSizeInBits();
14074 LLVMContext *Context = DAG.getContext();
14075 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14077 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14078 Constant *C = ConstantInt::get(*Context, MaskElt);
14079 C = ConstantVector::getSplat(NumElts, C);
14080 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14081 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14082 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14083 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14084 MachinePointerInfo::getConstantPool(),
14085 false, false, false, Alignment);
14087 if (VT.isVector()) {
14088 // For a vector, cast operands to a vector type, perform the logic op,
14089 // and cast the result back to the original value type.
14090 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14091 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14092 SDValue Operand = IsFNABS ?
14093 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14094 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14095 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14096 return DAG.getNode(ISD::BITCAST, dl, VT,
14097 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14100 // If not vector, then scalar.
14101 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14102 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14103 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14106 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14107 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14108 LLVMContext *Context = DAG.getContext();
14109 SDValue Op0 = Op.getOperand(0);
14110 SDValue Op1 = Op.getOperand(1);
14112 MVT VT = Op.getSimpleValueType();
14113 MVT SrcVT = Op1.getSimpleValueType();
14115 // If second operand is smaller, extend it first.
14116 if (SrcVT.bitsLT(VT)) {
14117 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14120 // And if it is bigger, shrink it first.
14121 if (SrcVT.bitsGT(VT)) {
14122 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14126 // At this point the operands and the result should have the same
14127 // type, and that won't be f80 since that is not custom lowered.
14129 // First get the sign bit of second operand.
14130 SmallVector<Constant*,4> CV;
14131 if (SrcVT == MVT::f64) {
14132 const fltSemantics &Sem = APFloat::IEEEdouble;
14133 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14134 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14136 const fltSemantics &Sem = APFloat::IEEEsingle;
14137 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14138 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14139 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14140 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14142 Constant *C = ConstantVector::get(CV);
14143 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14144 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14145 MachinePointerInfo::getConstantPool(),
14146 false, false, false, 16);
14147 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14149 // Shift sign bit right or left if the two operands have different types.
14150 if (SrcVT.bitsGT(VT)) {
14151 // Op0 is MVT::f32, Op1 is MVT::f64.
14152 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14153 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14154 DAG.getConstant(32, MVT::i32));
14155 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14156 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14157 DAG.getIntPtrConstant(0));
14160 // Clear first operand sign bit.
14162 if (VT == MVT::f64) {
14163 const fltSemantics &Sem = APFloat::IEEEdouble;
14164 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14165 APInt(64, ~(1ULL << 63)))));
14166 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14168 const fltSemantics &Sem = APFloat::IEEEsingle;
14169 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14170 APInt(32, ~(1U << 31)))));
14171 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14172 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14173 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14175 C = ConstantVector::get(CV);
14176 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14177 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14178 MachinePointerInfo::getConstantPool(),
14179 false, false, false, 16);
14180 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14182 // Or the value with the sign bit.
14183 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14186 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14187 SDValue N0 = Op.getOperand(0);
14189 MVT VT = Op.getSimpleValueType();
14191 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14192 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14193 DAG.getConstant(1, VT));
14194 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14197 // Check whether an OR'd tree is PTEST-able.
14198 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14199 SelectionDAG &DAG) {
14200 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14202 if (!Subtarget->hasSSE41())
14205 if (!Op->hasOneUse())
14208 SDNode *N = Op.getNode();
14211 SmallVector<SDValue, 8> Opnds;
14212 DenseMap<SDValue, unsigned> VecInMap;
14213 SmallVector<SDValue, 8> VecIns;
14214 EVT VT = MVT::Other;
14216 // Recognize a special case where a vector is casted into wide integer to
14218 Opnds.push_back(N->getOperand(0));
14219 Opnds.push_back(N->getOperand(1));
14221 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14222 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14223 // BFS traverse all OR'd operands.
14224 if (I->getOpcode() == ISD::OR) {
14225 Opnds.push_back(I->getOperand(0));
14226 Opnds.push_back(I->getOperand(1));
14227 // Re-evaluate the number of nodes to be traversed.
14228 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14232 // Quit if a non-EXTRACT_VECTOR_ELT
14233 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14236 // Quit if without a constant index.
14237 SDValue Idx = I->getOperand(1);
14238 if (!isa<ConstantSDNode>(Idx))
14241 SDValue ExtractedFromVec = I->getOperand(0);
14242 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14243 if (M == VecInMap.end()) {
14244 VT = ExtractedFromVec.getValueType();
14245 // Quit if not 128/256-bit vector.
14246 if (!VT.is128BitVector() && !VT.is256BitVector())
14248 // Quit if not the same type.
14249 if (VecInMap.begin() != VecInMap.end() &&
14250 VT != VecInMap.begin()->first.getValueType())
14252 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14253 VecIns.push_back(ExtractedFromVec);
14255 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14258 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14259 "Not extracted from 128-/256-bit vector.");
14261 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14263 for (DenseMap<SDValue, unsigned>::const_iterator
14264 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14265 // Quit if not all elements are used.
14266 if (I->second != FullMask)
14270 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14272 // Cast all vectors into TestVT for PTEST.
14273 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14274 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14276 // If more than one full vectors are evaluated, OR them first before PTEST.
14277 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14278 // Each iteration will OR 2 nodes and append the result until there is only
14279 // 1 node left, i.e. the final OR'd value of all vectors.
14280 SDValue LHS = VecIns[Slot];
14281 SDValue RHS = VecIns[Slot + 1];
14282 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14285 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14286 VecIns.back(), VecIns.back());
14289 /// \brief return true if \c Op has a use that doesn't just read flags.
14290 static bool hasNonFlagsUse(SDValue Op) {
14291 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14293 SDNode *User = *UI;
14294 unsigned UOpNo = UI.getOperandNo();
14295 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14296 // Look pass truncate.
14297 UOpNo = User->use_begin().getOperandNo();
14298 User = *User->use_begin();
14301 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14302 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14308 /// Emit nodes that will be selected as "test Op0,Op0", or something
14310 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14311 SelectionDAG &DAG) const {
14312 if (Op.getValueType() == MVT::i1)
14313 // KORTEST instruction should be selected
14314 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14315 DAG.getConstant(0, Op.getValueType()));
14317 // CF and OF aren't always set the way we want. Determine which
14318 // of these we need.
14319 bool NeedCF = false;
14320 bool NeedOF = false;
14323 case X86::COND_A: case X86::COND_AE:
14324 case X86::COND_B: case X86::COND_BE:
14327 case X86::COND_G: case X86::COND_GE:
14328 case X86::COND_L: case X86::COND_LE:
14329 case X86::COND_O: case X86::COND_NO: {
14330 // Check if we really need to set the
14331 // Overflow flag. If NoSignedWrap is present
14332 // that is not actually needed.
14333 switch (Op->getOpcode()) {
14338 const BinaryWithFlagsSDNode *BinNode =
14339 cast<BinaryWithFlagsSDNode>(Op.getNode());
14340 if (BinNode->hasNoSignedWrap())
14350 // See if we can use the EFLAGS value from the operand instead of
14351 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14352 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14353 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14354 // Emit a CMP with 0, which is the TEST pattern.
14355 //if (Op.getValueType() == MVT::i1)
14356 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14357 // DAG.getConstant(0, MVT::i1));
14358 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14359 DAG.getConstant(0, Op.getValueType()));
14361 unsigned Opcode = 0;
14362 unsigned NumOperands = 0;
14364 // Truncate operations may prevent the merge of the SETCC instruction
14365 // and the arithmetic instruction before it. Attempt to truncate the operands
14366 // of the arithmetic instruction and use a reduced bit-width instruction.
14367 bool NeedTruncation = false;
14368 SDValue ArithOp = Op;
14369 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14370 SDValue Arith = Op->getOperand(0);
14371 // Both the trunc and the arithmetic op need to have one user each.
14372 if (Arith->hasOneUse())
14373 switch (Arith.getOpcode()) {
14380 NeedTruncation = true;
14386 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14387 // which may be the result of a CAST. We use the variable 'Op', which is the
14388 // non-casted variable when we check for possible users.
14389 switch (ArithOp.getOpcode()) {
14391 // Due to an isel shortcoming, be conservative if this add is likely to be
14392 // selected as part of a load-modify-store instruction. When the root node
14393 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14394 // uses of other nodes in the match, such as the ADD in this case. This
14395 // leads to the ADD being left around and reselected, with the result being
14396 // two adds in the output. Alas, even if none our users are stores, that
14397 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14398 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14399 // climbing the DAG back to the root, and it doesn't seem to be worth the
14401 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14402 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14403 if (UI->getOpcode() != ISD::CopyToReg &&
14404 UI->getOpcode() != ISD::SETCC &&
14405 UI->getOpcode() != ISD::STORE)
14408 if (ConstantSDNode *C =
14409 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14410 // An add of one will be selected as an INC.
14411 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14412 Opcode = X86ISD::INC;
14417 // An add of negative one (subtract of one) will be selected as a DEC.
14418 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14419 Opcode = X86ISD::DEC;
14425 // Otherwise use a regular EFLAGS-setting add.
14426 Opcode = X86ISD::ADD;
14431 // If we have a constant logical shift that's only used in a comparison
14432 // against zero turn it into an equivalent AND. This allows turning it into
14433 // a TEST instruction later.
14434 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14435 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14436 EVT VT = Op.getValueType();
14437 unsigned BitWidth = VT.getSizeInBits();
14438 unsigned ShAmt = Op->getConstantOperandVal(1);
14439 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14441 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14442 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14443 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14444 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14446 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14447 DAG.getConstant(Mask, VT));
14448 DAG.ReplaceAllUsesWith(Op, New);
14454 // If the primary and result isn't used, don't bother using X86ISD::AND,
14455 // because a TEST instruction will be better.
14456 if (!hasNonFlagsUse(Op))
14462 // Due to the ISEL shortcoming noted above, be conservative if this op is
14463 // likely to be selected as part of a load-modify-store instruction.
14464 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14465 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14466 if (UI->getOpcode() == ISD::STORE)
14469 // Otherwise use a regular EFLAGS-setting instruction.
14470 switch (ArithOp.getOpcode()) {
14471 default: llvm_unreachable("unexpected operator!");
14472 case ISD::SUB: Opcode = X86ISD::SUB; break;
14473 case ISD::XOR: Opcode = X86ISD::XOR; break;
14474 case ISD::AND: Opcode = X86ISD::AND; break;
14476 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14477 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14478 if (EFLAGS.getNode())
14481 Opcode = X86ISD::OR;
14495 return SDValue(Op.getNode(), 1);
14501 // If we found that truncation is beneficial, perform the truncation and
14503 if (NeedTruncation) {
14504 EVT VT = Op.getValueType();
14505 SDValue WideVal = Op->getOperand(0);
14506 EVT WideVT = WideVal.getValueType();
14507 unsigned ConvertedOp = 0;
14508 // Use a target machine opcode to prevent further DAGCombine
14509 // optimizations that may separate the arithmetic operations
14510 // from the setcc node.
14511 switch (WideVal.getOpcode()) {
14513 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14514 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14515 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14516 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14517 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14521 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14522 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14523 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14524 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14525 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14531 // Emit a CMP with 0, which is the TEST pattern.
14532 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14533 DAG.getConstant(0, Op.getValueType()));
14535 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14536 SmallVector<SDValue, 4> Ops;
14537 for (unsigned i = 0; i != NumOperands; ++i)
14538 Ops.push_back(Op.getOperand(i));
14540 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14541 DAG.ReplaceAllUsesWith(Op, New);
14542 return SDValue(New.getNode(), 1);
14545 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14547 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14548 SDLoc dl, SelectionDAG &DAG) const {
14549 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14550 if (C->getAPIntValue() == 0)
14551 return EmitTest(Op0, X86CC, dl, DAG);
14553 if (Op0.getValueType() == MVT::i1)
14554 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14557 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14558 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14559 // Do the comparison at i32 if it's smaller, besides the Atom case.
14560 // This avoids subregister aliasing issues. Keep the smaller reference
14561 // if we're optimizing for size, however, as that'll allow better folding
14562 // of memory operations.
14563 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14564 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14565 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14566 !Subtarget->isAtom()) {
14567 unsigned ExtendOp =
14568 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14569 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14570 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14572 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14573 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14574 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14576 return SDValue(Sub.getNode(), 1);
14578 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14581 /// Convert a comparison if required by the subtarget.
14582 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14583 SelectionDAG &DAG) const {
14584 // If the subtarget does not support the FUCOMI instruction, floating-point
14585 // comparisons have to be converted.
14586 if (Subtarget->hasCMov() ||
14587 Cmp.getOpcode() != X86ISD::CMP ||
14588 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14589 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14592 // The instruction selector will select an FUCOM instruction instead of
14593 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14594 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14595 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14597 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14598 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14599 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14600 DAG.getConstant(8, MVT::i8));
14601 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14602 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14605 /// The minimum architected relative accuracy is 2^-12. We need one
14606 /// Newton-Raphson step to have a good float result (24 bits of precision).
14607 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14608 DAGCombinerInfo &DCI,
14609 unsigned &RefinementSteps,
14610 bool &UseOneConstNR) const {
14611 // FIXME: We should use instruction latency models to calculate the cost of
14612 // each potential sequence, but this is very hard to do reliably because
14613 // at least Intel's Core* chips have variable timing based on the number of
14614 // significant digits in the divisor and/or sqrt operand.
14615 if (!Subtarget->useSqrtEst())
14618 EVT VT = Op.getValueType();
14620 // SSE1 has rsqrtss and rsqrtps.
14621 // TODO: Add support for AVX512 (v16f32).
14622 // It is likely not profitable to do this for f64 because a double-precision
14623 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14624 // instructions: convert to single, rsqrtss, convert back to double, refine
14625 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14626 // along with FMA, this could be a throughput win.
14627 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14628 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14629 RefinementSteps = 1;
14630 UseOneConstNR = false;
14631 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14636 /// The minimum architected relative accuracy is 2^-12. We need one
14637 /// Newton-Raphson step to have a good float result (24 bits of precision).
14638 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14639 DAGCombinerInfo &DCI,
14640 unsigned &RefinementSteps) const {
14641 // FIXME: We should use instruction latency models to calculate the cost of
14642 // each potential sequence, but this is very hard to do reliably because
14643 // at least Intel's Core* chips have variable timing based on the number of
14644 // significant digits in the divisor.
14645 if (!Subtarget->useReciprocalEst())
14648 EVT VT = Op.getValueType();
14650 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14651 // TODO: Add support for AVX512 (v16f32).
14652 // It is likely not profitable to do this for f64 because a double-precision
14653 // reciprocal estimate with refinement on x86 prior to FMA requires
14654 // 15 instructions: convert to single, rcpss, convert back to double, refine
14655 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14656 // along with FMA, this could be a throughput win.
14657 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14658 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14659 RefinementSteps = ReciprocalEstimateRefinementSteps;
14660 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14665 static bool isAllOnes(SDValue V) {
14666 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14667 return C && C->isAllOnesValue();
14670 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14671 /// if it's possible.
14672 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14673 SDLoc dl, SelectionDAG &DAG) const {
14674 SDValue Op0 = And.getOperand(0);
14675 SDValue Op1 = And.getOperand(1);
14676 if (Op0.getOpcode() == ISD::TRUNCATE)
14677 Op0 = Op0.getOperand(0);
14678 if (Op1.getOpcode() == ISD::TRUNCATE)
14679 Op1 = Op1.getOperand(0);
14682 if (Op1.getOpcode() == ISD::SHL)
14683 std::swap(Op0, Op1);
14684 if (Op0.getOpcode() == ISD::SHL) {
14685 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14686 if (And00C->getZExtValue() == 1) {
14687 // If we looked past a truncate, check that it's only truncating away
14689 unsigned BitWidth = Op0.getValueSizeInBits();
14690 unsigned AndBitWidth = And.getValueSizeInBits();
14691 if (BitWidth > AndBitWidth) {
14693 DAG.computeKnownBits(Op0, Zeros, Ones);
14694 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14698 RHS = Op0.getOperand(1);
14700 } else if (Op1.getOpcode() == ISD::Constant) {
14701 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14702 uint64_t AndRHSVal = AndRHS->getZExtValue();
14703 SDValue AndLHS = Op0;
14705 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14706 LHS = AndLHS.getOperand(0);
14707 RHS = AndLHS.getOperand(1);
14710 // Use BT if the immediate can't be encoded in a TEST instruction.
14711 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14713 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14717 if (LHS.getNode()) {
14718 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14719 // instruction. Since the shift amount is in-range-or-undefined, we know
14720 // that doing a bittest on the i32 value is ok. We extend to i32 because
14721 // the encoding for the i16 version is larger than the i32 version.
14722 // Also promote i16 to i32 for performance / code size reason.
14723 if (LHS.getValueType() == MVT::i8 ||
14724 LHS.getValueType() == MVT::i16)
14725 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14727 // If the operand types disagree, extend the shift amount to match. Since
14728 // BT ignores high bits (like shifts) we can use anyextend.
14729 if (LHS.getValueType() != RHS.getValueType())
14730 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14732 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14733 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14734 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14735 DAG.getConstant(Cond, MVT::i8), BT);
14741 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14743 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14748 // SSE Condition code mapping:
14757 switch (SetCCOpcode) {
14758 default: llvm_unreachable("Unexpected SETCC condition");
14760 case ISD::SETEQ: SSECC = 0; break;
14762 case ISD::SETGT: Swap = true; // Fallthrough
14764 case ISD::SETOLT: SSECC = 1; break;
14766 case ISD::SETGE: Swap = true; // Fallthrough
14768 case ISD::SETOLE: SSECC = 2; break;
14769 case ISD::SETUO: SSECC = 3; break;
14771 case ISD::SETNE: SSECC = 4; break;
14772 case ISD::SETULE: Swap = true; // Fallthrough
14773 case ISD::SETUGE: SSECC = 5; break;
14774 case ISD::SETULT: Swap = true; // Fallthrough
14775 case ISD::SETUGT: SSECC = 6; break;
14776 case ISD::SETO: SSECC = 7; break;
14778 case ISD::SETONE: SSECC = 8; break;
14781 std::swap(Op0, Op1);
14786 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14787 // ones, and then concatenate the result back.
14788 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14789 MVT VT = Op.getSimpleValueType();
14791 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14792 "Unsupported value type for operation");
14794 unsigned NumElems = VT.getVectorNumElements();
14796 SDValue CC = Op.getOperand(2);
14798 // Extract the LHS vectors
14799 SDValue LHS = Op.getOperand(0);
14800 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14801 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14803 // Extract the RHS vectors
14804 SDValue RHS = Op.getOperand(1);
14805 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14806 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14808 // Issue the operation on the smaller types and concatenate the result back
14809 MVT EltVT = VT.getVectorElementType();
14810 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14811 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14812 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14813 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14816 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14817 const X86Subtarget *Subtarget) {
14818 SDValue Op0 = Op.getOperand(0);
14819 SDValue Op1 = Op.getOperand(1);
14820 SDValue CC = Op.getOperand(2);
14821 MVT VT = Op.getSimpleValueType();
14824 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14825 Op.getValueType().getScalarType() == MVT::i1 &&
14826 "Cannot set masked compare for this operation");
14828 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14830 bool Unsigned = false;
14833 switch (SetCCOpcode) {
14834 default: llvm_unreachable("Unexpected SETCC condition");
14835 case ISD::SETNE: SSECC = 4; break;
14836 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14837 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14838 case ISD::SETLT: Swap = true; //fall-through
14839 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14840 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14841 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14842 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14843 case ISD::SETULE: Unsigned = true; //fall-through
14844 case ISD::SETLE: SSECC = 2; break;
14848 std::swap(Op0, Op1);
14850 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14851 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14852 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14853 DAG.getConstant(SSECC, MVT::i8));
14856 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14857 /// operand \p Op1. If non-trivial (for example because it's not constant)
14858 /// return an empty value.
14859 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14861 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14865 MVT VT = Op1.getSimpleValueType();
14866 MVT EVT = VT.getVectorElementType();
14867 unsigned n = VT.getVectorNumElements();
14868 SmallVector<SDValue, 8> ULTOp1;
14870 for (unsigned i = 0; i < n; ++i) {
14871 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14872 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14875 // Avoid underflow.
14876 APInt Val = Elt->getAPIntValue();
14880 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14883 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14886 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14887 SelectionDAG &DAG) {
14888 SDValue Op0 = Op.getOperand(0);
14889 SDValue Op1 = Op.getOperand(1);
14890 SDValue CC = Op.getOperand(2);
14891 MVT VT = Op.getSimpleValueType();
14892 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14893 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14898 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14899 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14902 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14903 unsigned Opc = X86ISD::CMPP;
14904 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14905 assert(VT.getVectorNumElements() <= 16);
14906 Opc = X86ISD::CMPM;
14908 // In the two special cases we can't handle, emit two comparisons.
14911 unsigned CombineOpc;
14912 if (SetCCOpcode == ISD::SETUEQ) {
14913 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14915 assert(SetCCOpcode == ISD::SETONE);
14916 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14919 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14920 DAG.getConstant(CC0, MVT::i8));
14921 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14922 DAG.getConstant(CC1, MVT::i8));
14923 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14925 // Handle all other FP comparisons here.
14926 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14927 DAG.getConstant(SSECC, MVT::i8));
14930 // Break 256-bit integer vector compare into smaller ones.
14931 if (VT.is256BitVector() && !Subtarget->hasInt256())
14932 return Lower256IntVSETCC(Op, DAG);
14934 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14935 EVT OpVT = Op1.getValueType();
14936 if (Subtarget->hasAVX512()) {
14937 if (Op1.getValueType().is512BitVector() ||
14938 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14939 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14940 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14942 // In AVX-512 architecture setcc returns mask with i1 elements,
14943 // But there is no compare instruction for i8 and i16 elements in KNL.
14944 // We are not talking about 512-bit operands in this case, these
14945 // types are illegal.
14947 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14948 OpVT.getVectorElementType().getSizeInBits() >= 8))
14949 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14950 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14953 // We are handling one of the integer comparisons here. Since SSE only has
14954 // GT and EQ comparisons for integer, swapping operands and multiple
14955 // operations may be required for some comparisons.
14957 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14958 bool Subus = false;
14960 switch (SetCCOpcode) {
14961 default: llvm_unreachable("Unexpected SETCC condition");
14962 case ISD::SETNE: Invert = true;
14963 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14964 case ISD::SETLT: Swap = true;
14965 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14966 case ISD::SETGE: Swap = true;
14967 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14968 Invert = true; break;
14969 case ISD::SETULT: Swap = true;
14970 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14971 FlipSigns = true; break;
14972 case ISD::SETUGE: Swap = true;
14973 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14974 FlipSigns = true; Invert = true; break;
14977 // Special case: Use min/max operations for SETULE/SETUGE
14978 MVT VET = VT.getVectorElementType();
14980 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14981 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14984 switch (SetCCOpcode) {
14986 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14987 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14990 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14993 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14994 if (!MinMax && hasSubus) {
14995 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14997 // t = psubus Op0, Op1
14998 // pcmpeq t, <0..0>
14999 switch (SetCCOpcode) {
15001 case ISD::SETULT: {
15002 // If the comparison is against a constant we can turn this into a
15003 // setule. With psubus, setule does not require a swap. This is
15004 // beneficial because the constant in the register is no longer
15005 // destructed as the destination so it can be hoisted out of a loop.
15006 // Only do this pre-AVX since vpcmp* is no longer destructive.
15007 if (Subtarget->hasAVX())
15009 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15010 if (ULEOp1.getNode()) {
15012 Subus = true; Invert = false; Swap = false;
15016 // Psubus is better than flip-sign because it requires no inversion.
15017 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15018 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15022 Opc = X86ISD::SUBUS;
15028 std::swap(Op0, Op1);
15030 // Check that the operation in question is available (most are plain SSE2,
15031 // but PCMPGTQ and PCMPEQQ have different requirements).
15032 if (VT == MVT::v2i64) {
15033 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15034 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15036 // First cast everything to the right type.
15037 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15038 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15040 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15041 // bits of the inputs before performing those operations. The lower
15042 // compare is always unsigned.
15045 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15047 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15048 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15049 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15050 Sign, Zero, Sign, Zero);
15052 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15053 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15055 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15056 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15057 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15059 // Create masks for only the low parts/high parts of the 64 bit integers.
15060 static const int MaskHi[] = { 1, 1, 3, 3 };
15061 static const int MaskLo[] = { 0, 0, 2, 2 };
15062 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15063 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15064 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15066 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15067 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15070 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15072 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15075 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15076 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15077 // pcmpeqd + pshufd + pand.
15078 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15080 // First cast everything to the right type.
15081 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15082 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15085 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15087 // Make sure the lower and upper halves are both all-ones.
15088 static const int Mask[] = { 1, 0, 3, 2 };
15089 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15090 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15093 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15095 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15099 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15100 // bits of the inputs before performing those operations.
15102 EVT EltVT = VT.getVectorElementType();
15103 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15104 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15105 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15108 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15110 // If the logical-not of the result is required, perform that now.
15112 Result = DAG.getNOT(dl, Result, VT);
15115 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15118 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15119 getZeroVector(VT, Subtarget, DAG, dl));
15124 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15126 MVT VT = Op.getSimpleValueType();
15128 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15130 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15131 && "SetCC type must be 8-bit or 1-bit integer");
15132 SDValue Op0 = Op.getOperand(0);
15133 SDValue Op1 = Op.getOperand(1);
15135 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15137 // Optimize to BT if possible.
15138 // Lower (X & (1 << N)) == 0 to BT(X, N).
15139 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15140 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15141 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15142 Op1.getOpcode() == ISD::Constant &&
15143 cast<ConstantSDNode>(Op1)->isNullValue() &&
15144 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15145 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15146 if (NewSetCC.getNode())
15150 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15152 if (Op1.getOpcode() == ISD::Constant &&
15153 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15154 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15155 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15157 // If the input is a setcc, then reuse the input setcc or use a new one with
15158 // the inverted condition.
15159 if (Op0.getOpcode() == X86ISD::SETCC) {
15160 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15161 bool Invert = (CC == ISD::SETNE) ^
15162 cast<ConstantSDNode>(Op1)->isNullValue();
15166 CCode = X86::GetOppositeBranchCondition(CCode);
15167 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15168 DAG.getConstant(CCode, MVT::i8),
15169 Op0.getOperand(1));
15171 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15175 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15176 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15177 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15179 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15180 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15183 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15184 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15185 if (X86CC == X86::COND_INVALID)
15188 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15189 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15190 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15191 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15193 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15197 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15198 static bool isX86LogicalCmp(SDValue Op) {
15199 unsigned Opc = Op.getNode()->getOpcode();
15200 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15201 Opc == X86ISD::SAHF)
15203 if (Op.getResNo() == 1 &&
15204 (Opc == X86ISD::ADD ||
15205 Opc == X86ISD::SUB ||
15206 Opc == X86ISD::ADC ||
15207 Opc == X86ISD::SBB ||
15208 Opc == X86ISD::SMUL ||
15209 Opc == X86ISD::UMUL ||
15210 Opc == X86ISD::INC ||
15211 Opc == X86ISD::DEC ||
15212 Opc == X86ISD::OR ||
15213 Opc == X86ISD::XOR ||
15214 Opc == X86ISD::AND))
15217 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15223 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15224 if (V.getOpcode() != ISD::TRUNCATE)
15227 SDValue VOp0 = V.getOperand(0);
15228 unsigned InBits = VOp0.getValueSizeInBits();
15229 unsigned Bits = V.getValueSizeInBits();
15230 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15233 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15234 bool addTest = true;
15235 SDValue Cond = Op.getOperand(0);
15236 SDValue Op1 = Op.getOperand(1);
15237 SDValue Op2 = Op.getOperand(2);
15239 EVT VT = Op1.getValueType();
15242 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15243 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15244 // sequence later on.
15245 if (Cond.getOpcode() == ISD::SETCC &&
15246 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15247 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15248 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15249 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15250 int SSECC = translateX86FSETCC(
15251 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15254 if (Subtarget->hasAVX512()) {
15255 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15256 DAG.getConstant(SSECC, MVT::i8));
15257 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15259 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15260 DAG.getConstant(SSECC, MVT::i8));
15261 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15262 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15263 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15267 if (Cond.getOpcode() == ISD::SETCC) {
15268 SDValue NewCond = LowerSETCC(Cond, DAG);
15269 if (NewCond.getNode())
15273 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15274 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15275 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15276 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15277 if (Cond.getOpcode() == X86ISD::SETCC &&
15278 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15279 isZero(Cond.getOperand(1).getOperand(1))) {
15280 SDValue Cmp = Cond.getOperand(1);
15282 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15284 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15285 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15286 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15288 SDValue CmpOp0 = Cmp.getOperand(0);
15289 // Apply further optimizations for special cases
15290 // (select (x != 0), -1, 0) -> neg & sbb
15291 // (select (x == 0), 0, -1) -> neg & sbb
15292 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15293 if (YC->isNullValue() &&
15294 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15295 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15296 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15297 DAG.getConstant(0, CmpOp0.getValueType()),
15299 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15300 DAG.getConstant(X86::COND_B, MVT::i8),
15301 SDValue(Neg.getNode(), 1));
15305 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15306 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15307 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15309 SDValue Res = // Res = 0 or -1.
15310 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15311 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15313 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15314 Res = DAG.getNOT(DL, Res, Res.getValueType());
15316 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15317 if (!N2C || !N2C->isNullValue())
15318 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15323 // Look past (and (setcc_carry (cmp ...)), 1).
15324 if (Cond.getOpcode() == ISD::AND &&
15325 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15326 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15327 if (C && C->getAPIntValue() == 1)
15328 Cond = Cond.getOperand(0);
15331 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15332 // setting operand in place of the X86ISD::SETCC.
15333 unsigned CondOpcode = Cond.getOpcode();
15334 if (CondOpcode == X86ISD::SETCC ||
15335 CondOpcode == X86ISD::SETCC_CARRY) {
15336 CC = Cond.getOperand(0);
15338 SDValue Cmp = Cond.getOperand(1);
15339 unsigned Opc = Cmp.getOpcode();
15340 MVT VT = Op.getSimpleValueType();
15342 bool IllegalFPCMov = false;
15343 if (VT.isFloatingPoint() && !VT.isVector() &&
15344 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15345 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15347 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15348 Opc == X86ISD::BT) { // FIXME
15352 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15353 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15354 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15355 Cond.getOperand(0).getValueType() != MVT::i8)) {
15356 SDValue LHS = Cond.getOperand(0);
15357 SDValue RHS = Cond.getOperand(1);
15358 unsigned X86Opcode;
15361 switch (CondOpcode) {
15362 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15363 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15364 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15365 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15366 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15367 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15368 default: llvm_unreachable("unexpected overflowing operator");
15370 if (CondOpcode == ISD::UMULO)
15371 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15374 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15376 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15378 if (CondOpcode == ISD::UMULO)
15379 Cond = X86Op.getValue(2);
15381 Cond = X86Op.getValue(1);
15383 CC = DAG.getConstant(X86Cond, MVT::i8);
15388 // Look pass the truncate if the high bits are known zero.
15389 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15390 Cond = Cond.getOperand(0);
15392 // We know the result of AND is compared against zero. Try to match
15394 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15395 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15396 if (NewSetCC.getNode()) {
15397 CC = NewSetCC.getOperand(0);
15398 Cond = NewSetCC.getOperand(1);
15405 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15406 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15409 // a < b ? -1 : 0 -> RES = ~setcc_carry
15410 // a < b ? 0 : -1 -> RES = setcc_carry
15411 // a >= b ? -1 : 0 -> RES = setcc_carry
15412 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15413 if (Cond.getOpcode() == X86ISD::SUB) {
15414 Cond = ConvertCmpIfNecessary(Cond, DAG);
15415 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15417 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15418 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15419 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15420 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15421 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15422 return DAG.getNOT(DL, Res, Res.getValueType());
15427 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15428 // widen the cmov and push the truncate through. This avoids introducing a new
15429 // branch during isel and doesn't add any extensions.
15430 if (Op.getValueType() == MVT::i8 &&
15431 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15432 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15433 if (T1.getValueType() == T2.getValueType() &&
15434 // Blacklist CopyFromReg to avoid partial register stalls.
15435 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15436 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15437 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15438 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15442 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15443 // condition is true.
15444 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15445 SDValue Ops[] = { Op2, Op1, CC, Cond };
15446 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15449 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15450 SelectionDAG &DAG) {
15451 MVT VT = Op->getSimpleValueType(0);
15452 SDValue In = Op->getOperand(0);
15453 MVT InVT = In.getSimpleValueType();
15454 MVT VTElt = VT.getVectorElementType();
15455 MVT InVTElt = InVT.getVectorElementType();
15459 if ((InVTElt == MVT::i1) &&
15460 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15461 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15463 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15464 VTElt.getSizeInBits() <= 16)) ||
15466 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15467 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15469 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15470 VTElt.getSizeInBits() >= 32))))
15471 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15473 unsigned int NumElts = VT.getVectorNumElements();
15475 if (NumElts != 8 && NumElts != 16)
15478 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15479 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15480 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15481 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15484 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15485 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15487 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15488 Constant *C = ConstantInt::get(*DAG.getContext(),
15489 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15491 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15492 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15493 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15494 MachinePointerInfo::getConstantPool(),
15495 false, false, false, Alignment);
15496 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15497 if (VT.is512BitVector())
15499 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15502 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15503 SelectionDAG &DAG) {
15504 MVT VT = Op->getSimpleValueType(0);
15505 SDValue In = Op->getOperand(0);
15506 MVT InVT = In.getSimpleValueType();
15509 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15510 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15512 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15513 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15514 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15517 if (Subtarget->hasInt256())
15518 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15520 // Optimize vectors in AVX mode
15521 // Sign extend v8i16 to v8i32 and
15524 // Divide input vector into two parts
15525 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15526 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15527 // concat the vectors to original VT
15529 unsigned NumElems = InVT.getVectorNumElements();
15530 SDValue Undef = DAG.getUNDEF(InVT);
15532 SmallVector<int,8> ShufMask1(NumElems, -1);
15533 for (unsigned i = 0; i != NumElems/2; ++i)
15536 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15538 SmallVector<int,8> ShufMask2(NumElems, -1);
15539 for (unsigned i = 0; i != NumElems/2; ++i)
15540 ShufMask2[i] = i + NumElems/2;
15542 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15544 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15545 VT.getVectorNumElements()/2);
15547 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15548 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15550 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15553 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15554 // may emit an illegal shuffle but the expansion is still better than scalar
15555 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15556 // we'll emit a shuffle and a arithmetic shift.
15557 // TODO: It is possible to support ZExt by zeroing the undef values during
15558 // the shuffle phase or after the shuffle.
15559 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15560 SelectionDAG &DAG) {
15561 MVT RegVT = Op.getSimpleValueType();
15562 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15563 assert(RegVT.isInteger() &&
15564 "We only custom lower integer vector sext loads.");
15566 // Nothing useful we can do without SSE2 shuffles.
15567 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15569 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15571 EVT MemVT = Ld->getMemoryVT();
15572 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15573 unsigned RegSz = RegVT.getSizeInBits();
15575 ISD::LoadExtType Ext = Ld->getExtensionType();
15577 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15578 && "Only anyext and sext are currently implemented.");
15579 assert(MemVT != RegVT && "Cannot extend to the same type");
15580 assert(MemVT.isVector() && "Must load a vector from memory");
15582 unsigned NumElems = RegVT.getVectorNumElements();
15583 unsigned MemSz = MemVT.getSizeInBits();
15584 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15586 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15587 // The only way in which we have a legal 256-bit vector result but not the
15588 // integer 256-bit operations needed to directly lower a sextload is if we
15589 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15590 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15591 // correctly legalized. We do this late to allow the canonical form of
15592 // sextload to persist throughout the rest of the DAG combiner -- it wants
15593 // to fold together any extensions it can, and so will fuse a sign_extend
15594 // of an sextload into a sextload targeting a wider value.
15596 if (MemSz == 128) {
15597 // Just switch this to a normal load.
15598 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15599 "it must be a legal 128-bit vector "
15601 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15602 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15603 Ld->isInvariant(), Ld->getAlignment());
15605 assert(MemSz < 128 &&
15606 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15607 // Do an sext load to a 128-bit vector type. We want to use the same
15608 // number of elements, but elements half as wide. This will end up being
15609 // recursively lowered by this routine, but will succeed as we definitely
15610 // have all the necessary features if we're using AVX1.
15612 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15613 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15615 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15616 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15617 Ld->isNonTemporal(), Ld->isInvariant(),
15618 Ld->getAlignment());
15621 // Replace chain users with the new chain.
15622 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15623 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15625 // Finally, do a normal sign-extend to the desired register.
15626 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15629 // All sizes must be a power of two.
15630 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15631 "Non-power-of-two elements are not custom lowered!");
15633 // Attempt to load the original value using scalar loads.
15634 // Find the largest scalar type that divides the total loaded size.
15635 MVT SclrLoadTy = MVT::i8;
15636 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15637 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15638 MVT Tp = (MVT::SimpleValueType)tp;
15639 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15644 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15645 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15647 SclrLoadTy = MVT::f64;
15649 // Calculate the number of scalar loads that we need to perform
15650 // in order to load our vector from memory.
15651 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15653 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15654 "Can only lower sext loads with a single scalar load!");
15656 unsigned loadRegZize = RegSz;
15657 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15660 // Represent our vector as a sequence of elements which are the
15661 // largest scalar that we can load.
15662 EVT LoadUnitVecVT = EVT::getVectorVT(
15663 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15665 // Represent the data using the same element type that is stored in
15666 // memory. In practice, we ''widen'' MemVT.
15668 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15669 loadRegZize / MemVT.getScalarType().getSizeInBits());
15671 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15672 "Invalid vector type");
15674 // We can't shuffle using an illegal type.
15675 assert(TLI.isTypeLegal(WideVecVT) &&
15676 "We only lower types that form legal widened vector types");
15678 SmallVector<SDValue, 8> Chains;
15679 SDValue Ptr = Ld->getBasePtr();
15680 SDValue Increment =
15681 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15682 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15684 for (unsigned i = 0; i < NumLoads; ++i) {
15685 // Perform a single load.
15686 SDValue ScalarLoad =
15687 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15688 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15689 Ld->getAlignment());
15690 Chains.push_back(ScalarLoad.getValue(1));
15691 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15692 // another round of DAGCombining.
15694 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15696 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15697 ScalarLoad, DAG.getIntPtrConstant(i));
15699 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15702 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15704 // Bitcast the loaded value to a vector of the original element type, in
15705 // the size of the target vector type.
15706 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15707 unsigned SizeRatio = RegSz / MemSz;
15709 if (Ext == ISD::SEXTLOAD) {
15710 // If we have SSE4.1, we can directly emit a VSEXT node.
15711 if (Subtarget->hasSSE41()) {
15712 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15713 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15717 // Otherwise we'll shuffle the small elements in the high bits of the
15718 // larger type and perform an arithmetic shift. If the shift is not legal
15719 // it's better to scalarize.
15720 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15721 "We can't implement a sext load without an arithmetic right shift!");
15723 // Redistribute the loaded elements into the different locations.
15724 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15725 for (unsigned i = 0; i != NumElems; ++i)
15726 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15728 SDValue Shuff = DAG.getVectorShuffle(
15729 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15731 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15733 // Build the arithmetic shift.
15734 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15735 MemVT.getVectorElementType().getSizeInBits();
15737 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15739 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15743 // Redistribute the loaded elements into the different locations.
15744 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15745 for (unsigned i = 0; i != NumElems; ++i)
15746 ShuffleVec[i * SizeRatio] = i;
15748 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15749 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15751 // Bitcast to the requested type.
15752 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15753 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15757 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15758 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15759 // from the AND / OR.
15760 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15761 Opc = Op.getOpcode();
15762 if (Opc != ISD::OR && Opc != ISD::AND)
15764 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15765 Op.getOperand(0).hasOneUse() &&
15766 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15767 Op.getOperand(1).hasOneUse());
15770 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15771 // 1 and that the SETCC node has a single use.
15772 static bool isXor1OfSetCC(SDValue Op) {
15773 if (Op.getOpcode() != ISD::XOR)
15775 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15776 if (N1C && N1C->getAPIntValue() == 1) {
15777 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15778 Op.getOperand(0).hasOneUse();
15783 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15784 bool addTest = true;
15785 SDValue Chain = Op.getOperand(0);
15786 SDValue Cond = Op.getOperand(1);
15787 SDValue Dest = Op.getOperand(2);
15790 bool Inverted = false;
15792 if (Cond.getOpcode() == ISD::SETCC) {
15793 // Check for setcc([su]{add,sub,mul}o == 0).
15794 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15795 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15796 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15797 Cond.getOperand(0).getResNo() == 1 &&
15798 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15799 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15800 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15801 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15802 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15803 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15805 Cond = Cond.getOperand(0);
15807 SDValue NewCond = LowerSETCC(Cond, DAG);
15808 if (NewCond.getNode())
15813 // FIXME: LowerXALUO doesn't handle these!!
15814 else if (Cond.getOpcode() == X86ISD::ADD ||
15815 Cond.getOpcode() == X86ISD::SUB ||
15816 Cond.getOpcode() == X86ISD::SMUL ||
15817 Cond.getOpcode() == X86ISD::UMUL)
15818 Cond = LowerXALUO(Cond, DAG);
15821 // Look pass (and (setcc_carry (cmp ...)), 1).
15822 if (Cond.getOpcode() == ISD::AND &&
15823 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15824 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15825 if (C && C->getAPIntValue() == 1)
15826 Cond = Cond.getOperand(0);
15829 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15830 // setting operand in place of the X86ISD::SETCC.
15831 unsigned CondOpcode = Cond.getOpcode();
15832 if (CondOpcode == X86ISD::SETCC ||
15833 CondOpcode == X86ISD::SETCC_CARRY) {
15834 CC = Cond.getOperand(0);
15836 SDValue Cmp = Cond.getOperand(1);
15837 unsigned Opc = Cmp.getOpcode();
15838 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15839 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15843 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15847 // These can only come from an arithmetic instruction with overflow,
15848 // e.g. SADDO, UADDO.
15849 Cond = Cond.getNode()->getOperand(1);
15855 CondOpcode = Cond.getOpcode();
15856 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15857 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15858 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15859 Cond.getOperand(0).getValueType() != MVT::i8)) {
15860 SDValue LHS = Cond.getOperand(0);
15861 SDValue RHS = Cond.getOperand(1);
15862 unsigned X86Opcode;
15865 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15866 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15868 switch (CondOpcode) {
15869 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15871 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15873 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15876 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15877 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15879 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15881 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15884 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15885 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15886 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15887 default: llvm_unreachable("unexpected overflowing operator");
15890 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15891 if (CondOpcode == ISD::UMULO)
15892 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15895 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15897 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15899 if (CondOpcode == ISD::UMULO)
15900 Cond = X86Op.getValue(2);
15902 Cond = X86Op.getValue(1);
15904 CC = DAG.getConstant(X86Cond, MVT::i8);
15908 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15909 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15910 if (CondOpc == ISD::OR) {
15911 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15912 // two branches instead of an explicit OR instruction with a
15914 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15915 isX86LogicalCmp(Cmp)) {
15916 CC = Cond.getOperand(0).getOperand(0);
15917 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15918 Chain, Dest, CC, Cmp);
15919 CC = Cond.getOperand(1).getOperand(0);
15923 } else { // ISD::AND
15924 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15925 // two branches instead of an explicit AND instruction with a
15926 // separate test. However, we only do this if this block doesn't
15927 // have a fall-through edge, because this requires an explicit
15928 // jmp when the condition is false.
15929 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15930 isX86LogicalCmp(Cmp) &&
15931 Op.getNode()->hasOneUse()) {
15932 X86::CondCode CCode =
15933 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15934 CCode = X86::GetOppositeBranchCondition(CCode);
15935 CC = DAG.getConstant(CCode, MVT::i8);
15936 SDNode *User = *Op.getNode()->use_begin();
15937 // Look for an unconditional branch following this conditional branch.
15938 // We need this because we need to reverse the successors in order
15939 // to implement FCMP_OEQ.
15940 if (User->getOpcode() == ISD::BR) {
15941 SDValue FalseBB = User->getOperand(1);
15943 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15944 assert(NewBR == User);
15948 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15949 Chain, Dest, CC, Cmp);
15950 X86::CondCode CCode =
15951 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15952 CCode = X86::GetOppositeBranchCondition(CCode);
15953 CC = DAG.getConstant(CCode, MVT::i8);
15959 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15960 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15961 // It should be transformed during dag combiner except when the condition
15962 // is set by a arithmetics with overflow node.
15963 X86::CondCode CCode =
15964 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15965 CCode = X86::GetOppositeBranchCondition(CCode);
15966 CC = DAG.getConstant(CCode, MVT::i8);
15967 Cond = Cond.getOperand(0).getOperand(1);
15969 } else if (Cond.getOpcode() == ISD::SETCC &&
15970 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15971 // For FCMP_OEQ, we can emit
15972 // two branches instead of an explicit AND instruction with a
15973 // separate test. However, we only do this if this block doesn't
15974 // have a fall-through edge, because this requires an explicit
15975 // jmp when the condition is false.
15976 if (Op.getNode()->hasOneUse()) {
15977 SDNode *User = *Op.getNode()->use_begin();
15978 // Look for an unconditional branch following this conditional branch.
15979 // We need this because we need to reverse the successors in order
15980 // to implement FCMP_OEQ.
15981 if (User->getOpcode() == ISD::BR) {
15982 SDValue FalseBB = User->getOperand(1);
15984 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15985 assert(NewBR == User);
15989 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15990 Cond.getOperand(0), Cond.getOperand(1));
15991 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15992 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15993 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15994 Chain, Dest, CC, Cmp);
15995 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16000 } else if (Cond.getOpcode() == ISD::SETCC &&
16001 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16002 // For FCMP_UNE, we can emit
16003 // two branches instead of an explicit AND instruction with a
16004 // separate test. However, we only do this if this block doesn't
16005 // have a fall-through edge, because this requires an explicit
16006 // jmp when the condition is false.
16007 if (Op.getNode()->hasOneUse()) {
16008 SDNode *User = *Op.getNode()->use_begin();
16009 // Look for an unconditional branch following this conditional branch.
16010 // We need this because we need to reverse the successors in order
16011 // to implement FCMP_UNE.
16012 if (User->getOpcode() == ISD::BR) {
16013 SDValue FalseBB = User->getOperand(1);
16015 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16016 assert(NewBR == User);
16019 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16020 Cond.getOperand(0), Cond.getOperand(1));
16021 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16022 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16023 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16024 Chain, Dest, CC, Cmp);
16025 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16035 // Look pass the truncate if the high bits are known zero.
16036 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16037 Cond = Cond.getOperand(0);
16039 // We know the result of AND is compared against zero. Try to match
16041 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16042 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16043 if (NewSetCC.getNode()) {
16044 CC = NewSetCC.getOperand(0);
16045 Cond = NewSetCC.getOperand(1);
16052 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16053 CC = DAG.getConstant(X86Cond, MVT::i8);
16054 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16056 Cond = ConvertCmpIfNecessary(Cond, DAG);
16057 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16058 Chain, Dest, CC, Cond);
16061 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16062 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16063 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16064 // that the guard pages used by the OS virtual memory manager are allocated in
16065 // correct sequence.
16067 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16068 SelectionDAG &DAG) const {
16069 MachineFunction &MF = DAG.getMachineFunction();
16070 bool SplitStack = MF.shouldSplitStack();
16071 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
16076 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16077 SDNode* Node = Op.getNode();
16079 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16080 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16081 " not tell us which reg is the stack pointer!");
16082 EVT VT = Node->getValueType(0);
16083 SDValue Tmp1 = SDValue(Node, 0);
16084 SDValue Tmp2 = SDValue(Node, 1);
16085 SDValue Tmp3 = Node->getOperand(2);
16086 SDValue Chain = Tmp1.getOperand(0);
16088 // Chain the dynamic stack allocation so that it doesn't modify the stack
16089 // pointer when other instructions are using the stack.
16090 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16093 SDValue Size = Tmp2.getOperand(1);
16094 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16095 Chain = SP.getValue(1);
16096 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16097 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16098 unsigned StackAlign = TFI.getStackAlignment();
16099 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16100 if (Align > StackAlign)
16101 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16102 DAG.getConstant(-(uint64_t)Align, VT));
16103 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16105 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16106 DAG.getIntPtrConstant(0, true), SDValue(),
16109 SDValue Ops[2] = { Tmp1, Tmp2 };
16110 return DAG.getMergeValues(Ops, dl);
16114 SDValue Chain = Op.getOperand(0);
16115 SDValue Size = Op.getOperand(1);
16116 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16117 EVT VT = Op.getNode()->getValueType(0);
16119 bool Is64Bit = Subtarget->is64Bit();
16120 EVT SPTy = getPointerTy();
16123 MachineRegisterInfo &MRI = MF.getRegInfo();
16126 // The 64 bit implementation of segmented stacks needs to clobber both r10
16127 // r11. This makes it impossible to use it along with nested parameters.
16128 const Function *F = MF.getFunction();
16130 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16132 if (I->hasNestAttr())
16133 report_fatal_error("Cannot use segmented stacks with functions that "
16134 "have nested arguments.");
16137 const TargetRegisterClass *AddrRegClass =
16138 getRegClassFor(getPointerTy());
16139 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16140 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16141 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16142 DAG.getRegister(Vreg, SPTy));
16143 SDValue Ops1[2] = { Value, Chain };
16144 return DAG.getMergeValues(Ops1, dl);
16147 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16149 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16150 Flag = Chain.getValue(1);
16151 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16153 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16155 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16156 DAG.getSubtarget().getRegisterInfo());
16157 unsigned SPReg = RegInfo->getStackRegister();
16158 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16159 Chain = SP.getValue(1);
16162 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16163 DAG.getConstant(-(uint64_t)Align, VT));
16164 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16167 SDValue Ops1[2] = { SP, Chain };
16168 return DAG.getMergeValues(Ops1, dl);
16172 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16173 MachineFunction &MF = DAG.getMachineFunction();
16174 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16176 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16179 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16180 // vastart just stores the address of the VarArgsFrameIndex slot into the
16181 // memory location argument.
16182 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16184 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16185 MachinePointerInfo(SV), false, false, 0);
16189 // gp_offset (0 - 6 * 8)
16190 // fp_offset (48 - 48 + 8 * 16)
16191 // overflow_arg_area (point to parameters coming in memory).
16193 SmallVector<SDValue, 8> MemOps;
16194 SDValue FIN = Op.getOperand(1);
16196 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16197 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16199 FIN, MachinePointerInfo(SV), false, false, 0);
16200 MemOps.push_back(Store);
16203 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16204 FIN, DAG.getIntPtrConstant(4));
16205 Store = DAG.getStore(Op.getOperand(0), DL,
16206 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16208 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16209 MemOps.push_back(Store);
16211 // Store ptr to overflow_arg_area
16212 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16213 FIN, DAG.getIntPtrConstant(4));
16214 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16216 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16217 MachinePointerInfo(SV, 8),
16219 MemOps.push_back(Store);
16221 // Store ptr to reg_save_area.
16222 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16223 FIN, DAG.getIntPtrConstant(8));
16224 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16226 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16227 MachinePointerInfo(SV, 16), false, false, 0);
16228 MemOps.push_back(Store);
16229 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16232 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16233 assert(Subtarget->is64Bit() &&
16234 "LowerVAARG only handles 64-bit va_arg!");
16235 assert((Subtarget->isTargetLinux() ||
16236 Subtarget->isTargetDarwin()) &&
16237 "Unhandled target in LowerVAARG");
16238 assert(Op.getNode()->getNumOperands() == 4);
16239 SDValue Chain = Op.getOperand(0);
16240 SDValue SrcPtr = Op.getOperand(1);
16241 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16242 unsigned Align = Op.getConstantOperandVal(3);
16245 EVT ArgVT = Op.getNode()->getValueType(0);
16246 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16247 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16250 // Decide which area this value should be read from.
16251 // TODO: Implement the AMD64 ABI in its entirety. This simple
16252 // selection mechanism works only for the basic types.
16253 if (ArgVT == MVT::f80) {
16254 llvm_unreachable("va_arg for f80 not yet implemented");
16255 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16256 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16257 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16258 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16260 llvm_unreachable("Unhandled argument type in LowerVAARG");
16263 if (ArgMode == 2) {
16264 // Sanity Check: Make sure using fp_offset makes sense.
16265 assert(!DAG.getTarget().Options.UseSoftFloat &&
16266 !(DAG.getMachineFunction()
16267 .getFunction()->getAttributes()
16268 .hasAttribute(AttributeSet::FunctionIndex,
16269 Attribute::NoImplicitFloat)) &&
16270 Subtarget->hasSSE1());
16273 // Insert VAARG_64 node into the DAG
16274 // VAARG_64 returns two values: Variable Argument Address, Chain
16275 SmallVector<SDValue, 11> InstOps;
16276 InstOps.push_back(Chain);
16277 InstOps.push_back(SrcPtr);
16278 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16279 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16280 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16281 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16282 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16283 VTs, InstOps, MVT::i64,
16284 MachinePointerInfo(SV),
16286 /*Volatile=*/false,
16288 /*WriteMem=*/true);
16289 Chain = VAARG.getValue(1);
16291 // Load the next argument and return it
16292 return DAG.getLoad(ArgVT, dl,
16295 MachinePointerInfo(),
16296 false, false, false, 0);
16299 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16300 SelectionDAG &DAG) {
16301 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16302 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16303 SDValue Chain = Op.getOperand(0);
16304 SDValue DstPtr = Op.getOperand(1);
16305 SDValue SrcPtr = Op.getOperand(2);
16306 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16307 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16310 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16311 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16313 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16316 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16317 // amount is a constant. Takes immediate version of shift as input.
16318 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16319 SDValue SrcOp, uint64_t ShiftAmt,
16320 SelectionDAG &DAG) {
16321 MVT ElementType = VT.getVectorElementType();
16323 // Fold this packed shift into its first operand if ShiftAmt is 0.
16327 // Check for ShiftAmt >= element width
16328 if (ShiftAmt >= ElementType.getSizeInBits()) {
16329 if (Opc == X86ISD::VSRAI)
16330 ShiftAmt = ElementType.getSizeInBits() - 1;
16332 return DAG.getConstant(0, VT);
16335 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16336 && "Unknown target vector shift-by-constant node");
16338 // Fold this packed vector shift into a build vector if SrcOp is a
16339 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16340 if (VT == SrcOp.getSimpleValueType() &&
16341 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16342 SmallVector<SDValue, 8> Elts;
16343 unsigned NumElts = SrcOp->getNumOperands();
16344 ConstantSDNode *ND;
16347 default: llvm_unreachable(nullptr);
16348 case X86ISD::VSHLI:
16349 for (unsigned i=0; i!=NumElts; ++i) {
16350 SDValue CurrentOp = SrcOp->getOperand(i);
16351 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16352 Elts.push_back(CurrentOp);
16355 ND = cast<ConstantSDNode>(CurrentOp);
16356 const APInt &C = ND->getAPIntValue();
16357 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16360 case X86ISD::VSRLI:
16361 for (unsigned i=0; i!=NumElts; ++i) {
16362 SDValue CurrentOp = SrcOp->getOperand(i);
16363 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16364 Elts.push_back(CurrentOp);
16367 ND = cast<ConstantSDNode>(CurrentOp);
16368 const APInt &C = ND->getAPIntValue();
16369 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16372 case X86ISD::VSRAI:
16373 for (unsigned i=0; i!=NumElts; ++i) {
16374 SDValue CurrentOp = SrcOp->getOperand(i);
16375 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16376 Elts.push_back(CurrentOp);
16379 ND = cast<ConstantSDNode>(CurrentOp);
16380 const APInt &C = ND->getAPIntValue();
16381 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16386 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16389 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16392 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16393 // may or may not be a constant. Takes immediate version of shift as input.
16394 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16395 SDValue SrcOp, SDValue ShAmt,
16396 SelectionDAG &DAG) {
16397 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16399 // Catch shift-by-constant.
16400 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16401 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16402 CShAmt->getZExtValue(), DAG);
16404 // Change opcode to non-immediate version
16406 default: llvm_unreachable("Unknown target vector shift node");
16407 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16408 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16409 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16412 // Need to build a vector containing shift amount
16413 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16416 ShOps[1] = DAG.getConstant(0, MVT::i32);
16417 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16418 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16420 // The return type has to be a 128-bit type with the same element
16421 // type as the input type.
16422 MVT EltVT = VT.getVectorElementType();
16423 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16425 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16426 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16429 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16430 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16431 /// necessary casting for \p Mask when lowering masking intrinsics.
16432 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16433 SDValue PreservedSrc,
16434 const X86Subtarget *Subtarget,
16435 SelectionDAG &DAG) {
16436 EVT VT = Op.getValueType();
16437 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16438 MVT::i1, VT.getVectorNumElements());
16439 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16440 Mask.getValueType().getSizeInBits());
16443 assert(MaskVT.isSimple() && "invalid mask type");
16445 if (isAllOnes(Mask))
16448 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16449 // are extracted by EXTRACT_SUBVECTOR.
16450 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16451 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16452 DAG.getIntPtrConstant(0));
16454 switch (Op.getOpcode()) {
16456 case X86ISD::PCMPEQM:
16457 case X86ISD::PCMPGTM:
16459 case X86ISD::CMPMU:
16460 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16462 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16463 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16464 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16467 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16469 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16470 case Intrinsic::x86_fma_vfmadd_ps:
16471 case Intrinsic::x86_fma_vfmadd_pd:
16472 case Intrinsic::x86_fma_vfmadd_ps_256:
16473 case Intrinsic::x86_fma_vfmadd_pd_256:
16474 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16475 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16476 return X86ISD::FMADD;
16477 case Intrinsic::x86_fma_vfmsub_ps:
16478 case Intrinsic::x86_fma_vfmsub_pd:
16479 case Intrinsic::x86_fma_vfmsub_ps_256:
16480 case Intrinsic::x86_fma_vfmsub_pd_256:
16481 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16482 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16483 return X86ISD::FMSUB;
16484 case Intrinsic::x86_fma_vfnmadd_ps:
16485 case Intrinsic::x86_fma_vfnmadd_pd:
16486 case Intrinsic::x86_fma_vfnmadd_ps_256:
16487 case Intrinsic::x86_fma_vfnmadd_pd_256:
16488 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16489 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16490 return X86ISD::FNMADD;
16491 case Intrinsic::x86_fma_vfnmsub_ps:
16492 case Intrinsic::x86_fma_vfnmsub_pd:
16493 case Intrinsic::x86_fma_vfnmsub_ps_256:
16494 case Intrinsic::x86_fma_vfnmsub_pd_256:
16495 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16496 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16497 return X86ISD::FNMSUB;
16498 case Intrinsic::x86_fma_vfmaddsub_ps:
16499 case Intrinsic::x86_fma_vfmaddsub_pd:
16500 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16501 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16502 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16503 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16504 return X86ISD::FMADDSUB;
16505 case Intrinsic::x86_fma_vfmsubadd_ps:
16506 case Intrinsic::x86_fma_vfmsubadd_pd:
16507 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16508 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16509 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16510 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16511 return X86ISD::FMSUBADD;
16515 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16516 SelectionDAG &DAG) {
16518 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16519 EVT VT = Op.getValueType();
16520 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16522 switch(IntrData->Type) {
16523 case INTR_TYPE_1OP:
16524 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16525 case INTR_TYPE_2OP:
16526 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16528 case INTR_TYPE_3OP:
16529 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16530 Op.getOperand(2), Op.getOperand(3));
16531 case INTR_TYPE_1OP_MASK_RM: {
16532 SDValue Src = Op.getOperand(1);
16533 SDValue Src0 = Op.getOperand(2);
16534 SDValue Mask = Op.getOperand(3);
16535 SDValue RoundingMode = Op.getOperand(4);
16536 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16538 Mask, Src0, Subtarget, DAG);
16542 case CMP_MASK_CC: {
16543 // Comparison intrinsics with masks.
16544 // Example of transformation:
16545 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16546 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16548 // (v8i1 (insert_subvector undef,
16549 // (v2i1 (and (PCMPEQM %a, %b),
16550 // (extract_subvector
16551 // (v8i1 (bitcast %mask)), 0))), 0))))
16552 EVT VT = Op.getOperand(1).getValueType();
16553 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16554 VT.getVectorNumElements());
16555 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16556 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16557 Mask.getValueType().getSizeInBits());
16559 if (IntrData->Type == CMP_MASK_CC) {
16560 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16561 Op.getOperand(2), Op.getOperand(3));
16563 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16564 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16567 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16568 DAG.getTargetConstant(0, MaskVT),
16570 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16571 DAG.getUNDEF(BitcastVT), CmpMask,
16572 DAG.getIntPtrConstant(0));
16573 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16575 case COMI: { // Comparison intrinsics
16576 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16577 SDValue LHS = Op.getOperand(1);
16578 SDValue RHS = Op.getOperand(2);
16579 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16580 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16581 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16582 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16583 DAG.getConstant(X86CC, MVT::i8), Cond);
16584 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16587 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16588 Op.getOperand(1), Op.getOperand(2), DAG);
16590 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16591 Op.getOperand(1), Op.getOperand(2), DAG),
16592 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);;
16599 default: return SDValue(); // Don't custom lower most intrinsics.
16601 // Arithmetic intrinsics.
16602 case Intrinsic::x86_sse2_pmulu_dq:
16603 case Intrinsic::x86_avx2_pmulu_dq:
16604 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16605 Op.getOperand(1), Op.getOperand(2));
16607 case Intrinsic::x86_sse41_pmuldq:
16608 case Intrinsic::x86_avx2_pmul_dq:
16609 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16610 Op.getOperand(1), Op.getOperand(2));
16612 case Intrinsic::x86_sse2_pmulhu_w:
16613 case Intrinsic::x86_avx2_pmulhu_w:
16614 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16615 Op.getOperand(1), Op.getOperand(2));
16617 case Intrinsic::x86_sse2_pmulh_w:
16618 case Intrinsic::x86_avx2_pmulh_w:
16619 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16620 Op.getOperand(1), Op.getOperand(2));
16622 // SSE/SSE2/AVX floating point max/min intrinsics.
16623 case Intrinsic::x86_sse_max_ps:
16624 case Intrinsic::x86_sse2_max_pd:
16625 case Intrinsic::x86_avx_max_ps_256:
16626 case Intrinsic::x86_avx_max_pd_256:
16627 case Intrinsic::x86_sse_min_ps:
16628 case Intrinsic::x86_sse2_min_pd:
16629 case Intrinsic::x86_avx_min_ps_256:
16630 case Intrinsic::x86_avx_min_pd_256: {
16633 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16634 case Intrinsic::x86_sse_max_ps:
16635 case Intrinsic::x86_sse2_max_pd:
16636 case Intrinsic::x86_avx_max_ps_256:
16637 case Intrinsic::x86_avx_max_pd_256:
16638 Opcode = X86ISD::FMAX;
16640 case Intrinsic::x86_sse_min_ps:
16641 case Intrinsic::x86_sse2_min_pd:
16642 case Intrinsic::x86_avx_min_ps_256:
16643 case Intrinsic::x86_avx_min_pd_256:
16644 Opcode = X86ISD::FMIN;
16647 return DAG.getNode(Opcode, dl, Op.getValueType(),
16648 Op.getOperand(1), Op.getOperand(2));
16651 // AVX2 variable shift intrinsics
16652 case Intrinsic::x86_avx2_psllv_d:
16653 case Intrinsic::x86_avx2_psllv_q:
16654 case Intrinsic::x86_avx2_psllv_d_256:
16655 case Intrinsic::x86_avx2_psllv_q_256:
16656 case Intrinsic::x86_avx2_psrlv_d:
16657 case Intrinsic::x86_avx2_psrlv_q:
16658 case Intrinsic::x86_avx2_psrlv_d_256:
16659 case Intrinsic::x86_avx2_psrlv_q_256:
16660 case Intrinsic::x86_avx2_psrav_d:
16661 case Intrinsic::x86_avx2_psrav_d_256: {
16664 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16665 case Intrinsic::x86_avx2_psllv_d:
16666 case Intrinsic::x86_avx2_psllv_q:
16667 case Intrinsic::x86_avx2_psllv_d_256:
16668 case Intrinsic::x86_avx2_psllv_q_256:
16671 case Intrinsic::x86_avx2_psrlv_d:
16672 case Intrinsic::x86_avx2_psrlv_q:
16673 case Intrinsic::x86_avx2_psrlv_d_256:
16674 case Intrinsic::x86_avx2_psrlv_q_256:
16677 case Intrinsic::x86_avx2_psrav_d:
16678 case Intrinsic::x86_avx2_psrav_d_256:
16682 return DAG.getNode(Opcode, dl, Op.getValueType(),
16683 Op.getOperand(1), Op.getOperand(2));
16686 case Intrinsic::x86_sse2_packssdw_128:
16687 case Intrinsic::x86_sse2_packsswb_128:
16688 case Intrinsic::x86_avx2_packssdw:
16689 case Intrinsic::x86_avx2_packsswb:
16690 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16691 Op.getOperand(1), Op.getOperand(2));
16693 case Intrinsic::x86_sse2_packuswb_128:
16694 case Intrinsic::x86_sse41_packusdw:
16695 case Intrinsic::x86_avx2_packuswb:
16696 case Intrinsic::x86_avx2_packusdw:
16697 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16698 Op.getOperand(1), Op.getOperand(2));
16700 case Intrinsic::x86_ssse3_pshuf_b_128:
16701 case Intrinsic::x86_avx2_pshuf_b:
16702 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16703 Op.getOperand(1), Op.getOperand(2));
16705 case Intrinsic::x86_sse2_pshuf_d:
16706 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16707 Op.getOperand(1), Op.getOperand(2));
16709 case Intrinsic::x86_sse2_pshufl_w:
16710 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16711 Op.getOperand(1), Op.getOperand(2));
16713 case Intrinsic::x86_sse2_pshufh_w:
16714 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16715 Op.getOperand(1), Op.getOperand(2));
16717 case Intrinsic::x86_ssse3_psign_b_128:
16718 case Intrinsic::x86_ssse3_psign_w_128:
16719 case Intrinsic::x86_ssse3_psign_d_128:
16720 case Intrinsic::x86_avx2_psign_b:
16721 case Intrinsic::x86_avx2_psign_w:
16722 case Intrinsic::x86_avx2_psign_d:
16723 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16724 Op.getOperand(1), Op.getOperand(2));
16726 case Intrinsic::x86_avx2_permd:
16727 case Intrinsic::x86_avx2_permps:
16728 // Operands intentionally swapped. Mask is last operand to intrinsic,
16729 // but second operand for node/instruction.
16730 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16731 Op.getOperand(2), Op.getOperand(1));
16733 case Intrinsic::x86_avx512_mask_valign_q_512:
16734 case Intrinsic::x86_avx512_mask_valign_d_512:
16735 // Vector source operands are swapped.
16736 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16737 Op.getValueType(), Op.getOperand(2),
16740 Op.getOperand(5), Op.getOperand(4),
16743 // ptest and testp intrinsics. The intrinsic these come from are designed to
16744 // return an integer value, not just an instruction so lower it to the ptest
16745 // or testp pattern and a setcc for the result.
16746 case Intrinsic::x86_sse41_ptestz:
16747 case Intrinsic::x86_sse41_ptestc:
16748 case Intrinsic::x86_sse41_ptestnzc:
16749 case Intrinsic::x86_avx_ptestz_256:
16750 case Intrinsic::x86_avx_ptestc_256:
16751 case Intrinsic::x86_avx_ptestnzc_256:
16752 case Intrinsic::x86_avx_vtestz_ps:
16753 case Intrinsic::x86_avx_vtestc_ps:
16754 case Intrinsic::x86_avx_vtestnzc_ps:
16755 case Intrinsic::x86_avx_vtestz_pd:
16756 case Intrinsic::x86_avx_vtestc_pd:
16757 case Intrinsic::x86_avx_vtestnzc_pd:
16758 case Intrinsic::x86_avx_vtestz_ps_256:
16759 case Intrinsic::x86_avx_vtestc_ps_256:
16760 case Intrinsic::x86_avx_vtestnzc_ps_256:
16761 case Intrinsic::x86_avx_vtestz_pd_256:
16762 case Intrinsic::x86_avx_vtestc_pd_256:
16763 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16764 bool IsTestPacked = false;
16767 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16768 case Intrinsic::x86_avx_vtestz_ps:
16769 case Intrinsic::x86_avx_vtestz_pd:
16770 case Intrinsic::x86_avx_vtestz_ps_256:
16771 case Intrinsic::x86_avx_vtestz_pd_256:
16772 IsTestPacked = true; // Fallthrough
16773 case Intrinsic::x86_sse41_ptestz:
16774 case Intrinsic::x86_avx_ptestz_256:
16776 X86CC = X86::COND_E;
16778 case Intrinsic::x86_avx_vtestc_ps:
16779 case Intrinsic::x86_avx_vtestc_pd:
16780 case Intrinsic::x86_avx_vtestc_ps_256:
16781 case Intrinsic::x86_avx_vtestc_pd_256:
16782 IsTestPacked = true; // Fallthrough
16783 case Intrinsic::x86_sse41_ptestc:
16784 case Intrinsic::x86_avx_ptestc_256:
16786 X86CC = X86::COND_B;
16788 case Intrinsic::x86_avx_vtestnzc_ps:
16789 case Intrinsic::x86_avx_vtestnzc_pd:
16790 case Intrinsic::x86_avx_vtestnzc_ps_256:
16791 case Intrinsic::x86_avx_vtestnzc_pd_256:
16792 IsTestPacked = true; // Fallthrough
16793 case Intrinsic::x86_sse41_ptestnzc:
16794 case Intrinsic::x86_avx_ptestnzc_256:
16796 X86CC = X86::COND_A;
16800 SDValue LHS = Op.getOperand(1);
16801 SDValue RHS = Op.getOperand(2);
16802 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16803 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16804 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16805 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16806 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16808 case Intrinsic::x86_avx512_kortestz_w:
16809 case Intrinsic::x86_avx512_kortestc_w: {
16810 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16811 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16812 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16813 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16814 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16815 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16816 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16819 case Intrinsic::x86_sse42_pcmpistria128:
16820 case Intrinsic::x86_sse42_pcmpestria128:
16821 case Intrinsic::x86_sse42_pcmpistric128:
16822 case Intrinsic::x86_sse42_pcmpestric128:
16823 case Intrinsic::x86_sse42_pcmpistrio128:
16824 case Intrinsic::x86_sse42_pcmpestrio128:
16825 case Intrinsic::x86_sse42_pcmpistris128:
16826 case Intrinsic::x86_sse42_pcmpestris128:
16827 case Intrinsic::x86_sse42_pcmpistriz128:
16828 case Intrinsic::x86_sse42_pcmpestriz128: {
16832 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16833 case Intrinsic::x86_sse42_pcmpistria128:
16834 Opcode = X86ISD::PCMPISTRI;
16835 X86CC = X86::COND_A;
16837 case Intrinsic::x86_sse42_pcmpestria128:
16838 Opcode = X86ISD::PCMPESTRI;
16839 X86CC = X86::COND_A;
16841 case Intrinsic::x86_sse42_pcmpistric128:
16842 Opcode = X86ISD::PCMPISTRI;
16843 X86CC = X86::COND_B;
16845 case Intrinsic::x86_sse42_pcmpestric128:
16846 Opcode = X86ISD::PCMPESTRI;
16847 X86CC = X86::COND_B;
16849 case Intrinsic::x86_sse42_pcmpistrio128:
16850 Opcode = X86ISD::PCMPISTRI;
16851 X86CC = X86::COND_O;
16853 case Intrinsic::x86_sse42_pcmpestrio128:
16854 Opcode = X86ISD::PCMPESTRI;
16855 X86CC = X86::COND_O;
16857 case Intrinsic::x86_sse42_pcmpistris128:
16858 Opcode = X86ISD::PCMPISTRI;
16859 X86CC = X86::COND_S;
16861 case Intrinsic::x86_sse42_pcmpestris128:
16862 Opcode = X86ISD::PCMPESTRI;
16863 X86CC = X86::COND_S;
16865 case Intrinsic::x86_sse42_pcmpistriz128:
16866 Opcode = X86ISD::PCMPISTRI;
16867 X86CC = X86::COND_E;
16869 case Intrinsic::x86_sse42_pcmpestriz128:
16870 Opcode = X86ISD::PCMPESTRI;
16871 X86CC = X86::COND_E;
16874 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16875 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16876 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16877 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16878 DAG.getConstant(X86CC, MVT::i8),
16879 SDValue(PCMP.getNode(), 1));
16880 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16883 case Intrinsic::x86_sse42_pcmpistri128:
16884 case Intrinsic::x86_sse42_pcmpestri128: {
16886 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16887 Opcode = X86ISD::PCMPISTRI;
16889 Opcode = X86ISD::PCMPESTRI;
16891 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16892 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16893 return DAG.getNode(Opcode, dl, VTs, NewOps);
16896 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16897 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16898 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16899 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16900 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16901 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16902 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16903 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16904 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16905 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16906 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16907 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16908 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16909 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16910 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16911 dl, Op.getValueType(),
16915 Op.getOperand(4), Op.getOperand(1),
16921 case Intrinsic::x86_fma_vfmadd_ps:
16922 case Intrinsic::x86_fma_vfmadd_pd:
16923 case Intrinsic::x86_fma_vfmsub_ps:
16924 case Intrinsic::x86_fma_vfmsub_pd:
16925 case Intrinsic::x86_fma_vfnmadd_ps:
16926 case Intrinsic::x86_fma_vfnmadd_pd:
16927 case Intrinsic::x86_fma_vfnmsub_ps:
16928 case Intrinsic::x86_fma_vfnmsub_pd:
16929 case Intrinsic::x86_fma_vfmaddsub_ps:
16930 case Intrinsic::x86_fma_vfmaddsub_pd:
16931 case Intrinsic::x86_fma_vfmsubadd_ps:
16932 case Intrinsic::x86_fma_vfmsubadd_pd:
16933 case Intrinsic::x86_fma_vfmadd_ps_256:
16934 case Intrinsic::x86_fma_vfmadd_pd_256:
16935 case Intrinsic::x86_fma_vfmsub_ps_256:
16936 case Intrinsic::x86_fma_vfmsub_pd_256:
16937 case Intrinsic::x86_fma_vfnmadd_ps_256:
16938 case Intrinsic::x86_fma_vfnmadd_pd_256:
16939 case Intrinsic::x86_fma_vfnmsub_ps_256:
16940 case Intrinsic::x86_fma_vfnmsub_pd_256:
16941 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16942 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16943 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16944 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16945 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16946 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16950 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16951 SDValue Src, SDValue Mask, SDValue Base,
16952 SDValue Index, SDValue ScaleOp, SDValue Chain,
16953 const X86Subtarget * Subtarget) {
16955 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16956 assert(C && "Invalid scale type");
16957 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16958 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16959 Index.getSimpleValueType().getVectorNumElements());
16961 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16963 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16965 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16966 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16967 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16968 SDValue Segment = DAG.getRegister(0, MVT::i32);
16969 if (Src.getOpcode() == ISD::UNDEF)
16970 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16971 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16972 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16973 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16974 return DAG.getMergeValues(RetOps, dl);
16977 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16978 SDValue Src, SDValue Mask, SDValue Base,
16979 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16981 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16982 assert(C && "Invalid scale type");
16983 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16984 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16985 SDValue Segment = DAG.getRegister(0, MVT::i32);
16986 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16987 Index.getSimpleValueType().getVectorNumElements());
16989 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16991 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16993 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16994 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16995 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16996 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16997 return SDValue(Res, 1);
17000 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17001 SDValue Mask, SDValue Base, SDValue Index,
17002 SDValue ScaleOp, SDValue Chain) {
17004 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17005 assert(C && "Invalid scale type");
17006 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17007 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17008 SDValue Segment = DAG.getRegister(0, MVT::i32);
17010 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17012 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17014 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17016 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17017 //SDVTList VTs = DAG.getVTList(MVT::Other);
17018 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17019 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17020 return SDValue(Res, 0);
17023 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17024 // read performance monitor counters (x86_rdpmc).
17025 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17026 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17027 SmallVectorImpl<SDValue> &Results) {
17028 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17029 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17032 // The ECX register is used to select the index of the performance counter
17034 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17036 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17038 // Reads the content of a 64-bit performance counter and returns it in the
17039 // registers EDX:EAX.
17040 if (Subtarget->is64Bit()) {
17041 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17042 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17045 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17046 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17049 Chain = HI.getValue(1);
17051 if (Subtarget->is64Bit()) {
17052 // The EAX register is loaded with the low-order 32 bits. The EDX register
17053 // is loaded with the supported high-order bits of the counter.
17054 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17055 DAG.getConstant(32, MVT::i8));
17056 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17057 Results.push_back(Chain);
17061 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17062 SDValue Ops[] = { LO, HI };
17063 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17064 Results.push_back(Pair);
17065 Results.push_back(Chain);
17068 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17069 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17070 // also used to custom lower READCYCLECOUNTER nodes.
17071 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17072 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17073 SmallVectorImpl<SDValue> &Results) {
17074 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17075 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17078 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17079 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17080 // and the EAX register is loaded with the low-order 32 bits.
17081 if (Subtarget->is64Bit()) {
17082 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17083 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17086 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17087 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17090 SDValue Chain = HI.getValue(1);
17092 if (Opcode == X86ISD::RDTSCP_DAG) {
17093 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17095 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17096 // the ECX register. Add 'ecx' explicitly to the chain.
17097 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17099 // Explicitly store the content of ECX at the location passed in input
17100 // to the 'rdtscp' intrinsic.
17101 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17102 MachinePointerInfo(), false, false, 0);
17105 if (Subtarget->is64Bit()) {
17106 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17107 // the EAX register is loaded with the low-order 32 bits.
17108 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17109 DAG.getConstant(32, MVT::i8));
17110 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17111 Results.push_back(Chain);
17115 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17116 SDValue Ops[] = { LO, HI };
17117 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17118 Results.push_back(Pair);
17119 Results.push_back(Chain);
17122 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17123 SelectionDAG &DAG) {
17124 SmallVector<SDValue, 2> Results;
17126 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17128 return DAG.getMergeValues(Results, DL);
17132 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17133 SelectionDAG &DAG) {
17134 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17136 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17141 switch(IntrData->Type) {
17143 llvm_unreachable("Unknown Intrinsic Type");
17147 // Emit the node with the right value type.
17148 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17149 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17151 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17152 // Otherwise return the value from Rand, which is always 0, casted to i32.
17153 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17154 DAG.getConstant(1, Op->getValueType(1)),
17155 DAG.getConstant(X86::COND_B, MVT::i32),
17156 SDValue(Result.getNode(), 1) };
17157 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17158 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17161 // Return { result, isValid, chain }.
17162 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17163 SDValue(Result.getNode(), 2));
17166 //gather(v1, mask, index, base, scale);
17167 SDValue Chain = Op.getOperand(0);
17168 SDValue Src = Op.getOperand(2);
17169 SDValue Base = Op.getOperand(3);
17170 SDValue Index = Op.getOperand(4);
17171 SDValue Mask = Op.getOperand(5);
17172 SDValue Scale = Op.getOperand(6);
17173 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17177 //scatter(base, mask, index, v1, scale);
17178 SDValue Chain = Op.getOperand(0);
17179 SDValue Base = Op.getOperand(2);
17180 SDValue Mask = Op.getOperand(3);
17181 SDValue Index = Op.getOperand(4);
17182 SDValue Src = Op.getOperand(5);
17183 SDValue Scale = Op.getOperand(6);
17184 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17187 SDValue Hint = Op.getOperand(6);
17189 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17190 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17191 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17192 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17193 SDValue Chain = Op.getOperand(0);
17194 SDValue Mask = Op.getOperand(2);
17195 SDValue Index = Op.getOperand(3);
17196 SDValue Base = Op.getOperand(4);
17197 SDValue Scale = Op.getOperand(5);
17198 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17200 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17202 SmallVector<SDValue, 2> Results;
17203 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17204 return DAG.getMergeValues(Results, dl);
17206 // Read Performance Monitoring Counters.
17208 SmallVector<SDValue, 2> Results;
17209 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17210 return DAG.getMergeValues(Results, dl);
17212 // XTEST intrinsics.
17214 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17215 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17216 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17217 DAG.getConstant(X86::COND_NE, MVT::i8),
17219 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17220 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17221 Ret, SDValue(InTrans.getNode(), 1));
17225 SmallVector<SDValue, 2> Results;
17226 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17227 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17228 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17229 DAG.getConstant(-1, MVT::i8));
17230 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17231 Op.getOperand(4), GenCF.getValue(1));
17232 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17233 Op.getOperand(5), MachinePointerInfo(),
17235 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17236 DAG.getConstant(X86::COND_B, MVT::i8),
17238 Results.push_back(SetCC);
17239 Results.push_back(Store);
17240 return DAG.getMergeValues(Results, dl);
17245 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17246 SelectionDAG &DAG) const {
17247 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17248 MFI->setReturnAddressIsTaken(true);
17250 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17253 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17255 EVT PtrVT = getPointerTy();
17258 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17259 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17260 DAG.getSubtarget().getRegisterInfo());
17261 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17262 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17263 DAG.getNode(ISD::ADD, dl, PtrVT,
17264 FrameAddr, Offset),
17265 MachinePointerInfo(), false, false, false, 0);
17268 // Just load the return address.
17269 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17270 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17271 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17274 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17275 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17276 MFI->setFrameAddressIsTaken(true);
17278 EVT VT = Op.getValueType();
17279 SDLoc dl(Op); // FIXME probably not meaningful
17280 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17281 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17282 DAG.getSubtarget().getRegisterInfo());
17283 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17284 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17285 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17286 "Invalid Frame Register!");
17287 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17289 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17290 MachinePointerInfo(),
17291 false, false, false, 0);
17295 // FIXME? Maybe this could be a TableGen attribute on some registers and
17296 // this table could be generated automatically from RegInfo.
17297 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17299 unsigned Reg = StringSwitch<unsigned>(RegName)
17300 .Case("esp", X86::ESP)
17301 .Case("rsp", X86::RSP)
17305 report_fatal_error("Invalid register name global variable");
17308 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17309 SelectionDAG &DAG) const {
17310 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17311 DAG.getSubtarget().getRegisterInfo());
17312 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17315 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17316 SDValue Chain = Op.getOperand(0);
17317 SDValue Offset = Op.getOperand(1);
17318 SDValue Handler = Op.getOperand(2);
17321 EVT PtrVT = getPointerTy();
17322 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17323 DAG.getSubtarget().getRegisterInfo());
17324 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17325 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17326 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17327 "Invalid Frame Register!");
17328 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17329 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17331 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17332 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17333 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17334 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17336 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17338 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17339 DAG.getRegister(StoreAddrReg, PtrVT));
17342 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17343 SelectionDAG &DAG) const {
17345 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17346 DAG.getVTList(MVT::i32, MVT::Other),
17347 Op.getOperand(0), Op.getOperand(1));
17350 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17351 SelectionDAG &DAG) const {
17353 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17354 Op.getOperand(0), Op.getOperand(1));
17357 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17358 return Op.getOperand(0);
17361 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17362 SelectionDAG &DAG) const {
17363 SDValue Root = Op.getOperand(0);
17364 SDValue Trmp = Op.getOperand(1); // trampoline
17365 SDValue FPtr = Op.getOperand(2); // nested function
17366 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17369 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17370 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17372 if (Subtarget->is64Bit()) {
17373 SDValue OutChains[6];
17375 // Large code-model.
17376 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17377 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17379 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17380 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17382 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17384 // Load the pointer to the nested function into R11.
17385 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17386 SDValue Addr = Trmp;
17387 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17388 Addr, MachinePointerInfo(TrmpAddr),
17391 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17392 DAG.getConstant(2, MVT::i64));
17393 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17394 MachinePointerInfo(TrmpAddr, 2),
17397 // Load the 'nest' parameter value into R10.
17398 // R10 is specified in X86CallingConv.td
17399 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17400 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17401 DAG.getConstant(10, MVT::i64));
17402 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17403 Addr, MachinePointerInfo(TrmpAddr, 10),
17406 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17407 DAG.getConstant(12, MVT::i64));
17408 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17409 MachinePointerInfo(TrmpAddr, 12),
17412 // Jump to the nested function.
17413 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17414 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17415 DAG.getConstant(20, MVT::i64));
17416 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17417 Addr, MachinePointerInfo(TrmpAddr, 20),
17420 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17421 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17422 DAG.getConstant(22, MVT::i64));
17423 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17424 MachinePointerInfo(TrmpAddr, 22),
17427 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17429 const Function *Func =
17430 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17431 CallingConv::ID CC = Func->getCallingConv();
17436 llvm_unreachable("Unsupported calling convention");
17437 case CallingConv::C:
17438 case CallingConv::X86_StdCall: {
17439 // Pass 'nest' parameter in ECX.
17440 // Must be kept in sync with X86CallingConv.td
17441 NestReg = X86::ECX;
17443 // Check that ECX wasn't needed by an 'inreg' parameter.
17444 FunctionType *FTy = Func->getFunctionType();
17445 const AttributeSet &Attrs = Func->getAttributes();
17447 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17448 unsigned InRegCount = 0;
17451 for (FunctionType::param_iterator I = FTy->param_begin(),
17452 E = FTy->param_end(); I != E; ++I, ++Idx)
17453 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17454 // FIXME: should only count parameters that are lowered to integers.
17455 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17457 if (InRegCount > 2) {
17458 report_fatal_error("Nest register in use - reduce number of inreg"
17464 case CallingConv::X86_FastCall:
17465 case CallingConv::X86_ThisCall:
17466 case CallingConv::Fast:
17467 // Pass 'nest' parameter in EAX.
17468 // Must be kept in sync with X86CallingConv.td
17469 NestReg = X86::EAX;
17473 SDValue OutChains[4];
17474 SDValue Addr, Disp;
17476 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17477 DAG.getConstant(10, MVT::i32));
17478 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17480 // This is storing the opcode for MOV32ri.
17481 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17482 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17483 OutChains[0] = DAG.getStore(Root, dl,
17484 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17485 Trmp, MachinePointerInfo(TrmpAddr),
17488 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17489 DAG.getConstant(1, MVT::i32));
17490 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17491 MachinePointerInfo(TrmpAddr, 1),
17494 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17495 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17496 DAG.getConstant(5, MVT::i32));
17497 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17498 MachinePointerInfo(TrmpAddr, 5),
17501 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17502 DAG.getConstant(6, MVT::i32));
17503 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17504 MachinePointerInfo(TrmpAddr, 6),
17507 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17511 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17512 SelectionDAG &DAG) const {
17514 The rounding mode is in bits 11:10 of FPSR, and has the following
17516 00 Round to nearest
17521 FLT_ROUNDS, on the other hand, expects the following:
17528 To perform the conversion, we do:
17529 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17532 MachineFunction &MF = DAG.getMachineFunction();
17533 const TargetMachine &TM = MF.getTarget();
17534 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17535 unsigned StackAlignment = TFI.getStackAlignment();
17536 MVT VT = Op.getSimpleValueType();
17539 // Save FP Control Word to stack slot
17540 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17541 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17543 MachineMemOperand *MMO =
17544 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17545 MachineMemOperand::MOStore, 2, 2);
17547 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17548 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17549 DAG.getVTList(MVT::Other),
17550 Ops, MVT::i16, MMO);
17552 // Load FP Control Word from stack slot
17553 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17554 MachinePointerInfo(), false, false, false, 0);
17556 // Transform as necessary
17558 DAG.getNode(ISD::SRL, DL, MVT::i16,
17559 DAG.getNode(ISD::AND, DL, MVT::i16,
17560 CWD, DAG.getConstant(0x800, MVT::i16)),
17561 DAG.getConstant(11, MVT::i8));
17563 DAG.getNode(ISD::SRL, DL, MVT::i16,
17564 DAG.getNode(ISD::AND, DL, MVT::i16,
17565 CWD, DAG.getConstant(0x400, MVT::i16)),
17566 DAG.getConstant(9, MVT::i8));
17569 DAG.getNode(ISD::AND, DL, MVT::i16,
17570 DAG.getNode(ISD::ADD, DL, MVT::i16,
17571 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17572 DAG.getConstant(1, MVT::i16)),
17573 DAG.getConstant(3, MVT::i16));
17575 return DAG.getNode((VT.getSizeInBits() < 16 ?
17576 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17579 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17580 MVT VT = Op.getSimpleValueType();
17582 unsigned NumBits = VT.getSizeInBits();
17585 Op = Op.getOperand(0);
17586 if (VT == MVT::i8) {
17587 // Zero extend to i32 since there is not an i8 bsr.
17589 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17592 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17593 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17594 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17596 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17599 DAG.getConstant(NumBits+NumBits-1, OpVT),
17600 DAG.getConstant(X86::COND_E, MVT::i8),
17603 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17605 // Finally xor with NumBits-1.
17606 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17609 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17613 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17614 MVT VT = Op.getSimpleValueType();
17616 unsigned NumBits = VT.getSizeInBits();
17619 Op = Op.getOperand(0);
17620 if (VT == MVT::i8) {
17621 // Zero extend to i32 since there is not an i8 bsr.
17623 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17626 // Issue a bsr (scan bits in reverse).
17627 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17628 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17630 // And xor with NumBits-1.
17631 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17634 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17638 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17639 MVT VT = Op.getSimpleValueType();
17640 unsigned NumBits = VT.getSizeInBits();
17642 Op = Op.getOperand(0);
17644 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17645 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17646 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17648 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17651 DAG.getConstant(NumBits, VT),
17652 DAG.getConstant(X86::COND_E, MVT::i8),
17655 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17658 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17659 // ones, and then concatenate the result back.
17660 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17661 MVT VT = Op.getSimpleValueType();
17663 assert(VT.is256BitVector() && VT.isInteger() &&
17664 "Unsupported value type for operation");
17666 unsigned NumElems = VT.getVectorNumElements();
17669 // Extract the LHS vectors
17670 SDValue LHS = Op.getOperand(0);
17671 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17672 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17674 // Extract the RHS vectors
17675 SDValue RHS = Op.getOperand(1);
17676 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17677 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17679 MVT EltVT = VT.getVectorElementType();
17680 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17682 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17683 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17684 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17687 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17688 assert(Op.getSimpleValueType().is256BitVector() &&
17689 Op.getSimpleValueType().isInteger() &&
17690 "Only handle AVX 256-bit vector integer operation");
17691 return Lower256IntArith(Op, DAG);
17694 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17695 assert(Op.getSimpleValueType().is256BitVector() &&
17696 Op.getSimpleValueType().isInteger() &&
17697 "Only handle AVX 256-bit vector integer operation");
17698 return Lower256IntArith(Op, DAG);
17701 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17702 SelectionDAG &DAG) {
17704 MVT VT = Op.getSimpleValueType();
17706 // Decompose 256-bit ops into smaller 128-bit ops.
17707 if (VT.is256BitVector() && !Subtarget->hasInt256())
17708 return Lower256IntArith(Op, DAG);
17710 SDValue A = Op.getOperand(0);
17711 SDValue B = Op.getOperand(1);
17713 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17714 if (VT == MVT::v4i32) {
17715 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17716 "Should not custom lower when pmuldq is available!");
17718 // Extract the odd parts.
17719 static const int UnpackMask[] = { 1, -1, 3, -1 };
17720 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17721 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17723 // Multiply the even parts.
17724 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17725 // Now multiply odd parts.
17726 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17728 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17729 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17731 // Merge the two vectors back together with a shuffle. This expands into 2
17733 static const int ShufMask[] = { 0, 4, 2, 6 };
17734 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17737 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17738 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17740 // Ahi = psrlqi(a, 32);
17741 // Bhi = psrlqi(b, 32);
17743 // AloBlo = pmuludq(a, b);
17744 // AloBhi = pmuludq(a, Bhi);
17745 // AhiBlo = pmuludq(Ahi, b);
17747 // AloBhi = psllqi(AloBhi, 32);
17748 // AhiBlo = psllqi(AhiBlo, 32);
17749 // return AloBlo + AloBhi + AhiBlo;
17751 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17752 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17754 // Bit cast to 32-bit vectors for MULUDQ
17755 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17756 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17757 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17758 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17759 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17760 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17762 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17763 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17764 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17766 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17767 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17769 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17770 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17773 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17774 assert(Subtarget->isTargetWin64() && "Unexpected target");
17775 EVT VT = Op.getValueType();
17776 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17777 "Unexpected return type for lowering");
17781 switch (Op->getOpcode()) {
17782 default: llvm_unreachable("Unexpected request for libcall!");
17783 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17784 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17785 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17786 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17787 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17788 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17792 SDValue InChain = DAG.getEntryNode();
17794 TargetLowering::ArgListTy Args;
17795 TargetLowering::ArgListEntry Entry;
17796 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17797 EVT ArgVT = Op->getOperand(i).getValueType();
17798 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17799 "Unexpected argument type for lowering");
17800 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17801 Entry.Node = StackPtr;
17802 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17804 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17805 Entry.Ty = PointerType::get(ArgTy,0);
17806 Entry.isSExt = false;
17807 Entry.isZExt = false;
17808 Args.push_back(Entry);
17811 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17814 TargetLowering::CallLoweringInfo CLI(DAG);
17815 CLI.setDebugLoc(dl).setChain(InChain)
17816 .setCallee(getLibcallCallingConv(LC),
17817 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17818 Callee, std::move(Args), 0)
17819 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17821 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17822 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17825 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17826 SelectionDAG &DAG) {
17827 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17828 EVT VT = Op0.getValueType();
17831 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17832 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17834 // PMULxD operations multiply each even value (starting at 0) of LHS with
17835 // the related value of RHS and produce a widen result.
17836 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17837 // => <2 x i64> <ae|cg>
17839 // In other word, to have all the results, we need to perform two PMULxD:
17840 // 1. one with the even values.
17841 // 2. one with the odd values.
17842 // To achieve #2, with need to place the odd values at an even position.
17844 // Place the odd value at an even position (basically, shift all values 1
17845 // step to the left):
17846 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17847 // <a|b|c|d> => <b|undef|d|undef>
17848 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17849 // <e|f|g|h> => <f|undef|h|undef>
17850 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17852 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17854 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17855 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17857 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17858 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17859 // => <2 x i64> <ae|cg>
17860 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17861 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17862 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17863 // => <2 x i64> <bf|dh>
17864 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17865 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17867 // Shuffle it back into the right order.
17868 SDValue Highs, Lows;
17869 if (VT == MVT::v8i32) {
17870 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17871 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17872 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17873 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17875 const int HighMask[] = {1, 5, 3, 7};
17876 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17877 const int LowMask[] = {0, 4, 2, 6};
17878 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17881 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17882 // unsigned multiply.
17883 if (IsSigned && !Subtarget->hasSSE41()) {
17885 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17886 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17887 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17888 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17889 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17891 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17892 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17895 // The first result of MUL_LOHI is actually the low value, followed by the
17897 SDValue Ops[] = {Lows, Highs};
17898 return DAG.getMergeValues(Ops, dl);
17901 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17902 const X86Subtarget *Subtarget) {
17903 MVT VT = Op.getSimpleValueType();
17905 SDValue R = Op.getOperand(0);
17906 SDValue Amt = Op.getOperand(1);
17908 // Optimize shl/srl/sra with constant shift amount.
17909 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17910 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17911 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17913 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17914 (Subtarget->hasInt256() &&
17915 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17916 (Subtarget->hasAVX512() &&
17917 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17918 if (Op.getOpcode() == ISD::SHL)
17919 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17921 if (Op.getOpcode() == ISD::SRL)
17922 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17924 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17925 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17929 if (VT == MVT::v16i8) {
17930 if (Op.getOpcode() == ISD::SHL) {
17931 // Make a large shift.
17932 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17933 MVT::v8i16, R, ShiftAmt,
17935 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17936 // Zero out the rightmost bits.
17937 SmallVector<SDValue, 16> V(16,
17938 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17940 return DAG.getNode(ISD::AND, dl, VT, SHL,
17941 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17943 if (Op.getOpcode() == ISD::SRL) {
17944 // Make a large shift.
17945 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17946 MVT::v8i16, R, ShiftAmt,
17948 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17949 // Zero out the leftmost bits.
17950 SmallVector<SDValue, 16> V(16,
17951 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17953 return DAG.getNode(ISD::AND, dl, VT, SRL,
17954 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17956 if (Op.getOpcode() == ISD::SRA) {
17957 if (ShiftAmt == 7) {
17958 // R s>> 7 === R s< 0
17959 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17960 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17963 // R s>> a === ((R u>> a) ^ m) - m
17964 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17965 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17967 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17968 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17969 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17972 llvm_unreachable("Unknown shift opcode.");
17975 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17976 if (Op.getOpcode() == ISD::SHL) {
17977 // Make a large shift.
17978 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17979 MVT::v16i16, R, ShiftAmt,
17981 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17982 // Zero out the rightmost bits.
17983 SmallVector<SDValue, 32> V(32,
17984 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17986 return DAG.getNode(ISD::AND, dl, VT, SHL,
17987 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17989 if (Op.getOpcode() == ISD::SRL) {
17990 // Make a large shift.
17991 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17992 MVT::v16i16, R, ShiftAmt,
17994 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17995 // Zero out the leftmost bits.
17996 SmallVector<SDValue, 32> V(32,
17997 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17999 return DAG.getNode(ISD::AND, dl, VT, SRL,
18000 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18002 if (Op.getOpcode() == ISD::SRA) {
18003 if (ShiftAmt == 7) {
18004 // R s>> 7 === R s< 0
18005 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18006 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18009 // R s>> a === ((R u>> a) ^ m) - m
18010 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18011 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18013 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18014 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18015 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18018 llvm_unreachable("Unknown shift opcode.");
18023 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18024 if (!Subtarget->is64Bit() &&
18025 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18026 Amt.getOpcode() == ISD::BITCAST &&
18027 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18028 Amt = Amt.getOperand(0);
18029 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18030 VT.getVectorNumElements();
18031 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18032 uint64_t ShiftAmt = 0;
18033 for (unsigned i = 0; i != Ratio; ++i) {
18034 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18038 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18040 // Check remaining shift amounts.
18041 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18042 uint64_t ShAmt = 0;
18043 for (unsigned j = 0; j != Ratio; ++j) {
18044 ConstantSDNode *C =
18045 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18049 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18051 if (ShAmt != ShiftAmt)
18054 switch (Op.getOpcode()) {
18056 llvm_unreachable("Unknown shift opcode!");
18058 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18061 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18064 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18072 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18073 const X86Subtarget* Subtarget) {
18074 MVT VT = Op.getSimpleValueType();
18076 SDValue R = Op.getOperand(0);
18077 SDValue Amt = Op.getOperand(1);
18079 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18080 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18081 (Subtarget->hasInt256() &&
18082 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18083 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18084 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18086 EVT EltVT = VT.getVectorElementType();
18088 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18089 unsigned NumElts = VT.getVectorNumElements();
18091 for (i = 0; i != NumElts; ++i) {
18092 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
18096 for (j = i; j != NumElts; ++j) {
18097 SDValue Arg = Amt.getOperand(j);
18098 if (Arg.getOpcode() == ISD::UNDEF) continue;
18099 if (Arg != Amt.getOperand(i))
18102 if (i != NumElts && j == NumElts)
18103 BaseShAmt = Amt.getOperand(i);
18105 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18106 Amt = Amt.getOperand(0);
18107 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18108 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18109 SDValue InVec = Amt.getOperand(0);
18110 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18111 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18113 for (; i != NumElts; ++i) {
18114 SDValue Arg = InVec.getOperand(i);
18115 if (Arg.getOpcode() == ISD::UNDEF) continue;
18119 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18120 if (ConstantSDNode *C =
18121 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18122 unsigned SplatIdx =
18123 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18124 if (C->getZExtValue() == SplatIdx)
18125 BaseShAmt = InVec.getOperand(1);
18128 if (!BaseShAmt.getNode())
18129 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18130 DAG.getIntPtrConstant(0));
18134 if (BaseShAmt.getNode()) {
18135 if (EltVT.bitsGT(MVT::i32))
18136 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18137 else if (EltVT.bitsLT(MVT::i32))
18138 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18140 switch (Op.getOpcode()) {
18142 llvm_unreachable("Unknown shift opcode!");
18144 switch (VT.SimpleTy) {
18145 default: return SDValue();
18154 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18157 switch (VT.SimpleTy) {
18158 default: return SDValue();
18165 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18168 switch (VT.SimpleTy) {
18169 default: return SDValue();
18178 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18184 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18185 if (!Subtarget->is64Bit() &&
18186 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18187 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18188 Amt.getOpcode() == ISD::BITCAST &&
18189 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18190 Amt = Amt.getOperand(0);
18191 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18192 VT.getVectorNumElements();
18193 std::vector<SDValue> Vals(Ratio);
18194 for (unsigned i = 0; i != Ratio; ++i)
18195 Vals[i] = Amt.getOperand(i);
18196 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18197 for (unsigned j = 0; j != Ratio; ++j)
18198 if (Vals[j] != Amt.getOperand(i + j))
18201 switch (Op.getOpcode()) {
18203 llvm_unreachable("Unknown shift opcode!");
18205 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18207 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18209 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18216 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18217 SelectionDAG &DAG) {
18218 MVT VT = Op.getSimpleValueType();
18220 SDValue R = Op.getOperand(0);
18221 SDValue Amt = Op.getOperand(1);
18224 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18225 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18227 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18231 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18235 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18237 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18238 if (Subtarget->hasInt256()) {
18239 if (Op.getOpcode() == ISD::SRL &&
18240 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18241 VT == MVT::v4i64 || VT == MVT::v8i32))
18243 if (Op.getOpcode() == ISD::SHL &&
18244 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18245 VT == MVT::v4i64 || VT == MVT::v8i32))
18247 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18251 // If possible, lower this packed shift into a vector multiply instead of
18252 // expanding it into a sequence of scalar shifts.
18253 // Do this only if the vector shift count is a constant build_vector.
18254 if (Op.getOpcode() == ISD::SHL &&
18255 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18256 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18257 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18258 SmallVector<SDValue, 8> Elts;
18259 EVT SVT = VT.getScalarType();
18260 unsigned SVTBits = SVT.getSizeInBits();
18261 const APInt &One = APInt(SVTBits, 1);
18262 unsigned NumElems = VT.getVectorNumElements();
18264 for (unsigned i=0; i !=NumElems; ++i) {
18265 SDValue Op = Amt->getOperand(i);
18266 if (Op->getOpcode() == ISD::UNDEF) {
18267 Elts.push_back(Op);
18271 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18272 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18273 uint64_t ShAmt = C.getZExtValue();
18274 if (ShAmt >= SVTBits) {
18275 Elts.push_back(DAG.getUNDEF(SVT));
18278 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18280 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18281 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18284 // Lower SHL with variable shift amount.
18285 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18286 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18288 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18289 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18290 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18291 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18294 // If possible, lower this shift as a sequence of two shifts by
18295 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18297 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18299 // Could be rewritten as:
18300 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18302 // The advantage is that the two shifts from the example would be
18303 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18304 // the vector shift into four scalar shifts plus four pairs of vector
18306 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18307 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18308 unsigned TargetOpcode = X86ISD::MOVSS;
18309 bool CanBeSimplified;
18310 // The splat value for the first packed shift (the 'X' from the example).
18311 SDValue Amt1 = Amt->getOperand(0);
18312 // The splat value for the second packed shift (the 'Y' from the example).
18313 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18314 Amt->getOperand(2);
18316 // See if it is possible to replace this node with a sequence of
18317 // two shifts followed by a MOVSS/MOVSD
18318 if (VT == MVT::v4i32) {
18319 // Check if it is legal to use a MOVSS.
18320 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18321 Amt2 == Amt->getOperand(3);
18322 if (!CanBeSimplified) {
18323 // Otherwise, check if we can still simplify this node using a MOVSD.
18324 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18325 Amt->getOperand(2) == Amt->getOperand(3);
18326 TargetOpcode = X86ISD::MOVSD;
18327 Amt2 = Amt->getOperand(2);
18330 // Do similar checks for the case where the machine value type
18332 CanBeSimplified = Amt1 == Amt->getOperand(1);
18333 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18334 CanBeSimplified = Amt2 == Amt->getOperand(i);
18336 if (!CanBeSimplified) {
18337 TargetOpcode = X86ISD::MOVSD;
18338 CanBeSimplified = true;
18339 Amt2 = Amt->getOperand(4);
18340 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18341 CanBeSimplified = Amt1 == Amt->getOperand(i);
18342 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18343 CanBeSimplified = Amt2 == Amt->getOperand(j);
18347 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18348 isa<ConstantSDNode>(Amt2)) {
18349 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18350 EVT CastVT = MVT::v4i32;
18352 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18353 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18355 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18356 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18357 if (TargetOpcode == X86ISD::MOVSD)
18358 CastVT = MVT::v2i64;
18359 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18360 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18361 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18363 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18367 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18368 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18371 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18372 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18374 // Turn 'a' into a mask suitable for VSELECT
18375 SDValue VSelM = DAG.getConstant(0x80, VT);
18376 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18377 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18379 SDValue CM1 = DAG.getConstant(0x0f, VT);
18380 SDValue CM2 = DAG.getConstant(0x3f, VT);
18382 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18383 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18384 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18385 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18386 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18389 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18390 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18391 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18393 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18394 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18395 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18396 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18397 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18400 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18401 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18402 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18404 // return VSELECT(r, r+r, a);
18405 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18406 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18410 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18411 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18412 // solution better.
18413 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18414 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18416 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18417 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18418 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18419 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18420 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18423 // Decompose 256-bit shifts into smaller 128-bit shifts.
18424 if (VT.is256BitVector()) {
18425 unsigned NumElems = VT.getVectorNumElements();
18426 MVT EltVT = VT.getVectorElementType();
18427 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18429 // Extract the two vectors
18430 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18431 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18433 // Recreate the shift amount vectors
18434 SDValue Amt1, Amt2;
18435 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18436 // Constant shift amount
18437 SmallVector<SDValue, 4> Amt1Csts;
18438 SmallVector<SDValue, 4> Amt2Csts;
18439 for (unsigned i = 0; i != NumElems/2; ++i)
18440 Amt1Csts.push_back(Amt->getOperand(i));
18441 for (unsigned i = NumElems/2; i != NumElems; ++i)
18442 Amt2Csts.push_back(Amt->getOperand(i));
18444 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18445 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18447 // Variable shift amount
18448 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18449 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18452 // Issue new vector shifts for the smaller types
18453 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18454 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18456 // Concatenate the result back
18457 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18463 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18464 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18465 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18466 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18467 // has only one use.
18468 SDNode *N = Op.getNode();
18469 SDValue LHS = N->getOperand(0);
18470 SDValue RHS = N->getOperand(1);
18471 unsigned BaseOp = 0;
18474 switch (Op.getOpcode()) {
18475 default: llvm_unreachable("Unknown ovf instruction!");
18477 // A subtract of one will be selected as a INC. Note that INC doesn't
18478 // set CF, so we can't do this for UADDO.
18479 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18481 BaseOp = X86ISD::INC;
18482 Cond = X86::COND_O;
18485 BaseOp = X86ISD::ADD;
18486 Cond = X86::COND_O;
18489 BaseOp = X86ISD::ADD;
18490 Cond = X86::COND_B;
18493 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18494 // set CF, so we can't do this for USUBO.
18495 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18497 BaseOp = X86ISD::DEC;
18498 Cond = X86::COND_O;
18501 BaseOp = X86ISD::SUB;
18502 Cond = X86::COND_O;
18505 BaseOp = X86ISD::SUB;
18506 Cond = X86::COND_B;
18509 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18510 Cond = X86::COND_O;
18512 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18513 if (N->getValueType(0) == MVT::i8) {
18514 BaseOp = X86ISD::UMUL8;
18515 Cond = X86::COND_O;
18518 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18520 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18523 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18524 DAG.getConstant(X86::COND_O, MVT::i32),
18525 SDValue(Sum.getNode(), 2));
18527 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18531 // Also sets EFLAGS.
18532 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18533 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18536 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18537 DAG.getConstant(Cond, MVT::i32),
18538 SDValue(Sum.getNode(), 1));
18540 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18543 // Sign extension of the low part of vector elements. This may be used either
18544 // when sign extend instructions are not available or if the vector element
18545 // sizes already match the sign-extended size. If the vector elements are in
18546 // their pre-extended size and sign extend instructions are available, that will
18547 // be handled by LowerSIGN_EXTEND.
18548 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18549 SelectionDAG &DAG) const {
18551 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18552 MVT VT = Op.getSimpleValueType();
18554 if (!Subtarget->hasSSE2() || !VT.isVector())
18557 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18558 ExtraVT.getScalarType().getSizeInBits();
18560 switch (VT.SimpleTy) {
18561 default: return SDValue();
18564 if (!Subtarget->hasFp256())
18566 if (!Subtarget->hasInt256()) {
18567 // needs to be split
18568 unsigned NumElems = VT.getVectorNumElements();
18570 // Extract the LHS vectors
18571 SDValue LHS = Op.getOperand(0);
18572 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18573 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18575 MVT EltVT = VT.getVectorElementType();
18576 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18578 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18579 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18580 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18582 SDValue Extra = DAG.getValueType(ExtraVT);
18584 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18585 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18587 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18592 SDValue Op0 = Op.getOperand(0);
18594 // This is a sign extension of some low part of vector elements without
18595 // changing the size of the vector elements themselves:
18596 // Shift-Left + Shift-Right-Algebraic.
18597 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18599 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18605 /// Returns true if the operand type is exactly twice the native width, and
18606 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18607 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18608 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18609 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18610 const X86Subtarget &Subtarget =
18611 getTargetMachine().getSubtarget<X86Subtarget>();
18612 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18615 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18616 else if (OpWidth == 128)
18617 return Subtarget.hasCmpxchg16b();
18622 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18623 return needsCmpXchgNb(SI->getValueOperand()->getType());
18626 // Note: this turns large loads into lock cmpxchg8b/16b.
18627 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18628 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18629 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18630 return needsCmpXchgNb(PTy->getElementType());
18633 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18634 const X86Subtarget &Subtarget =
18635 getTargetMachine().getSubtarget<X86Subtarget>();
18636 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18637 const Type *MemType = AI->getType();
18639 // If the operand is too big, we must see if cmpxchg8/16b is available
18640 // and default to library calls otherwise.
18641 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18642 return needsCmpXchgNb(MemType);
18644 AtomicRMWInst::BinOp Op = AI->getOperation();
18647 llvm_unreachable("Unknown atomic operation");
18648 case AtomicRMWInst::Xchg:
18649 case AtomicRMWInst::Add:
18650 case AtomicRMWInst::Sub:
18651 // It's better to use xadd, xsub or xchg for these in all cases.
18653 case AtomicRMWInst::Or:
18654 case AtomicRMWInst::And:
18655 case AtomicRMWInst::Xor:
18656 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18657 // prefix to a normal instruction for these operations.
18658 return !AI->use_empty();
18659 case AtomicRMWInst::Nand:
18660 case AtomicRMWInst::Max:
18661 case AtomicRMWInst::Min:
18662 case AtomicRMWInst::UMax:
18663 case AtomicRMWInst::UMin:
18664 // These always require a non-trivial set of data operations on x86. We must
18665 // use a cmpxchg loop.
18670 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18671 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18672 // no-sse2). There isn't any reason to disable it if the target processor
18674 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18678 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18679 const X86Subtarget &Subtarget =
18680 getTargetMachine().getSubtarget<X86Subtarget>();
18681 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18682 const Type *MemType = AI->getType();
18683 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18684 // there is no benefit in turning such RMWs into loads, and it is actually
18685 // harmful as it introduces a mfence.
18686 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18689 auto Builder = IRBuilder<>(AI);
18690 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18691 auto SynchScope = AI->getSynchScope();
18692 // We must restrict the ordering to avoid generating loads with Release or
18693 // ReleaseAcquire orderings.
18694 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18695 auto Ptr = AI->getPointerOperand();
18697 // Before the load we need a fence. Here is an example lifted from
18698 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18701 // x.store(1, relaxed);
18702 // r1 = y.fetch_add(0, release);
18704 // y.fetch_add(42, acquire);
18705 // r2 = x.load(relaxed);
18706 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18707 // lowered to just a load without a fence. A mfence flushes the store buffer,
18708 // making the optimization clearly correct.
18709 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18710 // otherwise, we might be able to be more agressive on relaxed idempotent
18711 // rmw. In practice, they do not look useful, so we don't try to be
18712 // especially clever.
18713 if (SynchScope == SingleThread) {
18714 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18715 // the IR level, so we must wrap it in an intrinsic.
18717 } else if (hasMFENCE(Subtarget)) {
18718 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18719 Intrinsic::x86_sse2_mfence);
18720 Builder.CreateCall(MFence);
18722 // FIXME: it might make sense to use a locked operation here but on a
18723 // different cache-line to prevent cache-line bouncing. In practice it
18724 // is probably a small win, and x86 processors without mfence are rare
18725 // enough that we do not bother.
18729 // Finally we can emit the atomic load.
18730 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18731 AI->getType()->getPrimitiveSizeInBits());
18732 Loaded->setAtomic(Order, SynchScope);
18733 AI->replaceAllUsesWith(Loaded);
18734 AI->eraseFromParent();
18738 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18739 SelectionDAG &DAG) {
18741 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18742 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18743 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18744 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18746 // The only fence that needs an instruction is a sequentially-consistent
18747 // cross-thread fence.
18748 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18749 if (hasMFENCE(*Subtarget))
18750 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18752 SDValue Chain = Op.getOperand(0);
18753 SDValue Zero = DAG.getConstant(0, MVT::i32);
18755 DAG.getRegister(X86::ESP, MVT::i32), // Base
18756 DAG.getTargetConstant(1, MVT::i8), // Scale
18757 DAG.getRegister(0, MVT::i32), // Index
18758 DAG.getTargetConstant(0, MVT::i32), // Disp
18759 DAG.getRegister(0, MVT::i32), // Segment.
18763 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18764 return SDValue(Res, 0);
18767 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18768 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18771 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18772 SelectionDAG &DAG) {
18773 MVT T = Op.getSimpleValueType();
18777 switch(T.SimpleTy) {
18778 default: llvm_unreachable("Invalid value type!");
18779 case MVT::i8: Reg = X86::AL; size = 1; break;
18780 case MVT::i16: Reg = X86::AX; size = 2; break;
18781 case MVT::i32: Reg = X86::EAX; size = 4; break;
18783 assert(Subtarget->is64Bit() && "Node not type legal!");
18784 Reg = X86::RAX; size = 8;
18787 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18788 Op.getOperand(2), SDValue());
18789 SDValue Ops[] = { cpIn.getValue(0),
18792 DAG.getTargetConstant(size, MVT::i8),
18793 cpIn.getValue(1) };
18794 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18795 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18796 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18800 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18801 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18802 MVT::i32, cpOut.getValue(2));
18803 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18804 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18806 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18807 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18808 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18812 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18813 SelectionDAG &DAG) {
18814 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18815 MVT DstVT = Op.getSimpleValueType();
18817 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18818 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18819 if (DstVT != MVT::f64)
18820 // This conversion needs to be expanded.
18823 SDValue InVec = Op->getOperand(0);
18825 unsigned NumElts = SrcVT.getVectorNumElements();
18826 EVT SVT = SrcVT.getVectorElementType();
18828 // Widen the vector in input in the case of MVT::v2i32.
18829 // Example: from MVT::v2i32 to MVT::v4i32.
18830 SmallVector<SDValue, 16> Elts;
18831 for (unsigned i = 0, e = NumElts; i != e; ++i)
18832 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18833 DAG.getIntPtrConstant(i)));
18835 // Explicitly mark the extra elements as Undef.
18836 SDValue Undef = DAG.getUNDEF(SVT);
18837 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18838 Elts.push_back(Undef);
18840 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18841 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18842 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18843 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18844 DAG.getIntPtrConstant(0));
18847 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18848 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18849 assert((DstVT == MVT::i64 ||
18850 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18851 "Unexpected custom BITCAST");
18852 // i64 <=> MMX conversions are Legal.
18853 if (SrcVT==MVT::i64 && DstVT.isVector())
18855 if (DstVT==MVT::i64 && SrcVT.isVector())
18857 // MMX <=> MMX conversions are Legal.
18858 if (SrcVT.isVector() && DstVT.isVector())
18860 // All other conversions need to be expanded.
18864 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18865 SDNode *Node = Op.getNode();
18867 EVT T = Node->getValueType(0);
18868 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18869 DAG.getConstant(0, T), Node->getOperand(2));
18870 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18871 cast<AtomicSDNode>(Node)->getMemoryVT(),
18872 Node->getOperand(0),
18873 Node->getOperand(1), negOp,
18874 cast<AtomicSDNode>(Node)->getMemOperand(),
18875 cast<AtomicSDNode>(Node)->getOrdering(),
18876 cast<AtomicSDNode>(Node)->getSynchScope());
18879 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18880 SDNode *Node = Op.getNode();
18882 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18884 // Convert seq_cst store -> xchg
18885 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18886 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18887 // (The only way to get a 16-byte store is cmpxchg16b)
18888 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18889 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18890 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18891 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18892 cast<AtomicSDNode>(Node)->getMemoryVT(),
18893 Node->getOperand(0),
18894 Node->getOperand(1), Node->getOperand(2),
18895 cast<AtomicSDNode>(Node)->getMemOperand(),
18896 cast<AtomicSDNode>(Node)->getOrdering(),
18897 cast<AtomicSDNode>(Node)->getSynchScope());
18898 return Swap.getValue(1);
18900 // Other atomic stores have a simple pattern.
18904 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18905 EVT VT = Op.getNode()->getSimpleValueType(0);
18907 // Let legalize expand this if it isn't a legal type yet.
18908 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18911 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18914 bool ExtraOp = false;
18915 switch (Op.getOpcode()) {
18916 default: llvm_unreachable("Invalid code");
18917 case ISD::ADDC: Opc = X86ISD::ADD; break;
18918 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18919 case ISD::SUBC: Opc = X86ISD::SUB; break;
18920 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18924 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18926 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18927 Op.getOperand(1), Op.getOperand(2));
18930 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18931 SelectionDAG &DAG) {
18932 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18934 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18935 // which returns the values as { float, float } (in XMM0) or
18936 // { double, double } (which is returned in XMM0, XMM1).
18938 SDValue Arg = Op.getOperand(0);
18939 EVT ArgVT = Arg.getValueType();
18940 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18942 TargetLowering::ArgListTy Args;
18943 TargetLowering::ArgListEntry Entry;
18947 Entry.isSExt = false;
18948 Entry.isZExt = false;
18949 Args.push_back(Entry);
18951 bool isF64 = ArgVT == MVT::f64;
18952 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18953 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18954 // the results are returned via SRet in memory.
18955 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18956 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18957 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18959 Type *RetTy = isF64
18960 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18961 : (Type*)VectorType::get(ArgTy, 4);
18963 TargetLowering::CallLoweringInfo CLI(DAG);
18964 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18965 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18967 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18970 // Returned in xmm0 and xmm1.
18971 return CallResult.first;
18973 // Returned in bits 0:31 and 32:64 xmm0.
18974 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18975 CallResult.first, DAG.getIntPtrConstant(0));
18976 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18977 CallResult.first, DAG.getIntPtrConstant(1));
18978 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18979 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18982 /// LowerOperation - Provide custom lowering hooks for some operations.
18984 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18985 switch (Op.getOpcode()) {
18986 default: llvm_unreachable("Should not custom lower this!");
18987 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18988 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18989 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18990 return LowerCMP_SWAP(Op, Subtarget, DAG);
18991 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18992 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18993 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18994 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18995 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18996 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18997 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18998 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18999 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19000 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19001 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19002 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19003 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19004 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19005 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19006 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19007 case ISD::SHL_PARTS:
19008 case ISD::SRA_PARTS:
19009 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19010 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19011 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19012 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19013 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19014 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19015 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19016 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19017 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19018 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19019 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19021 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19022 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19023 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19024 case ISD::SETCC: return LowerSETCC(Op, DAG);
19025 case ISD::SELECT: return LowerSELECT(Op, DAG);
19026 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19027 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19028 case ISD::VASTART: return LowerVASTART(Op, DAG);
19029 case ISD::VAARG: return LowerVAARG(Op, DAG);
19030 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19031 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19032 case ISD::INTRINSIC_VOID:
19033 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19034 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19035 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19036 case ISD::FRAME_TO_ARGS_OFFSET:
19037 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19038 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19039 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19040 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19041 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19042 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19043 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19044 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19045 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19046 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19047 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19048 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19049 case ISD::UMUL_LOHI:
19050 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19053 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19059 case ISD::UMULO: return LowerXALUO(Op, DAG);
19060 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19061 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19065 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19066 case ISD::ADD: return LowerADD(Op, DAG);
19067 case ISD::SUB: return LowerSUB(Op, DAG);
19068 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19072 /// ReplaceNodeResults - Replace a node with an illegal result type
19073 /// with a new node built out of custom code.
19074 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19075 SmallVectorImpl<SDValue>&Results,
19076 SelectionDAG &DAG) const {
19078 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19079 switch (N->getOpcode()) {
19081 llvm_unreachable("Do not know how to custom type legalize this operation!");
19082 case ISD::SIGN_EXTEND_INREG:
19087 // We don't want to expand or promote these.
19094 case ISD::UDIVREM: {
19095 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19096 Results.push_back(V);
19099 case ISD::FP_TO_SINT:
19100 case ISD::FP_TO_UINT: {
19101 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19103 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19106 std::pair<SDValue,SDValue> Vals =
19107 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19108 SDValue FIST = Vals.first, StackSlot = Vals.second;
19109 if (FIST.getNode()) {
19110 EVT VT = N->getValueType(0);
19111 // Return a load from the stack slot.
19112 if (StackSlot.getNode())
19113 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19114 MachinePointerInfo(),
19115 false, false, false, 0));
19117 Results.push_back(FIST);
19121 case ISD::UINT_TO_FP: {
19122 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19123 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19124 N->getValueType(0) != MVT::v2f32)
19126 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19128 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19130 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19131 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19132 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19133 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19134 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19135 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19138 case ISD::FP_ROUND: {
19139 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19141 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19142 Results.push_back(V);
19145 case ISD::INTRINSIC_W_CHAIN: {
19146 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19148 default : llvm_unreachable("Do not know how to custom type "
19149 "legalize this intrinsic operation!");
19150 case Intrinsic::x86_rdtsc:
19151 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19153 case Intrinsic::x86_rdtscp:
19154 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19156 case Intrinsic::x86_rdpmc:
19157 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19160 case ISD::READCYCLECOUNTER: {
19161 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19164 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19165 EVT T = N->getValueType(0);
19166 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19167 bool Regs64bit = T == MVT::i128;
19168 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19169 SDValue cpInL, cpInH;
19170 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19171 DAG.getConstant(0, HalfT));
19172 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19173 DAG.getConstant(1, HalfT));
19174 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19175 Regs64bit ? X86::RAX : X86::EAX,
19177 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19178 Regs64bit ? X86::RDX : X86::EDX,
19179 cpInH, cpInL.getValue(1));
19180 SDValue swapInL, swapInH;
19181 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19182 DAG.getConstant(0, HalfT));
19183 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19184 DAG.getConstant(1, HalfT));
19185 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19186 Regs64bit ? X86::RBX : X86::EBX,
19187 swapInL, cpInH.getValue(1));
19188 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19189 Regs64bit ? X86::RCX : X86::ECX,
19190 swapInH, swapInL.getValue(1));
19191 SDValue Ops[] = { swapInH.getValue(0),
19193 swapInH.getValue(1) };
19194 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19195 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19196 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19197 X86ISD::LCMPXCHG8_DAG;
19198 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19199 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19200 Regs64bit ? X86::RAX : X86::EAX,
19201 HalfT, Result.getValue(1));
19202 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19203 Regs64bit ? X86::RDX : X86::EDX,
19204 HalfT, cpOutL.getValue(2));
19205 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19207 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19208 MVT::i32, cpOutH.getValue(2));
19210 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19211 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19212 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19214 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19215 Results.push_back(Success);
19216 Results.push_back(EFLAGS.getValue(1));
19219 case ISD::ATOMIC_SWAP:
19220 case ISD::ATOMIC_LOAD_ADD:
19221 case ISD::ATOMIC_LOAD_SUB:
19222 case ISD::ATOMIC_LOAD_AND:
19223 case ISD::ATOMIC_LOAD_OR:
19224 case ISD::ATOMIC_LOAD_XOR:
19225 case ISD::ATOMIC_LOAD_NAND:
19226 case ISD::ATOMIC_LOAD_MIN:
19227 case ISD::ATOMIC_LOAD_MAX:
19228 case ISD::ATOMIC_LOAD_UMIN:
19229 case ISD::ATOMIC_LOAD_UMAX:
19230 case ISD::ATOMIC_LOAD: {
19231 // Delegate to generic TypeLegalization. Situations we can really handle
19232 // should have already been dealt with by AtomicExpandPass.cpp.
19235 case ISD::BITCAST: {
19236 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19237 EVT DstVT = N->getValueType(0);
19238 EVT SrcVT = N->getOperand(0)->getValueType(0);
19240 if (SrcVT != MVT::f64 ||
19241 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19244 unsigned NumElts = DstVT.getVectorNumElements();
19245 EVT SVT = DstVT.getVectorElementType();
19246 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19247 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19248 MVT::v2f64, N->getOperand(0));
19249 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19251 if (ExperimentalVectorWideningLegalization) {
19252 // If we are legalizing vectors by widening, we already have the desired
19253 // legal vector type, just return it.
19254 Results.push_back(ToVecInt);
19258 SmallVector<SDValue, 8> Elts;
19259 for (unsigned i = 0, e = NumElts; i != e; ++i)
19260 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19261 ToVecInt, DAG.getIntPtrConstant(i)));
19263 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19268 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19270 default: return nullptr;
19271 case X86ISD::BSF: return "X86ISD::BSF";
19272 case X86ISD::BSR: return "X86ISD::BSR";
19273 case X86ISD::SHLD: return "X86ISD::SHLD";
19274 case X86ISD::SHRD: return "X86ISD::SHRD";
19275 case X86ISD::FAND: return "X86ISD::FAND";
19276 case X86ISD::FANDN: return "X86ISD::FANDN";
19277 case X86ISD::FOR: return "X86ISD::FOR";
19278 case X86ISD::FXOR: return "X86ISD::FXOR";
19279 case X86ISD::FSRL: return "X86ISD::FSRL";
19280 case X86ISD::FILD: return "X86ISD::FILD";
19281 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19282 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19283 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19284 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19285 case X86ISD::FLD: return "X86ISD::FLD";
19286 case X86ISD::FST: return "X86ISD::FST";
19287 case X86ISD::CALL: return "X86ISD::CALL";
19288 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19289 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19290 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19291 case X86ISD::BT: return "X86ISD::BT";
19292 case X86ISD::CMP: return "X86ISD::CMP";
19293 case X86ISD::COMI: return "X86ISD::COMI";
19294 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19295 case X86ISD::CMPM: return "X86ISD::CMPM";
19296 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19297 case X86ISD::SETCC: return "X86ISD::SETCC";
19298 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19299 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19300 case X86ISD::CMOV: return "X86ISD::CMOV";
19301 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19302 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19303 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19304 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19305 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19306 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19307 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19308 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19309 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19310 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19311 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19312 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19313 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19314 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19315 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19316 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19317 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19318 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19319 case X86ISD::HADD: return "X86ISD::HADD";
19320 case X86ISD::HSUB: return "X86ISD::HSUB";
19321 case X86ISD::FHADD: return "X86ISD::FHADD";
19322 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19323 case X86ISD::UMAX: return "X86ISD::UMAX";
19324 case X86ISD::UMIN: return "X86ISD::UMIN";
19325 case X86ISD::SMAX: return "X86ISD::SMAX";
19326 case X86ISD::SMIN: return "X86ISD::SMIN";
19327 case X86ISD::FMAX: return "X86ISD::FMAX";
19328 case X86ISD::FMIN: return "X86ISD::FMIN";
19329 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19330 case X86ISD::FMINC: return "X86ISD::FMINC";
19331 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19332 case X86ISD::FRCP: return "X86ISD::FRCP";
19333 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19334 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19335 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19336 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19337 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19338 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19339 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19340 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19341 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19342 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19343 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19344 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19345 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19346 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19347 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19348 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19349 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19350 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19351 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19352 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19353 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19354 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19355 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19356 case X86ISD::VSHL: return "X86ISD::VSHL";
19357 case X86ISD::VSRL: return "X86ISD::VSRL";
19358 case X86ISD::VSRA: return "X86ISD::VSRA";
19359 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19360 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19361 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19362 case X86ISD::CMPP: return "X86ISD::CMPP";
19363 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19364 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19365 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19366 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19367 case X86ISD::ADD: return "X86ISD::ADD";
19368 case X86ISD::SUB: return "X86ISD::SUB";
19369 case X86ISD::ADC: return "X86ISD::ADC";
19370 case X86ISD::SBB: return "X86ISD::SBB";
19371 case X86ISD::SMUL: return "X86ISD::SMUL";
19372 case X86ISD::UMUL: return "X86ISD::UMUL";
19373 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19374 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19375 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19376 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19377 case X86ISD::INC: return "X86ISD::INC";
19378 case X86ISD::DEC: return "X86ISD::DEC";
19379 case X86ISD::OR: return "X86ISD::OR";
19380 case X86ISD::XOR: return "X86ISD::XOR";
19381 case X86ISD::AND: return "X86ISD::AND";
19382 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19383 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19384 case X86ISD::PTEST: return "X86ISD::PTEST";
19385 case X86ISD::TESTP: return "X86ISD::TESTP";
19386 case X86ISD::TESTM: return "X86ISD::TESTM";
19387 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19388 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19389 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19390 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19391 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19392 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19393 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19394 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19395 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19396 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19397 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19398 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19399 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19400 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19401 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19402 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19403 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19404 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19405 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19406 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19407 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19408 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19409 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19410 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19411 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19412 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19413 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19414 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19415 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19416 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19417 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19418 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19419 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19420 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19421 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19422 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19423 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19424 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19425 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19426 case X86ISD::SAHF: return "X86ISD::SAHF";
19427 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19428 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19429 case X86ISD::FMADD: return "X86ISD::FMADD";
19430 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19431 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19432 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19433 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19434 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19435 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19436 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19437 case X86ISD::XTEST: return "X86ISD::XTEST";
19441 // isLegalAddressingMode - Return true if the addressing mode represented
19442 // by AM is legal for this target, for a load/store of the specified type.
19443 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19445 // X86 supports extremely general addressing modes.
19446 CodeModel::Model M = getTargetMachine().getCodeModel();
19447 Reloc::Model R = getTargetMachine().getRelocationModel();
19449 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19450 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19455 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19457 // If a reference to this global requires an extra load, we can't fold it.
19458 if (isGlobalStubReference(GVFlags))
19461 // If BaseGV requires a register for the PIC base, we cannot also have a
19462 // BaseReg specified.
19463 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19466 // If lower 4G is not available, then we must use rip-relative addressing.
19467 if ((M != CodeModel::Small || R != Reloc::Static) &&
19468 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19472 switch (AM.Scale) {
19478 // These scales always work.
19483 // These scales are formed with basereg+scalereg. Only accept if there is
19488 default: // Other stuff never works.
19495 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19496 unsigned Bits = Ty->getScalarSizeInBits();
19498 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19499 // particularly cheaper than those without.
19503 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19504 // variable shifts just as cheap as scalar ones.
19505 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19508 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19509 // fully general vector.
19513 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19514 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19516 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19517 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19518 return NumBits1 > NumBits2;
19521 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19522 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19525 if (!isTypeLegal(EVT::getEVT(Ty1)))
19528 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19530 // Assuming the caller doesn't have a zeroext or signext return parameter,
19531 // truncation all the way down to i1 is valid.
19535 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19536 return isInt<32>(Imm);
19539 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19540 // Can also use sub to handle negated immediates.
19541 return isInt<32>(Imm);
19544 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19545 if (!VT1.isInteger() || !VT2.isInteger())
19547 unsigned NumBits1 = VT1.getSizeInBits();
19548 unsigned NumBits2 = VT2.getSizeInBits();
19549 return NumBits1 > NumBits2;
19552 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19553 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19554 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19557 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19558 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19559 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19562 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19563 EVT VT1 = Val.getValueType();
19564 if (isZExtFree(VT1, VT2))
19567 if (Val.getOpcode() != ISD::LOAD)
19570 if (!VT1.isSimple() || !VT1.isInteger() ||
19571 !VT2.isSimple() || !VT2.isInteger())
19574 switch (VT1.getSimpleVT().SimpleTy) {
19579 // X86 has 8, 16, and 32-bit zero-extending loads.
19587 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19588 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19591 VT = VT.getScalarType();
19593 if (!VT.isSimple())
19596 switch (VT.getSimpleVT().SimpleTy) {
19607 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19608 // i16 instructions are longer (0x66 prefix) and potentially slower.
19609 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19612 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19613 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19614 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19615 /// are assumed to be legal.
19617 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19619 if (!VT.isSimple())
19622 MVT SVT = VT.getSimpleVT();
19624 // Very little shuffling can be done for 64-bit vectors right now.
19625 if (VT.getSizeInBits() == 64)
19628 // If this is a single-input shuffle with no 128 bit lane crossings we can
19629 // lower it into pshufb.
19630 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19631 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19632 bool isLegal = true;
19633 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19634 if (M[I] >= (int)SVT.getVectorNumElements() ||
19635 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19644 // FIXME: blends, shifts.
19645 return (SVT.getVectorNumElements() == 2 ||
19646 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19647 isMOVLMask(M, SVT) ||
19648 isMOVHLPSMask(M, SVT) ||
19649 isSHUFPMask(M, SVT) ||
19650 isSHUFPMask(M, SVT, /* Commuted */ true) ||
19651 isPSHUFDMask(M, SVT) ||
19652 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
19653 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19654 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19655 isPALIGNRMask(M, SVT, Subtarget) ||
19656 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19657 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19658 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19659 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19660 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19661 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19665 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19667 if (!VT.isSimple())
19670 MVT SVT = VT.getSimpleVT();
19671 unsigned NumElts = SVT.getVectorNumElements();
19672 // FIXME: This collection of masks seems suspect.
19675 if (NumElts == 4 && SVT.is128BitVector()) {
19676 return (isMOVLMask(Mask, SVT) ||
19677 isCommutedMOVLMask(Mask, SVT, true) ||
19678 isSHUFPMask(Mask, SVT) ||
19679 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19680 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19681 Subtarget->hasInt256()));
19686 //===----------------------------------------------------------------------===//
19687 // X86 Scheduler Hooks
19688 //===----------------------------------------------------------------------===//
19690 /// Utility function to emit xbegin specifying the start of an RTM region.
19691 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19692 const TargetInstrInfo *TII) {
19693 DebugLoc DL = MI->getDebugLoc();
19695 const BasicBlock *BB = MBB->getBasicBlock();
19696 MachineFunction::iterator I = MBB;
19699 // For the v = xbegin(), we generate
19710 MachineBasicBlock *thisMBB = MBB;
19711 MachineFunction *MF = MBB->getParent();
19712 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19713 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19714 MF->insert(I, mainMBB);
19715 MF->insert(I, sinkMBB);
19717 // Transfer the remainder of BB and its successor edges to sinkMBB.
19718 sinkMBB->splice(sinkMBB->begin(), MBB,
19719 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19720 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19724 // # fallthrough to mainMBB
19725 // # abortion to sinkMBB
19726 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19727 thisMBB->addSuccessor(mainMBB);
19728 thisMBB->addSuccessor(sinkMBB);
19732 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19733 mainMBB->addSuccessor(sinkMBB);
19736 // EAX is live into the sinkMBB
19737 sinkMBB->addLiveIn(X86::EAX);
19738 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19739 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19742 MI->eraseFromParent();
19746 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19747 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19748 // in the .td file.
19749 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19750 const TargetInstrInfo *TII) {
19752 switch (MI->getOpcode()) {
19753 default: llvm_unreachable("illegal opcode!");
19754 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19755 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19756 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19757 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19758 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19759 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19760 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19761 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19764 DebugLoc dl = MI->getDebugLoc();
19765 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19767 unsigned NumArgs = MI->getNumOperands();
19768 for (unsigned i = 1; i < NumArgs; ++i) {
19769 MachineOperand &Op = MI->getOperand(i);
19770 if (!(Op.isReg() && Op.isImplicit()))
19771 MIB.addOperand(Op);
19773 if (MI->hasOneMemOperand())
19774 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19776 BuildMI(*BB, MI, dl,
19777 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19778 .addReg(X86::XMM0);
19780 MI->eraseFromParent();
19784 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19785 // defs in an instruction pattern
19786 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19787 const TargetInstrInfo *TII) {
19789 switch (MI->getOpcode()) {
19790 default: llvm_unreachable("illegal opcode!");
19791 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19792 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19793 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19794 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19795 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19796 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19797 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19798 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19801 DebugLoc dl = MI->getDebugLoc();
19802 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19804 unsigned NumArgs = MI->getNumOperands(); // remove the results
19805 for (unsigned i = 1; i < NumArgs; ++i) {
19806 MachineOperand &Op = MI->getOperand(i);
19807 if (!(Op.isReg() && Op.isImplicit()))
19808 MIB.addOperand(Op);
19810 if (MI->hasOneMemOperand())
19811 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19813 BuildMI(*BB, MI, dl,
19814 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19817 MI->eraseFromParent();
19821 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19822 const TargetInstrInfo *TII,
19823 const X86Subtarget* Subtarget) {
19824 DebugLoc dl = MI->getDebugLoc();
19826 // Address into RAX/EAX, other two args into ECX, EDX.
19827 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19828 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19829 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19830 for (int i = 0; i < X86::AddrNumOperands; ++i)
19831 MIB.addOperand(MI->getOperand(i));
19833 unsigned ValOps = X86::AddrNumOperands;
19834 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19835 .addReg(MI->getOperand(ValOps).getReg());
19836 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19837 .addReg(MI->getOperand(ValOps+1).getReg());
19839 // The instruction doesn't actually take any operands though.
19840 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19842 MI->eraseFromParent(); // The pseudo is gone now.
19846 MachineBasicBlock *
19847 X86TargetLowering::EmitVAARG64WithCustomInserter(
19849 MachineBasicBlock *MBB) const {
19850 // Emit va_arg instruction on X86-64.
19852 // Operands to this pseudo-instruction:
19853 // 0 ) Output : destination address (reg)
19854 // 1-5) Input : va_list address (addr, i64mem)
19855 // 6 ) ArgSize : Size (in bytes) of vararg type
19856 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19857 // 8 ) Align : Alignment of type
19858 // 9 ) EFLAGS (implicit-def)
19860 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19861 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19863 unsigned DestReg = MI->getOperand(0).getReg();
19864 MachineOperand &Base = MI->getOperand(1);
19865 MachineOperand &Scale = MI->getOperand(2);
19866 MachineOperand &Index = MI->getOperand(3);
19867 MachineOperand &Disp = MI->getOperand(4);
19868 MachineOperand &Segment = MI->getOperand(5);
19869 unsigned ArgSize = MI->getOperand(6).getImm();
19870 unsigned ArgMode = MI->getOperand(7).getImm();
19871 unsigned Align = MI->getOperand(8).getImm();
19873 // Memory Reference
19874 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19875 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19876 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19878 // Machine Information
19879 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19880 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19881 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19882 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19883 DebugLoc DL = MI->getDebugLoc();
19885 // struct va_list {
19888 // i64 overflow_area (address)
19889 // i64 reg_save_area (address)
19891 // sizeof(va_list) = 24
19892 // alignment(va_list) = 8
19894 unsigned TotalNumIntRegs = 6;
19895 unsigned TotalNumXMMRegs = 8;
19896 bool UseGPOffset = (ArgMode == 1);
19897 bool UseFPOffset = (ArgMode == 2);
19898 unsigned MaxOffset = TotalNumIntRegs * 8 +
19899 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19901 /* Align ArgSize to a multiple of 8 */
19902 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19903 bool NeedsAlign = (Align > 8);
19905 MachineBasicBlock *thisMBB = MBB;
19906 MachineBasicBlock *overflowMBB;
19907 MachineBasicBlock *offsetMBB;
19908 MachineBasicBlock *endMBB;
19910 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19911 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19912 unsigned OffsetReg = 0;
19914 if (!UseGPOffset && !UseFPOffset) {
19915 // If we only pull from the overflow region, we don't create a branch.
19916 // We don't need to alter control flow.
19917 OffsetDestReg = 0; // unused
19918 OverflowDestReg = DestReg;
19920 offsetMBB = nullptr;
19921 overflowMBB = thisMBB;
19924 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19925 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19926 // If not, pull from overflow_area. (branch to overflowMBB)
19931 // offsetMBB overflowMBB
19936 // Registers for the PHI in endMBB
19937 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19938 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19940 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19941 MachineFunction *MF = MBB->getParent();
19942 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19943 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19944 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19946 MachineFunction::iterator MBBIter = MBB;
19949 // Insert the new basic blocks
19950 MF->insert(MBBIter, offsetMBB);
19951 MF->insert(MBBIter, overflowMBB);
19952 MF->insert(MBBIter, endMBB);
19954 // Transfer the remainder of MBB and its successor edges to endMBB.
19955 endMBB->splice(endMBB->begin(), thisMBB,
19956 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19957 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19959 // Make offsetMBB and overflowMBB successors of thisMBB
19960 thisMBB->addSuccessor(offsetMBB);
19961 thisMBB->addSuccessor(overflowMBB);
19963 // endMBB is a successor of both offsetMBB and overflowMBB
19964 offsetMBB->addSuccessor(endMBB);
19965 overflowMBB->addSuccessor(endMBB);
19967 // Load the offset value into a register
19968 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19969 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19973 .addDisp(Disp, UseFPOffset ? 4 : 0)
19974 .addOperand(Segment)
19975 .setMemRefs(MMOBegin, MMOEnd);
19977 // Check if there is enough room left to pull this argument.
19978 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19980 .addImm(MaxOffset + 8 - ArgSizeA8);
19982 // Branch to "overflowMBB" if offset >= max
19983 // Fall through to "offsetMBB" otherwise
19984 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19985 .addMBB(overflowMBB);
19988 // In offsetMBB, emit code to use the reg_save_area.
19990 assert(OffsetReg != 0);
19992 // Read the reg_save_area address.
19993 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19994 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19999 .addOperand(Segment)
20000 .setMemRefs(MMOBegin, MMOEnd);
20002 // Zero-extend the offset
20003 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20004 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20007 .addImm(X86::sub_32bit);
20009 // Add the offset to the reg_save_area to get the final address.
20010 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20011 .addReg(OffsetReg64)
20012 .addReg(RegSaveReg);
20014 // Compute the offset for the next argument
20015 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20016 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20018 .addImm(UseFPOffset ? 16 : 8);
20020 // Store it back into the va_list.
20021 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20025 .addDisp(Disp, UseFPOffset ? 4 : 0)
20026 .addOperand(Segment)
20027 .addReg(NextOffsetReg)
20028 .setMemRefs(MMOBegin, MMOEnd);
20031 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20036 // Emit code to use overflow area
20039 // Load the overflow_area address into a register.
20040 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20041 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20046 .addOperand(Segment)
20047 .setMemRefs(MMOBegin, MMOEnd);
20049 // If we need to align it, do so. Otherwise, just copy the address
20050 // to OverflowDestReg.
20052 // Align the overflow address
20053 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20054 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20056 // aligned_addr = (addr + (align-1)) & ~(align-1)
20057 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20058 .addReg(OverflowAddrReg)
20061 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20063 .addImm(~(uint64_t)(Align-1));
20065 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20066 .addReg(OverflowAddrReg);
20069 // Compute the next overflow address after this argument.
20070 // (the overflow address should be kept 8-byte aligned)
20071 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20072 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20073 .addReg(OverflowDestReg)
20074 .addImm(ArgSizeA8);
20076 // Store the new overflow address.
20077 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20082 .addOperand(Segment)
20083 .addReg(NextAddrReg)
20084 .setMemRefs(MMOBegin, MMOEnd);
20086 // If we branched, emit the PHI to the front of endMBB.
20088 BuildMI(*endMBB, endMBB->begin(), DL,
20089 TII->get(X86::PHI), DestReg)
20090 .addReg(OffsetDestReg).addMBB(offsetMBB)
20091 .addReg(OverflowDestReg).addMBB(overflowMBB);
20094 // Erase the pseudo instruction
20095 MI->eraseFromParent();
20100 MachineBasicBlock *
20101 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20103 MachineBasicBlock *MBB) const {
20104 // Emit code to save XMM registers to the stack. The ABI says that the
20105 // number of registers to save is given in %al, so it's theoretically
20106 // possible to do an indirect jump trick to avoid saving all of them,
20107 // however this code takes a simpler approach and just executes all
20108 // of the stores if %al is non-zero. It's less code, and it's probably
20109 // easier on the hardware branch predictor, and stores aren't all that
20110 // expensive anyway.
20112 // Create the new basic blocks. One block contains all the XMM stores,
20113 // and one block is the final destination regardless of whether any
20114 // stores were performed.
20115 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20116 MachineFunction *F = MBB->getParent();
20117 MachineFunction::iterator MBBIter = MBB;
20119 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20120 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20121 F->insert(MBBIter, XMMSaveMBB);
20122 F->insert(MBBIter, EndMBB);
20124 // Transfer the remainder of MBB and its successor edges to EndMBB.
20125 EndMBB->splice(EndMBB->begin(), MBB,
20126 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20127 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20129 // The original block will now fall through to the XMM save block.
20130 MBB->addSuccessor(XMMSaveMBB);
20131 // The XMMSaveMBB will fall through to the end block.
20132 XMMSaveMBB->addSuccessor(EndMBB);
20134 // Now add the instructions.
20135 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20136 DebugLoc DL = MI->getDebugLoc();
20138 unsigned CountReg = MI->getOperand(0).getReg();
20139 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20140 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20142 if (!Subtarget->isTargetWin64()) {
20143 // If %al is 0, branch around the XMM save block.
20144 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20145 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20146 MBB->addSuccessor(EndMBB);
20149 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20150 // that was just emitted, but clearly shouldn't be "saved".
20151 assert((MI->getNumOperands() <= 3 ||
20152 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20153 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20154 && "Expected last argument to be EFLAGS");
20155 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20156 // In the XMM save block, save all the XMM argument registers.
20157 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20158 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20159 MachineMemOperand *MMO =
20160 F->getMachineMemOperand(
20161 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20162 MachineMemOperand::MOStore,
20163 /*Size=*/16, /*Align=*/16);
20164 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20165 .addFrameIndex(RegSaveFrameIndex)
20166 .addImm(/*Scale=*/1)
20167 .addReg(/*IndexReg=*/0)
20168 .addImm(/*Disp=*/Offset)
20169 .addReg(/*Segment=*/0)
20170 .addReg(MI->getOperand(i).getReg())
20171 .addMemOperand(MMO);
20174 MI->eraseFromParent(); // The pseudo instruction is gone now.
20179 // The EFLAGS operand of SelectItr might be missing a kill marker
20180 // because there were multiple uses of EFLAGS, and ISel didn't know
20181 // which to mark. Figure out whether SelectItr should have had a
20182 // kill marker, and set it if it should. Returns the correct kill
20184 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20185 MachineBasicBlock* BB,
20186 const TargetRegisterInfo* TRI) {
20187 // Scan forward through BB for a use/def of EFLAGS.
20188 MachineBasicBlock::iterator miI(std::next(SelectItr));
20189 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20190 const MachineInstr& mi = *miI;
20191 if (mi.readsRegister(X86::EFLAGS))
20193 if (mi.definesRegister(X86::EFLAGS))
20194 break; // Should have kill-flag - update below.
20197 // If we hit the end of the block, check whether EFLAGS is live into a
20199 if (miI == BB->end()) {
20200 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20201 sEnd = BB->succ_end();
20202 sItr != sEnd; ++sItr) {
20203 MachineBasicBlock* succ = *sItr;
20204 if (succ->isLiveIn(X86::EFLAGS))
20209 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20210 // out. SelectMI should have a kill flag on EFLAGS.
20211 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20215 MachineBasicBlock *
20216 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20217 MachineBasicBlock *BB) const {
20218 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20219 DebugLoc DL = MI->getDebugLoc();
20221 // To "insert" a SELECT_CC instruction, we actually have to insert the
20222 // diamond control-flow pattern. The incoming instruction knows the
20223 // destination vreg to set, the condition code register to branch on, the
20224 // true/false values to select between, and a branch opcode to use.
20225 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20226 MachineFunction::iterator It = BB;
20232 // cmpTY ccX, r1, r2
20234 // fallthrough --> copy0MBB
20235 MachineBasicBlock *thisMBB = BB;
20236 MachineFunction *F = BB->getParent();
20237 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20238 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20239 F->insert(It, copy0MBB);
20240 F->insert(It, sinkMBB);
20242 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20243 // live into the sink and copy blocks.
20244 const TargetRegisterInfo *TRI =
20245 BB->getParent()->getSubtarget().getRegisterInfo();
20246 if (!MI->killsRegister(X86::EFLAGS) &&
20247 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20248 copy0MBB->addLiveIn(X86::EFLAGS);
20249 sinkMBB->addLiveIn(X86::EFLAGS);
20252 // Transfer the remainder of BB and its successor edges to sinkMBB.
20253 sinkMBB->splice(sinkMBB->begin(), BB,
20254 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20255 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20257 // Add the true and fallthrough blocks as its successors.
20258 BB->addSuccessor(copy0MBB);
20259 BB->addSuccessor(sinkMBB);
20261 // Create the conditional branch instruction.
20263 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20264 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20267 // %FalseValue = ...
20268 // # fallthrough to sinkMBB
20269 copy0MBB->addSuccessor(sinkMBB);
20272 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20274 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20275 TII->get(X86::PHI), MI->getOperand(0).getReg())
20276 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20277 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20279 MI->eraseFromParent(); // The pseudo instruction is gone now.
20283 MachineBasicBlock *
20284 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20285 MachineBasicBlock *BB) const {
20286 MachineFunction *MF = BB->getParent();
20287 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20288 DebugLoc DL = MI->getDebugLoc();
20289 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20291 assert(MF->shouldSplitStack());
20293 const bool Is64Bit = Subtarget->is64Bit();
20294 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20296 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20297 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20300 // ... [Till the alloca]
20301 // If stacklet is not large enough, jump to mallocMBB
20304 // Allocate by subtracting from RSP
20305 // Jump to continueMBB
20308 // Allocate by call to runtime
20312 // [rest of original BB]
20315 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20316 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20317 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20319 MachineRegisterInfo &MRI = MF->getRegInfo();
20320 const TargetRegisterClass *AddrRegClass =
20321 getRegClassFor(getPointerTy());
20323 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20324 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20325 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20326 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20327 sizeVReg = MI->getOperand(1).getReg(),
20328 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20330 MachineFunction::iterator MBBIter = BB;
20333 MF->insert(MBBIter, bumpMBB);
20334 MF->insert(MBBIter, mallocMBB);
20335 MF->insert(MBBIter, continueMBB);
20337 continueMBB->splice(continueMBB->begin(), BB,
20338 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20339 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20341 // Add code to the main basic block to check if the stack limit has been hit,
20342 // and if so, jump to mallocMBB otherwise to bumpMBB.
20343 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20344 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20345 .addReg(tmpSPVReg).addReg(sizeVReg);
20346 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20347 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20348 .addReg(SPLimitVReg);
20349 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20351 // bumpMBB simply decreases the stack pointer, since we know the current
20352 // stacklet has enough space.
20353 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20354 .addReg(SPLimitVReg);
20355 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20356 .addReg(SPLimitVReg);
20357 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20359 // Calls into a routine in libgcc to allocate more space from the heap.
20360 const uint32_t *RegMask = MF->getTarget()
20361 .getSubtargetImpl()
20362 ->getRegisterInfo()
20363 ->getCallPreservedMask(CallingConv::C);
20365 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20367 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20368 .addExternalSymbol("__morestack_allocate_stack_space")
20369 .addRegMask(RegMask)
20370 .addReg(X86::RDI, RegState::Implicit)
20371 .addReg(X86::RAX, RegState::ImplicitDefine);
20372 } else if (Is64Bit) {
20373 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20375 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20376 .addExternalSymbol("__morestack_allocate_stack_space")
20377 .addRegMask(RegMask)
20378 .addReg(X86::EDI, RegState::Implicit)
20379 .addReg(X86::EAX, RegState::ImplicitDefine);
20381 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20383 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20384 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20385 .addExternalSymbol("__morestack_allocate_stack_space")
20386 .addRegMask(RegMask)
20387 .addReg(X86::EAX, RegState::ImplicitDefine);
20391 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20394 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20395 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20396 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20398 // Set up the CFG correctly.
20399 BB->addSuccessor(bumpMBB);
20400 BB->addSuccessor(mallocMBB);
20401 mallocMBB->addSuccessor(continueMBB);
20402 bumpMBB->addSuccessor(continueMBB);
20404 // Take care of the PHI nodes.
20405 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20406 MI->getOperand(0).getReg())
20407 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20408 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20410 // Delete the original pseudo instruction.
20411 MI->eraseFromParent();
20414 return continueMBB;
20417 MachineBasicBlock *
20418 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20419 MachineBasicBlock *BB) const {
20420 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20421 DebugLoc DL = MI->getDebugLoc();
20423 assert(!Subtarget->isTargetMacho());
20425 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20426 // non-trivial part is impdef of ESP.
20428 if (Subtarget->isTargetWin64()) {
20429 if (Subtarget->isTargetCygMing()) {
20430 // ___chkstk(Mingw64):
20431 // Clobbers R10, R11, RAX and EFLAGS.
20433 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20434 .addExternalSymbol("___chkstk")
20435 .addReg(X86::RAX, RegState::Implicit)
20436 .addReg(X86::RSP, RegState::Implicit)
20437 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20438 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20439 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20441 // __chkstk(MSVCRT): does not update stack pointer.
20442 // Clobbers R10, R11 and EFLAGS.
20443 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20444 .addExternalSymbol("__chkstk")
20445 .addReg(X86::RAX, RegState::Implicit)
20446 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20447 // RAX has the offset to be subtracted from RSP.
20448 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20453 const char *StackProbeSymbol =
20454 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
20456 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20457 .addExternalSymbol(StackProbeSymbol)
20458 .addReg(X86::EAX, RegState::Implicit)
20459 .addReg(X86::ESP, RegState::Implicit)
20460 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20461 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20462 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20465 MI->eraseFromParent(); // The pseudo instruction is gone now.
20469 MachineBasicBlock *
20470 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20471 MachineBasicBlock *BB) const {
20472 // This is pretty easy. We're taking the value that we received from
20473 // our load from the relocation, sticking it in either RDI (x86-64)
20474 // or EAX and doing an indirect call. The return value will then
20475 // be in the normal return register.
20476 MachineFunction *F = BB->getParent();
20477 const X86InstrInfo *TII =
20478 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20479 DebugLoc DL = MI->getDebugLoc();
20481 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20482 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20484 // Get a register mask for the lowered call.
20485 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20486 // proper register mask.
20487 const uint32_t *RegMask = F->getTarget()
20488 .getSubtargetImpl()
20489 ->getRegisterInfo()
20490 ->getCallPreservedMask(CallingConv::C);
20491 if (Subtarget->is64Bit()) {
20492 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20493 TII->get(X86::MOV64rm), X86::RDI)
20495 .addImm(0).addReg(0)
20496 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20497 MI->getOperand(3).getTargetFlags())
20499 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20500 addDirectMem(MIB, X86::RDI);
20501 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20502 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20503 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20504 TII->get(X86::MOV32rm), X86::EAX)
20506 .addImm(0).addReg(0)
20507 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20508 MI->getOperand(3).getTargetFlags())
20510 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20511 addDirectMem(MIB, X86::EAX);
20512 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20514 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20515 TII->get(X86::MOV32rm), X86::EAX)
20516 .addReg(TII->getGlobalBaseReg(F))
20517 .addImm(0).addReg(0)
20518 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20519 MI->getOperand(3).getTargetFlags())
20521 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20522 addDirectMem(MIB, X86::EAX);
20523 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20526 MI->eraseFromParent(); // The pseudo instruction is gone now.
20530 MachineBasicBlock *
20531 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20532 MachineBasicBlock *MBB) const {
20533 DebugLoc DL = MI->getDebugLoc();
20534 MachineFunction *MF = MBB->getParent();
20535 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20536 MachineRegisterInfo &MRI = MF->getRegInfo();
20538 const BasicBlock *BB = MBB->getBasicBlock();
20539 MachineFunction::iterator I = MBB;
20542 // Memory Reference
20543 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20544 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20547 unsigned MemOpndSlot = 0;
20549 unsigned CurOp = 0;
20551 DstReg = MI->getOperand(CurOp++).getReg();
20552 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20553 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20554 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20555 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20557 MemOpndSlot = CurOp;
20559 MVT PVT = getPointerTy();
20560 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20561 "Invalid Pointer Size!");
20563 // For v = setjmp(buf), we generate
20566 // buf[LabelOffset] = restoreMBB
20567 // SjLjSetup restoreMBB
20573 // v = phi(main, restore)
20578 MachineBasicBlock *thisMBB = MBB;
20579 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20580 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20581 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20582 MF->insert(I, mainMBB);
20583 MF->insert(I, sinkMBB);
20584 MF->push_back(restoreMBB);
20586 MachineInstrBuilder MIB;
20588 // Transfer the remainder of BB and its successor edges to sinkMBB.
20589 sinkMBB->splice(sinkMBB->begin(), MBB,
20590 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20591 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20594 unsigned PtrStoreOpc = 0;
20595 unsigned LabelReg = 0;
20596 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20597 Reloc::Model RM = MF->getTarget().getRelocationModel();
20598 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20599 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20601 // Prepare IP either in reg or imm.
20602 if (!UseImmLabel) {
20603 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20604 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20605 LabelReg = MRI.createVirtualRegister(PtrRC);
20606 if (Subtarget->is64Bit()) {
20607 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20611 .addMBB(restoreMBB)
20614 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20615 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20616 .addReg(XII->getGlobalBaseReg(MF))
20619 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20623 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20625 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20626 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20627 if (i == X86::AddrDisp)
20628 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20630 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20633 MIB.addReg(LabelReg);
20635 MIB.addMBB(restoreMBB);
20636 MIB.setMemRefs(MMOBegin, MMOEnd);
20638 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20639 .addMBB(restoreMBB);
20641 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20642 MF->getSubtarget().getRegisterInfo());
20643 MIB.addRegMask(RegInfo->getNoPreservedMask());
20644 thisMBB->addSuccessor(mainMBB);
20645 thisMBB->addSuccessor(restoreMBB);
20649 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20650 mainMBB->addSuccessor(sinkMBB);
20653 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20654 TII->get(X86::PHI), DstReg)
20655 .addReg(mainDstReg).addMBB(mainMBB)
20656 .addReg(restoreDstReg).addMBB(restoreMBB);
20659 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20660 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20661 restoreMBB->addSuccessor(sinkMBB);
20663 MI->eraseFromParent();
20667 MachineBasicBlock *
20668 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20669 MachineBasicBlock *MBB) const {
20670 DebugLoc DL = MI->getDebugLoc();
20671 MachineFunction *MF = MBB->getParent();
20672 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20673 MachineRegisterInfo &MRI = MF->getRegInfo();
20675 // Memory Reference
20676 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20677 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20679 MVT PVT = getPointerTy();
20680 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20681 "Invalid Pointer Size!");
20683 const TargetRegisterClass *RC =
20684 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20685 unsigned Tmp = MRI.createVirtualRegister(RC);
20686 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20687 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20688 MF->getSubtarget().getRegisterInfo());
20689 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20690 unsigned SP = RegInfo->getStackRegister();
20692 MachineInstrBuilder MIB;
20694 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20695 const int64_t SPOffset = 2 * PVT.getStoreSize();
20697 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20698 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20701 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20702 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20703 MIB.addOperand(MI->getOperand(i));
20704 MIB.setMemRefs(MMOBegin, MMOEnd);
20706 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20707 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20708 if (i == X86::AddrDisp)
20709 MIB.addDisp(MI->getOperand(i), LabelOffset);
20711 MIB.addOperand(MI->getOperand(i));
20713 MIB.setMemRefs(MMOBegin, MMOEnd);
20715 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20716 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20717 if (i == X86::AddrDisp)
20718 MIB.addDisp(MI->getOperand(i), SPOffset);
20720 MIB.addOperand(MI->getOperand(i));
20722 MIB.setMemRefs(MMOBegin, MMOEnd);
20724 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20726 MI->eraseFromParent();
20730 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20731 // accumulator loops. Writing back to the accumulator allows the coalescer
20732 // to remove extra copies in the loop.
20733 MachineBasicBlock *
20734 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20735 MachineBasicBlock *MBB) const {
20736 MachineOperand &AddendOp = MI->getOperand(3);
20738 // Bail out early if the addend isn't a register - we can't switch these.
20739 if (!AddendOp.isReg())
20742 MachineFunction &MF = *MBB->getParent();
20743 MachineRegisterInfo &MRI = MF.getRegInfo();
20745 // Check whether the addend is defined by a PHI:
20746 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20747 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20748 if (!AddendDef.isPHI())
20751 // Look for the following pattern:
20753 // %addend = phi [%entry, 0], [%loop, %result]
20755 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20759 // %addend = phi [%entry, 0], [%loop, %result]
20761 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20763 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20764 assert(AddendDef.getOperand(i).isReg());
20765 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20766 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20767 if (&PHISrcInst == MI) {
20768 // Found a matching instruction.
20769 unsigned NewFMAOpc = 0;
20770 switch (MI->getOpcode()) {
20771 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20772 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20773 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20774 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20775 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20776 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20777 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20778 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20779 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20780 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20781 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20782 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20783 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20784 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20785 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20786 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20787 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20788 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20789 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20790 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20792 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20793 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20794 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20795 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20796 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20797 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20798 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20799 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20800 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20801 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20802 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20803 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20804 default: llvm_unreachable("Unrecognized FMA variant.");
20807 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20808 MachineInstrBuilder MIB =
20809 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20810 .addOperand(MI->getOperand(0))
20811 .addOperand(MI->getOperand(3))
20812 .addOperand(MI->getOperand(2))
20813 .addOperand(MI->getOperand(1));
20814 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20815 MI->eraseFromParent();
20822 MachineBasicBlock *
20823 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20824 MachineBasicBlock *BB) const {
20825 switch (MI->getOpcode()) {
20826 default: llvm_unreachable("Unexpected instr type to insert");
20827 case X86::TAILJMPd64:
20828 case X86::TAILJMPr64:
20829 case X86::TAILJMPm64:
20830 llvm_unreachable("TAILJMP64 would not be touched here.");
20831 case X86::TCRETURNdi64:
20832 case X86::TCRETURNri64:
20833 case X86::TCRETURNmi64:
20835 case X86::WIN_ALLOCA:
20836 return EmitLoweredWinAlloca(MI, BB);
20837 case X86::SEG_ALLOCA_32:
20838 case X86::SEG_ALLOCA_64:
20839 return EmitLoweredSegAlloca(MI, BB);
20840 case X86::TLSCall_32:
20841 case X86::TLSCall_64:
20842 return EmitLoweredTLSCall(MI, BB);
20843 case X86::CMOV_GR8:
20844 case X86::CMOV_FR32:
20845 case X86::CMOV_FR64:
20846 case X86::CMOV_V4F32:
20847 case X86::CMOV_V2F64:
20848 case X86::CMOV_V2I64:
20849 case X86::CMOV_V8F32:
20850 case X86::CMOV_V4F64:
20851 case X86::CMOV_V4I64:
20852 case X86::CMOV_V16F32:
20853 case X86::CMOV_V8F64:
20854 case X86::CMOV_V8I64:
20855 case X86::CMOV_GR16:
20856 case X86::CMOV_GR32:
20857 case X86::CMOV_RFP32:
20858 case X86::CMOV_RFP64:
20859 case X86::CMOV_RFP80:
20860 return EmitLoweredSelect(MI, BB);
20862 case X86::FP32_TO_INT16_IN_MEM:
20863 case X86::FP32_TO_INT32_IN_MEM:
20864 case X86::FP32_TO_INT64_IN_MEM:
20865 case X86::FP64_TO_INT16_IN_MEM:
20866 case X86::FP64_TO_INT32_IN_MEM:
20867 case X86::FP64_TO_INT64_IN_MEM:
20868 case X86::FP80_TO_INT16_IN_MEM:
20869 case X86::FP80_TO_INT32_IN_MEM:
20870 case X86::FP80_TO_INT64_IN_MEM: {
20871 MachineFunction *F = BB->getParent();
20872 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20873 DebugLoc DL = MI->getDebugLoc();
20875 // Change the floating point control register to use "round towards zero"
20876 // mode when truncating to an integer value.
20877 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20878 addFrameReference(BuildMI(*BB, MI, DL,
20879 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20881 // Load the old value of the high byte of the control word...
20883 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20884 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20887 // Set the high part to be round to zero...
20888 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20891 // Reload the modified control word now...
20892 addFrameReference(BuildMI(*BB, MI, DL,
20893 TII->get(X86::FLDCW16m)), CWFrameIdx);
20895 // Restore the memory image of control word to original value
20896 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20899 // Get the X86 opcode to use.
20901 switch (MI->getOpcode()) {
20902 default: llvm_unreachable("illegal opcode!");
20903 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20904 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20905 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20906 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20907 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20908 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20909 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20910 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20911 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20915 MachineOperand &Op = MI->getOperand(0);
20917 AM.BaseType = X86AddressMode::RegBase;
20918 AM.Base.Reg = Op.getReg();
20920 AM.BaseType = X86AddressMode::FrameIndexBase;
20921 AM.Base.FrameIndex = Op.getIndex();
20923 Op = MI->getOperand(1);
20925 AM.Scale = Op.getImm();
20926 Op = MI->getOperand(2);
20928 AM.IndexReg = Op.getImm();
20929 Op = MI->getOperand(3);
20930 if (Op.isGlobal()) {
20931 AM.GV = Op.getGlobal();
20933 AM.Disp = Op.getImm();
20935 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20936 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20938 // Reload the original control word now.
20939 addFrameReference(BuildMI(*BB, MI, DL,
20940 TII->get(X86::FLDCW16m)), CWFrameIdx);
20942 MI->eraseFromParent(); // The pseudo instruction is gone now.
20945 // String/text processing lowering.
20946 case X86::PCMPISTRM128REG:
20947 case X86::VPCMPISTRM128REG:
20948 case X86::PCMPISTRM128MEM:
20949 case X86::VPCMPISTRM128MEM:
20950 case X86::PCMPESTRM128REG:
20951 case X86::VPCMPESTRM128REG:
20952 case X86::PCMPESTRM128MEM:
20953 case X86::VPCMPESTRM128MEM:
20954 assert(Subtarget->hasSSE42() &&
20955 "Target must have SSE4.2 or AVX features enabled");
20956 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20958 // String/text processing lowering.
20959 case X86::PCMPISTRIREG:
20960 case X86::VPCMPISTRIREG:
20961 case X86::PCMPISTRIMEM:
20962 case X86::VPCMPISTRIMEM:
20963 case X86::PCMPESTRIREG:
20964 case X86::VPCMPESTRIREG:
20965 case X86::PCMPESTRIMEM:
20966 case X86::VPCMPESTRIMEM:
20967 assert(Subtarget->hasSSE42() &&
20968 "Target must have SSE4.2 or AVX features enabled");
20969 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20971 // Thread synchronization.
20973 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20978 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20980 case X86::VASTART_SAVE_XMM_REGS:
20981 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20983 case X86::VAARG_64:
20984 return EmitVAARG64WithCustomInserter(MI, BB);
20986 case X86::EH_SjLj_SetJmp32:
20987 case X86::EH_SjLj_SetJmp64:
20988 return emitEHSjLjSetJmp(MI, BB);
20990 case X86::EH_SjLj_LongJmp32:
20991 case X86::EH_SjLj_LongJmp64:
20992 return emitEHSjLjLongJmp(MI, BB);
20994 case TargetOpcode::STACKMAP:
20995 case TargetOpcode::PATCHPOINT:
20996 return emitPatchPoint(MI, BB);
20998 case X86::VFMADDPDr213r:
20999 case X86::VFMADDPSr213r:
21000 case X86::VFMADDSDr213r:
21001 case X86::VFMADDSSr213r:
21002 case X86::VFMSUBPDr213r:
21003 case X86::VFMSUBPSr213r:
21004 case X86::VFMSUBSDr213r:
21005 case X86::VFMSUBSSr213r:
21006 case X86::VFNMADDPDr213r:
21007 case X86::VFNMADDPSr213r:
21008 case X86::VFNMADDSDr213r:
21009 case X86::VFNMADDSSr213r:
21010 case X86::VFNMSUBPDr213r:
21011 case X86::VFNMSUBPSr213r:
21012 case X86::VFNMSUBSDr213r:
21013 case X86::VFNMSUBSSr213r:
21014 case X86::VFMADDSUBPDr213r:
21015 case X86::VFMADDSUBPSr213r:
21016 case X86::VFMSUBADDPDr213r:
21017 case X86::VFMSUBADDPSr213r:
21018 case X86::VFMADDPDr213rY:
21019 case X86::VFMADDPSr213rY:
21020 case X86::VFMSUBPDr213rY:
21021 case X86::VFMSUBPSr213rY:
21022 case X86::VFNMADDPDr213rY:
21023 case X86::VFNMADDPSr213rY:
21024 case X86::VFNMSUBPDr213rY:
21025 case X86::VFNMSUBPSr213rY:
21026 case X86::VFMADDSUBPDr213rY:
21027 case X86::VFMADDSUBPSr213rY:
21028 case X86::VFMSUBADDPDr213rY:
21029 case X86::VFMSUBADDPSr213rY:
21030 return emitFMA3Instr(MI, BB);
21034 //===----------------------------------------------------------------------===//
21035 // X86 Optimization Hooks
21036 //===----------------------------------------------------------------------===//
21038 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21041 const SelectionDAG &DAG,
21042 unsigned Depth) const {
21043 unsigned BitWidth = KnownZero.getBitWidth();
21044 unsigned Opc = Op.getOpcode();
21045 assert((Opc >= ISD::BUILTIN_OP_END ||
21046 Opc == ISD::INTRINSIC_WO_CHAIN ||
21047 Opc == ISD::INTRINSIC_W_CHAIN ||
21048 Opc == ISD::INTRINSIC_VOID) &&
21049 "Should use MaskedValueIsZero if you don't know whether Op"
21050 " is a target node!");
21052 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21066 // These nodes' second result is a boolean.
21067 if (Op.getResNo() == 0)
21070 case X86ISD::SETCC:
21071 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21073 case ISD::INTRINSIC_WO_CHAIN: {
21074 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21075 unsigned NumLoBits = 0;
21078 case Intrinsic::x86_sse_movmsk_ps:
21079 case Intrinsic::x86_avx_movmsk_ps_256:
21080 case Intrinsic::x86_sse2_movmsk_pd:
21081 case Intrinsic::x86_avx_movmsk_pd_256:
21082 case Intrinsic::x86_mmx_pmovmskb:
21083 case Intrinsic::x86_sse2_pmovmskb_128:
21084 case Intrinsic::x86_avx2_pmovmskb: {
21085 // High bits of movmskp{s|d}, pmovmskb are known zero.
21087 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21088 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21089 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21090 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21091 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21092 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21093 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21094 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21096 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21105 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21107 const SelectionDAG &,
21108 unsigned Depth) const {
21109 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21110 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21111 return Op.getValueType().getScalarType().getSizeInBits();
21117 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21118 /// node is a GlobalAddress + offset.
21119 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21120 const GlobalValue* &GA,
21121 int64_t &Offset) const {
21122 if (N->getOpcode() == X86ISD::Wrapper) {
21123 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21124 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21125 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21129 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21132 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21133 /// same as extracting the high 128-bit part of 256-bit vector and then
21134 /// inserting the result into the low part of a new 256-bit vector
21135 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21136 EVT VT = SVOp->getValueType(0);
21137 unsigned NumElems = VT.getVectorNumElements();
21139 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21140 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21141 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21142 SVOp->getMaskElt(j) >= 0)
21148 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21149 /// same as extracting the low 128-bit part of 256-bit vector and then
21150 /// inserting the result into the high part of a new 256-bit vector
21151 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21152 EVT VT = SVOp->getValueType(0);
21153 unsigned NumElems = VT.getVectorNumElements();
21155 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21156 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21157 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21158 SVOp->getMaskElt(j) >= 0)
21164 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21165 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21166 TargetLowering::DAGCombinerInfo &DCI,
21167 const X86Subtarget* Subtarget) {
21169 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21170 SDValue V1 = SVOp->getOperand(0);
21171 SDValue V2 = SVOp->getOperand(1);
21172 EVT VT = SVOp->getValueType(0);
21173 unsigned NumElems = VT.getVectorNumElements();
21175 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21176 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21180 // V UNDEF BUILD_VECTOR UNDEF
21182 // CONCAT_VECTOR CONCAT_VECTOR
21185 // RESULT: V + zero extended
21187 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21188 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21189 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21192 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21195 // To match the shuffle mask, the first half of the mask should
21196 // be exactly the first vector, and all the rest a splat with the
21197 // first element of the second one.
21198 for (unsigned i = 0; i != NumElems/2; ++i)
21199 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21200 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21203 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21204 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21205 if (Ld->hasNUsesOfValue(1, 0)) {
21206 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21207 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21209 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21211 Ld->getPointerInfo(),
21212 Ld->getAlignment(),
21213 false/*isVolatile*/, true/*ReadMem*/,
21214 false/*WriteMem*/);
21216 // Make sure the newly-created LOAD is in the same position as Ld in
21217 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21218 // and update uses of Ld's output chain to use the TokenFactor.
21219 if (Ld->hasAnyUseOfValue(1)) {
21220 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21221 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21222 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21223 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21224 SDValue(ResNode.getNode(), 1));
21227 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21231 // Emit a zeroed vector and insert the desired subvector on its
21233 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21234 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21235 return DCI.CombineTo(N, InsV);
21238 //===--------------------------------------------------------------------===//
21239 // Combine some shuffles into subvector extracts and inserts:
21242 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21243 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21244 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21245 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21246 return DCI.CombineTo(N, InsV);
21249 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21250 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21251 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21252 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21253 return DCI.CombineTo(N, InsV);
21259 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21262 /// This is the leaf of the recursive combinine below. When we have found some
21263 /// chain of single-use x86 shuffle instructions and accumulated the combined
21264 /// shuffle mask represented by them, this will try to pattern match that mask
21265 /// into either a single instruction if there is a special purpose instruction
21266 /// for this operation, or into a PSHUFB instruction which is a fully general
21267 /// instruction but should only be used to replace chains over a certain depth.
21268 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21269 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21270 TargetLowering::DAGCombinerInfo &DCI,
21271 const X86Subtarget *Subtarget) {
21272 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21274 // Find the operand that enters the chain. Note that multiple uses are OK
21275 // here, we're not going to remove the operand we find.
21276 SDValue Input = Op.getOperand(0);
21277 while (Input.getOpcode() == ISD::BITCAST)
21278 Input = Input.getOperand(0);
21280 MVT VT = Input.getSimpleValueType();
21281 MVT RootVT = Root.getSimpleValueType();
21284 // Just remove no-op shuffle masks.
21285 if (Mask.size() == 1) {
21286 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21291 // Use the float domain if the operand type is a floating point type.
21292 bool FloatDomain = VT.isFloatingPoint();
21294 // For floating point shuffles, we don't have free copies in the shuffle
21295 // instructions or the ability to load as part of the instruction, so
21296 // canonicalize their shuffles to UNPCK or MOV variants.
21298 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21299 // vectors because it can have a load folded into it that UNPCK cannot. This
21300 // doesn't preclude something switching to the shorter encoding post-RA.
21302 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21303 bool Lo = Mask.equals(0, 0);
21306 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21307 // is no slower than UNPCKLPD but has the option to fold the input operand
21308 // into even an unaligned memory load.
21309 if (Lo && Subtarget->hasSSE3()) {
21310 Shuffle = X86ISD::MOVDDUP;
21311 ShuffleVT = MVT::v2f64;
21313 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21314 // than the UNPCK variants.
21315 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21316 ShuffleVT = MVT::v4f32;
21318 if (Depth == 1 && Root->getOpcode() == Shuffle)
21319 return false; // Nothing to do!
21320 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21321 DCI.AddToWorklist(Op.getNode());
21322 if (Shuffle == X86ISD::MOVDDUP)
21323 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21325 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21326 DCI.AddToWorklist(Op.getNode());
21327 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21331 if (Subtarget->hasSSE3() &&
21332 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21333 bool Lo = Mask.equals(0, 0, 2, 2);
21334 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21335 MVT ShuffleVT = MVT::v4f32;
21336 if (Depth == 1 && Root->getOpcode() == Shuffle)
21337 return false; // Nothing to do!
21338 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21339 DCI.AddToWorklist(Op.getNode());
21340 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21341 DCI.AddToWorklist(Op.getNode());
21342 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21346 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21347 bool Lo = Mask.equals(0, 0, 1, 1);
21348 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21349 MVT ShuffleVT = MVT::v4f32;
21350 if (Depth == 1 && Root->getOpcode() == Shuffle)
21351 return false; // Nothing to do!
21352 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21353 DCI.AddToWorklist(Op.getNode());
21354 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21355 DCI.AddToWorklist(Op.getNode());
21356 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21362 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21363 // variants as none of these have single-instruction variants that are
21364 // superior to the UNPCK formulation.
21365 if (!FloatDomain &&
21366 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21367 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21368 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21369 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21371 bool Lo = Mask[0] == 0;
21372 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21373 if (Depth == 1 && Root->getOpcode() == Shuffle)
21374 return false; // Nothing to do!
21376 switch (Mask.size()) {
21378 ShuffleVT = MVT::v8i16;
21381 ShuffleVT = MVT::v16i8;
21384 llvm_unreachable("Impossible mask size!");
21386 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21387 DCI.AddToWorklist(Op.getNode());
21388 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21389 DCI.AddToWorklist(Op.getNode());
21390 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21395 // Don't try to re-form single instruction chains under any circumstances now
21396 // that we've done encoding canonicalization for them.
21400 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21401 // can replace them with a single PSHUFB instruction profitably. Intel's
21402 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21403 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21404 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21405 SmallVector<SDValue, 16> PSHUFBMask;
21406 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21407 int Ratio = 16 / Mask.size();
21408 for (unsigned i = 0; i < 16; ++i) {
21409 if (Mask[i / Ratio] == SM_SentinelUndef) {
21410 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21413 int M = Mask[i / Ratio] != SM_SentinelZero
21414 ? Ratio * Mask[i / Ratio] + i % Ratio
21416 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21418 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21419 DCI.AddToWorklist(Op.getNode());
21420 SDValue PSHUFBMaskOp =
21421 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21422 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21423 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21424 DCI.AddToWorklist(Op.getNode());
21425 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21430 // Failed to find any combines.
21434 /// \brief Fully generic combining of x86 shuffle instructions.
21436 /// This should be the last combine run over the x86 shuffle instructions. Once
21437 /// they have been fully optimized, this will recursively consider all chains
21438 /// of single-use shuffle instructions, build a generic model of the cumulative
21439 /// shuffle operation, and check for simpler instructions which implement this
21440 /// operation. We use this primarily for two purposes:
21442 /// 1) Collapse generic shuffles to specialized single instructions when
21443 /// equivalent. In most cases, this is just an encoding size win, but
21444 /// sometimes we will collapse multiple generic shuffles into a single
21445 /// special-purpose shuffle.
21446 /// 2) Look for sequences of shuffle instructions with 3 or more total
21447 /// instructions, and replace them with the slightly more expensive SSSE3
21448 /// PSHUFB instruction if available. We do this as the last combining step
21449 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21450 /// a suitable short sequence of other instructions. The PHUFB will either
21451 /// use a register or have to read from memory and so is slightly (but only
21452 /// slightly) more expensive than the other shuffle instructions.
21454 /// Because this is inherently a quadratic operation (for each shuffle in
21455 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21456 /// This should never be an issue in practice as the shuffle lowering doesn't
21457 /// produce sequences of more than 8 instructions.
21459 /// FIXME: We will currently miss some cases where the redundant shuffling
21460 /// would simplify under the threshold for PSHUFB formation because of
21461 /// combine-ordering. To fix this, we should do the redundant instruction
21462 /// combining in this recursive walk.
21463 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21464 ArrayRef<int> RootMask,
21465 int Depth, bool HasPSHUFB,
21467 TargetLowering::DAGCombinerInfo &DCI,
21468 const X86Subtarget *Subtarget) {
21469 // Bound the depth of our recursive combine because this is ultimately
21470 // quadratic in nature.
21474 // Directly rip through bitcasts to find the underlying operand.
21475 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21476 Op = Op.getOperand(0);
21478 MVT VT = Op.getSimpleValueType();
21479 if (!VT.isVector())
21480 return false; // Bail if we hit a non-vector.
21481 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21482 // version should be added.
21483 if (VT.getSizeInBits() != 128)
21486 assert(Root.getSimpleValueType().isVector() &&
21487 "Shuffles operate on vector types!");
21488 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21489 "Can only combine shuffles of the same vector register size.");
21491 if (!isTargetShuffle(Op.getOpcode()))
21493 SmallVector<int, 16> OpMask;
21495 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21496 // We only can combine unary shuffles which we can decode the mask for.
21497 if (!HaveMask || !IsUnary)
21500 assert(VT.getVectorNumElements() == OpMask.size() &&
21501 "Different mask size from vector size!");
21502 assert(((RootMask.size() > OpMask.size() &&
21503 RootMask.size() % OpMask.size() == 0) ||
21504 (OpMask.size() > RootMask.size() &&
21505 OpMask.size() % RootMask.size() == 0) ||
21506 OpMask.size() == RootMask.size()) &&
21507 "The smaller number of elements must divide the larger.");
21508 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21509 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21510 assert(((RootRatio == 1 && OpRatio == 1) ||
21511 (RootRatio == 1) != (OpRatio == 1)) &&
21512 "Must not have a ratio for both incoming and op masks!");
21514 SmallVector<int, 16> Mask;
21515 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21517 // Merge this shuffle operation's mask into our accumulated mask. Note that
21518 // this shuffle's mask will be the first applied to the input, followed by the
21519 // root mask to get us all the way to the root value arrangement. The reason
21520 // for this order is that we are recursing up the operation chain.
21521 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21522 int RootIdx = i / RootRatio;
21523 if (RootMask[RootIdx] < 0) {
21524 // This is a zero or undef lane, we're done.
21525 Mask.push_back(RootMask[RootIdx]);
21529 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21530 int OpIdx = RootMaskedIdx / OpRatio;
21531 if (OpMask[OpIdx] < 0) {
21532 // The incoming lanes are zero or undef, it doesn't matter which ones we
21534 Mask.push_back(OpMask[OpIdx]);
21538 // Ok, we have non-zero lanes, map them through.
21539 Mask.push_back(OpMask[OpIdx] * OpRatio +
21540 RootMaskedIdx % OpRatio);
21543 // See if we can recurse into the operand to combine more things.
21544 switch (Op.getOpcode()) {
21545 case X86ISD::PSHUFB:
21547 case X86ISD::PSHUFD:
21548 case X86ISD::PSHUFHW:
21549 case X86ISD::PSHUFLW:
21550 if (Op.getOperand(0).hasOneUse() &&
21551 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21552 HasPSHUFB, DAG, DCI, Subtarget))
21556 case X86ISD::UNPCKL:
21557 case X86ISD::UNPCKH:
21558 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21559 // We can't check for single use, we have to check that this shuffle is the only user.
21560 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21561 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21562 HasPSHUFB, DAG, DCI, Subtarget))
21567 // Minor canonicalization of the accumulated shuffle mask to make it easier
21568 // to match below. All this does is detect masks with squential pairs of
21569 // elements, and shrink them to the half-width mask. It does this in a loop
21570 // so it will reduce the size of the mask to the minimal width mask which
21571 // performs an equivalent shuffle.
21572 SmallVector<int, 16> WidenedMask;
21573 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21574 Mask = std::move(WidenedMask);
21575 WidenedMask.clear();
21578 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21582 /// \brief Get the PSHUF-style mask from PSHUF node.
21584 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21585 /// PSHUF-style masks that can be reused with such instructions.
21586 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21587 SmallVector<int, 4> Mask;
21589 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21593 switch (N.getOpcode()) {
21594 case X86ISD::PSHUFD:
21596 case X86ISD::PSHUFLW:
21599 case X86ISD::PSHUFHW:
21600 Mask.erase(Mask.begin(), Mask.begin() + 4);
21601 for (int &M : Mask)
21605 llvm_unreachable("No valid shuffle instruction found!");
21609 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21611 /// We walk up the chain and look for a combinable shuffle, skipping over
21612 /// shuffles that we could hoist this shuffle's transformation past without
21613 /// altering anything.
21615 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21617 TargetLowering::DAGCombinerInfo &DCI) {
21618 assert(N.getOpcode() == X86ISD::PSHUFD &&
21619 "Called with something other than an x86 128-bit half shuffle!");
21622 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21623 // of the shuffles in the chain so that we can form a fresh chain to replace
21625 SmallVector<SDValue, 8> Chain;
21626 SDValue V = N.getOperand(0);
21627 for (; V.hasOneUse(); V = V.getOperand(0)) {
21628 switch (V.getOpcode()) {
21630 return SDValue(); // Nothing combined!
21633 // Skip bitcasts as we always know the type for the target specific
21637 case X86ISD::PSHUFD:
21638 // Found another dword shuffle.
21641 case X86ISD::PSHUFLW:
21642 // Check that the low words (being shuffled) are the identity in the
21643 // dword shuffle, and the high words are self-contained.
21644 if (Mask[0] != 0 || Mask[1] != 1 ||
21645 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21648 Chain.push_back(V);
21651 case X86ISD::PSHUFHW:
21652 // Check that the high words (being shuffled) are the identity in the
21653 // dword shuffle, and the low words are self-contained.
21654 if (Mask[2] != 2 || Mask[3] != 3 ||
21655 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21658 Chain.push_back(V);
21661 case X86ISD::UNPCKL:
21662 case X86ISD::UNPCKH:
21663 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21664 // shuffle into a preceding word shuffle.
21665 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21668 // Search for a half-shuffle which we can combine with.
21669 unsigned CombineOp =
21670 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21671 if (V.getOperand(0) != V.getOperand(1) ||
21672 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21674 Chain.push_back(V);
21675 V = V.getOperand(0);
21677 switch (V.getOpcode()) {
21679 return SDValue(); // Nothing to combine.
21681 case X86ISD::PSHUFLW:
21682 case X86ISD::PSHUFHW:
21683 if (V.getOpcode() == CombineOp)
21686 Chain.push_back(V);
21690 V = V.getOperand(0);
21694 } while (V.hasOneUse());
21697 // Break out of the loop if we break out of the switch.
21701 if (!V.hasOneUse())
21702 // We fell out of the loop without finding a viable combining instruction.
21705 // Merge this node's mask and our incoming mask.
21706 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21707 for (int &M : Mask)
21709 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21710 getV4X86ShuffleImm8ForMask(Mask, DAG));
21712 // Rebuild the chain around this new shuffle.
21713 while (!Chain.empty()) {
21714 SDValue W = Chain.pop_back_val();
21716 if (V.getValueType() != W.getOperand(0).getValueType())
21717 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21719 switch (W.getOpcode()) {
21721 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21723 case X86ISD::UNPCKL:
21724 case X86ISD::UNPCKH:
21725 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21728 case X86ISD::PSHUFD:
21729 case X86ISD::PSHUFLW:
21730 case X86ISD::PSHUFHW:
21731 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21735 if (V.getValueType() != N.getValueType())
21736 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21738 // Return the new chain to replace N.
21742 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21744 /// We walk up the chain, skipping shuffles of the other half and looking
21745 /// through shuffles which switch halves trying to find a shuffle of the same
21746 /// pair of dwords.
21747 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21749 TargetLowering::DAGCombinerInfo &DCI) {
21751 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21752 "Called with something other than an x86 128-bit half shuffle!");
21754 unsigned CombineOpcode = N.getOpcode();
21756 // Walk up a single-use chain looking for a combinable shuffle.
21757 SDValue V = N.getOperand(0);
21758 for (; V.hasOneUse(); V = V.getOperand(0)) {
21759 switch (V.getOpcode()) {
21761 return false; // Nothing combined!
21764 // Skip bitcasts as we always know the type for the target specific
21768 case X86ISD::PSHUFLW:
21769 case X86ISD::PSHUFHW:
21770 if (V.getOpcode() == CombineOpcode)
21773 // Other-half shuffles are no-ops.
21776 // Break out of the loop if we break out of the switch.
21780 if (!V.hasOneUse())
21781 // We fell out of the loop without finding a viable combining instruction.
21784 // Combine away the bottom node as its shuffle will be accumulated into
21785 // a preceding shuffle.
21786 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21788 // Record the old value.
21791 // Merge this node's mask and our incoming mask (adjusted to account for all
21792 // the pshufd instructions encountered).
21793 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21794 for (int &M : Mask)
21796 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21797 getV4X86ShuffleImm8ForMask(Mask, DAG));
21799 // Check that the shuffles didn't cancel each other out. If not, we need to
21800 // combine to the new one.
21802 // Replace the combinable shuffle with the combined one, updating all users
21803 // so that we re-evaluate the chain here.
21804 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21809 /// \brief Try to combine x86 target specific shuffles.
21810 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21811 TargetLowering::DAGCombinerInfo &DCI,
21812 const X86Subtarget *Subtarget) {
21814 MVT VT = N.getSimpleValueType();
21815 SmallVector<int, 4> Mask;
21817 switch (N.getOpcode()) {
21818 case X86ISD::PSHUFD:
21819 case X86ISD::PSHUFLW:
21820 case X86ISD::PSHUFHW:
21821 Mask = getPSHUFShuffleMask(N);
21822 assert(Mask.size() == 4);
21828 // Nuke no-op shuffles that show up after combining.
21829 if (isNoopShuffleMask(Mask))
21830 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21832 // Look for simplifications involving one or two shuffle instructions.
21833 SDValue V = N.getOperand(0);
21834 switch (N.getOpcode()) {
21837 case X86ISD::PSHUFLW:
21838 case X86ISD::PSHUFHW:
21839 assert(VT == MVT::v8i16);
21842 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21843 return SDValue(); // We combined away this shuffle, so we're done.
21845 // See if this reduces to a PSHUFD which is no more expensive and can
21846 // combine with more operations. Note that it has to at least flip the
21847 // dwords as otherwise it would have been removed as a no-op.
21848 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21849 int DMask[] = {0, 1, 2, 3};
21850 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21851 DMask[DOffset + 0] = DOffset + 1;
21852 DMask[DOffset + 1] = DOffset + 0;
21853 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21854 DCI.AddToWorklist(V.getNode());
21855 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21856 getV4X86ShuffleImm8ForMask(DMask, DAG));
21857 DCI.AddToWorklist(V.getNode());
21858 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21861 // Look for shuffle patterns which can be implemented as a single unpack.
21862 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21863 // only works when we have a PSHUFD followed by two half-shuffles.
21864 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21865 (V.getOpcode() == X86ISD::PSHUFLW ||
21866 V.getOpcode() == X86ISD::PSHUFHW) &&
21867 V.getOpcode() != N.getOpcode() &&
21869 SDValue D = V.getOperand(0);
21870 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21871 D = D.getOperand(0);
21872 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21873 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21874 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21875 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21876 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21878 for (int i = 0; i < 4; ++i) {
21879 WordMask[i + NOffset] = Mask[i] + NOffset;
21880 WordMask[i + VOffset] = VMask[i] + VOffset;
21882 // Map the word mask through the DWord mask.
21884 for (int i = 0; i < 8; ++i)
21885 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21886 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21887 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21888 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21889 std::begin(UnpackLoMask)) ||
21890 std::equal(std::begin(MappedMask), std::end(MappedMask),
21891 std::begin(UnpackHiMask))) {
21892 // We can replace all three shuffles with an unpack.
21893 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21894 DCI.AddToWorklist(V.getNode());
21895 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21897 DL, MVT::v8i16, V, V);
21904 case X86ISD::PSHUFD:
21905 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21914 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21916 /// We combine this directly on the abstract vector shuffle nodes so it is
21917 /// easier to generically match. We also insert dummy vector shuffle nodes for
21918 /// the operands which explicitly discard the lanes which are unused by this
21919 /// operation to try to flow through the rest of the combiner the fact that
21920 /// they're unused.
21921 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21923 EVT VT = N->getValueType(0);
21925 // We only handle target-independent shuffles.
21926 // FIXME: It would be easy and harmless to use the target shuffle mask
21927 // extraction tool to support more.
21928 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21931 auto *SVN = cast<ShuffleVectorSDNode>(N);
21932 ArrayRef<int> Mask = SVN->getMask();
21933 SDValue V1 = N->getOperand(0);
21934 SDValue V2 = N->getOperand(1);
21936 // We require the first shuffle operand to be the SUB node, and the second to
21937 // be the ADD node.
21938 // FIXME: We should support the commuted patterns.
21939 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21942 // If there are other uses of these operations we can't fold them.
21943 if (!V1->hasOneUse() || !V2->hasOneUse())
21946 // Ensure that both operations have the same operands. Note that we can
21947 // commute the FADD operands.
21948 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21949 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21950 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21953 // We're looking for blends between FADD and FSUB nodes. We insist on these
21954 // nodes being lined up in a specific expected pattern.
21955 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21956 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21957 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21960 // Only specific types are legal at this point, assert so we notice if and
21961 // when these change.
21962 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21963 VT == MVT::v4f64) &&
21964 "Unknown vector type encountered!");
21966 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21969 /// PerformShuffleCombine - Performs several different shuffle combines.
21970 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21971 TargetLowering::DAGCombinerInfo &DCI,
21972 const X86Subtarget *Subtarget) {
21974 SDValue N0 = N->getOperand(0);
21975 SDValue N1 = N->getOperand(1);
21976 EVT VT = N->getValueType(0);
21978 // Don't create instructions with illegal types after legalize types has run.
21979 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21980 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21983 // If we have legalized the vector types, look for blends of FADD and FSUB
21984 // nodes that we can fuse into an ADDSUB node.
21985 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21986 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21989 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21990 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21991 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21992 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21994 // During Type Legalization, when promoting illegal vector types,
21995 // the backend might introduce new shuffle dag nodes and bitcasts.
21997 // This code performs the following transformation:
21998 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21999 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22001 // We do this only if both the bitcast and the BINOP dag nodes have
22002 // one use. Also, perform this transformation only if the new binary
22003 // operation is legal. This is to avoid introducing dag nodes that
22004 // potentially need to be further expanded (or custom lowered) into a
22005 // less optimal sequence of dag nodes.
22006 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22007 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22008 N0.getOpcode() == ISD::BITCAST) {
22009 SDValue BC0 = N0.getOperand(0);
22010 EVT SVT = BC0.getValueType();
22011 unsigned Opcode = BC0.getOpcode();
22012 unsigned NumElts = VT.getVectorNumElements();
22014 if (BC0.hasOneUse() && SVT.isVector() &&
22015 SVT.getVectorNumElements() * 2 == NumElts &&
22016 TLI.isOperationLegal(Opcode, VT)) {
22017 bool CanFold = false;
22029 unsigned SVTNumElts = SVT.getVectorNumElements();
22030 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22031 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22032 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22033 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22034 CanFold = SVOp->getMaskElt(i) < 0;
22037 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22038 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22039 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22040 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22045 // Only handle 128 wide vector from here on.
22046 if (!VT.is128BitVector())
22049 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22050 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22051 // consecutive, non-overlapping, and in the right order.
22052 SmallVector<SDValue, 16> Elts;
22053 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22054 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22056 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22060 if (isTargetShuffle(N->getOpcode())) {
22062 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22063 if (Shuffle.getNode())
22066 // Try recursively combining arbitrary sequences of x86 shuffle
22067 // instructions into higher-order shuffles. We do this after combining
22068 // specific PSHUF instruction sequences into their minimal form so that we
22069 // can evaluate how many specialized shuffle instructions are involved in
22070 // a particular chain.
22071 SmallVector<int, 1> NonceMask; // Just a placeholder.
22072 NonceMask.push_back(0);
22073 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22074 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22076 return SDValue(); // This routine will use CombineTo to replace N.
22082 /// PerformTruncateCombine - Converts truncate operation to
22083 /// a sequence of vector shuffle operations.
22084 /// It is possible when we truncate 256-bit vector to 128-bit vector
22085 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22086 TargetLowering::DAGCombinerInfo &DCI,
22087 const X86Subtarget *Subtarget) {
22091 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22092 /// specific shuffle of a load can be folded into a single element load.
22093 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22094 /// shuffles have been custom lowered so we need to handle those here.
22095 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22096 TargetLowering::DAGCombinerInfo &DCI) {
22097 if (DCI.isBeforeLegalizeOps())
22100 SDValue InVec = N->getOperand(0);
22101 SDValue EltNo = N->getOperand(1);
22103 if (!isa<ConstantSDNode>(EltNo))
22106 EVT OriginalVT = InVec.getValueType();
22108 if (InVec.getOpcode() == ISD::BITCAST) {
22109 // Don't duplicate a load with other uses.
22110 if (!InVec.hasOneUse())
22112 EVT BCVT = InVec.getOperand(0).getValueType();
22113 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22115 InVec = InVec.getOperand(0);
22118 EVT CurrentVT = InVec.getValueType();
22120 if (!isTargetShuffle(InVec.getOpcode()))
22123 // Don't duplicate a load with other uses.
22124 if (!InVec.hasOneUse())
22127 SmallVector<int, 16> ShuffleMask;
22129 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22130 ShuffleMask, UnaryShuffle))
22133 // Select the input vector, guarding against out of range extract vector.
22134 unsigned NumElems = CurrentVT.getVectorNumElements();
22135 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22136 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22137 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22138 : InVec.getOperand(1);
22140 // If inputs to shuffle are the same for both ops, then allow 2 uses
22141 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22143 if (LdNode.getOpcode() == ISD::BITCAST) {
22144 // Don't duplicate a load with other uses.
22145 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22148 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22149 LdNode = LdNode.getOperand(0);
22152 if (!ISD::isNormalLoad(LdNode.getNode()))
22155 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22157 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22160 EVT EltVT = N->getValueType(0);
22161 // If there's a bitcast before the shuffle, check if the load type and
22162 // alignment is valid.
22163 unsigned Align = LN0->getAlignment();
22164 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22165 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22166 EltVT.getTypeForEVT(*DAG.getContext()));
22168 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22171 // All checks match so transform back to vector_shuffle so that DAG combiner
22172 // can finish the job
22175 // Create shuffle node taking into account the case that its a unary shuffle
22176 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22177 : InVec.getOperand(1);
22178 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22179 InVec.getOperand(0), Shuffle,
22181 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22182 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22186 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22187 /// generation and convert it from being a bunch of shuffles and extracts
22188 /// to a simple store and scalar loads to extract the elements.
22189 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22190 TargetLowering::DAGCombinerInfo &DCI) {
22191 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22192 if (NewOp.getNode())
22195 SDValue InputVector = N->getOperand(0);
22197 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22198 // from mmx to v2i32 has a single usage.
22199 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22200 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22201 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22202 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22203 N->getValueType(0),
22204 InputVector.getNode()->getOperand(0));
22206 // Only operate on vectors of 4 elements, where the alternative shuffling
22207 // gets to be more expensive.
22208 if (InputVector.getValueType() != MVT::v4i32)
22211 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22212 // single use which is a sign-extend or zero-extend, and all elements are
22214 SmallVector<SDNode *, 4> Uses;
22215 unsigned ExtractedElements = 0;
22216 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22217 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22218 if (UI.getUse().getResNo() != InputVector.getResNo())
22221 SDNode *Extract = *UI;
22222 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22225 if (Extract->getValueType(0) != MVT::i32)
22227 if (!Extract->hasOneUse())
22229 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22230 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22232 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22235 // Record which element was extracted.
22236 ExtractedElements |=
22237 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22239 Uses.push_back(Extract);
22242 // If not all the elements were used, this may not be worthwhile.
22243 if (ExtractedElements != 15)
22246 // Ok, we've now decided to do the transformation.
22247 SDLoc dl(InputVector);
22249 // Store the value to a temporary stack slot.
22250 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22251 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22252 MachinePointerInfo(), false, false, 0);
22254 // Replace each use (extract) with a load of the appropriate element.
22255 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22256 UE = Uses.end(); UI != UE; ++UI) {
22257 SDNode *Extract = *UI;
22259 // cOMpute the element's address.
22260 SDValue Idx = Extract->getOperand(1);
22262 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22263 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22264 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22265 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22267 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22268 StackPtr, OffsetVal);
22270 // Load the scalar.
22271 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22272 ScalarAddr, MachinePointerInfo(),
22273 false, false, false, 0);
22275 // Replace the exact with the load.
22276 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22279 // The replacement was made in place; don't return anything.
22283 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22284 static std::pair<unsigned, bool>
22285 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22286 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22287 if (!VT.isVector())
22288 return std::make_pair(0, false);
22290 bool NeedSplit = false;
22291 switch (VT.getSimpleVT().SimpleTy) {
22292 default: return std::make_pair(0, false);
22296 if (!Subtarget->hasAVX2())
22298 if (!Subtarget->hasAVX())
22299 return std::make_pair(0, false);
22304 if (!Subtarget->hasSSE2())
22305 return std::make_pair(0, false);
22308 // SSE2 has only a small subset of the operations.
22309 bool hasUnsigned = Subtarget->hasSSE41() ||
22310 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22311 bool hasSigned = Subtarget->hasSSE41() ||
22312 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22314 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22317 // Check for x CC y ? x : y.
22318 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22319 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22324 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22327 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22330 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22333 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22335 // Check for x CC y ? y : x -- a min/max with reversed arms.
22336 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22337 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22342 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22345 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22348 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22351 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22355 return std::make_pair(Opc, NeedSplit);
22359 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22360 const X86Subtarget *Subtarget) {
22362 SDValue Cond = N->getOperand(0);
22363 SDValue LHS = N->getOperand(1);
22364 SDValue RHS = N->getOperand(2);
22366 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22367 SDValue CondSrc = Cond->getOperand(0);
22368 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22369 Cond = CondSrc->getOperand(0);
22372 MVT VT = N->getSimpleValueType(0);
22373 MVT EltVT = VT.getVectorElementType();
22374 unsigned NumElems = VT.getVectorNumElements();
22375 // There is no blend with immediate in AVX-512.
22376 if (VT.is512BitVector())
22379 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
22381 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
22384 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22387 // A vselect where all conditions and data are constants can be optimized into
22388 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22389 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22390 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22393 unsigned MaskValue = 0;
22394 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22397 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22398 for (unsigned i = 0; i < NumElems; ++i) {
22399 // Be sure we emit undef where we can.
22400 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22401 ShuffleMask[i] = -1;
22403 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22406 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22409 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22411 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22412 TargetLowering::DAGCombinerInfo &DCI,
22413 const X86Subtarget *Subtarget) {
22415 SDValue Cond = N->getOperand(0);
22416 // Get the LHS/RHS of the select.
22417 SDValue LHS = N->getOperand(1);
22418 SDValue RHS = N->getOperand(2);
22419 EVT VT = LHS.getValueType();
22420 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22422 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22423 // instructions match the semantics of the common C idiom x<y?x:y but not
22424 // x<=y?x:y, because of how they handle negative zero (which can be
22425 // ignored in unsafe-math mode).
22426 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22427 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22428 (Subtarget->hasSSE2() ||
22429 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22430 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22432 unsigned Opcode = 0;
22433 // Check for x CC y ? x : y.
22434 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22435 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22439 // Converting this to a min would handle NaNs incorrectly, and swapping
22440 // the operands would cause it to handle comparisons between positive
22441 // and negative zero incorrectly.
22442 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22443 if (!DAG.getTarget().Options.UnsafeFPMath &&
22444 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22446 std::swap(LHS, RHS);
22448 Opcode = X86ISD::FMIN;
22451 // Converting this to a min would handle comparisons between positive
22452 // and negative zero incorrectly.
22453 if (!DAG.getTarget().Options.UnsafeFPMath &&
22454 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22456 Opcode = X86ISD::FMIN;
22459 // Converting this to a min would handle both negative zeros and NaNs
22460 // incorrectly, but we can swap the operands to fix both.
22461 std::swap(LHS, RHS);
22465 Opcode = X86ISD::FMIN;
22469 // Converting this to a max would handle comparisons between positive
22470 // and negative zero incorrectly.
22471 if (!DAG.getTarget().Options.UnsafeFPMath &&
22472 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22474 Opcode = X86ISD::FMAX;
22477 // Converting this to a max would handle NaNs incorrectly, and swapping
22478 // the operands would cause it to handle comparisons between positive
22479 // and negative zero incorrectly.
22480 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22481 if (!DAG.getTarget().Options.UnsafeFPMath &&
22482 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22484 std::swap(LHS, RHS);
22486 Opcode = X86ISD::FMAX;
22489 // Converting this to a max would handle both negative zeros and NaNs
22490 // incorrectly, but we can swap the operands to fix both.
22491 std::swap(LHS, RHS);
22495 Opcode = X86ISD::FMAX;
22498 // Check for x CC y ? y : x -- a min/max with reversed arms.
22499 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22500 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22504 // Converting this to a min would handle comparisons between positive
22505 // and negative zero incorrectly, and swapping the operands would
22506 // cause it to handle NaNs incorrectly.
22507 if (!DAG.getTarget().Options.UnsafeFPMath &&
22508 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22509 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22511 std::swap(LHS, RHS);
22513 Opcode = X86ISD::FMIN;
22516 // Converting this to a min would handle NaNs incorrectly.
22517 if (!DAG.getTarget().Options.UnsafeFPMath &&
22518 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22520 Opcode = X86ISD::FMIN;
22523 // Converting this to a min would handle both negative zeros and NaNs
22524 // incorrectly, but we can swap the operands to fix both.
22525 std::swap(LHS, RHS);
22529 Opcode = X86ISD::FMIN;
22533 // Converting this to a max would handle NaNs incorrectly.
22534 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22536 Opcode = X86ISD::FMAX;
22539 // Converting this to a max would handle comparisons between positive
22540 // and negative zero incorrectly, and swapping the operands would
22541 // cause it to handle NaNs incorrectly.
22542 if (!DAG.getTarget().Options.UnsafeFPMath &&
22543 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22544 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22546 std::swap(LHS, RHS);
22548 Opcode = X86ISD::FMAX;
22551 // Converting this to a max would handle both negative zeros and NaNs
22552 // incorrectly, but we can swap the operands to fix both.
22553 std::swap(LHS, RHS);
22557 Opcode = X86ISD::FMAX;
22563 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22566 EVT CondVT = Cond.getValueType();
22567 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22568 CondVT.getVectorElementType() == MVT::i1) {
22569 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22570 // lowering on KNL. In this case we convert it to
22571 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22572 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22573 // Since SKX these selects have a proper lowering.
22574 EVT OpVT = LHS.getValueType();
22575 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22576 (OpVT.getVectorElementType() == MVT::i8 ||
22577 OpVT.getVectorElementType() == MVT::i16) &&
22578 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22579 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22580 DCI.AddToWorklist(Cond.getNode());
22581 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22584 // If this is a select between two integer constants, try to do some
22586 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22587 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22588 // Don't do this for crazy integer types.
22589 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22590 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22591 // so that TrueC (the true value) is larger than FalseC.
22592 bool NeedsCondInvert = false;
22594 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22595 // Efficiently invertible.
22596 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22597 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22598 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22599 NeedsCondInvert = true;
22600 std::swap(TrueC, FalseC);
22603 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22604 if (FalseC->getAPIntValue() == 0 &&
22605 TrueC->getAPIntValue().isPowerOf2()) {
22606 if (NeedsCondInvert) // Invert the condition if needed.
22607 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22608 DAG.getConstant(1, Cond.getValueType()));
22610 // Zero extend the condition if needed.
22611 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22613 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22614 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22615 DAG.getConstant(ShAmt, MVT::i8));
22618 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22619 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22620 if (NeedsCondInvert) // Invert the condition if needed.
22621 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22622 DAG.getConstant(1, Cond.getValueType()));
22624 // Zero extend the condition if needed.
22625 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22626 FalseC->getValueType(0), Cond);
22627 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22628 SDValue(FalseC, 0));
22631 // Optimize cases that will turn into an LEA instruction. This requires
22632 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22633 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22634 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22635 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22637 bool isFastMultiplier = false;
22639 switch ((unsigned char)Diff) {
22641 case 1: // result = add base, cond
22642 case 2: // result = lea base( , cond*2)
22643 case 3: // result = lea base(cond, cond*2)
22644 case 4: // result = lea base( , cond*4)
22645 case 5: // result = lea base(cond, cond*4)
22646 case 8: // result = lea base( , cond*8)
22647 case 9: // result = lea base(cond, cond*8)
22648 isFastMultiplier = true;
22653 if (isFastMultiplier) {
22654 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22655 if (NeedsCondInvert) // Invert the condition if needed.
22656 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22657 DAG.getConstant(1, Cond.getValueType()));
22659 // Zero extend the condition if needed.
22660 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22662 // Scale the condition by the difference.
22664 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22665 DAG.getConstant(Diff, Cond.getValueType()));
22667 // Add the base if non-zero.
22668 if (FalseC->getAPIntValue() != 0)
22669 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22670 SDValue(FalseC, 0));
22677 // Canonicalize max and min:
22678 // (x > y) ? x : y -> (x >= y) ? x : y
22679 // (x < y) ? x : y -> (x <= y) ? x : y
22680 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22681 // the need for an extra compare
22682 // against zero. e.g.
22683 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22685 // testl %edi, %edi
22687 // cmovgl %edi, %eax
22691 // cmovsl %eax, %edi
22692 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22693 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22694 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22695 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22700 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22701 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22702 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22703 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22708 // Early exit check
22709 if (!TLI.isTypeLegal(VT))
22712 // Match VSELECTs into subs with unsigned saturation.
22713 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22714 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22715 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22716 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22717 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22719 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22720 // left side invert the predicate to simplify logic below.
22722 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22724 CC = ISD::getSetCCInverse(CC, true);
22725 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22729 if (Other.getNode() && Other->getNumOperands() == 2 &&
22730 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22731 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22732 SDValue CondRHS = Cond->getOperand(1);
22734 // Look for a general sub with unsigned saturation first.
22735 // x >= y ? x-y : 0 --> subus x, y
22736 // x > y ? x-y : 0 --> subus x, y
22737 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22738 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22739 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22741 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22742 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22743 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22744 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22745 // If the RHS is a constant we have to reverse the const
22746 // canonicalization.
22747 // x > C-1 ? x+-C : 0 --> subus x, C
22748 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22749 CondRHSConst->getAPIntValue() ==
22750 (-OpRHSConst->getAPIntValue() - 1))
22751 return DAG.getNode(
22752 X86ISD::SUBUS, DL, VT, OpLHS,
22753 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22755 // Another special case: If C was a sign bit, the sub has been
22756 // canonicalized into a xor.
22757 // FIXME: Would it be better to use computeKnownBits to determine
22758 // whether it's safe to decanonicalize the xor?
22759 // x s< 0 ? x^C : 0 --> subus x, C
22760 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22761 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22762 OpRHSConst->getAPIntValue().isSignBit())
22763 // Note that we have to rebuild the RHS constant here to ensure we
22764 // don't rely on particular values of undef lanes.
22765 return DAG.getNode(
22766 X86ISD::SUBUS, DL, VT, OpLHS,
22767 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22772 // Try to match a min/max vector operation.
22773 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22774 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22775 unsigned Opc = ret.first;
22776 bool NeedSplit = ret.second;
22778 if (Opc && NeedSplit) {
22779 unsigned NumElems = VT.getVectorNumElements();
22780 // Extract the LHS vectors
22781 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22782 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22784 // Extract the RHS vectors
22785 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22786 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22788 // Create min/max for each subvector
22789 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22790 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22792 // Merge the result
22793 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22795 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22798 // Simplify vector selection if condition value type matches vselect
22800 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22801 assert(Cond.getValueType().isVector() &&
22802 "vector select expects a vector selector!");
22804 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22805 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22807 // Try invert the condition if true value is not all 1s and false value
22809 if (!TValIsAllOnes && !FValIsAllZeros &&
22810 // Check if the selector will be produced by CMPP*/PCMP*
22811 Cond.getOpcode() == ISD::SETCC &&
22812 // Check if SETCC has already been promoted
22813 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
22814 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22815 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22817 if (TValIsAllZeros || FValIsAllOnes) {
22818 SDValue CC = Cond.getOperand(2);
22819 ISD::CondCode NewCC =
22820 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22821 Cond.getOperand(0).getValueType().isInteger());
22822 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22823 std::swap(LHS, RHS);
22824 TValIsAllOnes = FValIsAllOnes;
22825 FValIsAllZeros = TValIsAllZeros;
22829 if (TValIsAllOnes || FValIsAllZeros) {
22832 if (TValIsAllOnes && FValIsAllZeros)
22834 else if (TValIsAllOnes)
22835 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22836 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22837 else if (FValIsAllZeros)
22838 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22839 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22841 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22845 // Try to fold this VSELECT into a MOVSS/MOVSD
22846 if (N->getOpcode() == ISD::VSELECT &&
22847 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22848 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22849 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22850 bool CanFold = false;
22851 unsigned NumElems = Cond.getNumOperands();
22855 if (isZero(Cond.getOperand(0))) {
22858 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22859 // fold (vselect <0,-1> -> (movsd A, B)
22860 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22861 CanFold = isAllOnes(Cond.getOperand(i));
22862 } else if (isAllOnes(Cond.getOperand(0))) {
22866 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22867 // fold (vselect <-1,0> -> (movsd B, A)
22868 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22869 CanFold = isZero(Cond.getOperand(i));
22873 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22874 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22875 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22878 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22879 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22880 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22881 // (v2i64 (bitcast B)))))
22883 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22884 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22885 // (v2f64 (bitcast B)))))
22887 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22888 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22889 // (v2i64 (bitcast A)))))
22891 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22892 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22893 // (v2f64 (bitcast A)))))
22895 CanFold = (isZero(Cond.getOperand(0)) &&
22896 isZero(Cond.getOperand(1)) &&
22897 isAllOnes(Cond.getOperand(2)) &&
22898 isAllOnes(Cond.getOperand(3)));
22900 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22901 isAllOnes(Cond.getOperand(1)) &&
22902 isZero(Cond.getOperand(2)) &&
22903 isZero(Cond.getOperand(3))) {
22905 std::swap(LHS, RHS);
22909 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22910 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22911 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22912 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22914 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22920 // If we know that this node is legal then we know that it is going to be
22921 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22922 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22923 // to simplify previous instructions.
22924 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22925 !DCI.isBeforeLegalize() &&
22926 // We explicitly check against v8i16 and v16i16 because, although
22927 // they're marked as Custom, they might only be legal when Cond is a
22928 // build_vector of constants. This will be taken care in a later
22930 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22931 VT != MVT::v8i16) &&
22932 // Don't optimize vector of constants. Those are handled by
22933 // the generic code and all the bits must be properly set for
22934 // the generic optimizer.
22935 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
22936 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22938 // Don't optimize vector selects that map to mask-registers.
22942 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22943 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22945 APInt KnownZero, KnownOne;
22946 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22947 DCI.isBeforeLegalizeOps());
22948 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22949 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22951 // If we changed the computation somewhere in the DAG, this change
22952 // will affect all users of Cond.
22953 // Make sure it is fine and update all the nodes so that we do not
22954 // use the generic VSELECT anymore. Otherwise, we may perform
22955 // wrong optimizations as we messed up with the actual expectation
22956 // for the vector boolean values.
22957 if (Cond != TLO.Old) {
22958 // Check all uses of that condition operand to check whether it will be
22959 // consumed by non-BLEND instructions, which may depend on all bits are
22961 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22963 if (I->getOpcode() != ISD::VSELECT)
22964 // TODO: Add other opcodes eventually lowered into BLEND.
22967 // Update all the users of the condition, before committing the change,
22968 // so that the VSELECT optimizations that expect the correct vector
22969 // boolean value will not be triggered.
22970 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22972 DAG.ReplaceAllUsesOfValueWith(
22974 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22975 Cond, I->getOperand(1), I->getOperand(2)));
22976 DCI.CommitTargetLoweringOpt(TLO);
22979 // At this point, only Cond is changed. Change the condition
22980 // just for N to keep the opportunity to optimize all other
22981 // users their own way.
22982 DAG.ReplaceAllUsesOfValueWith(
22984 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22985 TLO.New, N->getOperand(1), N->getOperand(2)));
22990 // We should generate an X86ISD::BLENDI from a vselect if its argument
22991 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22992 // constants. This specific pattern gets generated when we split a
22993 // selector for a 512 bit vector in a machine without AVX512 (but with
22994 // 256-bit vectors), during legalization:
22996 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22998 // Iff we find this pattern and the build_vectors are built from
22999 // constants, we translate the vselect into a shuffle_vector that we
23000 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23001 if ((N->getOpcode() == ISD::VSELECT ||
23002 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23003 !DCI.isBeforeLegalize()) {
23004 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23005 if (Shuffle.getNode())
23012 // Check whether a boolean test is testing a boolean value generated by
23013 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23016 // Simplify the following patterns:
23017 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23018 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23019 // to (Op EFLAGS Cond)
23021 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23022 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23023 // to (Op EFLAGS !Cond)
23025 // where Op could be BRCOND or CMOV.
23027 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23028 // Quit if not CMP and SUB with its value result used.
23029 if (Cmp.getOpcode() != X86ISD::CMP &&
23030 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23033 // Quit if not used as a boolean value.
23034 if (CC != X86::COND_E && CC != X86::COND_NE)
23037 // Check CMP operands. One of them should be 0 or 1 and the other should be
23038 // an SetCC or extended from it.
23039 SDValue Op1 = Cmp.getOperand(0);
23040 SDValue Op2 = Cmp.getOperand(1);
23043 const ConstantSDNode* C = nullptr;
23044 bool needOppositeCond = (CC == X86::COND_E);
23045 bool checkAgainstTrue = false; // Is it a comparison against 1?
23047 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23049 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23051 else // Quit if all operands are not constants.
23054 if (C->getZExtValue() == 1) {
23055 needOppositeCond = !needOppositeCond;
23056 checkAgainstTrue = true;
23057 } else if (C->getZExtValue() != 0)
23058 // Quit if the constant is neither 0 or 1.
23061 bool truncatedToBoolWithAnd = false;
23062 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23063 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23064 SetCC.getOpcode() == ISD::TRUNCATE ||
23065 SetCC.getOpcode() == ISD::AND) {
23066 if (SetCC.getOpcode() == ISD::AND) {
23068 ConstantSDNode *CS;
23069 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23070 CS->getZExtValue() == 1)
23072 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23073 CS->getZExtValue() == 1)
23077 SetCC = SetCC.getOperand(OpIdx);
23078 truncatedToBoolWithAnd = true;
23080 SetCC = SetCC.getOperand(0);
23083 switch (SetCC.getOpcode()) {
23084 case X86ISD::SETCC_CARRY:
23085 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23086 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23087 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23088 // truncated to i1 using 'and'.
23089 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23091 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23092 "Invalid use of SETCC_CARRY!");
23094 case X86ISD::SETCC:
23095 // Set the condition code or opposite one if necessary.
23096 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23097 if (needOppositeCond)
23098 CC = X86::GetOppositeBranchCondition(CC);
23099 return SetCC.getOperand(1);
23100 case X86ISD::CMOV: {
23101 // Check whether false/true value has canonical one, i.e. 0 or 1.
23102 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23103 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23104 // Quit if true value is not a constant.
23107 // Quit if false value is not a constant.
23109 SDValue Op = SetCC.getOperand(0);
23110 // Skip 'zext' or 'trunc' node.
23111 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23112 Op.getOpcode() == ISD::TRUNCATE)
23113 Op = Op.getOperand(0);
23114 // A special case for rdrand/rdseed, where 0 is set if false cond is
23116 if ((Op.getOpcode() != X86ISD::RDRAND &&
23117 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23120 // Quit if false value is not the constant 0 or 1.
23121 bool FValIsFalse = true;
23122 if (FVal && FVal->getZExtValue() != 0) {
23123 if (FVal->getZExtValue() != 1)
23125 // If FVal is 1, opposite cond is needed.
23126 needOppositeCond = !needOppositeCond;
23127 FValIsFalse = false;
23129 // Quit if TVal is not the constant opposite of FVal.
23130 if (FValIsFalse && TVal->getZExtValue() != 1)
23132 if (!FValIsFalse && TVal->getZExtValue() != 0)
23134 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23135 if (needOppositeCond)
23136 CC = X86::GetOppositeBranchCondition(CC);
23137 return SetCC.getOperand(3);
23144 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23145 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23146 TargetLowering::DAGCombinerInfo &DCI,
23147 const X86Subtarget *Subtarget) {
23150 // If the flag operand isn't dead, don't touch this CMOV.
23151 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23154 SDValue FalseOp = N->getOperand(0);
23155 SDValue TrueOp = N->getOperand(1);
23156 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23157 SDValue Cond = N->getOperand(3);
23159 if (CC == X86::COND_E || CC == X86::COND_NE) {
23160 switch (Cond.getOpcode()) {
23164 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23165 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23166 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23172 Flags = checkBoolTestSetCCCombine(Cond, CC);
23173 if (Flags.getNode() &&
23174 // Extra check as FCMOV only supports a subset of X86 cond.
23175 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23176 SDValue Ops[] = { FalseOp, TrueOp,
23177 DAG.getConstant(CC, MVT::i8), Flags };
23178 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23181 // If this is a select between two integer constants, try to do some
23182 // optimizations. Note that the operands are ordered the opposite of SELECT
23184 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23185 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23186 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23187 // larger than FalseC (the false value).
23188 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23189 CC = X86::GetOppositeBranchCondition(CC);
23190 std::swap(TrueC, FalseC);
23191 std::swap(TrueOp, FalseOp);
23194 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23195 // This is efficient for any integer data type (including i8/i16) and
23197 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23198 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23199 DAG.getConstant(CC, MVT::i8), Cond);
23201 // Zero extend the condition if needed.
23202 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23204 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23205 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23206 DAG.getConstant(ShAmt, MVT::i8));
23207 if (N->getNumValues() == 2) // Dead flag value?
23208 return DCI.CombineTo(N, Cond, SDValue());
23212 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23213 // for any integer data type, including i8/i16.
23214 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23215 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23216 DAG.getConstant(CC, MVT::i8), Cond);
23218 // Zero extend the condition if needed.
23219 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23220 FalseC->getValueType(0), Cond);
23221 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23222 SDValue(FalseC, 0));
23224 if (N->getNumValues() == 2) // Dead flag value?
23225 return DCI.CombineTo(N, Cond, SDValue());
23229 // Optimize cases that will turn into an LEA instruction. This requires
23230 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23231 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23232 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23233 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23235 bool isFastMultiplier = false;
23237 switch ((unsigned char)Diff) {
23239 case 1: // result = add base, cond
23240 case 2: // result = lea base( , cond*2)
23241 case 3: // result = lea base(cond, cond*2)
23242 case 4: // result = lea base( , cond*4)
23243 case 5: // result = lea base(cond, cond*4)
23244 case 8: // result = lea base( , cond*8)
23245 case 9: // result = lea base(cond, cond*8)
23246 isFastMultiplier = true;
23251 if (isFastMultiplier) {
23252 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23253 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23254 DAG.getConstant(CC, MVT::i8), Cond);
23255 // Zero extend the condition if needed.
23256 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23258 // Scale the condition by the difference.
23260 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23261 DAG.getConstant(Diff, Cond.getValueType()));
23263 // Add the base if non-zero.
23264 if (FalseC->getAPIntValue() != 0)
23265 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23266 SDValue(FalseC, 0));
23267 if (N->getNumValues() == 2) // Dead flag value?
23268 return DCI.CombineTo(N, Cond, SDValue());
23275 // Handle these cases:
23276 // (select (x != c), e, c) -> select (x != c), e, x),
23277 // (select (x == c), c, e) -> select (x == c), x, e)
23278 // where the c is an integer constant, and the "select" is the combination
23279 // of CMOV and CMP.
23281 // The rationale for this change is that the conditional-move from a constant
23282 // needs two instructions, however, conditional-move from a register needs
23283 // only one instruction.
23285 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23286 // some instruction-combining opportunities. This opt needs to be
23287 // postponed as late as possible.
23289 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23290 // the DCI.xxxx conditions are provided to postpone the optimization as
23291 // late as possible.
23293 ConstantSDNode *CmpAgainst = nullptr;
23294 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23295 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23296 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23298 if (CC == X86::COND_NE &&
23299 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23300 CC = X86::GetOppositeBranchCondition(CC);
23301 std::swap(TrueOp, FalseOp);
23304 if (CC == X86::COND_E &&
23305 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23306 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23307 DAG.getConstant(CC, MVT::i8), Cond };
23308 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23316 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23317 const X86Subtarget *Subtarget) {
23318 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23320 default: return SDValue();
23321 // SSE/AVX/AVX2 blend intrinsics.
23322 case Intrinsic::x86_avx2_pblendvb:
23323 case Intrinsic::x86_avx2_pblendw:
23324 case Intrinsic::x86_avx2_pblendd_128:
23325 case Intrinsic::x86_avx2_pblendd_256:
23326 // Don't try to simplify this intrinsic if we don't have AVX2.
23327 if (!Subtarget->hasAVX2())
23330 case Intrinsic::x86_avx_blend_pd_256:
23331 case Intrinsic::x86_avx_blend_ps_256:
23332 case Intrinsic::x86_avx_blendv_pd_256:
23333 case Intrinsic::x86_avx_blendv_ps_256:
23334 // Don't try to simplify this intrinsic if we don't have AVX.
23335 if (!Subtarget->hasAVX())
23338 case Intrinsic::x86_sse41_pblendw:
23339 case Intrinsic::x86_sse41_blendpd:
23340 case Intrinsic::x86_sse41_blendps:
23341 case Intrinsic::x86_sse41_blendvps:
23342 case Intrinsic::x86_sse41_blendvpd:
23343 case Intrinsic::x86_sse41_pblendvb: {
23344 SDValue Op0 = N->getOperand(1);
23345 SDValue Op1 = N->getOperand(2);
23346 SDValue Mask = N->getOperand(3);
23348 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23349 if (!Subtarget->hasSSE41())
23352 // fold (blend A, A, Mask) -> A
23355 // fold (blend A, B, allZeros) -> A
23356 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23358 // fold (blend A, B, allOnes) -> B
23359 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23362 // Simplify the case where the mask is a constant i32 value.
23363 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23364 if (C->isNullValue())
23366 if (C->isAllOnesValue())
23373 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23374 case Intrinsic::x86_sse2_psrai_w:
23375 case Intrinsic::x86_sse2_psrai_d:
23376 case Intrinsic::x86_avx2_psrai_w:
23377 case Intrinsic::x86_avx2_psrai_d:
23378 case Intrinsic::x86_sse2_psra_w:
23379 case Intrinsic::x86_sse2_psra_d:
23380 case Intrinsic::x86_avx2_psra_w:
23381 case Intrinsic::x86_avx2_psra_d: {
23382 SDValue Op0 = N->getOperand(1);
23383 SDValue Op1 = N->getOperand(2);
23384 EVT VT = Op0.getValueType();
23385 assert(VT.isVector() && "Expected a vector type!");
23387 if (isa<BuildVectorSDNode>(Op1))
23388 Op1 = Op1.getOperand(0);
23390 if (!isa<ConstantSDNode>(Op1))
23393 EVT SVT = VT.getVectorElementType();
23394 unsigned SVTBits = SVT.getSizeInBits();
23396 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23397 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23398 uint64_t ShAmt = C.getZExtValue();
23400 // Don't try to convert this shift into a ISD::SRA if the shift
23401 // count is bigger than or equal to the element size.
23402 if (ShAmt >= SVTBits)
23405 // Trivial case: if the shift count is zero, then fold this
23406 // into the first operand.
23410 // Replace this packed shift intrinsic with a target independent
23412 SDValue Splat = DAG.getConstant(C, VT);
23413 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23418 /// PerformMulCombine - Optimize a single multiply with constant into two
23419 /// in order to implement it with two cheaper instructions, e.g.
23420 /// LEA + SHL, LEA + LEA.
23421 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23422 TargetLowering::DAGCombinerInfo &DCI) {
23423 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23426 EVT VT = N->getValueType(0);
23427 if (VT != MVT::i64)
23430 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23433 uint64_t MulAmt = C->getZExtValue();
23434 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23437 uint64_t MulAmt1 = 0;
23438 uint64_t MulAmt2 = 0;
23439 if ((MulAmt % 9) == 0) {
23441 MulAmt2 = MulAmt / 9;
23442 } else if ((MulAmt % 5) == 0) {
23444 MulAmt2 = MulAmt / 5;
23445 } else if ((MulAmt % 3) == 0) {
23447 MulAmt2 = MulAmt / 3;
23450 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23453 if (isPowerOf2_64(MulAmt2) &&
23454 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23455 // If second multiplifer is pow2, issue it first. We want the multiply by
23456 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23458 std::swap(MulAmt1, MulAmt2);
23461 if (isPowerOf2_64(MulAmt1))
23462 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23463 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23465 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23466 DAG.getConstant(MulAmt1, VT));
23468 if (isPowerOf2_64(MulAmt2))
23469 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23470 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23472 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23473 DAG.getConstant(MulAmt2, VT));
23475 // Do not add new nodes to DAG combiner worklist.
23476 DCI.CombineTo(N, NewMul, false);
23481 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23482 SDValue N0 = N->getOperand(0);
23483 SDValue N1 = N->getOperand(1);
23484 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23485 EVT VT = N0.getValueType();
23487 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23488 // since the result of setcc_c is all zero's or all ones.
23489 if (VT.isInteger() && !VT.isVector() &&
23490 N1C && N0.getOpcode() == ISD::AND &&
23491 N0.getOperand(1).getOpcode() == ISD::Constant) {
23492 SDValue N00 = N0.getOperand(0);
23493 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23494 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23495 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23496 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23497 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23498 APInt ShAmt = N1C->getAPIntValue();
23499 Mask = Mask.shl(ShAmt);
23501 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23502 N00, DAG.getConstant(Mask, VT));
23506 // Hardware support for vector shifts is sparse which makes us scalarize the
23507 // vector operations in many cases. Also, on sandybridge ADD is faster than
23509 // (shl V, 1) -> add V,V
23510 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23511 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23512 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23513 // We shift all of the values by one. In many cases we do not have
23514 // hardware support for this operation. This is better expressed as an ADD
23516 if (N1SplatC->getZExtValue() == 1)
23517 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23523 /// \brief Returns a vector of 0s if the node in input is a vector logical
23524 /// shift by a constant amount which is known to be bigger than or equal
23525 /// to the vector element size in bits.
23526 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23527 const X86Subtarget *Subtarget) {
23528 EVT VT = N->getValueType(0);
23530 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23531 (!Subtarget->hasInt256() ||
23532 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23535 SDValue Amt = N->getOperand(1);
23537 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23538 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23539 APInt ShiftAmt = AmtSplat->getAPIntValue();
23540 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23542 // SSE2/AVX2 logical shifts always return a vector of 0s
23543 // if the shift amount is bigger than or equal to
23544 // the element size. The constant shift amount will be
23545 // encoded as a 8-bit immediate.
23546 if (ShiftAmt.trunc(8).uge(MaxAmount))
23547 return getZeroVector(VT, Subtarget, DAG, DL);
23553 /// PerformShiftCombine - Combine shifts.
23554 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23555 TargetLowering::DAGCombinerInfo &DCI,
23556 const X86Subtarget *Subtarget) {
23557 if (N->getOpcode() == ISD::SHL) {
23558 SDValue V = PerformSHLCombine(N, DAG);
23559 if (V.getNode()) return V;
23562 if (N->getOpcode() != ISD::SRA) {
23563 // Try to fold this logical shift into a zero vector.
23564 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23565 if (V.getNode()) return V;
23571 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23572 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23573 // and friends. Likewise for OR -> CMPNEQSS.
23574 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23575 TargetLowering::DAGCombinerInfo &DCI,
23576 const X86Subtarget *Subtarget) {
23579 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23580 // we're requiring SSE2 for both.
23581 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23582 SDValue N0 = N->getOperand(0);
23583 SDValue N1 = N->getOperand(1);
23584 SDValue CMP0 = N0->getOperand(1);
23585 SDValue CMP1 = N1->getOperand(1);
23588 // The SETCCs should both refer to the same CMP.
23589 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23592 SDValue CMP00 = CMP0->getOperand(0);
23593 SDValue CMP01 = CMP0->getOperand(1);
23594 EVT VT = CMP00.getValueType();
23596 if (VT == MVT::f32 || VT == MVT::f64) {
23597 bool ExpectingFlags = false;
23598 // Check for any users that want flags:
23599 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23600 !ExpectingFlags && UI != UE; ++UI)
23601 switch (UI->getOpcode()) {
23606 ExpectingFlags = true;
23608 case ISD::CopyToReg:
23609 case ISD::SIGN_EXTEND:
23610 case ISD::ZERO_EXTEND:
23611 case ISD::ANY_EXTEND:
23615 if (!ExpectingFlags) {
23616 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23617 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23619 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23620 X86::CondCode tmp = cc0;
23625 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23626 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23627 // FIXME: need symbolic constants for these magic numbers.
23628 // See X86ATTInstPrinter.cpp:printSSECC().
23629 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23630 if (Subtarget->hasAVX512()) {
23631 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23632 CMP01, DAG.getConstant(x86cc, MVT::i8));
23633 if (N->getValueType(0) != MVT::i1)
23634 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23638 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23639 CMP00.getValueType(), CMP00, CMP01,
23640 DAG.getConstant(x86cc, MVT::i8));
23642 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23643 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23645 if (is64BitFP && !Subtarget->is64Bit()) {
23646 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23647 // 64-bit integer, since that's not a legal type. Since
23648 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23649 // bits, but can do this little dance to extract the lowest 32 bits
23650 // and work with those going forward.
23651 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23653 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23655 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23656 Vector32, DAG.getIntPtrConstant(0));
23660 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23661 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23662 DAG.getConstant(1, IntVT));
23663 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23664 return OneBitOfTruth;
23672 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23673 /// so it can be folded inside ANDNP.
23674 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23675 EVT VT = N->getValueType(0);
23677 // Match direct AllOnes for 128 and 256-bit vectors
23678 if (ISD::isBuildVectorAllOnes(N))
23681 // Look through a bit convert.
23682 if (N->getOpcode() == ISD::BITCAST)
23683 N = N->getOperand(0).getNode();
23685 // Sometimes the operand may come from a insert_subvector building a 256-bit
23687 if (VT.is256BitVector() &&
23688 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23689 SDValue V1 = N->getOperand(0);
23690 SDValue V2 = N->getOperand(1);
23692 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23693 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23694 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23695 ISD::isBuildVectorAllOnes(V2.getNode()))
23702 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23703 // register. In most cases we actually compare or select YMM-sized registers
23704 // and mixing the two types creates horrible code. This method optimizes
23705 // some of the transition sequences.
23706 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23707 TargetLowering::DAGCombinerInfo &DCI,
23708 const X86Subtarget *Subtarget) {
23709 EVT VT = N->getValueType(0);
23710 if (!VT.is256BitVector())
23713 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23714 N->getOpcode() == ISD::ZERO_EXTEND ||
23715 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23717 SDValue Narrow = N->getOperand(0);
23718 EVT NarrowVT = Narrow->getValueType(0);
23719 if (!NarrowVT.is128BitVector())
23722 if (Narrow->getOpcode() != ISD::XOR &&
23723 Narrow->getOpcode() != ISD::AND &&
23724 Narrow->getOpcode() != ISD::OR)
23727 SDValue N0 = Narrow->getOperand(0);
23728 SDValue N1 = Narrow->getOperand(1);
23731 // The Left side has to be a trunc.
23732 if (N0.getOpcode() != ISD::TRUNCATE)
23735 // The type of the truncated inputs.
23736 EVT WideVT = N0->getOperand(0)->getValueType(0);
23740 // The right side has to be a 'trunc' or a constant vector.
23741 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23742 ConstantSDNode *RHSConstSplat = nullptr;
23743 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23744 RHSConstSplat = RHSBV->getConstantSplatNode();
23745 if (!RHSTrunc && !RHSConstSplat)
23748 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23750 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23753 // Set N0 and N1 to hold the inputs to the new wide operation.
23754 N0 = N0->getOperand(0);
23755 if (RHSConstSplat) {
23756 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23757 SDValue(RHSConstSplat, 0));
23758 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23759 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23760 } else if (RHSTrunc) {
23761 N1 = N1->getOperand(0);
23764 // Generate the wide operation.
23765 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23766 unsigned Opcode = N->getOpcode();
23768 case ISD::ANY_EXTEND:
23770 case ISD::ZERO_EXTEND: {
23771 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23772 APInt Mask = APInt::getAllOnesValue(InBits);
23773 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23774 return DAG.getNode(ISD::AND, DL, VT,
23775 Op, DAG.getConstant(Mask, VT));
23777 case ISD::SIGN_EXTEND:
23778 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23779 Op, DAG.getValueType(NarrowVT));
23781 llvm_unreachable("Unexpected opcode");
23785 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23786 TargetLowering::DAGCombinerInfo &DCI,
23787 const X86Subtarget *Subtarget) {
23788 EVT VT = N->getValueType(0);
23789 if (DCI.isBeforeLegalizeOps())
23792 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23796 // Create BEXTR instructions
23797 // BEXTR is ((X >> imm) & (2**size-1))
23798 if (VT == MVT::i32 || VT == MVT::i64) {
23799 SDValue N0 = N->getOperand(0);
23800 SDValue N1 = N->getOperand(1);
23803 // Check for BEXTR.
23804 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23805 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23806 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23807 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23808 if (MaskNode && ShiftNode) {
23809 uint64_t Mask = MaskNode->getZExtValue();
23810 uint64_t Shift = ShiftNode->getZExtValue();
23811 if (isMask_64(Mask)) {
23812 uint64_t MaskSize = CountPopulation_64(Mask);
23813 if (Shift + MaskSize <= VT.getSizeInBits())
23814 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23815 DAG.getConstant(Shift | (MaskSize << 8), VT));
23823 // Want to form ANDNP nodes:
23824 // 1) In the hopes of then easily combining them with OR and AND nodes
23825 // to form PBLEND/PSIGN.
23826 // 2) To match ANDN packed intrinsics
23827 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23830 SDValue N0 = N->getOperand(0);
23831 SDValue N1 = N->getOperand(1);
23834 // Check LHS for vnot
23835 if (N0.getOpcode() == ISD::XOR &&
23836 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23837 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23838 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23840 // Check RHS for vnot
23841 if (N1.getOpcode() == ISD::XOR &&
23842 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23843 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23844 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23849 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23850 TargetLowering::DAGCombinerInfo &DCI,
23851 const X86Subtarget *Subtarget) {
23852 if (DCI.isBeforeLegalizeOps())
23855 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23859 SDValue N0 = N->getOperand(0);
23860 SDValue N1 = N->getOperand(1);
23861 EVT VT = N->getValueType(0);
23863 // look for psign/blend
23864 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23865 if (!Subtarget->hasSSSE3() ||
23866 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23869 // Canonicalize pandn to RHS
23870 if (N0.getOpcode() == X86ISD::ANDNP)
23872 // or (and (m, y), (pandn m, x))
23873 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23874 SDValue Mask = N1.getOperand(0);
23875 SDValue X = N1.getOperand(1);
23877 if (N0.getOperand(0) == Mask)
23878 Y = N0.getOperand(1);
23879 if (N0.getOperand(1) == Mask)
23880 Y = N0.getOperand(0);
23882 // Check to see if the mask appeared in both the AND and ANDNP and
23886 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23887 // Look through mask bitcast.
23888 if (Mask.getOpcode() == ISD::BITCAST)
23889 Mask = Mask.getOperand(0);
23890 if (X.getOpcode() == ISD::BITCAST)
23891 X = X.getOperand(0);
23892 if (Y.getOpcode() == ISD::BITCAST)
23893 Y = Y.getOperand(0);
23895 EVT MaskVT = Mask.getValueType();
23897 // Validate that the Mask operand is a vector sra node.
23898 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23899 // there is no psrai.b
23900 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23901 unsigned SraAmt = ~0;
23902 if (Mask.getOpcode() == ISD::SRA) {
23903 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23904 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23905 SraAmt = AmtConst->getZExtValue();
23906 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23907 SDValue SraC = Mask.getOperand(1);
23908 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23910 if ((SraAmt + 1) != EltBits)
23915 // Now we know we at least have a plendvb with the mask val. See if
23916 // we can form a psignb/w/d.
23917 // psign = x.type == y.type == mask.type && y = sub(0, x);
23918 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23919 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23920 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23921 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23922 "Unsupported VT for PSIGN");
23923 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23924 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23926 // PBLENDVB only available on SSE 4.1
23927 if (!Subtarget->hasSSE41())
23930 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23932 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23933 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23934 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23935 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23936 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23940 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23943 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23944 MachineFunction &MF = DAG.getMachineFunction();
23945 bool OptForSize = MF.getFunction()->getAttributes().
23946 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23948 // SHLD/SHRD instructions have lower register pressure, but on some
23949 // platforms they have higher latency than the equivalent
23950 // series of shifts/or that would otherwise be generated.
23951 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23952 // have higher latencies and we are not optimizing for size.
23953 if (!OptForSize && Subtarget->isSHLDSlow())
23956 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23958 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23960 if (!N0.hasOneUse() || !N1.hasOneUse())
23963 SDValue ShAmt0 = N0.getOperand(1);
23964 if (ShAmt0.getValueType() != MVT::i8)
23966 SDValue ShAmt1 = N1.getOperand(1);
23967 if (ShAmt1.getValueType() != MVT::i8)
23969 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23970 ShAmt0 = ShAmt0.getOperand(0);
23971 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23972 ShAmt1 = ShAmt1.getOperand(0);
23975 unsigned Opc = X86ISD::SHLD;
23976 SDValue Op0 = N0.getOperand(0);
23977 SDValue Op1 = N1.getOperand(0);
23978 if (ShAmt0.getOpcode() == ISD::SUB) {
23979 Opc = X86ISD::SHRD;
23980 std::swap(Op0, Op1);
23981 std::swap(ShAmt0, ShAmt1);
23984 unsigned Bits = VT.getSizeInBits();
23985 if (ShAmt1.getOpcode() == ISD::SUB) {
23986 SDValue Sum = ShAmt1.getOperand(0);
23987 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23988 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23989 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23990 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23991 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23992 return DAG.getNode(Opc, DL, VT,
23994 DAG.getNode(ISD::TRUNCATE, DL,
23997 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23998 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24000 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24001 return DAG.getNode(Opc, DL, VT,
24002 N0.getOperand(0), N1.getOperand(0),
24003 DAG.getNode(ISD::TRUNCATE, DL,
24010 // Generate NEG and CMOV for integer abs.
24011 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24012 EVT VT = N->getValueType(0);
24014 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24015 // 8-bit integer abs to NEG and CMOV.
24016 if (VT.isInteger() && VT.getSizeInBits() == 8)
24019 SDValue N0 = N->getOperand(0);
24020 SDValue N1 = N->getOperand(1);
24023 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24024 // and change it to SUB and CMOV.
24025 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24026 N0.getOpcode() == ISD::ADD &&
24027 N0.getOperand(1) == N1 &&
24028 N1.getOpcode() == ISD::SRA &&
24029 N1.getOperand(0) == N0.getOperand(0))
24030 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24031 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24032 // Generate SUB & CMOV.
24033 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24034 DAG.getConstant(0, VT), N0.getOperand(0));
24036 SDValue Ops[] = { N0.getOperand(0), Neg,
24037 DAG.getConstant(X86::COND_GE, MVT::i8),
24038 SDValue(Neg.getNode(), 1) };
24039 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24044 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24045 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24046 TargetLowering::DAGCombinerInfo &DCI,
24047 const X86Subtarget *Subtarget) {
24048 if (DCI.isBeforeLegalizeOps())
24051 if (Subtarget->hasCMov()) {
24052 SDValue RV = performIntegerAbsCombine(N, DAG);
24060 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24061 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24062 TargetLowering::DAGCombinerInfo &DCI,
24063 const X86Subtarget *Subtarget) {
24064 LoadSDNode *Ld = cast<LoadSDNode>(N);
24065 EVT RegVT = Ld->getValueType(0);
24066 EVT MemVT = Ld->getMemoryVT();
24068 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24070 // On Sandybridge unaligned 256bit loads are inefficient.
24071 ISD::LoadExtType Ext = Ld->getExtensionType();
24072 unsigned Alignment = Ld->getAlignment();
24073 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24074 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
24075 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24076 unsigned NumElems = RegVT.getVectorNumElements();
24080 SDValue Ptr = Ld->getBasePtr();
24081 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24083 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24085 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24086 Ld->getPointerInfo(), Ld->isVolatile(),
24087 Ld->isNonTemporal(), Ld->isInvariant(),
24089 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24090 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24091 Ld->getPointerInfo(), Ld->isVolatile(),
24092 Ld->isNonTemporal(), Ld->isInvariant(),
24093 std::min(16U, Alignment));
24094 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24096 Load2.getValue(1));
24098 SDValue NewVec = DAG.getUNDEF(RegVT);
24099 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24100 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24101 return DCI.CombineTo(N, NewVec, TF, true);
24107 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24108 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24109 const X86Subtarget *Subtarget) {
24110 StoreSDNode *St = cast<StoreSDNode>(N);
24111 EVT VT = St->getValue().getValueType();
24112 EVT StVT = St->getMemoryVT();
24114 SDValue StoredVal = St->getOperand(1);
24115 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24117 // If we are saving a concatenation of two XMM registers, perform two stores.
24118 // On Sandy Bridge, 256-bit memory operations are executed by two
24119 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
24120 // memory operation.
24121 unsigned Alignment = St->getAlignment();
24122 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24123 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
24124 StVT == VT && !IsAligned) {
24125 unsigned NumElems = VT.getVectorNumElements();
24129 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24130 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24132 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24133 SDValue Ptr0 = St->getBasePtr();
24134 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24136 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24137 St->getPointerInfo(), St->isVolatile(),
24138 St->isNonTemporal(), Alignment);
24139 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24140 St->getPointerInfo(), St->isVolatile(),
24141 St->isNonTemporal(),
24142 std::min(16U, Alignment));
24143 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24146 // Optimize trunc store (of multiple scalars) to shuffle and store.
24147 // First, pack all of the elements in one place. Next, store to memory
24148 // in fewer chunks.
24149 if (St->isTruncatingStore() && VT.isVector()) {
24150 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24151 unsigned NumElems = VT.getVectorNumElements();
24152 assert(StVT != VT && "Cannot truncate to the same type");
24153 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24154 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24156 // From, To sizes and ElemCount must be pow of two
24157 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24158 // We are going to use the original vector elt for storing.
24159 // Accumulated smaller vector elements must be a multiple of the store size.
24160 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24162 unsigned SizeRatio = FromSz / ToSz;
24164 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24166 // Create a type on which we perform the shuffle
24167 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24168 StVT.getScalarType(), NumElems*SizeRatio);
24170 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24172 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24173 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24174 for (unsigned i = 0; i != NumElems; ++i)
24175 ShuffleVec[i] = i * SizeRatio;
24177 // Can't shuffle using an illegal type.
24178 if (!TLI.isTypeLegal(WideVecVT))
24181 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24182 DAG.getUNDEF(WideVecVT),
24184 // At this point all of the data is stored at the bottom of the
24185 // register. We now need to save it to mem.
24187 // Find the largest store unit
24188 MVT StoreType = MVT::i8;
24189 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24190 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24191 MVT Tp = (MVT::SimpleValueType)tp;
24192 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24196 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24197 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24198 (64 <= NumElems * ToSz))
24199 StoreType = MVT::f64;
24201 // Bitcast the original vector into a vector of store-size units
24202 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24203 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24204 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24205 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24206 SmallVector<SDValue, 8> Chains;
24207 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24208 TLI.getPointerTy());
24209 SDValue Ptr = St->getBasePtr();
24211 // Perform one or more big stores into memory.
24212 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24213 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24214 StoreType, ShuffWide,
24215 DAG.getIntPtrConstant(i));
24216 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24217 St->getPointerInfo(), St->isVolatile(),
24218 St->isNonTemporal(), St->getAlignment());
24219 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24220 Chains.push_back(Ch);
24223 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24226 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24227 // the FP state in cases where an emms may be missing.
24228 // A preferable solution to the general problem is to figure out the right
24229 // places to insert EMMS. This qualifies as a quick hack.
24231 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24232 if (VT.getSizeInBits() != 64)
24235 const Function *F = DAG.getMachineFunction().getFunction();
24236 bool NoImplicitFloatOps = F->getAttributes().
24237 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24238 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24239 && Subtarget->hasSSE2();
24240 if ((VT.isVector() ||
24241 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24242 isa<LoadSDNode>(St->getValue()) &&
24243 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24244 St->getChain().hasOneUse() && !St->isVolatile()) {
24245 SDNode* LdVal = St->getValue().getNode();
24246 LoadSDNode *Ld = nullptr;
24247 int TokenFactorIndex = -1;
24248 SmallVector<SDValue, 8> Ops;
24249 SDNode* ChainVal = St->getChain().getNode();
24250 // Must be a store of a load. We currently handle two cases: the load
24251 // is a direct child, and it's under an intervening TokenFactor. It is
24252 // possible to dig deeper under nested TokenFactors.
24253 if (ChainVal == LdVal)
24254 Ld = cast<LoadSDNode>(St->getChain());
24255 else if (St->getValue().hasOneUse() &&
24256 ChainVal->getOpcode() == ISD::TokenFactor) {
24257 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24258 if (ChainVal->getOperand(i).getNode() == LdVal) {
24259 TokenFactorIndex = i;
24260 Ld = cast<LoadSDNode>(St->getValue());
24262 Ops.push_back(ChainVal->getOperand(i));
24266 if (!Ld || !ISD::isNormalLoad(Ld))
24269 // If this is not the MMX case, i.e. we are just turning i64 load/store
24270 // into f64 load/store, avoid the transformation if there are multiple
24271 // uses of the loaded value.
24272 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24277 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24278 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24280 if (Subtarget->is64Bit() || F64IsLegal) {
24281 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24282 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24283 Ld->getPointerInfo(), Ld->isVolatile(),
24284 Ld->isNonTemporal(), Ld->isInvariant(),
24285 Ld->getAlignment());
24286 SDValue NewChain = NewLd.getValue(1);
24287 if (TokenFactorIndex != -1) {
24288 Ops.push_back(NewChain);
24289 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24291 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24292 St->getPointerInfo(),
24293 St->isVolatile(), St->isNonTemporal(),
24294 St->getAlignment());
24297 // Otherwise, lower to two pairs of 32-bit loads / stores.
24298 SDValue LoAddr = Ld->getBasePtr();
24299 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24300 DAG.getConstant(4, MVT::i32));
24302 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24303 Ld->getPointerInfo(),
24304 Ld->isVolatile(), Ld->isNonTemporal(),
24305 Ld->isInvariant(), Ld->getAlignment());
24306 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24307 Ld->getPointerInfo().getWithOffset(4),
24308 Ld->isVolatile(), Ld->isNonTemporal(),
24310 MinAlign(Ld->getAlignment(), 4));
24312 SDValue NewChain = LoLd.getValue(1);
24313 if (TokenFactorIndex != -1) {
24314 Ops.push_back(LoLd);
24315 Ops.push_back(HiLd);
24316 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24319 LoAddr = St->getBasePtr();
24320 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24321 DAG.getConstant(4, MVT::i32));
24323 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24324 St->getPointerInfo(),
24325 St->isVolatile(), St->isNonTemporal(),
24326 St->getAlignment());
24327 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24328 St->getPointerInfo().getWithOffset(4),
24330 St->isNonTemporal(),
24331 MinAlign(St->getAlignment(), 4));
24332 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24337 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24338 /// and return the operands for the horizontal operation in LHS and RHS. A
24339 /// horizontal operation performs the binary operation on successive elements
24340 /// of its first operand, then on successive elements of its second operand,
24341 /// returning the resulting values in a vector. For example, if
24342 /// A = < float a0, float a1, float a2, float a3 >
24344 /// B = < float b0, float b1, float b2, float b3 >
24345 /// then the result of doing a horizontal operation on A and B is
24346 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24347 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24348 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24349 /// set to A, RHS to B, and the routine returns 'true'.
24350 /// Note that the binary operation should have the property that if one of the
24351 /// operands is UNDEF then the result is UNDEF.
24352 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24353 // Look for the following pattern: if
24354 // A = < float a0, float a1, float a2, float a3 >
24355 // B = < float b0, float b1, float b2, float b3 >
24357 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24358 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24359 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24360 // which is A horizontal-op B.
24362 // At least one of the operands should be a vector shuffle.
24363 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24364 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24367 MVT VT = LHS.getSimpleValueType();
24369 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24370 "Unsupported vector type for horizontal add/sub");
24372 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24373 // operate independently on 128-bit lanes.
24374 unsigned NumElts = VT.getVectorNumElements();
24375 unsigned NumLanes = VT.getSizeInBits()/128;
24376 unsigned NumLaneElts = NumElts / NumLanes;
24377 assert((NumLaneElts % 2 == 0) &&
24378 "Vector type should have an even number of elements in each lane");
24379 unsigned HalfLaneElts = NumLaneElts/2;
24381 // View LHS in the form
24382 // LHS = VECTOR_SHUFFLE A, B, LMask
24383 // If LHS is not a shuffle then pretend it is the shuffle
24384 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24385 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24388 SmallVector<int, 16> LMask(NumElts);
24389 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24390 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24391 A = LHS.getOperand(0);
24392 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24393 B = LHS.getOperand(1);
24394 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24395 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24397 if (LHS.getOpcode() != ISD::UNDEF)
24399 for (unsigned i = 0; i != NumElts; ++i)
24403 // Likewise, view RHS in the form
24404 // RHS = VECTOR_SHUFFLE C, D, RMask
24406 SmallVector<int, 16> RMask(NumElts);
24407 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24408 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24409 C = RHS.getOperand(0);
24410 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24411 D = RHS.getOperand(1);
24412 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24413 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24415 if (RHS.getOpcode() != ISD::UNDEF)
24417 for (unsigned i = 0; i != NumElts; ++i)
24421 // Check that the shuffles are both shuffling the same vectors.
24422 if (!(A == C && B == D) && !(A == D && B == C))
24425 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24426 if (!A.getNode() && !B.getNode())
24429 // If A and B occur in reverse order in RHS, then "swap" them (which means
24430 // rewriting the mask).
24432 CommuteVectorShuffleMask(RMask, NumElts);
24434 // At this point LHS and RHS are equivalent to
24435 // LHS = VECTOR_SHUFFLE A, B, LMask
24436 // RHS = VECTOR_SHUFFLE A, B, RMask
24437 // Check that the masks correspond to performing a horizontal operation.
24438 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24439 for (unsigned i = 0; i != NumLaneElts; ++i) {
24440 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24442 // Ignore any UNDEF components.
24443 if (LIdx < 0 || RIdx < 0 ||
24444 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24445 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24448 // Check that successive elements are being operated on. If not, this is
24449 // not a horizontal operation.
24450 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24451 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24452 if (!(LIdx == Index && RIdx == Index + 1) &&
24453 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24458 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24459 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24463 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24464 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24465 const X86Subtarget *Subtarget) {
24466 EVT VT = N->getValueType(0);
24467 SDValue LHS = N->getOperand(0);
24468 SDValue RHS = N->getOperand(1);
24470 // Try to synthesize horizontal adds from adds of shuffles.
24471 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24472 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24473 isHorizontalBinOp(LHS, RHS, true))
24474 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24478 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24479 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24480 const X86Subtarget *Subtarget) {
24481 EVT VT = N->getValueType(0);
24482 SDValue LHS = N->getOperand(0);
24483 SDValue RHS = N->getOperand(1);
24485 // Try to synthesize horizontal subs from subs of shuffles.
24486 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24487 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24488 isHorizontalBinOp(LHS, RHS, false))
24489 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24493 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24494 /// X86ISD::FXOR nodes.
24495 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24496 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24497 // F[X]OR(0.0, x) -> x
24498 // F[X]OR(x, 0.0) -> x
24499 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24500 if (C->getValueAPF().isPosZero())
24501 return N->getOperand(1);
24502 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24503 if (C->getValueAPF().isPosZero())
24504 return N->getOperand(0);
24508 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24509 /// X86ISD::FMAX nodes.
24510 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24511 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24513 // Only perform optimizations if UnsafeMath is used.
24514 if (!DAG.getTarget().Options.UnsafeFPMath)
24517 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24518 // into FMINC and FMAXC, which are Commutative operations.
24519 unsigned NewOp = 0;
24520 switch (N->getOpcode()) {
24521 default: llvm_unreachable("unknown opcode");
24522 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24523 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24526 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24527 N->getOperand(0), N->getOperand(1));
24530 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24531 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24532 // FAND(0.0, x) -> 0.0
24533 // FAND(x, 0.0) -> 0.0
24534 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24535 if (C->getValueAPF().isPosZero())
24536 return N->getOperand(0);
24537 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24538 if (C->getValueAPF().isPosZero())
24539 return N->getOperand(1);
24543 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24544 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24545 // FANDN(x, 0.0) -> 0.0
24546 // FANDN(0.0, x) -> x
24547 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24548 if (C->getValueAPF().isPosZero())
24549 return N->getOperand(1);
24550 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24551 if (C->getValueAPF().isPosZero())
24552 return N->getOperand(1);
24556 static SDValue PerformBTCombine(SDNode *N,
24558 TargetLowering::DAGCombinerInfo &DCI) {
24559 // BT ignores high bits in the bit index operand.
24560 SDValue Op1 = N->getOperand(1);
24561 if (Op1.hasOneUse()) {
24562 unsigned BitWidth = Op1.getValueSizeInBits();
24563 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24564 APInt KnownZero, KnownOne;
24565 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24566 !DCI.isBeforeLegalizeOps());
24567 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24568 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24569 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24570 DCI.CommitTargetLoweringOpt(TLO);
24575 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24576 SDValue Op = N->getOperand(0);
24577 if (Op.getOpcode() == ISD::BITCAST)
24578 Op = Op.getOperand(0);
24579 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24580 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24581 VT.getVectorElementType().getSizeInBits() ==
24582 OpVT.getVectorElementType().getSizeInBits()) {
24583 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24588 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24589 const X86Subtarget *Subtarget) {
24590 EVT VT = N->getValueType(0);
24591 if (!VT.isVector())
24594 SDValue N0 = N->getOperand(0);
24595 SDValue N1 = N->getOperand(1);
24596 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24599 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24600 // both SSE and AVX2 since there is no sign-extended shift right
24601 // operation on a vector with 64-bit elements.
24602 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24603 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24604 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24605 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24606 SDValue N00 = N0.getOperand(0);
24608 // EXTLOAD has a better solution on AVX2,
24609 // it may be replaced with X86ISD::VSEXT node.
24610 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24611 if (!ISD::isNormalLoad(N00.getNode()))
24614 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24615 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24617 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24623 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24624 TargetLowering::DAGCombinerInfo &DCI,
24625 const X86Subtarget *Subtarget) {
24626 SDValue N0 = N->getOperand(0);
24627 EVT VT = N->getValueType(0);
24629 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24630 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24631 // This exposes the sext to the sdivrem lowering, so that it directly extends
24632 // from AH (which we otherwise need to do contortions to access).
24633 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24634 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24636 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24637 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24638 N0.getOperand(0), N0.getOperand(1));
24639 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24640 return R.getValue(1);
24643 if (!DCI.isBeforeLegalizeOps())
24646 if (!Subtarget->hasFp256())
24649 if (VT.isVector() && VT.getSizeInBits() == 256) {
24650 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24658 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24659 const X86Subtarget* Subtarget) {
24661 EVT VT = N->getValueType(0);
24663 // Let legalize expand this if it isn't a legal type yet.
24664 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24667 EVT ScalarVT = VT.getScalarType();
24668 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24669 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24672 SDValue A = N->getOperand(0);
24673 SDValue B = N->getOperand(1);
24674 SDValue C = N->getOperand(2);
24676 bool NegA = (A.getOpcode() == ISD::FNEG);
24677 bool NegB = (B.getOpcode() == ISD::FNEG);
24678 bool NegC = (C.getOpcode() == ISD::FNEG);
24680 // Negative multiplication when NegA xor NegB
24681 bool NegMul = (NegA != NegB);
24683 A = A.getOperand(0);
24685 B = B.getOperand(0);
24687 C = C.getOperand(0);
24691 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24693 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24695 return DAG.getNode(Opcode, dl, VT, A, B, C);
24698 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24699 TargetLowering::DAGCombinerInfo &DCI,
24700 const X86Subtarget *Subtarget) {
24701 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24702 // (and (i32 x86isd::setcc_carry), 1)
24703 // This eliminates the zext. This transformation is necessary because
24704 // ISD::SETCC is always legalized to i8.
24706 SDValue N0 = N->getOperand(0);
24707 EVT VT = N->getValueType(0);
24709 if (N0.getOpcode() == ISD::AND &&
24711 N0.getOperand(0).hasOneUse()) {
24712 SDValue N00 = N0.getOperand(0);
24713 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24714 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24715 if (!C || C->getZExtValue() != 1)
24717 return DAG.getNode(ISD::AND, dl, VT,
24718 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24719 N00.getOperand(0), N00.getOperand(1)),
24720 DAG.getConstant(1, VT));
24724 if (N0.getOpcode() == ISD::TRUNCATE &&
24726 N0.getOperand(0).hasOneUse()) {
24727 SDValue N00 = N0.getOperand(0);
24728 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24729 return DAG.getNode(ISD::AND, dl, VT,
24730 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24731 N00.getOperand(0), N00.getOperand(1)),
24732 DAG.getConstant(1, VT));
24735 if (VT.is256BitVector()) {
24736 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24741 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24742 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24743 // This exposes the zext to the udivrem lowering, so that it directly extends
24744 // from AH (which we otherwise need to do contortions to access).
24745 if (N0.getOpcode() == ISD::UDIVREM &&
24746 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24747 (VT == MVT::i32 || VT == MVT::i64)) {
24748 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24749 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24750 N0.getOperand(0), N0.getOperand(1));
24751 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24752 return R.getValue(1);
24758 // Optimize x == -y --> x+y == 0
24759 // x != -y --> x+y != 0
24760 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24761 const X86Subtarget* Subtarget) {
24762 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24763 SDValue LHS = N->getOperand(0);
24764 SDValue RHS = N->getOperand(1);
24765 EVT VT = N->getValueType(0);
24768 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24769 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24770 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24771 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24772 LHS.getValueType(), RHS, LHS.getOperand(1));
24773 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24774 addV, DAG.getConstant(0, addV.getValueType()), CC);
24776 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24777 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24778 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24779 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24780 RHS.getValueType(), LHS, RHS.getOperand(1));
24781 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24782 addV, DAG.getConstant(0, addV.getValueType()), CC);
24785 if (VT.getScalarType() == MVT::i1) {
24786 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24787 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24788 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24789 if (!IsSEXT0 && !IsVZero0)
24791 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24792 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24793 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24795 if (!IsSEXT1 && !IsVZero1)
24798 if (IsSEXT0 && IsVZero1) {
24799 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24800 if (CC == ISD::SETEQ)
24801 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24802 return LHS.getOperand(0);
24804 if (IsSEXT1 && IsVZero0) {
24805 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24806 if (CC == ISD::SETEQ)
24807 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24808 return RHS.getOperand(0);
24815 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24816 const X86Subtarget *Subtarget) {
24818 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24819 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24820 "X86insertps is only defined for v4x32");
24822 SDValue Ld = N->getOperand(1);
24823 if (MayFoldLoad(Ld)) {
24824 // Extract the countS bits from the immediate so we can get the proper
24825 // address when narrowing the vector load to a specific element.
24826 // When the second source op is a memory address, interps doesn't use
24827 // countS and just gets an f32 from that address.
24828 unsigned DestIndex =
24829 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24830 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24834 // Create this as a scalar to vector to match the instruction pattern.
24835 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24836 // countS bits are ignored when loading from memory on insertps, which
24837 // means we don't need to explicitly set them to 0.
24838 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24839 LoadScalarToVector, N->getOperand(2));
24842 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24843 // as "sbb reg,reg", since it can be extended without zext and produces
24844 // an all-ones bit which is more useful than 0/1 in some cases.
24845 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24848 return DAG.getNode(ISD::AND, DL, VT,
24849 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24850 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24851 DAG.getConstant(1, VT));
24852 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24853 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24854 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24855 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24858 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24859 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24860 TargetLowering::DAGCombinerInfo &DCI,
24861 const X86Subtarget *Subtarget) {
24863 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24864 SDValue EFLAGS = N->getOperand(1);
24866 if (CC == X86::COND_A) {
24867 // Try to convert COND_A into COND_B in an attempt to facilitate
24868 // materializing "setb reg".
24870 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24871 // cannot take an immediate as its first operand.
24873 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24874 EFLAGS.getValueType().isInteger() &&
24875 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24876 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24877 EFLAGS.getNode()->getVTList(),
24878 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24879 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24880 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24884 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24885 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24887 if (CC == X86::COND_B)
24888 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24892 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24893 if (Flags.getNode()) {
24894 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24895 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24901 // Optimize branch condition evaluation.
24903 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24904 TargetLowering::DAGCombinerInfo &DCI,
24905 const X86Subtarget *Subtarget) {
24907 SDValue Chain = N->getOperand(0);
24908 SDValue Dest = N->getOperand(1);
24909 SDValue EFLAGS = N->getOperand(3);
24910 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24914 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24915 if (Flags.getNode()) {
24916 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24917 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24924 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24925 SelectionDAG &DAG) {
24926 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24927 // optimize away operation when it's from a constant.
24929 // The general transformation is:
24930 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24931 // AND(VECTOR_CMP(x,y), constant2)
24932 // constant2 = UNARYOP(constant)
24934 // Early exit if this isn't a vector operation, the operand of the
24935 // unary operation isn't a bitwise AND, or if the sizes of the operations
24936 // aren't the same.
24937 EVT VT = N->getValueType(0);
24938 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24939 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24940 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24943 // Now check that the other operand of the AND is a constant. We could
24944 // make the transformation for non-constant splats as well, but it's unclear
24945 // that would be a benefit as it would not eliminate any operations, just
24946 // perform one more step in scalar code before moving to the vector unit.
24947 if (BuildVectorSDNode *BV =
24948 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24949 // Bail out if the vector isn't a constant.
24950 if (!BV->isConstant())
24953 // Everything checks out. Build up the new and improved node.
24955 EVT IntVT = BV->getValueType(0);
24956 // Create a new constant of the appropriate type for the transformed
24958 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24959 // The AND node needs bitcasts to/from an integer vector type around it.
24960 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24961 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24962 N->getOperand(0)->getOperand(0), MaskConst);
24963 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24970 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24971 const X86TargetLowering *XTLI) {
24972 // First try to optimize away the conversion entirely when it's
24973 // conditionally from a constant. Vectors only.
24974 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24975 if (Res != SDValue())
24978 // Now move on to more general possibilities.
24979 SDValue Op0 = N->getOperand(0);
24980 EVT InVT = Op0->getValueType(0);
24982 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24983 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24985 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24986 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24987 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24990 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24991 // a 32-bit target where SSE doesn't support i64->FP operations.
24992 if (Op0.getOpcode() == ISD::LOAD) {
24993 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24994 EVT VT = Ld->getValueType(0);
24995 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24996 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24997 !XTLI->getSubtarget()->is64Bit() &&
24999 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25000 Ld->getChain(), Op0, DAG);
25001 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25008 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25009 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25010 X86TargetLowering::DAGCombinerInfo &DCI) {
25011 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25012 // the result is either zero or one (depending on the input carry bit).
25013 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25014 if (X86::isZeroNode(N->getOperand(0)) &&
25015 X86::isZeroNode(N->getOperand(1)) &&
25016 // We don't have a good way to replace an EFLAGS use, so only do this when
25018 SDValue(N, 1).use_empty()) {
25020 EVT VT = N->getValueType(0);
25021 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25022 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25023 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25024 DAG.getConstant(X86::COND_B,MVT::i8),
25026 DAG.getConstant(1, VT));
25027 return DCI.CombineTo(N, Res1, CarryOut);
25033 // fold (add Y, (sete X, 0)) -> adc 0, Y
25034 // (add Y, (setne X, 0)) -> sbb -1, Y
25035 // (sub (sete X, 0), Y) -> sbb 0, Y
25036 // (sub (setne X, 0), Y) -> adc -1, Y
25037 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25040 // Look through ZExts.
25041 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25042 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25045 SDValue SetCC = Ext.getOperand(0);
25046 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25049 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25050 if (CC != X86::COND_E && CC != X86::COND_NE)
25053 SDValue Cmp = SetCC.getOperand(1);
25054 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25055 !X86::isZeroNode(Cmp.getOperand(1)) ||
25056 !Cmp.getOperand(0).getValueType().isInteger())
25059 SDValue CmpOp0 = Cmp.getOperand(0);
25060 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25061 DAG.getConstant(1, CmpOp0.getValueType()));
25063 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25064 if (CC == X86::COND_NE)
25065 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25066 DL, OtherVal.getValueType(), OtherVal,
25067 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25068 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25069 DL, OtherVal.getValueType(), OtherVal,
25070 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25073 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25074 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25075 const X86Subtarget *Subtarget) {
25076 EVT VT = N->getValueType(0);
25077 SDValue Op0 = N->getOperand(0);
25078 SDValue Op1 = N->getOperand(1);
25080 // Try to synthesize horizontal adds from adds of shuffles.
25081 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25082 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25083 isHorizontalBinOp(Op0, Op1, true))
25084 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25086 return OptimizeConditionalInDecrement(N, DAG);
25089 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25090 const X86Subtarget *Subtarget) {
25091 SDValue Op0 = N->getOperand(0);
25092 SDValue Op1 = N->getOperand(1);
25094 // X86 can't encode an immediate LHS of a sub. See if we can push the
25095 // negation into a preceding instruction.
25096 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25097 // If the RHS of the sub is a XOR with one use and a constant, invert the
25098 // immediate. Then add one to the LHS of the sub so we can turn
25099 // X-Y -> X+~Y+1, saving one register.
25100 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25101 isa<ConstantSDNode>(Op1.getOperand(1))) {
25102 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25103 EVT VT = Op0.getValueType();
25104 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25106 DAG.getConstant(~XorC, VT));
25107 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25108 DAG.getConstant(C->getAPIntValue()+1, VT));
25112 // Try to synthesize horizontal adds from adds of shuffles.
25113 EVT VT = N->getValueType(0);
25114 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25115 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25116 isHorizontalBinOp(Op0, Op1, true))
25117 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25119 return OptimizeConditionalInDecrement(N, DAG);
25122 /// performVZEXTCombine - Performs build vector combines
25123 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25124 TargetLowering::DAGCombinerInfo &DCI,
25125 const X86Subtarget *Subtarget) {
25127 MVT VT = N->getSimpleValueType(0);
25128 SDValue Op = N->getOperand(0);
25129 MVT OpVT = Op.getSimpleValueType();
25130 MVT OpEltVT = OpVT.getVectorElementType();
25131 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25133 // (vzext (bitcast (vzext (x)) -> (vzext x)
25135 while (V.getOpcode() == ISD::BITCAST)
25136 V = V.getOperand(0);
25138 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25139 MVT InnerVT = V.getSimpleValueType();
25140 MVT InnerEltVT = InnerVT.getVectorElementType();
25142 // If the element sizes match exactly, we can just do one larger vzext. This
25143 // is always an exact type match as vzext operates on integer types.
25144 if (OpEltVT == InnerEltVT) {
25145 assert(OpVT == InnerVT && "Types must match for vzext!");
25146 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25149 // The only other way we can combine them is if only a single element of the
25150 // inner vzext is used in the input to the outer vzext.
25151 if (InnerEltVT.getSizeInBits() < InputBits)
25154 // In this case, the inner vzext is completely dead because we're going to
25155 // only look at bits inside of the low element. Just do the outer vzext on
25156 // a bitcast of the input to the inner.
25157 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25158 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25161 // Check if we can bypass extracting and re-inserting an element of an input
25162 // vector. Essentialy:
25163 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25164 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25165 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25166 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25167 SDValue ExtractedV = V.getOperand(0);
25168 SDValue OrigV = ExtractedV.getOperand(0);
25169 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25170 if (ExtractIdx->getZExtValue() == 0) {
25171 MVT OrigVT = OrigV.getSimpleValueType();
25172 // Extract a subvector if necessary...
25173 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25174 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25175 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25176 OrigVT.getVectorNumElements() / Ratio);
25177 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25178 DAG.getIntPtrConstant(0));
25180 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25181 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25188 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25189 DAGCombinerInfo &DCI) const {
25190 SelectionDAG &DAG = DCI.DAG;
25191 switch (N->getOpcode()) {
25193 case ISD::EXTRACT_VECTOR_ELT:
25194 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25197 case X86ISD::SHRUNKBLEND:
25198 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25199 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25200 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25201 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25202 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25203 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25206 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25207 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25208 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25209 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25210 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25211 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25212 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25213 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25214 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25216 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25218 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25219 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25220 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25221 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25222 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25223 case ISD::ANY_EXTEND:
25224 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25225 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25226 case ISD::SIGN_EXTEND_INREG:
25227 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25228 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25229 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25230 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25231 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25232 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25233 case X86ISD::SHUFP: // Handle all target specific shuffles
25234 case X86ISD::PALIGNR:
25235 case X86ISD::UNPCKH:
25236 case X86ISD::UNPCKL:
25237 case X86ISD::MOVHLPS:
25238 case X86ISD::MOVLHPS:
25239 case X86ISD::PSHUFB:
25240 case X86ISD::PSHUFD:
25241 case X86ISD::PSHUFHW:
25242 case X86ISD::PSHUFLW:
25243 case X86ISD::MOVSS:
25244 case X86ISD::MOVSD:
25245 case X86ISD::VPERMILPI:
25246 case X86ISD::VPERM2X128:
25247 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25248 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25249 case ISD::INTRINSIC_WO_CHAIN:
25250 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25251 case X86ISD::INSERTPS:
25252 return PerformINSERTPSCombine(N, DAG, Subtarget);
25253 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25259 /// isTypeDesirableForOp - Return true if the target has native support for
25260 /// the specified value type and it is 'desirable' to use the type for the
25261 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25262 /// instruction encodings are longer and some i16 instructions are slow.
25263 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25264 if (!isTypeLegal(VT))
25266 if (VT != MVT::i16)
25273 case ISD::SIGN_EXTEND:
25274 case ISD::ZERO_EXTEND:
25275 case ISD::ANY_EXTEND:
25288 /// IsDesirableToPromoteOp - This method query the target whether it is
25289 /// beneficial for dag combiner to promote the specified node. If true, it
25290 /// should return the desired promotion type by reference.
25291 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25292 EVT VT = Op.getValueType();
25293 if (VT != MVT::i16)
25296 bool Promote = false;
25297 bool Commute = false;
25298 switch (Op.getOpcode()) {
25301 LoadSDNode *LD = cast<LoadSDNode>(Op);
25302 // If the non-extending load has a single use and it's not live out, then it
25303 // might be folded.
25304 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25305 Op.hasOneUse()*/) {
25306 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25307 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25308 // The only case where we'd want to promote LOAD (rather then it being
25309 // promoted as an operand is when it's only use is liveout.
25310 if (UI->getOpcode() != ISD::CopyToReg)
25317 case ISD::SIGN_EXTEND:
25318 case ISD::ZERO_EXTEND:
25319 case ISD::ANY_EXTEND:
25324 SDValue N0 = Op.getOperand(0);
25325 // Look out for (store (shl (load), x)).
25326 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25339 SDValue N0 = Op.getOperand(0);
25340 SDValue N1 = Op.getOperand(1);
25341 if (!Commute && MayFoldLoad(N1))
25343 // Avoid disabling potential load folding opportunities.
25344 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25346 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25356 //===----------------------------------------------------------------------===//
25357 // X86 Inline Assembly Support
25358 //===----------------------------------------------------------------------===//
25361 // Helper to match a string separated by whitespace.
25362 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25363 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25365 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25366 StringRef piece(*args[i]);
25367 if (!s.startswith(piece)) // Check if the piece matches.
25370 s = s.substr(piece.size());
25371 StringRef::size_type pos = s.find_first_not_of(" \t");
25372 if (pos == 0) // We matched a prefix.
25380 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25383 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25385 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25386 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25387 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25388 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25390 if (AsmPieces.size() == 3)
25392 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25399 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25400 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25402 std::string AsmStr = IA->getAsmString();
25404 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25405 if (!Ty || Ty->getBitWidth() % 16 != 0)
25408 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25409 SmallVector<StringRef, 4> AsmPieces;
25410 SplitString(AsmStr, AsmPieces, ";\n");
25412 switch (AsmPieces.size()) {
25413 default: return false;
25415 // FIXME: this should verify that we are targeting a 486 or better. If not,
25416 // we will turn this bswap into something that will be lowered to logical
25417 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25418 // lower so don't worry about this.
25420 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25421 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25422 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25423 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25424 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25425 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25426 // No need to check constraints, nothing other than the equivalent of
25427 // "=r,0" would be valid here.
25428 return IntrinsicLowering::LowerToByteSwap(CI);
25431 // rorw $$8, ${0:w} --> llvm.bswap.i16
25432 if (CI->getType()->isIntegerTy(16) &&
25433 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25434 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25435 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25437 const std::string &ConstraintsStr = IA->getConstraintString();
25438 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25439 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25440 if (clobbersFlagRegisters(AsmPieces))
25441 return IntrinsicLowering::LowerToByteSwap(CI);
25445 if (CI->getType()->isIntegerTy(32) &&
25446 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25447 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25448 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25449 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25451 const std::string &ConstraintsStr = IA->getConstraintString();
25452 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25453 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25454 if (clobbersFlagRegisters(AsmPieces))
25455 return IntrinsicLowering::LowerToByteSwap(CI);
25458 if (CI->getType()->isIntegerTy(64)) {
25459 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25460 if (Constraints.size() >= 2 &&
25461 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25462 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25463 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25464 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25465 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25466 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25467 return IntrinsicLowering::LowerToByteSwap(CI);
25475 /// getConstraintType - Given a constraint letter, return the type of
25476 /// constraint it is for this target.
25477 X86TargetLowering::ConstraintType
25478 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25479 if (Constraint.size() == 1) {
25480 switch (Constraint[0]) {
25491 return C_RegisterClass;
25515 return TargetLowering::getConstraintType(Constraint);
25518 /// Examine constraint type and operand type and determine a weight value.
25519 /// This object must already have been set up with the operand type
25520 /// and the current alternative constraint selected.
25521 TargetLowering::ConstraintWeight
25522 X86TargetLowering::getSingleConstraintMatchWeight(
25523 AsmOperandInfo &info, const char *constraint) const {
25524 ConstraintWeight weight = CW_Invalid;
25525 Value *CallOperandVal = info.CallOperandVal;
25526 // If we don't have a value, we can't do a match,
25527 // but allow it at the lowest weight.
25528 if (!CallOperandVal)
25530 Type *type = CallOperandVal->getType();
25531 // Look at the constraint type.
25532 switch (*constraint) {
25534 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25545 if (CallOperandVal->getType()->isIntegerTy())
25546 weight = CW_SpecificReg;
25551 if (type->isFloatingPointTy())
25552 weight = CW_SpecificReg;
25555 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25556 weight = CW_SpecificReg;
25560 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25561 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25562 weight = CW_Register;
25565 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25566 if (C->getZExtValue() <= 31)
25567 weight = CW_Constant;
25571 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25572 if (C->getZExtValue() <= 63)
25573 weight = CW_Constant;
25577 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25578 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25579 weight = CW_Constant;
25583 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25584 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25585 weight = CW_Constant;
25589 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25590 if (C->getZExtValue() <= 3)
25591 weight = CW_Constant;
25595 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25596 if (C->getZExtValue() <= 0xff)
25597 weight = CW_Constant;
25602 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25603 weight = CW_Constant;
25607 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25608 if ((C->getSExtValue() >= -0x80000000LL) &&
25609 (C->getSExtValue() <= 0x7fffffffLL))
25610 weight = CW_Constant;
25614 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25615 if (C->getZExtValue() <= 0xffffffff)
25616 weight = CW_Constant;
25623 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25624 /// with another that has more specific requirements based on the type of the
25625 /// corresponding operand.
25626 const char *X86TargetLowering::
25627 LowerXConstraint(EVT ConstraintVT) const {
25628 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25629 // 'f' like normal targets.
25630 if (ConstraintVT.isFloatingPoint()) {
25631 if (Subtarget->hasSSE2())
25633 if (Subtarget->hasSSE1())
25637 return TargetLowering::LowerXConstraint(ConstraintVT);
25640 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25641 /// vector. If it is invalid, don't add anything to Ops.
25642 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25643 std::string &Constraint,
25644 std::vector<SDValue>&Ops,
25645 SelectionDAG &DAG) const {
25648 // Only support length 1 constraints for now.
25649 if (Constraint.length() > 1) return;
25651 char ConstraintLetter = Constraint[0];
25652 switch (ConstraintLetter) {
25655 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25656 if (C->getZExtValue() <= 31) {
25657 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25663 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25664 if (C->getZExtValue() <= 63) {
25665 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25671 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25672 if (isInt<8>(C->getSExtValue())) {
25673 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25679 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25680 if (C->getZExtValue() <= 255) {
25681 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25687 // 32-bit signed value
25688 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25689 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25690 C->getSExtValue())) {
25691 // Widen to 64 bits here to get it sign extended.
25692 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25695 // FIXME gcc accepts some relocatable values here too, but only in certain
25696 // memory models; it's complicated.
25701 // 32-bit unsigned value
25702 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25703 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25704 C->getZExtValue())) {
25705 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25709 // FIXME gcc accepts some relocatable values here too, but only in certain
25710 // memory models; it's complicated.
25714 // Literal immediates are always ok.
25715 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25716 // Widen to 64 bits here to get it sign extended.
25717 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25721 // In any sort of PIC mode addresses need to be computed at runtime by
25722 // adding in a register or some sort of table lookup. These can't
25723 // be used as immediates.
25724 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25727 // If we are in non-pic codegen mode, we allow the address of a global (with
25728 // an optional displacement) to be used with 'i'.
25729 GlobalAddressSDNode *GA = nullptr;
25730 int64_t Offset = 0;
25732 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25734 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25735 Offset += GA->getOffset();
25737 } else if (Op.getOpcode() == ISD::ADD) {
25738 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25739 Offset += C->getZExtValue();
25740 Op = Op.getOperand(0);
25743 } else if (Op.getOpcode() == ISD::SUB) {
25744 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25745 Offset += -C->getZExtValue();
25746 Op = Op.getOperand(0);
25751 // Otherwise, this isn't something we can handle, reject it.
25755 const GlobalValue *GV = GA->getGlobal();
25756 // If we require an extra load to get this address, as in PIC mode, we
25757 // can't accept it.
25758 if (isGlobalStubReference(
25759 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25762 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25763 GA->getValueType(0), Offset);
25768 if (Result.getNode()) {
25769 Ops.push_back(Result);
25772 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25775 std::pair<unsigned, const TargetRegisterClass*>
25776 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25778 // First, see if this is a constraint that directly corresponds to an LLVM
25780 if (Constraint.size() == 1) {
25781 // GCC Constraint Letters
25782 switch (Constraint[0]) {
25784 // TODO: Slight differences here in allocation order and leaving
25785 // RIP in the class. Do they matter any more here than they do
25786 // in the normal allocation?
25787 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25788 if (Subtarget->is64Bit()) {
25789 if (VT == MVT::i32 || VT == MVT::f32)
25790 return std::make_pair(0U, &X86::GR32RegClass);
25791 if (VT == MVT::i16)
25792 return std::make_pair(0U, &X86::GR16RegClass);
25793 if (VT == MVT::i8 || VT == MVT::i1)
25794 return std::make_pair(0U, &X86::GR8RegClass);
25795 if (VT == MVT::i64 || VT == MVT::f64)
25796 return std::make_pair(0U, &X86::GR64RegClass);
25799 // 32-bit fallthrough
25800 case 'Q': // Q_REGS
25801 if (VT == MVT::i32 || VT == MVT::f32)
25802 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25803 if (VT == MVT::i16)
25804 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25805 if (VT == MVT::i8 || VT == MVT::i1)
25806 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25807 if (VT == MVT::i64)
25808 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25810 case 'r': // GENERAL_REGS
25811 case 'l': // INDEX_REGS
25812 if (VT == MVT::i8 || VT == MVT::i1)
25813 return std::make_pair(0U, &X86::GR8RegClass);
25814 if (VT == MVT::i16)
25815 return std::make_pair(0U, &X86::GR16RegClass);
25816 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25817 return std::make_pair(0U, &X86::GR32RegClass);
25818 return std::make_pair(0U, &X86::GR64RegClass);
25819 case 'R': // LEGACY_REGS
25820 if (VT == MVT::i8 || VT == MVT::i1)
25821 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25822 if (VT == MVT::i16)
25823 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25824 if (VT == MVT::i32 || !Subtarget->is64Bit())
25825 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25826 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25827 case 'f': // FP Stack registers.
25828 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25829 // value to the correct fpstack register class.
25830 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25831 return std::make_pair(0U, &X86::RFP32RegClass);
25832 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25833 return std::make_pair(0U, &X86::RFP64RegClass);
25834 return std::make_pair(0U, &X86::RFP80RegClass);
25835 case 'y': // MMX_REGS if MMX allowed.
25836 if (!Subtarget->hasMMX()) break;
25837 return std::make_pair(0U, &X86::VR64RegClass);
25838 case 'Y': // SSE_REGS if SSE2 allowed
25839 if (!Subtarget->hasSSE2()) break;
25841 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25842 if (!Subtarget->hasSSE1()) break;
25844 switch (VT.SimpleTy) {
25846 // Scalar SSE types.
25849 return std::make_pair(0U, &X86::FR32RegClass);
25852 return std::make_pair(0U, &X86::FR64RegClass);
25860 return std::make_pair(0U, &X86::VR128RegClass);
25868 return std::make_pair(0U, &X86::VR256RegClass);
25873 return std::make_pair(0U, &X86::VR512RegClass);
25879 // Use the default implementation in TargetLowering to convert the register
25880 // constraint into a member of a register class.
25881 std::pair<unsigned, const TargetRegisterClass*> Res;
25882 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25884 // Not found as a standard register?
25886 // Map st(0) -> st(7) -> ST0
25887 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25888 tolower(Constraint[1]) == 's' &&
25889 tolower(Constraint[2]) == 't' &&
25890 Constraint[3] == '(' &&
25891 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25892 Constraint[5] == ')' &&
25893 Constraint[6] == '}') {
25895 Res.first = X86::FP0+Constraint[4]-'0';
25896 Res.second = &X86::RFP80RegClass;
25900 // GCC allows "st(0)" to be called just plain "st".
25901 if (StringRef("{st}").equals_lower(Constraint)) {
25902 Res.first = X86::FP0;
25903 Res.second = &X86::RFP80RegClass;
25908 if (StringRef("{flags}").equals_lower(Constraint)) {
25909 Res.first = X86::EFLAGS;
25910 Res.second = &X86::CCRRegClass;
25914 // 'A' means EAX + EDX.
25915 if (Constraint == "A") {
25916 Res.first = X86::EAX;
25917 Res.second = &X86::GR32_ADRegClass;
25923 // Otherwise, check to see if this is a register class of the wrong value
25924 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25925 // turn into {ax},{dx}.
25926 if (Res.second->hasType(VT))
25927 return Res; // Correct type already, nothing to do.
25929 // All of the single-register GCC register classes map their values onto
25930 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25931 // really want an 8-bit or 32-bit register, map to the appropriate register
25932 // class and return the appropriate register.
25933 if (Res.second == &X86::GR16RegClass) {
25934 if (VT == MVT::i8 || VT == MVT::i1) {
25935 unsigned DestReg = 0;
25936 switch (Res.first) {
25938 case X86::AX: DestReg = X86::AL; break;
25939 case X86::DX: DestReg = X86::DL; break;
25940 case X86::CX: DestReg = X86::CL; break;
25941 case X86::BX: DestReg = X86::BL; break;
25944 Res.first = DestReg;
25945 Res.second = &X86::GR8RegClass;
25947 } else if (VT == MVT::i32 || VT == MVT::f32) {
25948 unsigned DestReg = 0;
25949 switch (Res.first) {
25951 case X86::AX: DestReg = X86::EAX; break;
25952 case X86::DX: DestReg = X86::EDX; break;
25953 case X86::CX: DestReg = X86::ECX; break;
25954 case X86::BX: DestReg = X86::EBX; break;
25955 case X86::SI: DestReg = X86::ESI; break;
25956 case X86::DI: DestReg = X86::EDI; break;
25957 case X86::BP: DestReg = X86::EBP; break;
25958 case X86::SP: DestReg = X86::ESP; break;
25961 Res.first = DestReg;
25962 Res.second = &X86::GR32RegClass;
25964 } else if (VT == MVT::i64 || VT == MVT::f64) {
25965 unsigned DestReg = 0;
25966 switch (Res.first) {
25968 case X86::AX: DestReg = X86::RAX; break;
25969 case X86::DX: DestReg = X86::RDX; break;
25970 case X86::CX: DestReg = X86::RCX; break;
25971 case X86::BX: DestReg = X86::RBX; break;
25972 case X86::SI: DestReg = X86::RSI; break;
25973 case X86::DI: DestReg = X86::RDI; break;
25974 case X86::BP: DestReg = X86::RBP; break;
25975 case X86::SP: DestReg = X86::RSP; break;
25978 Res.first = DestReg;
25979 Res.second = &X86::GR64RegClass;
25982 } else if (Res.second == &X86::FR32RegClass ||
25983 Res.second == &X86::FR64RegClass ||
25984 Res.second == &X86::VR128RegClass ||
25985 Res.second == &X86::VR256RegClass ||
25986 Res.second == &X86::FR32XRegClass ||
25987 Res.second == &X86::FR64XRegClass ||
25988 Res.second == &X86::VR128XRegClass ||
25989 Res.second == &X86::VR256XRegClass ||
25990 Res.second == &X86::VR512RegClass) {
25991 // Handle references to XMM physical registers that got mapped into the
25992 // wrong class. This can happen with constraints like {xmm0} where the
25993 // target independent register mapper will just pick the first match it can
25994 // find, ignoring the required type.
25996 if (VT == MVT::f32 || VT == MVT::i32)
25997 Res.second = &X86::FR32RegClass;
25998 else if (VT == MVT::f64 || VT == MVT::i64)
25999 Res.second = &X86::FR64RegClass;
26000 else if (X86::VR128RegClass.hasType(VT))
26001 Res.second = &X86::VR128RegClass;
26002 else if (X86::VR256RegClass.hasType(VT))
26003 Res.second = &X86::VR256RegClass;
26004 else if (X86::VR512RegClass.hasType(VT))
26005 Res.second = &X86::VR512RegClass;
26011 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26013 // Scaling factors are not free at all.
26014 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26015 // will take 2 allocations in the out of order engine instead of 1
26016 // for plain addressing mode, i.e. inst (reg1).
26018 // vaddps (%rsi,%drx), %ymm0, %ymm1
26019 // Requires two allocations (one for the load, one for the computation)
26021 // vaddps (%rsi), %ymm0, %ymm1
26022 // Requires just 1 allocation, i.e., freeing allocations for other operations
26023 // and having less micro operations to execute.
26025 // For some X86 architectures, this is even worse because for instance for
26026 // stores, the complex addressing mode forces the instruction to use the
26027 // "load" ports instead of the dedicated "store" port.
26028 // E.g., on Haswell:
26029 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26030 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26031 if (isLegalAddressingMode(AM, Ty))
26032 // Scale represents reg2 * scale, thus account for 1
26033 // as soon as we use a second register.
26034 return AM.Scale != 0;
26038 bool X86TargetLowering::isTargetFTOL() const {
26039 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();