1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit bounday. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
171 unsigned IdxVal, SelectionDAG &DAG,
173 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
174 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
177 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
178 unsigned IdxVal, SelectionDAG &DAG,
180 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
181 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
184 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
185 /// instructions. This is used because creating CONCAT_VECTOR nodes of
186 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
187 /// large BUILD_VECTORS.
188 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
189 unsigned NumElems, SelectionDAG &DAG,
191 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
192 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
195 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
196 unsigned NumElems, SelectionDAG &DAG,
198 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
199 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
202 // FIXME: This should stop caching the target machine as soon as
203 // we can remove resetOperationActions et al.
204 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
205 : TargetLowering(TM) {
206 Subtarget = &TM.getSubtarget<X86Subtarget>();
207 X86ScalarSSEf64 = Subtarget->hasSSE2();
208 X86ScalarSSEf32 = Subtarget->hasSSE1();
209 TD = getDataLayout();
211 resetOperationActions();
214 void X86TargetLowering::resetOperationActions() {
215 const TargetMachine &TM = getTargetMachine();
216 static bool FirstTimeThrough = true;
218 // If none of the target options have changed, then we don't need to reset the
219 // operation actions.
220 if (!FirstTimeThrough && TO == TM.Options) return;
222 if (!FirstTimeThrough) {
223 // Reinitialize the actions.
225 FirstTimeThrough = false;
230 // Set up the TargetLowering object.
231 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
233 // X86 is weird, it always uses i8 for shift amounts and setcc results.
234 setBooleanContents(ZeroOrOneBooleanContent);
235 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
236 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
238 // For 64-bit since we have so many registers use the ILP scheduler, for
239 // 32-bit code use the register pressure specific scheduling.
240 // For Atom, always use ILP scheduling.
241 if (Subtarget->isAtom())
242 setSchedulingPreference(Sched::ILP);
243 else if (Subtarget->is64Bit())
244 setSchedulingPreference(Sched::ILP);
246 setSchedulingPreference(Sched::RegPressure);
247 const X86RegisterInfo *RegInfo =
248 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
249 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
251 // Bypass expensive divides on Atom when compiling with O2
252 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
253 addBypassSlowDiv(32, 8);
254 if (Subtarget->is64Bit())
255 addBypassSlowDiv(64, 16);
258 if (Subtarget->isTargetKnownWindowsMSVC()) {
259 // Setup Windows compiler runtime calls.
260 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
261 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
262 setLibcallName(RTLIB::SREM_I64, "_allrem");
263 setLibcallName(RTLIB::UREM_I64, "_aullrem");
264 setLibcallName(RTLIB::MUL_I64, "_allmul");
265 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
266 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
268 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
269 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
271 // The _ftol2 runtime function has an unusual calling conv, which
272 // is modeled by a special pseudo-instruction.
273 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
274 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
275 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
276 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
279 if (Subtarget->isTargetDarwin()) {
280 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
281 setUseUnderscoreSetJmp(false);
282 setUseUnderscoreLongJmp(false);
283 } else if (Subtarget->isTargetWindowsGNU()) {
284 // MS runtime is weird: it exports _setjmp, but longjmp!
285 setUseUnderscoreSetJmp(true);
286 setUseUnderscoreLongJmp(false);
288 setUseUnderscoreSetJmp(true);
289 setUseUnderscoreLongJmp(true);
292 // Set up the register classes.
293 addRegisterClass(MVT::i8, &X86::GR8RegClass);
294 addRegisterClass(MVT::i16, &X86::GR16RegClass);
295 addRegisterClass(MVT::i32, &X86::GR32RegClass);
296 if (Subtarget->is64Bit())
297 addRegisterClass(MVT::i64, &X86::GR64RegClass);
299 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
301 // We don't accept any truncstore of integer registers.
302 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
303 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
304 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
305 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
306 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
307 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
309 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
311 // SETOEQ and SETUNE require checking two conditions.
312 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
313 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
314 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
315 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
316 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
317 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
319 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
321 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
322 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
325 if (Subtarget->is64Bit()) {
326 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 } else if (!TM.Options.UseSoftFloat) {
329 // We have an algorithm for SSE2->double, and we turn this into a
330 // 64-bit FILD followed by conditional FADD for other targets.
331 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
332 // We have an algorithm for SSE2, and we turn this into a 64-bit
333 // FILD for other targets.
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
337 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
339 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
342 if (!TM.Options.UseSoftFloat) {
343 // SSE has no i16 to fp conversion, only i32
344 if (X86ScalarSSEf32) {
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
346 // f32 and f64 cases are Legal, f80 case is not
347 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
357 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
358 // are Legal, f80 is custom lowered.
359 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
360 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
362 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
364 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
367 if (X86ScalarSSEf32) {
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
369 // f32 and f64 cases are Legal, f80 case is not
370 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
376 // Handle FP_TO_UINT by promoting the destination to a larger signed
378 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
379 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
382 if (Subtarget->is64Bit()) {
383 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
384 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
385 } else if (!TM.Options.UseSoftFloat) {
386 // Since AVX is a superset of SSE3, only check for SSE here.
387 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
388 // Expand FP_TO_UINT into a select.
389 // FIXME: We would like to use a Custom expander here eventually to do
390 // the optimal thing for SSE vs. the default expansion in the legalizer.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
393 // With SSE3 we can use fisttpll to convert to a signed i64; without
394 // SSE, we're stuck with a fistpll.
395 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
398 if (isTargetFTOL()) {
399 // Use the _ftol2 runtime function, which has a pseudo-instruction
400 // to handle its weird calling convention.
401 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
404 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
405 if (!X86ScalarSSEf64) {
406 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
407 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
408 if (Subtarget->is64Bit()) {
409 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
410 // Without SSE, i64->f64 goes through memory.
411 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
415 // Scalar integer divide and remainder are lowered to use operations that
416 // produce two results, to match the available instructions. This exposes
417 // the two-result form to trivial CSE, which is able to combine x/y and x%y
418 // into a single instruction.
420 // Scalar integer multiply-high is also lowered to use two-result
421 // operations, to match the available instructions. However, plain multiply
422 // (low) operations are left as Legal, as there are single-result
423 // instructions for this in x86. Using the two-result multiply instructions
424 // when both high and low results are needed must be arranged by dagcombine.
425 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
427 setOperationAction(ISD::MULHS, VT, Expand);
428 setOperationAction(ISD::MULHU, VT, Expand);
429 setOperationAction(ISD::SDIV, VT, Expand);
430 setOperationAction(ISD::UDIV, VT, Expand);
431 setOperationAction(ISD::SREM, VT, Expand);
432 setOperationAction(ISD::UREM, VT, Expand);
434 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
435 setOperationAction(ISD::ADDC, VT, Custom);
436 setOperationAction(ISD::ADDE, VT, Custom);
437 setOperationAction(ISD::SUBC, VT, Custom);
438 setOperationAction(ISD::SUBE, VT, Custom);
441 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
442 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
443 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
444 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
445 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
446 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
447 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
448 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
449 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
456 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
457 if (Subtarget->is64Bit())
458 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
461 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
462 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
463 setOperationAction(ISD::FREM , MVT::f32 , Expand);
464 setOperationAction(ISD::FREM , MVT::f64 , Expand);
465 setOperationAction(ISD::FREM , MVT::f80 , Expand);
466 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
468 // Promote the i8 variants and force them on up to i32 which has a shorter
470 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
471 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
473 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
474 if (Subtarget->hasBMI()) {
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
476 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
477 if (Subtarget->is64Bit())
478 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
480 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
481 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
482 if (Subtarget->is64Bit())
483 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
486 if (Subtarget->hasLZCNT()) {
487 // When promoting the i8 variants, force them to i32 for a shorter
489 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
490 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
492 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
494 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
495 if (Subtarget->is64Bit())
496 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
498 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
499 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
500 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
504 if (Subtarget->is64Bit()) {
505 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
510 // Special handling for half-precision floating point conversions.
511 // If we don't have F16C support, then lower half float conversions
512 // into library calls.
513 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
514 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
515 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
518 // There's never any support for operations beyond MVT::f32.
519 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
520 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
521 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
522 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
524 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
525 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
527 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
529 if (Subtarget->hasPOPCNT()) {
530 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
532 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
533 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
534 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
535 if (Subtarget->is64Bit())
536 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
539 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
541 if (!Subtarget->hasMOVBE())
542 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
544 // These should be promoted to a larger select which is supported.
545 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
546 // X86 wants to expand cmov itself.
547 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
548 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
549 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
550 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
552 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
553 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
555 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
556 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
558 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
559 if (Subtarget->is64Bit()) {
560 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
563 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
564 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
565 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
566 // support continuation, user-level threading, and etc.. As a result, no
567 // other SjLj exception interfaces are implemented and please don't build
568 // your own exception handling based on them.
569 // LLVM/Clang supports zero-cost DWARF exception handling.
570 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
571 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
574 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
575 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
576 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
577 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
578 if (Subtarget->is64Bit())
579 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
580 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
581 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
582 if (Subtarget->is64Bit()) {
583 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
584 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
585 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
586 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
587 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
589 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
590 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
591 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
592 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
593 if (Subtarget->is64Bit()) {
594 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
595 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
596 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
599 if (Subtarget->hasSSE1())
600 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
602 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
604 // Expand certain atomics
605 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
607 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
608 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
609 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
612 if (Subtarget->hasCmpxchg16b()) {
613 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
616 // FIXME - use subtarget debug flags
617 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
618 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
619 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
622 if (Subtarget->is64Bit()) {
623 setExceptionPointerRegister(X86::RAX);
624 setExceptionSelectorRegister(X86::RDX);
626 setExceptionPointerRegister(X86::EAX);
627 setExceptionSelectorRegister(X86::EDX);
629 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
630 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
632 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
633 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
635 setOperationAction(ISD::TRAP, MVT::Other, Legal);
636 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
638 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
639 setOperationAction(ISD::VASTART , MVT::Other, Custom);
640 setOperationAction(ISD::VAEND , MVT::Other, Expand);
641 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
642 // TargetInfo::X86_64ABIBuiltinVaList
643 setOperationAction(ISD::VAARG , MVT::Other, Custom);
644 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
646 // TargetInfo::CharPtrBuiltinVaList
647 setOperationAction(ISD::VAARG , MVT::Other, Expand);
648 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
651 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
652 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
654 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
656 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
657 // f32 and f64 use SSE.
658 // Set up the FP register classes.
659 addRegisterClass(MVT::f32, &X86::FR32RegClass);
660 addRegisterClass(MVT::f64, &X86::FR64RegClass);
662 // Use ANDPD to simulate FABS.
663 setOperationAction(ISD::FABS , MVT::f64, Custom);
664 setOperationAction(ISD::FABS , MVT::f32, Custom);
666 // Use XORP to simulate FNEG.
667 setOperationAction(ISD::FNEG , MVT::f64, Custom);
668 setOperationAction(ISD::FNEG , MVT::f32, Custom);
670 // Use ANDPD and ORPD to simulate FCOPYSIGN.
671 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
672 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
674 // Lower this to FGETSIGNx86 plus an AND.
675 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
676 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
678 // We don't support sin/cos/fmod
679 setOperationAction(ISD::FSIN , MVT::f64, Expand);
680 setOperationAction(ISD::FCOS , MVT::f64, Expand);
681 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
682 setOperationAction(ISD::FSIN , MVT::f32, Expand);
683 setOperationAction(ISD::FCOS , MVT::f32, Expand);
684 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
686 // Expand FP immediates into loads from the stack, except for the special
688 addLegalFPImmediate(APFloat(+0.0)); // xorpd
689 addLegalFPImmediate(APFloat(+0.0f)); // xorps
690 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
691 // Use SSE for f32, x87 for f64.
692 // Set up the FP register classes.
693 addRegisterClass(MVT::f32, &X86::FR32RegClass);
694 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
696 // Use ANDPS to simulate FABS.
697 setOperationAction(ISD::FABS , MVT::f32, Custom);
699 // Use XORP to simulate FNEG.
700 setOperationAction(ISD::FNEG , MVT::f32, Custom);
702 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
704 // Use ANDPS and ORPS to simulate FCOPYSIGN.
705 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
706 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
708 // We don't support sin/cos/fmod
709 setOperationAction(ISD::FSIN , MVT::f32, Expand);
710 setOperationAction(ISD::FCOS , MVT::f32, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
713 // Special cases we handle for FP constants.
714 addLegalFPImmediate(APFloat(+0.0f)); // xorps
715 addLegalFPImmediate(APFloat(+0.0)); // FLD0
716 addLegalFPImmediate(APFloat(+1.0)); // FLD1
717 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
718 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
720 if (!TM.Options.UnsafeFPMath) {
721 setOperationAction(ISD::FSIN , MVT::f64, Expand);
722 setOperationAction(ISD::FCOS , MVT::f64, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
725 } else if (!TM.Options.UseSoftFloat) {
726 // f32 and f64 in x87.
727 // Set up the FP register classes.
728 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
729 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
731 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
732 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
733 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
734 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
736 if (!TM.Options.UnsafeFPMath) {
737 setOperationAction(ISD::FSIN , MVT::f64, Expand);
738 setOperationAction(ISD::FSIN , MVT::f32, Expand);
739 setOperationAction(ISD::FCOS , MVT::f64, Expand);
740 setOperationAction(ISD::FCOS , MVT::f32, Expand);
741 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
742 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
744 addLegalFPImmediate(APFloat(+0.0)); // FLD0
745 addLegalFPImmediate(APFloat(+1.0)); // FLD1
746 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
747 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
748 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
749 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
750 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
751 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
754 // We don't support FMA.
755 setOperationAction(ISD::FMA, MVT::f64, Expand);
756 setOperationAction(ISD::FMA, MVT::f32, Expand);
758 // Long double always uses X87.
759 if (!TM.Options.UseSoftFloat) {
760 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
761 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
762 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
764 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
765 addLegalFPImmediate(TmpFlt); // FLD0
767 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
770 APFloat TmpFlt2(+1.0);
771 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
773 addLegalFPImmediate(TmpFlt2); // FLD1
774 TmpFlt2.changeSign();
775 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
778 if (!TM.Options.UnsafeFPMath) {
779 setOperationAction(ISD::FSIN , MVT::f80, Expand);
780 setOperationAction(ISD::FCOS , MVT::f80, Expand);
781 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
784 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
785 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
786 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
787 setOperationAction(ISD::FRINT, MVT::f80, Expand);
788 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
789 setOperationAction(ISD::FMA, MVT::f80, Expand);
792 // Always use a library call for pow.
793 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
794 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
795 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
797 setOperationAction(ISD::FLOG, MVT::f80, Expand);
798 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
799 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
800 setOperationAction(ISD::FEXP, MVT::f80, Expand);
801 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
802 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
803 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
805 // First set operation action for all vector types to either promote
806 // (for widening) or expand (for scalarization). Then we will selectively
807 // turn on ones that can be effectively codegen'd.
808 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
809 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
810 MVT VT = (MVT::SimpleValueType)i;
811 setOperationAction(ISD::ADD , VT, Expand);
812 setOperationAction(ISD::SUB , VT, Expand);
813 setOperationAction(ISD::FADD, VT, Expand);
814 setOperationAction(ISD::FNEG, VT, Expand);
815 setOperationAction(ISD::FSUB, VT, Expand);
816 setOperationAction(ISD::MUL , VT, Expand);
817 setOperationAction(ISD::FMUL, VT, Expand);
818 setOperationAction(ISD::SDIV, VT, Expand);
819 setOperationAction(ISD::UDIV, VT, Expand);
820 setOperationAction(ISD::FDIV, VT, Expand);
821 setOperationAction(ISD::SREM, VT, Expand);
822 setOperationAction(ISD::UREM, VT, Expand);
823 setOperationAction(ISD::LOAD, VT, Expand);
824 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
825 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
826 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
827 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
828 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
829 setOperationAction(ISD::FABS, VT, Expand);
830 setOperationAction(ISD::FSIN, VT, Expand);
831 setOperationAction(ISD::FSINCOS, VT, Expand);
832 setOperationAction(ISD::FCOS, VT, Expand);
833 setOperationAction(ISD::FSINCOS, VT, Expand);
834 setOperationAction(ISD::FREM, VT, Expand);
835 setOperationAction(ISD::FMA, VT, Expand);
836 setOperationAction(ISD::FPOWI, VT, Expand);
837 setOperationAction(ISD::FSQRT, VT, Expand);
838 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
839 setOperationAction(ISD::FFLOOR, VT, Expand);
840 setOperationAction(ISD::FCEIL, VT, Expand);
841 setOperationAction(ISD::FTRUNC, VT, Expand);
842 setOperationAction(ISD::FRINT, VT, Expand);
843 setOperationAction(ISD::FNEARBYINT, VT, Expand);
844 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
845 setOperationAction(ISD::MULHS, VT, Expand);
846 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
847 setOperationAction(ISD::MULHU, VT, Expand);
848 setOperationAction(ISD::SDIVREM, VT, Expand);
849 setOperationAction(ISD::UDIVREM, VT, Expand);
850 setOperationAction(ISD::FPOW, VT, Expand);
851 setOperationAction(ISD::CTPOP, VT, Expand);
852 setOperationAction(ISD::CTTZ, VT, Expand);
853 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
854 setOperationAction(ISD::CTLZ, VT, Expand);
855 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
856 setOperationAction(ISD::SHL, VT, Expand);
857 setOperationAction(ISD::SRA, VT, Expand);
858 setOperationAction(ISD::SRL, VT, Expand);
859 setOperationAction(ISD::ROTL, VT, Expand);
860 setOperationAction(ISD::ROTR, VT, Expand);
861 setOperationAction(ISD::BSWAP, VT, Expand);
862 setOperationAction(ISD::SETCC, VT, Expand);
863 setOperationAction(ISD::FLOG, VT, Expand);
864 setOperationAction(ISD::FLOG2, VT, Expand);
865 setOperationAction(ISD::FLOG10, VT, Expand);
866 setOperationAction(ISD::FEXP, VT, Expand);
867 setOperationAction(ISD::FEXP2, VT, Expand);
868 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
869 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
870 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
871 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
872 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
873 setOperationAction(ISD::TRUNCATE, VT, Expand);
874 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
875 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
876 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
877 setOperationAction(ISD::VSELECT, VT, Expand);
878 setOperationAction(ISD::SELECT_CC, VT, Expand);
879 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
880 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
881 setTruncStoreAction(VT,
882 (MVT::SimpleValueType)InnerVT, Expand);
883 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
884 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
886 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
887 // we have to deal with them whether we ask for Expansion or not. Setting
888 // Expand causes its own optimisation problems though, so leave them legal.
889 if (VT.getVectorElementType() == MVT::i1)
890 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
893 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
894 // with -msoft-float, disable use of MMX as well.
895 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
896 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
897 // No operations on x86mmx supported, everything uses intrinsics.
900 // MMX-sized vectors (other than x86mmx) are expected to be expanded
901 // into smaller operations.
902 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
903 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
904 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
905 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
906 setOperationAction(ISD::AND, MVT::v8i8, Expand);
907 setOperationAction(ISD::AND, MVT::v4i16, Expand);
908 setOperationAction(ISD::AND, MVT::v2i32, Expand);
909 setOperationAction(ISD::AND, MVT::v1i64, Expand);
910 setOperationAction(ISD::OR, MVT::v8i8, Expand);
911 setOperationAction(ISD::OR, MVT::v4i16, Expand);
912 setOperationAction(ISD::OR, MVT::v2i32, Expand);
913 setOperationAction(ISD::OR, MVT::v1i64, Expand);
914 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
915 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
916 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
917 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
918 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
921 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
922 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
923 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
924 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
925 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
926 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
927 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
928 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
929 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
930 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
932 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
933 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
935 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
936 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
937 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
938 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
939 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
940 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
941 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
942 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
943 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
944 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
945 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
946 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
947 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
950 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
951 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
953 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
954 // registers cannot be used even for integer operations.
955 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
956 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
957 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
958 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
960 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
961 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
962 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
963 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
964 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
965 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
966 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
967 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
968 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
969 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
970 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
971 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
972 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
973 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
974 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
975 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
976 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
977 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
978 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
979 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
980 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
981 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
983 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
984 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
985 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
986 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
988 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
989 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
992 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
994 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
995 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
996 MVT VT = (MVT::SimpleValueType)i;
997 // Do not attempt to custom lower non-power-of-2 vectors
998 if (!isPowerOf2_32(VT.getVectorNumElements()))
1000 // Do not attempt to custom lower non-128-bit vectors
1001 if (!VT.is128BitVector())
1003 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1004 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1008 // We support custom legalizing of sext and anyext loads for specific
1009 // memory vector types which we can load as a scalar (or sequence of
1010 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1011 // loads these must work with a single scalar load.
1012 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1013 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1014 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1015 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1017 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1018 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1020 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1022 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1023 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1024 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1025 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1026 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1027 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1029 if (Subtarget->is64Bit()) {
1030 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1031 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1034 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1035 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1036 MVT VT = (MVT::SimpleValueType)i;
1038 // Do not attempt to promote non-128-bit vectors
1039 if (!VT.is128BitVector())
1042 setOperationAction(ISD::AND, VT, Promote);
1043 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1044 setOperationAction(ISD::OR, VT, Promote);
1045 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1046 setOperationAction(ISD::XOR, VT, Promote);
1047 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1048 setOperationAction(ISD::LOAD, VT, Promote);
1049 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1050 setOperationAction(ISD::SELECT, VT, Promote);
1051 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1054 // Custom lower v2i64 and v2f64 selects.
1055 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1056 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1057 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1058 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1060 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1061 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1063 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1064 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1065 // As there is no 64-bit GPR available, we need build a special custom
1066 // sequence to convert from v2i32 to v2f32.
1067 if (!Subtarget->is64Bit())
1068 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1070 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1071 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1073 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1075 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1076 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1077 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1080 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1081 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1082 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1083 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1084 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1085 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1086 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1087 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1088 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1089 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1090 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1092 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1093 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1094 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1095 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1098 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1099 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1100 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1101 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1103 // FIXME: Do we need to handle scalar-to-vector here?
1104 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1106 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1107 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1108 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1109 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1110 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1111 // There is no BLENDI for byte vectors. We don't need to custom lower
1112 // some vselects for now.
1113 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1115 // SSE41 brings specific instructions for doing vector sign extend even in
1116 // cases where we don't have SRA.
1117 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1118 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1119 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1121 // i8 and i16 vectors are custom because the source register and source
1122 // source memory operand types are not the same width. f32 vectors are
1123 // custom since the immediate controlling the insert encodes additional
1125 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1128 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1130 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1133 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1135 // FIXME: these should be Legal, but that's only for the case where
1136 // the index is constant. For now custom expand to deal with that.
1137 if (Subtarget->is64Bit()) {
1138 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1143 if (Subtarget->hasSSE2()) {
1144 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1145 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1147 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1148 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1150 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1151 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1153 // In the customized shift lowering, the legal cases in AVX2 will be
1155 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1156 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1158 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1159 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1161 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1164 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1165 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1170 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1172 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1173 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1174 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1176 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1187 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1189 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1200 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1202 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1203 // even though v8i16 is a legal type.
1204 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1205 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1206 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1208 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1209 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1210 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1212 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1213 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1215 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1217 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1218 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1220 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1223 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1224 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1226 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1229 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1231 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1233 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1235 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1236 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1237 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1238 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1240 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1241 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1242 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1243 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1244 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1245 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1246 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1247 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1248 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1249 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1250 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1251 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1253 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1254 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1255 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1256 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1257 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1258 setOperationAction(ISD::FMA, MVT::f32, Legal);
1259 setOperationAction(ISD::FMA, MVT::f64, Legal);
1262 if (Subtarget->hasInt256()) {
1263 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1264 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1265 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1266 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1268 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1269 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1270 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1271 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1273 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1274 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1275 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1276 // Don't lower v32i8 because there is no 128-bit byte mul
1278 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1279 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1280 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1281 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1283 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1284 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1286 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1287 // when we have a 256bit-wide blend with immediate.
1288 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1290 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1291 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1292 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1293 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1295 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1296 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1297 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1298 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1300 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1301 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1302 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1303 // Don't lower v32i8 because there is no 128-bit byte mul
1306 // In the customized shift lowering, the legal cases in AVX2 will be
1308 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1309 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1311 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1312 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1314 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1316 // Custom lower several nodes for 256-bit types.
1317 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1318 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1319 MVT VT = (MVT::SimpleValueType)i;
1321 // Extract subvector is special because the value type
1322 // (result) is 128-bit but the source is 256-bit wide.
1323 if (VT.is128BitVector())
1324 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1326 // Do not attempt to custom lower other non-256-bit vectors
1327 if (!VT.is256BitVector())
1330 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1331 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1332 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1334 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1335 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1336 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1339 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1340 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1341 MVT VT = (MVT::SimpleValueType)i;
1343 // Do not attempt to promote non-256-bit vectors
1344 if (!VT.is256BitVector())
1347 setOperationAction(ISD::AND, VT, Promote);
1348 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1349 setOperationAction(ISD::OR, VT, Promote);
1350 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1351 setOperationAction(ISD::XOR, VT, Promote);
1352 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1353 setOperationAction(ISD::LOAD, VT, Promote);
1354 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1355 setOperationAction(ISD::SELECT, VT, Promote);
1356 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1360 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1361 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1362 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1363 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1364 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1366 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1367 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1368 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1370 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1371 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1372 setOperationAction(ISD::XOR, MVT::i1, Legal);
1373 setOperationAction(ISD::OR, MVT::i1, Legal);
1374 setOperationAction(ISD::AND, MVT::i1, Legal);
1375 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1376 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1377 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1378 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1379 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1380 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1382 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1383 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1384 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1385 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1386 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1387 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1389 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1390 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1391 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1392 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1393 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1394 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1395 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1398 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1399 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1400 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1401 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1402 if (Subtarget->is64Bit()) {
1403 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1404 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1408 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1409 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1410 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1411 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1412 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1414 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1415 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1417 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1420 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1421 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1423 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1429 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1437 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1444 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1445 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1447 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1449 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1451 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1453 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1455 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1459 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1460 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1462 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1463 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1465 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1467 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1468 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1470 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1471 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1473 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1476 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1477 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1478 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1480 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1481 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1483 if (Subtarget->hasCDI()) {
1484 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1485 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1488 // Custom lower several nodes.
1489 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1490 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1491 MVT VT = (MVT::SimpleValueType)i;
1493 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1494 // Extract subvector is special because the value type
1495 // (result) is 256/128-bit but the source is 512-bit wide.
1496 if (VT.is128BitVector() || VT.is256BitVector())
1497 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1499 if (VT.getVectorElementType() == MVT::i1)
1500 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1502 // Do not attempt to custom lower other non-512-bit vectors
1503 if (!VT.is512BitVector())
1506 if ( EltSize >= 32) {
1507 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1508 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1509 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1510 setOperationAction(ISD::VSELECT, VT, Legal);
1511 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1512 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1513 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1516 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1517 MVT VT = (MVT::SimpleValueType)i;
1519 // Do not attempt to promote non-256-bit vectors
1520 if (!VT.is512BitVector())
1523 setOperationAction(ISD::SELECT, VT, Promote);
1524 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1528 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1529 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1530 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1532 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1533 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1535 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1536 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1537 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1538 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1540 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1541 const MVT VT = (MVT::SimpleValueType)i;
1543 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1545 // Do not attempt to promote non-256-bit vectors
1546 if (!VT.is512BitVector())
1549 if ( EltSize < 32) {
1550 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1551 setOperationAction(ISD::VSELECT, VT, Legal);
1556 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1557 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1558 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1560 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1561 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1562 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1565 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1566 // of this type with custom code.
1567 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1568 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1569 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1573 // We want to custom lower some of our intrinsics.
1574 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1577 if (!Subtarget->is64Bit())
1578 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1580 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1581 // handle type legalization for these operations here.
1583 // FIXME: We really should do custom legalization for addition and
1584 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1585 // than generic legalization for 64-bit multiplication-with-overflow, though.
1586 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1587 // Add/Sub/Mul with overflow operations are custom lowered.
1589 setOperationAction(ISD::SADDO, VT, Custom);
1590 setOperationAction(ISD::UADDO, VT, Custom);
1591 setOperationAction(ISD::SSUBO, VT, Custom);
1592 setOperationAction(ISD::USUBO, VT, Custom);
1593 setOperationAction(ISD::SMULO, VT, Custom);
1594 setOperationAction(ISD::UMULO, VT, Custom);
1598 if (!Subtarget->is64Bit()) {
1599 // These libcalls are not available in 32-bit.
1600 setLibcallName(RTLIB::SHL_I128, nullptr);
1601 setLibcallName(RTLIB::SRL_I128, nullptr);
1602 setLibcallName(RTLIB::SRA_I128, nullptr);
1605 // Combine sin / cos into one node or libcall if possible.
1606 if (Subtarget->hasSinCos()) {
1607 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1608 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1609 if (Subtarget->isTargetDarwin()) {
1610 // For MacOSX, we don't want to the normal expansion of a libcall to
1611 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1613 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1614 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1618 if (Subtarget->isTargetWin64()) {
1619 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1620 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1621 setOperationAction(ISD::SREM, MVT::i128, Custom);
1622 setOperationAction(ISD::UREM, MVT::i128, Custom);
1623 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1624 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1627 // We have target-specific dag combine patterns for the following nodes:
1628 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1629 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1630 setTargetDAGCombine(ISD::VSELECT);
1631 setTargetDAGCombine(ISD::SELECT);
1632 setTargetDAGCombine(ISD::SHL);
1633 setTargetDAGCombine(ISD::SRA);
1634 setTargetDAGCombine(ISD::SRL);
1635 setTargetDAGCombine(ISD::OR);
1636 setTargetDAGCombine(ISD::AND);
1637 setTargetDAGCombine(ISD::ADD);
1638 setTargetDAGCombine(ISD::FADD);
1639 setTargetDAGCombine(ISD::FSUB);
1640 setTargetDAGCombine(ISD::FMA);
1641 setTargetDAGCombine(ISD::SUB);
1642 setTargetDAGCombine(ISD::LOAD);
1643 setTargetDAGCombine(ISD::STORE);
1644 setTargetDAGCombine(ISD::ZERO_EXTEND);
1645 setTargetDAGCombine(ISD::ANY_EXTEND);
1646 setTargetDAGCombine(ISD::SIGN_EXTEND);
1647 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1648 setTargetDAGCombine(ISD::TRUNCATE);
1649 setTargetDAGCombine(ISD::SINT_TO_FP);
1650 setTargetDAGCombine(ISD::SETCC);
1651 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1652 setTargetDAGCombine(ISD::BUILD_VECTOR);
1653 if (Subtarget->is64Bit())
1654 setTargetDAGCombine(ISD::MUL);
1655 setTargetDAGCombine(ISD::XOR);
1657 computeRegisterProperties();
1659 // On Darwin, -Os means optimize for size without hurting performance,
1660 // do not reduce the limit.
1661 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1662 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1663 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1664 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1665 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1666 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1667 setPrefLoopAlignment(4); // 2^4 bytes.
1669 // Predictable cmov don't hurt on atom because it's in-order.
1670 PredictableSelectIsExpensive = !Subtarget->isAtom();
1672 setPrefFunctionAlignment(4); // 2^4 bytes.
1674 verifyIntrinsicTables();
1677 // This has so far only been implemented for 64-bit MachO.
1678 bool X86TargetLowering::useLoadStackGuardNode() const {
1679 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1680 Subtarget->is64Bit();
1683 TargetLoweringBase::LegalizeTypeAction
1684 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1685 if (ExperimentalVectorWideningLegalization &&
1686 VT.getVectorNumElements() != 1 &&
1687 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1688 return TypeWidenVector;
1690 return TargetLoweringBase::getPreferredVectorAction(VT);
1693 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1695 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1697 const unsigned NumElts = VT.getVectorNumElements();
1698 const EVT EltVT = VT.getVectorElementType();
1699 if (VT.is512BitVector()) {
1700 if (Subtarget->hasAVX512())
1701 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1702 EltVT == MVT::f32 || EltVT == MVT::f64)
1704 case 8: return MVT::v8i1;
1705 case 16: return MVT::v16i1;
1707 if (Subtarget->hasBWI())
1708 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1710 case 32: return MVT::v32i1;
1711 case 64: return MVT::v64i1;
1715 if (VT.is256BitVector() || VT.is128BitVector()) {
1716 if (Subtarget->hasVLX())
1717 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1718 EltVT == MVT::f32 || EltVT == MVT::f64)
1720 case 2: return MVT::v2i1;
1721 case 4: return MVT::v4i1;
1722 case 8: return MVT::v8i1;
1724 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1725 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1727 case 8: return MVT::v8i1;
1728 case 16: return MVT::v16i1;
1729 case 32: return MVT::v32i1;
1733 return VT.changeVectorElementTypeToInteger();
1736 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1737 /// the desired ByVal argument alignment.
1738 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1741 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1742 if (VTy->getBitWidth() == 128)
1744 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1745 unsigned EltAlign = 0;
1746 getMaxByValAlign(ATy->getElementType(), EltAlign);
1747 if (EltAlign > MaxAlign)
1748 MaxAlign = EltAlign;
1749 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1750 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1751 unsigned EltAlign = 0;
1752 getMaxByValAlign(STy->getElementType(i), EltAlign);
1753 if (EltAlign > MaxAlign)
1754 MaxAlign = EltAlign;
1761 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1762 /// function arguments in the caller parameter area. For X86, aggregates
1763 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1764 /// are at 4-byte boundaries.
1765 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1766 if (Subtarget->is64Bit()) {
1767 // Max of 8 and alignment of type.
1768 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1775 if (Subtarget->hasSSE1())
1776 getMaxByValAlign(Ty, Align);
1780 /// getOptimalMemOpType - Returns the target specific optimal type for load
1781 /// and store operations as a result of memset, memcpy, and memmove
1782 /// lowering. If DstAlign is zero that means it's safe to destination
1783 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1784 /// means there isn't a need to check it against alignment requirement,
1785 /// probably because the source does not need to be loaded. If 'IsMemset' is
1786 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1787 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1788 /// source is constant so it does not need to be loaded.
1789 /// It returns EVT::Other if the type should be determined using generic
1790 /// target-independent logic.
1792 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1793 unsigned DstAlign, unsigned SrcAlign,
1794 bool IsMemset, bool ZeroMemset,
1796 MachineFunction &MF) const {
1797 const Function *F = MF.getFunction();
1798 if ((!IsMemset || ZeroMemset) &&
1799 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1800 Attribute::NoImplicitFloat)) {
1802 (Subtarget->isUnalignedMemAccessFast() ||
1803 ((DstAlign == 0 || DstAlign >= 16) &&
1804 (SrcAlign == 0 || SrcAlign >= 16)))) {
1806 if (Subtarget->hasInt256())
1808 if (Subtarget->hasFp256())
1811 if (Subtarget->hasSSE2())
1813 if (Subtarget->hasSSE1())
1815 } else if (!MemcpyStrSrc && Size >= 8 &&
1816 !Subtarget->is64Bit() &&
1817 Subtarget->hasSSE2()) {
1818 // Do not use f64 to lower memcpy if source is string constant. It's
1819 // better to use i32 to avoid the loads.
1823 if (Subtarget->is64Bit() && Size >= 8)
1828 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1830 return X86ScalarSSEf32;
1831 else if (VT == MVT::f64)
1832 return X86ScalarSSEf64;
1837 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1842 *Fast = Subtarget->isUnalignedMemAccessFast();
1846 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1847 /// current function. The returned value is a member of the
1848 /// MachineJumpTableInfo::JTEntryKind enum.
1849 unsigned X86TargetLowering::getJumpTableEncoding() const {
1850 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1852 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1853 Subtarget->isPICStyleGOT())
1854 return MachineJumpTableInfo::EK_Custom32;
1856 // Otherwise, use the normal jump table encoding heuristics.
1857 return TargetLowering::getJumpTableEncoding();
1861 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1862 const MachineBasicBlock *MBB,
1863 unsigned uid,MCContext &Ctx) const{
1864 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1865 Subtarget->isPICStyleGOT());
1866 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1868 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1869 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1872 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1874 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1875 SelectionDAG &DAG) const {
1876 if (!Subtarget->is64Bit())
1877 // This doesn't have SDLoc associated with it, but is not really the
1878 // same as a Register.
1879 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1883 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1884 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1886 const MCExpr *X86TargetLowering::
1887 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1888 MCContext &Ctx) const {
1889 // X86-64 uses RIP relative addressing based on the jump table label.
1890 if (Subtarget->isPICStyleRIPRel())
1891 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1893 // Otherwise, the reference is relative to the PIC base.
1894 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1897 // FIXME: Why this routine is here? Move to RegInfo!
1898 std::pair<const TargetRegisterClass*, uint8_t>
1899 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1900 const TargetRegisterClass *RRC = nullptr;
1902 switch (VT.SimpleTy) {
1904 return TargetLowering::findRepresentativeClass(VT);
1905 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1906 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1909 RRC = &X86::VR64RegClass;
1911 case MVT::f32: case MVT::f64:
1912 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1913 case MVT::v4f32: case MVT::v2f64:
1914 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1916 RRC = &X86::VR128RegClass;
1919 return std::make_pair(RRC, Cost);
1922 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1923 unsigned &Offset) const {
1924 if (!Subtarget->isTargetLinux())
1927 if (Subtarget->is64Bit()) {
1928 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1930 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1942 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1943 unsigned DestAS) const {
1944 assert(SrcAS != DestAS && "Expected different address spaces!");
1946 return SrcAS < 256 && DestAS < 256;
1949 //===----------------------------------------------------------------------===//
1950 // Return Value Calling Convention Implementation
1951 //===----------------------------------------------------------------------===//
1953 #include "X86GenCallingConv.inc"
1956 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1957 MachineFunction &MF, bool isVarArg,
1958 const SmallVectorImpl<ISD::OutputArg> &Outs,
1959 LLVMContext &Context) const {
1960 SmallVector<CCValAssign, 16> RVLocs;
1961 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1962 return CCInfo.CheckReturn(Outs, RetCC_X86);
1965 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1966 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1971 X86TargetLowering::LowerReturn(SDValue Chain,
1972 CallingConv::ID CallConv, bool isVarArg,
1973 const SmallVectorImpl<ISD::OutputArg> &Outs,
1974 const SmallVectorImpl<SDValue> &OutVals,
1975 SDLoc dl, SelectionDAG &DAG) const {
1976 MachineFunction &MF = DAG.getMachineFunction();
1977 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1979 SmallVector<CCValAssign, 16> RVLocs;
1980 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1981 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1984 SmallVector<SDValue, 6> RetOps;
1985 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1986 // Operand #1 = Bytes To Pop
1987 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1990 // Copy the result values into the output registers.
1991 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1992 CCValAssign &VA = RVLocs[i];
1993 assert(VA.isRegLoc() && "Can only return in registers!");
1994 SDValue ValToCopy = OutVals[i];
1995 EVT ValVT = ValToCopy.getValueType();
1997 // Promote values to the appropriate types
1998 if (VA.getLocInfo() == CCValAssign::SExt)
1999 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2000 else if (VA.getLocInfo() == CCValAssign::ZExt)
2001 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2002 else if (VA.getLocInfo() == CCValAssign::AExt)
2003 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2004 else if (VA.getLocInfo() == CCValAssign::BCvt)
2005 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2007 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2008 "Unexpected FP-extend for return value.");
2010 // If this is x86-64, and we disabled SSE, we can't return FP values,
2011 // or SSE or MMX vectors.
2012 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2013 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2014 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2015 report_fatal_error("SSE register return with SSE disabled");
2017 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2018 // llvm-gcc has never done it right and no one has noticed, so this
2019 // should be OK for now.
2020 if (ValVT == MVT::f64 &&
2021 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2022 report_fatal_error("SSE2 register return with SSE2 disabled");
2024 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2025 // the RET instruction and handled by the FP Stackifier.
2026 if (VA.getLocReg() == X86::FP0 ||
2027 VA.getLocReg() == X86::FP1) {
2028 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2029 // change the value to the FP stack register class.
2030 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2031 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2032 RetOps.push_back(ValToCopy);
2033 // Don't emit a copytoreg.
2037 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2038 // which is returned in RAX / RDX.
2039 if (Subtarget->is64Bit()) {
2040 if (ValVT == MVT::x86mmx) {
2041 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2042 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2043 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2045 // If we don't have SSE2 available, convert to v4f32 so the generated
2046 // register is legal.
2047 if (!Subtarget->hasSSE2())
2048 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2053 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2054 Flag = Chain.getValue(1);
2055 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2058 // The x86-64 ABIs require that for returning structs by value we copy
2059 // the sret argument into %rax/%eax (depending on ABI) for the return.
2060 // Win32 requires us to put the sret argument to %eax as well.
2061 // We saved the argument into a virtual register in the entry block,
2062 // so now we copy the value out and into %rax/%eax.
2063 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2064 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2065 MachineFunction &MF = DAG.getMachineFunction();
2066 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2067 unsigned Reg = FuncInfo->getSRetReturnReg();
2069 "SRetReturnReg should have been set in LowerFormalArguments().");
2070 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2073 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2074 X86::RAX : X86::EAX;
2075 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2076 Flag = Chain.getValue(1);
2078 // RAX/EAX now acts like a return value.
2079 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2082 RetOps[0] = Chain; // Update chain.
2084 // Add the flag if we have it.
2086 RetOps.push_back(Flag);
2088 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2091 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2092 if (N->getNumValues() != 1)
2094 if (!N->hasNUsesOfValue(1, 0))
2097 SDValue TCChain = Chain;
2098 SDNode *Copy = *N->use_begin();
2099 if (Copy->getOpcode() == ISD::CopyToReg) {
2100 // If the copy has a glue operand, we conservatively assume it isn't safe to
2101 // perform a tail call.
2102 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2104 TCChain = Copy->getOperand(0);
2105 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2108 bool HasRet = false;
2109 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2111 if (UI->getOpcode() != X86ISD::RET_FLAG)
2113 // If we are returning more than one value, we can definitely
2114 // not make a tail call see PR19530
2115 if (UI->getNumOperands() > 4)
2117 if (UI->getNumOperands() == 4 &&
2118 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2131 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2132 ISD::NodeType ExtendKind) const {
2134 // TODO: Is this also valid on 32-bit?
2135 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2136 ReturnMVT = MVT::i8;
2138 ReturnMVT = MVT::i32;
2140 EVT MinVT = getRegisterType(Context, ReturnMVT);
2141 return VT.bitsLT(MinVT) ? MinVT : VT;
2144 /// LowerCallResult - Lower the result values of a call into the
2145 /// appropriate copies out of appropriate physical registers.
2148 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2149 CallingConv::ID CallConv, bool isVarArg,
2150 const SmallVectorImpl<ISD::InputArg> &Ins,
2151 SDLoc dl, SelectionDAG &DAG,
2152 SmallVectorImpl<SDValue> &InVals) const {
2154 // Assign locations to each value returned by this call.
2155 SmallVector<CCValAssign, 16> RVLocs;
2156 bool Is64Bit = Subtarget->is64Bit();
2157 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2159 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2161 // Copy all of the result registers out of their specified physreg.
2162 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2163 CCValAssign &VA = RVLocs[i];
2164 EVT CopyVT = VA.getValVT();
2166 // If this is x86-64, and we disabled SSE, we can't return FP values
2167 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2168 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2169 report_fatal_error("SSE register return with SSE disabled");
2172 // If we prefer to use the value in xmm registers, copy it out as f80 and
2173 // use a truncate to move it from fp stack reg to xmm reg.
2174 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2175 isScalarFPTypeInSSEReg(VA.getValVT()))
2178 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2179 CopyVT, InFlag).getValue(1);
2180 SDValue Val = Chain.getValue(0);
2182 if (CopyVT != VA.getValVT())
2183 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2184 // This truncation won't change the value.
2185 DAG.getIntPtrConstant(1));
2187 InFlag = Chain.getValue(2);
2188 InVals.push_back(Val);
2194 //===----------------------------------------------------------------------===//
2195 // C & StdCall & Fast Calling Convention implementation
2196 //===----------------------------------------------------------------------===//
2197 // StdCall calling convention seems to be standard for many Windows' API
2198 // routines and around. It differs from C calling convention just a little:
2199 // callee should clean up the stack, not caller. Symbols should be also
2200 // decorated in some fancy way :) It doesn't support any vector arguments.
2201 // For info on fast calling convention see Fast Calling Convention (tail call)
2202 // implementation LowerX86_32FastCCCallTo.
2204 /// CallIsStructReturn - Determines whether a call uses struct return
2206 enum StructReturnType {
2211 static StructReturnType
2212 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2214 return NotStructReturn;
2216 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2217 if (!Flags.isSRet())
2218 return NotStructReturn;
2219 if (Flags.isInReg())
2220 return RegStructReturn;
2221 return StackStructReturn;
2224 /// ArgsAreStructReturn - Determines whether a function uses struct
2225 /// return semantics.
2226 static StructReturnType
2227 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2229 return NotStructReturn;
2231 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2232 if (!Flags.isSRet())
2233 return NotStructReturn;
2234 if (Flags.isInReg())
2235 return RegStructReturn;
2236 return StackStructReturn;
2239 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2240 /// by "Src" to address "Dst" with size and alignment information specified by
2241 /// the specific parameter attribute. The copy will be passed as a byval
2242 /// function parameter.
2244 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2245 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2247 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2249 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2250 /*isVolatile*/false, /*AlwaysInline=*/true,
2251 MachinePointerInfo(), MachinePointerInfo());
2254 /// IsTailCallConvention - Return true if the calling convention is one that
2255 /// supports tail call optimization.
2256 static bool IsTailCallConvention(CallingConv::ID CC) {
2257 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2258 CC == CallingConv::HiPE);
2261 /// \brief Return true if the calling convention is a C calling convention.
2262 static bool IsCCallConvention(CallingConv::ID CC) {
2263 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2264 CC == CallingConv::X86_64_SysV);
2267 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2268 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2272 CallingConv::ID CalleeCC = CS.getCallingConv();
2273 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2279 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2280 /// a tailcall target by changing its ABI.
2281 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2282 bool GuaranteedTailCallOpt) {
2283 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2287 X86TargetLowering::LowerMemArgument(SDValue Chain,
2288 CallingConv::ID CallConv,
2289 const SmallVectorImpl<ISD::InputArg> &Ins,
2290 SDLoc dl, SelectionDAG &DAG,
2291 const CCValAssign &VA,
2292 MachineFrameInfo *MFI,
2294 // Create the nodes corresponding to a load from this parameter slot.
2295 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2296 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2297 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2298 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2301 // If value is passed by pointer we have address passed instead of the value
2303 if (VA.getLocInfo() == CCValAssign::Indirect)
2304 ValVT = VA.getLocVT();
2306 ValVT = VA.getValVT();
2308 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2309 // changed with more analysis.
2310 // In case of tail call optimization mark all arguments mutable. Since they
2311 // could be overwritten by lowering of arguments in case of a tail call.
2312 if (Flags.isByVal()) {
2313 unsigned Bytes = Flags.getByValSize();
2314 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2315 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2316 return DAG.getFrameIndex(FI, getPointerTy());
2318 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2319 VA.getLocMemOffset(), isImmutable);
2320 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2321 return DAG.getLoad(ValVT, dl, Chain, FIN,
2322 MachinePointerInfo::getFixedStack(FI),
2323 false, false, false, 0);
2327 // FIXME: Get this from tablegen.
2328 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2329 const X86Subtarget *Subtarget) {
2330 assert(Subtarget->is64Bit());
2332 if (Subtarget->isCallingConvWin64(CallConv)) {
2333 static const MCPhysReg GPR64ArgRegsWin64[] = {
2334 X86::RCX, X86::RDX, X86::R8, X86::R9
2336 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2339 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2340 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2342 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2345 // FIXME: Get this from tablegen.
2346 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2347 CallingConv::ID CallConv,
2348 const X86Subtarget *Subtarget) {
2349 assert(Subtarget->is64Bit());
2350 if (Subtarget->isCallingConvWin64(CallConv)) {
2351 // The XMM registers which might contain var arg parameters are shadowed
2352 // in their paired GPR. So we only need to save the GPR to their home
2354 // TODO: __vectorcall will change this.
2358 const Function *Fn = MF.getFunction();
2359 bool NoImplicitFloatOps = Fn->getAttributes().
2360 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2361 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2362 "SSE register cannot be used when SSE is disabled!");
2363 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2364 !Subtarget->hasSSE1())
2365 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2369 static const MCPhysReg XMMArgRegs64Bit[] = {
2370 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2371 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2373 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2377 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2378 CallingConv::ID CallConv,
2380 const SmallVectorImpl<ISD::InputArg> &Ins,
2383 SmallVectorImpl<SDValue> &InVals)
2385 MachineFunction &MF = DAG.getMachineFunction();
2386 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2388 const Function* Fn = MF.getFunction();
2389 if (Fn->hasExternalLinkage() &&
2390 Subtarget->isTargetCygMing() &&
2391 Fn->getName() == "main")
2392 FuncInfo->setForceFramePointer(true);
2394 MachineFrameInfo *MFI = MF.getFrameInfo();
2395 bool Is64Bit = Subtarget->is64Bit();
2396 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2398 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2399 "Var args not supported with calling convention fastcc, ghc or hipe");
2401 // Assign locations to all of the incoming arguments.
2402 SmallVector<CCValAssign, 16> ArgLocs;
2403 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2405 // Allocate shadow area for Win64
2407 CCInfo.AllocateStack(32, 8);
2409 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2411 unsigned LastVal = ~0U;
2413 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2414 CCValAssign &VA = ArgLocs[i];
2415 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2417 assert(VA.getValNo() != LastVal &&
2418 "Don't support value assigned to multiple locs yet");
2420 LastVal = VA.getValNo();
2422 if (VA.isRegLoc()) {
2423 EVT RegVT = VA.getLocVT();
2424 const TargetRegisterClass *RC;
2425 if (RegVT == MVT::i32)
2426 RC = &X86::GR32RegClass;
2427 else if (Is64Bit && RegVT == MVT::i64)
2428 RC = &X86::GR64RegClass;
2429 else if (RegVT == MVT::f32)
2430 RC = &X86::FR32RegClass;
2431 else if (RegVT == MVT::f64)
2432 RC = &X86::FR64RegClass;
2433 else if (RegVT.is512BitVector())
2434 RC = &X86::VR512RegClass;
2435 else if (RegVT.is256BitVector())
2436 RC = &X86::VR256RegClass;
2437 else if (RegVT.is128BitVector())
2438 RC = &X86::VR128RegClass;
2439 else if (RegVT == MVT::x86mmx)
2440 RC = &X86::VR64RegClass;
2441 else if (RegVT == MVT::i1)
2442 RC = &X86::VK1RegClass;
2443 else if (RegVT == MVT::v8i1)
2444 RC = &X86::VK8RegClass;
2445 else if (RegVT == MVT::v16i1)
2446 RC = &X86::VK16RegClass;
2447 else if (RegVT == MVT::v32i1)
2448 RC = &X86::VK32RegClass;
2449 else if (RegVT == MVT::v64i1)
2450 RC = &X86::VK64RegClass;
2452 llvm_unreachable("Unknown argument type!");
2454 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2455 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2457 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2458 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2460 if (VA.getLocInfo() == CCValAssign::SExt)
2461 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2462 DAG.getValueType(VA.getValVT()));
2463 else if (VA.getLocInfo() == CCValAssign::ZExt)
2464 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2465 DAG.getValueType(VA.getValVT()));
2466 else if (VA.getLocInfo() == CCValAssign::BCvt)
2467 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2469 if (VA.isExtInLoc()) {
2470 // Handle MMX values passed in XMM regs.
2471 if (RegVT.isVector())
2472 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2474 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2477 assert(VA.isMemLoc());
2478 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2481 // If value is passed via pointer - do a load.
2482 if (VA.getLocInfo() == CCValAssign::Indirect)
2483 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2484 MachinePointerInfo(), false, false, false, 0);
2486 InVals.push_back(ArgValue);
2489 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2490 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2491 // The x86-64 ABIs require that for returning structs by value we copy
2492 // the sret argument into %rax/%eax (depending on ABI) for the return.
2493 // Win32 requires us to put the sret argument to %eax as well.
2494 // Save the argument into a virtual register so that we can access it
2495 // from the return points.
2496 if (Ins[i].Flags.isSRet()) {
2497 unsigned Reg = FuncInfo->getSRetReturnReg();
2499 MVT PtrTy = getPointerTy();
2500 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2501 FuncInfo->setSRetReturnReg(Reg);
2503 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2504 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2510 unsigned StackSize = CCInfo.getNextStackOffset();
2511 // Align stack specially for tail calls.
2512 if (FuncIsMadeTailCallSafe(CallConv,
2513 MF.getTarget().Options.GuaranteedTailCallOpt))
2514 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2516 // If the function takes variable number of arguments, make a frame index for
2517 // the start of the first vararg value... for expansion of llvm.va_start. We
2518 // can skip this if there are no va_start calls.
2519 if (MFI->hasVAStart() &&
2520 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2521 CallConv != CallingConv::X86_ThisCall))) {
2522 FuncInfo->setVarArgsFrameIndex(
2523 MFI->CreateFixedObject(1, StackSize, true));
2526 // 64-bit calling conventions support varargs and register parameters, so we
2527 // have to do extra work to spill them in the prologue or forward them to
2529 if (Is64Bit && isVarArg &&
2530 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2531 // Find the first unallocated argument registers.
2532 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2533 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2534 unsigned NumIntRegs =
2535 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2536 unsigned NumXMMRegs =
2537 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2538 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2539 "SSE register cannot be used when SSE is disabled!");
2541 // Gather all the live in physical registers.
2542 SmallVector<SDValue, 6> LiveGPRs;
2543 SmallVector<SDValue, 8> LiveXMMRegs;
2545 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2546 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2548 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2550 if (!ArgXMMs.empty()) {
2551 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2552 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2553 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2554 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2555 LiveXMMRegs.push_back(
2556 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2560 // Store them to the va_list returned by va_start.
2561 if (MFI->hasVAStart()) {
2563 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2564 // Get to the caller-allocated home save location. Add 8 to account
2565 // for the return address.
2566 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2567 FuncInfo->setRegSaveFrameIndex(
2568 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2569 // Fixup to set vararg frame on shadow area (4 x i64).
2571 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2573 // For X86-64, if there are vararg parameters that are passed via
2574 // registers, then we must store them to their spots on the stack so
2575 // they may be loaded by deferencing the result of va_next.
2576 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2577 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2578 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2579 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2582 // Store the integer parameter registers.
2583 SmallVector<SDValue, 8> MemOps;
2584 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2586 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2587 for (SDValue Val : LiveGPRs) {
2588 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2589 DAG.getIntPtrConstant(Offset));
2591 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2592 MachinePointerInfo::getFixedStack(
2593 FuncInfo->getRegSaveFrameIndex(), Offset),
2595 MemOps.push_back(Store);
2599 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2600 // Now store the XMM (fp + vector) parameter registers.
2601 SmallVector<SDValue, 12> SaveXMMOps;
2602 SaveXMMOps.push_back(Chain);
2603 SaveXMMOps.push_back(ALVal);
2604 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2605 FuncInfo->getRegSaveFrameIndex()));
2606 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2607 FuncInfo->getVarArgsFPOffset()));
2608 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2610 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2611 MVT::Other, SaveXMMOps));
2614 if (!MemOps.empty())
2615 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2617 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2618 // to the liveout set on a musttail call.
2619 assert(MFI->hasMustTailInVarArgFunc());
2620 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2621 typedef X86MachineFunctionInfo::Forward Forward;
2623 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2625 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2626 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2627 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2630 if (!ArgXMMs.empty()) {
2632 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2633 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2634 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2636 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2638 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2639 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2641 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2647 // Some CCs need callee pop.
2648 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2649 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2650 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2652 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2653 // If this is an sret function, the return should pop the hidden pointer.
2654 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2655 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2656 argsAreStructReturn(Ins) == StackStructReturn)
2657 FuncInfo->setBytesToPopOnReturn(4);
2661 // RegSaveFrameIndex is X86-64 only.
2662 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2663 if (CallConv == CallingConv::X86_FastCall ||
2664 CallConv == CallingConv::X86_ThisCall)
2665 // fastcc functions can't have varargs.
2666 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2669 FuncInfo->setArgumentStackSize(StackSize);
2675 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2676 SDValue StackPtr, SDValue Arg,
2677 SDLoc dl, SelectionDAG &DAG,
2678 const CCValAssign &VA,
2679 ISD::ArgFlagsTy Flags) const {
2680 unsigned LocMemOffset = VA.getLocMemOffset();
2681 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2682 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2683 if (Flags.isByVal())
2684 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2686 return DAG.getStore(Chain, dl, Arg, PtrOff,
2687 MachinePointerInfo::getStack(LocMemOffset),
2691 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2692 /// optimization is performed and it is required.
2694 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2695 SDValue &OutRetAddr, SDValue Chain,
2696 bool IsTailCall, bool Is64Bit,
2697 int FPDiff, SDLoc dl) const {
2698 // Adjust the Return address stack slot.
2699 EVT VT = getPointerTy();
2700 OutRetAddr = getReturnAddressFrameIndex(DAG);
2702 // Load the "old" Return address.
2703 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2704 false, false, false, 0);
2705 return SDValue(OutRetAddr.getNode(), 1);
2708 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2709 /// optimization is performed and it is required (FPDiff!=0).
2710 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2711 SDValue Chain, SDValue RetAddrFrIdx,
2712 EVT PtrVT, unsigned SlotSize,
2713 int FPDiff, SDLoc dl) {
2714 // Store the return address to the appropriate stack slot.
2715 if (!FPDiff) return Chain;
2716 // Calculate the new stack slot for the return address.
2717 int NewReturnAddrFI =
2718 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2720 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2721 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2722 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2728 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2729 SmallVectorImpl<SDValue> &InVals) const {
2730 SelectionDAG &DAG = CLI.DAG;
2732 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2733 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2734 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2735 SDValue Chain = CLI.Chain;
2736 SDValue Callee = CLI.Callee;
2737 CallingConv::ID CallConv = CLI.CallConv;
2738 bool &isTailCall = CLI.IsTailCall;
2739 bool isVarArg = CLI.IsVarArg;
2741 MachineFunction &MF = DAG.getMachineFunction();
2742 bool Is64Bit = Subtarget->is64Bit();
2743 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2744 StructReturnType SR = callIsStructReturn(Outs);
2745 bool IsSibcall = false;
2746 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2748 if (MF.getTarget().Options.DisableTailCalls)
2751 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2753 // Force this to be a tail call. The verifier rules are enough to ensure
2754 // that we can lower this successfully without moving the return address
2757 } else if (isTailCall) {
2758 // Check if it's really possible to do a tail call.
2759 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2760 isVarArg, SR != NotStructReturn,
2761 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2762 Outs, OutVals, Ins, DAG);
2764 // Sibcalls are automatically detected tailcalls which do not require
2766 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2773 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2774 "Var args not supported with calling convention fastcc, ghc or hipe");
2776 // Analyze operands of the call, assigning locations to each operand.
2777 SmallVector<CCValAssign, 16> ArgLocs;
2778 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2780 // Allocate shadow area for Win64
2782 CCInfo.AllocateStack(32, 8);
2784 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2786 // Get a count of how many bytes are to be pushed on the stack.
2787 unsigned NumBytes = CCInfo.getNextStackOffset();
2789 // This is a sibcall. The memory operands are available in caller's
2790 // own caller's stack.
2792 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2793 IsTailCallConvention(CallConv))
2794 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2797 if (isTailCall && !IsSibcall && !IsMustTail) {
2798 // Lower arguments at fp - stackoffset + fpdiff.
2799 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2801 FPDiff = NumBytesCallerPushed - NumBytes;
2803 // Set the delta of movement of the returnaddr stackslot.
2804 // But only set if delta is greater than previous delta.
2805 if (FPDiff < X86Info->getTCReturnAddrDelta())
2806 X86Info->setTCReturnAddrDelta(FPDiff);
2809 unsigned NumBytesToPush = NumBytes;
2810 unsigned NumBytesToPop = NumBytes;
2812 // If we have an inalloca argument, all stack space has already been allocated
2813 // for us and be right at the top of the stack. We don't support multiple
2814 // arguments passed in memory when using inalloca.
2815 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2817 if (!ArgLocs.back().isMemLoc())
2818 report_fatal_error("cannot use inalloca attribute on a register "
2820 if (ArgLocs.back().getLocMemOffset() != 0)
2821 report_fatal_error("any parameter with the inalloca attribute must be "
2822 "the only memory argument");
2826 Chain = DAG.getCALLSEQ_START(
2827 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2829 SDValue RetAddrFrIdx;
2830 // Load return address for tail calls.
2831 if (isTailCall && FPDiff)
2832 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2833 Is64Bit, FPDiff, dl);
2835 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2836 SmallVector<SDValue, 8> MemOpChains;
2839 // Walk the register/memloc assignments, inserting copies/loads. In the case
2840 // of tail call optimization arguments are handle later.
2841 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2842 DAG.getSubtarget().getRegisterInfo());
2843 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2844 // Skip inalloca arguments, they have already been written.
2845 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2846 if (Flags.isInAlloca())
2849 CCValAssign &VA = ArgLocs[i];
2850 EVT RegVT = VA.getLocVT();
2851 SDValue Arg = OutVals[i];
2852 bool isByVal = Flags.isByVal();
2854 // Promote the value if needed.
2855 switch (VA.getLocInfo()) {
2856 default: llvm_unreachable("Unknown loc info!");
2857 case CCValAssign::Full: break;
2858 case CCValAssign::SExt:
2859 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2861 case CCValAssign::ZExt:
2862 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2864 case CCValAssign::AExt:
2865 if (RegVT.is128BitVector()) {
2866 // Special case: passing MMX values in XMM registers.
2867 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2868 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2869 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2871 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2873 case CCValAssign::BCvt:
2874 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2876 case CCValAssign::Indirect: {
2877 // Store the argument.
2878 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2879 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2880 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2881 MachinePointerInfo::getFixedStack(FI),
2888 if (VA.isRegLoc()) {
2889 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2890 if (isVarArg && IsWin64) {
2891 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2892 // shadow reg if callee is a varargs function.
2893 unsigned ShadowReg = 0;
2894 switch (VA.getLocReg()) {
2895 case X86::XMM0: ShadowReg = X86::RCX; break;
2896 case X86::XMM1: ShadowReg = X86::RDX; break;
2897 case X86::XMM2: ShadowReg = X86::R8; break;
2898 case X86::XMM3: ShadowReg = X86::R9; break;
2901 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2903 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2904 assert(VA.isMemLoc());
2905 if (!StackPtr.getNode())
2906 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2908 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2909 dl, DAG, VA, Flags));
2913 if (!MemOpChains.empty())
2914 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2916 if (Subtarget->isPICStyleGOT()) {
2917 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2920 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2921 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2923 // If we are tail calling and generating PIC/GOT style code load the
2924 // address of the callee into ECX. The value in ecx is used as target of
2925 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2926 // for tail calls on PIC/GOT architectures. Normally we would just put the
2927 // address of GOT into ebx and then call target@PLT. But for tail calls
2928 // ebx would be restored (since ebx is callee saved) before jumping to the
2931 // Note: The actual moving to ECX is done further down.
2932 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2933 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2934 !G->getGlobal()->hasProtectedVisibility())
2935 Callee = LowerGlobalAddress(Callee, DAG);
2936 else if (isa<ExternalSymbolSDNode>(Callee))
2937 Callee = LowerExternalSymbol(Callee, DAG);
2941 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2942 // From AMD64 ABI document:
2943 // For calls that may call functions that use varargs or stdargs
2944 // (prototype-less calls or calls to functions containing ellipsis (...) in
2945 // the declaration) %al is used as hidden argument to specify the number
2946 // of SSE registers used. The contents of %al do not need to match exactly
2947 // the number of registers, but must be an ubound on the number of SSE
2948 // registers used and is in the range 0 - 8 inclusive.
2950 // Count the number of XMM registers allocated.
2951 static const MCPhysReg XMMArgRegs[] = {
2952 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2953 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2955 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2956 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2957 && "SSE registers cannot be used when SSE is disabled");
2959 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2960 DAG.getConstant(NumXMMRegs, MVT::i8)));
2963 if (Is64Bit && isVarArg && IsMustTail) {
2964 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2965 for (const auto &F : Forwards) {
2966 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2967 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2971 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2972 // don't need this because the eligibility check rejects calls that require
2973 // shuffling arguments passed in memory.
2974 if (!IsSibcall && isTailCall) {
2975 // Force all the incoming stack arguments to be loaded from the stack
2976 // before any new outgoing arguments are stored to the stack, because the
2977 // outgoing stack slots may alias the incoming argument stack slots, and
2978 // the alias isn't otherwise explicit. This is slightly more conservative
2979 // than necessary, because it means that each store effectively depends
2980 // on every argument instead of just those arguments it would clobber.
2981 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2983 SmallVector<SDValue, 8> MemOpChains2;
2986 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2987 CCValAssign &VA = ArgLocs[i];
2990 assert(VA.isMemLoc());
2991 SDValue Arg = OutVals[i];
2992 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2993 // Skip inalloca arguments. They don't require any work.
2994 if (Flags.isInAlloca())
2996 // Create frame index.
2997 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2998 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2999 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3000 FIN = DAG.getFrameIndex(FI, getPointerTy());
3002 if (Flags.isByVal()) {
3003 // Copy relative to framepointer.
3004 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3005 if (!StackPtr.getNode())
3006 StackPtr = DAG.getCopyFromReg(Chain, dl,
3007 RegInfo->getStackRegister(),
3009 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3011 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3015 // Store relative to framepointer.
3016 MemOpChains2.push_back(
3017 DAG.getStore(ArgChain, dl, Arg, FIN,
3018 MachinePointerInfo::getFixedStack(FI),
3023 if (!MemOpChains2.empty())
3024 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3026 // Store the return address to the appropriate stack slot.
3027 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3028 getPointerTy(), RegInfo->getSlotSize(),
3032 // Build a sequence of copy-to-reg nodes chained together with token chain
3033 // and flag operands which copy the outgoing args into registers.
3035 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3036 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3037 RegsToPass[i].second, InFlag);
3038 InFlag = Chain.getValue(1);
3041 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3042 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3043 // In the 64-bit large code model, we have to make all calls
3044 // through a register, since the call instruction's 32-bit
3045 // pc-relative offset may not be large enough to hold the whole
3047 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3048 // If the callee is a GlobalAddress node (quite common, every direct call
3049 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3052 // We should use extra load for direct calls to dllimported functions in
3054 const GlobalValue *GV = G->getGlobal();
3055 if (!GV->hasDLLImportStorageClass()) {
3056 unsigned char OpFlags = 0;
3057 bool ExtraLoad = false;
3058 unsigned WrapperKind = ISD::DELETED_NODE;
3060 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3061 // external symbols most go through the PLT in PIC mode. If the symbol
3062 // has hidden or protected visibility, or if it is static or local, then
3063 // we don't need to use the PLT - we can directly call it.
3064 if (Subtarget->isTargetELF() &&
3065 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3066 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3067 OpFlags = X86II::MO_PLT;
3068 } else if (Subtarget->isPICStyleStubAny() &&
3069 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3070 (!Subtarget->getTargetTriple().isMacOSX() ||
3071 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3072 // PC-relative references to external symbols should go through $stub,
3073 // unless we're building with the leopard linker or later, which
3074 // automatically synthesizes these stubs.
3075 OpFlags = X86II::MO_DARWIN_STUB;
3076 } else if (Subtarget->isPICStyleRIPRel() &&
3077 isa<Function>(GV) &&
3078 cast<Function>(GV)->getAttributes().
3079 hasAttribute(AttributeSet::FunctionIndex,
3080 Attribute::NonLazyBind)) {
3081 // If the function is marked as non-lazy, generate an indirect call
3082 // which loads from the GOT directly. This avoids runtime overhead
3083 // at the cost of eager binding (and one extra byte of encoding).
3084 OpFlags = X86II::MO_GOTPCREL;
3085 WrapperKind = X86ISD::WrapperRIP;
3089 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3090 G->getOffset(), OpFlags);
3092 // Add a wrapper if needed.
3093 if (WrapperKind != ISD::DELETED_NODE)
3094 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3095 // Add extra indirection if needed.
3097 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3098 MachinePointerInfo::getGOT(),
3099 false, false, false, 0);
3101 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3102 unsigned char OpFlags = 0;
3104 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3105 // external symbols should go through the PLT.
3106 if (Subtarget->isTargetELF() &&
3107 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3108 OpFlags = X86II::MO_PLT;
3109 } else if (Subtarget->isPICStyleStubAny() &&
3110 (!Subtarget->getTargetTriple().isMacOSX() ||
3111 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3112 // PC-relative references to external symbols should go through $stub,
3113 // unless we're building with the leopard linker or later, which
3114 // automatically synthesizes these stubs.
3115 OpFlags = X86II::MO_DARWIN_STUB;
3118 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3120 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3121 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3122 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3125 // Returns a chain & a flag for retval copy to use.
3126 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3127 SmallVector<SDValue, 8> Ops;
3129 if (!IsSibcall && isTailCall) {
3130 Chain = DAG.getCALLSEQ_END(Chain,
3131 DAG.getIntPtrConstant(NumBytesToPop, true),
3132 DAG.getIntPtrConstant(0, true), InFlag, dl);
3133 InFlag = Chain.getValue(1);
3136 Ops.push_back(Chain);
3137 Ops.push_back(Callee);
3140 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3142 // Add argument registers to the end of the list so that they are known live
3144 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3145 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3146 RegsToPass[i].second.getValueType()));
3148 // Add a register mask operand representing the call-preserved registers.
3149 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3150 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3151 assert(Mask && "Missing call preserved mask for calling convention");
3152 Ops.push_back(DAG.getRegisterMask(Mask));
3154 if (InFlag.getNode())
3155 Ops.push_back(InFlag);
3159 //// If this is the first return lowered for this function, add the regs
3160 //// to the liveout set for the function.
3161 // This isn't right, although it's probably harmless on x86; liveouts
3162 // should be computed from returns not tail calls. Consider a void
3163 // function making a tail call to a function returning int.
3164 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3167 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3168 InFlag = Chain.getValue(1);
3170 // Create the CALLSEQ_END node.
3171 unsigned NumBytesForCalleeToPop;
3172 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3173 DAG.getTarget().Options.GuaranteedTailCallOpt))
3174 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3175 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3176 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3177 SR == StackStructReturn)
3178 // If this is a call to a struct-return function, the callee
3179 // pops the hidden struct pointer, so we have to push it back.
3180 // This is common for Darwin/X86, Linux & Mingw32 targets.
3181 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3182 NumBytesForCalleeToPop = 4;
3184 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3186 // Returns a flag for retval copy to use.
3188 Chain = DAG.getCALLSEQ_END(Chain,
3189 DAG.getIntPtrConstant(NumBytesToPop, true),
3190 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3193 InFlag = Chain.getValue(1);
3196 // Handle result values, copying them out of physregs into vregs that we
3198 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3199 Ins, dl, DAG, InVals);
3202 //===----------------------------------------------------------------------===//
3203 // Fast Calling Convention (tail call) implementation
3204 //===----------------------------------------------------------------------===//
3206 // Like std call, callee cleans arguments, convention except that ECX is
3207 // reserved for storing the tail called function address. Only 2 registers are
3208 // free for argument passing (inreg). Tail call optimization is performed
3210 // * tailcallopt is enabled
3211 // * caller/callee are fastcc
3212 // On X86_64 architecture with GOT-style position independent code only local
3213 // (within module) calls are supported at the moment.
3214 // To keep the stack aligned according to platform abi the function
3215 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3216 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3217 // If a tail called function callee has more arguments than the caller the
3218 // caller needs to make sure that there is room to move the RETADDR to. This is
3219 // achieved by reserving an area the size of the argument delta right after the
3220 // original RETADDR, but before the saved framepointer or the spilled registers
3221 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3233 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3234 /// for a 16 byte align requirement.
3236 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3237 SelectionDAG& DAG) const {
3238 MachineFunction &MF = DAG.getMachineFunction();
3239 const TargetMachine &TM = MF.getTarget();
3240 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3241 TM.getSubtargetImpl()->getRegisterInfo());
3242 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3243 unsigned StackAlignment = TFI.getStackAlignment();
3244 uint64_t AlignMask = StackAlignment - 1;
3245 int64_t Offset = StackSize;
3246 unsigned SlotSize = RegInfo->getSlotSize();
3247 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3248 // Number smaller than 12 so just add the difference.
3249 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3251 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3252 Offset = ((~AlignMask) & Offset) + StackAlignment +
3253 (StackAlignment-SlotSize);
3258 /// MatchingStackOffset - Return true if the given stack call argument is
3259 /// already available in the same position (relatively) of the caller's
3260 /// incoming argument stack.
3262 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3263 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3264 const X86InstrInfo *TII) {
3265 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3267 if (Arg.getOpcode() == ISD::CopyFromReg) {
3268 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3269 if (!TargetRegisterInfo::isVirtualRegister(VR))
3271 MachineInstr *Def = MRI->getVRegDef(VR);
3274 if (!Flags.isByVal()) {
3275 if (!TII->isLoadFromStackSlot(Def, FI))
3278 unsigned Opcode = Def->getOpcode();
3279 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3280 Def->getOperand(1).isFI()) {
3281 FI = Def->getOperand(1).getIndex();
3282 Bytes = Flags.getByValSize();
3286 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3287 if (Flags.isByVal())
3288 // ByVal argument is passed in as a pointer but it's now being
3289 // dereferenced. e.g.
3290 // define @foo(%struct.X* %A) {
3291 // tail call @bar(%struct.X* byval %A)
3294 SDValue Ptr = Ld->getBasePtr();
3295 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3298 FI = FINode->getIndex();
3299 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3300 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3301 FI = FINode->getIndex();
3302 Bytes = Flags.getByValSize();
3306 assert(FI != INT_MAX);
3307 if (!MFI->isFixedObjectIndex(FI))
3309 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3312 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3313 /// for tail call optimization. Targets which want to do tail call
3314 /// optimization should implement this function.
3316 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3317 CallingConv::ID CalleeCC,
3319 bool isCalleeStructRet,
3320 bool isCallerStructRet,
3322 const SmallVectorImpl<ISD::OutputArg> &Outs,
3323 const SmallVectorImpl<SDValue> &OutVals,
3324 const SmallVectorImpl<ISD::InputArg> &Ins,
3325 SelectionDAG &DAG) const {
3326 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3329 // If -tailcallopt is specified, make fastcc functions tail-callable.
3330 const MachineFunction &MF = DAG.getMachineFunction();
3331 const Function *CallerF = MF.getFunction();
3333 // If the function return type is x86_fp80 and the callee return type is not,
3334 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3335 // perform a tailcall optimization here.
3336 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3339 CallingConv::ID CallerCC = CallerF->getCallingConv();
3340 bool CCMatch = CallerCC == CalleeCC;
3341 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3342 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3344 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3345 if (IsTailCallConvention(CalleeCC) && CCMatch)
3350 // Look for obvious safe cases to perform tail call optimization that do not
3351 // require ABI changes. This is what gcc calls sibcall.
3353 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3354 // emit a special epilogue.
3355 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3356 DAG.getSubtarget().getRegisterInfo());
3357 if (RegInfo->needsStackRealignment(MF))
3360 // Also avoid sibcall optimization if either caller or callee uses struct
3361 // return semantics.
3362 if (isCalleeStructRet || isCallerStructRet)
3365 // An stdcall/thiscall caller is expected to clean up its arguments; the
3366 // callee isn't going to do that.
3367 // FIXME: this is more restrictive than needed. We could produce a tailcall
3368 // when the stack adjustment matches. For example, with a thiscall that takes
3369 // only one argument.
3370 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3371 CallerCC == CallingConv::X86_ThisCall))
3374 // Do not sibcall optimize vararg calls unless all arguments are passed via
3376 if (isVarArg && !Outs.empty()) {
3378 // Optimizing for varargs on Win64 is unlikely to be safe without
3379 // additional testing.
3380 if (IsCalleeWin64 || IsCallerWin64)
3383 SmallVector<CCValAssign, 16> ArgLocs;
3384 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3387 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3388 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3389 if (!ArgLocs[i].isRegLoc())
3393 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3394 // stack. Therefore, if it's not used by the call it is not safe to optimize
3395 // this into a sibcall.
3396 bool Unused = false;
3397 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3404 SmallVector<CCValAssign, 16> RVLocs;
3405 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3407 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3408 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3409 CCValAssign &VA = RVLocs[i];
3410 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3415 // If the calling conventions do not match, then we'd better make sure the
3416 // results are returned in the same way as what the caller expects.
3418 SmallVector<CCValAssign, 16> RVLocs1;
3419 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3421 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3423 SmallVector<CCValAssign, 16> RVLocs2;
3424 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3426 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3428 if (RVLocs1.size() != RVLocs2.size())
3430 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3431 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3433 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3435 if (RVLocs1[i].isRegLoc()) {
3436 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3439 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3445 // If the callee takes no arguments then go on to check the results of the
3447 if (!Outs.empty()) {
3448 // Check if stack adjustment is needed. For now, do not do this if any
3449 // argument is passed on the stack.
3450 SmallVector<CCValAssign, 16> ArgLocs;
3451 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3454 // Allocate shadow area for Win64
3456 CCInfo.AllocateStack(32, 8);
3458 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3459 if (CCInfo.getNextStackOffset()) {
3460 MachineFunction &MF = DAG.getMachineFunction();
3461 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3464 // Check if the arguments are already laid out in the right way as
3465 // the caller's fixed stack objects.
3466 MachineFrameInfo *MFI = MF.getFrameInfo();
3467 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3468 const X86InstrInfo *TII =
3469 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3470 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3471 CCValAssign &VA = ArgLocs[i];
3472 SDValue Arg = OutVals[i];
3473 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3474 if (VA.getLocInfo() == CCValAssign::Indirect)
3476 if (!VA.isRegLoc()) {
3477 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3484 // If the tailcall address may be in a register, then make sure it's
3485 // possible to register allocate for it. In 32-bit, the call address can
3486 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3487 // callee-saved registers are restored. These happen to be the same
3488 // registers used to pass 'inreg' arguments so watch out for those.
3489 if (!Subtarget->is64Bit() &&
3490 ((!isa<GlobalAddressSDNode>(Callee) &&
3491 !isa<ExternalSymbolSDNode>(Callee)) ||
3492 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3493 unsigned NumInRegs = 0;
3494 // In PIC we need an extra register to formulate the address computation
3496 unsigned MaxInRegs =
3497 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3499 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3500 CCValAssign &VA = ArgLocs[i];
3503 unsigned Reg = VA.getLocReg();
3506 case X86::EAX: case X86::EDX: case X86::ECX:
3507 if (++NumInRegs == MaxInRegs)
3519 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3520 const TargetLibraryInfo *libInfo) const {
3521 return X86::createFastISel(funcInfo, libInfo);
3524 //===----------------------------------------------------------------------===//
3525 // Other Lowering Hooks
3526 //===----------------------------------------------------------------------===//
3528 static bool MayFoldLoad(SDValue Op) {
3529 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3532 static bool MayFoldIntoStore(SDValue Op) {
3533 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3536 static bool isTargetShuffle(unsigned Opcode) {
3538 default: return false;
3539 case X86ISD::BLENDI:
3540 case X86ISD::PSHUFB:
3541 case X86ISD::PSHUFD:
3542 case X86ISD::PSHUFHW:
3543 case X86ISD::PSHUFLW:
3545 case X86ISD::PALIGNR:
3546 case X86ISD::MOVLHPS:
3547 case X86ISD::MOVLHPD:
3548 case X86ISD::MOVHLPS:
3549 case X86ISD::MOVLPS:
3550 case X86ISD::MOVLPD:
3551 case X86ISD::MOVSHDUP:
3552 case X86ISD::MOVSLDUP:
3553 case X86ISD::MOVDDUP:
3556 case X86ISD::UNPCKL:
3557 case X86ISD::UNPCKH:
3558 case X86ISD::VPERMILPI:
3559 case X86ISD::VPERM2X128:
3560 case X86ISD::VPERMI:
3565 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3566 SDValue V1, SelectionDAG &DAG) {
3568 default: llvm_unreachable("Unknown x86 shuffle node");
3569 case X86ISD::MOVSHDUP:
3570 case X86ISD::MOVSLDUP:
3571 case X86ISD::MOVDDUP:
3572 return DAG.getNode(Opc, dl, VT, V1);
3576 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3577 SDValue V1, unsigned TargetMask,
3578 SelectionDAG &DAG) {
3580 default: llvm_unreachable("Unknown x86 shuffle node");
3581 case X86ISD::PSHUFD:
3582 case X86ISD::PSHUFHW:
3583 case X86ISD::PSHUFLW:
3584 case X86ISD::VPERMILPI:
3585 case X86ISD::VPERMI:
3586 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3590 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3591 SDValue V1, SDValue V2, unsigned TargetMask,
3592 SelectionDAG &DAG) {
3594 default: llvm_unreachable("Unknown x86 shuffle node");
3595 case X86ISD::PALIGNR:
3596 case X86ISD::VALIGN:
3598 case X86ISD::VPERM2X128:
3599 return DAG.getNode(Opc, dl, VT, V1, V2,
3600 DAG.getConstant(TargetMask, MVT::i8));
3604 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3605 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3607 default: llvm_unreachable("Unknown x86 shuffle node");
3608 case X86ISD::MOVLHPS:
3609 case X86ISD::MOVLHPD:
3610 case X86ISD::MOVHLPS:
3611 case X86ISD::MOVLPS:
3612 case X86ISD::MOVLPD:
3615 case X86ISD::UNPCKL:
3616 case X86ISD::UNPCKH:
3617 return DAG.getNode(Opc, dl, VT, V1, V2);
3621 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3622 MachineFunction &MF = DAG.getMachineFunction();
3623 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3624 DAG.getSubtarget().getRegisterInfo());
3625 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3626 int ReturnAddrIndex = FuncInfo->getRAIndex();
3628 if (ReturnAddrIndex == 0) {
3629 // Set up a frame object for the return address.
3630 unsigned SlotSize = RegInfo->getSlotSize();
3631 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3634 FuncInfo->setRAIndex(ReturnAddrIndex);
3637 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3640 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3641 bool hasSymbolicDisplacement) {
3642 // Offset should fit into 32 bit immediate field.
3643 if (!isInt<32>(Offset))
3646 // If we don't have a symbolic displacement - we don't have any extra
3648 if (!hasSymbolicDisplacement)
3651 // FIXME: Some tweaks might be needed for medium code model.
3652 if (M != CodeModel::Small && M != CodeModel::Kernel)
3655 // For small code model we assume that latest object is 16MB before end of 31
3656 // bits boundary. We may also accept pretty large negative constants knowing
3657 // that all objects are in the positive half of address space.
3658 if (M == CodeModel::Small && Offset < 16*1024*1024)
3661 // For kernel code model we know that all object resist in the negative half
3662 // of 32bits address space. We may not accept negative offsets, since they may
3663 // be just off and we may accept pretty large positive ones.
3664 if (M == CodeModel::Kernel && Offset > 0)
3670 /// isCalleePop - Determines whether the callee is required to pop its
3671 /// own arguments. Callee pop is necessary to support tail calls.
3672 bool X86::isCalleePop(CallingConv::ID CallingConv,
3673 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3674 switch (CallingConv) {
3677 case CallingConv::X86_StdCall:
3678 case CallingConv::X86_FastCall:
3679 case CallingConv::X86_ThisCall:
3681 case CallingConv::Fast:
3682 case CallingConv::GHC:
3683 case CallingConv::HiPE:
3690 /// \brief Return true if the condition is an unsigned comparison operation.
3691 static bool isX86CCUnsigned(unsigned X86CC) {
3693 default: llvm_unreachable("Invalid integer condition!");
3694 case X86::COND_E: return true;
3695 case X86::COND_G: return false;
3696 case X86::COND_GE: return false;
3697 case X86::COND_L: return false;
3698 case X86::COND_LE: return false;
3699 case X86::COND_NE: return true;
3700 case X86::COND_B: return true;
3701 case X86::COND_A: return true;
3702 case X86::COND_BE: return true;
3703 case X86::COND_AE: return true;
3705 llvm_unreachable("covered switch fell through?!");
3708 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3709 /// specific condition code, returning the condition code and the LHS/RHS of the
3710 /// comparison to make.
3711 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3712 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3714 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3715 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3716 // X > -1 -> X == 0, jump !sign.
3717 RHS = DAG.getConstant(0, RHS.getValueType());
3718 return X86::COND_NS;
3720 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3721 // X < 0 -> X == 0, jump on sign.
3724 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3726 RHS = DAG.getConstant(0, RHS.getValueType());
3727 return X86::COND_LE;
3731 switch (SetCCOpcode) {
3732 default: llvm_unreachable("Invalid integer condition!");
3733 case ISD::SETEQ: return X86::COND_E;
3734 case ISD::SETGT: return X86::COND_G;
3735 case ISD::SETGE: return X86::COND_GE;
3736 case ISD::SETLT: return X86::COND_L;
3737 case ISD::SETLE: return X86::COND_LE;
3738 case ISD::SETNE: return X86::COND_NE;
3739 case ISD::SETULT: return X86::COND_B;
3740 case ISD::SETUGT: return X86::COND_A;
3741 case ISD::SETULE: return X86::COND_BE;
3742 case ISD::SETUGE: return X86::COND_AE;
3746 // First determine if it is required or is profitable to flip the operands.
3748 // If LHS is a foldable load, but RHS is not, flip the condition.
3749 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3750 !ISD::isNON_EXTLoad(RHS.getNode())) {
3751 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3752 std::swap(LHS, RHS);
3755 switch (SetCCOpcode) {
3761 std::swap(LHS, RHS);
3765 // On a floating point condition, the flags are set as follows:
3767 // 0 | 0 | 0 | X > Y
3768 // 0 | 0 | 1 | X < Y
3769 // 1 | 0 | 0 | X == Y
3770 // 1 | 1 | 1 | unordered
3771 switch (SetCCOpcode) {
3772 default: llvm_unreachable("Condcode should be pre-legalized away");
3774 case ISD::SETEQ: return X86::COND_E;
3775 case ISD::SETOLT: // flipped
3777 case ISD::SETGT: return X86::COND_A;
3778 case ISD::SETOLE: // flipped
3780 case ISD::SETGE: return X86::COND_AE;
3781 case ISD::SETUGT: // flipped
3783 case ISD::SETLT: return X86::COND_B;
3784 case ISD::SETUGE: // flipped
3786 case ISD::SETLE: return X86::COND_BE;
3788 case ISD::SETNE: return X86::COND_NE;
3789 case ISD::SETUO: return X86::COND_P;
3790 case ISD::SETO: return X86::COND_NP;
3792 case ISD::SETUNE: return X86::COND_INVALID;
3796 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3797 /// code. Current x86 isa includes the following FP cmov instructions:
3798 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3799 static bool hasFPCMov(unsigned X86CC) {
3815 /// isFPImmLegal - Returns true if the target can instruction select the
3816 /// specified FP immediate natively. If false, the legalizer will
3817 /// materialize the FP immediate as a load from a constant pool.
3818 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3819 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3820 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3826 /// \brief Returns true if it is beneficial to convert a load of a constant
3827 /// to just the constant itself.
3828 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3830 assert(Ty->isIntegerTy());
3832 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3833 if (BitSize == 0 || BitSize > 64)
3838 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3839 /// the specified range (L, H].
3840 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3841 return (Val < 0) || (Val >= Low && Val < Hi);
3844 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3845 /// specified value.
3846 static bool isUndefOrEqual(int Val, int CmpVal) {
3847 return (Val < 0 || Val == CmpVal);
3850 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3851 /// from position Pos and ending in Pos+Size, falls within the specified
3852 /// sequential range (L, L+Pos]. or is undef.
3853 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3854 unsigned Pos, unsigned Size, int Low) {
3855 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3856 if (!isUndefOrEqual(Mask[i], Low))
3861 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3862 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3863 /// operand - by default will match for first operand.
3864 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3865 bool TestSecondOperand = false) {
3866 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3867 VT != MVT::v2f64 && VT != MVT::v2i64)
3870 unsigned NumElems = VT.getVectorNumElements();
3871 unsigned Lo = TestSecondOperand ? NumElems : 0;
3872 unsigned Hi = Lo + NumElems;
3874 for (unsigned i = 0; i < NumElems; ++i)
3875 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3881 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3882 /// is suitable for input to PSHUFHW.
3883 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3884 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3887 // Lower quadword copied in order or undef.
3888 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3891 // Upper quadword shuffled.
3892 for (unsigned i = 4; i != 8; ++i)
3893 if (!isUndefOrInRange(Mask[i], 4, 8))
3896 if (VT == MVT::v16i16) {
3897 // Lower quadword copied in order or undef.
3898 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3901 // Upper quadword shuffled.
3902 for (unsigned i = 12; i != 16; ++i)
3903 if (!isUndefOrInRange(Mask[i], 12, 16))
3910 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3911 /// is suitable for input to PSHUFLW.
3912 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3913 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3916 // Upper quadword copied in order.
3917 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3920 // Lower quadword shuffled.
3921 for (unsigned i = 0; i != 4; ++i)
3922 if (!isUndefOrInRange(Mask[i], 0, 4))
3925 if (VT == MVT::v16i16) {
3926 // Upper quadword copied in order.
3927 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3930 // Lower quadword shuffled.
3931 for (unsigned i = 8; i != 12; ++i)
3932 if (!isUndefOrInRange(Mask[i], 8, 12))
3939 /// \brief Return true if the mask specifies a shuffle of elements that is
3940 /// suitable for input to intralane (palignr) or interlane (valign) vector
3942 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3943 unsigned NumElts = VT.getVectorNumElements();
3944 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3945 unsigned NumLaneElts = NumElts/NumLanes;
3947 // Do not handle 64-bit element shuffles with palignr.
3948 if (NumLaneElts == 2)
3951 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3953 for (i = 0; i != NumLaneElts; ++i) {
3958 // Lane is all undef, go to next lane
3959 if (i == NumLaneElts)
3962 int Start = Mask[i+l];
3964 // Make sure its in this lane in one of the sources
3965 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3966 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3969 // If not lane 0, then we must match lane 0
3970 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3973 // Correct second source to be contiguous with first source
3974 if (Start >= (int)NumElts)
3975 Start -= NumElts - NumLaneElts;
3977 // Make sure we're shifting in the right direction.
3978 if (Start <= (int)(i+l))
3983 // Check the rest of the elements to see if they are consecutive.
3984 for (++i; i != NumLaneElts; ++i) {
3985 int Idx = Mask[i+l];
3987 // Make sure its in this lane
3988 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3989 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3992 // If not lane 0, then we must match lane 0
3993 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3996 if (Idx >= (int)NumElts)
3997 Idx -= NumElts - NumLaneElts;
3999 if (!isUndefOrEqual(Idx, Start+i))
4008 /// \brief Return true if the node specifies a shuffle of elements that is
4009 /// suitable for input to PALIGNR.
4010 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4011 const X86Subtarget *Subtarget) {
4012 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4013 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4014 VT.is512BitVector())
4015 // FIXME: Add AVX512BW.
4018 return isAlignrMask(Mask, VT, false);
4021 /// \brief Return true if the node specifies a shuffle of elements that is
4022 /// suitable for input to VALIGN.
4023 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4024 const X86Subtarget *Subtarget) {
4025 // FIXME: Add AVX512VL.
4026 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4028 return isAlignrMask(Mask, VT, true);
4031 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4032 /// the two vector operands have swapped position.
4033 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4034 unsigned NumElems) {
4035 for (unsigned i = 0; i != NumElems; ++i) {
4039 else if (idx < (int)NumElems)
4040 Mask[i] = idx + NumElems;
4042 Mask[i] = idx - NumElems;
4046 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4047 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4048 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4049 /// reverse of what x86 shuffles want.
4050 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4052 unsigned NumElems = VT.getVectorNumElements();
4053 unsigned NumLanes = VT.getSizeInBits()/128;
4054 unsigned NumLaneElems = NumElems/NumLanes;
4056 if (NumLaneElems != 2 && NumLaneElems != 4)
4059 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4060 bool symetricMaskRequired =
4061 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4063 // VSHUFPSY divides the resulting vector into 4 chunks.
4064 // The sources are also splitted into 4 chunks, and each destination
4065 // chunk must come from a different source chunk.
4067 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4068 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4070 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4071 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4073 // VSHUFPDY divides the resulting vector into 4 chunks.
4074 // The sources are also splitted into 4 chunks, and each destination
4075 // chunk must come from a different source chunk.
4077 // SRC1 => X3 X2 X1 X0
4078 // SRC2 => Y3 Y2 Y1 Y0
4080 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4082 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4083 unsigned HalfLaneElems = NumLaneElems/2;
4084 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4085 for (unsigned i = 0; i != NumLaneElems; ++i) {
4086 int Idx = Mask[i+l];
4087 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4088 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4090 // For VSHUFPSY, the mask of the second half must be the same as the
4091 // first but with the appropriate offsets. This works in the same way as
4092 // VPERMILPS works with masks.
4093 if (!symetricMaskRequired || Idx < 0)
4095 if (MaskVal[i] < 0) {
4096 MaskVal[i] = Idx - l;
4099 if ((signed)(Idx - l) != MaskVal[i])
4107 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4108 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4109 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4110 if (!VT.is128BitVector())
4113 unsigned NumElems = VT.getVectorNumElements();
4118 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4119 return isUndefOrEqual(Mask[0], 6) &&
4120 isUndefOrEqual(Mask[1], 7) &&
4121 isUndefOrEqual(Mask[2], 2) &&
4122 isUndefOrEqual(Mask[3], 3);
4125 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4126 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4128 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4129 if (!VT.is128BitVector())
4132 unsigned NumElems = VT.getVectorNumElements();
4137 return isUndefOrEqual(Mask[0], 2) &&
4138 isUndefOrEqual(Mask[1], 3) &&
4139 isUndefOrEqual(Mask[2], 2) &&
4140 isUndefOrEqual(Mask[3], 3);
4143 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4144 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4145 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4146 if (!VT.is128BitVector())
4149 unsigned NumElems = VT.getVectorNumElements();
4151 if (NumElems != 2 && NumElems != 4)
4154 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4155 if (!isUndefOrEqual(Mask[i], i + NumElems))
4158 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4159 if (!isUndefOrEqual(Mask[i], i))
4165 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4166 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4167 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4168 if (!VT.is128BitVector())
4171 unsigned NumElems = VT.getVectorNumElements();
4173 if (NumElems != 2 && NumElems != 4)
4176 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4177 if (!isUndefOrEqual(Mask[i], i))
4180 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4181 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4187 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4188 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4189 /// i. e: If all but one element come from the same vector.
4190 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4191 // TODO: Deal with AVX's VINSERTPS
4192 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4195 unsigned CorrectPosV1 = 0;
4196 unsigned CorrectPosV2 = 0;
4197 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4198 if (Mask[i] == -1) {
4206 else if (Mask[i] == i + 4)
4210 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4211 // We have 3 elements (undefs count as elements from any vector) from one
4212 // vector, and one from another.
4219 // Some special combinations that can be optimized.
4222 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4223 SelectionDAG &DAG) {
4224 MVT VT = SVOp->getSimpleValueType(0);
4227 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4230 ArrayRef<int> Mask = SVOp->getMask();
4232 // These are the special masks that may be optimized.
4233 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4234 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4235 bool MatchEvenMask = true;
4236 bool MatchOddMask = true;
4237 for (int i=0; i<8; ++i) {
4238 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4239 MatchEvenMask = false;
4240 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4241 MatchOddMask = false;
4244 if (!MatchEvenMask && !MatchOddMask)
4247 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4249 SDValue Op0 = SVOp->getOperand(0);
4250 SDValue Op1 = SVOp->getOperand(1);
4252 if (MatchEvenMask) {
4253 // Shift the second operand right to 32 bits.
4254 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4255 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4257 // Shift the first operand left to 32 bits.
4258 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4259 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4261 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4262 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4265 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4266 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4267 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4268 bool HasInt256, bool V2IsSplat = false) {
4270 assert(VT.getSizeInBits() >= 128 &&
4271 "Unsupported vector type for unpckl");
4273 unsigned NumElts = VT.getVectorNumElements();
4274 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4275 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4278 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4279 "Unsupported vector type for unpckh");
4281 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4282 unsigned NumLanes = VT.getSizeInBits()/128;
4283 unsigned NumLaneElts = NumElts/NumLanes;
4285 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4286 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4287 int BitI = Mask[l+i];
4288 int BitI1 = Mask[l+i+1];
4289 if (!isUndefOrEqual(BitI, j))
4292 if (!isUndefOrEqual(BitI1, NumElts))
4295 if (!isUndefOrEqual(BitI1, j + NumElts))
4304 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4305 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4306 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4307 bool HasInt256, bool V2IsSplat = false) {
4308 assert(VT.getSizeInBits() >= 128 &&
4309 "Unsupported vector type for unpckh");
4311 unsigned NumElts = VT.getVectorNumElements();
4312 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4313 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4316 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4317 "Unsupported vector type for unpckh");
4319 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4320 unsigned NumLanes = VT.getSizeInBits()/128;
4321 unsigned NumLaneElts = NumElts/NumLanes;
4323 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4324 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4325 int BitI = Mask[l+i];
4326 int BitI1 = Mask[l+i+1];
4327 if (!isUndefOrEqual(BitI, j))
4330 if (isUndefOrEqual(BitI1, NumElts))
4333 if (!isUndefOrEqual(BitI1, j+NumElts))
4341 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4342 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4344 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4345 unsigned NumElts = VT.getVectorNumElements();
4346 bool Is256BitVec = VT.is256BitVector();
4348 if (VT.is512BitVector())
4350 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4351 "Unsupported vector type for unpckh");
4353 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4354 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4357 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4358 // FIXME: Need a better way to get rid of this, there's no latency difference
4359 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4360 // the former later. We should also remove the "_undef" special mask.
4361 if (NumElts == 4 && Is256BitVec)
4364 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4365 // independently on 128-bit lanes.
4366 unsigned NumLanes = VT.getSizeInBits()/128;
4367 unsigned NumLaneElts = NumElts/NumLanes;
4369 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4370 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4371 int BitI = Mask[l+i];
4372 int BitI1 = Mask[l+i+1];
4374 if (!isUndefOrEqual(BitI, j))
4376 if (!isUndefOrEqual(BitI1, j))
4384 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4385 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4387 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4388 unsigned NumElts = VT.getVectorNumElements();
4390 if (VT.is512BitVector())
4393 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4394 "Unsupported vector type for unpckh");
4396 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4397 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4400 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4401 // independently on 128-bit lanes.
4402 unsigned NumLanes = VT.getSizeInBits()/128;
4403 unsigned NumLaneElts = NumElts/NumLanes;
4405 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4406 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4407 int BitI = Mask[l+i];
4408 int BitI1 = Mask[l+i+1];
4409 if (!isUndefOrEqual(BitI, j))
4411 if (!isUndefOrEqual(BitI1, j))
4418 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4419 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4420 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4421 if (!VT.is512BitVector())
4424 unsigned NumElts = VT.getVectorNumElements();
4425 unsigned HalfSize = NumElts/2;
4426 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4427 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4432 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4433 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4441 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4442 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4443 /// MOVSD, and MOVD, i.e. setting the lowest element.
4444 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4445 if (VT.getVectorElementType().getSizeInBits() < 32)
4447 if (!VT.is128BitVector())
4450 unsigned NumElts = VT.getVectorNumElements();
4452 if (!isUndefOrEqual(Mask[0], NumElts))
4455 for (unsigned i = 1; i != NumElts; ++i)
4456 if (!isUndefOrEqual(Mask[i], i))
4462 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4463 /// as permutations between 128-bit chunks or halves. As an example: this
4465 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4466 /// The first half comes from the second half of V1 and the second half from the
4467 /// the second half of V2.
4468 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4469 if (!HasFp256 || !VT.is256BitVector())
4472 // The shuffle result is divided into half A and half B. In total the two
4473 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4474 // B must come from C, D, E or F.
4475 unsigned HalfSize = VT.getVectorNumElements()/2;
4476 bool MatchA = false, MatchB = false;
4478 // Check if A comes from one of C, D, E, F.
4479 for (unsigned Half = 0; Half != 4; ++Half) {
4480 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4486 // Check if B comes from one of C, D, E, F.
4487 for (unsigned Half = 0; Half != 4; ++Half) {
4488 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4494 return MatchA && MatchB;
4497 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4498 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4499 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4500 MVT VT = SVOp->getSimpleValueType(0);
4502 unsigned HalfSize = VT.getVectorNumElements()/2;
4504 unsigned FstHalf = 0, SndHalf = 0;
4505 for (unsigned i = 0; i < HalfSize; ++i) {
4506 if (SVOp->getMaskElt(i) > 0) {
4507 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4511 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4512 if (SVOp->getMaskElt(i) > 0) {
4513 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4518 return (FstHalf | (SndHalf << 4));
4521 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4522 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4523 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4527 unsigned NumElts = VT.getVectorNumElements();
4529 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4530 for (unsigned i = 0; i != NumElts; ++i) {
4533 Imm8 |= Mask[i] << (i*2);
4538 unsigned LaneSize = 4;
4539 SmallVector<int, 4> MaskVal(LaneSize, -1);
4541 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4542 for (unsigned i = 0; i != LaneSize; ++i) {
4543 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4547 if (MaskVal[i] < 0) {
4548 MaskVal[i] = Mask[i+l] - l;
4549 Imm8 |= MaskVal[i] << (i*2);
4552 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4559 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4560 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4561 /// Note that VPERMIL mask matching is different depending whether theunderlying
4562 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4563 /// to the same elements of the low, but to the higher half of the source.
4564 /// In VPERMILPD the two lanes could be shuffled independently of each other
4565 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4566 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4567 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4568 if (VT.getSizeInBits() < 256 || EltSize < 32)
4570 bool symetricMaskRequired = (EltSize == 32);
4571 unsigned NumElts = VT.getVectorNumElements();
4573 unsigned NumLanes = VT.getSizeInBits()/128;
4574 unsigned LaneSize = NumElts/NumLanes;
4575 // 2 or 4 elements in one lane
4577 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4578 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4579 for (unsigned i = 0; i != LaneSize; ++i) {
4580 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4582 if (symetricMaskRequired) {
4583 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4584 ExpectedMaskVal[i] = Mask[i+l] - l;
4587 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4595 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4596 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4597 /// element of vector 2 and the other elements to come from vector 1 in order.
4598 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4599 bool V2IsSplat = false, bool V2IsUndef = false) {
4600 if (!VT.is128BitVector())
4603 unsigned NumOps = VT.getVectorNumElements();
4604 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4607 if (!isUndefOrEqual(Mask[0], 0))
4610 for (unsigned i = 1; i != NumOps; ++i)
4611 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4612 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4613 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4619 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4620 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4621 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4622 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4623 const X86Subtarget *Subtarget) {
4624 if (!Subtarget->hasSSE3())
4627 unsigned NumElems = VT.getVectorNumElements();
4629 if ((VT.is128BitVector() && NumElems != 4) ||
4630 (VT.is256BitVector() && NumElems != 8) ||
4631 (VT.is512BitVector() && NumElems != 16))
4634 // "i+1" is the value the indexed mask element must have
4635 for (unsigned i = 0; i != NumElems; i += 2)
4636 if (!isUndefOrEqual(Mask[i], i+1) ||
4637 !isUndefOrEqual(Mask[i+1], i+1))
4643 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4644 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4645 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4646 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4647 const X86Subtarget *Subtarget) {
4648 if (!Subtarget->hasSSE3())
4651 unsigned NumElems = VT.getVectorNumElements();
4653 if ((VT.is128BitVector() && NumElems != 4) ||
4654 (VT.is256BitVector() && NumElems != 8) ||
4655 (VT.is512BitVector() && NumElems != 16))
4658 // "i" is the value the indexed mask element must have
4659 for (unsigned i = 0; i != NumElems; i += 2)
4660 if (!isUndefOrEqual(Mask[i], i) ||
4661 !isUndefOrEqual(Mask[i+1], i))
4667 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4668 /// specifies a shuffle of elements that is suitable for input to 256-bit
4669 /// version of MOVDDUP.
4670 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4671 if (!HasFp256 || !VT.is256BitVector())
4674 unsigned NumElts = VT.getVectorNumElements();
4678 for (unsigned i = 0; i != NumElts/2; ++i)
4679 if (!isUndefOrEqual(Mask[i], 0))
4681 for (unsigned i = NumElts/2; i != NumElts; ++i)
4682 if (!isUndefOrEqual(Mask[i], NumElts/2))
4687 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4688 /// specifies a shuffle of elements that is suitable for input to 128-bit
4689 /// version of MOVDDUP.
4690 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4691 if (!VT.is128BitVector())
4694 unsigned e = VT.getVectorNumElements() / 2;
4695 for (unsigned i = 0; i != e; ++i)
4696 if (!isUndefOrEqual(Mask[i], i))
4698 for (unsigned i = 0; i != e; ++i)
4699 if (!isUndefOrEqual(Mask[e+i], i))
4704 /// isVEXTRACTIndex - Return true if the specified
4705 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4706 /// suitable for instruction that extract 128 or 256 bit vectors
4707 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4708 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4709 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4712 // The index should be aligned on a vecWidth-bit boundary.
4714 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4716 MVT VT = N->getSimpleValueType(0);
4717 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4718 bool Result = (Index * ElSize) % vecWidth == 0;
4723 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4724 /// operand specifies a subvector insert that is suitable for input to
4725 /// insertion of 128 or 256-bit subvectors
4726 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4727 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4728 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4730 // The index should be aligned on a vecWidth-bit boundary.
4732 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4734 MVT VT = N->getSimpleValueType(0);
4735 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4736 bool Result = (Index * ElSize) % vecWidth == 0;
4741 bool X86::isVINSERT128Index(SDNode *N) {
4742 return isVINSERTIndex(N, 128);
4745 bool X86::isVINSERT256Index(SDNode *N) {
4746 return isVINSERTIndex(N, 256);
4749 bool X86::isVEXTRACT128Index(SDNode *N) {
4750 return isVEXTRACTIndex(N, 128);
4753 bool X86::isVEXTRACT256Index(SDNode *N) {
4754 return isVEXTRACTIndex(N, 256);
4757 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4758 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4759 /// Handles 128-bit and 256-bit.
4760 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4761 MVT VT = N->getSimpleValueType(0);
4763 assert((VT.getSizeInBits() >= 128) &&
4764 "Unsupported vector type for PSHUF/SHUFP");
4766 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4767 // independently on 128-bit lanes.
4768 unsigned NumElts = VT.getVectorNumElements();
4769 unsigned NumLanes = VT.getSizeInBits()/128;
4770 unsigned NumLaneElts = NumElts/NumLanes;
4772 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4773 "Only supports 2, 4 or 8 elements per lane");
4775 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4777 for (unsigned i = 0; i != NumElts; ++i) {
4778 int Elt = N->getMaskElt(i);
4779 if (Elt < 0) continue;
4780 Elt &= NumLaneElts - 1;
4781 unsigned ShAmt = (i << Shift) % 8;
4782 Mask |= Elt << ShAmt;
4788 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4789 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4790 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4791 MVT VT = N->getSimpleValueType(0);
4793 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4794 "Unsupported vector type for PSHUFHW");
4796 unsigned NumElts = VT.getVectorNumElements();
4799 for (unsigned l = 0; l != NumElts; l += 8) {
4800 // 8 nodes per lane, but we only care about the last 4.
4801 for (unsigned i = 0; i < 4; ++i) {
4802 int Elt = N->getMaskElt(l+i+4);
4803 if (Elt < 0) continue;
4804 Elt &= 0x3; // only 2-bits.
4805 Mask |= Elt << (i * 2);
4812 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4813 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4814 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4815 MVT VT = N->getSimpleValueType(0);
4817 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4818 "Unsupported vector type for PSHUFHW");
4820 unsigned NumElts = VT.getVectorNumElements();
4823 for (unsigned l = 0; l != NumElts; l += 8) {
4824 // 8 nodes per lane, but we only care about the first 4.
4825 for (unsigned i = 0; i < 4; ++i) {
4826 int Elt = N->getMaskElt(l+i);
4827 if (Elt < 0) continue;
4828 Elt &= 0x3; // only 2-bits
4829 Mask |= Elt << (i * 2);
4836 /// \brief Return the appropriate immediate to shuffle the specified
4837 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4838 /// VALIGN (if Interlane is true) instructions.
4839 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4841 MVT VT = SVOp->getSimpleValueType(0);
4842 unsigned EltSize = InterLane ? 1 :
4843 VT.getVectorElementType().getSizeInBits() >> 3;
4845 unsigned NumElts = VT.getVectorNumElements();
4846 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4847 unsigned NumLaneElts = NumElts/NumLanes;
4851 for (i = 0; i != NumElts; ++i) {
4852 Val = SVOp->getMaskElt(i);
4856 if (Val >= (int)NumElts)
4857 Val -= NumElts - NumLaneElts;
4859 assert(Val - i > 0 && "PALIGNR imm should be positive");
4860 return (Val - i) * EltSize;
4863 /// \brief Return the appropriate immediate to shuffle the specified
4864 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4865 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4866 return getShuffleAlignrImmediate(SVOp, false);
4869 /// \brief Return the appropriate immediate to shuffle the specified
4870 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4871 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4872 return getShuffleAlignrImmediate(SVOp, true);
4876 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4877 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4878 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4879 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4882 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4884 MVT VecVT = N->getOperand(0).getSimpleValueType();
4885 MVT ElVT = VecVT.getVectorElementType();
4887 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4888 return Index / NumElemsPerChunk;
4891 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4892 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4893 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4894 llvm_unreachable("Illegal insert subvector for VINSERT");
4897 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4899 MVT VecVT = N->getSimpleValueType(0);
4900 MVT ElVT = VecVT.getVectorElementType();
4902 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4903 return Index / NumElemsPerChunk;
4906 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4907 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4908 /// and VINSERTI128 instructions.
4909 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4910 return getExtractVEXTRACTImmediate(N, 128);
4913 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4914 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4915 /// and VINSERTI64x4 instructions.
4916 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4917 return getExtractVEXTRACTImmediate(N, 256);
4920 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4921 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4922 /// and VINSERTI128 instructions.
4923 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4924 return getInsertVINSERTImmediate(N, 128);
4927 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4928 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4929 /// and VINSERTI64x4 instructions.
4930 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4931 return getInsertVINSERTImmediate(N, 256);
4934 /// isZero - Returns true if Elt is a constant integer zero
4935 static bool isZero(SDValue V) {
4936 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4937 return C && C->isNullValue();
4940 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4942 bool X86::isZeroNode(SDValue Elt) {
4945 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4946 return CFP->getValueAPF().isPosZero();
4950 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4951 /// match movhlps. The lower half elements should come from upper half of
4952 /// V1 (and in order), and the upper half elements should come from the upper
4953 /// half of V2 (and in order).
4954 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4955 if (!VT.is128BitVector())
4957 if (VT.getVectorNumElements() != 4)
4959 for (unsigned i = 0, e = 2; i != e; ++i)
4960 if (!isUndefOrEqual(Mask[i], i+2))
4962 for (unsigned i = 2; i != 4; ++i)
4963 if (!isUndefOrEqual(Mask[i], i+4))
4968 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4969 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4971 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4972 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4974 N = N->getOperand(0).getNode();
4975 if (!ISD::isNON_EXTLoad(N))
4978 *LD = cast<LoadSDNode>(N);
4982 // Test whether the given value is a vector value which will be legalized
4984 static bool WillBeConstantPoolLoad(SDNode *N) {
4985 if (N->getOpcode() != ISD::BUILD_VECTOR)
4988 // Check for any non-constant elements.
4989 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4990 switch (N->getOperand(i).getNode()->getOpcode()) {
4992 case ISD::ConstantFP:
4999 // Vectors of all-zeros and all-ones are materialized with special
5000 // instructions rather than being loaded.
5001 return !ISD::isBuildVectorAllZeros(N) &&
5002 !ISD::isBuildVectorAllOnes(N);
5005 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5006 /// match movlp{s|d}. The lower half elements should come from lower half of
5007 /// V1 (and in order), and the upper half elements should come from the upper
5008 /// half of V2 (and in order). And since V1 will become the source of the
5009 /// MOVLP, it must be either a vector load or a scalar load to vector.
5010 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5011 ArrayRef<int> Mask, MVT VT) {
5012 if (!VT.is128BitVector())
5015 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5017 // Is V2 is a vector load, don't do this transformation. We will try to use
5018 // load folding shufps op.
5019 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5022 unsigned NumElems = VT.getVectorNumElements();
5024 if (NumElems != 2 && NumElems != 4)
5026 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5027 if (!isUndefOrEqual(Mask[i], i))
5029 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5030 if (!isUndefOrEqual(Mask[i], i+NumElems))
5035 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5036 /// to an zero vector.
5037 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5038 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5039 SDValue V1 = N->getOperand(0);
5040 SDValue V2 = N->getOperand(1);
5041 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5042 for (unsigned i = 0; i != NumElems; ++i) {
5043 int Idx = N->getMaskElt(i);
5044 if (Idx >= (int)NumElems) {
5045 unsigned Opc = V2.getOpcode();
5046 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5048 if (Opc != ISD::BUILD_VECTOR ||
5049 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5051 } else if (Idx >= 0) {
5052 unsigned Opc = V1.getOpcode();
5053 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5055 if (Opc != ISD::BUILD_VECTOR ||
5056 !X86::isZeroNode(V1.getOperand(Idx)))
5063 /// getZeroVector - Returns a vector of specified type with all zero elements.
5065 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5066 SelectionDAG &DAG, SDLoc dl) {
5067 assert(VT.isVector() && "Expected a vector type");
5069 // Always build SSE zero vectors as <4 x i32> bitcasted
5070 // to their dest type. This ensures they get CSE'd.
5072 if (VT.is128BitVector()) { // SSE
5073 if (Subtarget->hasSSE2()) { // SSE2
5074 SDValue Cst = DAG.getConstant(0, MVT::i32);
5075 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5077 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5078 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5080 } else if (VT.is256BitVector()) { // AVX
5081 if (Subtarget->hasInt256()) { // AVX2
5082 SDValue Cst = DAG.getConstant(0, MVT::i32);
5083 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5084 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5086 // 256-bit logic and arithmetic instructions in AVX are all
5087 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5088 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5089 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5090 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5092 } else if (VT.is512BitVector()) { // AVX-512
5093 SDValue Cst = DAG.getConstant(0, MVT::i32);
5094 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5095 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5096 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5097 } else if (VT.getScalarType() == MVT::i1) {
5098 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5099 SDValue Cst = DAG.getConstant(0, MVT::i1);
5100 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5101 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5103 llvm_unreachable("Unexpected vector type");
5105 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5108 /// getOnesVector - Returns a vector of specified type with all bits set.
5109 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5110 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5111 /// Then bitcast to their original type, ensuring they get CSE'd.
5112 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5114 assert(VT.isVector() && "Expected a vector type");
5116 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5118 if (VT.is256BitVector()) {
5119 if (HasInt256) { // AVX2
5120 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5123 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5124 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5126 } else if (VT.is128BitVector()) {
5127 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5129 llvm_unreachable("Unexpected vector type");
5131 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5134 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5135 /// that point to V2 points to its first element.
5136 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5137 for (unsigned i = 0; i != NumElems; ++i) {
5138 if (Mask[i] > (int)NumElems) {
5144 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5145 /// operation of specified width.
5146 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5148 unsigned NumElems = VT.getVectorNumElements();
5149 SmallVector<int, 8> Mask;
5150 Mask.push_back(NumElems);
5151 for (unsigned i = 1; i != NumElems; ++i)
5153 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5156 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5157 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5159 unsigned NumElems = VT.getVectorNumElements();
5160 SmallVector<int, 8> Mask;
5161 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5163 Mask.push_back(i + NumElems);
5165 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5168 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5169 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5171 unsigned NumElems = VT.getVectorNumElements();
5172 SmallVector<int, 8> Mask;
5173 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5174 Mask.push_back(i + Half);
5175 Mask.push_back(i + NumElems + Half);
5177 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5180 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5181 // a generic shuffle instruction because the target has no such instructions.
5182 // Generate shuffles which repeat i16 and i8 several times until they can be
5183 // represented by v4f32 and then be manipulated by target suported shuffles.
5184 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5185 MVT VT = V.getSimpleValueType();
5186 int NumElems = VT.getVectorNumElements();
5189 while (NumElems > 4) {
5190 if (EltNo < NumElems/2) {
5191 V = getUnpackl(DAG, dl, VT, V, V);
5193 V = getUnpackh(DAG, dl, VT, V, V);
5194 EltNo -= NumElems/2;
5201 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5202 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5203 MVT VT = V.getSimpleValueType();
5206 if (VT.is128BitVector()) {
5207 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5208 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5209 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5211 } else if (VT.is256BitVector()) {
5212 // To use VPERMILPS to splat scalars, the second half of indicies must
5213 // refer to the higher part, which is a duplication of the lower one,
5214 // because VPERMILPS can only handle in-lane permutations.
5215 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5216 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5218 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5219 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5222 llvm_unreachable("Vector size not supported");
5224 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5227 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5228 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5229 MVT SrcVT = SV->getSimpleValueType(0);
5230 SDValue V1 = SV->getOperand(0);
5233 int EltNo = SV->getSplatIndex();
5234 int NumElems = SrcVT.getVectorNumElements();
5235 bool Is256BitVec = SrcVT.is256BitVector();
5237 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5238 "Unknown how to promote splat for type");
5240 // Extract the 128-bit part containing the splat element and update
5241 // the splat element index when it refers to the higher register.
5243 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5244 if (EltNo >= NumElems/2)
5245 EltNo -= NumElems/2;
5248 // All i16 and i8 vector types can't be used directly by a generic shuffle
5249 // instruction because the target has no such instruction. Generate shuffles
5250 // which repeat i16 and i8 several times until they fit in i32, and then can
5251 // be manipulated by target suported shuffles.
5252 MVT EltVT = SrcVT.getVectorElementType();
5253 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5254 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5256 // Recreate the 256-bit vector and place the same 128-bit vector
5257 // into the low and high part. This is necessary because we want
5258 // to use VPERM* to shuffle the vectors
5260 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5263 return getLegalSplat(DAG, V1, EltNo);
5266 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5267 /// vector of zero or undef vector. This produces a shuffle where the low
5268 /// element of V2 is swizzled into the zero/undef vector, landing at element
5269 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5270 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5272 const X86Subtarget *Subtarget,
5273 SelectionDAG &DAG) {
5274 MVT VT = V2.getSimpleValueType();
5276 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5277 unsigned NumElems = VT.getVectorNumElements();
5278 SmallVector<int, 16> MaskVec;
5279 for (unsigned i = 0; i != NumElems; ++i)
5280 // If this is the insertion idx, put the low elt of V2 here.
5281 MaskVec.push_back(i == Idx ? NumElems : i);
5282 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5285 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5286 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5287 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5288 /// shuffles which use a single input multiple times, and in those cases it will
5289 /// adjust the mask to only have indices within that single input.
5290 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5291 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5292 unsigned NumElems = VT.getVectorNumElements();
5296 bool IsFakeUnary = false;
5297 switch(N->getOpcode()) {
5298 case X86ISD::BLENDI:
5299 ImmN = N->getOperand(N->getNumOperands()-1);
5300 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5303 ImmN = N->getOperand(N->getNumOperands()-1);
5304 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5305 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5307 case X86ISD::UNPCKH:
5308 DecodeUNPCKHMask(VT, Mask);
5309 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5311 case X86ISD::UNPCKL:
5312 DecodeUNPCKLMask(VT, Mask);
5313 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5315 case X86ISD::MOVHLPS:
5316 DecodeMOVHLPSMask(NumElems, Mask);
5317 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5319 case X86ISD::MOVLHPS:
5320 DecodeMOVLHPSMask(NumElems, Mask);
5321 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5323 case X86ISD::PALIGNR:
5324 ImmN = N->getOperand(N->getNumOperands()-1);
5325 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5327 case X86ISD::PSHUFD:
5328 case X86ISD::VPERMILPI:
5329 ImmN = N->getOperand(N->getNumOperands()-1);
5330 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5333 case X86ISD::PSHUFHW:
5334 ImmN = N->getOperand(N->getNumOperands()-1);
5335 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5338 case X86ISD::PSHUFLW:
5339 ImmN = N->getOperand(N->getNumOperands()-1);
5340 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5343 case X86ISD::PSHUFB: {
5345 SDValue MaskNode = N->getOperand(1);
5346 while (MaskNode->getOpcode() == ISD::BITCAST)
5347 MaskNode = MaskNode->getOperand(0);
5349 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5350 // If we have a build-vector, then things are easy.
5351 EVT VT = MaskNode.getValueType();
5352 assert(VT.isVector() &&
5353 "Can't produce a non-vector with a build_vector!");
5354 if (!VT.isInteger())
5357 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5359 SmallVector<uint64_t, 32> RawMask;
5360 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5361 SDValue Op = MaskNode->getOperand(i);
5362 if (Op->getOpcode() == ISD::UNDEF) {
5363 RawMask.push_back((uint64_t)SM_SentinelUndef);
5366 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5369 APInt MaskElement = CN->getAPIntValue();
5371 // We now have to decode the element which could be any integer size and
5372 // extract each byte of it.
5373 for (int j = 0; j < NumBytesPerElement; ++j) {
5374 // Note that this is x86 and so always little endian: the low byte is
5375 // the first byte of the mask.
5376 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5377 MaskElement = MaskElement.lshr(8);
5380 DecodePSHUFBMask(RawMask, Mask);
5384 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5388 SDValue Ptr = MaskLoad->getBasePtr();
5389 if (Ptr->getOpcode() == X86ISD::Wrapper)
5390 Ptr = Ptr->getOperand(0);
5392 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5393 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5396 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5397 // FIXME: Support AVX-512 here.
5398 Type *Ty = C->getType();
5399 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5400 Ty->getVectorNumElements() != 32))
5403 DecodePSHUFBMask(C, Mask);
5409 case X86ISD::VPERMI:
5410 ImmN = N->getOperand(N->getNumOperands()-1);
5411 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5415 case X86ISD::MOVSD: {
5416 // The index 0 always comes from the first element of the second source,
5417 // this is why MOVSS and MOVSD are used in the first place. The other
5418 // elements come from the other positions of the first source vector
5419 Mask.push_back(NumElems);
5420 for (unsigned i = 1; i != NumElems; ++i) {
5425 case X86ISD::VPERM2X128:
5426 ImmN = N->getOperand(N->getNumOperands()-1);
5427 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5428 if (Mask.empty()) return false;
5430 case X86ISD::MOVSLDUP:
5431 DecodeMOVSLDUPMask(VT, Mask);
5433 case X86ISD::MOVSHDUP:
5434 DecodeMOVSHDUPMask(VT, Mask);
5436 case X86ISD::MOVDDUP:
5437 case X86ISD::MOVLHPD:
5438 case X86ISD::MOVLPD:
5439 case X86ISD::MOVLPS:
5440 // Not yet implemented
5442 default: llvm_unreachable("unknown target shuffle node");
5445 // If we have a fake unary shuffle, the shuffle mask is spread across two
5446 // inputs that are actually the same node. Re-map the mask to always point
5447 // into the first input.
5450 if (M >= (int)Mask.size())
5456 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5457 /// element of the result of the vector shuffle.
5458 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5461 return SDValue(); // Limit search depth.
5463 SDValue V = SDValue(N, 0);
5464 EVT VT = V.getValueType();
5465 unsigned Opcode = V.getOpcode();
5467 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5468 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5469 int Elt = SV->getMaskElt(Index);
5472 return DAG.getUNDEF(VT.getVectorElementType());
5474 unsigned NumElems = VT.getVectorNumElements();
5475 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5476 : SV->getOperand(1);
5477 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5480 // Recurse into target specific vector shuffles to find scalars.
5481 if (isTargetShuffle(Opcode)) {
5482 MVT ShufVT = V.getSimpleValueType();
5483 unsigned NumElems = ShufVT.getVectorNumElements();
5484 SmallVector<int, 16> ShuffleMask;
5487 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5490 int Elt = ShuffleMask[Index];
5492 return DAG.getUNDEF(ShufVT.getVectorElementType());
5494 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5496 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5500 // Actual nodes that may contain scalar elements
5501 if (Opcode == ISD::BITCAST) {
5502 V = V.getOperand(0);
5503 EVT SrcVT = V.getValueType();
5504 unsigned NumElems = VT.getVectorNumElements();
5506 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5510 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5511 return (Index == 0) ? V.getOperand(0)
5512 : DAG.getUNDEF(VT.getVectorElementType());
5514 if (V.getOpcode() == ISD::BUILD_VECTOR)
5515 return V.getOperand(Index);
5520 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5521 /// shuffle operation which come from a consecutively from a zero. The
5522 /// search can start in two different directions, from left or right.
5523 /// We count undefs as zeros until PreferredNum is reached.
5524 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5525 unsigned NumElems, bool ZerosFromLeft,
5527 unsigned PreferredNum = -1U) {
5528 unsigned NumZeros = 0;
5529 for (unsigned i = 0; i != NumElems; ++i) {
5530 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5531 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5535 if (X86::isZeroNode(Elt))
5537 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5538 NumZeros = std::min(NumZeros + 1, PreferredNum);
5546 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5547 /// correspond consecutively to elements from one of the vector operands,
5548 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5550 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5551 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5552 unsigned NumElems, unsigned &OpNum) {
5553 bool SeenV1 = false;
5554 bool SeenV2 = false;
5556 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5557 int Idx = SVOp->getMaskElt(i);
5558 // Ignore undef indicies
5562 if (Idx < (int)NumElems)
5567 // Only accept consecutive elements from the same vector
5568 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5572 OpNum = SeenV1 ? 0 : 1;
5576 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5577 /// logical left shift of a vector.
5578 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5579 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5581 SVOp->getSimpleValueType(0).getVectorNumElements();
5582 unsigned NumZeros = getNumOfConsecutiveZeros(
5583 SVOp, NumElems, false /* check zeros from right */, DAG,
5584 SVOp->getMaskElt(0));
5590 // Considering the elements in the mask that are not consecutive zeros,
5591 // check if they consecutively come from only one of the source vectors.
5593 // V1 = {X, A, B, C} 0
5595 // vector_shuffle V1, V2 <1, 2, 3, X>
5597 if (!isShuffleMaskConsecutive(SVOp,
5598 0, // Mask Start Index
5599 NumElems-NumZeros, // Mask End Index(exclusive)
5600 NumZeros, // Where to start looking in the src vector
5601 NumElems, // Number of elements in vector
5602 OpSrc)) // Which source operand ?
5607 ShVal = SVOp->getOperand(OpSrc);
5611 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5612 /// logical left shift of a vector.
5613 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5614 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5616 SVOp->getSimpleValueType(0).getVectorNumElements();
5617 unsigned NumZeros = getNumOfConsecutiveZeros(
5618 SVOp, NumElems, true /* check zeros from left */, DAG,
5619 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5625 // Considering the elements in the mask that are not consecutive zeros,
5626 // check if they consecutively come from only one of the source vectors.
5628 // 0 { A, B, X, X } = V2
5630 // vector_shuffle V1, V2 <X, X, 4, 5>
5632 if (!isShuffleMaskConsecutive(SVOp,
5633 NumZeros, // Mask Start Index
5634 NumElems, // Mask End Index(exclusive)
5635 0, // Where to start looking in the src vector
5636 NumElems, // Number of elements in vector
5637 OpSrc)) // Which source operand ?
5642 ShVal = SVOp->getOperand(OpSrc);
5646 /// isVectorShift - Returns true if the shuffle can be implemented as a
5647 /// logical left or right shift of a vector.
5648 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5649 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5650 // Although the logic below support any bitwidth size, there are no
5651 // shift instructions which handle more than 128-bit vectors.
5652 if (!SVOp->getSimpleValueType(0).is128BitVector())
5655 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5656 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5662 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5664 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5665 unsigned NumNonZero, unsigned NumZero,
5667 const X86Subtarget* Subtarget,
5668 const TargetLowering &TLI) {
5675 for (unsigned i = 0; i < 16; ++i) {
5676 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5677 if (ThisIsNonZero && First) {
5679 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5681 V = DAG.getUNDEF(MVT::v8i16);
5686 SDValue ThisElt, LastElt;
5687 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5688 if (LastIsNonZero) {
5689 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5690 MVT::i16, Op.getOperand(i-1));
5692 if (ThisIsNonZero) {
5693 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5694 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5695 ThisElt, DAG.getConstant(8, MVT::i8));
5697 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5701 if (ThisElt.getNode())
5702 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5703 DAG.getIntPtrConstant(i/2));
5707 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5710 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5712 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5713 unsigned NumNonZero, unsigned NumZero,
5715 const X86Subtarget* Subtarget,
5716 const TargetLowering &TLI) {
5723 for (unsigned i = 0; i < 8; ++i) {
5724 bool isNonZero = (NonZeros & (1 << i)) != 0;
5728 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5730 V = DAG.getUNDEF(MVT::v8i16);
5733 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5734 MVT::v8i16, V, Op.getOperand(i),
5735 DAG.getIntPtrConstant(i));
5742 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5743 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5744 const X86Subtarget *Subtarget,
5745 const TargetLowering &TLI) {
5746 // Find all zeroable elements.
5748 for (int i=0; i < 4; ++i) {
5749 SDValue Elt = Op->getOperand(i);
5750 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5752 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5753 [](bool M) { return !M; }) > 1 &&
5754 "We expect at least two non-zero elements!");
5756 // We only know how to deal with build_vector nodes where elements are either
5757 // zeroable or extract_vector_elt with constant index.
5758 SDValue FirstNonZero;
5759 for (int i=0; i < 4; ++i) {
5762 SDValue Elt = Op->getOperand(i);
5763 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5764 !isa<ConstantSDNode>(Elt.getOperand(1)))
5766 // Make sure that this node is extracting from a 128-bit vector.
5767 MVT VT = Elt.getOperand(0).getSimpleValueType();
5768 if (!VT.is128BitVector())
5770 if (!FirstNonZero.getNode())
5774 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5775 SDValue V1 = FirstNonZero.getOperand(0);
5776 MVT VT = V1.getSimpleValueType();
5778 // See if this build_vector can be lowered as a blend with zero.
5780 unsigned EltMaskIdx, EltIdx;
5782 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5783 if (Zeroable[EltIdx]) {
5784 // The zero vector will be on the right hand side.
5785 Mask[EltIdx] = EltIdx+4;
5789 Elt = Op->getOperand(EltIdx);
5790 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5791 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5792 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5794 Mask[EltIdx] = EltIdx;
5798 // Let the shuffle legalizer deal with blend operations.
5799 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5800 if (V1.getSimpleValueType() != VT)
5801 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5802 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5805 // See if we can lower this build_vector to a INSERTPS.
5806 if (!Subtarget->hasSSE41())
5809 SDValue V2 = Elt.getOperand(0);
5810 if (Elt == FirstNonZero)
5813 bool CanFold = true;
5814 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5818 SDValue Current = Op->getOperand(i);
5819 SDValue SrcVector = Current->getOperand(0);
5822 CanFold = SrcVector == V1 &&
5823 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5829 assert(V1.getNode() && "Expected at least two non-zero elements!");
5830 if (V1.getSimpleValueType() != MVT::v4f32)
5831 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5832 if (V2.getSimpleValueType() != MVT::v4f32)
5833 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5835 // Ok, we can emit an INSERTPS instruction.
5837 for (int i = 0; i < 4; ++i)
5841 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5842 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5843 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5844 DAG.getIntPtrConstant(InsertPSMask));
5845 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5848 /// getVShift - Return a vector logical shift node.
5850 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5851 unsigned NumBits, SelectionDAG &DAG,
5852 const TargetLowering &TLI, SDLoc dl) {
5853 assert(VT.is128BitVector() && "Unknown type for VShift");
5854 EVT ShVT = MVT::v2i64;
5855 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5856 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5857 return DAG.getNode(ISD::BITCAST, dl, VT,
5858 DAG.getNode(Opc, dl, ShVT, SrcOp,
5859 DAG.getConstant(NumBits,
5860 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5864 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5866 // Check if the scalar load can be widened into a vector load. And if
5867 // the address is "base + cst" see if the cst can be "absorbed" into
5868 // the shuffle mask.
5869 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5870 SDValue Ptr = LD->getBasePtr();
5871 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5873 EVT PVT = LD->getValueType(0);
5874 if (PVT != MVT::i32 && PVT != MVT::f32)
5879 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5880 FI = FINode->getIndex();
5882 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5883 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5884 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5885 Offset = Ptr.getConstantOperandVal(1);
5886 Ptr = Ptr.getOperand(0);
5891 // FIXME: 256-bit vector instructions don't require a strict alignment,
5892 // improve this code to support it better.
5893 unsigned RequiredAlign = VT.getSizeInBits()/8;
5894 SDValue Chain = LD->getChain();
5895 // Make sure the stack object alignment is at least 16 or 32.
5896 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5897 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5898 if (MFI->isFixedObjectIndex(FI)) {
5899 // Can't change the alignment. FIXME: It's possible to compute
5900 // the exact stack offset and reference FI + adjust offset instead.
5901 // If someone *really* cares about this. That's the way to implement it.
5904 MFI->setObjectAlignment(FI, RequiredAlign);
5908 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5909 // Ptr + (Offset & ~15).
5912 if ((Offset % RequiredAlign) & 3)
5914 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5916 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5917 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5919 int EltNo = (Offset - StartOffset) >> 2;
5920 unsigned NumElems = VT.getVectorNumElements();
5922 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5923 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5924 LD->getPointerInfo().getWithOffset(StartOffset),
5925 false, false, false, 0);
5927 SmallVector<int, 8> Mask;
5928 for (unsigned i = 0; i != NumElems; ++i)
5929 Mask.push_back(EltNo);
5931 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5937 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5938 /// vector of type 'VT', see if the elements can be replaced by a single large
5939 /// load which has the same value as a build_vector whose operands are 'elts'.
5941 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5943 /// FIXME: we'd also like to handle the case where the last elements are zero
5944 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5945 /// There's even a handy isZeroNode for that purpose.
5946 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5947 SDLoc &DL, SelectionDAG &DAG,
5948 bool isAfterLegalize) {
5949 EVT EltVT = VT.getVectorElementType();
5950 unsigned NumElems = Elts.size();
5952 LoadSDNode *LDBase = nullptr;
5953 unsigned LastLoadedElt = -1U;
5955 // For each element in the initializer, see if we've found a load or an undef.
5956 // If we don't find an initial load element, or later load elements are
5957 // non-consecutive, bail out.
5958 for (unsigned i = 0; i < NumElems; ++i) {
5959 SDValue Elt = Elts[i];
5961 if (!Elt.getNode() ||
5962 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5965 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5967 LDBase = cast<LoadSDNode>(Elt.getNode());
5971 if (Elt.getOpcode() == ISD::UNDEF)
5974 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5975 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5980 // If we have found an entire vector of loads and undefs, then return a large
5981 // load of the entire vector width starting at the base pointer. If we found
5982 // consecutive loads for the low half, generate a vzext_load node.
5983 if (LastLoadedElt == NumElems - 1) {
5985 if (isAfterLegalize &&
5986 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5989 SDValue NewLd = SDValue();
5991 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5992 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5993 LDBase->getPointerInfo(),
5994 LDBase->isVolatile(), LDBase->isNonTemporal(),
5995 LDBase->isInvariant(), 0);
5996 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5997 LDBase->getPointerInfo(),
5998 LDBase->isVolatile(), LDBase->isNonTemporal(),
5999 LDBase->isInvariant(), LDBase->getAlignment());
6001 if (LDBase->hasAnyUseOfValue(1)) {
6002 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6004 SDValue(NewLd.getNode(), 1));
6005 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6006 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6007 SDValue(NewLd.getNode(), 1));
6012 if (NumElems == 4 && LastLoadedElt == 1 &&
6013 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6014 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6015 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6017 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6018 LDBase->getPointerInfo(),
6019 LDBase->getAlignment(),
6020 false/*isVolatile*/, true/*ReadMem*/,
6023 // Make sure the newly-created LOAD is in the same position as LDBase in
6024 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6025 // update uses of LDBase's output chain to use the TokenFactor.
6026 if (LDBase->hasAnyUseOfValue(1)) {
6027 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6028 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6029 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6030 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6031 SDValue(ResNode.getNode(), 1));
6034 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6039 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6040 /// to generate a splat value for the following cases:
6041 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6042 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6043 /// a scalar load, or a constant.
6044 /// The VBROADCAST node is returned when a pattern is found,
6045 /// or SDValue() otherwise.
6046 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6047 SelectionDAG &DAG) {
6048 // VBROADCAST requires AVX.
6049 // TODO: Splats could be generated for non-AVX CPUs using SSE
6050 // instructions, but there's less potential gain for only 128-bit vectors.
6051 if (!Subtarget->hasAVX())
6054 MVT VT = Op.getSimpleValueType();
6057 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6058 "Unsupported vector type for broadcast.");
6063 switch (Op.getOpcode()) {
6065 // Unknown pattern found.
6068 case ISD::BUILD_VECTOR: {
6069 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6070 BitVector UndefElements;
6071 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6073 // We need a splat of a single value to use broadcast, and it doesn't
6074 // make any sense if the value is only in one element of the vector.
6075 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6079 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6080 Ld.getOpcode() == ISD::ConstantFP);
6082 // Make sure that all of the users of a non-constant load are from the
6083 // BUILD_VECTOR node.
6084 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6089 case ISD::VECTOR_SHUFFLE: {
6090 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6092 // Shuffles must have a splat mask where the first element is
6094 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6097 SDValue Sc = Op.getOperand(0);
6098 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6099 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6101 if (!Subtarget->hasInt256())
6104 // Use the register form of the broadcast instruction available on AVX2.
6105 if (VT.getSizeInBits() >= 256)
6106 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6107 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6110 Ld = Sc.getOperand(0);
6111 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6112 Ld.getOpcode() == ISD::ConstantFP);
6114 // The scalar_to_vector node and the suspected
6115 // load node must have exactly one user.
6116 // Constants may have multiple users.
6118 // AVX-512 has register version of the broadcast
6119 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6120 Ld.getValueType().getSizeInBits() >= 32;
6121 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6128 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6129 bool IsGE256 = (VT.getSizeInBits() >= 256);
6131 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6132 // instruction to save 8 or more bytes of constant pool data.
6133 // TODO: If multiple splats are generated to load the same constant,
6134 // it may be detrimental to overall size. There needs to be a way to detect
6135 // that condition to know if this is truly a size win.
6136 const Function *F = DAG.getMachineFunction().getFunction();
6137 bool OptForSize = F->getAttributes().
6138 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6140 // Handle broadcasting a single constant scalar from the constant pool
6142 // On Sandybridge (no AVX2), it is still better to load a constant vector
6143 // from the constant pool and not to broadcast it from a scalar.
6144 // But override that restriction when optimizing for size.
6145 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6146 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6147 EVT CVT = Ld.getValueType();
6148 assert(!CVT.isVector() && "Must not broadcast a vector type");
6150 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6151 // For size optimization, also splat v2f64 and v2i64, and for size opt
6152 // with AVX2, also splat i8 and i16.
6153 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6154 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6155 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6156 const Constant *C = nullptr;
6157 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6158 C = CI->getConstantIntValue();
6159 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6160 C = CF->getConstantFPValue();
6162 assert(C && "Invalid constant type");
6164 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6165 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6166 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6167 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6168 MachinePointerInfo::getConstantPool(),
6169 false, false, false, Alignment);
6171 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6175 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6177 // Handle AVX2 in-register broadcasts.
6178 if (!IsLoad && Subtarget->hasInt256() &&
6179 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6180 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6182 // The scalar source must be a normal load.
6186 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6187 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6189 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6190 // double since there is no vbroadcastsd xmm
6191 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6192 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6193 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6196 // Unsupported broadcast.
6200 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6201 /// underlying vector and index.
6203 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6205 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6207 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6208 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6211 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6213 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6215 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6216 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6219 // In this case the vector is the extract_subvector expression and the index
6220 // is 2, as specified by the shuffle.
6221 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6222 SDValue ShuffleVec = SVOp->getOperand(0);
6223 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6224 assert(ShuffleVecVT.getVectorElementType() ==
6225 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6227 int ShuffleIdx = SVOp->getMaskElt(Idx);
6228 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6229 ExtractedFromVec = ShuffleVec;
6235 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6236 MVT VT = Op.getSimpleValueType();
6238 // Skip if insert_vec_elt is not supported.
6239 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6240 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6244 unsigned NumElems = Op.getNumOperands();
6248 SmallVector<unsigned, 4> InsertIndices;
6249 SmallVector<int, 8> Mask(NumElems, -1);
6251 for (unsigned i = 0; i != NumElems; ++i) {
6252 unsigned Opc = Op.getOperand(i).getOpcode();
6254 if (Opc == ISD::UNDEF)
6257 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6258 // Quit if more than 1 elements need inserting.
6259 if (InsertIndices.size() > 1)
6262 InsertIndices.push_back(i);
6266 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6267 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6268 // Quit if non-constant index.
6269 if (!isa<ConstantSDNode>(ExtIdx))
6271 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6273 // Quit if extracted from vector of different type.
6274 if (ExtractedFromVec.getValueType() != VT)
6277 if (!VecIn1.getNode())
6278 VecIn1 = ExtractedFromVec;
6279 else if (VecIn1 != ExtractedFromVec) {
6280 if (!VecIn2.getNode())
6281 VecIn2 = ExtractedFromVec;
6282 else if (VecIn2 != ExtractedFromVec)
6283 // Quit if more than 2 vectors to shuffle
6287 if (ExtractedFromVec == VecIn1)
6289 else if (ExtractedFromVec == VecIn2)
6290 Mask[i] = Idx + NumElems;
6293 if (!VecIn1.getNode())
6296 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6297 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6298 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6299 unsigned Idx = InsertIndices[i];
6300 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6301 DAG.getIntPtrConstant(Idx));
6307 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6309 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6311 MVT VT = Op.getSimpleValueType();
6312 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6313 "Unexpected type in LowerBUILD_VECTORvXi1!");
6316 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6317 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6318 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6319 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6322 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6323 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6324 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6325 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6328 bool AllContants = true;
6329 uint64_t Immediate = 0;
6330 int NonConstIdx = -1;
6331 bool IsSplat = true;
6332 unsigned NumNonConsts = 0;
6333 unsigned NumConsts = 0;
6334 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6335 SDValue In = Op.getOperand(idx);
6336 if (In.getOpcode() == ISD::UNDEF)
6338 if (!isa<ConstantSDNode>(In)) {
6339 AllContants = false;
6345 if (cast<ConstantSDNode>(In)->getZExtValue())
6346 Immediate |= (1ULL << idx);
6348 if (In != Op.getOperand(0))
6353 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6354 DAG.getConstant(Immediate, MVT::i16));
6355 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6356 DAG.getIntPtrConstant(0));
6359 if (NumNonConsts == 1 && NonConstIdx != 0) {
6362 SDValue VecAsImm = DAG.getConstant(Immediate,
6363 MVT::getIntegerVT(VT.getSizeInBits()));
6364 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6367 DstVec = DAG.getUNDEF(VT);
6368 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6369 Op.getOperand(NonConstIdx),
6370 DAG.getIntPtrConstant(NonConstIdx));
6372 if (!IsSplat && (NonConstIdx != 0))
6373 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6374 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6377 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6378 DAG.getConstant(-1, SelectVT),
6379 DAG.getConstant(0, SelectVT));
6381 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6382 DAG.getConstant((Immediate | 1), SelectVT),
6383 DAG.getConstant(Immediate, SelectVT));
6384 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6387 /// \brief Return true if \p N implements a horizontal binop and return the
6388 /// operands for the horizontal binop into V0 and V1.
6390 /// This is a helper function of PerformBUILD_VECTORCombine.
6391 /// This function checks that the build_vector \p N in input implements a
6392 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6393 /// operation to match.
6394 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6395 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6396 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6399 /// This function only analyzes elements of \p N whose indices are
6400 /// in range [BaseIdx, LastIdx).
6401 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6403 unsigned BaseIdx, unsigned LastIdx,
6404 SDValue &V0, SDValue &V1) {
6405 EVT VT = N->getValueType(0);
6407 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6408 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6409 "Invalid Vector in input!");
6411 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6412 bool CanFold = true;
6413 unsigned ExpectedVExtractIdx = BaseIdx;
6414 unsigned NumElts = LastIdx - BaseIdx;
6415 V0 = DAG.getUNDEF(VT);
6416 V1 = DAG.getUNDEF(VT);
6418 // Check if N implements a horizontal binop.
6419 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6420 SDValue Op = N->getOperand(i + BaseIdx);
6423 if (Op->getOpcode() == ISD::UNDEF) {
6424 // Update the expected vector extract index.
6425 if (i * 2 == NumElts)
6426 ExpectedVExtractIdx = BaseIdx;
6427 ExpectedVExtractIdx += 2;
6431 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6436 SDValue Op0 = Op.getOperand(0);
6437 SDValue Op1 = Op.getOperand(1);
6439 // Try to match the following pattern:
6440 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6441 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6442 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6443 Op0.getOperand(0) == Op1.getOperand(0) &&
6444 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6445 isa<ConstantSDNode>(Op1.getOperand(1)));
6449 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6450 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6452 if (i * 2 < NumElts) {
6453 if (V0.getOpcode() == ISD::UNDEF)
6454 V0 = Op0.getOperand(0);
6456 if (V1.getOpcode() == ISD::UNDEF)
6457 V1 = Op0.getOperand(0);
6458 if (i * 2 == NumElts)
6459 ExpectedVExtractIdx = BaseIdx;
6462 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6463 if (I0 == ExpectedVExtractIdx)
6464 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6465 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6466 // Try to match the following dag sequence:
6467 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6468 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6472 ExpectedVExtractIdx += 2;
6478 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6479 /// a concat_vector.
6481 /// This is a helper function of PerformBUILD_VECTORCombine.
6482 /// This function expects two 256-bit vectors called V0 and V1.
6483 /// At first, each vector is split into two separate 128-bit vectors.
6484 /// Then, the resulting 128-bit vectors are used to implement two
6485 /// horizontal binary operations.
6487 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6489 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6490 /// the two new horizontal binop.
6491 /// When Mode is set, the first horizontal binop dag node would take as input
6492 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6493 /// horizontal binop dag node would take as input the lower 128-bit of V1
6494 /// and the upper 128-bit of V1.
6496 /// HADD V0_LO, V0_HI
6497 /// HADD V1_LO, V1_HI
6499 /// Otherwise, the first horizontal binop dag node takes as input the lower
6500 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6501 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6503 /// HADD V0_LO, V1_LO
6504 /// HADD V0_HI, V1_HI
6506 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6507 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6508 /// the upper 128-bits of the result.
6509 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6510 SDLoc DL, SelectionDAG &DAG,
6511 unsigned X86Opcode, bool Mode,
6512 bool isUndefLO, bool isUndefHI) {
6513 EVT VT = V0.getValueType();
6514 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6515 "Invalid nodes in input!");
6517 unsigned NumElts = VT.getVectorNumElements();
6518 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6519 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6520 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6521 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6522 EVT NewVT = V0_LO.getValueType();
6524 SDValue LO = DAG.getUNDEF(NewVT);
6525 SDValue HI = DAG.getUNDEF(NewVT);
6528 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6529 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6530 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6531 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6532 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6534 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6535 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6536 V1_LO->getOpcode() != ISD::UNDEF))
6537 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6539 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6540 V1_HI->getOpcode() != ISD::UNDEF))
6541 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6544 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6547 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6548 /// sequence of 'vadd + vsub + blendi'.
6549 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6550 const X86Subtarget *Subtarget) {
6552 EVT VT = BV->getValueType(0);
6553 unsigned NumElts = VT.getVectorNumElements();
6554 SDValue InVec0 = DAG.getUNDEF(VT);
6555 SDValue InVec1 = DAG.getUNDEF(VT);
6557 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6558 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6560 // Odd-numbered elements in the input build vector are obtained from
6561 // adding two integer/float elements.
6562 // Even-numbered elements in the input build vector are obtained from
6563 // subtracting two integer/float elements.
6564 unsigned ExpectedOpcode = ISD::FSUB;
6565 unsigned NextExpectedOpcode = ISD::FADD;
6566 bool AddFound = false;
6567 bool SubFound = false;
6569 for (unsigned i = 0, e = NumElts; i != e; i++) {
6570 SDValue Op = BV->getOperand(i);
6572 // Skip 'undef' values.
6573 unsigned Opcode = Op.getOpcode();
6574 if (Opcode == ISD::UNDEF) {
6575 std::swap(ExpectedOpcode, NextExpectedOpcode);
6579 // Early exit if we found an unexpected opcode.
6580 if (Opcode != ExpectedOpcode)
6583 SDValue Op0 = Op.getOperand(0);
6584 SDValue Op1 = Op.getOperand(1);
6586 // Try to match the following pattern:
6587 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6588 // Early exit if we cannot match that sequence.
6589 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6590 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6591 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6592 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6593 Op0.getOperand(1) != Op1.getOperand(1))
6596 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6600 // We found a valid add/sub node. Update the information accordingly.
6606 // Update InVec0 and InVec1.
6607 if (InVec0.getOpcode() == ISD::UNDEF)
6608 InVec0 = Op0.getOperand(0);
6609 if (InVec1.getOpcode() == ISD::UNDEF)
6610 InVec1 = Op1.getOperand(0);
6612 // Make sure that operands in input to each add/sub node always
6613 // come from a same pair of vectors.
6614 if (InVec0 != Op0.getOperand(0)) {
6615 if (ExpectedOpcode == ISD::FSUB)
6618 // FADD is commutable. Try to commute the operands
6619 // and then test again.
6620 std::swap(Op0, Op1);
6621 if (InVec0 != Op0.getOperand(0))
6625 if (InVec1 != Op1.getOperand(0))
6628 // Update the pair of expected opcodes.
6629 std::swap(ExpectedOpcode, NextExpectedOpcode);
6632 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6633 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6634 InVec1.getOpcode() != ISD::UNDEF)
6635 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6640 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6641 const X86Subtarget *Subtarget) {
6643 EVT VT = N->getValueType(0);
6644 unsigned NumElts = VT.getVectorNumElements();
6645 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6646 SDValue InVec0, InVec1;
6648 // Try to match an ADDSUB.
6649 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6650 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6651 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6652 if (Value.getNode())
6656 // Try to match horizontal ADD/SUB.
6657 unsigned NumUndefsLO = 0;
6658 unsigned NumUndefsHI = 0;
6659 unsigned Half = NumElts/2;
6661 // Count the number of UNDEF operands in the build_vector in input.
6662 for (unsigned i = 0, e = Half; i != e; ++i)
6663 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6666 for (unsigned i = Half, e = NumElts; i != e; ++i)
6667 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6670 // Early exit if this is either a build_vector of all UNDEFs or all the
6671 // operands but one are UNDEF.
6672 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6675 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6676 // Try to match an SSE3 float HADD/HSUB.
6677 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6678 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6680 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6681 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6682 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6683 // Try to match an SSSE3 integer HADD/HSUB.
6684 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6685 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6687 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6688 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6691 if (!Subtarget->hasAVX())
6694 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6695 // Try to match an AVX horizontal add/sub of packed single/double
6696 // precision floating point values from 256-bit vectors.
6697 SDValue InVec2, InVec3;
6698 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6699 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6700 ((InVec0.getOpcode() == ISD::UNDEF ||
6701 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6702 ((InVec1.getOpcode() == ISD::UNDEF ||
6703 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6704 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6706 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6707 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6708 ((InVec0.getOpcode() == ISD::UNDEF ||
6709 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6710 ((InVec1.getOpcode() == ISD::UNDEF ||
6711 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6712 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6713 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6714 // Try to match an AVX2 horizontal add/sub of signed integers.
6715 SDValue InVec2, InVec3;
6717 bool CanFold = true;
6719 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6720 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6721 ((InVec0.getOpcode() == ISD::UNDEF ||
6722 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6723 ((InVec1.getOpcode() == ISD::UNDEF ||
6724 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6725 X86Opcode = X86ISD::HADD;
6726 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6727 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6728 ((InVec0.getOpcode() == ISD::UNDEF ||
6729 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6730 ((InVec1.getOpcode() == ISD::UNDEF ||
6731 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6732 X86Opcode = X86ISD::HSUB;
6737 // Fold this build_vector into a single horizontal add/sub.
6738 // Do this only if the target has AVX2.
6739 if (Subtarget->hasAVX2())
6740 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6742 // Do not try to expand this build_vector into a pair of horizontal
6743 // add/sub if we can emit a pair of scalar add/sub.
6744 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6747 // Convert this build_vector into a pair of horizontal binop followed by
6749 bool isUndefLO = NumUndefsLO == Half;
6750 bool isUndefHI = NumUndefsHI == Half;
6751 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6752 isUndefLO, isUndefHI);
6756 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6757 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6759 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6760 X86Opcode = X86ISD::HADD;
6761 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6762 X86Opcode = X86ISD::HSUB;
6763 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6764 X86Opcode = X86ISD::FHADD;
6765 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6766 X86Opcode = X86ISD::FHSUB;
6770 // Don't try to expand this build_vector into a pair of horizontal add/sub
6771 // if we can simply emit a pair of scalar add/sub.
6772 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6775 // Convert this build_vector into two horizontal add/sub followed by
6777 bool isUndefLO = NumUndefsLO == Half;
6778 bool isUndefHI = NumUndefsHI == Half;
6779 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6780 isUndefLO, isUndefHI);
6787 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6790 MVT VT = Op.getSimpleValueType();
6791 MVT ExtVT = VT.getVectorElementType();
6792 unsigned NumElems = Op.getNumOperands();
6794 // Generate vectors for predicate vectors.
6795 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6796 return LowerBUILD_VECTORvXi1(Op, DAG);
6798 // Vectors containing all zeros can be matched by pxor and xorps later
6799 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6800 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6801 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6802 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6805 return getZeroVector(VT, Subtarget, DAG, dl);
6808 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6809 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6810 // vpcmpeqd on 256-bit vectors.
6811 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6812 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6815 if (!VT.is512BitVector())
6816 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6819 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6820 if (Broadcast.getNode())
6823 unsigned EVTBits = ExtVT.getSizeInBits();
6825 unsigned NumZero = 0;
6826 unsigned NumNonZero = 0;
6827 unsigned NonZeros = 0;
6828 bool IsAllConstants = true;
6829 SmallSet<SDValue, 8> Values;
6830 for (unsigned i = 0; i < NumElems; ++i) {
6831 SDValue Elt = Op.getOperand(i);
6832 if (Elt.getOpcode() == ISD::UNDEF)
6835 if (Elt.getOpcode() != ISD::Constant &&
6836 Elt.getOpcode() != ISD::ConstantFP)
6837 IsAllConstants = false;
6838 if (X86::isZeroNode(Elt))
6841 NonZeros |= (1 << i);
6846 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6847 if (NumNonZero == 0)
6848 return DAG.getUNDEF(VT);
6850 // Special case for single non-zero, non-undef, element.
6851 if (NumNonZero == 1) {
6852 unsigned Idx = countTrailingZeros(NonZeros);
6853 SDValue Item = Op.getOperand(Idx);
6855 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6856 // the value are obviously zero, truncate the value to i32 and do the
6857 // insertion that way. Only do this if the value is non-constant or if the
6858 // value is a constant being inserted into element 0. It is cheaper to do
6859 // a constant pool load than it is to do a movd + shuffle.
6860 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6861 (!IsAllConstants || Idx == 0)) {
6862 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6864 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6865 EVT VecVT = MVT::v4i32;
6866 unsigned VecElts = 4;
6868 // Truncate the value (which may itself be a constant) to i32, and
6869 // convert it to a vector with movd (S2V+shuffle to zero extend).
6870 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6871 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6873 // If using the new shuffle lowering, just directly insert this.
6874 if (ExperimentalVectorShuffleLowering)
6876 ISD::BITCAST, dl, VT,
6877 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6879 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6881 // Now we have our 32-bit value zero extended in the low element of
6882 // a vector. If Idx != 0, swizzle it into place.
6884 SmallVector<int, 4> Mask;
6885 Mask.push_back(Idx);
6886 for (unsigned i = 1; i != VecElts; ++i)
6888 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6891 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6895 // If we have a constant or non-constant insertion into the low element of
6896 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6897 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6898 // depending on what the source datatype is.
6901 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6903 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6904 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6905 if (VT.is256BitVector() || VT.is512BitVector()) {
6906 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6907 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6908 Item, DAG.getIntPtrConstant(0));
6910 assert(VT.is128BitVector() && "Expected an SSE value type!");
6911 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6912 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6913 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6916 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6917 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6918 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6919 if (VT.is256BitVector()) {
6920 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6921 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6923 assert(VT.is128BitVector() && "Expected an SSE value type!");
6924 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6926 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6930 // Is it a vector logical left shift?
6931 if (NumElems == 2 && Idx == 1 &&
6932 X86::isZeroNode(Op.getOperand(0)) &&
6933 !X86::isZeroNode(Op.getOperand(1))) {
6934 unsigned NumBits = VT.getSizeInBits();
6935 return getVShift(true, VT,
6936 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6937 VT, Op.getOperand(1)),
6938 NumBits/2, DAG, *this, dl);
6941 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6944 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6945 // is a non-constant being inserted into an element other than the low one,
6946 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6947 // movd/movss) to move this into the low element, then shuffle it into
6949 if (EVTBits == 32) {
6950 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6952 // If using the new shuffle lowering, just directly insert this.
6953 if (ExperimentalVectorShuffleLowering)
6954 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6956 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6957 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6958 SmallVector<int, 8> MaskVec;
6959 for (unsigned i = 0; i != NumElems; ++i)
6960 MaskVec.push_back(i == Idx ? 0 : 1);
6961 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6965 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6966 if (Values.size() == 1) {
6967 if (EVTBits == 32) {
6968 // Instead of a shuffle like this:
6969 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6970 // Check if it's possible to issue this instead.
6971 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6972 unsigned Idx = countTrailingZeros(NonZeros);
6973 SDValue Item = Op.getOperand(Idx);
6974 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6975 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6980 // A vector full of immediates; various special cases are already
6981 // handled, so this is best done with a single constant-pool load.
6985 // For AVX-length vectors, build the individual 128-bit pieces and use
6986 // shuffles to put them in place.
6987 if (VT.is256BitVector() || VT.is512BitVector()) {
6988 SmallVector<SDValue, 64> V;
6989 for (unsigned i = 0; i != NumElems; ++i)
6990 V.push_back(Op.getOperand(i));
6992 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6994 // Build both the lower and upper subvector.
6995 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6996 makeArrayRef(&V[0], NumElems/2));
6997 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6998 makeArrayRef(&V[NumElems / 2], NumElems/2));
7000 // Recreate the wider vector with the lower and upper part.
7001 if (VT.is256BitVector())
7002 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7003 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7006 // Let legalizer expand 2-wide build_vectors.
7007 if (EVTBits == 64) {
7008 if (NumNonZero == 1) {
7009 // One half is zero or undef.
7010 unsigned Idx = countTrailingZeros(NonZeros);
7011 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7012 Op.getOperand(Idx));
7013 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7018 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7019 if (EVTBits == 8 && NumElems == 16) {
7020 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7022 if (V.getNode()) return V;
7025 if (EVTBits == 16 && NumElems == 8) {
7026 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7028 if (V.getNode()) return V;
7031 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7032 if (EVTBits == 32 && NumElems == 4) {
7033 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7038 // If element VT is == 32 bits, turn it into a number of shuffles.
7039 SmallVector<SDValue, 8> V(NumElems);
7040 if (NumElems == 4 && NumZero > 0) {
7041 for (unsigned i = 0; i < 4; ++i) {
7042 bool isZero = !(NonZeros & (1 << i));
7044 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7046 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7049 for (unsigned i = 0; i < 2; ++i) {
7050 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7053 V[i] = V[i*2]; // Must be a zero vector.
7056 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7059 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7062 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7067 bool Reverse1 = (NonZeros & 0x3) == 2;
7068 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7072 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7073 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7075 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7078 if (Values.size() > 1 && VT.is128BitVector()) {
7079 // Check for a build vector of consecutive loads.
7080 for (unsigned i = 0; i < NumElems; ++i)
7081 V[i] = Op.getOperand(i);
7083 // Check for elements which are consecutive loads.
7084 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7088 // Check for a build vector from mostly shuffle plus few inserting.
7089 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7093 // For SSE 4.1, use insertps to put the high elements into the low element.
7094 if (getSubtarget()->hasSSE41()) {
7096 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7097 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7099 Result = DAG.getUNDEF(VT);
7101 for (unsigned i = 1; i < NumElems; ++i) {
7102 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7103 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7104 Op.getOperand(i), DAG.getIntPtrConstant(i));
7109 // Otherwise, expand into a number of unpckl*, start by extending each of
7110 // our (non-undef) elements to the full vector width with the element in the
7111 // bottom slot of the vector (which generates no code for SSE).
7112 for (unsigned i = 0; i < NumElems; ++i) {
7113 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7114 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7116 V[i] = DAG.getUNDEF(VT);
7119 // Next, we iteratively mix elements, e.g. for v4f32:
7120 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7121 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7122 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7123 unsigned EltStride = NumElems >> 1;
7124 while (EltStride != 0) {
7125 for (unsigned i = 0; i < EltStride; ++i) {
7126 // If V[i+EltStride] is undef and this is the first round of mixing,
7127 // then it is safe to just drop this shuffle: V[i] is already in the
7128 // right place, the one element (since it's the first round) being
7129 // inserted as undef can be dropped. This isn't safe for successive
7130 // rounds because they will permute elements within both vectors.
7131 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7132 EltStride == NumElems/2)
7135 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7144 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7145 // to create 256-bit vectors from two other 128-bit ones.
7146 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7148 MVT ResVT = Op.getSimpleValueType();
7150 assert((ResVT.is256BitVector() ||
7151 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7153 SDValue V1 = Op.getOperand(0);
7154 SDValue V2 = Op.getOperand(1);
7155 unsigned NumElems = ResVT.getVectorNumElements();
7156 if(ResVT.is256BitVector())
7157 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7159 if (Op.getNumOperands() == 4) {
7160 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7161 ResVT.getVectorNumElements()/2);
7162 SDValue V3 = Op.getOperand(2);
7163 SDValue V4 = Op.getOperand(3);
7164 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7165 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7167 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7170 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7171 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7172 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7173 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7174 Op.getNumOperands() == 4)));
7176 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7177 // from two other 128-bit ones.
7179 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7180 return LowerAVXCONCAT_VECTORS(Op, DAG);
7184 //===----------------------------------------------------------------------===//
7185 // Vector shuffle lowering
7187 // This is an experimental code path for lowering vector shuffles on x86. It is
7188 // designed to handle arbitrary vector shuffles and blends, gracefully
7189 // degrading performance as necessary. It works hard to recognize idiomatic
7190 // shuffles and lower them to optimal instruction patterns without leaving
7191 // a framework that allows reasonably efficient handling of all vector shuffle
7193 //===----------------------------------------------------------------------===//
7195 /// \brief Tiny helper function to identify a no-op mask.
7197 /// This is a somewhat boring predicate function. It checks whether the mask
7198 /// array input, which is assumed to be a single-input shuffle mask of the kind
7199 /// used by the X86 shuffle instructions (not a fully general
7200 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7201 /// in-place shuffle are 'no-op's.
7202 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7203 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7204 if (Mask[i] != -1 && Mask[i] != i)
7209 /// \brief Helper function to classify a mask as a single-input mask.
7211 /// This isn't a generic single-input test because in the vector shuffle
7212 /// lowering we canonicalize single inputs to be the first input operand. This
7213 /// means we can more quickly test for a single input by only checking whether
7214 /// an input from the second operand exists. We also assume that the size of
7215 /// mask corresponds to the size of the input vectors which isn't true in the
7216 /// fully general case.
7217 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7219 if (M >= (int)Mask.size())
7224 /// \brief Test whether there are elements crossing 128-bit lanes in this
7227 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7228 /// and we routinely test for these.
7229 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7230 int LaneSize = 128 / VT.getScalarSizeInBits();
7231 int Size = Mask.size();
7232 for (int i = 0; i < Size; ++i)
7233 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7238 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7240 /// This checks a shuffle mask to see if it is performing the same
7241 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7242 /// that it is also not lane-crossing. It may however involve a blend from the
7243 /// same lane of a second vector.
7245 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7246 /// non-trivial to compute in the face of undef lanes. The representation is
7247 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7248 /// entries from both V1 and V2 inputs to the wider mask.
7250 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7251 SmallVectorImpl<int> &RepeatedMask) {
7252 int LaneSize = 128 / VT.getScalarSizeInBits();
7253 RepeatedMask.resize(LaneSize, -1);
7254 int Size = Mask.size();
7255 for (int i = 0; i < Size; ++i) {
7258 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7259 // This entry crosses lanes, so there is no way to model this shuffle.
7262 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7263 if (RepeatedMask[i % LaneSize] == -1)
7264 // This is the first non-undef entry in this slot of a 128-bit lane.
7265 RepeatedMask[i % LaneSize] =
7266 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7267 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7268 // Found a mismatch with the repeated mask.
7274 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7275 // 2013 will allow us to use it as a non-type template parameter.
7278 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7280 /// See its documentation for details.
7281 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7282 if (Mask.size() != Args.size())
7284 for (int i = 0, e = Mask.size(); i < e; ++i) {
7285 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7286 if (Mask[i] != -1 && Mask[i] != *Args[i])
7294 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7297 /// This is a fast way to test a shuffle mask against a fixed pattern:
7299 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7301 /// It returns true if the mask is exactly as wide as the argument list, and
7302 /// each element of the mask is either -1 (signifying undef) or the value given
7303 /// in the argument.
7304 static const VariadicFunction1<
7305 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7307 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7309 /// This helper function produces an 8-bit shuffle immediate corresponding to
7310 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7311 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7314 /// NB: We rely heavily on "undef" masks preserving the input lane.
7315 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7316 SelectionDAG &DAG) {
7317 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7318 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7319 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7320 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7321 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7324 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7325 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7326 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7327 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7328 return DAG.getConstant(Imm, MVT::i8);
7331 /// \brief Try to emit a blend instruction for a shuffle.
7333 /// This doesn't do any checks for the availability of instructions for blending
7334 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7335 /// be matched in the backend with the type given. What it does check for is
7336 /// that the shuffle mask is in fact a blend.
7337 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7338 SDValue V2, ArrayRef<int> Mask,
7339 const X86Subtarget *Subtarget,
7340 SelectionDAG &DAG) {
7342 unsigned BlendMask = 0;
7343 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7344 if (Mask[i] >= Size) {
7345 if (Mask[i] != i + Size)
7346 return SDValue(); // Shuffled V2 input!
7347 BlendMask |= 1u << i;
7350 if (Mask[i] >= 0 && Mask[i] != i)
7351 return SDValue(); // Shuffled V1 input!
7353 switch (VT.SimpleTy) {
7358 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7359 DAG.getConstant(BlendMask, MVT::i8));
7363 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7367 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7368 // that instruction.
7369 if (Subtarget->hasAVX2()) {
7370 // Scale the blend by the number of 32-bit dwords per element.
7371 int Scale = VT.getScalarSizeInBits() / 32;
7373 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7374 if (Mask[i] >= Size)
7375 for (int j = 0; j < Scale; ++j)
7376 BlendMask |= 1u << (i * Scale + j);
7378 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7379 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7380 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7381 return DAG.getNode(ISD::BITCAST, DL, VT,
7382 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7383 DAG.getConstant(BlendMask, MVT::i8)));
7387 // For integer shuffles we need to expand the mask and cast the inputs to
7388 // v8i16s prior to blending.
7389 int Scale = 8 / VT.getVectorNumElements();
7391 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7392 if (Mask[i] >= Size)
7393 for (int j = 0; j < Scale; ++j)
7394 BlendMask |= 1u << (i * Scale + j);
7396 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7397 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7398 return DAG.getNode(ISD::BITCAST, DL, VT,
7399 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7400 DAG.getConstant(BlendMask, MVT::i8)));
7404 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7405 SmallVector<int, 8> RepeatedMask;
7406 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7407 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7408 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7410 for (int i = 0; i < 8; ++i)
7411 if (RepeatedMask[i] >= 16)
7412 BlendMask |= 1u << i;
7413 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7414 DAG.getConstant(BlendMask, MVT::i8));
7419 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7420 // Scale the blend by the number of bytes per element.
7421 int Scale = VT.getScalarSizeInBits() / 8;
7422 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7424 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7425 // mix of LLVM's code generator and the x86 backend. We tell the code
7426 // generator that boolean values in the elements of an x86 vector register
7427 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7428 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7429 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7430 // of the element (the remaining are ignored) and 0 in that high bit would
7431 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7432 // the LLVM model for boolean values in vector elements gets the relevant
7433 // bit set, it is set backwards and over constrained relative to x86's
7435 SDValue VSELECTMask[32];
7436 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7437 for (int j = 0; j < Scale; ++j)
7438 VSELECTMask[Scale * i + j] =
7439 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7440 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7442 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7443 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7445 ISD::BITCAST, DL, VT,
7446 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7447 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7452 llvm_unreachable("Not a supported integer vector type!");
7456 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7457 /// unblended shuffles followed by an unshuffled blend.
7459 /// This matches the extremely common pattern for handling combined
7460 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7462 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7466 SelectionDAG &DAG) {
7467 // Shuffle the input elements into the desired positions in V1 and V2 and
7468 // blend them together.
7469 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7470 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7471 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7472 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7473 if (Mask[i] >= 0 && Mask[i] < Size) {
7474 V1Mask[i] = Mask[i];
7476 } else if (Mask[i] >= Size) {
7477 V2Mask[i] = Mask[i] - Size;
7478 BlendMask[i] = i + Size;
7481 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7482 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7483 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7486 /// \brief Try to lower a vector shuffle as a byte rotation.
7488 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7489 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7490 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7491 /// try to generically lower a vector shuffle through such an pattern. It
7492 /// does not check for the profitability of lowering either as PALIGNR or
7493 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7494 /// This matches shuffle vectors that look like:
7496 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7498 /// Essentially it concatenates V1 and V2, shifts right by some number of
7499 /// elements, and takes the low elements as the result. Note that while this is
7500 /// specified as a *right shift* because x86 is little-endian, it is a *left
7501 /// rotate* of the vector lanes.
7503 /// Note that this only handles 128-bit vector widths currently.
7504 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7507 const X86Subtarget *Subtarget,
7508 SelectionDAG &DAG) {
7509 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7511 // We need to detect various ways of spelling a rotation:
7512 // [11, 12, 13, 14, 15, 0, 1, 2]
7513 // [-1, 12, 13, 14, -1, -1, 1, -1]
7514 // [-1, -1, -1, -1, -1, -1, 1, 2]
7515 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7516 // [-1, 4, 5, 6, -1, -1, 9, -1]
7517 // [-1, 4, 5, 6, -1, -1, -1, -1]
7520 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7523 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7525 // Based on the mod-Size value of this mask element determine where
7526 // a rotated vector would have started.
7527 int StartIdx = i - (Mask[i] % Size);
7529 // The identity rotation isn't interesting, stop.
7532 // If we found the tail of a vector the rotation must be the missing
7533 // front. If we found the head of a vector, it must be how much of the head.
7534 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7537 Rotation = CandidateRotation;
7538 else if (Rotation != CandidateRotation)
7539 // The rotations don't match, so we can't match this mask.
7542 // Compute which value this mask is pointing at.
7543 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7545 // Compute which of the two target values this index should be assigned to.
7546 // This reflects whether the high elements are remaining or the low elements
7548 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7550 // Either set up this value if we've not encountered it before, or check
7551 // that it remains consistent.
7554 else if (TargetV != MaskV)
7555 // This may be a rotation, but it pulls from the inputs in some
7556 // unsupported interleaving.
7560 // Check that we successfully analyzed the mask, and normalize the results.
7561 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7562 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7568 assert(VT.getSizeInBits() == 128 &&
7569 "Rotate-based lowering only supports 128-bit lowering!");
7570 assert(Mask.size() <= 16 &&
7571 "Can shuffle at most 16 bytes in a 128-bit vector!");
7573 // The actual rotate instruction rotates bytes, so we need to scale the
7574 // rotation based on how many bytes are in the vector.
7575 int Scale = 16 / Mask.size();
7577 // SSSE3 targets can use the palignr instruction
7578 if (Subtarget->hasSSSE3()) {
7579 // Cast the inputs to v16i8 to match PALIGNR.
7580 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7581 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7583 return DAG.getNode(ISD::BITCAST, DL, VT,
7584 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7585 DAG.getConstant(Rotation * Scale, MVT::i8)));
7588 // Default SSE2 implementation
7589 int LoByteShift = 16 - Rotation * Scale;
7590 int HiByteShift = Rotation * Scale;
7592 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7593 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7594 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7596 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7597 DAG.getConstant(8 * LoByteShift, MVT::i8));
7598 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7599 DAG.getConstant(8 * HiByteShift, MVT::i8));
7600 return DAG.getNode(ISD::BITCAST, DL, VT,
7601 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7604 /// \brief Compute whether each element of a shuffle is zeroable.
7606 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7607 /// Either it is an undef element in the shuffle mask, the element of the input
7608 /// referenced is undef, or the element of the input referenced is known to be
7609 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7610 /// as many lanes with this technique as possible to simplify the remaining
7612 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7613 SDValue V1, SDValue V2) {
7614 SmallBitVector Zeroable(Mask.size(), false);
7616 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7617 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7619 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7621 // Handle the easy cases.
7622 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7627 // If this is an index into a build_vector node, dig out the input value and
7629 SDValue V = M < Size ? V1 : V2;
7630 if (V.getOpcode() != ISD::BUILD_VECTOR)
7633 SDValue Input = V.getOperand(M % Size);
7634 // The UNDEF opcode check really should be dead code here, but not quite
7635 // worth asserting on (it isn't invalid, just unexpected).
7636 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7643 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7645 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7646 /// byte-shift instructions. The mask must consist of a shifted sequential
7647 /// shuffle from one of the input vectors and zeroable elements for the
7648 /// remaining 'shifted in' elements.
7650 /// Note that this only handles 128-bit vector widths currently.
7651 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7652 SDValue V2, ArrayRef<int> Mask,
7653 SelectionDAG &DAG) {
7654 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7656 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7658 int Size = Mask.size();
7659 int Scale = 16 / Size;
7661 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7662 ArrayRef<int> Mask) {
7663 for (int i = StartIndex; i < EndIndex; i++) {
7666 if (i + Base != Mask[i] - MaskOffset)
7672 for (int Shift = 1; Shift < Size; Shift++) {
7673 int ByteShift = Shift * Scale;
7675 // PSRLDQ : (little-endian) right byte shift
7676 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7677 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7678 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7679 bool ZeroableRight = true;
7680 for (int i = Size - Shift; i < Size; i++) {
7681 ZeroableRight &= Zeroable[i];
7684 if (ZeroableRight) {
7685 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7686 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7688 if (ValidShiftRight1 || ValidShiftRight2) {
7689 // Cast the inputs to v2i64 to match PSRLDQ.
7690 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7691 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7692 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7693 DAG.getConstant(ByteShift * 8, MVT::i8));
7694 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7698 // PSLLDQ : (little-endian) left byte shift
7699 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7700 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7701 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7702 bool ZeroableLeft = true;
7703 for (int i = 0; i < Shift; i++) {
7704 ZeroableLeft &= Zeroable[i];
7708 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7709 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7711 if (ValidShiftLeft1 || ValidShiftLeft2) {
7712 // Cast the inputs to v2i64 to match PSLLDQ.
7713 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7714 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7715 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7716 DAG.getConstant(ByteShift * 8, MVT::i8));
7717 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7725 /// \brief Lower a vector shuffle as a zero or any extension.
7727 /// Given a specific number of elements, element bit width, and extension
7728 /// stride, produce either a zero or any extension based on the available
7729 /// features of the subtarget.
7730 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7731 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7732 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7733 assert(Scale > 1 && "Need a scale to extend.");
7734 int EltBits = VT.getSizeInBits() / NumElements;
7735 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7736 "Only 8, 16, and 32 bit elements can be extended.");
7737 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7739 // Found a valid zext mask! Try various lowering strategies based on the
7740 // input type and available ISA extensions.
7741 if (Subtarget->hasSSE41()) {
7742 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7743 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7744 NumElements / Scale);
7745 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7746 return DAG.getNode(ISD::BITCAST, DL, VT,
7747 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7750 // For any extends we can cheat for larger element sizes and use shuffle
7751 // instructions that can fold with a load and/or copy.
7752 if (AnyExt && EltBits == 32) {
7753 int PSHUFDMask[4] = {0, -1, 1, -1};
7755 ISD::BITCAST, DL, VT,
7756 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7757 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7758 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7760 if (AnyExt && EltBits == 16 && Scale > 2) {
7761 int PSHUFDMask[4] = {0, -1, 0, -1};
7762 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7763 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7764 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7765 int PSHUFHWMask[4] = {1, -1, -1, -1};
7767 ISD::BITCAST, DL, VT,
7768 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7769 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7770 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7773 // If this would require more than 2 unpack instructions to expand, use
7774 // pshufb when available. We can only use more than 2 unpack instructions
7775 // when zero extending i8 elements which also makes it easier to use pshufb.
7776 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7777 assert(NumElements == 16 && "Unexpected byte vector width!");
7778 SDValue PSHUFBMask[16];
7779 for (int i = 0; i < 16; ++i)
7781 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7782 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7783 return DAG.getNode(ISD::BITCAST, DL, VT,
7784 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7785 DAG.getNode(ISD::BUILD_VECTOR, DL,
7786 MVT::v16i8, PSHUFBMask)));
7789 // Otherwise emit a sequence of unpacks.
7791 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7792 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7793 : getZeroVector(InputVT, Subtarget, DAG, DL);
7794 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7795 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7799 } while (Scale > 1);
7800 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7803 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7805 /// This routine will try to do everything in its power to cleverly lower
7806 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7807 /// check for the profitability of this lowering, it tries to aggressively
7808 /// match this pattern. It will use all of the micro-architectural details it
7809 /// can to emit an efficient lowering. It handles both blends with all-zero
7810 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7811 /// masking out later).
7813 /// The reason we have dedicated lowering for zext-style shuffles is that they
7814 /// are both incredibly common and often quite performance sensitive.
7815 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7816 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7817 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7818 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7820 int Bits = VT.getSizeInBits();
7821 int NumElements = Mask.size();
7823 // Define a helper function to check a particular ext-scale and lower to it if
7825 auto Lower = [&](int Scale) -> SDValue {
7828 for (int i = 0; i < NumElements; ++i) {
7830 continue; // Valid anywhere but doesn't tell us anything.
7831 if (i % Scale != 0) {
7832 // Each of the extend elements needs to be zeroable.
7836 // We no lorger are in the anyext case.
7841 // Each of the base elements needs to be consecutive indices into the
7842 // same input vector.
7843 SDValue V = Mask[i] < NumElements ? V1 : V2;
7846 else if (InputV != V)
7847 return SDValue(); // Flip-flopping inputs.
7849 if (Mask[i] % NumElements != i / Scale)
7850 return SDValue(); // Non-consecutive strided elemenst.
7853 // If we fail to find an input, we have a zero-shuffle which should always
7854 // have already been handled.
7855 // FIXME: Maybe handle this here in case during blending we end up with one?
7859 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7860 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7863 // The widest scale possible for extending is to a 64-bit integer.
7864 assert(Bits % 64 == 0 &&
7865 "The number of bits in a vector must be divisible by 64 on x86!");
7866 int NumExtElements = Bits / 64;
7868 // Each iteration, try extending the elements half as much, but into twice as
7870 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7871 assert(NumElements % NumExtElements == 0 &&
7872 "The input vector size must be divisble by the extended size.");
7873 if (SDValue V = Lower(NumElements / NumExtElements))
7877 // No viable ext lowering found.
7881 /// \brief Try to get a scalar value for a specific element of a vector.
7883 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7884 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7885 SelectionDAG &DAG) {
7886 MVT VT = V.getSimpleValueType();
7887 MVT EltVT = VT.getVectorElementType();
7888 while (V.getOpcode() == ISD::BITCAST)
7889 V = V.getOperand(0);
7890 // If the bitcasts shift the element size, we can't extract an equivalent
7892 MVT NewVT = V.getSimpleValueType();
7893 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7896 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7897 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7898 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7903 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7905 /// This is particularly important because the set of instructions varies
7906 /// significantly based on whether the operand is a load or not.
7907 static bool isShuffleFoldableLoad(SDValue V) {
7908 while (V.getOpcode() == ISD::BITCAST)
7909 V = V.getOperand(0);
7911 return ISD::isNON_EXTLoad(V.getNode());
7914 /// \brief Try to lower insertion of a single element into a zero vector.
7916 /// This is a common pattern that we have especially efficient patterns to lower
7917 /// across all subtarget feature sets.
7918 static SDValue lowerVectorShuffleAsElementInsertion(
7919 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7920 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7921 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7923 MVT EltVT = VT.getVectorElementType();
7925 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7926 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7928 bool IsV1Zeroable = true;
7929 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7930 if (i != V2Index && !Zeroable[i]) {
7931 IsV1Zeroable = false;
7935 // Check for a single input from a SCALAR_TO_VECTOR node.
7936 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7937 // all the smarts here sunk into that routine. However, the current
7938 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7939 // vector shuffle lowering is dead.
7940 if (SDValue V2S = getScalarValueForVectorElement(
7941 V2, Mask[V2Index] - Mask.size(), DAG)) {
7942 // We need to zext the scalar if it is smaller than an i32.
7943 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7944 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7945 // Using zext to expand a narrow element won't work for non-zero
7950 // Zero-extend directly to i32.
7952 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7954 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7955 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7956 EltVT == MVT::i16) {
7957 // Either not inserting from the low element of the input or the input
7958 // element size is too small to use VZEXT_MOVL to clear the high bits.
7962 if (!IsV1Zeroable) {
7963 // If V1 can't be treated as a zero vector we have fewer options to lower
7964 // this. We can't support integer vectors or non-zero targets cheaply, and
7965 // the V1 elements can't be permuted in any way.
7966 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7967 if (!VT.isFloatingPoint() || V2Index != 0)
7969 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7970 V1Mask[V2Index] = -1;
7971 if (!isNoopShuffleMask(V1Mask))
7973 // This is essentially a special case blend operation, but if we have
7974 // general purpose blend operations, they are always faster. Bail and let
7975 // the rest of the lowering handle these as blends.
7976 if (Subtarget->hasSSE41())
7979 // Otherwise, use MOVSD or MOVSS.
7980 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7981 "Only two types of floating point element types to handle!");
7982 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7986 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7988 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7991 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7992 // the desired position. Otherwise it is more efficient to do a vector
7993 // shift left. We know that we can do a vector shift left because all
7994 // the inputs are zero.
7995 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7996 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7997 V2Shuffle[V2Index] = 0;
7998 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8000 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8002 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8004 V2Index * EltVT.getSizeInBits(),
8005 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8006 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8012 /// \brief Try to lower broadcast of a single element.
8014 /// For convenience, this code also bundles all of the subtarget feature set
8015 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8016 /// a convenient way to factor it out.
8017 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8019 const X86Subtarget *Subtarget,
8020 SelectionDAG &DAG) {
8021 if (!Subtarget->hasAVX())
8023 if (VT.isInteger() && !Subtarget->hasAVX2())
8026 // Check that the mask is a broadcast.
8027 int BroadcastIdx = -1;
8029 if (M >= 0 && BroadcastIdx == -1)
8031 else if (M >= 0 && M != BroadcastIdx)
8034 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8035 "a sorted mask where the broadcast "
8038 // Go up the chain of (vector) values to try and find a scalar load that
8039 // we can combine with the broadcast.
8041 switch (V.getOpcode()) {
8042 case ISD::CONCAT_VECTORS: {
8043 int OperandSize = Mask.size() / V.getNumOperands();
8044 V = V.getOperand(BroadcastIdx / OperandSize);
8045 BroadcastIdx %= OperandSize;
8049 case ISD::INSERT_SUBVECTOR: {
8050 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8051 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8055 int BeginIdx = (int)ConstantIdx->getZExtValue();
8057 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8058 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8059 BroadcastIdx -= BeginIdx;
8070 // Check if this is a broadcast of a scalar. We special case lowering
8071 // for scalars so that we can more effectively fold with loads.
8072 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8073 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8074 V = V.getOperand(BroadcastIdx);
8076 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8078 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8080 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8081 // We can't broadcast from a vector register w/o AVX2, and we can only
8082 // broadcast from the zero-element of a vector register.
8086 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8089 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8091 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8092 /// support for floating point shuffles but not integer shuffles. These
8093 /// instructions will incur a domain crossing penalty on some chips though so
8094 /// it is better to avoid lowering through this for integer vectors where
8096 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8097 const X86Subtarget *Subtarget,
8098 SelectionDAG &DAG) {
8100 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8101 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8102 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8103 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8104 ArrayRef<int> Mask = SVOp->getMask();
8105 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8107 if (isSingleInputShuffleMask(Mask)) {
8108 // Straight shuffle of a single input vector. Simulate this by using the
8109 // single input as both of the "inputs" to this instruction..
8110 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8112 if (Subtarget->hasAVX()) {
8113 // If we have AVX, we can use VPERMILPS which will allow folding a load
8114 // into the shuffle.
8115 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8116 DAG.getConstant(SHUFPDMask, MVT::i8));
8119 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8120 DAG.getConstant(SHUFPDMask, MVT::i8));
8122 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8123 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8125 // Use dedicated unpack instructions for masks that match their pattern.
8126 if (isShuffleEquivalent(Mask, 0, 2))
8127 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8128 if (isShuffleEquivalent(Mask, 1, 3))
8129 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8131 // If we have a single input, insert that into V1 if we can do so cheaply.
8132 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8133 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8134 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8136 // Try inverting the insertion since for v2 masks it is easy to do and we
8137 // can't reliably sort the mask one way or the other.
8138 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8139 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8140 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8141 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8145 // Try to use one of the special instruction patterns to handle two common
8146 // blend patterns if a zero-blend above didn't work.
8147 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8148 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8149 // We can either use a special instruction to load over the low double or
8150 // to move just the low double.
8152 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8154 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8156 if (Subtarget->hasSSE41())
8157 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8161 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8162 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8163 DAG.getConstant(SHUFPDMask, MVT::i8));
8166 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8168 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8169 /// the integer unit to minimize domain crossing penalties. However, for blends
8170 /// it falls back to the floating point shuffle operation with appropriate bit
8172 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8173 const X86Subtarget *Subtarget,
8174 SelectionDAG &DAG) {
8176 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8177 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8178 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8179 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8180 ArrayRef<int> Mask = SVOp->getMask();
8181 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8183 if (isSingleInputShuffleMask(Mask)) {
8184 // Check for being able to broadcast a single element.
8185 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8186 Mask, Subtarget, DAG))
8189 // Straight shuffle of a single input vector. For everything from SSE2
8190 // onward this has a single fast instruction with no scary immediates.
8191 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8192 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8193 int WidenedMask[4] = {
8194 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8195 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8197 ISD::BITCAST, DL, MVT::v2i64,
8198 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8199 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8202 // If we have a single input from V2 insert that into V1 if we can do so
8204 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8205 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8206 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8208 // Try inverting the insertion since for v2 masks it is easy to do and we
8209 // can't reliably sort the mask one way or the other.
8210 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8211 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8212 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8213 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8217 // Use dedicated unpack instructions for masks that match their pattern.
8218 if (isShuffleEquivalent(Mask, 0, 2))
8219 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8220 if (isShuffleEquivalent(Mask, 1, 3))
8221 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8223 if (Subtarget->hasSSE41())
8224 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8228 // Try to use byte shift instructions.
8229 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8230 DL, MVT::v2i64, V1, V2, Mask, DAG))
8233 // Try to use byte rotation instructions.
8234 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8235 if (Subtarget->hasSSSE3())
8236 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8237 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8240 // We implement this with SHUFPD which is pretty lame because it will likely
8241 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8242 // However, all the alternatives are still more cycles and newer chips don't
8243 // have this problem. It would be really nice if x86 had better shuffles here.
8244 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8245 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8246 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8247 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8250 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8252 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8253 /// It makes no assumptions about whether this is the *best* lowering, it simply
8255 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8256 ArrayRef<int> Mask, SDValue V1,
8257 SDValue V2, SelectionDAG &DAG) {
8258 SDValue LowV = V1, HighV = V2;
8259 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8262 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8264 if (NumV2Elements == 1) {
8266 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8269 // Compute the index adjacent to V2Index and in the same half by toggling
8271 int V2AdjIndex = V2Index ^ 1;
8273 if (Mask[V2AdjIndex] == -1) {
8274 // Handles all the cases where we have a single V2 element and an undef.
8275 // This will only ever happen in the high lanes because we commute the
8276 // vector otherwise.
8278 std::swap(LowV, HighV);
8279 NewMask[V2Index] -= 4;
8281 // Handle the case where the V2 element ends up adjacent to a V1 element.
8282 // To make this work, blend them together as the first step.
8283 int V1Index = V2AdjIndex;
8284 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8285 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8286 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8288 // Now proceed to reconstruct the final blend as we have the necessary
8289 // high or low half formed.
8296 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8297 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8299 } else if (NumV2Elements == 2) {
8300 if (Mask[0] < 4 && Mask[1] < 4) {
8301 // Handle the easy case where we have V1 in the low lanes and V2 in the
8305 } else if (Mask[2] < 4 && Mask[3] < 4) {
8306 // We also handle the reversed case because this utility may get called
8307 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8308 // arrange things in the right direction.
8314 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8315 // trying to place elements directly, just blend them and set up the final
8316 // shuffle to place them.
8318 // The first two blend mask elements are for V1, the second two are for
8320 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8321 Mask[2] < 4 ? Mask[2] : Mask[3],
8322 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8323 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8324 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8325 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8327 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8330 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8331 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8332 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8333 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8336 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8337 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8340 /// \brief Lower 4-lane 32-bit floating point shuffles.
8342 /// Uses instructions exclusively from the floating point unit to minimize
8343 /// domain crossing penalties, as these are sufficient to implement all v4f32
8345 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8346 const X86Subtarget *Subtarget,
8347 SelectionDAG &DAG) {
8349 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8350 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8351 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8352 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8353 ArrayRef<int> Mask = SVOp->getMask();
8354 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8357 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8359 if (NumV2Elements == 0) {
8360 // Check for being able to broadcast a single element.
8361 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8362 Mask, Subtarget, DAG))
8365 if (Subtarget->hasAVX()) {
8366 // If we have AVX, we can use VPERMILPS which will allow folding a load
8367 // into the shuffle.
8368 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8369 getV4X86ShuffleImm8ForMask(Mask, DAG));
8372 // Otherwise, use a straight shuffle of a single input vector. We pass the
8373 // input vector to both operands to simulate this with a SHUFPS.
8374 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8375 getV4X86ShuffleImm8ForMask(Mask, DAG));
8378 // Use dedicated unpack instructions for masks that match their pattern.
8379 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8380 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8381 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8382 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8384 // There are special ways we can lower some single-element blends. However, we
8385 // have custom ways we can lower more complex single-element blends below that
8386 // we defer to if both this and BLENDPS fail to match, so restrict this to
8387 // when the V2 input is targeting element 0 of the mask -- that is the fast
8389 if (NumV2Elements == 1 && Mask[0] >= 4)
8390 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8391 Mask, Subtarget, DAG))
8394 if (Subtarget->hasSSE41())
8395 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8399 // Check for whether we can use INSERTPS to perform the blend. We only use
8400 // INSERTPS when the V1 elements are already in the correct locations
8401 // because otherwise we can just always use two SHUFPS instructions which
8402 // are much smaller to encode than a SHUFPS and an INSERTPS.
8403 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8405 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8408 // When using INSERTPS we can zero any lane of the destination. Collect
8409 // the zero inputs into a mask and drop them from the lanes of V1 which
8410 // actually need to be present as inputs to the INSERTPS.
8411 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8413 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8414 bool InsertNeedsShuffle = false;
8416 for (int i = 0; i < 4; ++i)
8420 } else if (Mask[i] != i) {
8421 InsertNeedsShuffle = true;
8426 // We don't want to use INSERTPS or other insertion techniques if it will
8427 // require shuffling anyways.
8428 if (!InsertNeedsShuffle) {
8429 // If all of V1 is zeroable, replace it with undef.
8430 if ((ZMask | 1 << V2Index) == 0xF)
8431 V1 = DAG.getUNDEF(MVT::v4f32);
8433 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8434 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8436 // Insert the V2 element into the desired position.
8437 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8438 DAG.getConstant(InsertPSMask, MVT::i8));
8442 // Otherwise fall back to a SHUFPS lowering strategy.
8443 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8446 /// \brief Lower 4-lane i32 vector shuffles.
8448 /// We try to handle these with integer-domain shuffles where we can, but for
8449 /// blends we use the floating point domain blend instructions.
8450 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8451 const X86Subtarget *Subtarget,
8452 SelectionDAG &DAG) {
8454 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8455 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8456 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8457 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8458 ArrayRef<int> Mask = SVOp->getMask();
8459 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8461 // Whenever we can lower this as a zext, that instruction is strictly faster
8462 // than any alternative. It also allows us to fold memory operands into the
8463 // shuffle in many cases.
8464 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8465 Mask, Subtarget, DAG))
8469 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8471 if (NumV2Elements == 0) {
8472 // Check for being able to broadcast a single element.
8473 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8474 Mask, Subtarget, DAG))
8477 // Straight shuffle of a single input vector. For everything from SSE2
8478 // onward this has a single fast instruction with no scary immediates.
8479 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8480 // but we aren't actually going to use the UNPCK instruction because doing
8481 // so prevents folding a load into this instruction or making a copy.
8482 const int UnpackLoMask[] = {0, 0, 1, 1};
8483 const int UnpackHiMask[] = {2, 2, 3, 3};
8484 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8485 Mask = UnpackLoMask;
8486 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8487 Mask = UnpackHiMask;
8489 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8490 getV4X86ShuffleImm8ForMask(Mask, DAG));
8493 // There are special ways we can lower some single-element blends.
8494 if (NumV2Elements == 1)
8495 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8496 Mask, Subtarget, DAG))
8499 // Use dedicated unpack instructions for masks that match their pattern.
8500 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8501 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8502 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8503 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8505 if (Subtarget->hasSSE41())
8506 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8510 // Try to use byte shift instructions.
8511 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8512 DL, MVT::v4i32, V1, V2, Mask, DAG))
8515 // Try to use byte rotation instructions.
8516 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8517 if (Subtarget->hasSSSE3())
8518 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8519 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8522 // We implement this with SHUFPS because it can blend from two vectors.
8523 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8524 // up the inputs, bypassing domain shift penalties that we would encur if we
8525 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8527 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8528 DAG.getVectorShuffle(
8530 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8531 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8534 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8535 /// shuffle lowering, and the most complex part.
8537 /// The lowering strategy is to try to form pairs of input lanes which are
8538 /// targeted at the same half of the final vector, and then use a dword shuffle
8539 /// to place them onto the right half, and finally unpack the paired lanes into
8540 /// their final position.
8542 /// The exact breakdown of how to form these dword pairs and align them on the
8543 /// correct sides is really tricky. See the comments within the function for
8544 /// more of the details.
8545 static SDValue lowerV8I16SingleInputVectorShuffle(
8546 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8547 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8548 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8549 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8550 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8552 SmallVector<int, 4> LoInputs;
8553 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8554 [](int M) { return M >= 0; });
8555 std::sort(LoInputs.begin(), LoInputs.end());
8556 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8557 SmallVector<int, 4> HiInputs;
8558 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8559 [](int M) { return M >= 0; });
8560 std::sort(HiInputs.begin(), HiInputs.end());
8561 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8563 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8564 int NumHToL = LoInputs.size() - NumLToL;
8566 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8567 int NumHToH = HiInputs.size() - NumLToH;
8568 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8569 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8570 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8571 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8573 // Check for being able to broadcast a single element.
8574 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8575 Mask, Subtarget, DAG))
8578 // Use dedicated unpack instructions for masks that match their pattern.
8579 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8580 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8581 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8582 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8584 // Try to use byte shift instructions.
8585 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8586 DL, MVT::v8i16, V, V, Mask, DAG))
8589 // Try to use byte rotation instructions.
8590 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8591 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8594 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8595 // such inputs we can swap two of the dwords across the half mark and end up
8596 // with <=2 inputs to each half in each half. Once there, we can fall through
8597 // to the generic code below. For example:
8599 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8600 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8602 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8603 // and an existing 2-into-2 on the other half. In this case we may have to
8604 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8605 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8606 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8607 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8608 // half than the one we target for fixing) will be fixed when we re-enter this
8609 // path. We will also combine away any sequence of PSHUFD instructions that
8610 // result into a single instruction. Here is an example of the tricky case:
8612 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8613 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8615 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8617 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8618 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8620 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8621 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8623 // The result is fine to be handled by the generic logic.
8624 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8625 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8626 int AOffset, int BOffset) {
8627 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8628 "Must call this with A having 3 or 1 inputs from the A half.");
8629 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8630 "Must call this with B having 1 or 3 inputs from the B half.");
8631 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8632 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8634 // Compute the index of dword with only one word among the three inputs in
8635 // a half by taking the sum of the half with three inputs and subtracting
8636 // the sum of the actual three inputs. The difference is the remaining
8639 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8640 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8641 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8642 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8643 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8644 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8645 int TripleNonInputIdx =
8646 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8647 TripleDWord = TripleNonInputIdx / 2;
8649 // We use xor with one to compute the adjacent DWord to whichever one the
8651 OneInputDWord = (OneInput / 2) ^ 1;
8653 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8654 // and BToA inputs. If there is also such a problem with the BToB and AToB
8655 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8656 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8657 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8658 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8659 // Compute how many inputs will be flipped by swapping these DWords. We
8661 // to balance this to ensure we don't form a 3-1 shuffle in the other
8663 int NumFlippedAToBInputs =
8664 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8665 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8666 int NumFlippedBToBInputs =
8667 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8668 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8669 if ((NumFlippedAToBInputs == 1 &&
8670 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8671 (NumFlippedBToBInputs == 1 &&
8672 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8673 // We choose whether to fix the A half or B half based on whether that
8674 // half has zero flipped inputs. At zero, we may not be able to fix it
8675 // with that half. We also bias towards fixing the B half because that
8676 // will more commonly be the high half, and we have to bias one way.
8677 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8678 ArrayRef<int> Inputs) {
8679 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8680 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8681 PinnedIdx ^ 1) != Inputs.end();
8682 // Determine whether the free index is in the flipped dword or the
8683 // unflipped dword based on where the pinned index is. We use this bit
8684 // in an xor to conditionally select the adjacent dword.
8685 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8686 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8687 FixFreeIdx) != Inputs.end();
8688 if (IsFixIdxInput == IsFixFreeIdxInput)
8690 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8691 FixFreeIdx) != Inputs.end();
8692 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8693 "We need to be changing the number of flipped inputs!");
8694 int PSHUFHalfMask[] = {0, 1, 2, 3};
8695 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8696 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8698 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8701 if (M != -1 && M == FixIdx)
8703 else if (M != -1 && M == FixFreeIdx)
8706 if (NumFlippedBToBInputs != 0) {
8708 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8709 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8711 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8713 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8714 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8719 int PSHUFDMask[] = {0, 1, 2, 3};
8720 PSHUFDMask[ADWord] = BDWord;
8721 PSHUFDMask[BDWord] = ADWord;
8722 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8723 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8724 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8725 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8727 // Adjust the mask to match the new locations of A and B.
8729 if (M != -1 && M/2 == ADWord)
8730 M = 2 * BDWord + M % 2;
8731 else if (M != -1 && M/2 == BDWord)
8732 M = 2 * ADWord + M % 2;
8734 // Recurse back into this routine to re-compute state now that this isn't
8735 // a 3 and 1 problem.
8736 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8739 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8740 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8741 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8742 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8744 // At this point there are at most two inputs to the low and high halves from
8745 // each half. That means the inputs can always be grouped into dwords and
8746 // those dwords can then be moved to the correct half with a dword shuffle.
8747 // We use at most one low and one high word shuffle to collect these paired
8748 // inputs into dwords, and finally a dword shuffle to place them.
8749 int PSHUFLMask[4] = {-1, -1, -1, -1};
8750 int PSHUFHMask[4] = {-1, -1, -1, -1};
8751 int PSHUFDMask[4] = {-1, -1, -1, -1};
8753 // First fix the masks for all the inputs that are staying in their
8754 // original halves. This will then dictate the targets of the cross-half
8756 auto fixInPlaceInputs =
8757 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8758 MutableArrayRef<int> SourceHalfMask,
8759 MutableArrayRef<int> HalfMask, int HalfOffset) {
8760 if (InPlaceInputs.empty())
8762 if (InPlaceInputs.size() == 1) {
8763 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8764 InPlaceInputs[0] - HalfOffset;
8765 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8768 if (IncomingInputs.empty()) {
8769 // Just fix all of the in place inputs.
8770 for (int Input : InPlaceInputs) {
8771 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8772 PSHUFDMask[Input / 2] = Input / 2;
8777 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8778 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8779 InPlaceInputs[0] - HalfOffset;
8780 // Put the second input next to the first so that they are packed into
8781 // a dword. We find the adjacent index by toggling the low bit.
8782 int AdjIndex = InPlaceInputs[0] ^ 1;
8783 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8784 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8785 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8787 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8788 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8790 // Now gather the cross-half inputs and place them into a free dword of
8791 // their target half.
8792 // FIXME: This operation could almost certainly be simplified dramatically to
8793 // look more like the 3-1 fixing operation.
8794 auto moveInputsToRightHalf = [&PSHUFDMask](
8795 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8796 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8797 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8799 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8800 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8802 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8804 int LowWord = Word & ~1;
8805 int HighWord = Word | 1;
8806 return isWordClobbered(SourceHalfMask, LowWord) ||
8807 isWordClobbered(SourceHalfMask, HighWord);
8810 if (IncomingInputs.empty())
8813 if (ExistingInputs.empty()) {
8814 // Map any dwords with inputs from them into the right half.
8815 for (int Input : IncomingInputs) {
8816 // If the source half mask maps over the inputs, turn those into
8817 // swaps and use the swapped lane.
8818 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8819 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8820 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8821 Input - SourceOffset;
8822 // We have to swap the uses in our half mask in one sweep.
8823 for (int &M : HalfMask)
8824 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8826 else if (M == Input)
8827 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8829 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8830 Input - SourceOffset &&
8831 "Previous placement doesn't match!");
8833 // Note that this correctly re-maps both when we do a swap and when
8834 // we observe the other side of the swap above. We rely on that to
8835 // avoid swapping the members of the input list directly.
8836 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8839 // Map the input's dword into the correct half.
8840 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8841 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8843 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8845 "Previous placement doesn't match!");
8848 // And just directly shift any other-half mask elements to be same-half
8849 // as we will have mirrored the dword containing the element into the
8850 // same position within that half.
8851 for (int &M : HalfMask)
8852 if (M >= SourceOffset && M < SourceOffset + 4) {
8853 M = M - SourceOffset + DestOffset;
8854 assert(M >= 0 && "This should never wrap below zero!");
8859 // Ensure we have the input in a viable dword of its current half. This
8860 // is particularly tricky because the original position may be clobbered
8861 // by inputs being moved and *staying* in that half.
8862 if (IncomingInputs.size() == 1) {
8863 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8864 int InputFixed = std::find(std::begin(SourceHalfMask),
8865 std::end(SourceHalfMask), -1) -
8866 std::begin(SourceHalfMask) + SourceOffset;
8867 SourceHalfMask[InputFixed - SourceOffset] =
8868 IncomingInputs[0] - SourceOffset;
8869 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8871 IncomingInputs[0] = InputFixed;
8873 } else if (IncomingInputs.size() == 2) {
8874 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8875 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8876 // We have two non-adjacent or clobbered inputs we need to extract from
8877 // the source half. To do this, we need to map them into some adjacent
8878 // dword slot in the source mask.
8879 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8880 IncomingInputs[1] - SourceOffset};
8882 // If there is a free slot in the source half mask adjacent to one of
8883 // the inputs, place the other input in it. We use (Index XOR 1) to
8884 // compute an adjacent index.
8885 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8886 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8887 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8888 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8889 InputsFixed[1] = InputsFixed[0] ^ 1;
8890 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8891 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8892 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8893 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8894 InputsFixed[0] = InputsFixed[1] ^ 1;
8895 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8896 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8897 // The two inputs are in the same DWord but it is clobbered and the
8898 // adjacent DWord isn't used at all. Move both inputs to the free
8900 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8901 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8902 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8903 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8905 // The only way we hit this point is if there is no clobbering
8906 // (because there are no off-half inputs to this half) and there is no
8907 // free slot adjacent to one of the inputs. In this case, we have to
8908 // swap an input with a non-input.
8909 for (int i = 0; i < 4; ++i)
8910 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8911 "We can't handle any clobbers here!");
8912 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8913 "Cannot have adjacent inputs here!");
8915 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8916 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8918 // We also have to update the final source mask in this case because
8919 // it may need to undo the above swap.
8920 for (int &M : FinalSourceHalfMask)
8921 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8922 M = InputsFixed[1] + SourceOffset;
8923 else if (M == InputsFixed[1] + SourceOffset)
8924 M = (InputsFixed[0] ^ 1) + SourceOffset;
8926 InputsFixed[1] = InputsFixed[0] ^ 1;
8929 // Point everything at the fixed inputs.
8930 for (int &M : HalfMask)
8931 if (M == IncomingInputs[0])
8932 M = InputsFixed[0] + SourceOffset;
8933 else if (M == IncomingInputs[1])
8934 M = InputsFixed[1] + SourceOffset;
8936 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8937 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8940 llvm_unreachable("Unhandled input size!");
8943 // Now hoist the DWord down to the right half.
8944 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8945 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8946 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8947 for (int &M : HalfMask)
8948 for (int Input : IncomingInputs)
8950 M = FreeDWord * 2 + Input % 2;
8952 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8953 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8954 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8955 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8957 // Now enact all the shuffles we've computed to move the inputs into their
8959 if (!isNoopShuffleMask(PSHUFLMask))
8960 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8961 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8962 if (!isNoopShuffleMask(PSHUFHMask))
8963 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8964 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8965 if (!isNoopShuffleMask(PSHUFDMask))
8966 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8967 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8968 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8969 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8971 // At this point, each half should contain all its inputs, and we can then
8972 // just shuffle them into their final position.
8973 assert(std::count_if(LoMask.begin(), LoMask.end(),
8974 [](int M) { return M >= 4; }) == 0 &&
8975 "Failed to lift all the high half inputs to the low mask!");
8976 assert(std::count_if(HiMask.begin(), HiMask.end(),
8977 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8978 "Failed to lift all the low half inputs to the high mask!");
8980 // Do a half shuffle for the low mask.
8981 if (!isNoopShuffleMask(LoMask))
8982 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8983 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8985 // Do a half shuffle with the high mask after shifting its values down.
8986 for (int &M : HiMask)
8989 if (!isNoopShuffleMask(HiMask))
8990 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8991 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8996 /// \brief Detect whether the mask pattern should be lowered through
8999 /// This essentially tests whether viewing the mask as an interleaving of two
9000 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9001 /// lowering it through interleaving is a significantly better strategy.
9002 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9003 int NumEvenInputs[2] = {0, 0};
9004 int NumOddInputs[2] = {0, 0};
9005 int NumLoInputs[2] = {0, 0};
9006 int NumHiInputs[2] = {0, 0};
9007 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9011 int InputIdx = Mask[i] >= Size;
9014 ++NumLoInputs[InputIdx];
9016 ++NumHiInputs[InputIdx];
9019 ++NumEvenInputs[InputIdx];
9021 ++NumOddInputs[InputIdx];
9024 // The minimum number of cross-input results for both the interleaved and
9025 // split cases. If interleaving results in fewer cross-input results, return
9027 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9028 NumEvenInputs[0] + NumOddInputs[1]);
9029 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9030 NumLoInputs[0] + NumHiInputs[1]);
9031 return InterleavedCrosses < SplitCrosses;
9034 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9036 /// This strategy only works when the inputs from each vector fit into a single
9037 /// half of that vector, and generally there are not so many inputs as to leave
9038 /// the in-place shuffles required highly constrained (and thus expensive). It
9039 /// shifts all the inputs into a single side of both input vectors and then
9040 /// uses an unpack to interleave these inputs in a single vector. At that
9041 /// point, we will fall back on the generic single input shuffle lowering.
9042 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9044 MutableArrayRef<int> Mask,
9045 const X86Subtarget *Subtarget,
9046 SelectionDAG &DAG) {
9047 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9048 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9049 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9050 for (int i = 0; i < 8; ++i)
9051 if (Mask[i] >= 0 && Mask[i] < 4)
9052 LoV1Inputs.push_back(i);
9053 else if (Mask[i] >= 4 && Mask[i] < 8)
9054 HiV1Inputs.push_back(i);
9055 else if (Mask[i] >= 8 && Mask[i] < 12)
9056 LoV2Inputs.push_back(i);
9057 else if (Mask[i] >= 12)
9058 HiV2Inputs.push_back(i);
9060 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9061 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9064 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9065 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9066 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9068 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9069 HiV1Inputs.size() + HiV2Inputs.size();
9071 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9072 ArrayRef<int> HiInputs, bool MoveToLo,
9074 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9075 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9076 if (BadInputs.empty())
9079 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9080 int MoveOffset = MoveToLo ? 0 : 4;
9082 if (GoodInputs.empty()) {
9083 for (int BadInput : BadInputs) {
9084 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9085 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9088 if (GoodInputs.size() == 2) {
9089 // If the low inputs are spread across two dwords, pack them into
9091 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9092 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9093 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9094 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9096 // Otherwise pin the good inputs.
9097 for (int GoodInput : GoodInputs)
9098 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9101 if (BadInputs.size() == 2) {
9102 // If we have two bad inputs then there may be either one or two good
9103 // inputs fixed in place. Find a fixed input, and then find the *other*
9104 // two adjacent indices by using modular arithmetic.
9106 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9107 [](int M) { return M >= 0; }) -
9108 std::begin(MoveMask);
9110 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9111 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9112 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9113 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9114 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9115 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9116 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9118 assert(BadInputs.size() == 1 && "All sizes handled");
9119 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9120 std::end(MoveMask), -1) -
9121 std::begin(MoveMask);
9122 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9123 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9127 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9130 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9132 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9135 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9136 // cross-half traffic in the final shuffle.
9138 // Munge the mask to be a single-input mask after the unpack merges the
9142 M = 2 * (M % 4) + (M / 8);
9144 return DAG.getVectorShuffle(
9145 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9146 DL, MVT::v8i16, V1, V2),
9147 DAG.getUNDEF(MVT::v8i16), Mask);
9150 /// \brief Generic lowering of 8-lane i16 shuffles.
9152 /// This handles both single-input shuffles and combined shuffle/blends with
9153 /// two inputs. The single input shuffles are immediately delegated to
9154 /// a dedicated lowering routine.
9156 /// The blends are lowered in one of three fundamental ways. If there are few
9157 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9158 /// of the input is significantly cheaper when lowered as an interleaving of
9159 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9160 /// halves of the inputs separately (making them have relatively few inputs)
9161 /// and then concatenate them.
9162 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9163 const X86Subtarget *Subtarget,
9164 SelectionDAG &DAG) {
9166 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9167 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9168 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9169 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9170 ArrayRef<int> OrigMask = SVOp->getMask();
9171 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9172 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9173 MutableArrayRef<int> Mask(MaskStorage);
9175 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9177 // Whenever we can lower this as a zext, that instruction is strictly faster
9178 // than any alternative.
9179 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9180 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9183 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9184 auto isV2 = [](int M) { return M >= 8; };
9186 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9187 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9189 if (NumV2Inputs == 0)
9190 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9192 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9193 "to be V1-input shuffles.");
9195 // There are special ways we can lower some single-element blends.
9196 if (NumV2Inputs == 1)
9197 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9198 Mask, Subtarget, DAG))
9201 // Use dedicated unpack instructions for masks that match their pattern.
9202 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9203 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9204 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9205 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9207 if (Subtarget->hasSSE41())
9208 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9212 // Try to use byte shift instructions.
9213 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9214 DL, MVT::v8i16, V1, V2, Mask, DAG))
9217 // Try to use byte rotation instructions.
9218 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9219 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9222 if (NumV1Inputs + NumV2Inputs <= 4)
9223 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9225 // Check whether an interleaving lowering is likely to be more efficient.
9226 // This isn't perfect but it is a strong heuristic that tends to work well on
9227 // the kinds of shuffles that show up in practice.
9229 // FIXME: Handle 1x, 2x, and 4x interleaving.
9230 if (shouldLowerAsInterleaving(Mask)) {
9231 // FIXME: Figure out whether we should pack these into the low or high
9234 int EMask[8], OMask[8];
9235 for (int i = 0; i < 4; ++i) {
9236 EMask[i] = Mask[2*i];
9237 OMask[i] = Mask[2*i + 1];
9242 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9243 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9245 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9248 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9249 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9251 for (int i = 0; i < 4; ++i) {
9252 LoBlendMask[i] = Mask[i];
9253 HiBlendMask[i] = Mask[i + 4];
9256 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9257 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9258 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9259 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9261 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9262 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9265 /// \brief Check whether a compaction lowering can be done by dropping even
9266 /// elements and compute how many times even elements must be dropped.
9268 /// This handles shuffles which take every Nth element where N is a power of
9269 /// two. Example shuffle masks:
9271 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9272 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9273 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9274 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9275 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9276 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9278 /// Any of these lanes can of course be undef.
9280 /// This routine only supports N <= 3.
9281 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9284 /// \returns N above, or the number of times even elements must be dropped if
9285 /// there is such a number. Otherwise returns zero.
9286 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9287 // Figure out whether we're looping over two inputs or just one.
9288 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9290 // The modulus for the shuffle vector entries is based on whether this is
9291 // a single input or not.
9292 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9293 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9294 "We should only be called with masks with a power-of-2 size!");
9296 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9298 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9299 // and 2^3 simultaneously. This is because we may have ambiguity with
9300 // partially undef inputs.
9301 bool ViableForN[3] = {true, true, true};
9303 for (int i = 0, e = Mask.size(); i < e; ++i) {
9304 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9309 bool IsAnyViable = false;
9310 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9311 if (ViableForN[j]) {
9314 // The shuffle mask must be equal to (i * 2^N) % M.
9315 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9318 ViableForN[j] = false;
9320 // Early exit if we exhaust the possible powers of two.
9325 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9329 // Return 0 as there is no viable power of two.
9333 /// \brief Generic lowering of v16i8 shuffles.
9335 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9336 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9337 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9338 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9340 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9341 const X86Subtarget *Subtarget,
9342 SelectionDAG &DAG) {
9344 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9345 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9346 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9347 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9348 ArrayRef<int> OrigMask = SVOp->getMask();
9349 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9351 // Try to use byte shift instructions.
9352 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9353 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9356 // Try to use byte rotation instructions.
9357 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9358 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9361 // Try to use a zext lowering.
9362 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9363 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9366 int MaskStorage[16] = {
9367 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9368 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9369 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9370 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9371 MutableArrayRef<int> Mask(MaskStorage);
9372 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9373 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9376 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9378 // For single-input shuffles, there are some nicer lowering tricks we can use.
9379 if (NumV2Elements == 0) {
9380 // Check for being able to broadcast a single element.
9381 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9382 Mask, Subtarget, DAG))
9385 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9386 // Notably, this handles splat and partial-splat shuffles more efficiently.
9387 // However, it only makes sense if the pre-duplication shuffle simplifies
9388 // things significantly. Currently, this means we need to be able to
9389 // express the pre-duplication shuffle as an i16 shuffle.
9391 // FIXME: We should check for other patterns which can be widened into an
9392 // i16 shuffle as well.
9393 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9394 for (int i = 0; i < 16; i += 2)
9395 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9400 auto tryToWidenViaDuplication = [&]() -> SDValue {
9401 if (!canWidenViaDuplication(Mask))
9403 SmallVector<int, 4> LoInputs;
9404 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9405 [](int M) { return M >= 0 && M < 8; });
9406 std::sort(LoInputs.begin(), LoInputs.end());
9407 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9409 SmallVector<int, 4> HiInputs;
9410 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9411 [](int M) { return M >= 8; });
9412 std::sort(HiInputs.begin(), HiInputs.end());
9413 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9416 bool TargetLo = LoInputs.size() >= HiInputs.size();
9417 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9418 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9420 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9421 SmallDenseMap<int, int, 8> LaneMap;
9422 for (int I : InPlaceInputs) {
9423 PreDupI16Shuffle[I/2] = I/2;
9426 int j = TargetLo ? 0 : 4, je = j + 4;
9427 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9428 // Check if j is already a shuffle of this input. This happens when
9429 // there are two adjacent bytes after we move the low one.
9430 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9431 // If we haven't yet mapped the input, search for a slot into which
9433 while (j < je && PreDupI16Shuffle[j] != -1)
9437 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9440 // Map this input with the i16 shuffle.
9441 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9444 // Update the lane map based on the mapping we ended up with.
9445 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9448 ISD::BITCAST, DL, MVT::v16i8,
9449 DAG.getVectorShuffle(MVT::v8i16, DL,
9450 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9451 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9453 // Unpack the bytes to form the i16s that will be shuffled into place.
9454 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9455 MVT::v16i8, V1, V1);
9457 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9458 for (int i = 0; i < 16; ++i)
9459 if (Mask[i] != -1) {
9460 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9461 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9462 if (PostDupI16Shuffle[i / 2] == -1)
9463 PostDupI16Shuffle[i / 2] = MappedMask;
9465 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9466 "Conflicting entrties in the original shuffle!");
9469 ISD::BITCAST, DL, MVT::v16i8,
9470 DAG.getVectorShuffle(MVT::v8i16, DL,
9471 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9472 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9474 if (SDValue V = tryToWidenViaDuplication())
9478 // Check whether an interleaving lowering is likely to be more efficient.
9479 // This isn't perfect but it is a strong heuristic that tends to work well on
9480 // the kinds of shuffles that show up in practice.
9482 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9483 if (shouldLowerAsInterleaving(Mask)) {
9484 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9485 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9487 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9488 return (M >= 8 && M < 16) || M >= 24;
9490 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9491 -1, -1, -1, -1, -1, -1, -1, -1};
9492 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9493 -1, -1, -1, -1, -1, -1, -1, -1};
9494 bool UnpackLo = NumLoHalf >= NumHiHalf;
9495 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9496 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9497 for (int i = 0; i < 8; ++i) {
9498 TargetEMask[i] = Mask[2 * i];
9499 TargetOMask[i] = Mask[2 * i + 1];
9502 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9503 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9505 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9506 MVT::v16i8, Evens, Odds);
9509 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9510 // with PSHUFB. It is important to do this before we attempt to generate any
9511 // blends but after all of the single-input lowerings. If the single input
9512 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9513 // want to preserve that and we can DAG combine any longer sequences into
9514 // a PSHUFB in the end. But once we start blending from multiple inputs,
9515 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9516 // and there are *very* few patterns that would actually be faster than the
9517 // PSHUFB approach because of its ability to zero lanes.
9519 // FIXME: The only exceptions to the above are blends which are exact
9520 // interleavings with direct instructions supporting them. We currently don't
9521 // handle those well here.
9522 if (Subtarget->hasSSSE3()) {
9525 for (int i = 0; i < 16; ++i)
9526 if (Mask[i] == -1) {
9527 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9529 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9531 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9533 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9534 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9535 if (isSingleInputShuffleMask(Mask))
9536 return V1; // Single inputs are easy.
9538 // Otherwise, blend the two.
9539 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9540 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9541 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9544 // There are special ways we can lower some single-element blends.
9545 if (NumV2Elements == 1)
9546 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9547 Mask, Subtarget, DAG))
9550 // Check whether a compaction lowering can be done. This handles shuffles
9551 // which take every Nth element for some even N. See the helper function for
9554 // We special case these as they can be particularly efficiently handled with
9555 // the PACKUSB instruction on x86 and they show up in common patterns of
9556 // rearranging bytes to truncate wide elements.
9557 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9558 // NumEvenDrops is the power of two stride of the elements. Another way of
9559 // thinking about it is that we need to drop the even elements this many
9560 // times to get the original input.
9561 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9563 // First we need to zero all the dropped bytes.
9564 assert(NumEvenDrops <= 3 &&
9565 "No support for dropping even elements more than 3 times.");
9566 // We use the mask type to pick which bytes are preserved based on how many
9567 // elements are dropped.
9568 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9569 SDValue ByteClearMask =
9570 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9571 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9572 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9574 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9576 // Now pack things back together.
9577 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9578 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9579 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9580 for (int i = 1; i < NumEvenDrops; ++i) {
9581 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9582 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9588 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9589 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9590 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9591 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9593 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9594 MutableArrayRef<int> V1HalfBlendMask,
9595 MutableArrayRef<int> V2HalfBlendMask) {
9596 for (int i = 0; i < 8; ++i)
9597 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9598 V1HalfBlendMask[i] = HalfMask[i];
9600 } else if (HalfMask[i] >= 16) {
9601 V2HalfBlendMask[i] = HalfMask[i] - 16;
9602 HalfMask[i] = i + 8;
9605 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9606 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9608 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9610 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9611 MutableArrayRef<int> HiBlendMask) {
9613 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9614 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9616 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9617 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9618 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9619 [](int M) { return M >= 0 && M % 2 == 1; })) {
9620 // Use a mask to drop the high bytes.
9621 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9622 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9623 DAG.getConstant(0x00FF, MVT::v8i16));
9625 // This will be a single vector shuffle instead of a blend so nuke V2.
9626 V2 = DAG.getUNDEF(MVT::v8i16);
9628 // Squash the masks to point directly into V1.
9629 for (int &M : LoBlendMask)
9632 for (int &M : HiBlendMask)
9636 // Otherwise just unpack the low half of V into V1 and the high half into
9637 // V2 so that we can blend them as i16s.
9638 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9639 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9640 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9641 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9644 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9645 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9646 return std::make_pair(BlendedLo, BlendedHi);
9648 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9649 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9650 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9652 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9653 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9655 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9658 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9660 /// This routine breaks down the specific type of 128-bit shuffle and
9661 /// dispatches to the lowering routines accordingly.
9662 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9663 MVT VT, const X86Subtarget *Subtarget,
9664 SelectionDAG &DAG) {
9665 switch (VT.SimpleTy) {
9667 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9669 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9671 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9673 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9675 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9677 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9680 llvm_unreachable("Unimplemented!");
9684 /// \brief Helper function to test whether a shuffle mask could be
9685 /// simplified by widening the elements being shuffled.
9687 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9688 /// leaves it in an unspecified state.
9690 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9691 /// shuffle masks. The latter have the special property of a '-2' representing
9692 /// a zero-ed lane of a vector.
9693 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9694 SmallVectorImpl<int> &WidenedMask) {
9695 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9696 // If both elements are undef, its trivial.
9697 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9698 WidenedMask.push_back(SM_SentinelUndef);
9702 // Check for an undef mask and a mask value properly aligned to fit with
9703 // a pair of values. If we find such a case, use the non-undef mask's value.
9704 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9705 WidenedMask.push_back(Mask[i + 1] / 2);
9708 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9709 WidenedMask.push_back(Mask[i] / 2);
9713 // When zeroing, we need to spread the zeroing across both lanes to widen.
9714 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9715 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9716 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9717 WidenedMask.push_back(SM_SentinelZero);
9723 // Finally check if the two mask values are adjacent and aligned with
9725 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9726 WidenedMask.push_back(Mask[i] / 2);
9730 // Otherwise we can't safely widen the elements used in this shuffle.
9733 assert(WidenedMask.size() == Mask.size() / 2 &&
9734 "Incorrect size of mask after widening the elements!");
9739 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9741 /// This routine just extracts two subvectors, shuffles them independently, and
9742 /// then concatenates them back together. This should work effectively with all
9743 /// AVX vector shuffle types.
9744 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9745 SDValue V2, ArrayRef<int> Mask,
9746 SelectionDAG &DAG) {
9747 assert(VT.getSizeInBits() >= 256 &&
9748 "Only for 256-bit or wider vector shuffles!");
9749 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9750 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9752 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9753 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9755 int NumElements = VT.getVectorNumElements();
9756 int SplitNumElements = NumElements / 2;
9757 MVT ScalarVT = VT.getScalarType();
9758 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9760 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9761 DAG.getIntPtrConstant(0));
9762 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9763 DAG.getIntPtrConstant(SplitNumElements));
9764 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9765 DAG.getIntPtrConstant(0));
9766 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9767 DAG.getIntPtrConstant(SplitNumElements));
9769 // Now create two 4-way blends of these half-width vectors.
9770 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9771 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9772 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9773 for (int i = 0; i < SplitNumElements; ++i) {
9774 int M = HalfMask[i];
9775 if (M >= NumElements) {
9776 if (M >= NumElements + SplitNumElements)
9780 V2BlendMask.push_back(M - NumElements);
9781 V1BlendMask.push_back(-1);
9782 BlendMask.push_back(SplitNumElements + i);
9783 } else if (M >= 0) {
9784 if (M >= SplitNumElements)
9788 V2BlendMask.push_back(-1);
9789 V1BlendMask.push_back(M);
9790 BlendMask.push_back(i);
9792 V2BlendMask.push_back(-1);
9793 V1BlendMask.push_back(-1);
9794 BlendMask.push_back(-1);
9798 // Because the lowering happens after all combining takes place, we need to
9799 // manually combine these blend masks as much as possible so that we create
9800 // a minimal number of high-level vector shuffle nodes.
9802 // First try just blending the halves of V1 or V2.
9803 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9804 return DAG.getUNDEF(SplitVT);
9805 if (!UseLoV2 && !UseHiV2)
9806 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9807 if (!UseLoV1 && !UseHiV1)
9808 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9810 SDValue V1Blend, V2Blend;
9811 if (UseLoV1 && UseHiV1) {
9813 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9815 // We only use half of V1 so map the usage down into the final blend mask.
9816 V1Blend = UseLoV1 ? LoV1 : HiV1;
9817 for (int i = 0; i < SplitNumElements; ++i)
9818 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9819 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9821 if (UseLoV2 && UseHiV2) {
9823 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9825 // We only use half of V2 so map the usage down into the final blend mask.
9826 V2Blend = UseLoV2 ? LoV2 : HiV2;
9827 for (int i = 0; i < SplitNumElements; ++i)
9828 if (BlendMask[i] >= SplitNumElements)
9829 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9831 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9833 SDValue Lo = HalfBlend(LoMask);
9834 SDValue Hi = HalfBlend(HiMask);
9835 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9838 /// \brief Either split a vector in halves or decompose the shuffles and the
9841 /// This is provided as a good fallback for many lowerings of non-single-input
9842 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9843 /// between splitting the shuffle into 128-bit components and stitching those
9844 /// back together vs. extracting the single-input shuffles and blending those
9846 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9847 SDValue V2, ArrayRef<int> Mask,
9848 SelectionDAG &DAG) {
9849 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9850 "lower single-input shuffles as it "
9851 "could then recurse on itself.");
9852 int Size = Mask.size();
9854 // If this can be modeled as a broadcast of two elements followed by a blend,
9855 // prefer that lowering. This is especially important because broadcasts can
9856 // often fold with memory operands.
9857 auto DoBothBroadcast = [&] {
9858 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9861 if (V2BroadcastIdx == -1)
9862 V2BroadcastIdx = M - Size;
9863 else if (M - Size != V2BroadcastIdx)
9865 } else if (M >= 0) {
9866 if (V1BroadcastIdx == -1)
9868 else if (M != V1BroadcastIdx)
9873 if (DoBothBroadcast())
9874 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9877 // If the inputs all stem from a single 128-bit lane of each input, then we
9878 // split them rather than blending because the split will decompose to
9879 // unusually few instructions.
9880 int LaneCount = VT.getSizeInBits() / 128;
9881 int LaneSize = Size / LaneCount;
9882 SmallBitVector LaneInputs[2];
9883 LaneInputs[0].resize(LaneCount, false);
9884 LaneInputs[1].resize(LaneCount, false);
9885 for (int i = 0; i < Size; ++i)
9887 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9888 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9889 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9891 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9892 // that the decomposed single-input shuffles don't end up here.
9893 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9896 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9897 /// a permutation and blend of those lanes.
9899 /// This essentially blends the out-of-lane inputs to each lane into the lane
9900 /// from a permuted copy of the vector. This lowering strategy results in four
9901 /// instructions in the worst case for a single-input cross lane shuffle which
9902 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9903 /// of. Special cases for each particular shuffle pattern should be handled
9904 /// prior to trying this lowering.
9905 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9906 SDValue V1, SDValue V2,
9908 SelectionDAG &DAG) {
9909 // FIXME: This should probably be generalized for 512-bit vectors as well.
9910 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9911 int LaneSize = Mask.size() / 2;
9913 // If there are only inputs from one 128-bit lane, splitting will in fact be
9914 // less expensive. The flags track wether the given lane contains an element
9915 // that crosses to another lane.
9916 bool LaneCrossing[2] = {false, false};
9917 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9918 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9919 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9920 if (!LaneCrossing[0] || !LaneCrossing[1])
9921 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9923 if (isSingleInputShuffleMask(Mask)) {
9924 SmallVector<int, 32> FlippedBlendMask;
9925 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9926 FlippedBlendMask.push_back(
9927 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9929 : Mask[i] % LaneSize +
9930 (i / LaneSize) * LaneSize + Size));
9932 // Flip the vector, and blend the results which should now be in-lane. The
9933 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9934 // 5 for the high source. The value 3 selects the high half of source 2 and
9935 // the value 2 selects the low half of source 2. We only use source 2 to
9936 // allow folding it into a memory operand.
9937 unsigned PERMMask = 3 | 2 << 4;
9938 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9939 V1, DAG.getConstant(PERMMask, MVT::i8));
9940 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9943 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9944 // will be handled by the above logic and a blend of the results, much like
9945 // other patterns in AVX.
9946 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9949 /// \brief Handle lowering 2-lane 128-bit shuffles.
9950 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9951 SDValue V2, ArrayRef<int> Mask,
9952 const X86Subtarget *Subtarget,
9953 SelectionDAG &DAG) {
9954 // Blends are faster and handle all the non-lane-crossing cases.
9955 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9959 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9960 VT.getVectorNumElements() / 2);
9961 // Check for patterns which can be matched with a single insert of a 128-bit
9963 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9964 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9965 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9966 DAG.getIntPtrConstant(0));
9967 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9968 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9969 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9971 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9972 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9973 DAG.getIntPtrConstant(0));
9974 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9975 DAG.getIntPtrConstant(2));
9976 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9979 // Otherwise form a 128-bit permutation.
9980 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9981 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9982 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9983 DAG.getConstant(PermMask, MVT::i8));
9986 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9988 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9989 /// isn't available.
9990 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9991 const X86Subtarget *Subtarget,
9992 SelectionDAG &DAG) {
9994 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9995 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9996 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9997 ArrayRef<int> Mask = SVOp->getMask();
9998 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10000 SmallVector<int, 4> WidenedMask;
10001 if (canWidenShuffleElements(Mask, WidenedMask))
10002 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10005 if (isSingleInputShuffleMask(Mask)) {
10006 // Check for being able to broadcast a single element.
10007 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10008 Mask, Subtarget, DAG))
10011 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10012 // Non-half-crossing single input shuffles can be lowerid with an
10013 // interleaved permutation.
10014 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10015 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10016 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10017 DAG.getConstant(VPERMILPMask, MVT::i8));
10020 // With AVX2 we have direct support for this permutation.
10021 if (Subtarget->hasAVX2())
10022 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10023 getV4X86ShuffleImm8ForMask(Mask, DAG));
10025 // Otherwise, fall back.
10026 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10030 // X86 has dedicated unpack instructions that can handle specific blend
10031 // operations: UNPCKH and UNPCKL.
10032 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10033 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10034 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10035 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10037 // If we have a single input to the zero element, insert that into V1 if we
10038 // can do so cheaply.
10039 int NumV2Elements =
10040 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10041 if (NumV2Elements == 1 && Mask[0] >= 4)
10042 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10043 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10046 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10050 // Check if the blend happens to exactly fit that of SHUFPD.
10051 if ((Mask[0] == -1 || Mask[0] < 2) &&
10052 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10053 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10054 (Mask[3] == -1 || Mask[3] >= 6)) {
10055 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10056 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10057 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10058 DAG.getConstant(SHUFPDMask, MVT::i8));
10060 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10061 (Mask[1] == -1 || Mask[1] < 2) &&
10062 (Mask[2] == -1 || Mask[2] >= 6) &&
10063 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10064 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10065 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10066 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10067 DAG.getConstant(SHUFPDMask, MVT::i8));
10070 // If we have AVX2 then we always want to lower with a blend because an v4 we
10071 // can fully permute the elements.
10072 if (Subtarget->hasAVX2())
10073 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10076 // Otherwise fall back on generic lowering.
10077 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10080 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10082 /// This routine is only called when we have AVX2 and thus a reasonable
10083 /// instruction set for v4i64 shuffling..
10084 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10085 const X86Subtarget *Subtarget,
10086 SelectionDAG &DAG) {
10088 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10089 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10090 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10091 ArrayRef<int> Mask = SVOp->getMask();
10092 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10093 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10095 SmallVector<int, 4> WidenedMask;
10096 if (canWidenShuffleElements(Mask, WidenedMask))
10097 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10100 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10104 // Check for being able to broadcast a single element.
10105 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10106 Mask, Subtarget, DAG))
10109 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10110 // use lower latency instructions that will operate on both 128-bit lanes.
10111 SmallVector<int, 2> RepeatedMask;
10112 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10113 if (isSingleInputShuffleMask(Mask)) {
10114 int PSHUFDMask[] = {-1, -1, -1, -1};
10115 for (int i = 0; i < 2; ++i)
10116 if (RepeatedMask[i] >= 0) {
10117 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10118 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10120 return DAG.getNode(
10121 ISD::BITCAST, DL, MVT::v4i64,
10122 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10123 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10124 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10127 // Use dedicated unpack instructions for masks that match their pattern.
10128 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10129 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10130 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10131 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10134 // AVX2 provides a direct instruction for permuting a single input across
10136 if (isSingleInputShuffleMask(Mask))
10137 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10138 getV4X86ShuffleImm8ForMask(Mask, DAG));
10140 // Otherwise fall back on generic blend lowering.
10141 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10145 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10147 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10148 /// isn't available.
10149 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10150 const X86Subtarget *Subtarget,
10151 SelectionDAG &DAG) {
10153 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10154 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10155 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10156 ArrayRef<int> Mask = SVOp->getMask();
10157 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10159 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10163 // Check for being able to broadcast a single element.
10164 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10165 Mask, Subtarget, DAG))
10168 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10169 // options to efficiently lower the shuffle.
10170 SmallVector<int, 4> RepeatedMask;
10171 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10172 assert(RepeatedMask.size() == 4 &&
10173 "Repeated masks must be half the mask width!");
10174 if (isSingleInputShuffleMask(Mask))
10175 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10176 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10178 // Use dedicated unpack instructions for masks that match their pattern.
10179 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10180 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10181 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10182 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10184 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10185 // have already handled any direct blends. We also need to squash the
10186 // repeated mask into a simulated v4f32 mask.
10187 for (int i = 0; i < 4; ++i)
10188 if (RepeatedMask[i] >= 8)
10189 RepeatedMask[i] -= 4;
10190 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10193 // If we have a single input shuffle with different shuffle patterns in the
10194 // two 128-bit lanes use the variable mask to VPERMILPS.
10195 if (isSingleInputShuffleMask(Mask)) {
10196 SDValue VPermMask[8];
10197 for (int i = 0; i < 8; ++i)
10198 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10199 : DAG.getConstant(Mask[i], MVT::i32);
10200 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10201 return DAG.getNode(
10202 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10203 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10205 if (Subtarget->hasAVX2())
10206 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10207 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10208 DAG.getNode(ISD::BUILD_VECTOR, DL,
10209 MVT::v8i32, VPermMask)),
10212 // Otherwise, fall back.
10213 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10217 // If we have AVX2 then we always want to lower with a blend because at v8 we
10218 // can fully permute the elements.
10219 if (Subtarget->hasAVX2())
10220 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10223 // Otherwise fall back on generic lowering.
10224 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10227 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10229 /// This routine is only called when we have AVX2 and thus a reasonable
10230 /// instruction set for v8i32 shuffling..
10231 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10232 const X86Subtarget *Subtarget,
10233 SelectionDAG &DAG) {
10235 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10236 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10237 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10238 ArrayRef<int> Mask = SVOp->getMask();
10239 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10240 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10242 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10246 // Check for being able to broadcast a single element.
10247 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10248 Mask, Subtarget, DAG))
10251 // If the shuffle mask is repeated in each 128-bit lane we can use more
10252 // efficient instructions that mirror the shuffles across the two 128-bit
10254 SmallVector<int, 4> RepeatedMask;
10255 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10256 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10257 if (isSingleInputShuffleMask(Mask))
10258 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10259 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10261 // Use dedicated unpack instructions for masks that match their pattern.
10262 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10263 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10264 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10265 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10268 // If the shuffle patterns aren't repeated but it is a single input, directly
10269 // generate a cross-lane VPERMD instruction.
10270 if (isSingleInputShuffleMask(Mask)) {
10271 SDValue VPermMask[8];
10272 for (int i = 0; i < 8; ++i)
10273 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10274 : DAG.getConstant(Mask[i], MVT::i32);
10275 return DAG.getNode(
10276 X86ISD::VPERMV, DL, MVT::v8i32,
10277 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10280 // Otherwise fall back on generic blend lowering.
10281 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10285 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10287 /// This routine is only called when we have AVX2 and thus a reasonable
10288 /// instruction set for v16i16 shuffling..
10289 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10290 const X86Subtarget *Subtarget,
10291 SelectionDAG &DAG) {
10293 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10294 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10295 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10296 ArrayRef<int> Mask = SVOp->getMask();
10297 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10298 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10300 // Check for being able to broadcast a single element.
10301 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10302 Mask, Subtarget, DAG))
10305 // There are no generalized cross-lane shuffle operations available on i16
10307 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10308 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10311 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10315 // Use dedicated unpack instructions for masks that match their pattern.
10316 if (isShuffleEquivalent(Mask,
10317 // First 128-bit lane:
10318 0, 16, 1, 17, 2, 18, 3, 19,
10319 // Second 128-bit lane:
10320 8, 24, 9, 25, 10, 26, 11, 27))
10321 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10322 if (isShuffleEquivalent(Mask,
10323 // First 128-bit lane:
10324 4, 20, 5, 21, 6, 22, 7, 23,
10325 // Second 128-bit lane:
10326 12, 28, 13, 29, 14, 30, 15, 31))
10327 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10329 if (isSingleInputShuffleMask(Mask)) {
10330 SDValue PSHUFBMask[32];
10331 for (int i = 0; i < 16; ++i) {
10332 if (Mask[i] == -1) {
10333 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10337 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10338 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10339 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10340 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10342 return DAG.getNode(
10343 ISD::BITCAST, DL, MVT::v16i16,
10345 X86ISD::PSHUFB, DL, MVT::v32i8,
10346 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10347 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10350 // Otherwise fall back on generic lowering.
10351 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10354 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10356 /// This routine is only called when we have AVX2 and thus a reasonable
10357 /// instruction set for v32i8 shuffling..
10358 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10359 const X86Subtarget *Subtarget,
10360 SelectionDAG &DAG) {
10362 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10363 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10364 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10365 ArrayRef<int> Mask = SVOp->getMask();
10366 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10367 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10369 // Check for being able to broadcast a single element.
10370 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10371 Mask, Subtarget, DAG))
10374 // There are no generalized cross-lane shuffle operations available on i8
10376 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10377 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10380 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10384 // Use dedicated unpack instructions for masks that match their pattern.
10385 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10387 if (isShuffleEquivalent(
10389 // First 128-bit lane:
10390 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10391 // Second 128-bit lane:
10392 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10393 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10394 if (isShuffleEquivalent(
10396 // First 128-bit lane:
10397 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10398 // Second 128-bit lane:
10399 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10400 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10402 if (isSingleInputShuffleMask(Mask)) {
10403 SDValue PSHUFBMask[32];
10404 for (int i = 0; i < 32; ++i)
10407 ? DAG.getUNDEF(MVT::i8)
10408 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10410 return DAG.getNode(
10411 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10412 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10415 // Otherwise fall back on generic lowering.
10416 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10419 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10421 /// This routine either breaks down the specific type of a 256-bit x86 vector
10422 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10423 /// together based on the available instructions.
10424 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10425 MVT VT, const X86Subtarget *Subtarget,
10426 SelectionDAG &DAG) {
10428 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10429 ArrayRef<int> Mask = SVOp->getMask();
10431 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10432 // check for those subtargets here and avoid much of the subtarget querying in
10433 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10434 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10435 // floating point types there eventually, just immediately cast everything to
10436 // a float and operate entirely in that domain.
10437 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10438 int ElementBits = VT.getScalarSizeInBits();
10439 if (ElementBits < 32)
10440 // No floating point type available, decompose into 128-bit vectors.
10441 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10443 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10444 VT.getVectorNumElements());
10445 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10446 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10447 return DAG.getNode(ISD::BITCAST, DL, VT,
10448 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10451 switch (VT.SimpleTy) {
10453 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10455 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10457 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10459 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10461 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10463 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10466 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10470 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10471 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10472 const X86Subtarget *Subtarget,
10473 SelectionDAG &DAG) {
10475 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10476 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10477 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10478 ArrayRef<int> Mask = SVOp->getMask();
10479 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10481 // FIXME: Implement direct support for this type!
10482 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10485 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10486 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10487 const X86Subtarget *Subtarget,
10488 SelectionDAG &DAG) {
10490 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10491 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10492 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10493 ArrayRef<int> Mask = SVOp->getMask();
10494 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10496 // FIXME: Implement direct support for this type!
10497 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10500 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10501 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10502 const X86Subtarget *Subtarget,
10503 SelectionDAG &DAG) {
10505 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10506 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10507 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10508 ArrayRef<int> Mask = SVOp->getMask();
10509 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10511 // FIXME: Implement direct support for this type!
10512 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10515 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10516 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10517 const X86Subtarget *Subtarget,
10518 SelectionDAG &DAG) {
10520 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10521 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10522 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10523 ArrayRef<int> Mask = SVOp->getMask();
10524 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10526 // FIXME: Implement direct support for this type!
10527 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10530 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10531 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10532 const X86Subtarget *Subtarget,
10533 SelectionDAG &DAG) {
10535 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10536 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10537 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10538 ArrayRef<int> Mask = SVOp->getMask();
10539 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10540 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10542 // FIXME: Implement direct support for this type!
10543 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10546 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10547 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10548 const X86Subtarget *Subtarget,
10549 SelectionDAG &DAG) {
10551 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10552 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10553 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10554 ArrayRef<int> Mask = SVOp->getMask();
10555 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10556 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10558 // FIXME: Implement direct support for this type!
10559 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10562 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10564 /// This routine either breaks down the specific type of a 512-bit x86 vector
10565 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10566 /// together based on the available instructions.
10567 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10568 MVT VT, const X86Subtarget *Subtarget,
10569 SelectionDAG &DAG) {
10571 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10572 ArrayRef<int> Mask = SVOp->getMask();
10573 assert(Subtarget->hasAVX512() &&
10574 "Cannot lower 512-bit vectors w/ basic ISA!");
10576 // Check for being able to broadcast a single element.
10577 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10578 Mask, Subtarget, DAG))
10581 // Dispatch to each element type for lowering. If we don't have supprot for
10582 // specific element type shuffles at 512 bits, immediately split them and
10583 // lower them. Each lowering routine of a given type is allowed to assume that
10584 // the requisite ISA extensions for that element type are available.
10585 switch (VT.SimpleTy) {
10587 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10589 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10591 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10593 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10595 if (Subtarget->hasBWI())
10596 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10599 if (Subtarget->hasBWI())
10600 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10604 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10607 // Otherwise fall back on splitting.
10608 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10611 /// \brief Top-level lowering for x86 vector shuffles.
10613 /// This handles decomposition, canonicalization, and lowering of all x86
10614 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10615 /// above in helper routines. The canonicalization attempts to widen shuffles
10616 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10617 /// s.t. only one of the two inputs needs to be tested, etc.
10618 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10619 SelectionDAG &DAG) {
10620 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10621 ArrayRef<int> Mask = SVOp->getMask();
10622 SDValue V1 = Op.getOperand(0);
10623 SDValue V2 = Op.getOperand(1);
10624 MVT VT = Op.getSimpleValueType();
10625 int NumElements = VT.getVectorNumElements();
10628 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10630 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10631 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10632 if (V1IsUndef && V2IsUndef)
10633 return DAG.getUNDEF(VT);
10635 // When we create a shuffle node we put the UNDEF node to second operand,
10636 // but in some cases the first operand may be transformed to UNDEF.
10637 // In this case we should just commute the node.
10639 return DAG.getCommutedVectorShuffle(*SVOp);
10641 // Check for non-undef masks pointing at an undef vector and make the masks
10642 // undef as well. This makes it easier to match the shuffle based solely on
10646 if (M >= NumElements) {
10647 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10648 for (int &M : NewMask)
10649 if (M >= NumElements)
10651 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10654 // Try to collapse shuffles into using a vector type with fewer elements but
10655 // wider element types. We cap this to not form integers or floating point
10656 // elements wider than 64 bits, but it might be interesting to form i128
10657 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10658 SmallVector<int, 16> WidenedMask;
10659 if (VT.getScalarSizeInBits() < 64 &&
10660 canWidenShuffleElements(Mask, WidenedMask)) {
10661 MVT NewEltVT = VT.isFloatingPoint()
10662 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10663 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10664 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10665 // Make sure that the new vector type is legal. For example, v2f64 isn't
10667 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10668 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10669 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10670 return DAG.getNode(ISD::BITCAST, dl, VT,
10671 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10675 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10676 for (int M : SVOp->getMask())
10678 ++NumUndefElements;
10679 else if (M < NumElements)
10684 // Commute the shuffle as needed such that more elements come from V1 than
10685 // V2. This allows us to match the shuffle pattern strictly on how many
10686 // elements come from V1 without handling the symmetric cases.
10687 if (NumV2Elements > NumV1Elements)
10688 return DAG.getCommutedVectorShuffle(*SVOp);
10690 // When the number of V1 and V2 elements are the same, try to minimize the
10691 // number of uses of V2 in the low half of the vector. When that is tied,
10692 // ensure that the sum of indices for V1 is equal to or lower than the sum
10694 if (NumV1Elements == NumV2Elements) {
10695 int LowV1Elements = 0, LowV2Elements = 0;
10696 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10697 if (M >= NumElements)
10701 if (LowV2Elements > LowV1Elements) {
10702 return DAG.getCommutedVectorShuffle(*SVOp);
10703 } else if (LowV2Elements == LowV1Elements) {
10704 int SumV1Indices = 0, SumV2Indices = 0;
10705 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10706 if (SVOp->getMask()[i] >= NumElements)
10708 else if (SVOp->getMask()[i] >= 0)
10710 if (SumV2Indices < SumV1Indices)
10711 return DAG.getCommutedVectorShuffle(*SVOp);
10715 // For each vector width, delegate to a specialized lowering routine.
10716 if (VT.getSizeInBits() == 128)
10717 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10719 if (VT.getSizeInBits() == 256)
10720 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10722 // Force AVX-512 vectors to be scalarized for now.
10723 // FIXME: Implement AVX-512 support!
10724 if (VT.getSizeInBits() == 512)
10725 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10727 llvm_unreachable("Unimplemented!");
10731 //===----------------------------------------------------------------------===//
10732 // Legacy vector shuffle lowering
10734 // This code is the legacy code handling vector shuffles until the above
10735 // replaces its functionality and performance.
10736 //===----------------------------------------------------------------------===//
10738 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10739 bool hasInt256, unsigned *MaskOut = nullptr) {
10740 MVT EltVT = VT.getVectorElementType();
10742 // There is no blend with immediate in AVX-512.
10743 if (VT.is512BitVector())
10746 if (!hasSSE41 || EltVT == MVT::i8)
10748 if (!hasInt256 && VT == MVT::v16i16)
10751 unsigned MaskValue = 0;
10752 unsigned NumElems = VT.getVectorNumElements();
10753 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10754 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10755 unsigned NumElemsInLane = NumElems / NumLanes;
10757 // Blend for v16i16 should be symetric for the both lanes.
10758 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10760 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10761 int EltIdx = MaskVals[i];
10763 if ((EltIdx < 0 || EltIdx == (int)i) &&
10764 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10767 if (((unsigned)EltIdx == (i + NumElems)) &&
10768 (SndLaneEltIdx < 0 ||
10769 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10770 MaskValue |= (1 << i);
10776 *MaskOut = MaskValue;
10780 // Try to lower a shuffle node into a simple blend instruction.
10781 // This function assumes isBlendMask returns true for this
10782 // SuffleVectorSDNode
10783 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10784 unsigned MaskValue,
10785 const X86Subtarget *Subtarget,
10786 SelectionDAG &DAG) {
10787 MVT VT = SVOp->getSimpleValueType(0);
10788 MVT EltVT = VT.getVectorElementType();
10789 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10790 Subtarget->hasInt256() && "Trying to lower a "
10791 "VECTOR_SHUFFLE to a Blend but "
10792 "with the wrong mask"));
10793 SDValue V1 = SVOp->getOperand(0);
10794 SDValue V2 = SVOp->getOperand(1);
10796 unsigned NumElems = VT.getVectorNumElements();
10798 // Convert i32 vectors to floating point if it is not AVX2.
10799 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10801 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10802 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10804 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10805 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10808 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10809 DAG.getConstant(MaskValue, MVT::i32));
10810 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10813 /// In vector type \p VT, return true if the element at index \p InputIdx
10814 /// falls on a different 128-bit lane than \p OutputIdx.
10815 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10816 unsigned OutputIdx) {
10817 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10818 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10821 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10822 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10823 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10824 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10826 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10827 SelectionDAG &DAG) {
10828 MVT VT = V1.getSimpleValueType();
10829 assert(VT.is128BitVector() || VT.is256BitVector());
10831 MVT EltVT = VT.getVectorElementType();
10832 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10833 unsigned NumElts = VT.getVectorNumElements();
10835 SmallVector<SDValue, 32> PshufbMask;
10836 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10837 int InputIdx = MaskVals[OutputIdx];
10838 unsigned InputByteIdx;
10840 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10841 InputByteIdx = 0x80;
10843 // Cross lane is not allowed.
10844 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10846 InputByteIdx = InputIdx * EltSizeInBytes;
10847 // Index is an byte offset within the 128-bit lane.
10848 InputByteIdx &= 0xf;
10851 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10852 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10853 if (InputByteIdx != 0x80)
10858 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10860 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10861 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10862 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10865 // v8i16 shuffles - Prefer shuffles in the following order:
10866 // 1. [all] pshuflw, pshufhw, optional move
10867 // 2. [ssse3] 1 x pshufb
10868 // 3. [ssse3] 2 x pshufb + 1 x por
10869 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10871 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10872 SelectionDAG &DAG) {
10873 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10874 SDValue V1 = SVOp->getOperand(0);
10875 SDValue V2 = SVOp->getOperand(1);
10877 SmallVector<int, 8> MaskVals;
10879 // Determine if more than 1 of the words in each of the low and high quadwords
10880 // of the result come from the same quadword of one of the two inputs. Undef
10881 // mask values count as coming from any quadword, for better codegen.
10883 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10884 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10885 unsigned LoQuad[] = { 0, 0, 0, 0 };
10886 unsigned HiQuad[] = { 0, 0, 0, 0 };
10887 // Indices of quads used.
10888 std::bitset<4> InputQuads;
10889 for (unsigned i = 0; i < 8; ++i) {
10890 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10891 int EltIdx = SVOp->getMaskElt(i);
10892 MaskVals.push_back(EltIdx);
10900 ++Quad[EltIdx / 4];
10901 InputQuads.set(EltIdx / 4);
10904 int BestLoQuad = -1;
10905 unsigned MaxQuad = 1;
10906 for (unsigned i = 0; i < 4; ++i) {
10907 if (LoQuad[i] > MaxQuad) {
10909 MaxQuad = LoQuad[i];
10913 int BestHiQuad = -1;
10915 for (unsigned i = 0; i < 4; ++i) {
10916 if (HiQuad[i] > MaxQuad) {
10918 MaxQuad = HiQuad[i];
10922 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10923 // of the two input vectors, shuffle them into one input vector so only a
10924 // single pshufb instruction is necessary. If there are more than 2 input
10925 // quads, disable the next transformation since it does not help SSSE3.
10926 bool V1Used = InputQuads[0] || InputQuads[1];
10927 bool V2Used = InputQuads[2] || InputQuads[3];
10928 if (Subtarget->hasSSSE3()) {
10929 if (InputQuads.count() == 2 && V1Used && V2Used) {
10930 BestLoQuad = InputQuads[0] ? 0 : 1;
10931 BestHiQuad = InputQuads[2] ? 2 : 3;
10933 if (InputQuads.count() > 2) {
10939 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10940 // the shuffle mask. If a quad is scored as -1, that means that it contains
10941 // words from all 4 input quadwords.
10943 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10945 BestLoQuad < 0 ? 0 : BestLoQuad,
10946 BestHiQuad < 0 ? 1 : BestHiQuad
10948 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10949 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10950 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10951 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10953 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10954 // source words for the shuffle, to aid later transformations.
10955 bool AllWordsInNewV = true;
10956 bool InOrder[2] = { true, true };
10957 for (unsigned i = 0; i != 8; ++i) {
10958 int idx = MaskVals[i];
10960 InOrder[i/4] = false;
10961 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10963 AllWordsInNewV = false;
10967 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10968 if (AllWordsInNewV) {
10969 for (int i = 0; i != 8; ++i) {
10970 int idx = MaskVals[i];
10973 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10974 if ((idx != i) && idx < 4)
10976 if ((idx != i) && idx > 3)
10985 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10986 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10987 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10988 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10989 unsigned TargetMask = 0;
10990 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10991 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10992 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10993 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10994 getShufflePSHUFLWImmediate(SVOp);
10995 V1 = NewV.getOperand(0);
10996 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11000 // Promote splats to a larger type which usually leads to more efficient code.
11001 // FIXME: Is this true if pshufb is available?
11002 if (SVOp->isSplat())
11003 return PromoteSplat(SVOp, DAG);
11005 // If we have SSSE3, and all words of the result are from 1 input vector,
11006 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11007 // is present, fall back to case 4.
11008 if (Subtarget->hasSSSE3()) {
11009 SmallVector<SDValue,16> pshufbMask;
11011 // If we have elements from both input vectors, set the high bit of the
11012 // shuffle mask element to zero out elements that come from V2 in the V1
11013 // mask, and elements that come from V1 in the V2 mask, so that the two
11014 // results can be OR'd together.
11015 bool TwoInputs = V1Used && V2Used;
11016 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11018 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11020 // Calculate the shuffle mask for the second input, shuffle it, and
11021 // OR it with the first shuffled input.
11022 CommuteVectorShuffleMask(MaskVals, 8);
11023 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11024 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11025 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11028 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11029 // and update MaskVals with new element order.
11030 std::bitset<8> InOrder;
11031 if (BestLoQuad >= 0) {
11032 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11033 for (int i = 0; i != 4; ++i) {
11034 int idx = MaskVals[i];
11037 } else if ((idx / 4) == BestLoQuad) {
11038 MaskV[i] = idx & 3;
11042 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11045 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11046 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11047 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11048 NewV.getOperand(0),
11049 getShufflePSHUFLWImmediate(SVOp), DAG);
11053 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11054 // and update MaskVals with the new element order.
11055 if (BestHiQuad >= 0) {
11056 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11057 for (unsigned i = 4; i != 8; ++i) {
11058 int idx = MaskVals[i];
11061 } else if ((idx / 4) == BestHiQuad) {
11062 MaskV[i] = (idx & 3) + 4;
11066 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11069 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11070 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11071 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11072 NewV.getOperand(0),
11073 getShufflePSHUFHWImmediate(SVOp), DAG);
11077 // In case BestHi & BestLo were both -1, which means each quadword has a word
11078 // from each of the four input quadwords, calculate the InOrder bitvector now
11079 // before falling through to the insert/extract cleanup.
11080 if (BestLoQuad == -1 && BestHiQuad == -1) {
11082 for (int i = 0; i != 8; ++i)
11083 if (MaskVals[i] < 0 || MaskVals[i] == i)
11087 // The other elements are put in the right place using pextrw and pinsrw.
11088 for (unsigned i = 0; i != 8; ++i) {
11091 int EltIdx = MaskVals[i];
11094 SDValue ExtOp = (EltIdx < 8) ?
11095 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11096 DAG.getIntPtrConstant(EltIdx)) :
11097 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11098 DAG.getIntPtrConstant(EltIdx - 8));
11099 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11100 DAG.getIntPtrConstant(i));
11105 /// \brief v16i16 shuffles
11107 /// FIXME: We only support generation of a single pshufb currently. We can
11108 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11109 /// well (e.g 2 x pshufb + 1 x por).
11111 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11112 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11113 SDValue V1 = SVOp->getOperand(0);
11114 SDValue V2 = SVOp->getOperand(1);
11117 if (V2.getOpcode() != ISD::UNDEF)
11120 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11121 return getPSHUFB(MaskVals, V1, dl, DAG);
11124 // v16i8 shuffles - Prefer shuffles in the following order:
11125 // 1. [ssse3] 1 x pshufb
11126 // 2. [ssse3] 2 x pshufb + 1 x por
11127 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11128 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11129 const X86Subtarget* Subtarget,
11130 SelectionDAG &DAG) {
11131 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11132 SDValue V1 = SVOp->getOperand(0);
11133 SDValue V2 = SVOp->getOperand(1);
11135 ArrayRef<int> MaskVals = SVOp->getMask();
11137 // Promote splats to a larger type which usually leads to more efficient code.
11138 // FIXME: Is this true if pshufb is available?
11139 if (SVOp->isSplat())
11140 return PromoteSplat(SVOp, DAG);
11142 // If we have SSSE3, case 1 is generated when all result bytes come from
11143 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11144 // present, fall back to case 3.
11146 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11147 if (Subtarget->hasSSSE3()) {
11148 SmallVector<SDValue,16> pshufbMask;
11150 // If all result elements are from one input vector, then only translate
11151 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11153 // Otherwise, we have elements from both input vectors, and must zero out
11154 // elements that come from V2 in the first mask, and V1 in the second mask
11155 // so that we can OR them together.
11156 for (unsigned i = 0; i != 16; ++i) {
11157 int EltIdx = MaskVals[i];
11158 if (EltIdx < 0 || EltIdx >= 16)
11160 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11162 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11163 DAG.getNode(ISD::BUILD_VECTOR, dl,
11164 MVT::v16i8, pshufbMask));
11166 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11167 // the 2nd operand if it's undefined or zero.
11168 if (V2.getOpcode() == ISD::UNDEF ||
11169 ISD::isBuildVectorAllZeros(V2.getNode()))
11172 // Calculate the shuffle mask for the second input, shuffle it, and
11173 // OR it with the first shuffled input.
11174 pshufbMask.clear();
11175 for (unsigned i = 0; i != 16; ++i) {
11176 int EltIdx = MaskVals[i];
11177 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11178 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11180 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11181 DAG.getNode(ISD::BUILD_VECTOR, dl,
11182 MVT::v16i8, pshufbMask));
11183 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11186 // No SSSE3 - Calculate in place words and then fix all out of place words
11187 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11188 // the 16 different words that comprise the two doublequadword input vectors.
11189 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11190 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11192 for (int i = 0; i != 8; ++i) {
11193 int Elt0 = MaskVals[i*2];
11194 int Elt1 = MaskVals[i*2+1];
11196 // This word of the result is all undef, skip it.
11197 if (Elt0 < 0 && Elt1 < 0)
11200 // This word of the result is already in the correct place, skip it.
11201 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11204 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11205 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11208 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11209 // using a single extract together, load it and store it.
11210 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11211 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11212 DAG.getIntPtrConstant(Elt1 / 2));
11213 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11214 DAG.getIntPtrConstant(i));
11218 // If Elt1 is defined, extract it from the appropriate source. If the
11219 // source byte is not also odd, shift the extracted word left 8 bits
11220 // otherwise clear the bottom 8 bits if we need to do an or.
11222 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11223 DAG.getIntPtrConstant(Elt1 / 2));
11224 if ((Elt1 & 1) == 0)
11225 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11227 TLI.getShiftAmountTy(InsElt.getValueType())));
11228 else if (Elt0 >= 0)
11229 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11230 DAG.getConstant(0xFF00, MVT::i16));
11232 // If Elt0 is defined, extract it from the appropriate source. If the
11233 // source byte is not also even, shift the extracted word right 8 bits. If
11234 // Elt1 was also defined, OR the extracted values together before
11235 // inserting them in the result.
11237 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11238 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11239 if ((Elt0 & 1) != 0)
11240 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11242 TLI.getShiftAmountTy(InsElt0.getValueType())));
11243 else if (Elt1 >= 0)
11244 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11245 DAG.getConstant(0x00FF, MVT::i16));
11246 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11249 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11250 DAG.getIntPtrConstant(i));
11252 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11255 // v32i8 shuffles - Translate to VPSHUFB if possible.
11257 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11258 const X86Subtarget *Subtarget,
11259 SelectionDAG &DAG) {
11260 MVT VT = SVOp->getSimpleValueType(0);
11261 SDValue V1 = SVOp->getOperand(0);
11262 SDValue V2 = SVOp->getOperand(1);
11264 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11266 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11267 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11268 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11270 // VPSHUFB may be generated if
11271 // (1) one of input vector is undefined or zeroinitializer.
11272 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11273 // And (2) the mask indexes don't cross the 128-bit lane.
11274 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11275 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11278 if (V1IsAllZero && !V2IsAllZero) {
11279 CommuteVectorShuffleMask(MaskVals, 32);
11282 return getPSHUFB(MaskVals, V1, dl, DAG);
11285 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11286 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11287 /// done when every pair / quad of shuffle mask elements point to elements in
11288 /// the right sequence. e.g.
11289 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11291 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11292 SelectionDAG &DAG) {
11293 MVT VT = SVOp->getSimpleValueType(0);
11295 unsigned NumElems = VT.getVectorNumElements();
11298 switch (VT.SimpleTy) {
11299 default: llvm_unreachable("Unexpected!");
11302 return SDValue(SVOp, 0);
11303 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11304 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11305 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11306 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11307 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11308 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11311 SmallVector<int, 8> MaskVec;
11312 for (unsigned i = 0; i != NumElems; i += Scale) {
11314 for (unsigned j = 0; j != Scale; ++j) {
11315 int EltIdx = SVOp->getMaskElt(i+j);
11319 StartIdx = (EltIdx / Scale);
11320 if (EltIdx != (int)(StartIdx*Scale + j))
11323 MaskVec.push_back(StartIdx);
11326 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11327 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11328 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11331 /// getVZextMovL - Return a zero-extending vector move low node.
11333 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11334 SDValue SrcOp, SelectionDAG &DAG,
11335 const X86Subtarget *Subtarget, SDLoc dl) {
11336 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11337 LoadSDNode *LD = nullptr;
11338 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11339 LD = dyn_cast<LoadSDNode>(SrcOp);
11341 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11343 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11344 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11345 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11346 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11347 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11349 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11350 return DAG.getNode(ISD::BITCAST, dl, VT,
11351 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11352 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11354 SrcOp.getOperand(0)
11360 return DAG.getNode(ISD::BITCAST, dl, VT,
11361 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11362 DAG.getNode(ISD::BITCAST, dl,
11366 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11367 /// which could not be matched by any known target speficic shuffle
11369 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11371 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11372 if (NewOp.getNode())
11375 MVT VT = SVOp->getSimpleValueType(0);
11377 unsigned NumElems = VT.getVectorNumElements();
11378 unsigned NumLaneElems = NumElems / 2;
11381 MVT EltVT = VT.getVectorElementType();
11382 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11385 SmallVector<int, 16> Mask;
11386 for (unsigned l = 0; l < 2; ++l) {
11387 // Build a shuffle mask for the output, discovering on the fly which
11388 // input vectors to use as shuffle operands (recorded in InputUsed).
11389 // If building a suitable shuffle vector proves too hard, then bail
11390 // out with UseBuildVector set.
11391 bool UseBuildVector = false;
11392 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11393 unsigned LaneStart = l * NumLaneElems;
11394 for (unsigned i = 0; i != NumLaneElems; ++i) {
11395 // The mask element. This indexes into the input.
11396 int Idx = SVOp->getMaskElt(i+LaneStart);
11398 // the mask element does not index into any input vector.
11399 Mask.push_back(-1);
11403 // The input vector this mask element indexes into.
11404 int Input = Idx / NumLaneElems;
11406 // Turn the index into an offset from the start of the input vector.
11407 Idx -= Input * NumLaneElems;
11409 // Find or create a shuffle vector operand to hold this input.
11411 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11412 if (InputUsed[OpNo] == Input)
11413 // This input vector is already an operand.
11415 if (InputUsed[OpNo] < 0) {
11416 // Create a new operand for this input vector.
11417 InputUsed[OpNo] = Input;
11422 if (OpNo >= array_lengthof(InputUsed)) {
11423 // More than two input vectors used! Give up on trying to create a
11424 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11425 UseBuildVector = true;
11429 // Add the mask index for the new shuffle vector.
11430 Mask.push_back(Idx + OpNo * NumLaneElems);
11433 if (UseBuildVector) {
11434 SmallVector<SDValue, 16> SVOps;
11435 for (unsigned i = 0; i != NumLaneElems; ++i) {
11436 // The mask element. This indexes into the input.
11437 int Idx = SVOp->getMaskElt(i+LaneStart);
11439 SVOps.push_back(DAG.getUNDEF(EltVT));
11443 // The input vector this mask element indexes into.
11444 int Input = Idx / NumElems;
11446 // Turn the index into an offset from the start of the input vector.
11447 Idx -= Input * NumElems;
11449 // Extract the vector element by hand.
11450 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11451 SVOp->getOperand(Input),
11452 DAG.getIntPtrConstant(Idx)));
11455 // Construct the output using a BUILD_VECTOR.
11456 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11457 } else if (InputUsed[0] < 0) {
11458 // No input vectors were used! The result is undefined.
11459 Output[l] = DAG.getUNDEF(NVT);
11461 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11462 (InputUsed[0] % 2) * NumLaneElems,
11464 // If only one input was used, use an undefined vector for the other.
11465 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11466 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11467 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11468 // At least one input vector was used. Create a new shuffle vector.
11469 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11475 // Concatenate the result back
11476 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11479 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11480 /// 4 elements, and match them with several different shuffle types.
11482 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11483 SDValue V1 = SVOp->getOperand(0);
11484 SDValue V2 = SVOp->getOperand(1);
11486 MVT VT = SVOp->getSimpleValueType(0);
11488 assert(VT.is128BitVector() && "Unsupported vector size");
11490 std::pair<int, int> Locs[4];
11491 int Mask1[] = { -1, -1, -1, -1 };
11492 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11494 unsigned NumHi = 0;
11495 unsigned NumLo = 0;
11496 for (unsigned i = 0; i != 4; ++i) {
11497 int Idx = PermMask[i];
11499 Locs[i] = std::make_pair(-1, -1);
11501 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11503 Locs[i] = std::make_pair(0, NumLo);
11504 Mask1[NumLo] = Idx;
11507 Locs[i] = std::make_pair(1, NumHi);
11509 Mask1[2+NumHi] = Idx;
11515 if (NumLo <= 2 && NumHi <= 2) {
11516 // If no more than two elements come from either vector. This can be
11517 // implemented with two shuffles. First shuffle gather the elements.
11518 // The second shuffle, which takes the first shuffle as both of its
11519 // vector operands, put the elements into the right order.
11520 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11522 int Mask2[] = { -1, -1, -1, -1 };
11524 for (unsigned i = 0; i != 4; ++i)
11525 if (Locs[i].first != -1) {
11526 unsigned Idx = (i < 2) ? 0 : 4;
11527 Idx += Locs[i].first * 2 + Locs[i].second;
11531 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11534 if (NumLo == 3 || NumHi == 3) {
11535 // Otherwise, we must have three elements from one vector, call it X, and
11536 // one element from the other, call it Y. First, use a shufps to build an
11537 // intermediate vector with the one element from Y and the element from X
11538 // that will be in the same half in the final destination (the indexes don't
11539 // matter). Then, use a shufps to build the final vector, taking the half
11540 // containing the element from Y from the intermediate, and the other half
11543 // Normalize it so the 3 elements come from V1.
11544 CommuteVectorShuffleMask(PermMask, 4);
11548 // Find the element from V2.
11550 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11551 int Val = PermMask[HiIndex];
11558 Mask1[0] = PermMask[HiIndex];
11560 Mask1[2] = PermMask[HiIndex^1];
11562 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11564 if (HiIndex >= 2) {
11565 Mask1[0] = PermMask[0];
11566 Mask1[1] = PermMask[1];
11567 Mask1[2] = HiIndex & 1 ? 6 : 4;
11568 Mask1[3] = HiIndex & 1 ? 4 : 6;
11569 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11572 Mask1[0] = HiIndex & 1 ? 2 : 0;
11573 Mask1[1] = HiIndex & 1 ? 0 : 2;
11574 Mask1[2] = PermMask[2];
11575 Mask1[3] = PermMask[3];
11580 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11583 // Break it into (shuffle shuffle_hi, shuffle_lo).
11584 int LoMask[] = { -1, -1, -1, -1 };
11585 int HiMask[] = { -1, -1, -1, -1 };
11587 int *MaskPtr = LoMask;
11588 unsigned MaskIdx = 0;
11589 unsigned LoIdx = 0;
11590 unsigned HiIdx = 2;
11591 for (unsigned i = 0; i != 4; ++i) {
11598 int Idx = PermMask[i];
11600 Locs[i] = std::make_pair(-1, -1);
11601 } else if (Idx < 4) {
11602 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11603 MaskPtr[LoIdx] = Idx;
11606 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11607 MaskPtr[HiIdx] = Idx;
11612 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11613 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11614 int MaskOps[] = { -1, -1, -1, -1 };
11615 for (unsigned i = 0; i != 4; ++i)
11616 if (Locs[i].first != -1)
11617 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11618 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11621 static bool MayFoldVectorLoad(SDValue V) {
11622 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11623 V = V.getOperand(0);
11625 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11626 V = V.getOperand(0);
11627 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11628 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11629 // BUILD_VECTOR (load), undef
11630 V = V.getOperand(0);
11632 return MayFoldLoad(V);
11636 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11637 MVT VT = Op.getSimpleValueType();
11639 // Canonizalize to v2f64.
11640 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11641 return DAG.getNode(ISD::BITCAST, dl, VT,
11642 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11647 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11649 SDValue V1 = Op.getOperand(0);
11650 SDValue V2 = Op.getOperand(1);
11651 MVT VT = Op.getSimpleValueType();
11653 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11655 if (HasSSE2 && VT == MVT::v2f64)
11656 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11658 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11659 return DAG.getNode(ISD::BITCAST, dl, VT,
11660 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11661 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11662 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11666 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11667 SDValue V1 = Op.getOperand(0);
11668 SDValue V2 = Op.getOperand(1);
11669 MVT VT = Op.getSimpleValueType();
11671 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11672 "unsupported shuffle type");
11674 if (V2.getOpcode() == ISD::UNDEF)
11678 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11682 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11683 SDValue V1 = Op.getOperand(0);
11684 SDValue V2 = Op.getOperand(1);
11685 MVT VT = Op.getSimpleValueType();
11686 unsigned NumElems = VT.getVectorNumElements();
11688 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11689 // operand of these instructions is only memory, so check if there's a
11690 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11692 bool CanFoldLoad = false;
11694 // Trivial case, when V2 comes from a load.
11695 if (MayFoldVectorLoad(V2))
11696 CanFoldLoad = true;
11698 // When V1 is a load, it can be folded later into a store in isel, example:
11699 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11701 // (MOVLPSmr addr:$src1, VR128:$src2)
11702 // So, recognize this potential and also use MOVLPS or MOVLPD
11703 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11704 CanFoldLoad = true;
11706 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11708 if (HasSSE2 && NumElems == 2)
11709 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11712 // If we don't care about the second element, proceed to use movss.
11713 if (SVOp->getMaskElt(1) != -1)
11714 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11717 // movl and movlp will both match v2i64, but v2i64 is never matched by
11718 // movl earlier because we make it strict to avoid messing with the movlp load
11719 // folding logic (see the code above getMOVLP call). Match it here then,
11720 // this is horrible, but will stay like this until we move all shuffle
11721 // matching to x86 specific nodes. Note that for the 1st condition all
11722 // types are matched with movsd.
11724 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11725 // as to remove this logic from here, as much as possible
11726 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11727 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11728 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11731 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11733 // Invert the operand order and use SHUFPS to match it.
11734 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11735 getShuffleSHUFImmediate(SVOp), DAG);
11738 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11739 SelectionDAG &DAG) {
11741 MVT VT = Load->getSimpleValueType(0);
11742 MVT EVT = VT.getVectorElementType();
11743 SDValue Addr = Load->getOperand(1);
11744 SDValue NewAddr = DAG.getNode(
11745 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11746 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11749 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11750 DAG.getMachineFunction().getMachineMemOperand(
11751 Load->getMemOperand(), 0, EVT.getStoreSize()));
11755 // It is only safe to call this function if isINSERTPSMask is true for
11756 // this shufflevector mask.
11757 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11758 SelectionDAG &DAG) {
11759 // Generate an insertps instruction when inserting an f32 from memory onto a
11760 // v4f32 or when copying a member from one v4f32 to another.
11761 // We also use it for transferring i32 from one register to another,
11762 // since it simply copies the same bits.
11763 // If we're transferring an i32 from memory to a specific element in a
11764 // register, we output a generic DAG that will match the PINSRD
11766 MVT VT = SVOp->getSimpleValueType(0);
11767 MVT EVT = VT.getVectorElementType();
11768 SDValue V1 = SVOp->getOperand(0);
11769 SDValue V2 = SVOp->getOperand(1);
11770 auto Mask = SVOp->getMask();
11771 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11772 "unsupported vector type for insertps/pinsrd");
11774 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11775 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11776 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11780 unsigned DestIndex;
11784 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11787 // If we have 1 element from each vector, we have to check if we're
11788 // changing V1's element's place. If so, we're done. Otherwise, we
11789 // should assume we're changing V2's element's place and behave
11791 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11792 assert(DestIndex <= INT32_MAX && "truncated destination index");
11793 if (FromV1 == FromV2 &&
11794 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11798 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11801 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11802 "More than one element from V1 and from V2, or no elements from one "
11803 "of the vectors. This case should not have returned true from "
11808 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11811 // Get an index into the source vector in the range [0,4) (the mask is
11812 // in the range [0,8) because it can address V1 and V2)
11813 unsigned SrcIndex = Mask[DestIndex] % 4;
11814 if (MayFoldLoad(From)) {
11815 // Trivial case, when From comes from a load and is only used by the
11816 // shuffle. Make it use insertps from the vector that we need from that
11819 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11820 if (!NewLoad.getNode())
11823 if (EVT == MVT::f32) {
11824 // Create this as a scalar to vector to match the instruction pattern.
11825 SDValue LoadScalarToVector =
11826 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11827 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11828 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11830 } else { // EVT == MVT::i32
11831 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11832 // instruction, to match the PINSRD instruction, which loads an i32 to a
11833 // certain vector element.
11834 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11835 DAG.getConstant(DestIndex, MVT::i32));
11839 // Vector-element-to-vector
11840 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11841 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11844 // Reduce a vector shuffle to zext.
11845 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11846 SelectionDAG &DAG) {
11847 // PMOVZX is only available from SSE41.
11848 if (!Subtarget->hasSSE41())
11851 MVT VT = Op.getSimpleValueType();
11853 // Only AVX2 support 256-bit vector integer extending.
11854 if (!Subtarget->hasInt256() && VT.is256BitVector())
11857 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11859 SDValue V1 = Op.getOperand(0);
11860 SDValue V2 = Op.getOperand(1);
11861 unsigned NumElems = VT.getVectorNumElements();
11863 // Extending is an unary operation and the element type of the source vector
11864 // won't be equal to or larger than i64.
11865 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11866 VT.getVectorElementType() == MVT::i64)
11869 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11870 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11871 while ((1U << Shift) < NumElems) {
11872 if (SVOp->getMaskElt(1U << Shift) == 1)
11875 // The maximal ratio is 8, i.e. from i8 to i64.
11880 // Check the shuffle mask.
11881 unsigned Mask = (1U << Shift) - 1;
11882 for (unsigned i = 0; i != NumElems; ++i) {
11883 int EltIdx = SVOp->getMaskElt(i);
11884 if ((i & Mask) != 0 && EltIdx != -1)
11886 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11890 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11891 MVT NeVT = MVT::getIntegerVT(NBits);
11892 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11894 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11897 return DAG.getNode(ISD::BITCAST, DL, VT,
11898 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11901 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11902 SelectionDAG &DAG) {
11903 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11904 MVT VT = Op.getSimpleValueType();
11906 SDValue V1 = Op.getOperand(0);
11907 SDValue V2 = Op.getOperand(1);
11909 if (isZeroShuffle(SVOp))
11910 return getZeroVector(VT, Subtarget, DAG, dl);
11912 // Handle splat operations
11913 if (SVOp->isSplat()) {
11914 // Use vbroadcast whenever the splat comes from a foldable load
11915 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11916 if (Broadcast.getNode())
11920 // Check integer expanding shuffles.
11921 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11922 if (NewOp.getNode())
11925 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11927 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11928 VT == MVT::v32i8) {
11929 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11930 if (NewOp.getNode())
11931 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11932 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11933 // FIXME: Figure out a cleaner way to do this.
11934 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11935 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11936 if (NewOp.getNode()) {
11937 MVT NewVT = NewOp.getSimpleValueType();
11938 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11939 NewVT, true, false))
11940 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11943 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11944 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11945 if (NewOp.getNode()) {
11946 MVT NewVT = NewOp.getSimpleValueType();
11947 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11948 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11957 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11958 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11959 SDValue V1 = Op.getOperand(0);
11960 SDValue V2 = Op.getOperand(1);
11961 MVT VT = Op.getSimpleValueType();
11963 unsigned NumElems = VT.getVectorNumElements();
11964 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11965 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11966 bool V1IsSplat = false;
11967 bool V2IsSplat = false;
11968 bool HasSSE2 = Subtarget->hasSSE2();
11969 bool HasFp256 = Subtarget->hasFp256();
11970 bool HasInt256 = Subtarget->hasInt256();
11971 MachineFunction &MF = DAG.getMachineFunction();
11972 bool OptForSize = MF.getFunction()->getAttributes().
11973 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11975 // Check if we should use the experimental vector shuffle lowering. If so,
11976 // delegate completely to that code path.
11977 if (ExperimentalVectorShuffleLowering)
11978 return lowerVectorShuffle(Op, Subtarget, DAG);
11980 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11982 if (V1IsUndef && V2IsUndef)
11983 return DAG.getUNDEF(VT);
11985 // When we create a shuffle node we put the UNDEF node to second operand,
11986 // but in some cases the first operand may be transformed to UNDEF.
11987 // In this case we should just commute the node.
11989 return DAG.getCommutedVectorShuffle(*SVOp);
11991 // Vector shuffle lowering takes 3 steps:
11993 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11994 // narrowing and commutation of operands should be handled.
11995 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11997 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11998 // so the shuffle can be broken into other shuffles and the legalizer can
11999 // try the lowering again.
12001 // The general idea is that no vector_shuffle operation should be left to
12002 // be matched during isel, all of them must be converted to a target specific
12005 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12006 // narrowing and commutation of operands should be handled. The actual code
12007 // doesn't include all of those, work in progress...
12008 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12009 if (NewOp.getNode())
12012 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12014 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12015 // unpckh_undef). Only use pshufd if speed is more important than size.
12016 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12017 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12018 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12019 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12021 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12022 V2IsUndef && MayFoldVectorLoad(V1))
12023 return getMOVDDup(Op, dl, V1, DAG);
12025 if (isMOVHLPS_v_undef_Mask(M, VT))
12026 return getMOVHighToLow(Op, dl, DAG);
12028 // Use to match splats
12029 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12030 (VT == MVT::v2f64 || VT == MVT::v2i64))
12031 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12033 if (isPSHUFDMask(M, VT)) {
12034 // The actual implementation will match the mask in the if above and then
12035 // during isel it can match several different instructions, not only pshufd
12036 // as its name says, sad but true, emulate the behavior for now...
12037 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12038 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12040 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12042 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12043 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12045 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12046 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12049 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12053 if (isPALIGNRMask(M, VT, Subtarget))
12054 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12055 getShufflePALIGNRImmediate(SVOp),
12058 if (isVALIGNMask(M, VT, Subtarget))
12059 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12060 getShuffleVALIGNImmediate(SVOp),
12063 // Check if this can be converted into a logical shift.
12064 bool isLeft = false;
12065 unsigned ShAmt = 0;
12067 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12068 if (isShift && ShVal.hasOneUse()) {
12069 // If the shifted value has multiple uses, it may be cheaper to use
12070 // v_set0 + movlhps or movhlps, etc.
12071 MVT EltVT = VT.getVectorElementType();
12072 ShAmt *= EltVT.getSizeInBits();
12073 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12076 if (isMOVLMask(M, VT)) {
12077 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12078 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12079 if (!isMOVLPMask(M, VT)) {
12080 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12081 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12083 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12084 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12088 // FIXME: fold these into legal mask.
12089 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12090 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12092 if (isMOVHLPSMask(M, VT))
12093 return getMOVHighToLow(Op, dl, DAG);
12095 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12096 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12098 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12099 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12101 if (isMOVLPMask(M, VT))
12102 return getMOVLP(Op, dl, DAG, HasSSE2);
12104 if (ShouldXformToMOVHLPS(M, VT) ||
12105 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12106 return DAG.getCommutedVectorShuffle(*SVOp);
12109 // No better options. Use a vshldq / vsrldq.
12110 MVT EltVT = VT.getVectorElementType();
12111 ShAmt *= EltVT.getSizeInBits();
12112 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12115 bool Commuted = false;
12116 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12117 // 1,1,1,1 -> v8i16 though.
12118 BitVector UndefElements;
12119 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12120 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12122 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12123 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12126 // Canonicalize the splat or undef, if present, to be on the RHS.
12127 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12128 CommuteVectorShuffleMask(M, NumElems);
12130 std::swap(V1IsSplat, V2IsSplat);
12134 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12135 // Shuffling low element of v1 into undef, just return v1.
12138 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12139 // the instruction selector will not match, so get a canonical MOVL with
12140 // swapped operands to undo the commute.
12141 return getMOVL(DAG, dl, VT, V2, V1);
12144 if (isUNPCKLMask(M, VT, HasInt256))
12145 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12147 if (isUNPCKHMask(M, VT, HasInt256))
12148 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12151 // Normalize mask so all entries that point to V2 points to its first
12152 // element then try to match unpck{h|l} again. If match, return a
12153 // new vector_shuffle with the corrected mask.p
12154 SmallVector<int, 8> NewMask(M.begin(), M.end());
12155 NormalizeMask(NewMask, NumElems);
12156 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12157 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12158 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12159 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12163 // Commute is back and try unpck* again.
12164 // FIXME: this seems wrong.
12165 CommuteVectorShuffleMask(M, NumElems);
12167 std::swap(V1IsSplat, V2IsSplat);
12169 if (isUNPCKLMask(M, VT, HasInt256))
12170 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12172 if (isUNPCKHMask(M, VT, HasInt256))
12173 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12176 // Normalize the node to match x86 shuffle ops if needed
12177 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12178 return DAG.getCommutedVectorShuffle(*SVOp);
12180 // The checks below are all present in isShuffleMaskLegal, but they are
12181 // inlined here right now to enable us to directly emit target specific
12182 // nodes, and remove one by one until they don't return Op anymore.
12184 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12185 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12186 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12187 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12190 if (isPSHUFHWMask(M, VT, HasInt256))
12191 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12192 getShufflePSHUFHWImmediate(SVOp),
12195 if (isPSHUFLWMask(M, VT, HasInt256))
12196 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12197 getShufflePSHUFLWImmediate(SVOp),
12200 unsigned MaskValue;
12201 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12203 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12205 if (isSHUFPMask(M, VT))
12206 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12207 getShuffleSHUFImmediate(SVOp), DAG);
12209 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12210 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12211 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12212 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12214 //===--------------------------------------------------------------------===//
12215 // Generate target specific nodes for 128 or 256-bit shuffles only
12216 // supported in the AVX instruction set.
12219 // Handle VMOVDDUPY permutations
12220 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12221 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12223 // Handle VPERMILPS/D* permutations
12224 if (isVPERMILPMask(M, VT)) {
12225 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12226 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12227 getShuffleSHUFImmediate(SVOp), DAG);
12228 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12229 getShuffleSHUFImmediate(SVOp), DAG);
12233 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12234 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12235 Idx*(NumElems/2), DAG, dl);
12237 // Handle VPERM2F128/VPERM2I128 permutations
12238 if (isVPERM2X128Mask(M, VT, HasFp256))
12239 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12240 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12242 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12243 return getINSERTPS(SVOp, dl, DAG);
12246 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12247 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12249 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12250 VT.is512BitVector()) {
12251 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12252 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12253 SmallVector<SDValue, 16> permclMask;
12254 for (unsigned i = 0; i != NumElems; ++i) {
12255 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12258 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12260 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12261 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12262 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12263 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12264 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12267 //===--------------------------------------------------------------------===//
12268 // Since no target specific shuffle was selected for this generic one,
12269 // lower it into other known shuffles. FIXME: this isn't true yet, but
12270 // this is the plan.
12273 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12274 if (VT == MVT::v8i16) {
12275 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12276 if (NewOp.getNode())
12280 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12281 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12282 if (NewOp.getNode())
12286 if (VT == MVT::v16i8) {
12287 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12288 if (NewOp.getNode())
12292 if (VT == MVT::v32i8) {
12293 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12294 if (NewOp.getNode())
12298 // Handle all 128-bit wide vectors with 4 elements, and match them with
12299 // several different shuffle types.
12300 if (NumElems == 4 && VT.is128BitVector())
12301 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12303 // Handle general 256-bit shuffles
12304 if (VT.is256BitVector())
12305 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12310 // This function assumes its argument is a BUILD_VECTOR of constants or
12311 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12313 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12314 unsigned &MaskValue) {
12316 unsigned NumElems = BuildVector->getNumOperands();
12317 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12318 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12319 unsigned NumElemsInLane = NumElems / NumLanes;
12321 // Blend for v16i16 should be symetric for the both lanes.
12322 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12323 SDValue EltCond = BuildVector->getOperand(i);
12324 SDValue SndLaneEltCond =
12325 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12327 int Lane1Cond = -1, Lane2Cond = -1;
12328 if (isa<ConstantSDNode>(EltCond))
12329 Lane1Cond = !isZero(EltCond);
12330 if (isa<ConstantSDNode>(SndLaneEltCond))
12331 Lane2Cond = !isZero(SndLaneEltCond);
12333 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12334 // Lane1Cond != 0, means we want the first argument.
12335 // Lane1Cond == 0, means we want the second argument.
12336 // The encoding of this argument is 0 for the first argument, 1
12337 // for the second. Therefore, invert the condition.
12338 MaskValue |= !Lane1Cond << i;
12339 else if (Lane1Cond < 0)
12340 MaskValue |= !Lane2Cond << i;
12347 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12349 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12350 SelectionDAG &DAG) {
12351 SDValue Cond = Op.getOperand(0);
12352 SDValue LHS = Op.getOperand(1);
12353 SDValue RHS = Op.getOperand(2);
12355 MVT VT = Op.getSimpleValueType();
12356 MVT EltVT = VT.getVectorElementType();
12357 unsigned NumElems = VT.getVectorNumElements();
12359 // There is no blend with immediate in AVX-512.
12360 if (VT.is512BitVector())
12363 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12365 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12368 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12371 // Check the mask for BLEND and build the value.
12372 unsigned MaskValue = 0;
12373 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12376 // Convert i32 vectors to floating point if it is not AVX2.
12377 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12379 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12380 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12382 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12383 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12386 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12387 DAG.getConstant(MaskValue, MVT::i32));
12388 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12391 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12392 // A vselect where all conditions and data are constants can be optimized into
12393 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12394 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12395 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12396 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12399 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12400 if (BlendOp.getNode())
12403 // Some types for vselect were previously set to Expand, not Legal or
12404 // Custom. Return an empty SDValue so we fall-through to Expand, after
12405 // the Custom lowering phase.
12406 MVT VT = Op.getSimpleValueType();
12407 switch (VT.SimpleTy) {
12412 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12417 // We couldn't create a "Blend with immediate" node.
12418 // This node should still be legal, but we'll have to emit a blendv*
12423 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12424 MVT VT = Op.getSimpleValueType();
12427 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12430 if (VT.getSizeInBits() == 8) {
12431 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12432 Op.getOperand(0), Op.getOperand(1));
12433 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12434 DAG.getValueType(VT));
12435 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12438 if (VT.getSizeInBits() == 16) {
12439 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12440 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12442 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12443 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12444 DAG.getNode(ISD::BITCAST, dl,
12447 Op.getOperand(1)));
12448 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12449 Op.getOperand(0), Op.getOperand(1));
12450 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12451 DAG.getValueType(VT));
12452 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12455 if (VT == MVT::f32) {
12456 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12457 // the result back to FR32 register. It's only worth matching if the
12458 // result has a single use which is a store or a bitcast to i32. And in
12459 // the case of a store, it's not worth it if the index is a constant 0,
12460 // because a MOVSSmr can be used instead, which is smaller and faster.
12461 if (!Op.hasOneUse())
12463 SDNode *User = *Op.getNode()->use_begin();
12464 if ((User->getOpcode() != ISD::STORE ||
12465 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12466 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12467 (User->getOpcode() != ISD::BITCAST ||
12468 User->getValueType(0) != MVT::i32))
12470 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12471 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12474 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12477 if (VT == MVT::i32 || VT == MVT::i64) {
12478 // ExtractPS/pextrq works with constant index.
12479 if (isa<ConstantSDNode>(Op.getOperand(1)))
12485 /// Extract one bit from mask vector, like v16i1 or v8i1.
12486 /// AVX-512 feature.
12488 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12489 SDValue Vec = Op.getOperand(0);
12491 MVT VecVT = Vec.getSimpleValueType();
12492 SDValue Idx = Op.getOperand(1);
12493 MVT EltVT = Op.getSimpleValueType();
12495 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12497 // variable index can't be handled in mask registers,
12498 // extend vector to VR512
12499 if (!isa<ConstantSDNode>(Idx)) {
12500 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12501 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12502 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12503 ExtVT.getVectorElementType(), Ext, Idx);
12504 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12507 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12508 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12509 unsigned MaxSift = rc->getSize()*8 - 1;
12510 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12511 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12512 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12513 DAG.getConstant(MaxSift, MVT::i8));
12514 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12515 DAG.getIntPtrConstant(0));
12519 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12520 SelectionDAG &DAG) const {
12522 SDValue Vec = Op.getOperand(0);
12523 MVT VecVT = Vec.getSimpleValueType();
12524 SDValue Idx = Op.getOperand(1);
12526 if (Op.getSimpleValueType() == MVT::i1)
12527 return ExtractBitFromMaskVector(Op, DAG);
12529 if (!isa<ConstantSDNode>(Idx)) {
12530 if (VecVT.is512BitVector() ||
12531 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12532 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12535 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12536 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12537 MaskEltVT.getSizeInBits());
12539 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12540 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12541 getZeroVector(MaskVT, Subtarget, DAG, dl),
12542 Idx, DAG.getConstant(0, getPointerTy()));
12543 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12544 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12545 Perm, DAG.getConstant(0, getPointerTy()));
12550 // If this is a 256-bit vector result, first extract the 128-bit vector and
12551 // then extract the element from the 128-bit vector.
12552 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12554 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12555 // Get the 128-bit vector.
12556 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12557 MVT EltVT = VecVT.getVectorElementType();
12559 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12561 //if (IdxVal >= NumElems/2)
12562 // IdxVal -= NumElems/2;
12563 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12564 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12565 DAG.getConstant(IdxVal, MVT::i32));
12568 assert(VecVT.is128BitVector() && "Unexpected vector length");
12570 if (Subtarget->hasSSE41()) {
12571 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12576 MVT VT = Op.getSimpleValueType();
12577 // TODO: handle v16i8.
12578 if (VT.getSizeInBits() == 16) {
12579 SDValue Vec = Op.getOperand(0);
12580 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12582 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12583 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12584 DAG.getNode(ISD::BITCAST, dl,
12586 Op.getOperand(1)));
12587 // Transform it so it match pextrw which produces a 32-bit result.
12588 MVT EltVT = MVT::i32;
12589 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12590 Op.getOperand(0), Op.getOperand(1));
12591 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12592 DAG.getValueType(VT));
12593 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12596 if (VT.getSizeInBits() == 32) {
12597 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12601 // SHUFPS the element to the lowest double word, then movss.
12602 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12603 MVT VVT = Op.getOperand(0).getSimpleValueType();
12604 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12605 DAG.getUNDEF(VVT), Mask);
12606 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12607 DAG.getIntPtrConstant(0));
12610 if (VT.getSizeInBits() == 64) {
12611 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12612 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12613 // to match extract_elt for f64.
12614 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12618 // UNPCKHPD the element to the lowest double word, then movsd.
12619 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12620 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12621 int Mask[2] = { 1, -1 };
12622 MVT VVT = Op.getOperand(0).getSimpleValueType();
12623 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12624 DAG.getUNDEF(VVT), Mask);
12625 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12626 DAG.getIntPtrConstant(0));
12632 /// Insert one bit to mask vector, like v16i1 or v8i1.
12633 /// AVX-512 feature.
12635 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12637 SDValue Vec = Op.getOperand(0);
12638 SDValue Elt = Op.getOperand(1);
12639 SDValue Idx = Op.getOperand(2);
12640 MVT VecVT = Vec.getSimpleValueType();
12642 if (!isa<ConstantSDNode>(Idx)) {
12643 // Non constant index. Extend source and destination,
12644 // insert element and then truncate the result.
12645 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12646 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12647 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12648 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12649 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12650 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12653 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12654 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12655 if (Vec.getOpcode() == ISD::UNDEF)
12656 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12657 DAG.getConstant(IdxVal, MVT::i8));
12658 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12659 unsigned MaxSift = rc->getSize()*8 - 1;
12660 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12661 DAG.getConstant(MaxSift, MVT::i8));
12662 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12663 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12664 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12667 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12668 SelectionDAG &DAG) const {
12669 MVT VT = Op.getSimpleValueType();
12670 MVT EltVT = VT.getVectorElementType();
12672 if (EltVT == MVT::i1)
12673 return InsertBitToMaskVector(Op, DAG);
12676 SDValue N0 = Op.getOperand(0);
12677 SDValue N1 = Op.getOperand(1);
12678 SDValue N2 = Op.getOperand(2);
12679 if (!isa<ConstantSDNode>(N2))
12681 auto *N2C = cast<ConstantSDNode>(N2);
12682 unsigned IdxVal = N2C->getZExtValue();
12684 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12685 // into that, and then insert the subvector back into the result.
12686 if (VT.is256BitVector() || VT.is512BitVector()) {
12687 // Get the desired 128-bit vector half.
12688 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12690 // Insert the element into the desired half.
12691 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12692 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12694 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12695 DAG.getConstant(IdxIn128, MVT::i32));
12697 // Insert the changed part back to the 256-bit vector
12698 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12700 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12702 if (Subtarget->hasSSE41()) {
12703 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12705 if (VT == MVT::v8i16) {
12706 Opc = X86ISD::PINSRW;
12708 assert(VT == MVT::v16i8);
12709 Opc = X86ISD::PINSRB;
12712 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12714 if (N1.getValueType() != MVT::i32)
12715 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12716 if (N2.getValueType() != MVT::i32)
12717 N2 = DAG.getIntPtrConstant(IdxVal);
12718 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12721 if (EltVT == MVT::f32) {
12722 // Bits [7:6] of the constant are the source select. This will always be
12723 // zero here. The DAG Combiner may combine an extract_elt index into
12725 // bits. For example (insert (extract, 3), 2) could be matched by
12727 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12728 // Bits [5:4] of the constant are the destination select. This is the
12729 // value of the incoming immediate.
12730 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12731 // combine either bitwise AND or insert of float 0.0 to set these bits.
12732 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12733 // Create this as a scalar to vector..
12734 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12735 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12738 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12739 // PINSR* works with constant index.
12744 if (EltVT == MVT::i8)
12747 if (EltVT.getSizeInBits() == 16) {
12748 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12749 // as its second argument.
12750 if (N1.getValueType() != MVT::i32)
12751 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12752 if (N2.getValueType() != MVT::i32)
12753 N2 = DAG.getIntPtrConstant(IdxVal);
12754 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12759 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12761 MVT OpVT = Op.getSimpleValueType();
12763 // If this is a 256-bit vector result, first insert into a 128-bit
12764 // vector and then insert into the 256-bit vector.
12765 if (!OpVT.is128BitVector()) {
12766 // Insert into a 128-bit vector.
12767 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12768 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12769 OpVT.getVectorNumElements() / SizeFactor);
12771 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12773 // Insert the 128-bit vector.
12774 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12777 if (OpVT == MVT::v1i64 &&
12778 Op.getOperand(0).getValueType() == MVT::i64)
12779 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12781 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12782 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12783 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12784 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12787 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12788 // a simple subregister reference or explicit instructions to grab
12789 // upper bits of a vector.
12790 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12791 SelectionDAG &DAG) {
12793 SDValue In = Op.getOperand(0);
12794 SDValue Idx = Op.getOperand(1);
12795 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12796 MVT ResVT = Op.getSimpleValueType();
12797 MVT InVT = In.getSimpleValueType();
12799 if (Subtarget->hasFp256()) {
12800 if (ResVT.is128BitVector() &&
12801 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12802 isa<ConstantSDNode>(Idx)) {
12803 return Extract128BitVector(In, IdxVal, DAG, dl);
12805 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12806 isa<ConstantSDNode>(Idx)) {
12807 return Extract256BitVector(In, IdxVal, DAG, dl);
12813 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12814 // simple superregister reference or explicit instructions to insert
12815 // the upper bits of a vector.
12816 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12817 SelectionDAG &DAG) {
12818 if (Subtarget->hasFp256()) {
12819 SDLoc dl(Op.getNode());
12820 SDValue Vec = Op.getNode()->getOperand(0);
12821 SDValue SubVec = Op.getNode()->getOperand(1);
12822 SDValue Idx = Op.getNode()->getOperand(2);
12824 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12825 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12826 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12827 isa<ConstantSDNode>(Idx)) {
12828 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12829 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12832 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12833 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12834 isa<ConstantSDNode>(Idx)) {
12835 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12836 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12842 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12843 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12844 // one of the above mentioned nodes. It has to be wrapped because otherwise
12845 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12846 // be used to form addressing mode. These wrapped nodes will be selected
12849 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12850 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12852 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12853 // global base reg.
12854 unsigned char OpFlag = 0;
12855 unsigned WrapperKind = X86ISD::Wrapper;
12856 CodeModel::Model M = DAG.getTarget().getCodeModel();
12858 if (Subtarget->isPICStyleRIPRel() &&
12859 (M == CodeModel::Small || M == CodeModel::Kernel))
12860 WrapperKind = X86ISD::WrapperRIP;
12861 else if (Subtarget->isPICStyleGOT())
12862 OpFlag = X86II::MO_GOTOFF;
12863 else if (Subtarget->isPICStyleStubPIC())
12864 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12866 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12867 CP->getAlignment(),
12868 CP->getOffset(), OpFlag);
12870 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12871 // With PIC, the address is actually $g + Offset.
12873 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12874 DAG.getNode(X86ISD::GlobalBaseReg,
12875 SDLoc(), getPointerTy()),
12882 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12883 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12885 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12886 // global base reg.
12887 unsigned char OpFlag = 0;
12888 unsigned WrapperKind = X86ISD::Wrapper;
12889 CodeModel::Model M = DAG.getTarget().getCodeModel();
12891 if (Subtarget->isPICStyleRIPRel() &&
12892 (M == CodeModel::Small || M == CodeModel::Kernel))
12893 WrapperKind = X86ISD::WrapperRIP;
12894 else if (Subtarget->isPICStyleGOT())
12895 OpFlag = X86II::MO_GOTOFF;
12896 else if (Subtarget->isPICStyleStubPIC())
12897 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12899 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12902 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12904 // With PIC, the address is actually $g + Offset.
12906 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12907 DAG.getNode(X86ISD::GlobalBaseReg,
12908 SDLoc(), getPointerTy()),
12915 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12916 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12918 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12919 // global base reg.
12920 unsigned char OpFlag = 0;
12921 unsigned WrapperKind = X86ISD::Wrapper;
12922 CodeModel::Model M = DAG.getTarget().getCodeModel();
12924 if (Subtarget->isPICStyleRIPRel() &&
12925 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12926 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12927 OpFlag = X86II::MO_GOTPCREL;
12928 WrapperKind = X86ISD::WrapperRIP;
12929 } else if (Subtarget->isPICStyleGOT()) {
12930 OpFlag = X86II::MO_GOT;
12931 } else if (Subtarget->isPICStyleStubPIC()) {
12932 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12933 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12934 OpFlag = X86II::MO_DARWIN_NONLAZY;
12937 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12940 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12942 // With PIC, the address is actually $g + Offset.
12943 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12944 !Subtarget->is64Bit()) {
12945 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12946 DAG.getNode(X86ISD::GlobalBaseReg,
12947 SDLoc(), getPointerTy()),
12951 // For symbols that require a load from a stub to get the address, emit the
12953 if (isGlobalStubReference(OpFlag))
12954 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12955 MachinePointerInfo::getGOT(), false, false, false, 0);
12961 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12962 // Create the TargetBlockAddressAddress node.
12963 unsigned char OpFlags =
12964 Subtarget->ClassifyBlockAddressReference();
12965 CodeModel::Model M = DAG.getTarget().getCodeModel();
12966 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12967 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12969 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12972 if (Subtarget->isPICStyleRIPRel() &&
12973 (M == CodeModel::Small || M == CodeModel::Kernel))
12974 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12976 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12978 // With PIC, the address is actually $g + Offset.
12979 if (isGlobalRelativeToPICBase(OpFlags)) {
12980 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12981 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12989 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12990 int64_t Offset, SelectionDAG &DAG) const {
12991 // Create the TargetGlobalAddress node, folding in the constant
12992 // offset if it is legal.
12993 unsigned char OpFlags =
12994 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12995 CodeModel::Model M = DAG.getTarget().getCodeModel();
12997 if (OpFlags == X86II::MO_NO_FLAG &&
12998 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12999 // A direct static reference to a global.
13000 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13003 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13006 if (Subtarget->isPICStyleRIPRel() &&
13007 (M == CodeModel::Small || M == CodeModel::Kernel))
13008 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13010 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13012 // With PIC, the address is actually $g + Offset.
13013 if (isGlobalRelativeToPICBase(OpFlags)) {
13014 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13015 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13019 // For globals that require a load from a stub to get the address, emit the
13021 if (isGlobalStubReference(OpFlags))
13022 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13023 MachinePointerInfo::getGOT(), false, false, false, 0);
13025 // If there was a non-zero offset that we didn't fold, create an explicit
13026 // addition for it.
13028 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13029 DAG.getConstant(Offset, getPointerTy()));
13035 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13036 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13037 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13038 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13042 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13043 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13044 unsigned char OperandFlags, bool LocalDynamic = false) {
13045 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13046 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13048 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13049 GA->getValueType(0),
13053 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13057 SDValue Ops[] = { Chain, TGA, *InFlag };
13058 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13060 SDValue Ops[] = { Chain, TGA };
13061 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13064 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13065 MFI->setAdjustsStack(true);
13066 MFI->setHasCalls(true);
13068 SDValue Flag = Chain.getValue(1);
13069 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13072 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13074 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13077 SDLoc dl(GA); // ? function entry point might be better
13078 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13079 DAG.getNode(X86ISD::GlobalBaseReg,
13080 SDLoc(), PtrVT), InFlag);
13081 InFlag = Chain.getValue(1);
13083 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13086 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13088 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13090 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13091 X86::RAX, X86II::MO_TLSGD);
13094 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13100 // Get the start address of the TLS block for this module.
13101 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13102 .getInfo<X86MachineFunctionInfo>();
13103 MFI->incNumLocalDynamicTLSAccesses();
13107 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13108 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13111 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13112 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13113 InFlag = Chain.getValue(1);
13114 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13115 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13118 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13122 unsigned char OperandFlags = X86II::MO_DTPOFF;
13123 unsigned WrapperKind = X86ISD::Wrapper;
13124 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13125 GA->getValueType(0),
13126 GA->getOffset(), OperandFlags);
13127 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13129 // Add x@dtpoff with the base.
13130 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13133 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13134 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13135 const EVT PtrVT, TLSModel::Model model,
13136 bool is64Bit, bool isPIC) {
13139 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13140 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13141 is64Bit ? 257 : 256));
13143 SDValue ThreadPointer =
13144 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13145 MachinePointerInfo(Ptr), false, false, false, 0);
13147 unsigned char OperandFlags = 0;
13148 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13150 unsigned WrapperKind = X86ISD::Wrapper;
13151 if (model == TLSModel::LocalExec) {
13152 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13153 } else if (model == TLSModel::InitialExec) {
13155 OperandFlags = X86II::MO_GOTTPOFF;
13156 WrapperKind = X86ISD::WrapperRIP;
13158 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13161 llvm_unreachable("Unexpected model");
13164 // emit "addl x@ntpoff,%eax" (local exec)
13165 // or "addl x@indntpoff,%eax" (initial exec)
13166 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13168 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13169 GA->getOffset(), OperandFlags);
13170 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13172 if (model == TLSModel::InitialExec) {
13173 if (isPIC && !is64Bit) {
13174 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13175 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13179 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13180 MachinePointerInfo::getGOT(), false, false, false, 0);
13183 // The address of the thread local variable is the add of the thread
13184 // pointer with the offset of the variable.
13185 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13189 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13191 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13192 const GlobalValue *GV = GA->getGlobal();
13194 if (Subtarget->isTargetELF()) {
13195 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13198 case TLSModel::GeneralDynamic:
13199 if (Subtarget->is64Bit())
13200 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13201 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13202 case TLSModel::LocalDynamic:
13203 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13204 Subtarget->is64Bit());
13205 case TLSModel::InitialExec:
13206 case TLSModel::LocalExec:
13207 return LowerToTLSExecModel(
13208 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13209 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13211 llvm_unreachable("Unknown TLS model.");
13214 if (Subtarget->isTargetDarwin()) {
13215 // Darwin only has one model of TLS. Lower to that.
13216 unsigned char OpFlag = 0;
13217 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13218 X86ISD::WrapperRIP : X86ISD::Wrapper;
13220 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13221 // global base reg.
13222 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13223 !Subtarget->is64Bit();
13225 OpFlag = X86II::MO_TLVP_PIC_BASE;
13227 OpFlag = X86II::MO_TLVP;
13229 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13230 GA->getValueType(0),
13231 GA->getOffset(), OpFlag);
13232 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13234 // With PIC32, the address is actually $g + Offset.
13236 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13237 DAG.getNode(X86ISD::GlobalBaseReg,
13238 SDLoc(), getPointerTy()),
13241 // Lowering the machine isd will make sure everything is in the right
13243 SDValue Chain = DAG.getEntryNode();
13244 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13245 SDValue Args[] = { Chain, Offset };
13246 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13248 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13249 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13250 MFI->setAdjustsStack(true);
13252 // And our return value (tls address) is in the standard call return value
13254 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13255 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13256 Chain.getValue(1));
13259 if (Subtarget->isTargetKnownWindowsMSVC() ||
13260 Subtarget->isTargetWindowsGNU()) {
13261 // Just use the implicit TLS architecture
13262 // Need to generate someting similar to:
13263 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13265 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13266 // mov rcx, qword [rdx+rcx*8]
13267 // mov eax, .tls$:tlsvar
13268 // [rax+rcx] contains the address
13269 // Windows 64bit: gs:0x58
13270 // Windows 32bit: fs:__tls_array
13273 SDValue Chain = DAG.getEntryNode();
13275 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13276 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13277 // use its literal value of 0x2C.
13278 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13279 ? Type::getInt8PtrTy(*DAG.getContext(),
13281 : Type::getInt32PtrTy(*DAG.getContext(),
13285 Subtarget->is64Bit()
13286 ? DAG.getIntPtrConstant(0x58)
13287 : (Subtarget->isTargetWindowsGNU()
13288 ? DAG.getIntPtrConstant(0x2C)
13289 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13291 SDValue ThreadPointer =
13292 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13293 MachinePointerInfo(Ptr), false, false, false, 0);
13295 // Load the _tls_index variable
13296 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13297 if (Subtarget->is64Bit())
13298 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13299 IDX, MachinePointerInfo(), MVT::i32,
13300 false, false, false, 0);
13302 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13303 false, false, false, 0);
13305 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13307 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13309 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13310 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13311 false, false, false, 0);
13313 // Get the offset of start of .tls section
13314 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13315 GA->getValueType(0),
13316 GA->getOffset(), X86II::MO_SECREL);
13317 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13319 // The address of the thread local variable is the add of the thread
13320 // pointer with the offset of the variable.
13321 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13324 llvm_unreachable("TLS not implemented for this target.");
13327 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13328 /// and take a 2 x i32 value to shift plus a shift amount.
13329 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13330 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13331 MVT VT = Op.getSimpleValueType();
13332 unsigned VTBits = VT.getSizeInBits();
13334 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13335 SDValue ShOpLo = Op.getOperand(0);
13336 SDValue ShOpHi = Op.getOperand(1);
13337 SDValue ShAmt = Op.getOperand(2);
13338 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13339 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13341 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13342 DAG.getConstant(VTBits - 1, MVT::i8));
13343 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13344 DAG.getConstant(VTBits - 1, MVT::i8))
13345 : DAG.getConstant(0, VT);
13347 SDValue Tmp2, Tmp3;
13348 if (Op.getOpcode() == ISD::SHL_PARTS) {
13349 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13350 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13352 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13353 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13356 // If the shift amount is larger or equal than the width of a part we can't
13357 // rely on the results of shld/shrd. Insert a test and select the appropriate
13358 // values for large shift amounts.
13359 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13360 DAG.getConstant(VTBits, MVT::i8));
13361 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13362 AndNode, DAG.getConstant(0, MVT::i8));
13365 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13366 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13367 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13369 if (Op.getOpcode() == ISD::SHL_PARTS) {
13370 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13371 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13373 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13374 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13377 SDValue Ops[2] = { Lo, Hi };
13378 return DAG.getMergeValues(Ops, dl);
13381 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13382 SelectionDAG &DAG) const {
13383 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13386 if (SrcVT.isVector()) {
13387 if (SrcVT.getVectorElementType() == MVT::i1) {
13388 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13389 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13390 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13391 Op.getOperand(0)));
13396 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13397 "Unknown SINT_TO_FP to lower!");
13399 // These are really Legal; return the operand so the caller accepts it as
13401 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13403 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13404 Subtarget->is64Bit()) {
13408 unsigned Size = SrcVT.getSizeInBits()/8;
13409 MachineFunction &MF = DAG.getMachineFunction();
13410 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13411 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13412 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13414 MachinePointerInfo::getFixedStack(SSFI),
13416 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13419 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13421 SelectionDAG &DAG) const {
13425 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13427 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13429 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13431 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13433 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13434 MachineMemOperand *MMO;
13436 int SSFI = FI->getIndex();
13438 DAG.getMachineFunction()
13439 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13440 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13442 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13443 StackSlot = StackSlot.getOperand(1);
13445 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13446 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13448 Tys, Ops, SrcVT, MMO);
13451 Chain = Result.getValue(1);
13452 SDValue InFlag = Result.getValue(2);
13454 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13455 // shouldn't be necessary except that RFP cannot be live across
13456 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13457 MachineFunction &MF = DAG.getMachineFunction();
13458 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13459 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13460 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13461 Tys = DAG.getVTList(MVT::Other);
13463 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13465 MachineMemOperand *MMO =
13466 DAG.getMachineFunction()
13467 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13468 MachineMemOperand::MOStore, SSFISize, SSFISize);
13470 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13471 Ops, Op.getValueType(), MMO);
13472 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13473 MachinePointerInfo::getFixedStack(SSFI),
13474 false, false, false, 0);
13480 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13481 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13482 SelectionDAG &DAG) const {
13483 // This algorithm is not obvious. Here it is what we're trying to output:
13486 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13487 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13489 haddpd %xmm0, %xmm0
13491 pshufd $0x4e, %xmm0, %xmm1
13497 LLVMContext *Context = DAG.getContext();
13499 // Build some magic constants.
13500 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13501 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13502 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13504 SmallVector<Constant*,2> CV1;
13506 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13507 APInt(64, 0x4330000000000000ULL))));
13509 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13510 APInt(64, 0x4530000000000000ULL))));
13511 Constant *C1 = ConstantVector::get(CV1);
13512 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13514 // Load the 64-bit value into an XMM register.
13515 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13517 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13518 MachinePointerInfo::getConstantPool(),
13519 false, false, false, 16);
13520 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13521 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13524 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13525 MachinePointerInfo::getConstantPool(),
13526 false, false, false, 16);
13527 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13528 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13531 if (Subtarget->hasSSE3()) {
13532 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13533 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13535 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13536 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13538 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13539 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13543 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13544 DAG.getIntPtrConstant(0));
13547 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13548 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13549 SelectionDAG &DAG) const {
13551 // FP constant to bias correct the final result.
13552 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13555 // Load the 32-bit value into an XMM register.
13556 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13559 // Zero out the upper parts of the register.
13560 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13562 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13563 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13564 DAG.getIntPtrConstant(0));
13566 // Or the load with the bias.
13567 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13568 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13569 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13570 MVT::v2f64, Load)),
13571 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13572 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13573 MVT::v2f64, Bias)));
13574 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13575 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13576 DAG.getIntPtrConstant(0));
13578 // Subtract the bias.
13579 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13581 // Handle final rounding.
13582 EVT DestVT = Op.getValueType();
13584 if (DestVT.bitsLT(MVT::f64))
13585 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13586 DAG.getIntPtrConstant(0));
13587 if (DestVT.bitsGT(MVT::f64))
13588 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13590 // Handle final rounding.
13594 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13595 const X86Subtarget &Subtarget) {
13596 // The algorithm is the following:
13597 // #ifdef __SSE4_1__
13598 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13599 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13600 // (uint4) 0x53000000, 0xaa);
13602 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13603 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13605 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13606 // return (float4) lo + fhi;
13609 SDValue V = Op->getOperand(0);
13610 EVT VecIntVT = V.getValueType();
13611 bool Is128 = VecIntVT == MVT::v4i32;
13612 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13613 // If we convert to something else than the supported type, e.g., to v4f64,
13615 if (VecFloatVT != Op->getValueType(0))
13618 unsigned NumElts = VecIntVT.getVectorNumElements();
13619 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13620 "Unsupported custom type");
13621 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13623 // In the #idef/#else code, we have in common:
13624 // - The vector of constants:
13630 // Create the splat vector for 0x4b000000.
13631 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13632 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13633 CstLow, CstLow, CstLow, CstLow};
13634 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13635 makeArrayRef(&CstLowArray[0], NumElts));
13636 // Create the splat vector for 0x53000000.
13637 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13638 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13639 CstHigh, CstHigh, CstHigh, CstHigh};
13640 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13641 makeArrayRef(&CstHighArray[0], NumElts));
13643 // Create the right shift.
13644 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13645 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13646 CstShift, CstShift, CstShift, CstShift};
13647 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13648 makeArrayRef(&CstShiftArray[0], NumElts));
13649 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13652 if (Subtarget.hasSSE41()) {
13653 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13654 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13655 SDValue VecCstLowBitcast =
13656 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13657 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13658 // Low will be bitcasted right away, so do not bother bitcasting back to its
13660 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13661 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13662 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13663 // (uint4) 0x53000000, 0xaa);
13664 SDValue VecCstHighBitcast =
13665 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13666 SDValue VecShiftBitcast =
13667 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13668 // High will be bitcasted right away, so do not bother bitcasting back to
13669 // its original type.
13670 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13671 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13673 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13674 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13675 CstMask, CstMask, CstMask);
13676 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13677 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13678 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13680 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13681 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13684 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13685 SDValue CstFAdd = DAG.getConstantFP(
13686 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13687 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13688 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13689 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13690 makeArrayRef(&CstFAddArray[0], NumElts));
13692 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13693 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13695 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13696 // return (float4) lo + fhi;
13697 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13698 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13701 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13702 SelectionDAG &DAG) const {
13703 SDValue N0 = Op.getOperand(0);
13704 MVT SVT = N0.getSimpleValueType();
13707 switch (SVT.SimpleTy) {
13709 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13714 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13715 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13716 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13720 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13722 llvm_unreachable(nullptr);
13725 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13726 SelectionDAG &DAG) const {
13727 SDValue N0 = Op.getOperand(0);
13730 if (Op.getValueType().isVector())
13731 return lowerUINT_TO_FP_vec(Op, DAG);
13733 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13734 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13735 // the optimization here.
13736 if (DAG.SignBitIsZero(N0))
13737 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13739 MVT SrcVT = N0.getSimpleValueType();
13740 MVT DstVT = Op.getSimpleValueType();
13741 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13742 return LowerUINT_TO_FP_i64(Op, DAG);
13743 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13744 return LowerUINT_TO_FP_i32(Op, DAG);
13745 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13748 // Make a 64-bit buffer, and use it to build an FILD.
13749 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13750 if (SrcVT == MVT::i32) {
13751 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13752 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13753 getPointerTy(), StackSlot, WordOff);
13754 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13755 StackSlot, MachinePointerInfo(),
13757 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13758 OffsetSlot, MachinePointerInfo(),
13760 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13764 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13765 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13766 StackSlot, MachinePointerInfo(),
13768 // For i64 source, we need to add the appropriate power of 2 if the input
13769 // was negative. This is the same as the optimization in
13770 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13771 // we must be careful to do the computation in x87 extended precision, not
13772 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13773 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13774 MachineMemOperand *MMO =
13775 DAG.getMachineFunction()
13776 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13777 MachineMemOperand::MOLoad, 8, 8);
13779 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13780 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13781 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13784 APInt FF(32, 0x5F800000ULL);
13786 // Check whether the sign bit is set.
13787 SDValue SignSet = DAG.getSetCC(dl,
13788 getSetCCResultType(*DAG.getContext(), MVT::i64),
13789 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13792 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13793 SDValue FudgePtr = DAG.getConstantPool(
13794 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13797 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13798 SDValue Zero = DAG.getIntPtrConstant(0);
13799 SDValue Four = DAG.getIntPtrConstant(4);
13800 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13802 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13804 // Load the value out, extending it from f32 to f80.
13805 // FIXME: Avoid the extend by constructing the right constant pool?
13806 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13807 FudgePtr, MachinePointerInfo::getConstantPool(),
13808 MVT::f32, false, false, false, 4);
13809 // Extend everything to 80 bits to force it to be done on x87.
13810 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13811 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13814 std::pair<SDValue,SDValue>
13815 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13816 bool IsSigned, bool IsReplace) const {
13819 EVT DstTy = Op.getValueType();
13821 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13822 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13826 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13827 DstTy.getSimpleVT() >= MVT::i16 &&
13828 "Unknown FP_TO_INT to lower!");
13830 // These are really Legal.
13831 if (DstTy == MVT::i32 &&
13832 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13833 return std::make_pair(SDValue(), SDValue());
13834 if (Subtarget->is64Bit() &&
13835 DstTy == MVT::i64 &&
13836 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13837 return std::make_pair(SDValue(), SDValue());
13839 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13840 // stack slot, or into the FTOL runtime function.
13841 MachineFunction &MF = DAG.getMachineFunction();
13842 unsigned MemSize = DstTy.getSizeInBits()/8;
13843 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13844 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13847 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13848 Opc = X86ISD::WIN_FTOL;
13850 switch (DstTy.getSimpleVT().SimpleTy) {
13851 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13852 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13853 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13854 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13857 SDValue Chain = DAG.getEntryNode();
13858 SDValue Value = Op.getOperand(0);
13859 EVT TheVT = Op.getOperand(0).getValueType();
13860 // FIXME This causes a redundant load/store if the SSE-class value is already
13861 // in memory, such as if it is on the callstack.
13862 if (isScalarFPTypeInSSEReg(TheVT)) {
13863 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13864 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13865 MachinePointerInfo::getFixedStack(SSFI),
13867 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13869 Chain, StackSlot, DAG.getValueType(TheVT)
13872 MachineMemOperand *MMO =
13873 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13874 MachineMemOperand::MOLoad, MemSize, MemSize);
13875 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13876 Chain = Value.getValue(1);
13877 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13878 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13881 MachineMemOperand *MMO =
13882 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13883 MachineMemOperand::MOStore, MemSize, MemSize);
13885 if (Opc != X86ISD::WIN_FTOL) {
13886 // Build the FP_TO_INT*_IN_MEM
13887 SDValue Ops[] = { Chain, Value, StackSlot };
13888 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13890 return std::make_pair(FIST, StackSlot);
13892 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13893 DAG.getVTList(MVT::Other, MVT::Glue),
13895 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13896 MVT::i32, ftol.getValue(1));
13897 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13898 MVT::i32, eax.getValue(2));
13899 SDValue Ops[] = { eax, edx };
13900 SDValue pair = IsReplace
13901 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13902 : DAG.getMergeValues(Ops, DL);
13903 return std::make_pair(pair, SDValue());
13907 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13908 const X86Subtarget *Subtarget) {
13909 MVT VT = Op->getSimpleValueType(0);
13910 SDValue In = Op->getOperand(0);
13911 MVT InVT = In.getSimpleValueType();
13914 // Optimize vectors in AVX mode:
13917 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13918 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13919 // Concat upper and lower parts.
13922 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13923 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13924 // Concat upper and lower parts.
13927 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13928 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13929 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13932 if (Subtarget->hasInt256())
13933 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13935 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13936 SDValue Undef = DAG.getUNDEF(InVT);
13937 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13938 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13939 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13941 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13942 VT.getVectorNumElements()/2);
13944 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13945 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13947 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13950 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13951 SelectionDAG &DAG) {
13952 MVT VT = Op->getSimpleValueType(0);
13953 SDValue In = Op->getOperand(0);
13954 MVT InVT = In.getSimpleValueType();
13956 unsigned int NumElts = VT.getVectorNumElements();
13957 if (NumElts != 8 && NumElts != 16)
13960 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13961 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13963 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13964 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13965 // Now we have only mask extension
13966 assert(InVT.getVectorElementType() == MVT::i1);
13967 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13968 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13969 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13970 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13971 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13972 MachinePointerInfo::getConstantPool(),
13973 false, false, false, Alignment);
13975 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13976 if (VT.is512BitVector())
13978 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13981 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13982 SelectionDAG &DAG) {
13983 if (Subtarget->hasFp256()) {
13984 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13992 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13993 SelectionDAG &DAG) {
13995 MVT VT = Op.getSimpleValueType();
13996 SDValue In = Op.getOperand(0);
13997 MVT SVT = In.getSimpleValueType();
13999 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14000 return LowerZERO_EXTEND_AVX512(Op, DAG);
14002 if (Subtarget->hasFp256()) {
14003 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14008 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14009 VT.getVectorNumElements() != SVT.getVectorNumElements());
14013 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14015 MVT VT = Op.getSimpleValueType();
14016 SDValue In = Op.getOperand(0);
14017 MVT InVT = In.getSimpleValueType();
14019 if (VT == MVT::i1) {
14020 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14021 "Invalid scalar TRUNCATE operation");
14022 if (InVT.getSizeInBits() >= 32)
14024 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14025 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14027 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14028 "Invalid TRUNCATE operation");
14030 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14031 if (VT.getVectorElementType().getSizeInBits() >=8)
14032 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14034 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14035 unsigned NumElts = InVT.getVectorNumElements();
14036 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14037 if (InVT.getSizeInBits() < 512) {
14038 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14039 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14043 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14044 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14045 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14046 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14047 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14048 MachinePointerInfo::getConstantPool(),
14049 false, false, false, Alignment);
14050 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14051 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14052 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14055 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14056 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14057 if (Subtarget->hasInt256()) {
14058 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14059 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14060 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14062 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14063 DAG.getIntPtrConstant(0));
14066 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14067 DAG.getIntPtrConstant(0));
14068 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14069 DAG.getIntPtrConstant(2));
14070 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14071 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14072 static const int ShufMask[] = {0, 2, 4, 6};
14073 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14076 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14077 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14078 if (Subtarget->hasInt256()) {
14079 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14081 SmallVector<SDValue,32> pshufbMask;
14082 for (unsigned i = 0; i < 2; ++i) {
14083 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14084 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14085 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14086 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14087 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14088 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14089 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14090 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14091 for (unsigned j = 0; j < 8; ++j)
14092 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14094 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14095 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14096 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14098 static const int ShufMask[] = {0, 2, -1, -1};
14099 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14101 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14102 DAG.getIntPtrConstant(0));
14103 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14106 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14107 DAG.getIntPtrConstant(0));
14109 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14110 DAG.getIntPtrConstant(4));
14112 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14113 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14115 // The PSHUFB mask:
14116 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14117 -1, -1, -1, -1, -1, -1, -1, -1};
14119 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14120 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14121 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14123 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14124 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14126 // The MOVLHPS Mask:
14127 static const int ShufMask2[] = {0, 1, 4, 5};
14128 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14129 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14132 // Handle truncation of V256 to V128 using shuffles.
14133 if (!VT.is128BitVector() || !InVT.is256BitVector())
14136 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14138 unsigned NumElems = VT.getVectorNumElements();
14139 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14141 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14142 // Prepare truncation shuffle mask
14143 for (unsigned i = 0; i != NumElems; ++i)
14144 MaskVec[i] = i * 2;
14145 SDValue V = DAG.getVectorShuffle(NVT, DL,
14146 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14147 DAG.getUNDEF(NVT), &MaskVec[0]);
14148 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14149 DAG.getIntPtrConstant(0));
14152 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14153 SelectionDAG &DAG) const {
14154 assert(!Op.getSimpleValueType().isVector());
14156 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14157 /*IsSigned=*/ true, /*IsReplace=*/ false);
14158 SDValue FIST = Vals.first, StackSlot = Vals.second;
14159 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14160 if (!FIST.getNode()) return Op;
14162 if (StackSlot.getNode())
14163 // Load the result.
14164 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14165 FIST, StackSlot, MachinePointerInfo(),
14166 false, false, false, 0);
14168 // The node is the result.
14172 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14173 SelectionDAG &DAG) const {
14174 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14175 /*IsSigned=*/ false, /*IsReplace=*/ false);
14176 SDValue FIST = Vals.first, StackSlot = Vals.second;
14177 assert(FIST.getNode() && "Unexpected failure");
14179 if (StackSlot.getNode())
14180 // Load the result.
14181 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14182 FIST, StackSlot, MachinePointerInfo(),
14183 false, false, false, 0);
14185 // The node is the result.
14189 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14191 MVT VT = Op.getSimpleValueType();
14192 SDValue In = Op.getOperand(0);
14193 MVT SVT = In.getSimpleValueType();
14195 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14197 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14198 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14199 In, DAG.getUNDEF(SVT)));
14202 /// The only differences between FABS and FNEG are the mask and the logic op.
14203 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14204 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14205 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14206 "Wrong opcode for lowering FABS or FNEG.");
14208 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14210 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14211 // into an FNABS. We'll lower the FABS after that if it is still in use.
14213 for (SDNode *User : Op->uses())
14214 if (User->getOpcode() == ISD::FNEG)
14217 SDValue Op0 = Op.getOperand(0);
14218 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14221 MVT VT = Op.getSimpleValueType();
14222 // Assume scalar op for initialization; update for vector if needed.
14223 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14224 // generate a 16-byte vector constant and logic op even for the scalar case.
14225 // Using a 16-byte mask allows folding the load of the mask with
14226 // the logic op, so it can save (~4 bytes) on code size.
14228 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14229 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14230 // decide if we should generate a 16-byte constant mask when we only need 4 or
14231 // 8 bytes for the scalar case.
14232 if (VT.isVector()) {
14233 EltVT = VT.getVectorElementType();
14234 NumElts = VT.getVectorNumElements();
14237 unsigned EltBits = EltVT.getSizeInBits();
14238 LLVMContext *Context = DAG.getContext();
14239 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14241 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14242 Constant *C = ConstantInt::get(*Context, MaskElt);
14243 C = ConstantVector::getSplat(NumElts, C);
14244 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14245 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14246 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14247 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14248 MachinePointerInfo::getConstantPool(),
14249 false, false, false, Alignment);
14251 if (VT.isVector()) {
14252 // For a vector, cast operands to a vector type, perform the logic op,
14253 // and cast the result back to the original value type.
14254 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14255 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14256 SDValue Operand = IsFNABS ?
14257 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14258 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14259 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14260 return DAG.getNode(ISD::BITCAST, dl, VT,
14261 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14264 // If not vector, then scalar.
14265 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14266 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14267 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14270 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14271 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14272 LLVMContext *Context = DAG.getContext();
14273 SDValue Op0 = Op.getOperand(0);
14274 SDValue Op1 = Op.getOperand(1);
14276 MVT VT = Op.getSimpleValueType();
14277 MVT SrcVT = Op1.getSimpleValueType();
14279 // If second operand is smaller, extend it first.
14280 if (SrcVT.bitsLT(VT)) {
14281 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14284 // And if it is bigger, shrink it first.
14285 if (SrcVT.bitsGT(VT)) {
14286 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14290 // At this point the operands and the result should have the same
14291 // type, and that won't be f80 since that is not custom lowered.
14293 // First get the sign bit of second operand.
14294 SmallVector<Constant*,4> CV;
14295 if (SrcVT == MVT::f64) {
14296 const fltSemantics &Sem = APFloat::IEEEdouble;
14297 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14298 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14300 const fltSemantics &Sem = APFloat::IEEEsingle;
14301 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14302 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14303 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14304 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14306 Constant *C = ConstantVector::get(CV);
14307 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14308 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14309 MachinePointerInfo::getConstantPool(),
14310 false, false, false, 16);
14311 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14313 // Shift sign bit right or left if the two operands have different types.
14314 if (SrcVT.bitsGT(VT)) {
14315 // Op0 is MVT::f32, Op1 is MVT::f64.
14316 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14317 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14318 DAG.getConstant(32, MVT::i32));
14319 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14320 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14321 DAG.getIntPtrConstant(0));
14324 // Clear first operand sign bit.
14326 if (VT == MVT::f64) {
14327 const fltSemantics &Sem = APFloat::IEEEdouble;
14328 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14329 APInt(64, ~(1ULL << 63)))));
14330 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14332 const fltSemantics &Sem = APFloat::IEEEsingle;
14333 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14334 APInt(32, ~(1U << 31)))));
14335 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14336 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14337 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14339 C = ConstantVector::get(CV);
14340 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14341 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14342 MachinePointerInfo::getConstantPool(),
14343 false, false, false, 16);
14344 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14346 // Or the value with the sign bit.
14347 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14350 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14351 SDValue N0 = Op.getOperand(0);
14353 MVT VT = Op.getSimpleValueType();
14355 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14356 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14357 DAG.getConstant(1, VT));
14358 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14361 // Check whether an OR'd tree is PTEST-able.
14362 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14363 SelectionDAG &DAG) {
14364 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14366 if (!Subtarget->hasSSE41())
14369 if (!Op->hasOneUse())
14372 SDNode *N = Op.getNode();
14375 SmallVector<SDValue, 8> Opnds;
14376 DenseMap<SDValue, unsigned> VecInMap;
14377 SmallVector<SDValue, 8> VecIns;
14378 EVT VT = MVT::Other;
14380 // Recognize a special case where a vector is casted into wide integer to
14382 Opnds.push_back(N->getOperand(0));
14383 Opnds.push_back(N->getOperand(1));
14385 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14386 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14387 // BFS traverse all OR'd operands.
14388 if (I->getOpcode() == ISD::OR) {
14389 Opnds.push_back(I->getOperand(0));
14390 Opnds.push_back(I->getOperand(1));
14391 // Re-evaluate the number of nodes to be traversed.
14392 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14396 // Quit if a non-EXTRACT_VECTOR_ELT
14397 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14400 // Quit if without a constant index.
14401 SDValue Idx = I->getOperand(1);
14402 if (!isa<ConstantSDNode>(Idx))
14405 SDValue ExtractedFromVec = I->getOperand(0);
14406 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14407 if (M == VecInMap.end()) {
14408 VT = ExtractedFromVec.getValueType();
14409 // Quit if not 128/256-bit vector.
14410 if (!VT.is128BitVector() && !VT.is256BitVector())
14412 // Quit if not the same type.
14413 if (VecInMap.begin() != VecInMap.end() &&
14414 VT != VecInMap.begin()->first.getValueType())
14416 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14417 VecIns.push_back(ExtractedFromVec);
14419 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14422 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14423 "Not extracted from 128-/256-bit vector.");
14425 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14427 for (DenseMap<SDValue, unsigned>::const_iterator
14428 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14429 // Quit if not all elements are used.
14430 if (I->second != FullMask)
14434 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14436 // Cast all vectors into TestVT for PTEST.
14437 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14438 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14440 // If more than one full vectors are evaluated, OR them first before PTEST.
14441 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14442 // Each iteration will OR 2 nodes and append the result until there is only
14443 // 1 node left, i.e. the final OR'd value of all vectors.
14444 SDValue LHS = VecIns[Slot];
14445 SDValue RHS = VecIns[Slot + 1];
14446 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14449 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14450 VecIns.back(), VecIns.back());
14453 /// \brief return true if \c Op has a use that doesn't just read flags.
14454 static bool hasNonFlagsUse(SDValue Op) {
14455 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14457 SDNode *User = *UI;
14458 unsigned UOpNo = UI.getOperandNo();
14459 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14460 // Look pass truncate.
14461 UOpNo = User->use_begin().getOperandNo();
14462 User = *User->use_begin();
14465 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14466 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14472 /// Emit nodes that will be selected as "test Op0,Op0", or something
14474 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14475 SelectionDAG &DAG) const {
14476 if (Op.getValueType() == MVT::i1)
14477 // KORTEST instruction should be selected
14478 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14479 DAG.getConstant(0, Op.getValueType()));
14481 // CF and OF aren't always set the way we want. Determine which
14482 // of these we need.
14483 bool NeedCF = false;
14484 bool NeedOF = false;
14487 case X86::COND_A: case X86::COND_AE:
14488 case X86::COND_B: case X86::COND_BE:
14491 case X86::COND_G: case X86::COND_GE:
14492 case X86::COND_L: case X86::COND_LE:
14493 case X86::COND_O: case X86::COND_NO: {
14494 // Check if we really need to set the
14495 // Overflow flag. If NoSignedWrap is present
14496 // that is not actually needed.
14497 switch (Op->getOpcode()) {
14502 const BinaryWithFlagsSDNode *BinNode =
14503 cast<BinaryWithFlagsSDNode>(Op.getNode());
14504 if (BinNode->hasNoSignedWrap())
14514 // See if we can use the EFLAGS value from the operand instead of
14515 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14516 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14517 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14518 // Emit a CMP with 0, which is the TEST pattern.
14519 //if (Op.getValueType() == MVT::i1)
14520 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14521 // DAG.getConstant(0, MVT::i1));
14522 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14523 DAG.getConstant(0, Op.getValueType()));
14525 unsigned Opcode = 0;
14526 unsigned NumOperands = 0;
14528 // Truncate operations may prevent the merge of the SETCC instruction
14529 // and the arithmetic instruction before it. Attempt to truncate the operands
14530 // of the arithmetic instruction and use a reduced bit-width instruction.
14531 bool NeedTruncation = false;
14532 SDValue ArithOp = Op;
14533 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14534 SDValue Arith = Op->getOperand(0);
14535 // Both the trunc and the arithmetic op need to have one user each.
14536 if (Arith->hasOneUse())
14537 switch (Arith.getOpcode()) {
14544 NeedTruncation = true;
14550 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14551 // which may be the result of a CAST. We use the variable 'Op', which is the
14552 // non-casted variable when we check for possible users.
14553 switch (ArithOp.getOpcode()) {
14555 // Due to an isel shortcoming, be conservative if this add is likely to be
14556 // selected as part of a load-modify-store instruction. When the root node
14557 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14558 // uses of other nodes in the match, such as the ADD in this case. This
14559 // leads to the ADD being left around and reselected, with the result being
14560 // two adds in the output. Alas, even if none our users are stores, that
14561 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14562 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14563 // climbing the DAG back to the root, and it doesn't seem to be worth the
14565 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14566 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14567 if (UI->getOpcode() != ISD::CopyToReg &&
14568 UI->getOpcode() != ISD::SETCC &&
14569 UI->getOpcode() != ISD::STORE)
14572 if (ConstantSDNode *C =
14573 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14574 // An add of one will be selected as an INC.
14575 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14576 Opcode = X86ISD::INC;
14581 // An add of negative one (subtract of one) will be selected as a DEC.
14582 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14583 Opcode = X86ISD::DEC;
14589 // Otherwise use a regular EFLAGS-setting add.
14590 Opcode = X86ISD::ADD;
14595 // If we have a constant logical shift that's only used in a comparison
14596 // against zero turn it into an equivalent AND. This allows turning it into
14597 // a TEST instruction later.
14598 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14599 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14600 EVT VT = Op.getValueType();
14601 unsigned BitWidth = VT.getSizeInBits();
14602 unsigned ShAmt = Op->getConstantOperandVal(1);
14603 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14605 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14606 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14607 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14608 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14610 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14611 DAG.getConstant(Mask, VT));
14612 DAG.ReplaceAllUsesWith(Op, New);
14618 // If the primary and result isn't used, don't bother using X86ISD::AND,
14619 // because a TEST instruction will be better.
14620 if (!hasNonFlagsUse(Op))
14626 // Due to the ISEL shortcoming noted above, be conservative if this op is
14627 // likely to be selected as part of a load-modify-store instruction.
14628 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14629 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14630 if (UI->getOpcode() == ISD::STORE)
14633 // Otherwise use a regular EFLAGS-setting instruction.
14634 switch (ArithOp.getOpcode()) {
14635 default: llvm_unreachable("unexpected operator!");
14636 case ISD::SUB: Opcode = X86ISD::SUB; break;
14637 case ISD::XOR: Opcode = X86ISD::XOR; break;
14638 case ISD::AND: Opcode = X86ISD::AND; break;
14640 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14641 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14642 if (EFLAGS.getNode())
14645 Opcode = X86ISD::OR;
14659 return SDValue(Op.getNode(), 1);
14665 // If we found that truncation is beneficial, perform the truncation and
14667 if (NeedTruncation) {
14668 EVT VT = Op.getValueType();
14669 SDValue WideVal = Op->getOperand(0);
14670 EVT WideVT = WideVal.getValueType();
14671 unsigned ConvertedOp = 0;
14672 // Use a target machine opcode to prevent further DAGCombine
14673 // optimizations that may separate the arithmetic operations
14674 // from the setcc node.
14675 switch (WideVal.getOpcode()) {
14677 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14678 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14679 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14680 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14681 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14685 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14686 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14687 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14688 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14689 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14695 // Emit a CMP with 0, which is the TEST pattern.
14696 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14697 DAG.getConstant(0, Op.getValueType()));
14699 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14700 SmallVector<SDValue, 4> Ops;
14701 for (unsigned i = 0; i != NumOperands; ++i)
14702 Ops.push_back(Op.getOperand(i));
14704 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14705 DAG.ReplaceAllUsesWith(Op, New);
14706 return SDValue(New.getNode(), 1);
14709 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14711 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14712 SDLoc dl, SelectionDAG &DAG) const {
14713 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14714 if (C->getAPIntValue() == 0)
14715 return EmitTest(Op0, X86CC, dl, DAG);
14717 if (Op0.getValueType() == MVT::i1)
14718 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14721 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14722 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14723 // Do the comparison at i32 if it's smaller, besides the Atom case.
14724 // This avoids subregister aliasing issues. Keep the smaller reference
14725 // if we're optimizing for size, however, as that'll allow better folding
14726 // of memory operations.
14727 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14728 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14729 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14730 !Subtarget->isAtom()) {
14731 unsigned ExtendOp =
14732 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14733 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14734 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14736 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14737 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14738 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14740 return SDValue(Sub.getNode(), 1);
14742 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14745 /// Convert a comparison if required by the subtarget.
14746 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14747 SelectionDAG &DAG) const {
14748 // If the subtarget does not support the FUCOMI instruction, floating-point
14749 // comparisons have to be converted.
14750 if (Subtarget->hasCMov() ||
14751 Cmp.getOpcode() != X86ISD::CMP ||
14752 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14753 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14756 // The instruction selector will select an FUCOM instruction instead of
14757 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14758 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14759 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14761 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14762 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14763 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14764 DAG.getConstant(8, MVT::i8));
14765 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14766 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14769 /// The minimum architected relative accuracy is 2^-12. We need one
14770 /// Newton-Raphson step to have a good float result (24 bits of precision).
14771 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14772 DAGCombinerInfo &DCI,
14773 unsigned &RefinementSteps,
14774 bool &UseOneConstNR) const {
14775 // FIXME: We should use instruction latency models to calculate the cost of
14776 // each potential sequence, but this is very hard to do reliably because
14777 // at least Intel's Core* chips have variable timing based on the number of
14778 // significant digits in the divisor and/or sqrt operand.
14779 if (!Subtarget->useSqrtEst())
14782 EVT VT = Op.getValueType();
14784 // SSE1 has rsqrtss and rsqrtps.
14785 // TODO: Add support for AVX512 (v16f32).
14786 // It is likely not profitable to do this for f64 because a double-precision
14787 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14788 // instructions: convert to single, rsqrtss, convert back to double, refine
14789 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14790 // along with FMA, this could be a throughput win.
14791 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14792 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14793 RefinementSteps = 1;
14794 UseOneConstNR = false;
14795 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14800 /// The minimum architected relative accuracy is 2^-12. We need one
14801 /// Newton-Raphson step to have a good float result (24 bits of precision).
14802 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14803 DAGCombinerInfo &DCI,
14804 unsigned &RefinementSteps) const {
14805 // FIXME: We should use instruction latency models to calculate the cost of
14806 // each potential sequence, but this is very hard to do reliably because
14807 // at least Intel's Core* chips have variable timing based on the number of
14808 // significant digits in the divisor.
14809 if (!Subtarget->useReciprocalEst())
14812 EVT VT = Op.getValueType();
14814 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14815 // TODO: Add support for AVX512 (v16f32).
14816 // It is likely not profitable to do this for f64 because a double-precision
14817 // reciprocal estimate with refinement on x86 prior to FMA requires
14818 // 15 instructions: convert to single, rcpss, convert back to double, refine
14819 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14820 // along with FMA, this could be a throughput win.
14821 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14822 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14823 RefinementSteps = ReciprocalEstimateRefinementSteps;
14824 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14829 static bool isAllOnes(SDValue V) {
14830 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14831 return C && C->isAllOnesValue();
14834 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14835 /// if it's possible.
14836 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14837 SDLoc dl, SelectionDAG &DAG) const {
14838 SDValue Op0 = And.getOperand(0);
14839 SDValue Op1 = And.getOperand(1);
14840 if (Op0.getOpcode() == ISD::TRUNCATE)
14841 Op0 = Op0.getOperand(0);
14842 if (Op1.getOpcode() == ISD::TRUNCATE)
14843 Op1 = Op1.getOperand(0);
14846 if (Op1.getOpcode() == ISD::SHL)
14847 std::swap(Op0, Op1);
14848 if (Op0.getOpcode() == ISD::SHL) {
14849 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14850 if (And00C->getZExtValue() == 1) {
14851 // If we looked past a truncate, check that it's only truncating away
14853 unsigned BitWidth = Op0.getValueSizeInBits();
14854 unsigned AndBitWidth = And.getValueSizeInBits();
14855 if (BitWidth > AndBitWidth) {
14857 DAG.computeKnownBits(Op0, Zeros, Ones);
14858 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14862 RHS = Op0.getOperand(1);
14864 } else if (Op1.getOpcode() == ISD::Constant) {
14865 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14866 uint64_t AndRHSVal = AndRHS->getZExtValue();
14867 SDValue AndLHS = Op0;
14869 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14870 LHS = AndLHS.getOperand(0);
14871 RHS = AndLHS.getOperand(1);
14874 // Use BT if the immediate can't be encoded in a TEST instruction.
14875 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14877 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14881 if (LHS.getNode()) {
14882 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14883 // instruction. Since the shift amount is in-range-or-undefined, we know
14884 // that doing a bittest on the i32 value is ok. We extend to i32 because
14885 // the encoding for the i16 version is larger than the i32 version.
14886 // Also promote i16 to i32 for performance / code size reason.
14887 if (LHS.getValueType() == MVT::i8 ||
14888 LHS.getValueType() == MVT::i16)
14889 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14891 // If the operand types disagree, extend the shift amount to match. Since
14892 // BT ignores high bits (like shifts) we can use anyextend.
14893 if (LHS.getValueType() != RHS.getValueType())
14894 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14896 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14897 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14898 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14899 DAG.getConstant(Cond, MVT::i8), BT);
14905 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14907 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14912 // SSE Condition code mapping:
14921 switch (SetCCOpcode) {
14922 default: llvm_unreachable("Unexpected SETCC condition");
14924 case ISD::SETEQ: SSECC = 0; break;
14926 case ISD::SETGT: Swap = true; // Fallthrough
14928 case ISD::SETOLT: SSECC = 1; break;
14930 case ISD::SETGE: Swap = true; // Fallthrough
14932 case ISD::SETOLE: SSECC = 2; break;
14933 case ISD::SETUO: SSECC = 3; break;
14935 case ISD::SETNE: SSECC = 4; break;
14936 case ISD::SETULE: Swap = true; // Fallthrough
14937 case ISD::SETUGE: SSECC = 5; break;
14938 case ISD::SETULT: Swap = true; // Fallthrough
14939 case ISD::SETUGT: SSECC = 6; break;
14940 case ISD::SETO: SSECC = 7; break;
14942 case ISD::SETONE: SSECC = 8; break;
14945 std::swap(Op0, Op1);
14950 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14951 // ones, and then concatenate the result back.
14952 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14953 MVT VT = Op.getSimpleValueType();
14955 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14956 "Unsupported value type for operation");
14958 unsigned NumElems = VT.getVectorNumElements();
14960 SDValue CC = Op.getOperand(2);
14962 // Extract the LHS vectors
14963 SDValue LHS = Op.getOperand(0);
14964 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14965 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14967 // Extract the RHS vectors
14968 SDValue RHS = Op.getOperand(1);
14969 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14970 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14972 // Issue the operation on the smaller types and concatenate the result back
14973 MVT EltVT = VT.getVectorElementType();
14974 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14975 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14976 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14977 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14980 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14981 const X86Subtarget *Subtarget) {
14982 SDValue Op0 = Op.getOperand(0);
14983 SDValue Op1 = Op.getOperand(1);
14984 SDValue CC = Op.getOperand(2);
14985 MVT VT = Op.getSimpleValueType();
14988 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14989 Op.getValueType().getScalarType() == MVT::i1 &&
14990 "Cannot set masked compare for this operation");
14992 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14994 bool Unsigned = false;
14997 switch (SetCCOpcode) {
14998 default: llvm_unreachable("Unexpected SETCC condition");
14999 case ISD::SETNE: SSECC = 4; break;
15000 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15001 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15002 case ISD::SETLT: Swap = true; //fall-through
15003 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15004 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15005 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15006 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15007 case ISD::SETULE: Unsigned = true; //fall-through
15008 case ISD::SETLE: SSECC = 2; break;
15012 std::swap(Op0, Op1);
15014 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15015 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15016 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15017 DAG.getConstant(SSECC, MVT::i8));
15020 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15021 /// operand \p Op1. If non-trivial (for example because it's not constant)
15022 /// return an empty value.
15023 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15025 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15029 MVT VT = Op1.getSimpleValueType();
15030 MVT EVT = VT.getVectorElementType();
15031 unsigned n = VT.getVectorNumElements();
15032 SmallVector<SDValue, 8> ULTOp1;
15034 for (unsigned i = 0; i < n; ++i) {
15035 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15036 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15039 // Avoid underflow.
15040 APInt Val = Elt->getAPIntValue();
15044 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15047 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15050 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15051 SelectionDAG &DAG) {
15052 SDValue Op0 = Op.getOperand(0);
15053 SDValue Op1 = Op.getOperand(1);
15054 SDValue CC = Op.getOperand(2);
15055 MVT VT = Op.getSimpleValueType();
15056 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15057 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15062 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15063 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15066 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15067 unsigned Opc = X86ISD::CMPP;
15068 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15069 assert(VT.getVectorNumElements() <= 16);
15070 Opc = X86ISD::CMPM;
15072 // In the two special cases we can't handle, emit two comparisons.
15075 unsigned CombineOpc;
15076 if (SetCCOpcode == ISD::SETUEQ) {
15077 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15079 assert(SetCCOpcode == ISD::SETONE);
15080 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15083 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15084 DAG.getConstant(CC0, MVT::i8));
15085 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15086 DAG.getConstant(CC1, MVT::i8));
15087 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15089 // Handle all other FP comparisons here.
15090 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15091 DAG.getConstant(SSECC, MVT::i8));
15094 // Break 256-bit integer vector compare into smaller ones.
15095 if (VT.is256BitVector() && !Subtarget->hasInt256())
15096 return Lower256IntVSETCC(Op, DAG);
15098 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15099 EVT OpVT = Op1.getValueType();
15100 if (Subtarget->hasAVX512()) {
15101 if (Op1.getValueType().is512BitVector() ||
15102 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15103 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15104 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15106 // In AVX-512 architecture setcc returns mask with i1 elements,
15107 // But there is no compare instruction for i8 and i16 elements in KNL.
15108 // We are not talking about 512-bit operands in this case, these
15109 // types are illegal.
15111 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15112 OpVT.getVectorElementType().getSizeInBits() >= 8))
15113 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15114 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15117 // We are handling one of the integer comparisons here. Since SSE only has
15118 // GT and EQ comparisons for integer, swapping operands and multiple
15119 // operations may be required for some comparisons.
15121 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15122 bool Subus = false;
15124 switch (SetCCOpcode) {
15125 default: llvm_unreachable("Unexpected SETCC condition");
15126 case ISD::SETNE: Invert = true;
15127 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15128 case ISD::SETLT: Swap = true;
15129 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15130 case ISD::SETGE: Swap = true;
15131 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15132 Invert = true; break;
15133 case ISD::SETULT: Swap = true;
15134 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15135 FlipSigns = true; break;
15136 case ISD::SETUGE: Swap = true;
15137 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15138 FlipSigns = true; Invert = true; break;
15141 // Special case: Use min/max operations for SETULE/SETUGE
15142 MVT VET = VT.getVectorElementType();
15144 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15145 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15148 switch (SetCCOpcode) {
15150 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15151 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15154 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15157 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15158 if (!MinMax && hasSubus) {
15159 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15161 // t = psubus Op0, Op1
15162 // pcmpeq t, <0..0>
15163 switch (SetCCOpcode) {
15165 case ISD::SETULT: {
15166 // If the comparison is against a constant we can turn this into a
15167 // setule. With psubus, setule does not require a swap. This is
15168 // beneficial because the constant in the register is no longer
15169 // destructed as the destination so it can be hoisted out of a loop.
15170 // Only do this pre-AVX since vpcmp* is no longer destructive.
15171 if (Subtarget->hasAVX())
15173 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15174 if (ULEOp1.getNode()) {
15176 Subus = true; Invert = false; Swap = false;
15180 // Psubus is better than flip-sign because it requires no inversion.
15181 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15182 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15186 Opc = X86ISD::SUBUS;
15192 std::swap(Op0, Op1);
15194 // Check that the operation in question is available (most are plain SSE2,
15195 // but PCMPGTQ and PCMPEQQ have different requirements).
15196 if (VT == MVT::v2i64) {
15197 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15198 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15200 // First cast everything to the right type.
15201 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15202 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15204 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15205 // bits of the inputs before performing those operations. The lower
15206 // compare is always unsigned.
15209 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15211 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15212 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15213 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15214 Sign, Zero, Sign, Zero);
15216 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15217 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15219 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15220 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15221 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15223 // Create masks for only the low parts/high parts of the 64 bit integers.
15224 static const int MaskHi[] = { 1, 1, 3, 3 };
15225 static const int MaskLo[] = { 0, 0, 2, 2 };
15226 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15227 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15228 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15230 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15231 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15234 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15236 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15239 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15240 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15241 // pcmpeqd + pshufd + pand.
15242 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15244 // First cast everything to the right type.
15245 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15246 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15249 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15251 // Make sure the lower and upper halves are both all-ones.
15252 static const int Mask[] = { 1, 0, 3, 2 };
15253 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15254 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15257 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15259 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15263 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15264 // bits of the inputs before performing those operations.
15266 EVT EltVT = VT.getVectorElementType();
15267 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15268 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15269 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15272 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15274 // If the logical-not of the result is required, perform that now.
15276 Result = DAG.getNOT(dl, Result, VT);
15279 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15282 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15283 getZeroVector(VT, Subtarget, DAG, dl));
15288 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15290 MVT VT = Op.getSimpleValueType();
15292 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15294 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15295 && "SetCC type must be 8-bit or 1-bit integer");
15296 SDValue Op0 = Op.getOperand(0);
15297 SDValue Op1 = Op.getOperand(1);
15299 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15301 // Optimize to BT if possible.
15302 // Lower (X & (1 << N)) == 0 to BT(X, N).
15303 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15304 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15305 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15306 Op1.getOpcode() == ISD::Constant &&
15307 cast<ConstantSDNode>(Op1)->isNullValue() &&
15308 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15309 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15310 if (NewSetCC.getNode())
15314 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15316 if (Op1.getOpcode() == ISD::Constant &&
15317 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15318 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15319 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15321 // If the input is a setcc, then reuse the input setcc or use a new one with
15322 // the inverted condition.
15323 if (Op0.getOpcode() == X86ISD::SETCC) {
15324 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15325 bool Invert = (CC == ISD::SETNE) ^
15326 cast<ConstantSDNode>(Op1)->isNullValue();
15330 CCode = X86::GetOppositeBranchCondition(CCode);
15331 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15332 DAG.getConstant(CCode, MVT::i8),
15333 Op0.getOperand(1));
15335 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15339 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15340 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15341 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15343 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15344 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15347 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15348 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15349 if (X86CC == X86::COND_INVALID)
15352 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15353 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15354 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15355 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15357 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15361 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15362 static bool isX86LogicalCmp(SDValue Op) {
15363 unsigned Opc = Op.getNode()->getOpcode();
15364 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15365 Opc == X86ISD::SAHF)
15367 if (Op.getResNo() == 1 &&
15368 (Opc == X86ISD::ADD ||
15369 Opc == X86ISD::SUB ||
15370 Opc == X86ISD::ADC ||
15371 Opc == X86ISD::SBB ||
15372 Opc == X86ISD::SMUL ||
15373 Opc == X86ISD::UMUL ||
15374 Opc == X86ISD::INC ||
15375 Opc == X86ISD::DEC ||
15376 Opc == X86ISD::OR ||
15377 Opc == X86ISD::XOR ||
15378 Opc == X86ISD::AND))
15381 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15387 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15388 if (V.getOpcode() != ISD::TRUNCATE)
15391 SDValue VOp0 = V.getOperand(0);
15392 unsigned InBits = VOp0.getValueSizeInBits();
15393 unsigned Bits = V.getValueSizeInBits();
15394 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15397 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15398 bool addTest = true;
15399 SDValue Cond = Op.getOperand(0);
15400 SDValue Op1 = Op.getOperand(1);
15401 SDValue Op2 = Op.getOperand(2);
15403 EVT VT = Op1.getValueType();
15406 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15407 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15408 // sequence later on.
15409 if (Cond.getOpcode() == ISD::SETCC &&
15410 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15411 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15412 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15413 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15414 int SSECC = translateX86FSETCC(
15415 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15418 if (Subtarget->hasAVX512()) {
15419 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15420 DAG.getConstant(SSECC, MVT::i8));
15421 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15423 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15424 DAG.getConstant(SSECC, MVT::i8));
15425 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15426 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15427 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15431 if (Cond.getOpcode() == ISD::SETCC) {
15432 SDValue NewCond = LowerSETCC(Cond, DAG);
15433 if (NewCond.getNode())
15437 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15438 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15439 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15440 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15441 if (Cond.getOpcode() == X86ISD::SETCC &&
15442 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15443 isZero(Cond.getOperand(1).getOperand(1))) {
15444 SDValue Cmp = Cond.getOperand(1);
15446 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15448 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15449 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15450 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15452 SDValue CmpOp0 = Cmp.getOperand(0);
15453 // Apply further optimizations for special cases
15454 // (select (x != 0), -1, 0) -> neg & sbb
15455 // (select (x == 0), 0, -1) -> neg & sbb
15456 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15457 if (YC->isNullValue() &&
15458 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15459 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15460 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15461 DAG.getConstant(0, CmpOp0.getValueType()),
15463 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15464 DAG.getConstant(X86::COND_B, MVT::i8),
15465 SDValue(Neg.getNode(), 1));
15469 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15470 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15471 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15473 SDValue Res = // Res = 0 or -1.
15474 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15475 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15477 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15478 Res = DAG.getNOT(DL, Res, Res.getValueType());
15480 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15481 if (!N2C || !N2C->isNullValue())
15482 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15487 // Look past (and (setcc_carry (cmp ...)), 1).
15488 if (Cond.getOpcode() == ISD::AND &&
15489 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15490 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15491 if (C && C->getAPIntValue() == 1)
15492 Cond = Cond.getOperand(0);
15495 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15496 // setting operand in place of the X86ISD::SETCC.
15497 unsigned CondOpcode = Cond.getOpcode();
15498 if (CondOpcode == X86ISD::SETCC ||
15499 CondOpcode == X86ISD::SETCC_CARRY) {
15500 CC = Cond.getOperand(0);
15502 SDValue Cmp = Cond.getOperand(1);
15503 unsigned Opc = Cmp.getOpcode();
15504 MVT VT = Op.getSimpleValueType();
15506 bool IllegalFPCMov = false;
15507 if (VT.isFloatingPoint() && !VT.isVector() &&
15508 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15509 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15511 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15512 Opc == X86ISD::BT) { // FIXME
15516 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15517 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15518 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15519 Cond.getOperand(0).getValueType() != MVT::i8)) {
15520 SDValue LHS = Cond.getOperand(0);
15521 SDValue RHS = Cond.getOperand(1);
15522 unsigned X86Opcode;
15525 switch (CondOpcode) {
15526 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15527 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15528 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15529 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15530 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15531 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15532 default: llvm_unreachable("unexpected overflowing operator");
15534 if (CondOpcode == ISD::UMULO)
15535 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15538 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15540 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15542 if (CondOpcode == ISD::UMULO)
15543 Cond = X86Op.getValue(2);
15545 Cond = X86Op.getValue(1);
15547 CC = DAG.getConstant(X86Cond, MVT::i8);
15552 // Look pass the truncate if the high bits are known zero.
15553 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15554 Cond = Cond.getOperand(0);
15556 // We know the result of AND is compared against zero. Try to match
15558 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15559 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15560 if (NewSetCC.getNode()) {
15561 CC = NewSetCC.getOperand(0);
15562 Cond = NewSetCC.getOperand(1);
15569 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15570 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15573 // a < b ? -1 : 0 -> RES = ~setcc_carry
15574 // a < b ? 0 : -1 -> RES = setcc_carry
15575 // a >= b ? -1 : 0 -> RES = setcc_carry
15576 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15577 if (Cond.getOpcode() == X86ISD::SUB) {
15578 Cond = ConvertCmpIfNecessary(Cond, DAG);
15579 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15581 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15582 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15583 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15584 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15585 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15586 return DAG.getNOT(DL, Res, Res.getValueType());
15591 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15592 // widen the cmov and push the truncate through. This avoids introducing a new
15593 // branch during isel and doesn't add any extensions.
15594 if (Op.getValueType() == MVT::i8 &&
15595 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15596 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15597 if (T1.getValueType() == T2.getValueType() &&
15598 // Blacklist CopyFromReg to avoid partial register stalls.
15599 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15600 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15601 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15602 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15606 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15607 // condition is true.
15608 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15609 SDValue Ops[] = { Op2, Op1, CC, Cond };
15610 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15613 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15614 SelectionDAG &DAG) {
15615 MVT VT = Op->getSimpleValueType(0);
15616 SDValue In = Op->getOperand(0);
15617 MVT InVT = In.getSimpleValueType();
15618 MVT VTElt = VT.getVectorElementType();
15619 MVT InVTElt = InVT.getVectorElementType();
15623 if ((InVTElt == MVT::i1) &&
15624 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15625 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15627 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15628 VTElt.getSizeInBits() <= 16)) ||
15630 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15631 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15633 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15634 VTElt.getSizeInBits() >= 32))))
15635 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15637 unsigned int NumElts = VT.getVectorNumElements();
15639 if (NumElts != 8 && NumElts != 16)
15642 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15643 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15644 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15645 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15648 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15649 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15651 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15652 Constant *C = ConstantInt::get(*DAG.getContext(),
15653 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15655 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15656 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15657 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15658 MachinePointerInfo::getConstantPool(),
15659 false, false, false, Alignment);
15660 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15661 if (VT.is512BitVector())
15663 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15666 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15667 SelectionDAG &DAG) {
15668 MVT VT = Op->getSimpleValueType(0);
15669 SDValue In = Op->getOperand(0);
15670 MVT InVT = In.getSimpleValueType();
15673 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15674 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15676 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15677 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15678 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15681 if (Subtarget->hasInt256())
15682 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15684 // Optimize vectors in AVX mode
15685 // Sign extend v8i16 to v8i32 and
15688 // Divide input vector into two parts
15689 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15690 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15691 // concat the vectors to original VT
15693 unsigned NumElems = InVT.getVectorNumElements();
15694 SDValue Undef = DAG.getUNDEF(InVT);
15696 SmallVector<int,8> ShufMask1(NumElems, -1);
15697 for (unsigned i = 0; i != NumElems/2; ++i)
15700 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15702 SmallVector<int,8> ShufMask2(NumElems, -1);
15703 for (unsigned i = 0; i != NumElems/2; ++i)
15704 ShufMask2[i] = i + NumElems/2;
15706 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15708 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15709 VT.getVectorNumElements()/2);
15711 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15712 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15714 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15717 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15718 // may emit an illegal shuffle but the expansion is still better than scalar
15719 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15720 // we'll emit a shuffle and a arithmetic shift.
15721 // TODO: It is possible to support ZExt by zeroing the undef values during
15722 // the shuffle phase or after the shuffle.
15723 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15724 SelectionDAG &DAG) {
15725 MVT RegVT = Op.getSimpleValueType();
15726 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15727 assert(RegVT.isInteger() &&
15728 "We only custom lower integer vector sext loads.");
15730 // Nothing useful we can do without SSE2 shuffles.
15731 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15733 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15735 EVT MemVT = Ld->getMemoryVT();
15736 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15737 unsigned RegSz = RegVT.getSizeInBits();
15739 ISD::LoadExtType Ext = Ld->getExtensionType();
15741 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15742 && "Only anyext and sext are currently implemented.");
15743 assert(MemVT != RegVT && "Cannot extend to the same type");
15744 assert(MemVT.isVector() && "Must load a vector from memory");
15746 unsigned NumElems = RegVT.getVectorNumElements();
15747 unsigned MemSz = MemVT.getSizeInBits();
15748 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15750 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15751 // The only way in which we have a legal 256-bit vector result but not the
15752 // integer 256-bit operations needed to directly lower a sextload is if we
15753 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15754 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15755 // correctly legalized. We do this late to allow the canonical form of
15756 // sextload to persist throughout the rest of the DAG combiner -- it wants
15757 // to fold together any extensions it can, and so will fuse a sign_extend
15758 // of an sextload into a sextload targeting a wider value.
15760 if (MemSz == 128) {
15761 // Just switch this to a normal load.
15762 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15763 "it must be a legal 128-bit vector "
15765 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15766 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15767 Ld->isInvariant(), Ld->getAlignment());
15769 assert(MemSz < 128 &&
15770 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15771 // Do an sext load to a 128-bit vector type. We want to use the same
15772 // number of elements, but elements half as wide. This will end up being
15773 // recursively lowered by this routine, but will succeed as we definitely
15774 // have all the necessary features if we're using AVX1.
15776 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15777 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15779 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15780 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15781 Ld->isNonTemporal(), Ld->isInvariant(),
15782 Ld->getAlignment());
15785 // Replace chain users with the new chain.
15786 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15787 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15789 // Finally, do a normal sign-extend to the desired register.
15790 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15793 // All sizes must be a power of two.
15794 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15795 "Non-power-of-two elements are not custom lowered!");
15797 // Attempt to load the original value using scalar loads.
15798 // Find the largest scalar type that divides the total loaded size.
15799 MVT SclrLoadTy = MVT::i8;
15800 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15801 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15802 MVT Tp = (MVT::SimpleValueType)tp;
15803 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15808 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15809 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15811 SclrLoadTy = MVT::f64;
15813 // Calculate the number of scalar loads that we need to perform
15814 // in order to load our vector from memory.
15815 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15817 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15818 "Can only lower sext loads with a single scalar load!");
15820 unsigned loadRegZize = RegSz;
15821 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15824 // Represent our vector as a sequence of elements which are the
15825 // largest scalar that we can load.
15826 EVT LoadUnitVecVT = EVT::getVectorVT(
15827 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15829 // Represent the data using the same element type that is stored in
15830 // memory. In practice, we ''widen'' MemVT.
15832 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15833 loadRegZize / MemVT.getScalarType().getSizeInBits());
15835 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15836 "Invalid vector type");
15838 // We can't shuffle using an illegal type.
15839 assert(TLI.isTypeLegal(WideVecVT) &&
15840 "We only lower types that form legal widened vector types");
15842 SmallVector<SDValue, 8> Chains;
15843 SDValue Ptr = Ld->getBasePtr();
15844 SDValue Increment =
15845 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15846 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15848 for (unsigned i = 0; i < NumLoads; ++i) {
15849 // Perform a single load.
15850 SDValue ScalarLoad =
15851 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15852 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15853 Ld->getAlignment());
15854 Chains.push_back(ScalarLoad.getValue(1));
15855 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15856 // another round of DAGCombining.
15858 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15860 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15861 ScalarLoad, DAG.getIntPtrConstant(i));
15863 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15866 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15868 // Bitcast the loaded value to a vector of the original element type, in
15869 // the size of the target vector type.
15870 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15871 unsigned SizeRatio = RegSz / MemSz;
15873 if (Ext == ISD::SEXTLOAD) {
15874 // If we have SSE4.1, we can directly emit a VSEXT node.
15875 if (Subtarget->hasSSE41()) {
15876 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15877 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15881 // Otherwise we'll shuffle the small elements in the high bits of the
15882 // larger type and perform an arithmetic shift. If the shift is not legal
15883 // it's better to scalarize.
15884 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15885 "We can't implement a sext load without an arithmetic right shift!");
15887 // Redistribute the loaded elements into the different locations.
15888 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15889 for (unsigned i = 0; i != NumElems; ++i)
15890 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15892 SDValue Shuff = DAG.getVectorShuffle(
15893 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15895 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15897 // Build the arithmetic shift.
15898 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15899 MemVT.getVectorElementType().getSizeInBits();
15901 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15903 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15907 // Redistribute the loaded elements into the different locations.
15908 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15909 for (unsigned i = 0; i != NumElems; ++i)
15910 ShuffleVec[i * SizeRatio] = i;
15912 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15913 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15915 // Bitcast to the requested type.
15916 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15917 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15921 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15922 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15923 // from the AND / OR.
15924 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15925 Opc = Op.getOpcode();
15926 if (Opc != ISD::OR && Opc != ISD::AND)
15928 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15929 Op.getOperand(0).hasOneUse() &&
15930 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15931 Op.getOperand(1).hasOneUse());
15934 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15935 // 1 and that the SETCC node has a single use.
15936 static bool isXor1OfSetCC(SDValue Op) {
15937 if (Op.getOpcode() != ISD::XOR)
15939 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15940 if (N1C && N1C->getAPIntValue() == 1) {
15941 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15942 Op.getOperand(0).hasOneUse();
15947 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15948 bool addTest = true;
15949 SDValue Chain = Op.getOperand(0);
15950 SDValue Cond = Op.getOperand(1);
15951 SDValue Dest = Op.getOperand(2);
15954 bool Inverted = false;
15956 if (Cond.getOpcode() == ISD::SETCC) {
15957 // Check for setcc([su]{add,sub,mul}o == 0).
15958 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15959 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15960 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15961 Cond.getOperand(0).getResNo() == 1 &&
15962 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15963 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15964 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15965 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15966 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15967 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15969 Cond = Cond.getOperand(0);
15971 SDValue NewCond = LowerSETCC(Cond, DAG);
15972 if (NewCond.getNode())
15977 // FIXME: LowerXALUO doesn't handle these!!
15978 else if (Cond.getOpcode() == X86ISD::ADD ||
15979 Cond.getOpcode() == X86ISD::SUB ||
15980 Cond.getOpcode() == X86ISD::SMUL ||
15981 Cond.getOpcode() == X86ISD::UMUL)
15982 Cond = LowerXALUO(Cond, DAG);
15985 // Look pass (and (setcc_carry (cmp ...)), 1).
15986 if (Cond.getOpcode() == ISD::AND &&
15987 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15988 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15989 if (C && C->getAPIntValue() == 1)
15990 Cond = Cond.getOperand(0);
15993 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15994 // setting operand in place of the X86ISD::SETCC.
15995 unsigned CondOpcode = Cond.getOpcode();
15996 if (CondOpcode == X86ISD::SETCC ||
15997 CondOpcode == X86ISD::SETCC_CARRY) {
15998 CC = Cond.getOperand(0);
16000 SDValue Cmp = Cond.getOperand(1);
16001 unsigned Opc = Cmp.getOpcode();
16002 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16003 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16007 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16011 // These can only come from an arithmetic instruction with overflow,
16012 // e.g. SADDO, UADDO.
16013 Cond = Cond.getNode()->getOperand(1);
16019 CondOpcode = Cond.getOpcode();
16020 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16021 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16022 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16023 Cond.getOperand(0).getValueType() != MVT::i8)) {
16024 SDValue LHS = Cond.getOperand(0);
16025 SDValue RHS = Cond.getOperand(1);
16026 unsigned X86Opcode;
16029 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16030 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16032 switch (CondOpcode) {
16033 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16035 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16037 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16040 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16041 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16043 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16045 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16048 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16049 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16050 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16051 default: llvm_unreachable("unexpected overflowing operator");
16054 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16055 if (CondOpcode == ISD::UMULO)
16056 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16059 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16061 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16063 if (CondOpcode == ISD::UMULO)
16064 Cond = X86Op.getValue(2);
16066 Cond = X86Op.getValue(1);
16068 CC = DAG.getConstant(X86Cond, MVT::i8);
16072 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16073 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16074 if (CondOpc == ISD::OR) {
16075 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16076 // two branches instead of an explicit OR instruction with a
16078 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16079 isX86LogicalCmp(Cmp)) {
16080 CC = Cond.getOperand(0).getOperand(0);
16081 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16082 Chain, Dest, CC, Cmp);
16083 CC = Cond.getOperand(1).getOperand(0);
16087 } else { // ISD::AND
16088 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16089 // two branches instead of an explicit AND instruction with a
16090 // separate test. However, we only do this if this block doesn't
16091 // have a fall-through edge, because this requires an explicit
16092 // jmp when the condition is false.
16093 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16094 isX86LogicalCmp(Cmp) &&
16095 Op.getNode()->hasOneUse()) {
16096 X86::CondCode CCode =
16097 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16098 CCode = X86::GetOppositeBranchCondition(CCode);
16099 CC = DAG.getConstant(CCode, MVT::i8);
16100 SDNode *User = *Op.getNode()->use_begin();
16101 // Look for an unconditional branch following this conditional branch.
16102 // We need this because we need to reverse the successors in order
16103 // to implement FCMP_OEQ.
16104 if (User->getOpcode() == ISD::BR) {
16105 SDValue FalseBB = User->getOperand(1);
16107 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16108 assert(NewBR == User);
16112 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16113 Chain, Dest, CC, Cmp);
16114 X86::CondCode CCode =
16115 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16116 CCode = X86::GetOppositeBranchCondition(CCode);
16117 CC = DAG.getConstant(CCode, MVT::i8);
16123 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16124 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16125 // It should be transformed during dag combiner except when the condition
16126 // is set by a arithmetics with overflow node.
16127 X86::CondCode CCode =
16128 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16129 CCode = X86::GetOppositeBranchCondition(CCode);
16130 CC = DAG.getConstant(CCode, MVT::i8);
16131 Cond = Cond.getOperand(0).getOperand(1);
16133 } else if (Cond.getOpcode() == ISD::SETCC &&
16134 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16135 // For FCMP_OEQ, we can emit
16136 // two branches instead of an explicit AND instruction with a
16137 // separate test. However, we only do this if this block doesn't
16138 // have a fall-through edge, because this requires an explicit
16139 // jmp when the condition is false.
16140 if (Op.getNode()->hasOneUse()) {
16141 SDNode *User = *Op.getNode()->use_begin();
16142 // Look for an unconditional branch following this conditional branch.
16143 // We need this because we need to reverse the successors in order
16144 // to implement FCMP_OEQ.
16145 if (User->getOpcode() == ISD::BR) {
16146 SDValue FalseBB = User->getOperand(1);
16148 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16149 assert(NewBR == User);
16153 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16154 Cond.getOperand(0), Cond.getOperand(1));
16155 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16156 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16157 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16158 Chain, Dest, CC, Cmp);
16159 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16164 } else if (Cond.getOpcode() == ISD::SETCC &&
16165 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16166 // For FCMP_UNE, we can emit
16167 // two branches instead of an explicit AND instruction with a
16168 // separate test. However, we only do this if this block doesn't
16169 // have a fall-through edge, because this requires an explicit
16170 // jmp when the condition is false.
16171 if (Op.getNode()->hasOneUse()) {
16172 SDNode *User = *Op.getNode()->use_begin();
16173 // Look for an unconditional branch following this conditional branch.
16174 // We need this because we need to reverse the successors in order
16175 // to implement FCMP_UNE.
16176 if (User->getOpcode() == ISD::BR) {
16177 SDValue FalseBB = User->getOperand(1);
16179 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16180 assert(NewBR == User);
16183 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16184 Cond.getOperand(0), Cond.getOperand(1));
16185 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16186 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16187 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16188 Chain, Dest, CC, Cmp);
16189 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16199 // Look pass the truncate if the high bits are known zero.
16200 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16201 Cond = Cond.getOperand(0);
16203 // We know the result of AND is compared against zero. Try to match
16205 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16206 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16207 if (NewSetCC.getNode()) {
16208 CC = NewSetCC.getOperand(0);
16209 Cond = NewSetCC.getOperand(1);
16216 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16217 CC = DAG.getConstant(X86Cond, MVT::i8);
16218 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16220 Cond = ConvertCmpIfNecessary(Cond, DAG);
16221 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16222 Chain, Dest, CC, Cond);
16225 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16226 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16227 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16228 // that the guard pages used by the OS virtual memory manager are allocated in
16229 // correct sequence.
16231 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16232 SelectionDAG &DAG) const {
16233 MachineFunction &MF = DAG.getMachineFunction();
16234 bool SplitStack = MF.shouldSplitStack();
16235 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
16240 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16241 SDNode* Node = Op.getNode();
16243 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16244 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16245 " not tell us which reg is the stack pointer!");
16246 EVT VT = Node->getValueType(0);
16247 SDValue Tmp1 = SDValue(Node, 0);
16248 SDValue Tmp2 = SDValue(Node, 1);
16249 SDValue Tmp3 = Node->getOperand(2);
16250 SDValue Chain = Tmp1.getOperand(0);
16252 // Chain the dynamic stack allocation so that it doesn't modify the stack
16253 // pointer when other instructions are using the stack.
16254 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16257 SDValue Size = Tmp2.getOperand(1);
16258 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16259 Chain = SP.getValue(1);
16260 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16261 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16262 unsigned StackAlign = TFI.getStackAlignment();
16263 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16264 if (Align > StackAlign)
16265 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16266 DAG.getConstant(-(uint64_t)Align, VT));
16267 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16269 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16270 DAG.getIntPtrConstant(0, true), SDValue(),
16273 SDValue Ops[2] = { Tmp1, Tmp2 };
16274 return DAG.getMergeValues(Ops, dl);
16278 SDValue Chain = Op.getOperand(0);
16279 SDValue Size = Op.getOperand(1);
16280 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16281 EVT VT = Op.getNode()->getValueType(0);
16283 bool Is64Bit = Subtarget->is64Bit();
16284 EVT SPTy = getPointerTy();
16287 MachineRegisterInfo &MRI = MF.getRegInfo();
16290 // The 64 bit implementation of segmented stacks needs to clobber both r10
16291 // r11. This makes it impossible to use it along with nested parameters.
16292 const Function *F = MF.getFunction();
16294 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16296 if (I->hasNestAttr())
16297 report_fatal_error("Cannot use segmented stacks with functions that "
16298 "have nested arguments.");
16301 const TargetRegisterClass *AddrRegClass =
16302 getRegClassFor(getPointerTy());
16303 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16304 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16305 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16306 DAG.getRegister(Vreg, SPTy));
16307 SDValue Ops1[2] = { Value, Chain };
16308 return DAG.getMergeValues(Ops1, dl);
16311 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16313 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16314 Flag = Chain.getValue(1);
16315 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16317 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16319 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16320 DAG.getSubtarget().getRegisterInfo());
16321 unsigned SPReg = RegInfo->getStackRegister();
16322 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16323 Chain = SP.getValue(1);
16326 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16327 DAG.getConstant(-(uint64_t)Align, VT));
16328 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16331 SDValue Ops1[2] = { SP, Chain };
16332 return DAG.getMergeValues(Ops1, dl);
16336 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16337 MachineFunction &MF = DAG.getMachineFunction();
16338 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16340 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16343 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16344 // vastart just stores the address of the VarArgsFrameIndex slot into the
16345 // memory location argument.
16346 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16348 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16349 MachinePointerInfo(SV), false, false, 0);
16353 // gp_offset (0 - 6 * 8)
16354 // fp_offset (48 - 48 + 8 * 16)
16355 // overflow_arg_area (point to parameters coming in memory).
16357 SmallVector<SDValue, 8> MemOps;
16358 SDValue FIN = Op.getOperand(1);
16360 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16361 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16363 FIN, MachinePointerInfo(SV), false, false, 0);
16364 MemOps.push_back(Store);
16367 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16368 FIN, DAG.getIntPtrConstant(4));
16369 Store = DAG.getStore(Op.getOperand(0), DL,
16370 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16372 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16373 MemOps.push_back(Store);
16375 // Store ptr to overflow_arg_area
16376 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16377 FIN, DAG.getIntPtrConstant(4));
16378 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16380 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16381 MachinePointerInfo(SV, 8),
16383 MemOps.push_back(Store);
16385 // Store ptr to reg_save_area.
16386 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16387 FIN, DAG.getIntPtrConstant(8));
16388 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16390 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16391 MachinePointerInfo(SV, 16), false, false, 0);
16392 MemOps.push_back(Store);
16393 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16396 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16397 assert(Subtarget->is64Bit() &&
16398 "LowerVAARG only handles 64-bit va_arg!");
16399 assert((Subtarget->isTargetLinux() ||
16400 Subtarget->isTargetDarwin()) &&
16401 "Unhandled target in LowerVAARG");
16402 assert(Op.getNode()->getNumOperands() == 4);
16403 SDValue Chain = Op.getOperand(0);
16404 SDValue SrcPtr = Op.getOperand(1);
16405 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16406 unsigned Align = Op.getConstantOperandVal(3);
16409 EVT ArgVT = Op.getNode()->getValueType(0);
16410 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16411 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16414 // Decide which area this value should be read from.
16415 // TODO: Implement the AMD64 ABI in its entirety. This simple
16416 // selection mechanism works only for the basic types.
16417 if (ArgVT == MVT::f80) {
16418 llvm_unreachable("va_arg for f80 not yet implemented");
16419 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16420 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16421 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16422 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16424 llvm_unreachable("Unhandled argument type in LowerVAARG");
16427 if (ArgMode == 2) {
16428 // Sanity Check: Make sure using fp_offset makes sense.
16429 assert(!DAG.getTarget().Options.UseSoftFloat &&
16430 !(DAG.getMachineFunction()
16431 .getFunction()->getAttributes()
16432 .hasAttribute(AttributeSet::FunctionIndex,
16433 Attribute::NoImplicitFloat)) &&
16434 Subtarget->hasSSE1());
16437 // Insert VAARG_64 node into the DAG
16438 // VAARG_64 returns two values: Variable Argument Address, Chain
16439 SmallVector<SDValue, 11> InstOps;
16440 InstOps.push_back(Chain);
16441 InstOps.push_back(SrcPtr);
16442 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16443 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16444 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16445 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16446 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16447 VTs, InstOps, MVT::i64,
16448 MachinePointerInfo(SV),
16450 /*Volatile=*/false,
16452 /*WriteMem=*/true);
16453 Chain = VAARG.getValue(1);
16455 // Load the next argument and return it
16456 return DAG.getLoad(ArgVT, dl,
16459 MachinePointerInfo(),
16460 false, false, false, 0);
16463 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16464 SelectionDAG &DAG) {
16465 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16466 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16467 SDValue Chain = Op.getOperand(0);
16468 SDValue DstPtr = Op.getOperand(1);
16469 SDValue SrcPtr = Op.getOperand(2);
16470 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16471 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16474 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16475 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16477 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16480 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16481 // amount is a constant. Takes immediate version of shift as input.
16482 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16483 SDValue SrcOp, uint64_t ShiftAmt,
16484 SelectionDAG &DAG) {
16485 MVT ElementType = VT.getVectorElementType();
16487 // Fold this packed shift into its first operand if ShiftAmt is 0.
16491 // Check for ShiftAmt >= element width
16492 if (ShiftAmt >= ElementType.getSizeInBits()) {
16493 if (Opc == X86ISD::VSRAI)
16494 ShiftAmt = ElementType.getSizeInBits() - 1;
16496 return DAG.getConstant(0, VT);
16499 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16500 && "Unknown target vector shift-by-constant node");
16502 // Fold this packed vector shift into a build vector if SrcOp is a
16503 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16504 if (VT == SrcOp.getSimpleValueType() &&
16505 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16506 SmallVector<SDValue, 8> Elts;
16507 unsigned NumElts = SrcOp->getNumOperands();
16508 ConstantSDNode *ND;
16511 default: llvm_unreachable(nullptr);
16512 case X86ISD::VSHLI:
16513 for (unsigned i=0; i!=NumElts; ++i) {
16514 SDValue CurrentOp = SrcOp->getOperand(i);
16515 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16516 Elts.push_back(CurrentOp);
16519 ND = cast<ConstantSDNode>(CurrentOp);
16520 const APInt &C = ND->getAPIntValue();
16521 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16524 case X86ISD::VSRLI:
16525 for (unsigned i=0; i!=NumElts; ++i) {
16526 SDValue CurrentOp = SrcOp->getOperand(i);
16527 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16528 Elts.push_back(CurrentOp);
16531 ND = cast<ConstantSDNode>(CurrentOp);
16532 const APInt &C = ND->getAPIntValue();
16533 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16536 case X86ISD::VSRAI:
16537 for (unsigned i=0; i!=NumElts; ++i) {
16538 SDValue CurrentOp = SrcOp->getOperand(i);
16539 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16540 Elts.push_back(CurrentOp);
16543 ND = cast<ConstantSDNode>(CurrentOp);
16544 const APInt &C = ND->getAPIntValue();
16545 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16550 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16553 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16556 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16557 // may or may not be a constant. Takes immediate version of shift as input.
16558 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16559 SDValue SrcOp, SDValue ShAmt,
16560 SelectionDAG &DAG) {
16561 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16563 // Catch shift-by-constant.
16564 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16565 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16566 CShAmt->getZExtValue(), DAG);
16568 // Change opcode to non-immediate version
16570 default: llvm_unreachable("Unknown target vector shift node");
16571 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16572 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16573 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16576 // Need to build a vector containing shift amount
16577 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16580 ShOps[1] = DAG.getConstant(0, MVT::i32);
16581 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16582 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16584 // The return type has to be a 128-bit type with the same element
16585 // type as the input type.
16586 MVT EltVT = VT.getVectorElementType();
16587 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16589 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16590 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16593 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16594 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16595 /// necessary casting for \p Mask when lowering masking intrinsics.
16596 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16597 SDValue PreservedSrc,
16598 const X86Subtarget *Subtarget,
16599 SelectionDAG &DAG) {
16600 EVT VT = Op.getValueType();
16601 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16602 MVT::i1, VT.getVectorNumElements());
16603 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16604 Mask.getValueType().getSizeInBits());
16607 assert(MaskVT.isSimple() && "invalid mask type");
16609 if (isAllOnes(Mask))
16612 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16613 // are extracted by EXTRACT_SUBVECTOR.
16614 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16615 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16616 DAG.getIntPtrConstant(0));
16618 switch (Op.getOpcode()) {
16620 case X86ISD::PCMPEQM:
16621 case X86ISD::PCMPGTM:
16623 case X86ISD::CMPMU:
16624 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16626 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16627 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16628 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16631 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16633 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16634 case Intrinsic::x86_fma_vfmadd_ps:
16635 case Intrinsic::x86_fma_vfmadd_pd:
16636 case Intrinsic::x86_fma_vfmadd_ps_256:
16637 case Intrinsic::x86_fma_vfmadd_pd_256:
16638 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16639 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16640 return X86ISD::FMADD;
16641 case Intrinsic::x86_fma_vfmsub_ps:
16642 case Intrinsic::x86_fma_vfmsub_pd:
16643 case Intrinsic::x86_fma_vfmsub_ps_256:
16644 case Intrinsic::x86_fma_vfmsub_pd_256:
16645 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16646 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16647 return X86ISD::FMSUB;
16648 case Intrinsic::x86_fma_vfnmadd_ps:
16649 case Intrinsic::x86_fma_vfnmadd_pd:
16650 case Intrinsic::x86_fma_vfnmadd_ps_256:
16651 case Intrinsic::x86_fma_vfnmadd_pd_256:
16652 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16653 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16654 return X86ISD::FNMADD;
16655 case Intrinsic::x86_fma_vfnmsub_ps:
16656 case Intrinsic::x86_fma_vfnmsub_pd:
16657 case Intrinsic::x86_fma_vfnmsub_ps_256:
16658 case Intrinsic::x86_fma_vfnmsub_pd_256:
16659 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16660 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16661 return X86ISD::FNMSUB;
16662 case Intrinsic::x86_fma_vfmaddsub_ps:
16663 case Intrinsic::x86_fma_vfmaddsub_pd:
16664 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16665 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16666 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16667 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16668 return X86ISD::FMADDSUB;
16669 case Intrinsic::x86_fma_vfmsubadd_ps:
16670 case Intrinsic::x86_fma_vfmsubadd_pd:
16671 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16672 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16673 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16674 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16675 return X86ISD::FMSUBADD;
16679 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16680 SelectionDAG &DAG) {
16682 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16683 EVT VT = Op.getValueType();
16684 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16686 switch(IntrData->Type) {
16687 case INTR_TYPE_1OP:
16688 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16689 case INTR_TYPE_2OP:
16690 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16692 case INTR_TYPE_3OP:
16693 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16694 Op.getOperand(2), Op.getOperand(3));
16695 case INTR_TYPE_1OP_MASK_RM: {
16696 SDValue Src = Op.getOperand(1);
16697 SDValue Src0 = Op.getOperand(2);
16698 SDValue Mask = Op.getOperand(3);
16699 SDValue RoundingMode = Op.getOperand(4);
16700 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16702 Mask, Src0, Subtarget, DAG);
16706 case CMP_MASK_CC: {
16707 // Comparison intrinsics with masks.
16708 // Example of transformation:
16709 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16710 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16712 // (v8i1 (insert_subvector undef,
16713 // (v2i1 (and (PCMPEQM %a, %b),
16714 // (extract_subvector
16715 // (v8i1 (bitcast %mask)), 0))), 0))))
16716 EVT VT = Op.getOperand(1).getValueType();
16717 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16718 VT.getVectorNumElements());
16719 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16720 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16721 Mask.getValueType().getSizeInBits());
16723 if (IntrData->Type == CMP_MASK_CC) {
16724 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16725 Op.getOperand(2), Op.getOperand(3));
16727 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16728 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16731 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16732 DAG.getTargetConstant(0, MaskVT),
16734 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16735 DAG.getUNDEF(BitcastVT), CmpMask,
16736 DAG.getIntPtrConstant(0));
16737 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16739 case COMI: { // Comparison intrinsics
16740 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16741 SDValue LHS = Op.getOperand(1);
16742 SDValue RHS = Op.getOperand(2);
16743 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16744 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16745 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16746 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16747 DAG.getConstant(X86CC, MVT::i8), Cond);
16748 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16751 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16752 Op.getOperand(1), Op.getOperand(2), DAG);
16754 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16755 Op.getOperand(1), Op.getOperand(2), DAG),
16756 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);;
16763 default: return SDValue(); // Don't custom lower most intrinsics.
16765 // Arithmetic intrinsics.
16766 case Intrinsic::x86_sse2_pmulu_dq:
16767 case Intrinsic::x86_avx2_pmulu_dq:
16768 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16769 Op.getOperand(1), Op.getOperand(2));
16771 case Intrinsic::x86_sse41_pmuldq:
16772 case Intrinsic::x86_avx2_pmul_dq:
16773 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16774 Op.getOperand(1), Op.getOperand(2));
16776 case Intrinsic::x86_sse2_pmulhu_w:
16777 case Intrinsic::x86_avx2_pmulhu_w:
16778 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16779 Op.getOperand(1), Op.getOperand(2));
16781 case Intrinsic::x86_sse2_pmulh_w:
16782 case Intrinsic::x86_avx2_pmulh_w:
16783 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16784 Op.getOperand(1), Op.getOperand(2));
16786 // SSE/SSE2/AVX floating point max/min intrinsics.
16787 case Intrinsic::x86_sse_max_ps:
16788 case Intrinsic::x86_sse2_max_pd:
16789 case Intrinsic::x86_avx_max_ps_256:
16790 case Intrinsic::x86_avx_max_pd_256:
16791 case Intrinsic::x86_sse_min_ps:
16792 case Intrinsic::x86_sse2_min_pd:
16793 case Intrinsic::x86_avx_min_ps_256:
16794 case Intrinsic::x86_avx_min_pd_256: {
16797 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16798 case Intrinsic::x86_sse_max_ps:
16799 case Intrinsic::x86_sse2_max_pd:
16800 case Intrinsic::x86_avx_max_ps_256:
16801 case Intrinsic::x86_avx_max_pd_256:
16802 Opcode = X86ISD::FMAX;
16804 case Intrinsic::x86_sse_min_ps:
16805 case Intrinsic::x86_sse2_min_pd:
16806 case Intrinsic::x86_avx_min_ps_256:
16807 case Intrinsic::x86_avx_min_pd_256:
16808 Opcode = X86ISD::FMIN;
16811 return DAG.getNode(Opcode, dl, Op.getValueType(),
16812 Op.getOperand(1), Op.getOperand(2));
16815 // AVX2 variable shift intrinsics
16816 case Intrinsic::x86_avx2_psllv_d:
16817 case Intrinsic::x86_avx2_psllv_q:
16818 case Intrinsic::x86_avx2_psllv_d_256:
16819 case Intrinsic::x86_avx2_psllv_q_256:
16820 case Intrinsic::x86_avx2_psrlv_d:
16821 case Intrinsic::x86_avx2_psrlv_q:
16822 case Intrinsic::x86_avx2_psrlv_d_256:
16823 case Intrinsic::x86_avx2_psrlv_q_256:
16824 case Intrinsic::x86_avx2_psrav_d:
16825 case Intrinsic::x86_avx2_psrav_d_256: {
16828 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16829 case Intrinsic::x86_avx2_psllv_d:
16830 case Intrinsic::x86_avx2_psllv_q:
16831 case Intrinsic::x86_avx2_psllv_d_256:
16832 case Intrinsic::x86_avx2_psllv_q_256:
16835 case Intrinsic::x86_avx2_psrlv_d:
16836 case Intrinsic::x86_avx2_psrlv_q:
16837 case Intrinsic::x86_avx2_psrlv_d_256:
16838 case Intrinsic::x86_avx2_psrlv_q_256:
16841 case Intrinsic::x86_avx2_psrav_d:
16842 case Intrinsic::x86_avx2_psrav_d_256:
16846 return DAG.getNode(Opcode, dl, Op.getValueType(),
16847 Op.getOperand(1), Op.getOperand(2));
16850 case Intrinsic::x86_sse2_packssdw_128:
16851 case Intrinsic::x86_sse2_packsswb_128:
16852 case Intrinsic::x86_avx2_packssdw:
16853 case Intrinsic::x86_avx2_packsswb:
16854 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16855 Op.getOperand(1), Op.getOperand(2));
16857 case Intrinsic::x86_sse2_packuswb_128:
16858 case Intrinsic::x86_sse41_packusdw:
16859 case Intrinsic::x86_avx2_packuswb:
16860 case Intrinsic::x86_avx2_packusdw:
16861 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16862 Op.getOperand(1), Op.getOperand(2));
16864 case Intrinsic::x86_ssse3_pshuf_b_128:
16865 case Intrinsic::x86_avx2_pshuf_b:
16866 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16867 Op.getOperand(1), Op.getOperand(2));
16869 case Intrinsic::x86_sse2_pshuf_d:
16870 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16871 Op.getOperand(1), Op.getOperand(2));
16873 case Intrinsic::x86_sse2_pshufl_w:
16874 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16875 Op.getOperand(1), Op.getOperand(2));
16877 case Intrinsic::x86_sse2_pshufh_w:
16878 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16879 Op.getOperand(1), Op.getOperand(2));
16881 case Intrinsic::x86_ssse3_psign_b_128:
16882 case Intrinsic::x86_ssse3_psign_w_128:
16883 case Intrinsic::x86_ssse3_psign_d_128:
16884 case Intrinsic::x86_avx2_psign_b:
16885 case Intrinsic::x86_avx2_psign_w:
16886 case Intrinsic::x86_avx2_psign_d:
16887 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16888 Op.getOperand(1), Op.getOperand(2));
16890 case Intrinsic::x86_avx2_permd:
16891 case Intrinsic::x86_avx2_permps:
16892 // Operands intentionally swapped. Mask is last operand to intrinsic,
16893 // but second operand for node/instruction.
16894 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16895 Op.getOperand(2), Op.getOperand(1));
16897 case Intrinsic::x86_avx512_mask_valign_q_512:
16898 case Intrinsic::x86_avx512_mask_valign_d_512:
16899 // Vector source operands are swapped.
16900 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16901 Op.getValueType(), Op.getOperand(2),
16904 Op.getOperand(5), Op.getOperand(4),
16907 // ptest and testp intrinsics. The intrinsic these come from are designed to
16908 // return an integer value, not just an instruction so lower it to the ptest
16909 // or testp pattern and a setcc for the result.
16910 case Intrinsic::x86_sse41_ptestz:
16911 case Intrinsic::x86_sse41_ptestc:
16912 case Intrinsic::x86_sse41_ptestnzc:
16913 case Intrinsic::x86_avx_ptestz_256:
16914 case Intrinsic::x86_avx_ptestc_256:
16915 case Intrinsic::x86_avx_ptestnzc_256:
16916 case Intrinsic::x86_avx_vtestz_ps:
16917 case Intrinsic::x86_avx_vtestc_ps:
16918 case Intrinsic::x86_avx_vtestnzc_ps:
16919 case Intrinsic::x86_avx_vtestz_pd:
16920 case Intrinsic::x86_avx_vtestc_pd:
16921 case Intrinsic::x86_avx_vtestnzc_pd:
16922 case Intrinsic::x86_avx_vtestz_ps_256:
16923 case Intrinsic::x86_avx_vtestc_ps_256:
16924 case Intrinsic::x86_avx_vtestnzc_ps_256:
16925 case Intrinsic::x86_avx_vtestz_pd_256:
16926 case Intrinsic::x86_avx_vtestc_pd_256:
16927 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16928 bool IsTestPacked = false;
16931 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16932 case Intrinsic::x86_avx_vtestz_ps:
16933 case Intrinsic::x86_avx_vtestz_pd:
16934 case Intrinsic::x86_avx_vtestz_ps_256:
16935 case Intrinsic::x86_avx_vtestz_pd_256:
16936 IsTestPacked = true; // Fallthrough
16937 case Intrinsic::x86_sse41_ptestz:
16938 case Intrinsic::x86_avx_ptestz_256:
16940 X86CC = X86::COND_E;
16942 case Intrinsic::x86_avx_vtestc_ps:
16943 case Intrinsic::x86_avx_vtestc_pd:
16944 case Intrinsic::x86_avx_vtestc_ps_256:
16945 case Intrinsic::x86_avx_vtestc_pd_256:
16946 IsTestPacked = true; // Fallthrough
16947 case Intrinsic::x86_sse41_ptestc:
16948 case Intrinsic::x86_avx_ptestc_256:
16950 X86CC = X86::COND_B;
16952 case Intrinsic::x86_avx_vtestnzc_ps:
16953 case Intrinsic::x86_avx_vtestnzc_pd:
16954 case Intrinsic::x86_avx_vtestnzc_ps_256:
16955 case Intrinsic::x86_avx_vtestnzc_pd_256:
16956 IsTestPacked = true; // Fallthrough
16957 case Intrinsic::x86_sse41_ptestnzc:
16958 case Intrinsic::x86_avx_ptestnzc_256:
16960 X86CC = X86::COND_A;
16964 SDValue LHS = Op.getOperand(1);
16965 SDValue RHS = Op.getOperand(2);
16966 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16967 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16968 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16969 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16970 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16972 case Intrinsic::x86_avx512_kortestz_w:
16973 case Intrinsic::x86_avx512_kortestc_w: {
16974 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16975 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16976 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16977 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16978 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16979 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16980 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16983 case Intrinsic::x86_sse42_pcmpistria128:
16984 case Intrinsic::x86_sse42_pcmpestria128:
16985 case Intrinsic::x86_sse42_pcmpistric128:
16986 case Intrinsic::x86_sse42_pcmpestric128:
16987 case Intrinsic::x86_sse42_pcmpistrio128:
16988 case Intrinsic::x86_sse42_pcmpestrio128:
16989 case Intrinsic::x86_sse42_pcmpistris128:
16990 case Intrinsic::x86_sse42_pcmpestris128:
16991 case Intrinsic::x86_sse42_pcmpistriz128:
16992 case Intrinsic::x86_sse42_pcmpestriz128: {
16996 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16997 case Intrinsic::x86_sse42_pcmpistria128:
16998 Opcode = X86ISD::PCMPISTRI;
16999 X86CC = X86::COND_A;
17001 case Intrinsic::x86_sse42_pcmpestria128:
17002 Opcode = X86ISD::PCMPESTRI;
17003 X86CC = X86::COND_A;
17005 case Intrinsic::x86_sse42_pcmpistric128:
17006 Opcode = X86ISD::PCMPISTRI;
17007 X86CC = X86::COND_B;
17009 case Intrinsic::x86_sse42_pcmpestric128:
17010 Opcode = X86ISD::PCMPESTRI;
17011 X86CC = X86::COND_B;
17013 case Intrinsic::x86_sse42_pcmpistrio128:
17014 Opcode = X86ISD::PCMPISTRI;
17015 X86CC = X86::COND_O;
17017 case Intrinsic::x86_sse42_pcmpestrio128:
17018 Opcode = X86ISD::PCMPESTRI;
17019 X86CC = X86::COND_O;
17021 case Intrinsic::x86_sse42_pcmpistris128:
17022 Opcode = X86ISD::PCMPISTRI;
17023 X86CC = X86::COND_S;
17025 case Intrinsic::x86_sse42_pcmpestris128:
17026 Opcode = X86ISD::PCMPESTRI;
17027 X86CC = X86::COND_S;
17029 case Intrinsic::x86_sse42_pcmpistriz128:
17030 Opcode = X86ISD::PCMPISTRI;
17031 X86CC = X86::COND_E;
17033 case Intrinsic::x86_sse42_pcmpestriz128:
17034 Opcode = X86ISD::PCMPESTRI;
17035 X86CC = X86::COND_E;
17038 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17039 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17040 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17041 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17042 DAG.getConstant(X86CC, MVT::i8),
17043 SDValue(PCMP.getNode(), 1));
17044 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17047 case Intrinsic::x86_sse42_pcmpistri128:
17048 case Intrinsic::x86_sse42_pcmpestri128: {
17050 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17051 Opcode = X86ISD::PCMPISTRI;
17053 Opcode = X86ISD::PCMPESTRI;
17055 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17056 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17057 return DAG.getNode(Opcode, dl, VTs, NewOps);
17060 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17061 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17062 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17063 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17064 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17065 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17066 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17067 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17068 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17069 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17070 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17071 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17072 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17073 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17074 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17075 dl, Op.getValueType(),
17079 Op.getOperand(4), Op.getOperand(1),
17085 case Intrinsic::x86_fma_vfmadd_ps:
17086 case Intrinsic::x86_fma_vfmadd_pd:
17087 case Intrinsic::x86_fma_vfmsub_ps:
17088 case Intrinsic::x86_fma_vfmsub_pd:
17089 case Intrinsic::x86_fma_vfnmadd_ps:
17090 case Intrinsic::x86_fma_vfnmadd_pd:
17091 case Intrinsic::x86_fma_vfnmsub_ps:
17092 case Intrinsic::x86_fma_vfnmsub_pd:
17093 case Intrinsic::x86_fma_vfmaddsub_ps:
17094 case Intrinsic::x86_fma_vfmaddsub_pd:
17095 case Intrinsic::x86_fma_vfmsubadd_ps:
17096 case Intrinsic::x86_fma_vfmsubadd_pd:
17097 case Intrinsic::x86_fma_vfmadd_ps_256:
17098 case Intrinsic::x86_fma_vfmadd_pd_256:
17099 case Intrinsic::x86_fma_vfmsub_ps_256:
17100 case Intrinsic::x86_fma_vfmsub_pd_256:
17101 case Intrinsic::x86_fma_vfnmadd_ps_256:
17102 case Intrinsic::x86_fma_vfnmadd_pd_256:
17103 case Intrinsic::x86_fma_vfnmsub_ps_256:
17104 case Intrinsic::x86_fma_vfnmsub_pd_256:
17105 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17106 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17107 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17108 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17109 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17110 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17114 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17115 SDValue Src, SDValue Mask, SDValue Base,
17116 SDValue Index, SDValue ScaleOp, SDValue Chain,
17117 const X86Subtarget * Subtarget) {
17119 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17120 assert(C && "Invalid scale type");
17121 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17122 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17123 Index.getSimpleValueType().getVectorNumElements());
17125 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17127 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17129 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17130 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17131 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17132 SDValue Segment = DAG.getRegister(0, MVT::i32);
17133 if (Src.getOpcode() == ISD::UNDEF)
17134 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17135 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17136 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17137 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17138 return DAG.getMergeValues(RetOps, dl);
17141 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17142 SDValue Src, SDValue Mask, SDValue Base,
17143 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17145 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17146 assert(C && "Invalid scale type");
17147 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17148 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17149 SDValue Segment = DAG.getRegister(0, MVT::i32);
17150 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17151 Index.getSimpleValueType().getVectorNumElements());
17153 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17155 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17157 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17158 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17159 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17160 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17161 return SDValue(Res, 1);
17164 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17165 SDValue Mask, SDValue Base, SDValue Index,
17166 SDValue ScaleOp, SDValue Chain) {
17168 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17169 assert(C && "Invalid scale type");
17170 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17171 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17172 SDValue Segment = DAG.getRegister(0, MVT::i32);
17174 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17176 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17178 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17180 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17181 //SDVTList VTs = DAG.getVTList(MVT::Other);
17182 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17183 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17184 return SDValue(Res, 0);
17187 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17188 // read performance monitor counters (x86_rdpmc).
17189 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17190 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17191 SmallVectorImpl<SDValue> &Results) {
17192 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17193 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17196 // The ECX register is used to select the index of the performance counter
17198 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17200 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17202 // Reads the content of a 64-bit performance counter and returns it in the
17203 // registers EDX:EAX.
17204 if (Subtarget->is64Bit()) {
17205 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17206 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17209 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17210 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17213 Chain = HI.getValue(1);
17215 if (Subtarget->is64Bit()) {
17216 // The EAX register is loaded with the low-order 32 bits. The EDX register
17217 // is loaded with the supported high-order bits of the counter.
17218 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17219 DAG.getConstant(32, MVT::i8));
17220 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17221 Results.push_back(Chain);
17225 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17226 SDValue Ops[] = { LO, HI };
17227 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17228 Results.push_back(Pair);
17229 Results.push_back(Chain);
17232 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17233 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17234 // also used to custom lower READCYCLECOUNTER nodes.
17235 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17236 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17237 SmallVectorImpl<SDValue> &Results) {
17238 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17239 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17242 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17243 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17244 // and the EAX register is loaded with the low-order 32 bits.
17245 if (Subtarget->is64Bit()) {
17246 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17247 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17250 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17251 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17254 SDValue Chain = HI.getValue(1);
17256 if (Opcode == X86ISD::RDTSCP_DAG) {
17257 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17259 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17260 // the ECX register. Add 'ecx' explicitly to the chain.
17261 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17263 // Explicitly store the content of ECX at the location passed in input
17264 // to the 'rdtscp' intrinsic.
17265 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17266 MachinePointerInfo(), false, false, 0);
17269 if (Subtarget->is64Bit()) {
17270 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17271 // the EAX register is loaded with the low-order 32 bits.
17272 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17273 DAG.getConstant(32, MVT::i8));
17274 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17275 Results.push_back(Chain);
17279 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17280 SDValue Ops[] = { LO, HI };
17281 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17282 Results.push_back(Pair);
17283 Results.push_back(Chain);
17286 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17287 SelectionDAG &DAG) {
17288 SmallVector<SDValue, 2> Results;
17290 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17292 return DAG.getMergeValues(Results, DL);
17296 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17297 SelectionDAG &DAG) {
17298 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17300 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17305 switch(IntrData->Type) {
17307 llvm_unreachable("Unknown Intrinsic Type");
17311 // Emit the node with the right value type.
17312 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17313 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17315 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17316 // Otherwise return the value from Rand, which is always 0, casted to i32.
17317 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17318 DAG.getConstant(1, Op->getValueType(1)),
17319 DAG.getConstant(X86::COND_B, MVT::i32),
17320 SDValue(Result.getNode(), 1) };
17321 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17322 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17325 // Return { result, isValid, chain }.
17326 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17327 SDValue(Result.getNode(), 2));
17330 //gather(v1, mask, index, base, scale);
17331 SDValue Chain = Op.getOperand(0);
17332 SDValue Src = Op.getOperand(2);
17333 SDValue Base = Op.getOperand(3);
17334 SDValue Index = Op.getOperand(4);
17335 SDValue Mask = Op.getOperand(5);
17336 SDValue Scale = Op.getOperand(6);
17337 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17341 //scatter(base, mask, index, v1, scale);
17342 SDValue Chain = Op.getOperand(0);
17343 SDValue Base = Op.getOperand(2);
17344 SDValue Mask = Op.getOperand(3);
17345 SDValue Index = Op.getOperand(4);
17346 SDValue Src = Op.getOperand(5);
17347 SDValue Scale = Op.getOperand(6);
17348 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17351 SDValue Hint = Op.getOperand(6);
17353 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17354 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17355 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17356 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17357 SDValue Chain = Op.getOperand(0);
17358 SDValue Mask = Op.getOperand(2);
17359 SDValue Index = Op.getOperand(3);
17360 SDValue Base = Op.getOperand(4);
17361 SDValue Scale = Op.getOperand(5);
17362 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17364 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17366 SmallVector<SDValue, 2> Results;
17367 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17368 return DAG.getMergeValues(Results, dl);
17370 // Read Performance Monitoring Counters.
17372 SmallVector<SDValue, 2> Results;
17373 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17374 return DAG.getMergeValues(Results, dl);
17376 // XTEST intrinsics.
17378 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17379 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17380 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17381 DAG.getConstant(X86::COND_NE, MVT::i8),
17383 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17384 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17385 Ret, SDValue(InTrans.getNode(), 1));
17389 SmallVector<SDValue, 2> Results;
17390 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17391 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17392 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17393 DAG.getConstant(-1, MVT::i8));
17394 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17395 Op.getOperand(4), GenCF.getValue(1));
17396 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17397 Op.getOperand(5), MachinePointerInfo(),
17399 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17400 DAG.getConstant(X86::COND_B, MVT::i8),
17402 Results.push_back(SetCC);
17403 Results.push_back(Store);
17404 return DAG.getMergeValues(Results, dl);
17409 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17410 SelectionDAG &DAG) const {
17411 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17412 MFI->setReturnAddressIsTaken(true);
17414 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17417 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17419 EVT PtrVT = getPointerTy();
17422 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17423 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17424 DAG.getSubtarget().getRegisterInfo());
17425 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17426 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17427 DAG.getNode(ISD::ADD, dl, PtrVT,
17428 FrameAddr, Offset),
17429 MachinePointerInfo(), false, false, false, 0);
17432 // Just load the return address.
17433 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17434 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17435 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17438 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17439 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17440 MFI->setFrameAddressIsTaken(true);
17442 EVT VT = Op.getValueType();
17443 SDLoc dl(Op); // FIXME probably not meaningful
17444 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17445 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17446 DAG.getSubtarget().getRegisterInfo());
17447 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17448 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17449 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17450 "Invalid Frame Register!");
17451 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17453 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17454 MachinePointerInfo(),
17455 false, false, false, 0);
17459 // FIXME? Maybe this could be a TableGen attribute on some registers and
17460 // this table could be generated automatically from RegInfo.
17461 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17463 unsigned Reg = StringSwitch<unsigned>(RegName)
17464 .Case("esp", X86::ESP)
17465 .Case("rsp", X86::RSP)
17469 report_fatal_error("Invalid register name global variable");
17472 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17473 SelectionDAG &DAG) const {
17474 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17475 DAG.getSubtarget().getRegisterInfo());
17476 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17479 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17480 SDValue Chain = Op.getOperand(0);
17481 SDValue Offset = Op.getOperand(1);
17482 SDValue Handler = Op.getOperand(2);
17485 EVT PtrVT = getPointerTy();
17486 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17487 DAG.getSubtarget().getRegisterInfo());
17488 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17489 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17490 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17491 "Invalid Frame Register!");
17492 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17493 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17495 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17496 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17497 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17498 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17500 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17502 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17503 DAG.getRegister(StoreAddrReg, PtrVT));
17506 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17507 SelectionDAG &DAG) const {
17509 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17510 DAG.getVTList(MVT::i32, MVT::Other),
17511 Op.getOperand(0), Op.getOperand(1));
17514 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17515 SelectionDAG &DAG) const {
17517 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17518 Op.getOperand(0), Op.getOperand(1));
17521 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17522 return Op.getOperand(0);
17525 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17526 SelectionDAG &DAG) const {
17527 SDValue Root = Op.getOperand(0);
17528 SDValue Trmp = Op.getOperand(1); // trampoline
17529 SDValue FPtr = Op.getOperand(2); // nested function
17530 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17533 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17534 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17536 if (Subtarget->is64Bit()) {
17537 SDValue OutChains[6];
17539 // Large code-model.
17540 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17541 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17543 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17544 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17546 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17548 // Load the pointer to the nested function into R11.
17549 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17550 SDValue Addr = Trmp;
17551 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17552 Addr, MachinePointerInfo(TrmpAddr),
17555 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17556 DAG.getConstant(2, MVT::i64));
17557 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17558 MachinePointerInfo(TrmpAddr, 2),
17561 // Load the 'nest' parameter value into R10.
17562 // R10 is specified in X86CallingConv.td
17563 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17564 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17565 DAG.getConstant(10, MVT::i64));
17566 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17567 Addr, MachinePointerInfo(TrmpAddr, 10),
17570 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17571 DAG.getConstant(12, MVT::i64));
17572 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17573 MachinePointerInfo(TrmpAddr, 12),
17576 // Jump to the nested function.
17577 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17578 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17579 DAG.getConstant(20, MVT::i64));
17580 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17581 Addr, MachinePointerInfo(TrmpAddr, 20),
17584 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17585 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17586 DAG.getConstant(22, MVT::i64));
17587 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17588 MachinePointerInfo(TrmpAddr, 22),
17591 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17593 const Function *Func =
17594 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17595 CallingConv::ID CC = Func->getCallingConv();
17600 llvm_unreachable("Unsupported calling convention");
17601 case CallingConv::C:
17602 case CallingConv::X86_StdCall: {
17603 // Pass 'nest' parameter in ECX.
17604 // Must be kept in sync with X86CallingConv.td
17605 NestReg = X86::ECX;
17607 // Check that ECX wasn't needed by an 'inreg' parameter.
17608 FunctionType *FTy = Func->getFunctionType();
17609 const AttributeSet &Attrs = Func->getAttributes();
17611 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17612 unsigned InRegCount = 0;
17615 for (FunctionType::param_iterator I = FTy->param_begin(),
17616 E = FTy->param_end(); I != E; ++I, ++Idx)
17617 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17618 // FIXME: should only count parameters that are lowered to integers.
17619 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17621 if (InRegCount > 2) {
17622 report_fatal_error("Nest register in use - reduce number of inreg"
17628 case CallingConv::X86_FastCall:
17629 case CallingConv::X86_ThisCall:
17630 case CallingConv::Fast:
17631 // Pass 'nest' parameter in EAX.
17632 // Must be kept in sync with X86CallingConv.td
17633 NestReg = X86::EAX;
17637 SDValue OutChains[4];
17638 SDValue Addr, Disp;
17640 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17641 DAG.getConstant(10, MVT::i32));
17642 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17644 // This is storing the opcode for MOV32ri.
17645 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17646 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17647 OutChains[0] = DAG.getStore(Root, dl,
17648 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17649 Trmp, MachinePointerInfo(TrmpAddr),
17652 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17653 DAG.getConstant(1, MVT::i32));
17654 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17655 MachinePointerInfo(TrmpAddr, 1),
17658 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17659 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17660 DAG.getConstant(5, MVT::i32));
17661 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17662 MachinePointerInfo(TrmpAddr, 5),
17665 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17666 DAG.getConstant(6, MVT::i32));
17667 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17668 MachinePointerInfo(TrmpAddr, 6),
17671 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17675 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17676 SelectionDAG &DAG) const {
17678 The rounding mode is in bits 11:10 of FPSR, and has the following
17680 00 Round to nearest
17685 FLT_ROUNDS, on the other hand, expects the following:
17692 To perform the conversion, we do:
17693 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17696 MachineFunction &MF = DAG.getMachineFunction();
17697 const TargetMachine &TM = MF.getTarget();
17698 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17699 unsigned StackAlignment = TFI.getStackAlignment();
17700 MVT VT = Op.getSimpleValueType();
17703 // Save FP Control Word to stack slot
17704 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17705 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17707 MachineMemOperand *MMO =
17708 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17709 MachineMemOperand::MOStore, 2, 2);
17711 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17712 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17713 DAG.getVTList(MVT::Other),
17714 Ops, MVT::i16, MMO);
17716 // Load FP Control Word from stack slot
17717 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17718 MachinePointerInfo(), false, false, false, 0);
17720 // Transform as necessary
17722 DAG.getNode(ISD::SRL, DL, MVT::i16,
17723 DAG.getNode(ISD::AND, DL, MVT::i16,
17724 CWD, DAG.getConstant(0x800, MVT::i16)),
17725 DAG.getConstant(11, MVT::i8));
17727 DAG.getNode(ISD::SRL, DL, MVT::i16,
17728 DAG.getNode(ISD::AND, DL, MVT::i16,
17729 CWD, DAG.getConstant(0x400, MVT::i16)),
17730 DAG.getConstant(9, MVT::i8));
17733 DAG.getNode(ISD::AND, DL, MVT::i16,
17734 DAG.getNode(ISD::ADD, DL, MVT::i16,
17735 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17736 DAG.getConstant(1, MVT::i16)),
17737 DAG.getConstant(3, MVT::i16));
17739 return DAG.getNode((VT.getSizeInBits() < 16 ?
17740 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17743 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17744 MVT VT = Op.getSimpleValueType();
17746 unsigned NumBits = VT.getSizeInBits();
17749 Op = Op.getOperand(0);
17750 if (VT == MVT::i8) {
17751 // Zero extend to i32 since there is not an i8 bsr.
17753 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17756 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17757 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17758 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17760 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17763 DAG.getConstant(NumBits+NumBits-1, OpVT),
17764 DAG.getConstant(X86::COND_E, MVT::i8),
17767 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17769 // Finally xor with NumBits-1.
17770 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17773 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17777 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17778 MVT VT = Op.getSimpleValueType();
17780 unsigned NumBits = VT.getSizeInBits();
17783 Op = Op.getOperand(0);
17784 if (VT == MVT::i8) {
17785 // Zero extend to i32 since there is not an i8 bsr.
17787 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17790 // Issue a bsr (scan bits in reverse).
17791 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17792 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17794 // And xor with NumBits-1.
17795 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17798 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17802 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17803 MVT VT = Op.getSimpleValueType();
17804 unsigned NumBits = VT.getSizeInBits();
17806 Op = Op.getOperand(0);
17808 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17809 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17810 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17812 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17815 DAG.getConstant(NumBits, VT),
17816 DAG.getConstant(X86::COND_E, MVT::i8),
17819 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17822 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17823 // ones, and then concatenate the result back.
17824 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17825 MVT VT = Op.getSimpleValueType();
17827 assert(VT.is256BitVector() && VT.isInteger() &&
17828 "Unsupported value type for operation");
17830 unsigned NumElems = VT.getVectorNumElements();
17833 // Extract the LHS vectors
17834 SDValue LHS = Op.getOperand(0);
17835 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17836 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17838 // Extract the RHS vectors
17839 SDValue RHS = Op.getOperand(1);
17840 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17841 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17843 MVT EltVT = VT.getVectorElementType();
17844 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17846 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17847 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17848 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17851 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17852 assert(Op.getSimpleValueType().is256BitVector() &&
17853 Op.getSimpleValueType().isInteger() &&
17854 "Only handle AVX 256-bit vector integer operation");
17855 return Lower256IntArith(Op, DAG);
17858 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17859 assert(Op.getSimpleValueType().is256BitVector() &&
17860 Op.getSimpleValueType().isInteger() &&
17861 "Only handle AVX 256-bit vector integer operation");
17862 return Lower256IntArith(Op, DAG);
17865 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17866 SelectionDAG &DAG) {
17868 MVT VT = Op.getSimpleValueType();
17870 // Decompose 256-bit ops into smaller 128-bit ops.
17871 if (VT.is256BitVector() && !Subtarget->hasInt256())
17872 return Lower256IntArith(Op, DAG);
17874 SDValue A = Op.getOperand(0);
17875 SDValue B = Op.getOperand(1);
17877 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17878 if (VT == MVT::v4i32) {
17879 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17880 "Should not custom lower when pmuldq is available!");
17882 // Extract the odd parts.
17883 static const int UnpackMask[] = { 1, -1, 3, -1 };
17884 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17885 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17887 // Multiply the even parts.
17888 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17889 // Now multiply odd parts.
17890 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17892 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17893 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17895 // Merge the two vectors back together with a shuffle. This expands into 2
17897 static const int ShufMask[] = { 0, 4, 2, 6 };
17898 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17901 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17902 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17904 // Ahi = psrlqi(a, 32);
17905 // Bhi = psrlqi(b, 32);
17907 // AloBlo = pmuludq(a, b);
17908 // AloBhi = pmuludq(a, Bhi);
17909 // AhiBlo = pmuludq(Ahi, b);
17911 // AloBhi = psllqi(AloBhi, 32);
17912 // AhiBlo = psllqi(AhiBlo, 32);
17913 // return AloBlo + AloBhi + AhiBlo;
17915 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17916 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17918 // Bit cast to 32-bit vectors for MULUDQ
17919 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17920 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17921 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17922 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17923 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17924 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17926 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17927 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17928 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17930 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17931 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17933 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17934 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17937 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17938 assert(Subtarget->isTargetWin64() && "Unexpected target");
17939 EVT VT = Op.getValueType();
17940 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17941 "Unexpected return type for lowering");
17945 switch (Op->getOpcode()) {
17946 default: llvm_unreachable("Unexpected request for libcall!");
17947 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17948 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17949 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17950 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17951 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17952 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17956 SDValue InChain = DAG.getEntryNode();
17958 TargetLowering::ArgListTy Args;
17959 TargetLowering::ArgListEntry Entry;
17960 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17961 EVT ArgVT = Op->getOperand(i).getValueType();
17962 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17963 "Unexpected argument type for lowering");
17964 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17965 Entry.Node = StackPtr;
17966 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17968 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17969 Entry.Ty = PointerType::get(ArgTy,0);
17970 Entry.isSExt = false;
17971 Entry.isZExt = false;
17972 Args.push_back(Entry);
17975 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17978 TargetLowering::CallLoweringInfo CLI(DAG);
17979 CLI.setDebugLoc(dl).setChain(InChain)
17980 .setCallee(getLibcallCallingConv(LC),
17981 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17982 Callee, std::move(Args), 0)
17983 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17985 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17986 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17989 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17990 SelectionDAG &DAG) {
17991 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17992 EVT VT = Op0.getValueType();
17995 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17996 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17998 // PMULxD operations multiply each even value (starting at 0) of LHS with
17999 // the related value of RHS and produce a widen result.
18000 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18001 // => <2 x i64> <ae|cg>
18003 // In other word, to have all the results, we need to perform two PMULxD:
18004 // 1. one with the even values.
18005 // 2. one with the odd values.
18006 // To achieve #2, with need to place the odd values at an even position.
18008 // Place the odd value at an even position (basically, shift all values 1
18009 // step to the left):
18010 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18011 // <a|b|c|d> => <b|undef|d|undef>
18012 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18013 // <e|f|g|h> => <f|undef|h|undef>
18014 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18016 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18018 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18019 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18021 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18022 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18023 // => <2 x i64> <ae|cg>
18024 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18025 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18026 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18027 // => <2 x i64> <bf|dh>
18028 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18029 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18031 // Shuffle it back into the right order.
18032 SDValue Highs, Lows;
18033 if (VT == MVT::v8i32) {
18034 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18035 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18036 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18037 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18039 const int HighMask[] = {1, 5, 3, 7};
18040 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18041 const int LowMask[] = {0, 4, 2, 6};
18042 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18045 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18046 // unsigned multiply.
18047 if (IsSigned && !Subtarget->hasSSE41()) {
18049 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18050 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18051 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18052 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18053 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18055 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18056 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18059 // The first result of MUL_LOHI is actually the low value, followed by the
18061 SDValue Ops[] = {Lows, Highs};
18062 return DAG.getMergeValues(Ops, dl);
18065 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18066 const X86Subtarget *Subtarget) {
18067 MVT VT = Op.getSimpleValueType();
18069 SDValue R = Op.getOperand(0);
18070 SDValue Amt = Op.getOperand(1);
18072 // Optimize shl/srl/sra with constant shift amount.
18073 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18074 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18075 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18077 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18078 (Subtarget->hasInt256() &&
18079 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18080 (Subtarget->hasAVX512() &&
18081 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18082 if (Op.getOpcode() == ISD::SHL)
18083 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18085 if (Op.getOpcode() == ISD::SRL)
18086 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18088 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18089 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18093 if (VT == MVT::v16i8) {
18094 if (Op.getOpcode() == ISD::SHL) {
18095 // Make a large shift.
18096 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18097 MVT::v8i16, R, ShiftAmt,
18099 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18100 // Zero out the rightmost bits.
18101 SmallVector<SDValue, 16> V(16,
18102 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18104 return DAG.getNode(ISD::AND, dl, VT, SHL,
18105 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18107 if (Op.getOpcode() == ISD::SRL) {
18108 // Make a large shift.
18109 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18110 MVT::v8i16, R, ShiftAmt,
18112 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18113 // Zero out the leftmost bits.
18114 SmallVector<SDValue, 16> V(16,
18115 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18117 return DAG.getNode(ISD::AND, dl, VT, SRL,
18118 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18120 if (Op.getOpcode() == ISD::SRA) {
18121 if (ShiftAmt == 7) {
18122 // R s>> 7 === R s< 0
18123 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18124 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18127 // R s>> a === ((R u>> a) ^ m) - m
18128 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18129 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18131 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18132 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18133 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18136 llvm_unreachable("Unknown shift opcode.");
18139 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18140 if (Op.getOpcode() == ISD::SHL) {
18141 // Make a large shift.
18142 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18143 MVT::v16i16, R, ShiftAmt,
18145 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18146 // Zero out the rightmost bits.
18147 SmallVector<SDValue, 32> V(32,
18148 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18150 return DAG.getNode(ISD::AND, dl, VT, SHL,
18151 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18153 if (Op.getOpcode() == ISD::SRL) {
18154 // Make a large shift.
18155 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18156 MVT::v16i16, R, ShiftAmt,
18158 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18159 // Zero out the leftmost bits.
18160 SmallVector<SDValue, 32> V(32,
18161 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18163 return DAG.getNode(ISD::AND, dl, VT, SRL,
18164 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18166 if (Op.getOpcode() == ISD::SRA) {
18167 if (ShiftAmt == 7) {
18168 // R s>> 7 === R s< 0
18169 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18170 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18173 // R s>> a === ((R u>> a) ^ m) - m
18174 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18175 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18177 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18178 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18179 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18182 llvm_unreachable("Unknown shift opcode.");
18187 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18188 if (!Subtarget->is64Bit() &&
18189 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18190 Amt.getOpcode() == ISD::BITCAST &&
18191 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18192 Amt = Amt.getOperand(0);
18193 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18194 VT.getVectorNumElements();
18195 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18196 uint64_t ShiftAmt = 0;
18197 for (unsigned i = 0; i != Ratio; ++i) {
18198 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18202 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18204 // Check remaining shift amounts.
18205 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18206 uint64_t ShAmt = 0;
18207 for (unsigned j = 0; j != Ratio; ++j) {
18208 ConstantSDNode *C =
18209 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18213 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18215 if (ShAmt != ShiftAmt)
18218 switch (Op.getOpcode()) {
18220 llvm_unreachable("Unknown shift opcode!");
18222 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18225 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18228 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18236 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18237 const X86Subtarget* Subtarget) {
18238 MVT VT = Op.getSimpleValueType();
18240 SDValue R = Op.getOperand(0);
18241 SDValue Amt = Op.getOperand(1);
18243 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18244 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18245 (Subtarget->hasInt256() &&
18246 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18247 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18248 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18250 EVT EltVT = VT.getVectorElementType();
18252 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18253 unsigned NumElts = VT.getVectorNumElements();
18255 for (i = 0; i != NumElts; ++i) {
18256 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
18260 for (j = i; j != NumElts; ++j) {
18261 SDValue Arg = Amt.getOperand(j);
18262 if (Arg.getOpcode() == ISD::UNDEF) continue;
18263 if (Arg != Amt.getOperand(i))
18266 if (i != NumElts && j == NumElts)
18267 BaseShAmt = Amt.getOperand(i);
18269 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18270 Amt = Amt.getOperand(0);
18271 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18272 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18273 SDValue InVec = Amt.getOperand(0);
18274 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18275 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18277 for (; i != NumElts; ++i) {
18278 SDValue Arg = InVec.getOperand(i);
18279 if (Arg.getOpcode() == ISD::UNDEF) continue;
18283 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18284 if (ConstantSDNode *C =
18285 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18286 unsigned SplatIdx =
18287 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18288 if (C->getZExtValue() == SplatIdx)
18289 BaseShAmt = InVec.getOperand(1);
18292 if (!BaseShAmt.getNode())
18293 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18294 DAG.getIntPtrConstant(0));
18298 if (BaseShAmt.getNode()) {
18299 if (EltVT.bitsGT(MVT::i32))
18300 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18301 else if (EltVT.bitsLT(MVT::i32))
18302 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18304 switch (Op.getOpcode()) {
18306 llvm_unreachable("Unknown shift opcode!");
18308 switch (VT.SimpleTy) {
18309 default: return SDValue();
18318 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18321 switch (VT.SimpleTy) {
18322 default: return SDValue();
18329 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18332 switch (VT.SimpleTy) {
18333 default: return SDValue();
18342 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18348 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18349 if (!Subtarget->is64Bit() &&
18350 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18351 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18352 Amt.getOpcode() == ISD::BITCAST &&
18353 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18354 Amt = Amt.getOperand(0);
18355 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18356 VT.getVectorNumElements();
18357 std::vector<SDValue> Vals(Ratio);
18358 for (unsigned i = 0; i != Ratio; ++i)
18359 Vals[i] = Amt.getOperand(i);
18360 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18361 for (unsigned j = 0; j != Ratio; ++j)
18362 if (Vals[j] != Amt.getOperand(i + j))
18365 switch (Op.getOpcode()) {
18367 llvm_unreachable("Unknown shift opcode!");
18369 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18371 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18373 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18380 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18381 SelectionDAG &DAG) {
18382 MVT VT = Op.getSimpleValueType();
18384 SDValue R = Op.getOperand(0);
18385 SDValue Amt = Op.getOperand(1);
18388 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18389 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18391 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18395 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18399 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18401 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18402 if (Subtarget->hasInt256()) {
18403 if (Op.getOpcode() == ISD::SRL &&
18404 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18405 VT == MVT::v4i64 || VT == MVT::v8i32))
18407 if (Op.getOpcode() == ISD::SHL &&
18408 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18409 VT == MVT::v4i64 || VT == MVT::v8i32))
18411 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18415 // If possible, lower this packed shift into a vector multiply instead of
18416 // expanding it into a sequence of scalar shifts.
18417 // Do this only if the vector shift count is a constant build_vector.
18418 if (Op.getOpcode() == ISD::SHL &&
18419 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18420 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18421 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18422 SmallVector<SDValue, 8> Elts;
18423 EVT SVT = VT.getScalarType();
18424 unsigned SVTBits = SVT.getSizeInBits();
18425 const APInt &One = APInt(SVTBits, 1);
18426 unsigned NumElems = VT.getVectorNumElements();
18428 for (unsigned i=0; i !=NumElems; ++i) {
18429 SDValue Op = Amt->getOperand(i);
18430 if (Op->getOpcode() == ISD::UNDEF) {
18431 Elts.push_back(Op);
18435 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18436 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18437 uint64_t ShAmt = C.getZExtValue();
18438 if (ShAmt >= SVTBits) {
18439 Elts.push_back(DAG.getUNDEF(SVT));
18442 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18444 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18445 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18448 // Lower SHL with variable shift amount.
18449 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18450 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18452 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18453 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18454 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18455 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18458 // If possible, lower this shift as a sequence of two shifts by
18459 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18461 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18463 // Could be rewritten as:
18464 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18466 // The advantage is that the two shifts from the example would be
18467 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18468 // the vector shift into four scalar shifts plus four pairs of vector
18470 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18471 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18472 unsigned TargetOpcode = X86ISD::MOVSS;
18473 bool CanBeSimplified;
18474 // The splat value for the first packed shift (the 'X' from the example).
18475 SDValue Amt1 = Amt->getOperand(0);
18476 // The splat value for the second packed shift (the 'Y' from the example).
18477 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18478 Amt->getOperand(2);
18480 // See if it is possible to replace this node with a sequence of
18481 // two shifts followed by a MOVSS/MOVSD
18482 if (VT == MVT::v4i32) {
18483 // Check if it is legal to use a MOVSS.
18484 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18485 Amt2 == Amt->getOperand(3);
18486 if (!CanBeSimplified) {
18487 // Otherwise, check if we can still simplify this node using a MOVSD.
18488 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18489 Amt->getOperand(2) == Amt->getOperand(3);
18490 TargetOpcode = X86ISD::MOVSD;
18491 Amt2 = Amt->getOperand(2);
18494 // Do similar checks for the case where the machine value type
18496 CanBeSimplified = Amt1 == Amt->getOperand(1);
18497 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18498 CanBeSimplified = Amt2 == Amt->getOperand(i);
18500 if (!CanBeSimplified) {
18501 TargetOpcode = X86ISD::MOVSD;
18502 CanBeSimplified = true;
18503 Amt2 = Amt->getOperand(4);
18504 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18505 CanBeSimplified = Amt1 == Amt->getOperand(i);
18506 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18507 CanBeSimplified = Amt2 == Amt->getOperand(j);
18511 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18512 isa<ConstantSDNode>(Amt2)) {
18513 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18514 EVT CastVT = MVT::v4i32;
18516 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18517 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18519 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18520 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18521 if (TargetOpcode == X86ISD::MOVSD)
18522 CastVT = MVT::v2i64;
18523 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18524 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18525 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18527 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18531 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18532 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18535 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18536 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18538 // Turn 'a' into a mask suitable for VSELECT
18539 SDValue VSelM = DAG.getConstant(0x80, VT);
18540 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18541 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18543 SDValue CM1 = DAG.getConstant(0x0f, VT);
18544 SDValue CM2 = DAG.getConstant(0x3f, VT);
18546 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18547 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18548 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18549 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18550 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18553 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18554 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18555 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18557 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18558 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18559 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18560 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18561 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18564 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18565 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18566 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18568 // return VSELECT(r, r+r, a);
18569 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18570 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18574 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18575 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18576 // solution better.
18577 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18578 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18580 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18581 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18582 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18583 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18584 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18587 // Decompose 256-bit shifts into smaller 128-bit shifts.
18588 if (VT.is256BitVector()) {
18589 unsigned NumElems = VT.getVectorNumElements();
18590 MVT EltVT = VT.getVectorElementType();
18591 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18593 // Extract the two vectors
18594 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18595 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18597 // Recreate the shift amount vectors
18598 SDValue Amt1, Amt2;
18599 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18600 // Constant shift amount
18601 SmallVector<SDValue, 4> Amt1Csts;
18602 SmallVector<SDValue, 4> Amt2Csts;
18603 for (unsigned i = 0; i != NumElems/2; ++i)
18604 Amt1Csts.push_back(Amt->getOperand(i));
18605 for (unsigned i = NumElems/2; i != NumElems; ++i)
18606 Amt2Csts.push_back(Amt->getOperand(i));
18608 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18609 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18611 // Variable shift amount
18612 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18613 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18616 // Issue new vector shifts for the smaller types
18617 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18618 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18620 // Concatenate the result back
18621 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18627 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18628 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18629 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18630 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18631 // has only one use.
18632 SDNode *N = Op.getNode();
18633 SDValue LHS = N->getOperand(0);
18634 SDValue RHS = N->getOperand(1);
18635 unsigned BaseOp = 0;
18638 switch (Op.getOpcode()) {
18639 default: llvm_unreachable("Unknown ovf instruction!");
18641 // A subtract of one will be selected as a INC. Note that INC doesn't
18642 // set CF, so we can't do this for UADDO.
18643 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18645 BaseOp = X86ISD::INC;
18646 Cond = X86::COND_O;
18649 BaseOp = X86ISD::ADD;
18650 Cond = X86::COND_O;
18653 BaseOp = X86ISD::ADD;
18654 Cond = X86::COND_B;
18657 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18658 // set CF, so we can't do this for USUBO.
18659 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18661 BaseOp = X86ISD::DEC;
18662 Cond = X86::COND_O;
18665 BaseOp = X86ISD::SUB;
18666 Cond = X86::COND_O;
18669 BaseOp = X86ISD::SUB;
18670 Cond = X86::COND_B;
18673 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18674 Cond = X86::COND_O;
18676 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18677 if (N->getValueType(0) == MVT::i8) {
18678 BaseOp = X86ISD::UMUL8;
18679 Cond = X86::COND_O;
18682 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18684 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18687 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18688 DAG.getConstant(X86::COND_O, MVT::i32),
18689 SDValue(Sum.getNode(), 2));
18691 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18695 // Also sets EFLAGS.
18696 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18697 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18700 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18701 DAG.getConstant(Cond, MVT::i32),
18702 SDValue(Sum.getNode(), 1));
18704 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18707 // Sign extension of the low part of vector elements. This may be used either
18708 // when sign extend instructions are not available or if the vector element
18709 // sizes already match the sign-extended size. If the vector elements are in
18710 // their pre-extended size and sign extend instructions are available, that will
18711 // be handled by LowerSIGN_EXTEND.
18712 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18713 SelectionDAG &DAG) const {
18715 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18716 MVT VT = Op.getSimpleValueType();
18718 if (!Subtarget->hasSSE2() || !VT.isVector())
18721 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18722 ExtraVT.getScalarType().getSizeInBits();
18724 switch (VT.SimpleTy) {
18725 default: return SDValue();
18728 if (!Subtarget->hasFp256())
18730 if (!Subtarget->hasInt256()) {
18731 // needs to be split
18732 unsigned NumElems = VT.getVectorNumElements();
18734 // Extract the LHS vectors
18735 SDValue LHS = Op.getOperand(0);
18736 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18737 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18739 MVT EltVT = VT.getVectorElementType();
18740 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18742 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18743 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18744 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18746 SDValue Extra = DAG.getValueType(ExtraVT);
18748 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18749 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18751 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18756 SDValue Op0 = Op.getOperand(0);
18758 // This is a sign extension of some low part of vector elements without
18759 // changing the size of the vector elements themselves:
18760 // Shift-Left + Shift-Right-Algebraic.
18761 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18763 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18769 /// Returns true if the operand type is exactly twice the native width, and
18770 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18771 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18772 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18773 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18774 const X86Subtarget &Subtarget =
18775 getTargetMachine().getSubtarget<X86Subtarget>();
18776 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18779 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18780 else if (OpWidth == 128)
18781 return Subtarget.hasCmpxchg16b();
18786 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18787 return needsCmpXchgNb(SI->getValueOperand()->getType());
18790 // Note: this turns large loads into lock cmpxchg8b/16b.
18791 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18792 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18793 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18794 return needsCmpXchgNb(PTy->getElementType());
18797 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18798 const X86Subtarget &Subtarget =
18799 getTargetMachine().getSubtarget<X86Subtarget>();
18800 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18801 const Type *MemType = AI->getType();
18803 // If the operand is too big, we must see if cmpxchg8/16b is available
18804 // and default to library calls otherwise.
18805 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18806 return needsCmpXchgNb(MemType);
18808 AtomicRMWInst::BinOp Op = AI->getOperation();
18811 llvm_unreachable("Unknown atomic operation");
18812 case AtomicRMWInst::Xchg:
18813 case AtomicRMWInst::Add:
18814 case AtomicRMWInst::Sub:
18815 // It's better to use xadd, xsub or xchg for these in all cases.
18817 case AtomicRMWInst::Or:
18818 case AtomicRMWInst::And:
18819 case AtomicRMWInst::Xor:
18820 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18821 // prefix to a normal instruction for these operations.
18822 return !AI->use_empty();
18823 case AtomicRMWInst::Nand:
18824 case AtomicRMWInst::Max:
18825 case AtomicRMWInst::Min:
18826 case AtomicRMWInst::UMax:
18827 case AtomicRMWInst::UMin:
18828 // These always require a non-trivial set of data operations on x86. We must
18829 // use a cmpxchg loop.
18834 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18835 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18836 // no-sse2). There isn't any reason to disable it if the target processor
18838 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18842 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18843 const X86Subtarget &Subtarget =
18844 getTargetMachine().getSubtarget<X86Subtarget>();
18845 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18846 const Type *MemType = AI->getType();
18847 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18848 // there is no benefit in turning such RMWs into loads, and it is actually
18849 // harmful as it introduces a mfence.
18850 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18853 auto Builder = IRBuilder<>(AI);
18854 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18855 auto SynchScope = AI->getSynchScope();
18856 // We must restrict the ordering to avoid generating loads with Release or
18857 // ReleaseAcquire orderings.
18858 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18859 auto Ptr = AI->getPointerOperand();
18861 // Before the load we need a fence. Here is an example lifted from
18862 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18865 // x.store(1, relaxed);
18866 // r1 = y.fetch_add(0, release);
18868 // y.fetch_add(42, acquire);
18869 // r2 = x.load(relaxed);
18870 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18871 // lowered to just a load without a fence. A mfence flushes the store buffer,
18872 // making the optimization clearly correct.
18873 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18874 // otherwise, we might be able to be more agressive on relaxed idempotent
18875 // rmw. In practice, they do not look useful, so we don't try to be
18876 // especially clever.
18877 if (SynchScope == SingleThread) {
18878 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18879 // the IR level, so we must wrap it in an intrinsic.
18881 } else if (hasMFENCE(Subtarget)) {
18882 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18883 Intrinsic::x86_sse2_mfence);
18884 Builder.CreateCall(MFence);
18886 // FIXME: it might make sense to use a locked operation here but on a
18887 // different cache-line to prevent cache-line bouncing. In practice it
18888 // is probably a small win, and x86 processors without mfence are rare
18889 // enough that we do not bother.
18893 // Finally we can emit the atomic load.
18894 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18895 AI->getType()->getPrimitiveSizeInBits());
18896 Loaded->setAtomic(Order, SynchScope);
18897 AI->replaceAllUsesWith(Loaded);
18898 AI->eraseFromParent();
18902 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18903 SelectionDAG &DAG) {
18905 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18906 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18907 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18908 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18910 // The only fence that needs an instruction is a sequentially-consistent
18911 // cross-thread fence.
18912 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18913 if (hasMFENCE(*Subtarget))
18914 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18916 SDValue Chain = Op.getOperand(0);
18917 SDValue Zero = DAG.getConstant(0, MVT::i32);
18919 DAG.getRegister(X86::ESP, MVT::i32), // Base
18920 DAG.getTargetConstant(1, MVT::i8), // Scale
18921 DAG.getRegister(0, MVT::i32), // Index
18922 DAG.getTargetConstant(0, MVT::i32), // Disp
18923 DAG.getRegister(0, MVT::i32), // Segment.
18927 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18928 return SDValue(Res, 0);
18931 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18932 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18935 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18936 SelectionDAG &DAG) {
18937 MVT T = Op.getSimpleValueType();
18941 switch(T.SimpleTy) {
18942 default: llvm_unreachable("Invalid value type!");
18943 case MVT::i8: Reg = X86::AL; size = 1; break;
18944 case MVT::i16: Reg = X86::AX; size = 2; break;
18945 case MVT::i32: Reg = X86::EAX; size = 4; break;
18947 assert(Subtarget->is64Bit() && "Node not type legal!");
18948 Reg = X86::RAX; size = 8;
18951 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18952 Op.getOperand(2), SDValue());
18953 SDValue Ops[] = { cpIn.getValue(0),
18956 DAG.getTargetConstant(size, MVT::i8),
18957 cpIn.getValue(1) };
18958 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18959 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18960 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18964 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18965 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18966 MVT::i32, cpOut.getValue(2));
18967 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18968 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18970 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18971 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18972 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18976 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18977 SelectionDAG &DAG) {
18978 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18979 MVT DstVT = Op.getSimpleValueType();
18981 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18982 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18983 if (DstVT != MVT::f64)
18984 // This conversion needs to be expanded.
18987 SDValue InVec = Op->getOperand(0);
18989 unsigned NumElts = SrcVT.getVectorNumElements();
18990 EVT SVT = SrcVT.getVectorElementType();
18992 // Widen the vector in input in the case of MVT::v2i32.
18993 // Example: from MVT::v2i32 to MVT::v4i32.
18994 SmallVector<SDValue, 16> Elts;
18995 for (unsigned i = 0, e = NumElts; i != e; ++i)
18996 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18997 DAG.getIntPtrConstant(i)));
18999 // Explicitly mark the extra elements as Undef.
19000 SDValue Undef = DAG.getUNDEF(SVT);
19001 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19002 Elts.push_back(Undef);
19004 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19005 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19006 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19007 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19008 DAG.getIntPtrConstant(0));
19011 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19012 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19013 assert((DstVT == MVT::i64 ||
19014 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19015 "Unexpected custom BITCAST");
19016 // i64 <=> MMX conversions are Legal.
19017 if (SrcVT==MVT::i64 && DstVT.isVector())
19019 if (DstVT==MVT::i64 && SrcVT.isVector())
19021 // MMX <=> MMX conversions are Legal.
19022 if (SrcVT.isVector() && DstVT.isVector())
19024 // All other conversions need to be expanded.
19028 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19029 SDNode *Node = Op.getNode();
19031 EVT T = Node->getValueType(0);
19032 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19033 DAG.getConstant(0, T), Node->getOperand(2));
19034 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19035 cast<AtomicSDNode>(Node)->getMemoryVT(),
19036 Node->getOperand(0),
19037 Node->getOperand(1), negOp,
19038 cast<AtomicSDNode>(Node)->getMemOperand(),
19039 cast<AtomicSDNode>(Node)->getOrdering(),
19040 cast<AtomicSDNode>(Node)->getSynchScope());
19043 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19044 SDNode *Node = Op.getNode();
19046 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19048 // Convert seq_cst store -> xchg
19049 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19050 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19051 // (The only way to get a 16-byte store is cmpxchg16b)
19052 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19053 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19054 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19055 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19056 cast<AtomicSDNode>(Node)->getMemoryVT(),
19057 Node->getOperand(0),
19058 Node->getOperand(1), Node->getOperand(2),
19059 cast<AtomicSDNode>(Node)->getMemOperand(),
19060 cast<AtomicSDNode>(Node)->getOrdering(),
19061 cast<AtomicSDNode>(Node)->getSynchScope());
19062 return Swap.getValue(1);
19064 // Other atomic stores have a simple pattern.
19068 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19069 EVT VT = Op.getNode()->getSimpleValueType(0);
19071 // Let legalize expand this if it isn't a legal type yet.
19072 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19075 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19078 bool ExtraOp = false;
19079 switch (Op.getOpcode()) {
19080 default: llvm_unreachable("Invalid code");
19081 case ISD::ADDC: Opc = X86ISD::ADD; break;
19082 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19083 case ISD::SUBC: Opc = X86ISD::SUB; break;
19084 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19088 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19090 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19091 Op.getOperand(1), Op.getOperand(2));
19094 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19095 SelectionDAG &DAG) {
19096 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19098 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19099 // which returns the values as { float, float } (in XMM0) or
19100 // { double, double } (which is returned in XMM0, XMM1).
19102 SDValue Arg = Op.getOperand(0);
19103 EVT ArgVT = Arg.getValueType();
19104 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19106 TargetLowering::ArgListTy Args;
19107 TargetLowering::ArgListEntry Entry;
19111 Entry.isSExt = false;
19112 Entry.isZExt = false;
19113 Args.push_back(Entry);
19115 bool isF64 = ArgVT == MVT::f64;
19116 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19117 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19118 // the results are returned via SRet in memory.
19119 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19121 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19123 Type *RetTy = isF64
19124 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19125 : (Type*)VectorType::get(ArgTy, 4);
19127 TargetLowering::CallLoweringInfo CLI(DAG);
19128 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19129 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19131 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19134 // Returned in xmm0 and xmm1.
19135 return CallResult.first;
19137 // Returned in bits 0:31 and 32:64 xmm0.
19138 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19139 CallResult.first, DAG.getIntPtrConstant(0));
19140 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19141 CallResult.first, DAG.getIntPtrConstant(1));
19142 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19143 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19146 /// LowerOperation - Provide custom lowering hooks for some operations.
19148 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19149 switch (Op.getOpcode()) {
19150 default: llvm_unreachable("Should not custom lower this!");
19151 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19152 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19153 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19154 return LowerCMP_SWAP(Op, Subtarget, DAG);
19155 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19156 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19157 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19158 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19159 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19160 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19161 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19162 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19163 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19164 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19165 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19166 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19167 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19168 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19169 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19170 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19171 case ISD::SHL_PARTS:
19172 case ISD::SRA_PARTS:
19173 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19174 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19175 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19176 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19177 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19178 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19179 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19180 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19181 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19182 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19183 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19185 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19186 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19187 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19188 case ISD::SETCC: return LowerSETCC(Op, DAG);
19189 case ISD::SELECT: return LowerSELECT(Op, DAG);
19190 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19191 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19192 case ISD::VASTART: return LowerVASTART(Op, DAG);
19193 case ISD::VAARG: return LowerVAARG(Op, DAG);
19194 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19195 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19196 case ISD::INTRINSIC_VOID:
19197 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19198 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19199 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19200 case ISD::FRAME_TO_ARGS_OFFSET:
19201 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19202 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19203 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19204 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19205 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19206 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19207 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19208 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19209 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19210 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19211 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19212 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19213 case ISD::UMUL_LOHI:
19214 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19217 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19223 case ISD::UMULO: return LowerXALUO(Op, DAG);
19224 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19225 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19229 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19230 case ISD::ADD: return LowerADD(Op, DAG);
19231 case ISD::SUB: return LowerSUB(Op, DAG);
19232 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19236 /// ReplaceNodeResults - Replace a node with an illegal result type
19237 /// with a new node built out of custom code.
19238 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19239 SmallVectorImpl<SDValue>&Results,
19240 SelectionDAG &DAG) const {
19242 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19243 switch (N->getOpcode()) {
19245 llvm_unreachable("Do not know how to custom type legalize this operation!");
19246 case ISD::SIGN_EXTEND_INREG:
19251 // We don't want to expand or promote these.
19258 case ISD::UDIVREM: {
19259 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19260 Results.push_back(V);
19263 case ISD::FP_TO_SINT:
19264 case ISD::FP_TO_UINT: {
19265 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19267 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19270 std::pair<SDValue,SDValue> Vals =
19271 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19272 SDValue FIST = Vals.first, StackSlot = Vals.second;
19273 if (FIST.getNode()) {
19274 EVT VT = N->getValueType(0);
19275 // Return a load from the stack slot.
19276 if (StackSlot.getNode())
19277 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19278 MachinePointerInfo(),
19279 false, false, false, 0));
19281 Results.push_back(FIST);
19285 case ISD::UINT_TO_FP: {
19286 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19287 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19288 N->getValueType(0) != MVT::v2f32)
19290 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19292 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19294 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19295 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19296 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19297 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19298 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19299 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19302 case ISD::FP_ROUND: {
19303 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19305 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19306 Results.push_back(V);
19309 case ISD::INTRINSIC_W_CHAIN: {
19310 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19312 default : llvm_unreachable("Do not know how to custom type "
19313 "legalize this intrinsic operation!");
19314 case Intrinsic::x86_rdtsc:
19315 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19317 case Intrinsic::x86_rdtscp:
19318 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19320 case Intrinsic::x86_rdpmc:
19321 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19324 case ISD::READCYCLECOUNTER: {
19325 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19328 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19329 EVT T = N->getValueType(0);
19330 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19331 bool Regs64bit = T == MVT::i128;
19332 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19333 SDValue cpInL, cpInH;
19334 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19335 DAG.getConstant(0, HalfT));
19336 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19337 DAG.getConstant(1, HalfT));
19338 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19339 Regs64bit ? X86::RAX : X86::EAX,
19341 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19342 Regs64bit ? X86::RDX : X86::EDX,
19343 cpInH, cpInL.getValue(1));
19344 SDValue swapInL, swapInH;
19345 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19346 DAG.getConstant(0, HalfT));
19347 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19348 DAG.getConstant(1, HalfT));
19349 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19350 Regs64bit ? X86::RBX : X86::EBX,
19351 swapInL, cpInH.getValue(1));
19352 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19353 Regs64bit ? X86::RCX : X86::ECX,
19354 swapInH, swapInL.getValue(1));
19355 SDValue Ops[] = { swapInH.getValue(0),
19357 swapInH.getValue(1) };
19358 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19359 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19360 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19361 X86ISD::LCMPXCHG8_DAG;
19362 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19363 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19364 Regs64bit ? X86::RAX : X86::EAX,
19365 HalfT, Result.getValue(1));
19366 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19367 Regs64bit ? X86::RDX : X86::EDX,
19368 HalfT, cpOutL.getValue(2));
19369 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19371 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19372 MVT::i32, cpOutH.getValue(2));
19374 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19375 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19376 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19378 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19379 Results.push_back(Success);
19380 Results.push_back(EFLAGS.getValue(1));
19383 case ISD::ATOMIC_SWAP:
19384 case ISD::ATOMIC_LOAD_ADD:
19385 case ISD::ATOMIC_LOAD_SUB:
19386 case ISD::ATOMIC_LOAD_AND:
19387 case ISD::ATOMIC_LOAD_OR:
19388 case ISD::ATOMIC_LOAD_XOR:
19389 case ISD::ATOMIC_LOAD_NAND:
19390 case ISD::ATOMIC_LOAD_MIN:
19391 case ISD::ATOMIC_LOAD_MAX:
19392 case ISD::ATOMIC_LOAD_UMIN:
19393 case ISD::ATOMIC_LOAD_UMAX:
19394 case ISD::ATOMIC_LOAD: {
19395 // Delegate to generic TypeLegalization. Situations we can really handle
19396 // should have already been dealt with by AtomicExpandPass.cpp.
19399 case ISD::BITCAST: {
19400 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19401 EVT DstVT = N->getValueType(0);
19402 EVT SrcVT = N->getOperand(0)->getValueType(0);
19404 if (SrcVT != MVT::f64 ||
19405 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19408 unsigned NumElts = DstVT.getVectorNumElements();
19409 EVT SVT = DstVT.getVectorElementType();
19410 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19411 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19412 MVT::v2f64, N->getOperand(0));
19413 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19415 if (ExperimentalVectorWideningLegalization) {
19416 // If we are legalizing vectors by widening, we already have the desired
19417 // legal vector type, just return it.
19418 Results.push_back(ToVecInt);
19422 SmallVector<SDValue, 8> Elts;
19423 for (unsigned i = 0, e = NumElts; i != e; ++i)
19424 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19425 ToVecInt, DAG.getIntPtrConstant(i)));
19427 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19432 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19434 default: return nullptr;
19435 case X86ISD::BSF: return "X86ISD::BSF";
19436 case X86ISD::BSR: return "X86ISD::BSR";
19437 case X86ISD::SHLD: return "X86ISD::SHLD";
19438 case X86ISD::SHRD: return "X86ISD::SHRD";
19439 case X86ISD::FAND: return "X86ISD::FAND";
19440 case X86ISD::FANDN: return "X86ISD::FANDN";
19441 case X86ISD::FOR: return "X86ISD::FOR";
19442 case X86ISD::FXOR: return "X86ISD::FXOR";
19443 case X86ISD::FSRL: return "X86ISD::FSRL";
19444 case X86ISD::FILD: return "X86ISD::FILD";
19445 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19446 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19447 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19448 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19449 case X86ISD::FLD: return "X86ISD::FLD";
19450 case X86ISD::FST: return "X86ISD::FST";
19451 case X86ISD::CALL: return "X86ISD::CALL";
19452 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19453 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19454 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19455 case X86ISD::BT: return "X86ISD::BT";
19456 case X86ISD::CMP: return "X86ISD::CMP";
19457 case X86ISD::COMI: return "X86ISD::COMI";
19458 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19459 case X86ISD::CMPM: return "X86ISD::CMPM";
19460 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19461 case X86ISD::SETCC: return "X86ISD::SETCC";
19462 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19463 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19464 case X86ISD::CMOV: return "X86ISD::CMOV";
19465 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19466 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19467 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19468 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19469 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19470 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19471 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19472 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19473 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19474 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19475 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19476 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19477 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19478 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19479 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19480 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19481 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19482 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19483 case X86ISD::HADD: return "X86ISD::HADD";
19484 case X86ISD::HSUB: return "X86ISD::HSUB";
19485 case X86ISD::FHADD: return "X86ISD::FHADD";
19486 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19487 case X86ISD::UMAX: return "X86ISD::UMAX";
19488 case X86ISD::UMIN: return "X86ISD::UMIN";
19489 case X86ISD::SMAX: return "X86ISD::SMAX";
19490 case X86ISD::SMIN: return "X86ISD::SMIN";
19491 case X86ISD::FMAX: return "X86ISD::FMAX";
19492 case X86ISD::FMIN: return "X86ISD::FMIN";
19493 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19494 case X86ISD::FMINC: return "X86ISD::FMINC";
19495 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19496 case X86ISD::FRCP: return "X86ISD::FRCP";
19497 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19498 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19499 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19500 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19501 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19502 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19503 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19504 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19505 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19506 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19507 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19508 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19509 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19510 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19511 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19512 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19513 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19514 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19515 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19516 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19517 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19518 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19519 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19520 case X86ISD::VSHL: return "X86ISD::VSHL";
19521 case X86ISD::VSRL: return "X86ISD::VSRL";
19522 case X86ISD::VSRA: return "X86ISD::VSRA";
19523 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19524 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19525 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19526 case X86ISD::CMPP: return "X86ISD::CMPP";
19527 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19528 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19529 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19530 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19531 case X86ISD::ADD: return "X86ISD::ADD";
19532 case X86ISD::SUB: return "X86ISD::SUB";
19533 case X86ISD::ADC: return "X86ISD::ADC";
19534 case X86ISD::SBB: return "X86ISD::SBB";
19535 case X86ISD::SMUL: return "X86ISD::SMUL";
19536 case X86ISD::UMUL: return "X86ISD::UMUL";
19537 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19538 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19539 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19540 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19541 case X86ISD::INC: return "X86ISD::INC";
19542 case X86ISD::DEC: return "X86ISD::DEC";
19543 case X86ISD::OR: return "X86ISD::OR";
19544 case X86ISD::XOR: return "X86ISD::XOR";
19545 case X86ISD::AND: return "X86ISD::AND";
19546 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19547 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19548 case X86ISD::PTEST: return "X86ISD::PTEST";
19549 case X86ISD::TESTP: return "X86ISD::TESTP";
19550 case X86ISD::TESTM: return "X86ISD::TESTM";
19551 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19552 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19553 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19554 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19555 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19556 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19557 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19558 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19559 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19560 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19561 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19562 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19563 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19564 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19565 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19566 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19567 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19568 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19569 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19570 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19571 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19572 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19573 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19574 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19575 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19576 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19577 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19578 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19579 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19580 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19581 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19582 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19583 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19584 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19585 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19586 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19587 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19588 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19589 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19590 case X86ISD::SAHF: return "X86ISD::SAHF";
19591 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19592 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19593 case X86ISD::FMADD: return "X86ISD::FMADD";
19594 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19595 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19596 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19597 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19598 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19599 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19600 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19601 case X86ISD::XTEST: return "X86ISD::XTEST";
19605 // isLegalAddressingMode - Return true if the addressing mode represented
19606 // by AM is legal for this target, for a load/store of the specified type.
19607 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19609 // X86 supports extremely general addressing modes.
19610 CodeModel::Model M = getTargetMachine().getCodeModel();
19611 Reloc::Model R = getTargetMachine().getRelocationModel();
19613 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19614 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19619 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19621 // If a reference to this global requires an extra load, we can't fold it.
19622 if (isGlobalStubReference(GVFlags))
19625 // If BaseGV requires a register for the PIC base, we cannot also have a
19626 // BaseReg specified.
19627 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19630 // If lower 4G is not available, then we must use rip-relative addressing.
19631 if ((M != CodeModel::Small || R != Reloc::Static) &&
19632 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19636 switch (AM.Scale) {
19642 // These scales always work.
19647 // These scales are formed with basereg+scalereg. Only accept if there is
19652 default: // Other stuff never works.
19659 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19660 unsigned Bits = Ty->getScalarSizeInBits();
19662 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19663 // particularly cheaper than those without.
19667 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19668 // variable shifts just as cheap as scalar ones.
19669 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19672 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19673 // fully general vector.
19677 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19678 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19680 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19681 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19682 return NumBits1 > NumBits2;
19685 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19686 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19689 if (!isTypeLegal(EVT::getEVT(Ty1)))
19692 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19694 // Assuming the caller doesn't have a zeroext or signext return parameter,
19695 // truncation all the way down to i1 is valid.
19699 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19700 return isInt<32>(Imm);
19703 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19704 // Can also use sub to handle negated immediates.
19705 return isInt<32>(Imm);
19708 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19709 if (!VT1.isInteger() || !VT2.isInteger())
19711 unsigned NumBits1 = VT1.getSizeInBits();
19712 unsigned NumBits2 = VT2.getSizeInBits();
19713 return NumBits1 > NumBits2;
19716 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19717 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19718 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19721 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19722 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19723 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19726 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19727 EVT VT1 = Val.getValueType();
19728 if (isZExtFree(VT1, VT2))
19731 if (Val.getOpcode() != ISD::LOAD)
19734 if (!VT1.isSimple() || !VT1.isInteger() ||
19735 !VT2.isSimple() || !VT2.isInteger())
19738 switch (VT1.getSimpleVT().SimpleTy) {
19743 // X86 has 8, 16, and 32-bit zero-extending loads.
19751 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19752 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19755 VT = VT.getScalarType();
19757 if (!VT.isSimple())
19760 switch (VT.getSimpleVT().SimpleTy) {
19771 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19772 // i16 instructions are longer (0x66 prefix) and potentially slower.
19773 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19776 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19777 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19778 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19779 /// are assumed to be legal.
19781 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19783 if (!VT.isSimple())
19786 MVT SVT = VT.getSimpleVT();
19788 // Very little shuffling can be done for 64-bit vectors right now.
19789 if (VT.getSizeInBits() == 64)
19792 // If this is a single-input shuffle with no 128 bit lane crossings we can
19793 // lower it into pshufb.
19794 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19795 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19796 bool isLegal = true;
19797 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19798 if (M[I] >= (int)SVT.getVectorNumElements() ||
19799 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19808 // FIXME: blends, shifts.
19809 return (SVT.getVectorNumElements() == 2 ||
19810 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19811 isMOVLMask(M, SVT) ||
19812 isMOVHLPSMask(M, SVT) ||
19813 isSHUFPMask(M, SVT) ||
19814 isSHUFPMask(M, SVT, /* Commuted */ true) ||
19815 isPSHUFDMask(M, SVT) ||
19816 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
19817 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19818 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19819 isPALIGNRMask(M, SVT, Subtarget) ||
19820 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19821 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19822 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19823 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19824 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19825 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19829 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19831 if (!VT.isSimple())
19834 MVT SVT = VT.getSimpleVT();
19835 unsigned NumElts = SVT.getVectorNumElements();
19836 // FIXME: This collection of masks seems suspect.
19839 if (NumElts == 4 && SVT.is128BitVector()) {
19840 return (isMOVLMask(Mask, SVT) ||
19841 isCommutedMOVLMask(Mask, SVT, true) ||
19842 isSHUFPMask(Mask, SVT) ||
19843 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19844 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19845 Subtarget->hasInt256()));
19850 //===----------------------------------------------------------------------===//
19851 // X86 Scheduler Hooks
19852 //===----------------------------------------------------------------------===//
19854 /// Utility function to emit xbegin specifying the start of an RTM region.
19855 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19856 const TargetInstrInfo *TII) {
19857 DebugLoc DL = MI->getDebugLoc();
19859 const BasicBlock *BB = MBB->getBasicBlock();
19860 MachineFunction::iterator I = MBB;
19863 // For the v = xbegin(), we generate
19874 MachineBasicBlock *thisMBB = MBB;
19875 MachineFunction *MF = MBB->getParent();
19876 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19877 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19878 MF->insert(I, mainMBB);
19879 MF->insert(I, sinkMBB);
19881 // Transfer the remainder of BB and its successor edges to sinkMBB.
19882 sinkMBB->splice(sinkMBB->begin(), MBB,
19883 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19884 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19888 // # fallthrough to mainMBB
19889 // # abortion to sinkMBB
19890 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19891 thisMBB->addSuccessor(mainMBB);
19892 thisMBB->addSuccessor(sinkMBB);
19896 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19897 mainMBB->addSuccessor(sinkMBB);
19900 // EAX is live into the sinkMBB
19901 sinkMBB->addLiveIn(X86::EAX);
19902 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19903 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19906 MI->eraseFromParent();
19910 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19911 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19912 // in the .td file.
19913 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19914 const TargetInstrInfo *TII) {
19916 switch (MI->getOpcode()) {
19917 default: llvm_unreachable("illegal opcode!");
19918 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19919 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19920 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19921 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19922 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19923 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19924 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19925 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19928 DebugLoc dl = MI->getDebugLoc();
19929 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19931 unsigned NumArgs = MI->getNumOperands();
19932 for (unsigned i = 1; i < NumArgs; ++i) {
19933 MachineOperand &Op = MI->getOperand(i);
19934 if (!(Op.isReg() && Op.isImplicit()))
19935 MIB.addOperand(Op);
19937 if (MI->hasOneMemOperand())
19938 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19940 BuildMI(*BB, MI, dl,
19941 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19942 .addReg(X86::XMM0);
19944 MI->eraseFromParent();
19948 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19949 // defs in an instruction pattern
19950 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19951 const TargetInstrInfo *TII) {
19953 switch (MI->getOpcode()) {
19954 default: llvm_unreachable("illegal opcode!");
19955 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19956 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19957 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19958 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19959 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19960 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19961 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19962 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19965 DebugLoc dl = MI->getDebugLoc();
19966 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19968 unsigned NumArgs = MI->getNumOperands(); // remove the results
19969 for (unsigned i = 1; i < NumArgs; ++i) {
19970 MachineOperand &Op = MI->getOperand(i);
19971 if (!(Op.isReg() && Op.isImplicit()))
19972 MIB.addOperand(Op);
19974 if (MI->hasOneMemOperand())
19975 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19977 BuildMI(*BB, MI, dl,
19978 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19981 MI->eraseFromParent();
19985 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19986 const TargetInstrInfo *TII,
19987 const X86Subtarget* Subtarget) {
19988 DebugLoc dl = MI->getDebugLoc();
19990 // Address into RAX/EAX, other two args into ECX, EDX.
19991 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19992 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19993 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19994 for (int i = 0; i < X86::AddrNumOperands; ++i)
19995 MIB.addOperand(MI->getOperand(i));
19997 unsigned ValOps = X86::AddrNumOperands;
19998 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19999 .addReg(MI->getOperand(ValOps).getReg());
20000 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20001 .addReg(MI->getOperand(ValOps+1).getReg());
20003 // The instruction doesn't actually take any operands though.
20004 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20006 MI->eraseFromParent(); // The pseudo is gone now.
20010 MachineBasicBlock *
20011 X86TargetLowering::EmitVAARG64WithCustomInserter(
20013 MachineBasicBlock *MBB) const {
20014 // Emit va_arg instruction on X86-64.
20016 // Operands to this pseudo-instruction:
20017 // 0 ) Output : destination address (reg)
20018 // 1-5) Input : va_list address (addr, i64mem)
20019 // 6 ) ArgSize : Size (in bytes) of vararg type
20020 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20021 // 8 ) Align : Alignment of type
20022 // 9 ) EFLAGS (implicit-def)
20024 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20025 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20027 unsigned DestReg = MI->getOperand(0).getReg();
20028 MachineOperand &Base = MI->getOperand(1);
20029 MachineOperand &Scale = MI->getOperand(2);
20030 MachineOperand &Index = MI->getOperand(3);
20031 MachineOperand &Disp = MI->getOperand(4);
20032 MachineOperand &Segment = MI->getOperand(5);
20033 unsigned ArgSize = MI->getOperand(6).getImm();
20034 unsigned ArgMode = MI->getOperand(7).getImm();
20035 unsigned Align = MI->getOperand(8).getImm();
20037 // Memory Reference
20038 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20039 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20040 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20042 // Machine Information
20043 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20044 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20045 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20046 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20047 DebugLoc DL = MI->getDebugLoc();
20049 // struct va_list {
20052 // i64 overflow_area (address)
20053 // i64 reg_save_area (address)
20055 // sizeof(va_list) = 24
20056 // alignment(va_list) = 8
20058 unsigned TotalNumIntRegs = 6;
20059 unsigned TotalNumXMMRegs = 8;
20060 bool UseGPOffset = (ArgMode == 1);
20061 bool UseFPOffset = (ArgMode == 2);
20062 unsigned MaxOffset = TotalNumIntRegs * 8 +
20063 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20065 /* Align ArgSize to a multiple of 8 */
20066 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20067 bool NeedsAlign = (Align > 8);
20069 MachineBasicBlock *thisMBB = MBB;
20070 MachineBasicBlock *overflowMBB;
20071 MachineBasicBlock *offsetMBB;
20072 MachineBasicBlock *endMBB;
20074 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20075 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20076 unsigned OffsetReg = 0;
20078 if (!UseGPOffset && !UseFPOffset) {
20079 // If we only pull from the overflow region, we don't create a branch.
20080 // We don't need to alter control flow.
20081 OffsetDestReg = 0; // unused
20082 OverflowDestReg = DestReg;
20084 offsetMBB = nullptr;
20085 overflowMBB = thisMBB;
20088 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20089 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20090 // If not, pull from overflow_area. (branch to overflowMBB)
20095 // offsetMBB overflowMBB
20100 // Registers for the PHI in endMBB
20101 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20102 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20104 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20105 MachineFunction *MF = MBB->getParent();
20106 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20107 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20108 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20110 MachineFunction::iterator MBBIter = MBB;
20113 // Insert the new basic blocks
20114 MF->insert(MBBIter, offsetMBB);
20115 MF->insert(MBBIter, overflowMBB);
20116 MF->insert(MBBIter, endMBB);
20118 // Transfer the remainder of MBB and its successor edges to endMBB.
20119 endMBB->splice(endMBB->begin(), thisMBB,
20120 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20121 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20123 // Make offsetMBB and overflowMBB successors of thisMBB
20124 thisMBB->addSuccessor(offsetMBB);
20125 thisMBB->addSuccessor(overflowMBB);
20127 // endMBB is a successor of both offsetMBB and overflowMBB
20128 offsetMBB->addSuccessor(endMBB);
20129 overflowMBB->addSuccessor(endMBB);
20131 // Load the offset value into a register
20132 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20133 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20137 .addDisp(Disp, UseFPOffset ? 4 : 0)
20138 .addOperand(Segment)
20139 .setMemRefs(MMOBegin, MMOEnd);
20141 // Check if there is enough room left to pull this argument.
20142 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20144 .addImm(MaxOffset + 8 - ArgSizeA8);
20146 // Branch to "overflowMBB" if offset >= max
20147 // Fall through to "offsetMBB" otherwise
20148 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20149 .addMBB(overflowMBB);
20152 // In offsetMBB, emit code to use the reg_save_area.
20154 assert(OffsetReg != 0);
20156 // Read the reg_save_area address.
20157 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20158 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20163 .addOperand(Segment)
20164 .setMemRefs(MMOBegin, MMOEnd);
20166 // Zero-extend the offset
20167 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20168 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20171 .addImm(X86::sub_32bit);
20173 // Add the offset to the reg_save_area to get the final address.
20174 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20175 .addReg(OffsetReg64)
20176 .addReg(RegSaveReg);
20178 // Compute the offset for the next argument
20179 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20180 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20182 .addImm(UseFPOffset ? 16 : 8);
20184 // Store it back into the va_list.
20185 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20189 .addDisp(Disp, UseFPOffset ? 4 : 0)
20190 .addOperand(Segment)
20191 .addReg(NextOffsetReg)
20192 .setMemRefs(MMOBegin, MMOEnd);
20195 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20200 // Emit code to use overflow area
20203 // Load the overflow_area address into a register.
20204 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20205 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20210 .addOperand(Segment)
20211 .setMemRefs(MMOBegin, MMOEnd);
20213 // If we need to align it, do so. Otherwise, just copy the address
20214 // to OverflowDestReg.
20216 // Align the overflow address
20217 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20218 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20220 // aligned_addr = (addr + (align-1)) & ~(align-1)
20221 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20222 .addReg(OverflowAddrReg)
20225 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20227 .addImm(~(uint64_t)(Align-1));
20229 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20230 .addReg(OverflowAddrReg);
20233 // Compute the next overflow address after this argument.
20234 // (the overflow address should be kept 8-byte aligned)
20235 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20236 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20237 .addReg(OverflowDestReg)
20238 .addImm(ArgSizeA8);
20240 // Store the new overflow address.
20241 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20246 .addOperand(Segment)
20247 .addReg(NextAddrReg)
20248 .setMemRefs(MMOBegin, MMOEnd);
20250 // If we branched, emit the PHI to the front of endMBB.
20252 BuildMI(*endMBB, endMBB->begin(), DL,
20253 TII->get(X86::PHI), DestReg)
20254 .addReg(OffsetDestReg).addMBB(offsetMBB)
20255 .addReg(OverflowDestReg).addMBB(overflowMBB);
20258 // Erase the pseudo instruction
20259 MI->eraseFromParent();
20264 MachineBasicBlock *
20265 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20267 MachineBasicBlock *MBB) const {
20268 // Emit code to save XMM registers to the stack. The ABI says that the
20269 // number of registers to save is given in %al, so it's theoretically
20270 // possible to do an indirect jump trick to avoid saving all of them,
20271 // however this code takes a simpler approach and just executes all
20272 // of the stores if %al is non-zero. It's less code, and it's probably
20273 // easier on the hardware branch predictor, and stores aren't all that
20274 // expensive anyway.
20276 // Create the new basic blocks. One block contains all the XMM stores,
20277 // and one block is the final destination regardless of whether any
20278 // stores were performed.
20279 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20280 MachineFunction *F = MBB->getParent();
20281 MachineFunction::iterator MBBIter = MBB;
20283 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20284 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20285 F->insert(MBBIter, XMMSaveMBB);
20286 F->insert(MBBIter, EndMBB);
20288 // Transfer the remainder of MBB and its successor edges to EndMBB.
20289 EndMBB->splice(EndMBB->begin(), MBB,
20290 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20291 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20293 // The original block will now fall through to the XMM save block.
20294 MBB->addSuccessor(XMMSaveMBB);
20295 // The XMMSaveMBB will fall through to the end block.
20296 XMMSaveMBB->addSuccessor(EndMBB);
20298 // Now add the instructions.
20299 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20300 DebugLoc DL = MI->getDebugLoc();
20302 unsigned CountReg = MI->getOperand(0).getReg();
20303 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20304 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20306 if (!Subtarget->isTargetWin64()) {
20307 // If %al is 0, branch around the XMM save block.
20308 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20309 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20310 MBB->addSuccessor(EndMBB);
20313 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20314 // that was just emitted, but clearly shouldn't be "saved".
20315 assert((MI->getNumOperands() <= 3 ||
20316 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20317 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20318 && "Expected last argument to be EFLAGS");
20319 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20320 // In the XMM save block, save all the XMM argument registers.
20321 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20322 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20323 MachineMemOperand *MMO =
20324 F->getMachineMemOperand(
20325 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20326 MachineMemOperand::MOStore,
20327 /*Size=*/16, /*Align=*/16);
20328 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20329 .addFrameIndex(RegSaveFrameIndex)
20330 .addImm(/*Scale=*/1)
20331 .addReg(/*IndexReg=*/0)
20332 .addImm(/*Disp=*/Offset)
20333 .addReg(/*Segment=*/0)
20334 .addReg(MI->getOperand(i).getReg())
20335 .addMemOperand(MMO);
20338 MI->eraseFromParent(); // The pseudo instruction is gone now.
20343 // The EFLAGS operand of SelectItr might be missing a kill marker
20344 // because there were multiple uses of EFLAGS, and ISel didn't know
20345 // which to mark. Figure out whether SelectItr should have had a
20346 // kill marker, and set it if it should. Returns the correct kill
20348 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20349 MachineBasicBlock* BB,
20350 const TargetRegisterInfo* TRI) {
20351 // Scan forward through BB for a use/def of EFLAGS.
20352 MachineBasicBlock::iterator miI(std::next(SelectItr));
20353 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20354 const MachineInstr& mi = *miI;
20355 if (mi.readsRegister(X86::EFLAGS))
20357 if (mi.definesRegister(X86::EFLAGS))
20358 break; // Should have kill-flag - update below.
20361 // If we hit the end of the block, check whether EFLAGS is live into a
20363 if (miI == BB->end()) {
20364 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20365 sEnd = BB->succ_end();
20366 sItr != sEnd; ++sItr) {
20367 MachineBasicBlock* succ = *sItr;
20368 if (succ->isLiveIn(X86::EFLAGS))
20373 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20374 // out. SelectMI should have a kill flag on EFLAGS.
20375 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20379 MachineBasicBlock *
20380 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20381 MachineBasicBlock *BB) const {
20382 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20383 DebugLoc DL = MI->getDebugLoc();
20385 // To "insert" a SELECT_CC instruction, we actually have to insert the
20386 // diamond control-flow pattern. The incoming instruction knows the
20387 // destination vreg to set, the condition code register to branch on, the
20388 // true/false values to select between, and a branch opcode to use.
20389 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20390 MachineFunction::iterator It = BB;
20396 // cmpTY ccX, r1, r2
20398 // fallthrough --> copy0MBB
20399 MachineBasicBlock *thisMBB = BB;
20400 MachineFunction *F = BB->getParent();
20401 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20402 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20403 F->insert(It, copy0MBB);
20404 F->insert(It, sinkMBB);
20406 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20407 // live into the sink and copy blocks.
20408 const TargetRegisterInfo *TRI =
20409 BB->getParent()->getSubtarget().getRegisterInfo();
20410 if (!MI->killsRegister(X86::EFLAGS) &&
20411 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20412 copy0MBB->addLiveIn(X86::EFLAGS);
20413 sinkMBB->addLiveIn(X86::EFLAGS);
20416 // Transfer the remainder of BB and its successor edges to sinkMBB.
20417 sinkMBB->splice(sinkMBB->begin(), BB,
20418 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20419 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20421 // Add the true and fallthrough blocks as its successors.
20422 BB->addSuccessor(copy0MBB);
20423 BB->addSuccessor(sinkMBB);
20425 // Create the conditional branch instruction.
20427 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20428 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20431 // %FalseValue = ...
20432 // # fallthrough to sinkMBB
20433 copy0MBB->addSuccessor(sinkMBB);
20436 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20438 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20439 TII->get(X86::PHI), MI->getOperand(0).getReg())
20440 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20441 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20443 MI->eraseFromParent(); // The pseudo instruction is gone now.
20447 MachineBasicBlock *
20448 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20449 MachineBasicBlock *BB) const {
20450 MachineFunction *MF = BB->getParent();
20451 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20452 DebugLoc DL = MI->getDebugLoc();
20453 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20455 assert(MF->shouldSplitStack());
20457 const bool Is64Bit = Subtarget->is64Bit();
20458 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20460 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20461 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20464 // ... [Till the alloca]
20465 // If stacklet is not large enough, jump to mallocMBB
20468 // Allocate by subtracting from RSP
20469 // Jump to continueMBB
20472 // Allocate by call to runtime
20476 // [rest of original BB]
20479 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20480 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20481 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20483 MachineRegisterInfo &MRI = MF->getRegInfo();
20484 const TargetRegisterClass *AddrRegClass =
20485 getRegClassFor(getPointerTy());
20487 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20488 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20489 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20490 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20491 sizeVReg = MI->getOperand(1).getReg(),
20492 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20494 MachineFunction::iterator MBBIter = BB;
20497 MF->insert(MBBIter, bumpMBB);
20498 MF->insert(MBBIter, mallocMBB);
20499 MF->insert(MBBIter, continueMBB);
20501 continueMBB->splice(continueMBB->begin(), BB,
20502 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20503 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20505 // Add code to the main basic block to check if the stack limit has been hit,
20506 // and if so, jump to mallocMBB otherwise to bumpMBB.
20507 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20508 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20509 .addReg(tmpSPVReg).addReg(sizeVReg);
20510 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20511 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20512 .addReg(SPLimitVReg);
20513 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20515 // bumpMBB simply decreases the stack pointer, since we know the current
20516 // stacklet has enough space.
20517 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20518 .addReg(SPLimitVReg);
20519 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20520 .addReg(SPLimitVReg);
20521 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20523 // Calls into a routine in libgcc to allocate more space from the heap.
20524 const uint32_t *RegMask = MF->getTarget()
20525 .getSubtargetImpl()
20526 ->getRegisterInfo()
20527 ->getCallPreservedMask(CallingConv::C);
20529 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20531 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20532 .addExternalSymbol("__morestack_allocate_stack_space")
20533 .addRegMask(RegMask)
20534 .addReg(X86::RDI, RegState::Implicit)
20535 .addReg(X86::RAX, RegState::ImplicitDefine);
20536 } else if (Is64Bit) {
20537 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20539 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20540 .addExternalSymbol("__morestack_allocate_stack_space")
20541 .addRegMask(RegMask)
20542 .addReg(X86::EDI, RegState::Implicit)
20543 .addReg(X86::EAX, RegState::ImplicitDefine);
20545 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20547 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20548 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20549 .addExternalSymbol("__morestack_allocate_stack_space")
20550 .addRegMask(RegMask)
20551 .addReg(X86::EAX, RegState::ImplicitDefine);
20555 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20558 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20559 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20560 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20562 // Set up the CFG correctly.
20563 BB->addSuccessor(bumpMBB);
20564 BB->addSuccessor(mallocMBB);
20565 mallocMBB->addSuccessor(continueMBB);
20566 bumpMBB->addSuccessor(continueMBB);
20568 // Take care of the PHI nodes.
20569 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20570 MI->getOperand(0).getReg())
20571 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20572 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20574 // Delete the original pseudo instruction.
20575 MI->eraseFromParent();
20578 return continueMBB;
20581 MachineBasicBlock *
20582 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20583 MachineBasicBlock *BB) const {
20584 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20585 DebugLoc DL = MI->getDebugLoc();
20587 assert(!Subtarget->isTargetMacho());
20589 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20590 // non-trivial part is impdef of ESP.
20592 if (Subtarget->isTargetWin64()) {
20593 if (Subtarget->isTargetCygMing()) {
20594 // ___chkstk(Mingw64):
20595 // Clobbers R10, R11, RAX and EFLAGS.
20597 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20598 .addExternalSymbol("___chkstk")
20599 .addReg(X86::RAX, RegState::Implicit)
20600 .addReg(X86::RSP, RegState::Implicit)
20601 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20602 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20603 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20605 // __chkstk(MSVCRT): does not update stack pointer.
20606 // Clobbers R10, R11 and EFLAGS.
20607 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20608 .addExternalSymbol("__chkstk")
20609 .addReg(X86::RAX, RegState::Implicit)
20610 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20611 // RAX has the offset to be subtracted from RSP.
20612 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20617 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20618 Subtarget->isTargetWindowsItanium())
20622 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20623 .addExternalSymbol(StackProbeSymbol)
20624 .addReg(X86::EAX, RegState::Implicit)
20625 .addReg(X86::ESP, RegState::Implicit)
20626 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20627 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20628 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20631 MI->eraseFromParent(); // The pseudo instruction is gone now.
20635 MachineBasicBlock *
20636 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20637 MachineBasicBlock *BB) const {
20638 // This is pretty easy. We're taking the value that we received from
20639 // our load from the relocation, sticking it in either RDI (x86-64)
20640 // or EAX and doing an indirect call. The return value will then
20641 // be in the normal return register.
20642 MachineFunction *F = BB->getParent();
20643 const X86InstrInfo *TII =
20644 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20645 DebugLoc DL = MI->getDebugLoc();
20647 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20648 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20650 // Get a register mask for the lowered call.
20651 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20652 // proper register mask.
20653 const uint32_t *RegMask = F->getTarget()
20654 .getSubtargetImpl()
20655 ->getRegisterInfo()
20656 ->getCallPreservedMask(CallingConv::C);
20657 if (Subtarget->is64Bit()) {
20658 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20659 TII->get(X86::MOV64rm), X86::RDI)
20661 .addImm(0).addReg(0)
20662 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20663 MI->getOperand(3).getTargetFlags())
20665 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20666 addDirectMem(MIB, X86::RDI);
20667 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20668 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20669 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20670 TII->get(X86::MOV32rm), X86::EAX)
20672 .addImm(0).addReg(0)
20673 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20674 MI->getOperand(3).getTargetFlags())
20676 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20677 addDirectMem(MIB, X86::EAX);
20678 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20680 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20681 TII->get(X86::MOV32rm), X86::EAX)
20682 .addReg(TII->getGlobalBaseReg(F))
20683 .addImm(0).addReg(0)
20684 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20685 MI->getOperand(3).getTargetFlags())
20687 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20688 addDirectMem(MIB, X86::EAX);
20689 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20692 MI->eraseFromParent(); // The pseudo instruction is gone now.
20696 MachineBasicBlock *
20697 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20698 MachineBasicBlock *MBB) const {
20699 DebugLoc DL = MI->getDebugLoc();
20700 MachineFunction *MF = MBB->getParent();
20701 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20702 MachineRegisterInfo &MRI = MF->getRegInfo();
20704 const BasicBlock *BB = MBB->getBasicBlock();
20705 MachineFunction::iterator I = MBB;
20708 // Memory Reference
20709 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20710 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20713 unsigned MemOpndSlot = 0;
20715 unsigned CurOp = 0;
20717 DstReg = MI->getOperand(CurOp++).getReg();
20718 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20719 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20720 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20721 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20723 MemOpndSlot = CurOp;
20725 MVT PVT = getPointerTy();
20726 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20727 "Invalid Pointer Size!");
20729 // For v = setjmp(buf), we generate
20732 // buf[LabelOffset] = restoreMBB
20733 // SjLjSetup restoreMBB
20739 // v = phi(main, restore)
20744 MachineBasicBlock *thisMBB = MBB;
20745 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20746 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20747 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20748 MF->insert(I, mainMBB);
20749 MF->insert(I, sinkMBB);
20750 MF->push_back(restoreMBB);
20752 MachineInstrBuilder MIB;
20754 // Transfer the remainder of BB and its successor edges to sinkMBB.
20755 sinkMBB->splice(sinkMBB->begin(), MBB,
20756 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20757 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20760 unsigned PtrStoreOpc = 0;
20761 unsigned LabelReg = 0;
20762 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20763 Reloc::Model RM = MF->getTarget().getRelocationModel();
20764 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20765 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20767 // Prepare IP either in reg or imm.
20768 if (!UseImmLabel) {
20769 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20770 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20771 LabelReg = MRI.createVirtualRegister(PtrRC);
20772 if (Subtarget->is64Bit()) {
20773 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20777 .addMBB(restoreMBB)
20780 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20781 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20782 .addReg(XII->getGlobalBaseReg(MF))
20785 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20789 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20791 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20792 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20793 if (i == X86::AddrDisp)
20794 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20796 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20799 MIB.addReg(LabelReg);
20801 MIB.addMBB(restoreMBB);
20802 MIB.setMemRefs(MMOBegin, MMOEnd);
20804 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20805 .addMBB(restoreMBB);
20807 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20808 MF->getSubtarget().getRegisterInfo());
20809 MIB.addRegMask(RegInfo->getNoPreservedMask());
20810 thisMBB->addSuccessor(mainMBB);
20811 thisMBB->addSuccessor(restoreMBB);
20815 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20816 mainMBB->addSuccessor(sinkMBB);
20819 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20820 TII->get(X86::PHI), DstReg)
20821 .addReg(mainDstReg).addMBB(mainMBB)
20822 .addReg(restoreDstReg).addMBB(restoreMBB);
20825 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20826 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20827 restoreMBB->addSuccessor(sinkMBB);
20829 MI->eraseFromParent();
20833 MachineBasicBlock *
20834 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20835 MachineBasicBlock *MBB) const {
20836 DebugLoc DL = MI->getDebugLoc();
20837 MachineFunction *MF = MBB->getParent();
20838 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20839 MachineRegisterInfo &MRI = MF->getRegInfo();
20841 // Memory Reference
20842 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20843 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20845 MVT PVT = getPointerTy();
20846 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20847 "Invalid Pointer Size!");
20849 const TargetRegisterClass *RC =
20850 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20851 unsigned Tmp = MRI.createVirtualRegister(RC);
20852 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20853 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20854 MF->getSubtarget().getRegisterInfo());
20855 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20856 unsigned SP = RegInfo->getStackRegister();
20858 MachineInstrBuilder MIB;
20860 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20861 const int64_t SPOffset = 2 * PVT.getStoreSize();
20863 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20864 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20867 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20868 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20869 MIB.addOperand(MI->getOperand(i));
20870 MIB.setMemRefs(MMOBegin, MMOEnd);
20872 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20873 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20874 if (i == X86::AddrDisp)
20875 MIB.addDisp(MI->getOperand(i), LabelOffset);
20877 MIB.addOperand(MI->getOperand(i));
20879 MIB.setMemRefs(MMOBegin, MMOEnd);
20881 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20882 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20883 if (i == X86::AddrDisp)
20884 MIB.addDisp(MI->getOperand(i), SPOffset);
20886 MIB.addOperand(MI->getOperand(i));
20888 MIB.setMemRefs(MMOBegin, MMOEnd);
20890 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20892 MI->eraseFromParent();
20896 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20897 // accumulator loops. Writing back to the accumulator allows the coalescer
20898 // to remove extra copies in the loop.
20899 MachineBasicBlock *
20900 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20901 MachineBasicBlock *MBB) const {
20902 MachineOperand &AddendOp = MI->getOperand(3);
20904 // Bail out early if the addend isn't a register - we can't switch these.
20905 if (!AddendOp.isReg())
20908 MachineFunction &MF = *MBB->getParent();
20909 MachineRegisterInfo &MRI = MF.getRegInfo();
20911 // Check whether the addend is defined by a PHI:
20912 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20913 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20914 if (!AddendDef.isPHI())
20917 // Look for the following pattern:
20919 // %addend = phi [%entry, 0], [%loop, %result]
20921 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20925 // %addend = phi [%entry, 0], [%loop, %result]
20927 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20929 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20930 assert(AddendDef.getOperand(i).isReg());
20931 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20932 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20933 if (&PHISrcInst == MI) {
20934 // Found a matching instruction.
20935 unsigned NewFMAOpc = 0;
20936 switch (MI->getOpcode()) {
20937 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20938 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20939 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20940 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20941 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20942 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20943 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20944 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20945 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20946 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20947 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20948 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20949 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20950 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20951 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20952 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20953 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20954 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20955 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20956 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20958 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20959 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20960 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20961 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20962 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20963 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20964 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20965 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20966 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20967 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20968 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20969 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20970 default: llvm_unreachable("Unrecognized FMA variant.");
20973 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20974 MachineInstrBuilder MIB =
20975 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20976 .addOperand(MI->getOperand(0))
20977 .addOperand(MI->getOperand(3))
20978 .addOperand(MI->getOperand(2))
20979 .addOperand(MI->getOperand(1));
20980 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20981 MI->eraseFromParent();
20988 MachineBasicBlock *
20989 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20990 MachineBasicBlock *BB) const {
20991 switch (MI->getOpcode()) {
20992 default: llvm_unreachable("Unexpected instr type to insert");
20993 case X86::TAILJMPd64:
20994 case X86::TAILJMPr64:
20995 case X86::TAILJMPm64:
20996 llvm_unreachable("TAILJMP64 would not be touched here.");
20997 case X86::TCRETURNdi64:
20998 case X86::TCRETURNri64:
20999 case X86::TCRETURNmi64:
21001 case X86::WIN_ALLOCA:
21002 return EmitLoweredWinAlloca(MI, BB);
21003 case X86::SEG_ALLOCA_32:
21004 case X86::SEG_ALLOCA_64:
21005 return EmitLoweredSegAlloca(MI, BB);
21006 case X86::TLSCall_32:
21007 case X86::TLSCall_64:
21008 return EmitLoweredTLSCall(MI, BB);
21009 case X86::CMOV_GR8:
21010 case X86::CMOV_FR32:
21011 case X86::CMOV_FR64:
21012 case X86::CMOV_V4F32:
21013 case X86::CMOV_V2F64:
21014 case X86::CMOV_V2I64:
21015 case X86::CMOV_V8F32:
21016 case X86::CMOV_V4F64:
21017 case X86::CMOV_V4I64:
21018 case X86::CMOV_V16F32:
21019 case X86::CMOV_V8F64:
21020 case X86::CMOV_V8I64:
21021 case X86::CMOV_GR16:
21022 case X86::CMOV_GR32:
21023 case X86::CMOV_RFP32:
21024 case X86::CMOV_RFP64:
21025 case X86::CMOV_RFP80:
21026 return EmitLoweredSelect(MI, BB);
21028 case X86::FP32_TO_INT16_IN_MEM:
21029 case X86::FP32_TO_INT32_IN_MEM:
21030 case X86::FP32_TO_INT64_IN_MEM:
21031 case X86::FP64_TO_INT16_IN_MEM:
21032 case X86::FP64_TO_INT32_IN_MEM:
21033 case X86::FP64_TO_INT64_IN_MEM:
21034 case X86::FP80_TO_INT16_IN_MEM:
21035 case X86::FP80_TO_INT32_IN_MEM:
21036 case X86::FP80_TO_INT64_IN_MEM: {
21037 MachineFunction *F = BB->getParent();
21038 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21039 DebugLoc DL = MI->getDebugLoc();
21041 // Change the floating point control register to use "round towards zero"
21042 // mode when truncating to an integer value.
21043 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21044 addFrameReference(BuildMI(*BB, MI, DL,
21045 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21047 // Load the old value of the high byte of the control word...
21049 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21050 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21053 // Set the high part to be round to zero...
21054 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21057 // Reload the modified control word now...
21058 addFrameReference(BuildMI(*BB, MI, DL,
21059 TII->get(X86::FLDCW16m)), CWFrameIdx);
21061 // Restore the memory image of control word to original value
21062 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21065 // Get the X86 opcode to use.
21067 switch (MI->getOpcode()) {
21068 default: llvm_unreachable("illegal opcode!");
21069 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21070 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21071 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21072 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21073 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21074 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21075 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21076 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21077 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21081 MachineOperand &Op = MI->getOperand(0);
21083 AM.BaseType = X86AddressMode::RegBase;
21084 AM.Base.Reg = Op.getReg();
21086 AM.BaseType = X86AddressMode::FrameIndexBase;
21087 AM.Base.FrameIndex = Op.getIndex();
21089 Op = MI->getOperand(1);
21091 AM.Scale = Op.getImm();
21092 Op = MI->getOperand(2);
21094 AM.IndexReg = Op.getImm();
21095 Op = MI->getOperand(3);
21096 if (Op.isGlobal()) {
21097 AM.GV = Op.getGlobal();
21099 AM.Disp = Op.getImm();
21101 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21102 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21104 // Reload the original control word now.
21105 addFrameReference(BuildMI(*BB, MI, DL,
21106 TII->get(X86::FLDCW16m)), CWFrameIdx);
21108 MI->eraseFromParent(); // The pseudo instruction is gone now.
21111 // String/text processing lowering.
21112 case X86::PCMPISTRM128REG:
21113 case X86::VPCMPISTRM128REG:
21114 case X86::PCMPISTRM128MEM:
21115 case X86::VPCMPISTRM128MEM:
21116 case X86::PCMPESTRM128REG:
21117 case X86::VPCMPESTRM128REG:
21118 case X86::PCMPESTRM128MEM:
21119 case X86::VPCMPESTRM128MEM:
21120 assert(Subtarget->hasSSE42() &&
21121 "Target must have SSE4.2 or AVX features enabled");
21122 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21124 // String/text processing lowering.
21125 case X86::PCMPISTRIREG:
21126 case X86::VPCMPISTRIREG:
21127 case X86::PCMPISTRIMEM:
21128 case X86::VPCMPISTRIMEM:
21129 case X86::PCMPESTRIREG:
21130 case X86::VPCMPESTRIREG:
21131 case X86::PCMPESTRIMEM:
21132 case X86::VPCMPESTRIMEM:
21133 assert(Subtarget->hasSSE42() &&
21134 "Target must have SSE4.2 or AVX features enabled");
21135 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21137 // Thread synchronization.
21139 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21144 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21146 case X86::VASTART_SAVE_XMM_REGS:
21147 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21149 case X86::VAARG_64:
21150 return EmitVAARG64WithCustomInserter(MI, BB);
21152 case X86::EH_SjLj_SetJmp32:
21153 case X86::EH_SjLj_SetJmp64:
21154 return emitEHSjLjSetJmp(MI, BB);
21156 case X86::EH_SjLj_LongJmp32:
21157 case X86::EH_SjLj_LongJmp64:
21158 return emitEHSjLjLongJmp(MI, BB);
21160 case TargetOpcode::STACKMAP:
21161 case TargetOpcode::PATCHPOINT:
21162 return emitPatchPoint(MI, BB);
21164 case X86::VFMADDPDr213r:
21165 case X86::VFMADDPSr213r:
21166 case X86::VFMADDSDr213r:
21167 case X86::VFMADDSSr213r:
21168 case X86::VFMSUBPDr213r:
21169 case X86::VFMSUBPSr213r:
21170 case X86::VFMSUBSDr213r:
21171 case X86::VFMSUBSSr213r:
21172 case X86::VFNMADDPDr213r:
21173 case X86::VFNMADDPSr213r:
21174 case X86::VFNMADDSDr213r:
21175 case X86::VFNMADDSSr213r:
21176 case X86::VFNMSUBPDr213r:
21177 case X86::VFNMSUBPSr213r:
21178 case X86::VFNMSUBSDr213r:
21179 case X86::VFNMSUBSSr213r:
21180 case X86::VFMADDSUBPDr213r:
21181 case X86::VFMADDSUBPSr213r:
21182 case X86::VFMSUBADDPDr213r:
21183 case X86::VFMSUBADDPSr213r:
21184 case X86::VFMADDPDr213rY:
21185 case X86::VFMADDPSr213rY:
21186 case X86::VFMSUBPDr213rY:
21187 case X86::VFMSUBPSr213rY:
21188 case X86::VFNMADDPDr213rY:
21189 case X86::VFNMADDPSr213rY:
21190 case X86::VFNMSUBPDr213rY:
21191 case X86::VFNMSUBPSr213rY:
21192 case X86::VFMADDSUBPDr213rY:
21193 case X86::VFMADDSUBPSr213rY:
21194 case X86::VFMSUBADDPDr213rY:
21195 case X86::VFMSUBADDPSr213rY:
21196 return emitFMA3Instr(MI, BB);
21200 //===----------------------------------------------------------------------===//
21201 // X86 Optimization Hooks
21202 //===----------------------------------------------------------------------===//
21204 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21207 const SelectionDAG &DAG,
21208 unsigned Depth) const {
21209 unsigned BitWidth = KnownZero.getBitWidth();
21210 unsigned Opc = Op.getOpcode();
21211 assert((Opc >= ISD::BUILTIN_OP_END ||
21212 Opc == ISD::INTRINSIC_WO_CHAIN ||
21213 Opc == ISD::INTRINSIC_W_CHAIN ||
21214 Opc == ISD::INTRINSIC_VOID) &&
21215 "Should use MaskedValueIsZero if you don't know whether Op"
21216 " is a target node!");
21218 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21232 // These nodes' second result is a boolean.
21233 if (Op.getResNo() == 0)
21236 case X86ISD::SETCC:
21237 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21239 case ISD::INTRINSIC_WO_CHAIN: {
21240 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21241 unsigned NumLoBits = 0;
21244 case Intrinsic::x86_sse_movmsk_ps:
21245 case Intrinsic::x86_avx_movmsk_ps_256:
21246 case Intrinsic::x86_sse2_movmsk_pd:
21247 case Intrinsic::x86_avx_movmsk_pd_256:
21248 case Intrinsic::x86_mmx_pmovmskb:
21249 case Intrinsic::x86_sse2_pmovmskb_128:
21250 case Intrinsic::x86_avx2_pmovmskb: {
21251 // High bits of movmskp{s|d}, pmovmskb are known zero.
21253 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21254 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21255 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21256 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21257 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21258 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21259 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21260 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21262 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21271 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21273 const SelectionDAG &,
21274 unsigned Depth) const {
21275 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21276 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21277 return Op.getValueType().getScalarType().getSizeInBits();
21283 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21284 /// node is a GlobalAddress + offset.
21285 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21286 const GlobalValue* &GA,
21287 int64_t &Offset) const {
21288 if (N->getOpcode() == X86ISD::Wrapper) {
21289 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21290 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21291 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21295 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21298 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21299 /// same as extracting the high 128-bit part of 256-bit vector and then
21300 /// inserting the result into the low part of a new 256-bit vector
21301 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21302 EVT VT = SVOp->getValueType(0);
21303 unsigned NumElems = VT.getVectorNumElements();
21305 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21306 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21307 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21308 SVOp->getMaskElt(j) >= 0)
21314 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21315 /// same as extracting the low 128-bit part of 256-bit vector and then
21316 /// inserting the result into the high part of a new 256-bit vector
21317 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21318 EVT VT = SVOp->getValueType(0);
21319 unsigned NumElems = VT.getVectorNumElements();
21321 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21322 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21323 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21324 SVOp->getMaskElt(j) >= 0)
21330 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21331 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21332 TargetLowering::DAGCombinerInfo &DCI,
21333 const X86Subtarget* Subtarget) {
21335 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21336 SDValue V1 = SVOp->getOperand(0);
21337 SDValue V2 = SVOp->getOperand(1);
21338 EVT VT = SVOp->getValueType(0);
21339 unsigned NumElems = VT.getVectorNumElements();
21341 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21342 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21346 // V UNDEF BUILD_VECTOR UNDEF
21348 // CONCAT_VECTOR CONCAT_VECTOR
21351 // RESULT: V + zero extended
21353 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21354 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21355 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21358 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21361 // To match the shuffle mask, the first half of the mask should
21362 // be exactly the first vector, and all the rest a splat with the
21363 // first element of the second one.
21364 for (unsigned i = 0; i != NumElems/2; ++i)
21365 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21366 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21369 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21370 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21371 if (Ld->hasNUsesOfValue(1, 0)) {
21372 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21373 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21375 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21377 Ld->getPointerInfo(),
21378 Ld->getAlignment(),
21379 false/*isVolatile*/, true/*ReadMem*/,
21380 false/*WriteMem*/);
21382 // Make sure the newly-created LOAD is in the same position as Ld in
21383 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21384 // and update uses of Ld's output chain to use the TokenFactor.
21385 if (Ld->hasAnyUseOfValue(1)) {
21386 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21387 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21388 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21389 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21390 SDValue(ResNode.getNode(), 1));
21393 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21397 // Emit a zeroed vector and insert the desired subvector on its
21399 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21400 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21401 return DCI.CombineTo(N, InsV);
21404 //===--------------------------------------------------------------------===//
21405 // Combine some shuffles into subvector extracts and inserts:
21408 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21409 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21410 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21411 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21412 return DCI.CombineTo(N, InsV);
21415 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21416 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21417 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21418 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21419 return DCI.CombineTo(N, InsV);
21425 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21428 /// This is the leaf of the recursive combinine below. When we have found some
21429 /// chain of single-use x86 shuffle instructions and accumulated the combined
21430 /// shuffle mask represented by them, this will try to pattern match that mask
21431 /// into either a single instruction if there is a special purpose instruction
21432 /// for this operation, or into a PSHUFB instruction which is a fully general
21433 /// instruction but should only be used to replace chains over a certain depth.
21434 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21435 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21436 TargetLowering::DAGCombinerInfo &DCI,
21437 const X86Subtarget *Subtarget) {
21438 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21440 // Find the operand that enters the chain. Note that multiple uses are OK
21441 // here, we're not going to remove the operand we find.
21442 SDValue Input = Op.getOperand(0);
21443 while (Input.getOpcode() == ISD::BITCAST)
21444 Input = Input.getOperand(0);
21446 MVT VT = Input.getSimpleValueType();
21447 MVT RootVT = Root.getSimpleValueType();
21450 // Just remove no-op shuffle masks.
21451 if (Mask.size() == 1) {
21452 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21457 // Use the float domain if the operand type is a floating point type.
21458 bool FloatDomain = VT.isFloatingPoint();
21460 // For floating point shuffles, we don't have free copies in the shuffle
21461 // instructions or the ability to load as part of the instruction, so
21462 // canonicalize their shuffles to UNPCK or MOV variants.
21464 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21465 // vectors because it can have a load folded into it that UNPCK cannot. This
21466 // doesn't preclude something switching to the shorter encoding post-RA.
21468 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21469 bool Lo = Mask.equals(0, 0);
21472 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21473 // is no slower than UNPCKLPD but has the option to fold the input operand
21474 // into even an unaligned memory load.
21475 if (Lo && Subtarget->hasSSE3()) {
21476 Shuffle = X86ISD::MOVDDUP;
21477 ShuffleVT = MVT::v2f64;
21479 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21480 // than the UNPCK variants.
21481 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21482 ShuffleVT = MVT::v4f32;
21484 if (Depth == 1 && Root->getOpcode() == Shuffle)
21485 return false; // Nothing to do!
21486 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21487 DCI.AddToWorklist(Op.getNode());
21488 if (Shuffle == X86ISD::MOVDDUP)
21489 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21491 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21492 DCI.AddToWorklist(Op.getNode());
21493 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21497 if (Subtarget->hasSSE3() &&
21498 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21499 bool Lo = Mask.equals(0, 0, 2, 2);
21500 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21501 MVT ShuffleVT = MVT::v4f32;
21502 if (Depth == 1 && Root->getOpcode() == Shuffle)
21503 return false; // Nothing to do!
21504 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21505 DCI.AddToWorklist(Op.getNode());
21506 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21507 DCI.AddToWorklist(Op.getNode());
21508 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21512 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21513 bool Lo = Mask.equals(0, 0, 1, 1);
21514 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21515 MVT ShuffleVT = MVT::v4f32;
21516 if (Depth == 1 && Root->getOpcode() == Shuffle)
21517 return false; // Nothing to do!
21518 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21519 DCI.AddToWorklist(Op.getNode());
21520 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21521 DCI.AddToWorklist(Op.getNode());
21522 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21528 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21529 // variants as none of these have single-instruction variants that are
21530 // superior to the UNPCK formulation.
21531 if (!FloatDomain &&
21532 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21533 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21534 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21535 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21537 bool Lo = Mask[0] == 0;
21538 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21539 if (Depth == 1 && Root->getOpcode() == Shuffle)
21540 return false; // Nothing to do!
21542 switch (Mask.size()) {
21544 ShuffleVT = MVT::v8i16;
21547 ShuffleVT = MVT::v16i8;
21550 llvm_unreachable("Impossible mask size!");
21552 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21553 DCI.AddToWorklist(Op.getNode());
21554 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21555 DCI.AddToWorklist(Op.getNode());
21556 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21561 // Don't try to re-form single instruction chains under any circumstances now
21562 // that we've done encoding canonicalization for them.
21566 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21567 // can replace them with a single PSHUFB instruction profitably. Intel's
21568 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21569 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21570 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21571 SmallVector<SDValue, 16> PSHUFBMask;
21572 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21573 int Ratio = 16 / Mask.size();
21574 for (unsigned i = 0; i < 16; ++i) {
21575 if (Mask[i / Ratio] == SM_SentinelUndef) {
21576 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21579 int M = Mask[i / Ratio] != SM_SentinelZero
21580 ? Ratio * Mask[i / Ratio] + i % Ratio
21582 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21584 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21585 DCI.AddToWorklist(Op.getNode());
21586 SDValue PSHUFBMaskOp =
21587 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21588 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21589 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21590 DCI.AddToWorklist(Op.getNode());
21591 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21596 // Failed to find any combines.
21600 /// \brief Fully generic combining of x86 shuffle instructions.
21602 /// This should be the last combine run over the x86 shuffle instructions. Once
21603 /// they have been fully optimized, this will recursively consider all chains
21604 /// of single-use shuffle instructions, build a generic model of the cumulative
21605 /// shuffle operation, and check for simpler instructions which implement this
21606 /// operation. We use this primarily for two purposes:
21608 /// 1) Collapse generic shuffles to specialized single instructions when
21609 /// equivalent. In most cases, this is just an encoding size win, but
21610 /// sometimes we will collapse multiple generic shuffles into a single
21611 /// special-purpose shuffle.
21612 /// 2) Look for sequences of shuffle instructions with 3 or more total
21613 /// instructions, and replace them with the slightly more expensive SSSE3
21614 /// PSHUFB instruction if available. We do this as the last combining step
21615 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21616 /// a suitable short sequence of other instructions. The PHUFB will either
21617 /// use a register or have to read from memory and so is slightly (but only
21618 /// slightly) more expensive than the other shuffle instructions.
21620 /// Because this is inherently a quadratic operation (for each shuffle in
21621 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21622 /// This should never be an issue in practice as the shuffle lowering doesn't
21623 /// produce sequences of more than 8 instructions.
21625 /// FIXME: We will currently miss some cases where the redundant shuffling
21626 /// would simplify under the threshold for PSHUFB formation because of
21627 /// combine-ordering. To fix this, we should do the redundant instruction
21628 /// combining in this recursive walk.
21629 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21630 ArrayRef<int> RootMask,
21631 int Depth, bool HasPSHUFB,
21633 TargetLowering::DAGCombinerInfo &DCI,
21634 const X86Subtarget *Subtarget) {
21635 // Bound the depth of our recursive combine because this is ultimately
21636 // quadratic in nature.
21640 // Directly rip through bitcasts to find the underlying operand.
21641 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21642 Op = Op.getOperand(0);
21644 MVT VT = Op.getSimpleValueType();
21645 if (!VT.isVector())
21646 return false; // Bail if we hit a non-vector.
21647 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21648 // version should be added.
21649 if (VT.getSizeInBits() != 128)
21652 assert(Root.getSimpleValueType().isVector() &&
21653 "Shuffles operate on vector types!");
21654 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21655 "Can only combine shuffles of the same vector register size.");
21657 if (!isTargetShuffle(Op.getOpcode()))
21659 SmallVector<int, 16> OpMask;
21661 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21662 // We only can combine unary shuffles which we can decode the mask for.
21663 if (!HaveMask || !IsUnary)
21666 assert(VT.getVectorNumElements() == OpMask.size() &&
21667 "Different mask size from vector size!");
21668 assert(((RootMask.size() > OpMask.size() &&
21669 RootMask.size() % OpMask.size() == 0) ||
21670 (OpMask.size() > RootMask.size() &&
21671 OpMask.size() % RootMask.size() == 0) ||
21672 OpMask.size() == RootMask.size()) &&
21673 "The smaller number of elements must divide the larger.");
21674 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21675 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21676 assert(((RootRatio == 1 && OpRatio == 1) ||
21677 (RootRatio == 1) != (OpRatio == 1)) &&
21678 "Must not have a ratio for both incoming and op masks!");
21680 SmallVector<int, 16> Mask;
21681 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21683 // Merge this shuffle operation's mask into our accumulated mask. Note that
21684 // this shuffle's mask will be the first applied to the input, followed by the
21685 // root mask to get us all the way to the root value arrangement. The reason
21686 // for this order is that we are recursing up the operation chain.
21687 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21688 int RootIdx = i / RootRatio;
21689 if (RootMask[RootIdx] < 0) {
21690 // This is a zero or undef lane, we're done.
21691 Mask.push_back(RootMask[RootIdx]);
21695 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21696 int OpIdx = RootMaskedIdx / OpRatio;
21697 if (OpMask[OpIdx] < 0) {
21698 // The incoming lanes are zero or undef, it doesn't matter which ones we
21700 Mask.push_back(OpMask[OpIdx]);
21704 // Ok, we have non-zero lanes, map them through.
21705 Mask.push_back(OpMask[OpIdx] * OpRatio +
21706 RootMaskedIdx % OpRatio);
21709 // See if we can recurse into the operand to combine more things.
21710 switch (Op.getOpcode()) {
21711 case X86ISD::PSHUFB:
21713 case X86ISD::PSHUFD:
21714 case X86ISD::PSHUFHW:
21715 case X86ISD::PSHUFLW:
21716 if (Op.getOperand(0).hasOneUse() &&
21717 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21718 HasPSHUFB, DAG, DCI, Subtarget))
21722 case X86ISD::UNPCKL:
21723 case X86ISD::UNPCKH:
21724 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21725 // We can't check for single use, we have to check that this shuffle is the only user.
21726 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21727 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21728 HasPSHUFB, DAG, DCI, Subtarget))
21733 // Minor canonicalization of the accumulated shuffle mask to make it easier
21734 // to match below. All this does is detect masks with squential pairs of
21735 // elements, and shrink them to the half-width mask. It does this in a loop
21736 // so it will reduce the size of the mask to the minimal width mask which
21737 // performs an equivalent shuffle.
21738 SmallVector<int, 16> WidenedMask;
21739 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21740 Mask = std::move(WidenedMask);
21741 WidenedMask.clear();
21744 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21748 /// \brief Get the PSHUF-style mask from PSHUF node.
21750 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21751 /// PSHUF-style masks that can be reused with such instructions.
21752 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21753 SmallVector<int, 4> Mask;
21755 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21759 switch (N.getOpcode()) {
21760 case X86ISD::PSHUFD:
21762 case X86ISD::PSHUFLW:
21765 case X86ISD::PSHUFHW:
21766 Mask.erase(Mask.begin(), Mask.begin() + 4);
21767 for (int &M : Mask)
21771 llvm_unreachable("No valid shuffle instruction found!");
21775 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21777 /// We walk up the chain and look for a combinable shuffle, skipping over
21778 /// shuffles that we could hoist this shuffle's transformation past without
21779 /// altering anything.
21781 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21783 TargetLowering::DAGCombinerInfo &DCI) {
21784 assert(N.getOpcode() == X86ISD::PSHUFD &&
21785 "Called with something other than an x86 128-bit half shuffle!");
21788 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21789 // of the shuffles in the chain so that we can form a fresh chain to replace
21791 SmallVector<SDValue, 8> Chain;
21792 SDValue V = N.getOperand(0);
21793 for (; V.hasOneUse(); V = V.getOperand(0)) {
21794 switch (V.getOpcode()) {
21796 return SDValue(); // Nothing combined!
21799 // Skip bitcasts as we always know the type for the target specific
21803 case X86ISD::PSHUFD:
21804 // Found another dword shuffle.
21807 case X86ISD::PSHUFLW:
21808 // Check that the low words (being shuffled) are the identity in the
21809 // dword shuffle, and the high words are self-contained.
21810 if (Mask[0] != 0 || Mask[1] != 1 ||
21811 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21814 Chain.push_back(V);
21817 case X86ISD::PSHUFHW:
21818 // Check that the high words (being shuffled) are the identity in the
21819 // dword shuffle, and the low words are self-contained.
21820 if (Mask[2] != 2 || Mask[3] != 3 ||
21821 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21824 Chain.push_back(V);
21827 case X86ISD::UNPCKL:
21828 case X86ISD::UNPCKH:
21829 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21830 // shuffle into a preceding word shuffle.
21831 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21834 // Search for a half-shuffle which we can combine with.
21835 unsigned CombineOp =
21836 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21837 if (V.getOperand(0) != V.getOperand(1) ||
21838 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21840 Chain.push_back(V);
21841 V = V.getOperand(0);
21843 switch (V.getOpcode()) {
21845 return SDValue(); // Nothing to combine.
21847 case X86ISD::PSHUFLW:
21848 case X86ISD::PSHUFHW:
21849 if (V.getOpcode() == CombineOp)
21852 Chain.push_back(V);
21856 V = V.getOperand(0);
21860 } while (V.hasOneUse());
21863 // Break out of the loop if we break out of the switch.
21867 if (!V.hasOneUse())
21868 // We fell out of the loop without finding a viable combining instruction.
21871 // Merge this node's mask and our incoming mask.
21872 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21873 for (int &M : Mask)
21875 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21876 getV4X86ShuffleImm8ForMask(Mask, DAG));
21878 // Rebuild the chain around this new shuffle.
21879 while (!Chain.empty()) {
21880 SDValue W = Chain.pop_back_val();
21882 if (V.getValueType() != W.getOperand(0).getValueType())
21883 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21885 switch (W.getOpcode()) {
21887 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21889 case X86ISD::UNPCKL:
21890 case X86ISD::UNPCKH:
21891 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21894 case X86ISD::PSHUFD:
21895 case X86ISD::PSHUFLW:
21896 case X86ISD::PSHUFHW:
21897 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21901 if (V.getValueType() != N.getValueType())
21902 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21904 // Return the new chain to replace N.
21908 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21910 /// We walk up the chain, skipping shuffles of the other half and looking
21911 /// through shuffles which switch halves trying to find a shuffle of the same
21912 /// pair of dwords.
21913 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21915 TargetLowering::DAGCombinerInfo &DCI) {
21917 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21918 "Called with something other than an x86 128-bit half shuffle!");
21920 unsigned CombineOpcode = N.getOpcode();
21922 // Walk up a single-use chain looking for a combinable shuffle.
21923 SDValue V = N.getOperand(0);
21924 for (; V.hasOneUse(); V = V.getOperand(0)) {
21925 switch (V.getOpcode()) {
21927 return false; // Nothing combined!
21930 // Skip bitcasts as we always know the type for the target specific
21934 case X86ISD::PSHUFLW:
21935 case X86ISD::PSHUFHW:
21936 if (V.getOpcode() == CombineOpcode)
21939 // Other-half shuffles are no-ops.
21942 // Break out of the loop if we break out of the switch.
21946 if (!V.hasOneUse())
21947 // We fell out of the loop without finding a viable combining instruction.
21950 // Combine away the bottom node as its shuffle will be accumulated into
21951 // a preceding shuffle.
21952 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21954 // Record the old value.
21957 // Merge this node's mask and our incoming mask (adjusted to account for all
21958 // the pshufd instructions encountered).
21959 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21960 for (int &M : Mask)
21962 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21963 getV4X86ShuffleImm8ForMask(Mask, DAG));
21965 // Check that the shuffles didn't cancel each other out. If not, we need to
21966 // combine to the new one.
21968 // Replace the combinable shuffle with the combined one, updating all users
21969 // so that we re-evaluate the chain here.
21970 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21975 /// \brief Try to combine x86 target specific shuffles.
21976 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21977 TargetLowering::DAGCombinerInfo &DCI,
21978 const X86Subtarget *Subtarget) {
21980 MVT VT = N.getSimpleValueType();
21981 SmallVector<int, 4> Mask;
21983 switch (N.getOpcode()) {
21984 case X86ISD::PSHUFD:
21985 case X86ISD::PSHUFLW:
21986 case X86ISD::PSHUFHW:
21987 Mask = getPSHUFShuffleMask(N);
21988 assert(Mask.size() == 4);
21994 // Nuke no-op shuffles that show up after combining.
21995 if (isNoopShuffleMask(Mask))
21996 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21998 // Look for simplifications involving one or two shuffle instructions.
21999 SDValue V = N.getOperand(0);
22000 switch (N.getOpcode()) {
22003 case X86ISD::PSHUFLW:
22004 case X86ISD::PSHUFHW:
22005 assert(VT == MVT::v8i16);
22008 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22009 return SDValue(); // We combined away this shuffle, so we're done.
22011 // See if this reduces to a PSHUFD which is no more expensive and can
22012 // combine with more operations. Note that it has to at least flip the
22013 // dwords as otherwise it would have been removed as a no-op.
22014 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22015 int DMask[] = {0, 1, 2, 3};
22016 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22017 DMask[DOffset + 0] = DOffset + 1;
22018 DMask[DOffset + 1] = DOffset + 0;
22019 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22020 DCI.AddToWorklist(V.getNode());
22021 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22022 getV4X86ShuffleImm8ForMask(DMask, DAG));
22023 DCI.AddToWorklist(V.getNode());
22024 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22027 // Look for shuffle patterns which can be implemented as a single unpack.
22028 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22029 // only works when we have a PSHUFD followed by two half-shuffles.
22030 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22031 (V.getOpcode() == X86ISD::PSHUFLW ||
22032 V.getOpcode() == X86ISD::PSHUFHW) &&
22033 V.getOpcode() != N.getOpcode() &&
22035 SDValue D = V.getOperand(0);
22036 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22037 D = D.getOperand(0);
22038 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22039 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22040 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22041 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22042 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22044 for (int i = 0; i < 4; ++i) {
22045 WordMask[i + NOffset] = Mask[i] + NOffset;
22046 WordMask[i + VOffset] = VMask[i] + VOffset;
22048 // Map the word mask through the DWord mask.
22050 for (int i = 0; i < 8; ++i)
22051 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22052 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22053 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22054 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22055 std::begin(UnpackLoMask)) ||
22056 std::equal(std::begin(MappedMask), std::end(MappedMask),
22057 std::begin(UnpackHiMask))) {
22058 // We can replace all three shuffles with an unpack.
22059 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22060 DCI.AddToWorklist(V.getNode());
22061 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22063 DL, MVT::v8i16, V, V);
22070 case X86ISD::PSHUFD:
22071 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22080 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22082 /// We combine this directly on the abstract vector shuffle nodes so it is
22083 /// easier to generically match. We also insert dummy vector shuffle nodes for
22084 /// the operands which explicitly discard the lanes which are unused by this
22085 /// operation to try to flow through the rest of the combiner the fact that
22086 /// they're unused.
22087 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22089 EVT VT = N->getValueType(0);
22091 // We only handle target-independent shuffles.
22092 // FIXME: It would be easy and harmless to use the target shuffle mask
22093 // extraction tool to support more.
22094 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22097 auto *SVN = cast<ShuffleVectorSDNode>(N);
22098 ArrayRef<int> Mask = SVN->getMask();
22099 SDValue V1 = N->getOperand(0);
22100 SDValue V2 = N->getOperand(1);
22102 // We require the first shuffle operand to be the SUB node, and the second to
22103 // be the ADD node.
22104 // FIXME: We should support the commuted patterns.
22105 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22108 // If there are other uses of these operations we can't fold them.
22109 if (!V1->hasOneUse() || !V2->hasOneUse())
22112 // Ensure that both operations have the same operands. Note that we can
22113 // commute the FADD operands.
22114 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22115 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22116 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22119 // We're looking for blends between FADD and FSUB nodes. We insist on these
22120 // nodes being lined up in a specific expected pattern.
22121 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22122 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22123 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22126 // Only specific types are legal at this point, assert so we notice if and
22127 // when these change.
22128 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22129 VT == MVT::v4f64) &&
22130 "Unknown vector type encountered!");
22132 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22135 /// PerformShuffleCombine - Performs several different shuffle combines.
22136 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22137 TargetLowering::DAGCombinerInfo &DCI,
22138 const X86Subtarget *Subtarget) {
22140 SDValue N0 = N->getOperand(0);
22141 SDValue N1 = N->getOperand(1);
22142 EVT VT = N->getValueType(0);
22144 // Don't create instructions with illegal types after legalize types has run.
22145 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22146 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22149 // If we have legalized the vector types, look for blends of FADD and FSUB
22150 // nodes that we can fuse into an ADDSUB node.
22151 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22152 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22155 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22156 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22157 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22158 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22160 // During Type Legalization, when promoting illegal vector types,
22161 // the backend might introduce new shuffle dag nodes and bitcasts.
22163 // This code performs the following transformation:
22164 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22165 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22167 // We do this only if both the bitcast and the BINOP dag nodes have
22168 // one use. Also, perform this transformation only if the new binary
22169 // operation is legal. This is to avoid introducing dag nodes that
22170 // potentially need to be further expanded (or custom lowered) into a
22171 // less optimal sequence of dag nodes.
22172 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22173 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22174 N0.getOpcode() == ISD::BITCAST) {
22175 SDValue BC0 = N0.getOperand(0);
22176 EVT SVT = BC0.getValueType();
22177 unsigned Opcode = BC0.getOpcode();
22178 unsigned NumElts = VT.getVectorNumElements();
22180 if (BC0.hasOneUse() && SVT.isVector() &&
22181 SVT.getVectorNumElements() * 2 == NumElts &&
22182 TLI.isOperationLegal(Opcode, VT)) {
22183 bool CanFold = false;
22195 unsigned SVTNumElts = SVT.getVectorNumElements();
22196 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22197 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22198 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22199 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22200 CanFold = SVOp->getMaskElt(i) < 0;
22203 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22204 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22205 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22206 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22211 // Only handle 128 wide vector from here on.
22212 if (!VT.is128BitVector())
22215 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22216 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22217 // consecutive, non-overlapping, and in the right order.
22218 SmallVector<SDValue, 16> Elts;
22219 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22220 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22222 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22226 if (isTargetShuffle(N->getOpcode())) {
22228 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22229 if (Shuffle.getNode())
22232 // Try recursively combining arbitrary sequences of x86 shuffle
22233 // instructions into higher-order shuffles. We do this after combining
22234 // specific PSHUF instruction sequences into their minimal form so that we
22235 // can evaluate how many specialized shuffle instructions are involved in
22236 // a particular chain.
22237 SmallVector<int, 1> NonceMask; // Just a placeholder.
22238 NonceMask.push_back(0);
22239 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22240 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22242 return SDValue(); // This routine will use CombineTo to replace N.
22248 /// PerformTruncateCombine - Converts truncate operation to
22249 /// a sequence of vector shuffle operations.
22250 /// It is possible when we truncate 256-bit vector to 128-bit vector
22251 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22252 TargetLowering::DAGCombinerInfo &DCI,
22253 const X86Subtarget *Subtarget) {
22257 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22258 /// specific shuffle of a load can be folded into a single element load.
22259 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22260 /// shuffles have been custom lowered so we need to handle those here.
22261 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22262 TargetLowering::DAGCombinerInfo &DCI) {
22263 if (DCI.isBeforeLegalizeOps())
22266 SDValue InVec = N->getOperand(0);
22267 SDValue EltNo = N->getOperand(1);
22269 if (!isa<ConstantSDNode>(EltNo))
22272 EVT OriginalVT = InVec.getValueType();
22274 if (InVec.getOpcode() == ISD::BITCAST) {
22275 // Don't duplicate a load with other uses.
22276 if (!InVec.hasOneUse())
22278 EVT BCVT = InVec.getOperand(0).getValueType();
22279 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22281 InVec = InVec.getOperand(0);
22284 EVT CurrentVT = InVec.getValueType();
22286 if (!isTargetShuffle(InVec.getOpcode()))
22289 // Don't duplicate a load with other uses.
22290 if (!InVec.hasOneUse())
22293 SmallVector<int, 16> ShuffleMask;
22295 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22296 ShuffleMask, UnaryShuffle))
22299 // Select the input vector, guarding against out of range extract vector.
22300 unsigned NumElems = CurrentVT.getVectorNumElements();
22301 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22302 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22303 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22304 : InVec.getOperand(1);
22306 // If inputs to shuffle are the same for both ops, then allow 2 uses
22307 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22309 if (LdNode.getOpcode() == ISD::BITCAST) {
22310 // Don't duplicate a load with other uses.
22311 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22314 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22315 LdNode = LdNode.getOperand(0);
22318 if (!ISD::isNormalLoad(LdNode.getNode()))
22321 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22323 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22326 EVT EltVT = N->getValueType(0);
22327 // If there's a bitcast before the shuffle, check if the load type and
22328 // alignment is valid.
22329 unsigned Align = LN0->getAlignment();
22330 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22331 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22332 EltVT.getTypeForEVT(*DAG.getContext()));
22334 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22337 // All checks match so transform back to vector_shuffle so that DAG combiner
22338 // can finish the job
22341 // Create shuffle node taking into account the case that its a unary shuffle
22342 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22343 : InVec.getOperand(1);
22344 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22345 InVec.getOperand(0), Shuffle,
22347 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22348 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22352 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22353 /// generation and convert it from being a bunch of shuffles and extracts
22354 /// to a simple store and scalar loads to extract the elements.
22355 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22356 TargetLowering::DAGCombinerInfo &DCI) {
22357 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22358 if (NewOp.getNode())
22361 SDValue InputVector = N->getOperand(0);
22363 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22364 // from mmx to v2i32 has a single usage.
22365 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22366 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22367 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22368 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22369 N->getValueType(0),
22370 InputVector.getNode()->getOperand(0));
22372 // Only operate on vectors of 4 elements, where the alternative shuffling
22373 // gets to be more expensive.
22374 if (InputVector.getValueType() != MVT::v4i32)
22377 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22378 // single use which is a sign-extend or zero-extend, and all elements are
22380 SmallVector<SDNode *, 4> Uses;
22381 unsigned ExtractedElements = 0;
22382 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22383 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22384 if (UI.getUse().getResNo() != InputVector.getResNo())
22387 SDNode *Extract = *UI;
22388 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22391 if (Extract->getValueType(0) != MVT::i32)
22393 if (!Extract->hasOneUse())
22395 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22396 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22398 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22401 // Record which element was extracted.
22402 ExtractedElements |=
22403 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22405 Uses.push_back(Extract);
22408 // If not all the elements were used, this may not be worthwhile.
22409 if (ExtractedElements != 15)
22412 // Ok, we've now decided to do the transformation.
22413 SDLoc dl(InputVector);
22415 // Store the value to a temporary stack slot.
22416 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22417 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22418 MachinePointerInfo(), false, false, 0);
22420 // Replace each use (extract) with a load of the appropriate element.
22421 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22422 UE = Uses.end(); UI != UE; ++UI) {
22423 SDNode *Extract = *UI;
22425 // cOMpute the element's address.
22426 SDValue Idx = Extract->getOperand(1);
22428 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22429 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22430 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22431 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22433 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22434 StackPtr, OffsetVal);
22436 // Load the scalar.
22437 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22438 ScalarAddr, MachinePointerInfo(),
22439 false, false, false, 0);
22441 // Replace the exact with the load.
22442 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22445 // The replacement was made in place; don't return anything.
22449 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22450 static std::pair<unsigned, bool>
22451 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22452 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22453 if (!VT.isVector())
22454 return std::make_pair(0, false);
22456 bool NeedSplit = false;
22457 switch (VT.getSimpleVT().SimpleTy) {
22458 default: return std::make_pair(0, false);
22462 if (!Subtarget->hasAVX2())
22464 if (!Subtarget->hasAVX())
22465 return std::make_pair(0, false);
22470 if (!Subtarget->hasSSE2())
22471 return std::make_pair(0, false);
22474 // SSE2 has only a small subset of the operations.
22475 bool hasUnsigned = Subtarget->hasSSE41() ||
22476 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22477 bool hasSigned = Subtarget->hasSSE41() ||
22478 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22480 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22483 // Check for x CC y ? x : y.
22484 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22485 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22490 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22493 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22496 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22499 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22501 // Check for x CC y ? y : x -- a min/max with reversed arms.
22502 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22503 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22508 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22511 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22514 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22517 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22521 return std::make_pair(Opc, NeedSplit);
22525 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22526 const X86Subtarget *Subtarget) {
22528 SDValue Cond = N->getOperand(0);
22529 SDValue LHS = N->getOperand(1);
22530 SDValue RHS = N->getOperand(2);
22532 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22533 SDValue CondSrc = Cond->getOperand(0);
22534 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22535 Cond = CondSrc->getOperand(0);
22538 MVT VT = N->getSimpleValueType(0);
22539 MVT EltVT = VT.getVectorElementType();
22540 unsigned NumElems = VT.getVectorNumElements();
22541 // There is no blend with immediate in AVX-512.
22542 if (VT.is512BitVector())
22545 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
22547 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
22550 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22553 // A vselect where all conditions and data are constants can be optimized into
22554 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22555 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22556 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22559 unsigned MaskValue = 0;
22560 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22563 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22564 for (unsigned i = 0; i < NumElems; ++i) {
22565 // Be sure we emit undef where we can.
22566 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22567 ShuffleMask[i] = -1;
22569 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22572 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22575 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22577 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22578 TargetLowering::DAGCombinerInfo &DCI,
22579 const X86Subtarget *Subtarget) {
22581 SDValue Cond = N->getOperand(0);
22582 // Get the LHS/RHS of the select.
22583 SDValue LHS = N->getOperand(1);
22584 SDValue RHS = N->getOperand(2);
22585 EVT VT = LHS.getValueType();
22586 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22588 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22589 // instructions match the semantics of the common C idiom x<y?x:y but not
22590 // x<=y?x:y, because of how they handle negative zero (which can be
22591 // ignored in unsafe-math mode).
22592 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22593 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22594 (Subtarget->hasSSE2() ||
22595 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22596 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22598 unsigned Opcode = 0;
22599 // Check for x CC y ? x : y.
22600 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22601 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22605 // Converting this to a min would handle NaNs incorrectly, and swapping
22606 // the operands would cause it to handle comparisons between positive
22607 // and negative zero incorrectly.
22608 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22609 if (!DAG.getTarget().Options.UnsafeFPMath &&
22610 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22612 std::swap(LHS, RHS);
22614 Opcode = X86ISD::FMIN;
22617 // Converting this to a min would handle comparisons between positive
22618 // and negative zero incorrectly.
22619 if (!DAG.getTarget().Options.UnsafeFPMath &&
22620 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22622 Opcode = X86ISD::FMIN;
22625 // Converting this to a min would handle both negative zeros and NaNs
22626 // incorrectly, but we can swap the operands to fix both.
22627 std::swap(LHS, RHS);
22631 Opcode = X86ISD::FMIN;
22635 // Converting this to a max would handle comparisons between positive
22636 // and negative zero incorrectly.
22637 if (!DAG.getTarget().Options.UnsafeFPMath &&
22638 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22640 Opcode = X86ISD::FMAX;
22643 // Converting this to a max would handle NaNs incorrectly, and swapping
22644 // the operands would cause it to handle comparisons between positive
22645 // and negative zero incorrectly.
22646 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22647 if (!DAG.getTarget().Options.UnsafeFPMath &&
22648 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22650 std::swap(LHS, RHS);
22652 Opcode = X86ISD::FMAX;
22655 // Converting this to a max would handle both negative zeros and NaNs
22656 // incorrectly, but we can swap the operands to fix both.
22657 std::swap(LHS, RHS);
22661 Opcode = X86ISD::FMAX;
22664 // Check for x CC y ? y : x -- a min/max with reversed arms.
22665 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22666 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22670 // Converting this to a min would handle comparisons between positive
22671 // and negative zero incorrectly, and swapping the operands would
22672 // cause it to handle NaNs incorrectly.
22673 if (!DAG.getTarget().Options.UnsafeFPMath &&
22674 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22675 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22677 std::swap(LHS, RHS);
22679 Opcode = X86ISD::FMIN;
22682 // Converting this to a min would handle NaNs incorrectly.
22683 if (!DAG.getTarget().Options.UnsafeFPMath &&
22684 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22686 Opcode = X86ISD::FMIN;
22689 // Converting this to a min would handle both negative zeros and NaNs
22690 // incorrectly, but we can swap the operands to fix both.
22691 std::swap(LHS, RHS);
22695 Opcode = X86ISD::FMIN;
22699 // Converting this to a max would handle NaNs incorrectly.
22700 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22702 Opcode = X86ISD::FMAX;
22705 // Converting this to a max would handle comparisons between positive
22706 // and negative zero incorrectly, and swapping the operands would
22707 // cause it to handle NaNs incorrectly.
22708 if (!DAG.getTarget().Options.UnsafeFPMath &&
22709 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22710 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22712 std::swap(LHS, RHS);
22714 Opcode = X86ISD::FMAX;
22717 // Converting this to a max would handle both negative zeros and NaNs
22718 // incorrectly, but we can swap the operands to fix both.
22719 std::swap(LHS, RHS);
22723 Opcode = X86ISD::FMAX;
22729 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22732 EVT CondVT = Cond.getValueType();
22733 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22734 CondVT.getVectorElementType() == MVT::i1) {
22735 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22736 // lowering on KNL. In this case we convert it to
22737 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22738 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22739 // Since SKX these selects have a proper lowering.
22740 EVT OpVT = LHS.getValueType();
22741 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22742 (OpVT.getVectorElementType() == MVT::i8 ||
22743 OpVT.getVectorElementType() == MVT::i16) &&
22744 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22745 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22746 DCI.AddToWorklist(Cond.getNode());
22747 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22750 // If this is a select between two integer constants, try to do some
22752 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22753 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22754 // Don't do this for crazy integer types.
22755 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22756 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22757 // so that TrueC (the true value) is larger than FalseC.
22758 bool NeedsCondInvert = false;
22760 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22761 // Efficiently invertible.
22762 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22763 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22764 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22765 NeedsCondInvert = true;
22766 std::swap(TrueC, FalseC);
22769 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22770 if (FalseC->getAPIntValue() == 0 &&
22771 TrueC->getAPIntValue().isPowerOf2()) {
22772 if (NeedsCondInvert) // Invert the condition if needed.
22773 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22774 DAG.getConstant(1, Cond.getValueType()));
22776 // Zero extend the condition if needed.
22777 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22779 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22780 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22781 DAG.getConstant(ShAmt, MVT::i8));
22784 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22785 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22786 if (NeedsCondInvert) // Invert the condition if needed.
22787 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22788 DAG.getConstant(1, Cond.getValueType()));
22790 // Zero extend the condition if needed.
22791 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22792 FalseC->getValueType(0), Cond);
22793 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22794 SDValue(FalseC, 0));
22797 // Optimize cases that will turn into an LEA instruction. This requires
22798 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22799 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22800 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22801 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22803 bool isFastMultiplier = false;
22805 switch ((unsigned char)Diff) {
22807 case 1: // result = add base, cond
22808 case 2: // result = lea base( , cond*2)
22809 case 3: // result = lea base(cond, cond*2)
22810 case 4: // result = lea base( , cond*4)
22811 case 5: // result = lea base(cond, cond*4)
22812 case 8: // result = lea base( , cond*8)
22813 case 9: // result = lea base(cond, cond*8)
22814 isFastMultiplier = true;
22819 if (isFastMultiplier) {
22820 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22821 if (NeedsCondInvert) // Invert the condition if needed.
22822 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22823 DAG.getConstant(1, Cond.getValueType()));
22825 // Zero extend the condition if needed.
22826 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22828 // Scale the condition by the difference.
22830 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22831 DAG.getConstant(Diff, Cond.getValueType()));
22833 // Add the base if non-zero.
22834 if (FalseC->getAPIntValue() != 0)
22835 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22836 SDValue(FalseC, 0));
22843 // Canonicalize max and min:
22844 // (x > y) ? x : y -> (x >= y) ? x : y
22845 // (x < y) ? x : y -> (x <= y) ? x : y
22846 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22847 // the need for an extra compare
22848 // against zero. e.g.
22849 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22851 // testl %edi, %edi
22853 // cmovgl %edi, %eax
22857 // cmovsl %eax, %edi
22858 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22859 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22860 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22861 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22866 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22867 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22868 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22869 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22874 // Early exit check
22875 if (!TLI.isTypeLegal(VT))
22878 // Match VSELECTs into subs with unsigned saturation.
22879 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22880 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22881 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22882 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22883 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22885 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22886 // left side invert the predicate to simplify logic below.
22888 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22890 CC = ISD::getSetCCInverse(CC, true);
22891 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22895 if (Other.getNode() && Other->getNumOperands() == 2 &&
22896 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22897 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22898 SDValue CondRHS = Cond->getOperand(1);
22900 // Look for a general sub with unsigned saturation first.
22901 // x >= y ? x-y : 0 --> subus x, y
22902 // x > y ? x-y : 0 --> subus x, y
22903 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22904 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22905 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22907 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22908 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22909 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22910 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22911 // If the RHS is a constant we have to reverse the const
22912 // canonicalization.
22913 // x > C-1 ? x+-C : 0 --> subus x, C
22914 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22915 CondRHSConst->getAPIntValue() ==
22916 (-OpRHSConst->getAPIntValue() - 1))
22917 return DAG.getNode(
22918 X86ISD::SUBUS, DL, VT, OpLHS,
22919 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22921 // Another special case: If C was a sign bit, the sub has been
22922 // canonicalized into a xor.
22923 // FIXME: Would it be better to use computeKnownBits to determine
22924 // whether it's safe to decanonicalize the xor?
22925 // x s< 0 ? x^C : 0 --> subus x, C
22926 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22927 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22928 OpRHSConst->getAPIntValue().isSignBit())
22929 // Note that we have to rebuild the RHS constant here to ensure we
22930 // don't rely on particular values of undef lanes.
22931 return DAG.getNode(
22932 X86ISD::SUBUS, DL, VT, OpLHS,
22933 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22938 // Try to match a min/max vector operation.
22939 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22940 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22941 unsigned Opc = ret.first;
22942 bool NeedSplit = ret.second;
22944 if (Opc && NeedSplit) {
22945 unsigned NumElems = VT.getVectorNumElements();
22946 // Extract the LHS vectors
22947 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22948 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22950 // Extract the RHS vectors
22951 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22952 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22954 // Create min/max for each subvector
22955 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22956 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22958 // Merge the result
22959 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22961 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22964 // Simplify vector selection if condition value type matches vselect
22966 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22967 assert(Cond.getValueType().isVector() &&
22968 "vector select expects a vector selector!");
22970 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22971 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22973 // Try invert the condition if true value is not all 1s and false value
22975 if (!TValIsAllOnes && !FValIsAllZeros &&
22976 // Check if the selector will be produced by CMPP*/PCMP*
22977 Cond.getOpcode() == ISD::SETCC &&
22978 // Check if SETCC has already been promoted
22979 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
22980 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22981 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22983 if (TValIsAllZeros || FValIsAllOnes) {
22984 SDValue CC = Cond.getOperand(2);
22985 ISD::CondCode NewCC =
22986 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22987 Cond.getOperand(0).getValueType().isInteger());
22988 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22989 std::swap(LHS, RHS);
22990 TValIsAllOnes = FValIsAllOnes;
22991 FValIsAllZeros = TValIsAllZeros;
22995 if (TValIsAllOnes || FValIsAllZeros) {
22998 if (TValIsAllOnes && FValIsAllZeros)
23000 else if (TValIsAllOnes)
23001 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23002 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23003 else if (FValIsAllZeros)
23004 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23005 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23007 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23011 // Try to fold this VSELECT into a MOVSS/MOVSD
23012 if (N->getOpcode() == ISD::VSELECT &&
23013 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
23014 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
23015 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
23016 bool CanFold = false;
23017 unsigned NumElems = Cond.getNumOperands();
23021 if (isZero(Cond.getOperand(0))) {
23024 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
23025 // fold (vselect <0,-1> -> (movsd A, B)
23026 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
23027 CanFold = isAllOnes(Cond.getOperand(i));
23028 } else if (isAllOnes(Cond.getOperand(0))) {
23032 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
23033 // fold (vselect <-1,0> -> (movsd B, A)
23034 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
23035 CanFold = isZero(Cond.getOperand(i));
23039 if (VT == MVT::v4i32 || VT == MVT::v4f32)
23040 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
23041 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
23044 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
23045 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
23046 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
23047 // (v2i64 (bitcast B)))))
23049 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
23050 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
23051 // (v2f64 (bitcast B)))))
23053 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
23054 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
23055 // (v2i64 (bitcast A)))))
23057 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
23058 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
23059 // (v2f64 (bitcast A)))))
23061 CanFold = (isZero(Cond.getOperand(0)) &&
23062 isZero(Cond.getOperand(1)) &&
23063 isAllOnes(Cond.getOperand(2)) &&
23064 isAllOnes(Cond.getOperand(3)));
23066 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
23067 isAllOnes(Cond.getOperand(1)) &&
23068 isZero(Cond.getOperand(2)) &&
23069 isZero(Cond.getOperand(3))) {
23071 std::swap(LHS, RHS);
23075 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
23076 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
23077 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
23078 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
23080 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
23086 // If we know that this node is legal then we know that it is going to be
23087 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23088 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23089 // to simplify previous instructions.
23090 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23091 !DCI.isBeforeLegalize() &&
23092 // We explicitly check against v8i16 and v16i16 because, although
23093 // they're marked as Custom, they might only be legal when Cond is a
23094 // build_vector of constants. This will be taken care in a later
23096 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23097 VT != MVT::v8i16) &&
23098 // Don't optimize vector of constants. Those are handled by
23099 // the generic code and all the bits must be properly set for
23100 // the generic optimizer.
23101 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23102 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23104 // Don't optimize vector selects that map to mask-registers.
23108 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23109 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23111 APInt KnownZero, KnownOne;
23112 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23113 DCI.isBeforeLegalizeOps());
23114 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23115 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23117 // If we changed the computation somewhere in the DAG, this change
23118 // will affect all users of Cond.
23119 // Make sure it is fine and update all the nodes so that we do not
23120 // use the generic VSELECT anymore. Otherwise, we may perform
23121 // wrong optimizations as we messed up with the actual expectation
23122 // for the vector boolean values.
23123 if (Cond != TLO.Old) {
23124 // Check all uses of that condition operand to check whether it will be
23125 // consumed by non-BLEND instructions, which may depend on all bits are
23127 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23129 if (I->getOpcode() != ISD::VSELECT)
23130 // TODO: Add other opcodes eventually lowered into BLEND.
23133 // Update all the users of the condition, before committing the change,
23134 // so that the VSELECT optimizations that expect the correct vector
23135 // boolean value will not be triggered.
23136 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23138 DAG.ReplaceAllUsesOfValueWith(
23140 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23141 Cond, I->getOperand(1), I->getOperand(2)));
23142 DCI.CommitTargetLoweringOpt(TLO);
23145 // At this point, only Cond is changed. Change the condition
23146 // just for N to keep the opportunity to optimize all other
23147 // users their own way.
23148 DAG.ReplaceAllUsesOfValueWith(
23150 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23151 TLO.New, N->getOperand(1), N->getOperand(2)));
23156 // We should generate an X86ISD::BLENDI from a vselect if its argument
23157 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23158 // constants. This specific pattern gets generated when we split a
23159 // selector for a 512 bit vector in a machine without AVX512 (but with
23160 // 256-bit vectors), during legalization:
23162 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23164 // Iff we find this pattern and the build_vectors are built from
23165 // constants, we translate the vselect into a shuffle_vector that we
23166 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23167 if ((N->getOpcode() == ISD::VSELECT ||
23168 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23169 !DCI.isBeforeLegalize()) {
23170 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23171 if (Shuffle.getNode())
23178 // Check whether a boolean test is testing a boolean value generated by
23179 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23182 // Simplify the following patterns:
23183 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23184 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23185 // to (Op EFLAGS Cond)
23187 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23188 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23189 // to (Op EFLAGS !Cond)
23191 // where Op could be BRCOND or CMOV.
23193 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23194 // Quit if not CMP and SUB with its value result used.
23195 if (Cmp.getOpcode() != X86ISD::CMP &&
23196 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23199 // Quit if not used as a boolean value.
23200 if (CC != X86::COND_E && CC != X86::COND_NE)
23203 // Check CMP operands. One of them should be 0 or 1 and the other should be
23204 // an SetCC or extended from it.
23205 SDValue Op1 = Cmp.getOperand(0);
23206 SDValue Op2 = Cmp.getOperand(1);
23209 const ConstantSDNode* C = nullptr;
23210 bool needOppositeCond = (CC == X86::COND_E);
23211 bool checkAgainstTrue = false; // Is it a comparison against 1?
23213 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23215 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23217 else // Quit if all operands are not constants.
23220 if (C->getZExtValue() == 1) {
23221 needOppositeCond = !needOppositeCond;
23222 checkAgainstTrue = true;
23223 } else if (C->getZExtValue() != 0)
23224 // Quit if the constant is neither 0 or 1.
23227 bool truncatedToBoolWithAnd = false;
23228 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23229 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23230 SetCC.getOpcode() == ISD::TRUNCATE ||
23231 SetCC.getOpcode() == ISD::AND) {
23232 if (SetCC.getOpcode() == ISD::AND) {
23234 ConstantSDNode *CS;
23235 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23236 CS->getZExtValue() == 1)
23238 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23239 CS->getZExtValue() == 1)
23243 SetCC = SetCC.getOperand(OpIdx);
23244 truncatedToBoolWithAnd = true;
23246 SetCC = SetCC.getOperand(0);
23249 switch (SetCC.getOpcode()) {
23250 case X86ISD::SETCC_CARRY:
23251 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23252 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23253 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23254 // truncated to i1 using 'and'.
23255 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23257 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23258 "Invalid use of SETCC_CARRY!");
23260 case X86ISD::SETCC:
23261 // Set the condition code or opposite one if necessary.
23262 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23263 if (needOppositeCond)
23264 CC = X86::GetOppositeBranchCondition(CC);
23265 return SetCC.getOperand(1);
23266 case X86ISD::CMOV: {
23267 // Check whether false/true value has canonical one, i.e. 0 or 1.
23268 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23269 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23270 // Quit if true value is not a constant.
23273 // Quit if false value is not a constant.
23275 SDValue Op = SetCC.getOperand(0);
23276 // Skip 'zext' or 'trunc' node.
23277 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23278 Op.getOpcode() == ISD::TRUNCATE)
23279 Op = Op.getOperand(0);
23280 // A special case for rdrand/rdseed, where 0 is set if false cond is
23282 if ((Op.getOpcode() != X86ISD::RDRAND &&
23283 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23286 // Quit if false value is not the constant 0 or 1.
23287 bool FValIsFalse = true;
23288 if (FVal && FVal->getZExtValue() != 0) {
23289 if (FVal->getZExtValue() != 1)
23291 // If FVal is 1, opposite cond is needed.
23292 needOppositeCond = !needOppositeCond;
23293 FValIsFalse = false;
23295 // Quit if TVal is not the constant opposite of FVal.
23296 if (FValIsFalse && TVal->getZExtValue() != 1)
23298 if (!FValIsFalse && TVal->getZExtValue() != 0)
23300 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23301 if (needOppositeCond)
23302 CC = X86::GetOppositeBranchCondition(CC);
23303 return SetCC.getOperand(3);
23310 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23311 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23312 TargetLowering::DAGCombinerInfo &DCI,
23313 const X86Subtarget *Subtarget) {
23316 // If the flag operand isn't dead, don't touch this CMOV.
23317 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23320 SDValue FalseOp = N->getOperand(0);
23321 SDValue TrueOp = N->getOperand(1);
23322 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23323 SDValue Cond = N->getOperand(3);
23325 if (CC == X86::COND_E || CC == X86::COND_NE) {
23326 switch (Cond.getOpcode()) {
23330 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23331 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23332 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23338 Flags = checkBoolTestSetCCCombine(Cond, CC);
23339 if (Flags.getNode() &&
23340 // Extra check as FCMOV only supports a subset of X86 cond.
23341 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23342 SDValue Ops[] = { FalseOp, TrueOp,
23343 DAG.getConstant(CC, MVT::i8), Flags };
23344 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23347 // If this is a select between two integer constants, try to do some
23348 // optimizations. Note that the operands are ordered the opposite of SELECT
23350 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23351 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23352 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23353 // larger than FalseC (the false value).
23354 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23355 CC = X86::GetOppositeBranchCondition(CC);
23356 std::swap(TrueC, FalseC);
23357 std::swap(TrueOp, FalseOp);
23360 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23361 // This is efficient for any integer data type (including i8/i16) and
23363 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23364 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23365 DAG.getConstant(CC, MVT::i8), Cond);
23367 // Zero extend the condition if needed.
23368 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23370 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23371 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23372 DAG.getConstant(ShAmt, MVT::i8));
23373 if (N->getNumValues() == 2) // Dead flag value?
23374 return DCI.CombineTo(N, Cond, SDValue());
23378 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23379 // for any integer data type, including i8/i16.
23380 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23381 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23382 DAG.getConstant(CC, MVT::i8), Cond);
23384 // Zero extend the condition if needed.
23385 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23386 FalseC->getValueType(0), Cond);
23387 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23388 SDValue(FalseC, 0));
23390 if (N->getNumValues() == 2) // Dead flag value?
23391 return DCI.CombineTo(N, Cond, SDValue());
23395 // Optimize cases that will turn into an LEA instruction. This requires
23396 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23397 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23398 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23399 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23401 bool isFastMultiplier = false;
23403 switch ((unsigned char)Diff) {
23405 case 1: // result = add base, cond
23406 case 2: // result = lea base( , cond*2)
23407 case 3: // result = lea base(cond, cond*2)
23408 case 4: // result = lea base( , cond*4)
23409 case 5: // result = lea base(cond, cond*4)
23410 case 8: // result = lea base( , cond*8)
23411 case 9: // result = lea base(cond, cond*8)
23412 isFastMultiplier = true;
23417 if (isFastMultiplier) {
23418 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23419 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23420 DAG.getConstant(CC, MVT::i8), Cond);
23421 // Zero extend the condition if needed.
23422 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23424 // Scale the condition by the difference.
23426 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23427 DAG.getConstant(Diff, Cond.getValueType()));
23429 // Add the base if non-zero.
23430 if (FalseC->getAPIntValue() != 0)
23431 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23432 SDValue(FalseC, 0));
23433 if (N->getNumValues() == 2) // Dead flag value?
23434 return DCI.CombineTo(N, Cond, SDValue());
23441 // Handle these cases:
23442 // (select (x != c), e, c) -> select (x != c), e, x),
23443 // (select (x == c), c, e) -> select (x == c), x, e)
23444 // where the c is an integer constant, and the "select" is the combination
23445 // of CMOV and CMP.
23447 // The rationale for this change is that the conditional-move from a constant
23448 // needs two instructions, however, conditional-move from a register needs
23449 // only one instruction.
23451 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23452 // some instruction-combining opportunities. This opt needs to be
23453 // postponed as late as possible.
23455 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23456 // the DCI.xxxx conditions are provided to postpone the optimization as
23457 // late as possible.
23459 ConstantSDNode *CmpAgainst = nullptr;
23460 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23461 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23462 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23464 if (CC == X86::COND_NE &&
23465 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23466 CC = X86::GetOppositeBranchCondition(CC);
23467 std::swap(TrueOp, FalseOp);
23470 if (CC == X86::COND_E &&
23471 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23472 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23473 DAG.getConstant(CC, MVT::i8), Cond };
23474 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23482 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23483 const X86Subtarget *Subtarget) {
23484 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23486 default: return SDValue();
23487 // SSE/AVX/AVX2 blend intrinsics.
23488 case Intrinsic::x86_avx2_pblendvb:
23489 case Intrinsic::x86_avx2_pblendw:
23490 case Intrinsic::x86_avx2_pblendd_128:
23491 case Intrinsic::x86_avx2_pblendd_256:
23492 // Don't try to simplify this intrinsic if we don't have AVX2.
23493 if (!Subtarget->hasAVX2())
23496 case Intrinsic::x86_avx_blend_pd_256:
23497 case Intrinsic::x86_avx_blend_ps_256:
23498 case Intrinsic::x86_avx_blendv_pd_256:
23499 case Intrinsic::x86_avx_blendv_ps_256:
23500 // Don't try to simplify this intrinsic if we don't have AVX.
23501 if (!Subtarget->hasAVX())
23504 case Intrinsic::x86_sse41_pblendw:
23505 case Intrinsic::x86_sse41_blendpd:
23506 case Intrinsic::x86_sse41_blendps:
23507 case Intrinsic::x86_sse41_blendvps:
23508 case Intrinsic::x86_sse41_blendvpd:
23509 case Intrinsic::x86_sse41_pblendvb: {
23510 SDValue Op0 = N->getOperand(1);
23511 SDValue Op1 = N->getOperand(2);
23512 SDValue Mask = N->getOperand(3);
23514 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23515 if (!Subtarget->hasSSE41())
23518 // fold (blend A, A, Mask) -> A
23521 // fold (blend A, B, allZeros) -> A
23522 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23524 // fold (blend A, B, allOnes) -> B
23525 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23528 // Simplify the case where the mask is a constant i32 value.
23529 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23530 if (C->isNullValue())
23532 if (C->isAllOnesValue())
23539 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23540 case Intrinsic::x86_sse2_psrai_w:
23541 case Intrinsic::x86_sse2_psrai_d:
23542 case Intrinsic::x86_avx2_psrai_w:
23543 case Intrinsic::x86_avx2_psrai_d:
23544 case Intrinsic::x86_sse2_psra_w:
23545 case Intrinsic::x86_sse2_psra_d:
23546 case Intrinsic::x86_avx2_psra_w:
23547 case Intrinsic::x86_avx2_psra_d: {
23548 SDValue Op0 = N->getOperand(1);
23549 SDValue Op1 = N->getOperand(2);
23550 EVT VT = Op0.getValueType();
23551 assert(VT.isVector() && "Expected a vector type!");
23553 if (isa<BuildVectorSDNode>(Op1))
23554 Op1 = Op1.getOperand(0);
23556 if (!isa<ConstantSDNode>(Op1))
23559 EVT SVT = VT.getVectorElementType();
23560 unsigned SVTBits = SVT.getSizeInBits();
23562 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23563 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23564 uint64_t ShAmt = C.getZExtValue();
23566 // Don't try to convert this shift into a ISD::SRA if the shift
23567 // count is bigger than or equal to the element size.
23568 if (ShAmt >= SVTBits)
23571 // Trivial case: if the shift count is zero, then fold this
23572 // into the first operand.
23576 // Replace this packed shift intrinsic with a target independent
23578 SDValue Splat = DAG.getConstant(C, VT);
23579 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23584 /// PerformMulCombine - Optimize a single multiply with constant into two
23585 /// in order to implement it with two cheaper instructions, e.g.
23586 /// LEA + SHL, LEA + LEA.
23587 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23588 TargetLowering::DAGCombinerInfo &DCI) {
23589 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23592 EVT VT = N->getValueType(0);
23593 if (VT != MVT::i64)
23596 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23599 uint64_t MulAmt = C->getZExtValue();
23600 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23603 uint64_t MulAmt1 = 0;
23604 uint64_t MulAmt2 = 0;
23605 if ((MulAmt % 9) == 0) {
23607 MulAmt2 = MulAmt / 9;
23608 } else if ((MulAmt % 5) == 0) {
23610 MulAmt2 = MulAmt / 5;
23611 } else if ((MulAmt % 3) == 0) {
23613 MulAmt2 = MulAmt / 3;
23616 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23619 if (isPowerOf2_64(MulAmt2) &&
23620 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23621 // If second multiplifer is pow2, issue it first. We want the multiply by
23622 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23624 std::swap(MulAmt1, MulAmt2);
23627 if (isPowerOf2_64(MulAmt1))
23628 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23629 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23631 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23632 DAG.getConstant(MulAmt1, VT));
23634 if (isPowerOf2_64(MulAmt2))
23635 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23636 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23638 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23639 DAG.getConstant(MulAmt2, VT));
23641 // Do not add new nodes to DAG combiner worklist.
23642 DCI.CombineTo(N, NewMul, false);
23647 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23648 SDValue N0 = N->getOperand(0);
23649 SDValue N1 = N->getOperand(1);
23650 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23651 EVT VT = N0.getValueType();
23653 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23654 // since the result of setcc_c is all zero's or all ones.
23655 if (VT.isInteger() && !VT.isVector() &&
23656 N1C && N0.getOpcode() == ISD::AND &&
23657 N0.getOperand(1).getOpcode() == ISD::Constant) {
23658 SDValue N00 = N0.getOperand(0);
23659 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23660 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23661 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23662 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23663 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23664 APInt ShAmt = N1C->getAPIntValue();
23665 Mask = Mask.shl(ShAmt);
23667 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23668 N00, DAG.getConstant(Mask, VT));
23672 // Hardware support for vector shifts is sparse which makes us scalarize the
23673 // vector operations in many cases. Also, on sandybridge ADD is faster than
23675 // (shl V, 1) -> add V,V
23676 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23677 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23678 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23679 // We shift all of the values by one. In many cases we do not have
23680 // hardware support for this operation. This is better expressed as an ADD
23682 if (N1SplatC->getZExtValue() == 1)
23683 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23689 /// \brief Returns a vector of 0s if the node in input is a vector logical
23690 /// shift by a constant amount which is known to be bigger than or equal
23691 /// to the vector element size in bits.
23692 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23693 const X86Subtarget *Subtarget) {
23694 EVT VT = N->getValueType(0);
23696 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23697 (!Subtarget->hasInt256() ||
23698 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23701 SDValue Amt = N->getOperand(1);
23703 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23704 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23705 APInt ShiftAmt = AmtSplat->getAPIntValue();
23706 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23708 // SSE2/AVX2 logical shifts always return a vector of 0s
23709 // if the shift amount is bigger than or equal to
23710 // the element size. The constant shift amount will be
23711 // encoded as a 8-bit immediate.
23712 if (ShiftAmt.trunc(8).uge(MaxAmount))
23713 return getZeroVector(VT, Subtarget, DAG, DL);
23719 /// PerformShiftCombine - Combine shifts.
23720 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23721 TargetLowering::DAGCombinerInfo &DCI,
23722 const X86Subtarget *Subtarget) {
23723 if (N->getOpcode() == ISD::SHL) {
23724 SDValue V = PerformSHLCombine(N, DAG);
23725 if (V.getNode()) return V;
23728 if (N->getOpcode() != ISD::SRA) {
23729 // Try to fold this logical shift into a zero vector.
23730 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23731 if (V.getNode()) return V;
23737 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23738 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23739 // and friends. Likewise for OR -> CMPNEQSS.
23740 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23741 TargetLowering::DAGCombinerInfo &DCI,
23742 const X86Subtarget *Subtarget) {
23745 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23746 // we're requiring SSE2 for both.
23747 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23748 SDValue N0 = N->getOperand(0);
23749 SDValue N1 = N->getOperand(1);
23750 SDValue CMP0 = N0->getOperand(1);
23751 SDValue CMP1 = N1->getOperand(1);
23754 // The SETCCs should both refer to the same CMP.
23755 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23758 SDValue CMP00 = CMP0->getOperand(0);
23759 SDValue CMP01 = CMP0->getOperand(1);
23760 EVT VT = CMP00.getValueType();
23762 if (VT == MVT::f32 || VT == MVT::f64) {
23763 bool ExpectingFlags = false;
23764 // Check for any users that want flags:
23765 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23766 !ExpectingFlags && UI != UE; ++UI)
23767 switch (UI->getOpcode()) {
23772 ExpectingFlags = true;
23774 case ISD::CopyToReg:
23775 case ISD::SIGN_EXTEND:
23776 case ISD::ZERO_EXTEND:
23777 case ISD::ANY_EXTEND:
23781 if (!ExpectingFlags) {
23782 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23783 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23785 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23786 X86::CondCode tmp = cc0;
23791 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23792 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23793 // FIXME: need symbolic constants for these magic numbers.
23794 // See X86ATTInstPrinter.cpp:printSSECC().
23795 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23796 if (Subtarget->hasAVX512()) {
23797 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23798 CMP01, DAG.getConstant(x86cc, MVT::i8));
23799 if (N->getValueType(0) != MVT::i1)
23800 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23804 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23805 CMP00.getValueType(), CMP00, CMP01,
23806 DAG.getConstant(x86cc, MVT::i8));
23808 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23809 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23811 if (is64BitFP && !Subtarget->is64Bit()) {
23812 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23813 // 64-bit integer, since that's not a legal type. Since
23814 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23815 // bits, but can do this little dance to extract the lowest 32 bits
23816 // and work with those going forward.
23817 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23819 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23821 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23822 Vector32, DAG.getIntPtrConstant(0));
23826 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23827 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23828 DAG.getConstant(1, IntVT));
23829 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23830 return OneBitOfTruth;
23838 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23839 /// so it can be folded inside ANDNP.
23840 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23841 EVT VT = N->getValueType(0);
23843 // Match direct AllOnes for 128 and 256-bit vectors
23844 if (ISD::isBuildVectorAllOnes(N))
23847 // Look through a bit convert.
23848 if (N->getOpcode() == ISD::BITCAST)
23849 N = N->getOperand(0).getNode();
23851 // Sometimes the operand may come from a insert_subvector building a 256-bit
23853 if (VT.is256BitVector() &&
23854 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23855 SDValue V1 = N->getOperand(0);
23856 SDValue V2 = N->getOperand(1);
23858 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23859 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23860 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23861 ISD::isBuildVectorAllOnes(V2.getNode()))
23868 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23869 // register. In most cases we actually compare or select YMM-sized registers
23870 // and mixing the two types creates horrible code. This method optimizes
23871 // some of the transition sequences.
23872 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23873 TargetLowering::DAGCombinerInfo &DCI,
23874 const X86Subtarget *Subtarget) {
23875 EVT VT = N->getValueType(0);
23876 if (!VT.is256BitVector())
23879 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23880 N->getOpcode() == ISD::ZERO_EXTEND ||
23881 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23883 SDValue Narrow = N->getOperand(0);
23884 EVT NarrowVT = Narrow->getValueType(0);
23885 if (!NarrowVT.is128BitVector())
23888 if (Narrow->getOpcode() != ISD::XOR &&
23889 Narrow->getOpcode() != ISD::AND &&
23890 Narrow->getOpcode() != ISD::OR)
23893 SDValue N0 = Narrow->getOperand(0);
23894 SDValue N1 = Narrow->getOperand(1);
23897 // The Left side has to be a trunc.
23898 if (N0.getOpcode() != ISD::TRUNCATE)
23901 // The type of the truncated inputs.
23902 EVT WideVT = N0->getOperand(0)->getValueType(0);
23906 // The right side has to be a 'trunc' or a constant vector.
23907 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23908 ConstantSDNode *RHSConstSplat = nullptr;
23909 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23910 RHSConstSplat = RHSBV->getConstantSplatNode();
23911 if (!RHSTrunc && !RHSConstSplat)
23914 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23916 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23919 // Set N0 and N1 to hold the inputs to the new wide operation.
23920 N0 = N0->getOperand(0);
23921 if (RHSConstSplat) {
23922 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23923 SDValue(RHSConstSplat, 0));
23924 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23925 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23926 } else if (RHSTrunc) {
23927 N1 = N1->getOperand(0);
23930 // Generate the wide operation.
23931 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23932 unsigned Opcode = N->getOpcode();
23934 case ISD::ANY_EXTEND:
23936 case ISD::ZERO_EXTEND: {
23937 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23938 APInt Mask = APInt::getAllOnesValue(InBits);
23939 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23940 return DAG.getNode(ISD::AND, DL, VT,
23941 Op, DAG.getConstant(Mask, VT));
23943 case ISD::SIGN_EXTEND:
23944 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23945 Op, DAG.getValueType(NarrowVT));
23947 llvm_unreachable("Unexpected opcode");
23951 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23952 TargetLowering::DAGCombinerInfo &DCI,
23953 const X86Subtarget *Subtarget) {
23954 EVT VT = N->getValueType(0);
23955 if (DCI.isBeforeLegalizeOps())
23958 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23962 // Create BEXTR instructions
23963 // BEXTR is ((X >> imm) & (2**size-1))
23964 if (VT == MVT::i32 || VT == MVT::i64) {
23965 SDValue N0 = N->getOperand(0);
23966 SDValue N1 = N->getOperand(1);
23969 // Check for BEXTR.
23970 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23971 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23972 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23973 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23974 if (MaskNode && ShiftNode) {
23975 uint64_t Mask = MaskNode->getZExtValue();
23976 uint64_t Shift = ShiftNode->getZExtValue();
23977 if (isMask_64(Mask)) {
23978 uint64_t MaskSize = CountPopulation_64(Mask);
23979 if (Shift + MaskSize <= VT.getSizeInBits())
23980 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23981 DAG.getConstant(Shift | (MaskSize << 8), VT));
23989 // Want to form ANDNP nodes:
23990 // 1) In the hopes of then easily combining them with OR and AND nodes
23991 // to form PBLEND/PSIGN.
23992 // 2) To match ANDN packed intrinsics
23993 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23996 SDValue N0 = N->getOperand(0);
23997 SDValue N1 = N->getOperand(1);
24000 // Check LHS for vnot
24001 if (N0.getOpcode() == ISD::XOR &&
24002 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24003 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24004 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24006 // Check RHS for vnot
24007 if (N1.getOpcode() == ISD::XOR &&
24008 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24009 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24010 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24015 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24016 TargetLowering::DAGCombinerInfo &DCI,
24017 const X86Subtarget *Subtarget) {
24018 if (DCI.isBeforeLegalizeOps())
24021 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24025 SDValue N0 = N->getOperand(0);
24026 SDValue N1 = N->getOperand(1);
24027 EVT VT = N->getValueType(0);
24029 // look for psign/blend
24030 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24031 if (!Subtarget->hasSSSE3() ||
24032 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24035 // Canonicalize pandn to RHS
24036 if (N0.getOpcode() == X86ISD::ANDNP)
24038 // or (and (m, y), (pandn m, x))
24039 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24040 SDValue Mask = N1.getOperand(0);
24041 SDValue X = N1.getOperand(1);
24043 if (N0.getOperand(0) == Mask)
24044 Y = N0.getOperand(1);
24045 if (N0.getOperand(1) == Mask)
24046 Y = N0.getOperand(0);
24048 // Check to see if the mask appeared in both the AND and ANDNP and
24052 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24053 // Look through mask bitcast.
24054 if (Mask.getOpcode() == ISD::BITCAST)
24055 Mask = Mask.getOperand(0);
24056 if (X.getOpcode() == ISD::BITCAST)
24057 X = X.getOperand(0);
24058 if (Y.getOpcode() == ISD::BITCAST)
24059 Y = Y.getOperand(0);
24061 EVT MaskVT = Mask.getValueType();
24063 // Validate that the Mask operand is a vector sra node.
24064 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24065 // there is no psrai.b
24066 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24067 unsigned SraAmt = ~0;
24068 if (Mask.getOpcode() == ISD::SRA) {
24069 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24070 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24071 SraAmt = AmtConst->getZExtValue();
24072 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24073 SDValue SraC = Mask.getOperand(1);
24074 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24076 if ((SraAmt + 1) != EltBits)
24081 // Now we know we at least have a plendvb with the mask val. See if
24082 // we can form a psignb/w/d.
24083 // psign = x.type == y.type == mask.type && y = sub(0, x);
24084 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24085 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24086 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24087 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24088 "Unsupported VT for PSIGN");
24089 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24090 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24092 // PBLENDVB only available on SSE 4.1
24093 if (!Subtarget->hasSSE41())
24096 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24098 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24099 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24100 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24101 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24102 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24106 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24109 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24110 MachineFunction &MF = DAG.getMachineFunction();
24111 bool OptForSize = MF.getFunction()->getAttributes().
24112 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24114 // SHLD/SHRD instructions have lower register pressure, but on some
24115 // platforms they have higher latency than the equivalent
24116 // series of shifts/or that would otherwise be generated.
24117 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24118 // have higher latencies and we are not optimizing for size.
24119 if (!OptForSize && Subtarget->isSHLDSlow())
24122 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24124 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24126 if (!N0.hasOneUse() || !N1.hasOneUse())
24129 SDValue ShAmt0 = N0.getOperand(1);
24130 if (ShAmt0.getValueType() != MVT::i8)
24132 SDValue ShAmt1 = N1.getOperand(1);
24133 if (ShAmt1.getValueType() != MVT::i8)
24135 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24136 ShAmt0 = ShAmt0.getOperand(0);
24137 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24138 ShAmt1 = ShAmt1.getOperand(0);
24141 unsigned Opc = X86ISD::SHLD;
24142 SDValue Op0 = N0.getOperand(0);
24143 SDValue Op1 = N1.getOperand(0);
24144 if (ShAmt0.getOpcode() == ISD::SUB) {
24145 Opc = X86ISD::SHRD;
24146 std::swap(Op0, Op1);
24147 std::swap(ShAmt0, ShAmt1);
24150 unsigned Bits = VT.getSizeInBits();
24151 if (ShAmt1.getOpcode() == ISD::SUB) {
24152 SDValue Sum = ShAmt1.getOperand(0);
24153 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24154 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24155 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24156 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24157 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24158 return DAG.getNode(Opc, DL, VT,
24160 DAG.getNode(ISD::TRUNCATE, DL,
24163 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24164 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24166 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24167 return DAG.getNode(Opc, DL, VT,
24168 N0.getOperand(0), N1.getOperand(0),
24169 DAG.getNode(ISD::TRUNCATE, DL,
24176 // Generate NEG and CMOV for integer abs.
24177 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24178 EVT VT = N->getValueType(0);
24180 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24181 // 8-bit integer abs to NEG and CMOV.
24182 if (VT.isInteger() && VT.getSizeInBits() == 8)
24185 SDValue N0 = N->getOperand(0);
24186 SDValue N1 = N->getOperand(1);
24189 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24190 // and change it to SUB and CMOV.
24191 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24192 N0.getOpcode() == ISD::ADD &&
24193 N0.getOperand(1) == N1 &&
24194 N1.getOpcode() == ISD::SRA &&
24195 N1.getOperand(0) == N0.getOperand(0))
24196 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24197 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24198 // Generate SUB & CMOV.
24199 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24200 DAG.getConstant(0, VT), N0.getOperand(0));
24202 SDValue Ops[] = { N0.getOperand(0), Neg,
24203 DAG.getConstant(X86::COND_GE, MVT::i8),
24204 SDValue(Neg.getNode(), 1) };
24205 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24210 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24211 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24212 TargetLowering::DAGCombinerInfo &DCI,
24213 const X86Subtarget *Subtarget) {
24214 if (DCI.isBeforeLegalizeOps())
24217 if (Subtarget->hasCMov()) {
24218 SDValue RV = performIntegerAbsCombine(N, DAG);
24226 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24227 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24228 TargetLowering::DAGCombinerInfo &DCI,
24229 const X86Subtarget *Subtarget) {
24230 LoadSDNode *Ld = cast<LoadSDNode>(N);
24231 EVT RegVT = Ld->getValueType(0);
24232 EVT MemVT = Ld->getMemoryVT();
24234 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24236 // On Sandybridge unaligned 256bit loads are inefficient.
24237 ISD::LoadExtType Ext = Ld->getExtensionType();
24238 unsigned Alignment = Ld->getAlignment();
24239 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24240 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
24241 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24242 unsigned NumElems = RegVT.getVectorNumElements();
24246 SDValue Ptr = Ld->getBasePtr();
24247 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24249 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24251 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24252 Ld->getPointerInfo(), Ld->isVolatile(),
24253 Ld->isNonTemporal(), Ld->isInvariant(),
24255 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24256 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24257 Ld->getPointerInfo(), Ld->isVolatile(),
24258 Ld->isNonTemporal(), Ld->isInvariant(),
24259 std::min(16U, Alignment));
24260 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24262 Load2.getValue(1));
24264 SDValue NewVec = DAG.getUNDEF(RegVT);
24265 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24266 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24267 return DCI.CombineTo(N, NewVec, TF, true);
24273 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24274 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24275 const X86Subtarget *Subtarget) {
24276 StoreSDNode *St = cast<StoreSDNode>(N);
24277 EVT VT = St->getValue().getValueType();
24278 EVT StVT = St->getMemoryVT();
24280 SDValue StoredVal = St->getOperand(1);
24281 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24283 // If we are saving a concatenation of two XMM registers, perform two stores.
24284 // On Sandy Bridge, 256-bit memory operations are executed by two
24285 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
24286 // memory operation.
24287 unsigned Alignment = St->getAlignment();
24288 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24289 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
24290 StVT == VT && !IsAligned) {
24291 unsigned NumElems = VT.getVectorNumElements();
24295 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24296 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24298 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24299 SDValue Ptr0 = St->getBasePtr();
24300 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24302 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24303 St->getPointerInfo(), St->isVolatile(),
24304 St->isNonTemporal(), Alignment);
24305 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24306 St->getPointerInfo(), St->isVolatile(),
24307 St->isNonTemporal(),
24308 std::min(16U, Alignment));
24309 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24312 // Optimize trunc store (of multiple scalars) to shuffle and store.
24313 // First, pack all of the elements in one place. Next, store to memory
24314 // in fewer chunks.
24315 if (St->isTruncatingStore() && VT.isVector()) {
24316 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24317 unsigned NumElems = VT.getVectorNumElements();
24318 assert(StVT != VT && "Cannot truncate to the same type");
24319 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24320 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24322 // From, To sizes and ElemCount must be pow of two
24323 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24324 // We are going to use the original vector elt for storing.
24325 // Accumulated smaller vector elements must be a multiple of the store size.
24326 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24328 unsigned SizeRatio = FromSz / ToSz;
24330 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24332 // Create a type on which we perform the shuffle
24333 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24334 StVT.getScalarType(), NumElems*SizeRatio);
24336 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24338 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24339 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24340 for (unsigned i = 0; i != NumElems; ++i)
24341 ShuffleVec[i] = i * SizeRatio;
24343 // Can't shuffle using an illegal type.
24344 if (!TLI.isTypeLegal(WideVecVT))
24347 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24348 DAG.getUNDEF(WideVecVT),
24350 // At this point all of the data is stored at the bottom of the
24351 // register. We now need to save it to mem.
24353 // Find the largest store unit
24354 MVT StoreType = MVT::i8;
24355 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24356 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24357 MVT Tp = (MVT::SimpleValueType)tp;
24358 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24362 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24363 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24364 (64 <= NumElems * ToSz))
24365 StoreType = MVT::f64;
24367 // Bitcast the original vector into a vector of store-size units
24368 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24369 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24370 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24371 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24372 SmallVector<SDValue, 8> Chains;
24373 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24374 TLI.getPointerTy());
24375 SDValue Ptr = St->getBasePtr();
24377 // Perform one or more big stores into memory.
24378 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24379 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24380 StoreType, ShuffWide,
24381 DAG.getIntPtrConstant(i));
24382 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24383 St->getPointerInfo(), St->isVolatile(),
24384 St->isNonTemporal(), St->getAlignment());
24385 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24386 Chains.push_back(Ch);
24389 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24392 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24393 // the FP state in cases where an emms may be missing.
24394 // A preferable solution to the general problem is to figure out the right
24395 // places to insert EMMS. This qualifies as a quick hack.
24397 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24398 if (VT.getSizeInBits() != 64)
24401 const Function *F = DAG.getMachineFunction().getFunction();
24402 bool NoImplicitFloatOps = F->getAttributes().
24403 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24404 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24405 && Subtarget->hasSSE2();
24406 if ((VT.isVector() ||
24407 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24408 isa<LoadSDNode>(St->getValue()) &&
24409 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24410 St->getChain().hasOneUse() && !St->isVolatile()) {
24411 SDNode* LdVal = St->getValue().getNode();
24412 LoadSDNode *Ld = nullptr;
24413 int TokenFactorIndex = -1;
24414 SmallVector<SDValue, 8> Ops;
24415 SDNode* ChainVal = St->getChain().getNode();
24416 // Must be a store of a load. We currently handle two cases: the load
24417 // is a direct child, and it's under an intervening TokenFactor. It is
24418 // possible to dig deeper under nested TokenFactors.
24419 if (ChainVal == LdVal)
24420 Ld = cast<LoadSDNode>(St->getChain());
24421 else if (St->getValue().hasOneUse() &&
24422 ChainVal->getOpcode() == ISD::TokenFactor) {
24423 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24424 if (ChainVal->getOperand(i).getNode() == LdVal) {
24425 TokenFactorIndex = i;
24426 Ld = cast<LoadSDNode>(St->getValue());
24428 Ops.push_back(ChainVal->getOperand(i));
24432 if (!Ld || !ISD::isNormalLoad(Ld))
24435 // If this is not the MMX case, i.e. we are just turning i64 load/store
24436 // into f64 load/store, avoid the transformation if there are multiple
24437 // uses of the loaded value.
24438 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24443 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24444 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24446 if (Subtarget->is64Bit() || F64IsLegal) {
24447 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24448 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24449 Ld->getPointerInfo(), Ld->isVolatile(),
24450 Ld->isNonTemporal(), Ld->isInvariant(),
24451 Ld->getAlignment());
24452 SDValue NewChain = NewLd.getValue(1);
24453 if (TokenFactorIndex != -1) {
24454 Ops.push_back(NewChain);
24455 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24457 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24458 St->getPointerInfo(),
24459 St->isVolatile(), St->isNonTemporal(),
24460 St->getAlignment());
24463 // Otherwise, lower to two pairs of 32-bit loads / stores.
24464 SDValue LoAddr = Ld->getBasePtr();
24465 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24466 DAG.getConstant(4, MVT::i32));
24468 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24469 Ld->getPointerInfo(),
24470 Ld->isVolatile(), Ld->isNonTemporal(),
24471 Ld->isInvariant(), Ld->getAlignment());
24472 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24473 Ld->getPointerInfo().getWithOffset(4),
24474 Ld->isVolatile(), Ld->isNonTemporal(),
24476 MinAlign(Ld->getAlignment(), 4));
24478 SDValue NewChain = LoLd.getValue(1);
24479 if (TokenFactorIndex != -1) {
24480 Ops.push_back(LoLd);
24481 Ops.push_back(HiLd);
24482 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24485 LoAddr = St->getBasePtr();
24486 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24487 DAG.getConstant(4, MVT::i32));
24489 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24490 St->getPointerInfo(),
24491 St->isVolatile(), St->isNonTemporal(),
24492 St->getAlignment());
24493 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24494 St->getPointerInfo().getWithOffset(4),
24496 St->isNonTemporal(),
24497 MinAlign(St->getAlignment(), 4));
24498 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24503 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24504 /// and return the operands for the horizontal operation in LHS and RHS. A
24505 /// horizontal operation performs the binary operation on successive elements
24506 /// of its first operand, then on successive elements of its second operand,
24507 /// returning the resulting values in a vector. For example, if
24508 /// A = < float a0, float a1, float a2, float a3 >
24510 /// B = < float b0, float b1, float b2, float b3 >
24511 /// then the result of doing a horizontal operation on A and B is
24512 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24513 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24514 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24515 /// set to A, RHS to B, and the routine returns 'true'.
24516 /// Note that the binary operation should have the property that if one of the
24517 /// operands is UNDEF then the result is UNDEF.
24518 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24519 // Look for the following pattern: if
24520 // A = < float a0, float a1, float a2, float a3 >
24521 // B = < float b0, float b1, float b2, float b3 >
24523 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24524 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24525 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24526 // which is A horizontal-op B.
24528 // At least one of the operands should be a vector shuffle.
24529 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24530 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24533 MVT VT = LHS.getSimpleValueType();
24535 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24536 "Unsupported vector type for horizontal add/sub");
24538 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24539 // operate independently on 128-bit lanes.
24540 unsigned NumElts = VT.getVectorNumElements();
24541 unsigned NumLanes = VT.getSizeInBits()/128;
24542 unsigned NumLaneElts = NumElts / NumLanes;
24543 assert((NumLaneElts % 2 == 0) &&
24544 "Vector type should have an even number of elements in each lane");
24545 unsigned HalfLaneElts = NumLaneElts/2;
24547 // View LHS in the form
24548 // LHS = VECTOR_SHUFFLE A, B, LMask
24549 // If LHS is not a shuffle then pretend it is the shuffle
24550 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24551 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24554 SmallVector<int, 16> LMask(NumElts);
24555 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24556 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24557 A = LHS.getOperand(0);
24558 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24559 B = LHS.getOperand(1);
24560 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24561 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24563 if (LHS.getOpcode() != ISD::UNDEF)
24565 for (unsigned i = 0; i != NumElts; ++i)
24569 // Likewise, view RHS in the form
24570 // RHS = VECTOR_SHUFFLE C, D, RMask
24572 SmallVector<int, 16> RMask(NumElts);
24573 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24574 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24575 C = RHS.getOperand(0);
24576 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24577 D = RHS.getOperand(1);
24578 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24579 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24581 if (RHS.getOpcode() != ISD::UNDEF)
24583 for (unsigned i = 0; i != NumElts; ++i)
24587 // Check that the shuffles are both shuffling the same vectors.
24588 if (!(A == C && B == D) && !(A == D && B == C))
24591 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24592 if (!A.getNode() && !B.getNode())
24595 // If A and B occur in reverse order in RHS, then "swap" them (which means
24596 // rewriting the mask).
24598 CommuteVectorShuffleMask(RMask, NumElts);
24600 // At this point LHS and RHS are equivalent to
24601 // LHS = VECTOR_SHUFFLE A, B, LMask
24602 // RHS = VECTOR_SHUFFLE A, B, RMask
24603 // Check that the masks correspond to performing a horizontal operation.
24604 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24605 for (unsigned i = 0; i != NumLaneElts; ++i) {
24606 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24608 // Ignore any UNDEF components.
24609 if (LIdx < 0 || RIdx < 0 ||
24610 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24611 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24614 // Check that successive elements are being operated on. If not, this is
24615 // not a horizontal operation.
24616 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24617 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24618 if (!(LIdx == Index && RIdx == Index + 1) &&
24619 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24624 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24625 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24629 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24630 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24631 const X86Subtarget *Subtarget) {
24632 EVT VT = N->getValueType(0);
24633 SDValue LHS = N->getOperand(0);
24634 SDValue RHS = N->getOperand(1);
24636 // Try to synthesize horizontal adds from adds of shuffles.
24637 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24638 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24639 isHorizontalBinOp(LHS, RHS, true))
24640 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24644 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24645 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24646 const X86Subtarget *Subtarget) {
24647 EVT VT = N->getValueType(0);
24648 SDValue LHS = N->getOperand(0);
24649 SDValue RHS = N->getOperand(1);
24651 // Try to synthesize horizontal subs from subs of shuffles.
24652 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24653 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24654 isHorizontalBinOp(LHS, RHS, false))
24655 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24659 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24660 /// X86ISD::FXOR nodes.
24661 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24662 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24663 // F[X]OR(0.0, x) -> x
24664 // F[X]OR(x, 0.0) -> x
24665 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24666 if (C->getValueAPF().isPosZero())
24667 return N->getOperand(1);
24668 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24669 if (C->getValueAPF().isPosZero())
24670 return N->getOperand(0);
24674 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24675 /// X86ISD::FMAX nodes.
24676 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24677 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24679 // Only perform optimizations if UnsafeMath is used.
24680 if (!DAG.getTarget().Options.UnsafeFPMath)
24683 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24684 // into FMINC and FMAXC, which are Commutative operations.
24685 unsigned NewOp = 0;
24686 switch (N->getOpcode()) {
24687 default: llvm_unreachable("unknown opcode");
24688 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24689 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24692 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24693 N->getOperand(0), N->getOperand(1));
24696 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24697 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24698 // FAND(0.0, x) -> 0.0
24699 // FAND(x, 0.0) -> 0.0
24700 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24701 if (C->getValueAPF().isPosZero())
24702 return N->getOperand(0);
24703 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24704 if (C->getValueAPF().isPosZero())
24705 return N->getOperand(1);
24709 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24710 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24711 // FANDN(x, 0.0) -> 0.0
24712 // FANDN(0.0, x) -> x
24713 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24714 if (C->getValueAPF().isPosZero())
24715 return N->getOperand(1);
24716 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24717 if (C->getValueAPF().isPosZero())
24718 return N->getOperand(1);
24722 static SDValue PerformBTCombine(SDNode *N,
24724 TargetLowering::DAGCombinerInfo &DCI) {
24725 // BT ignores high bits in the bit index operand.
24726 SDValue Op1 = N->getOperand(1);
24727 if (Op1.hasOneUse()) {
24728 unsigned BitWidth = Op1.getValueSizeInBits();
24729 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24730 APInt KnownZero, KnownOne;
24731 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24732 !DCI.isBeforeLegalizeOps());
24733 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24734 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24735 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24736 DCI.CommitTargetLoweringOpt(TLO);
24741 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24742 SDValue Op = N->getOperand(0);
24743 if (Op.getOpcode() == ISD::BITCAST)
24744 Op = Op.getOperand(0);
24745 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24746 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24747 VT.getVectorElementType().getSizeInBits() ==
24748 OpVT.getVectorElementType().getSizeInBits()) {
24749 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24754 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24755 const X86Subtarget *Subtarget) {
24756 EVT VT = N->getValueType(0);
24757 if (!VT.isVector())
24760 SDValue N0 = N->getOperand(0);
24761 SDValue N1 = N->getOperand(1);
24762 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24765 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24766 // both SSE and AVX2 since there is no sign-extended shift right
24767 // operation on a vector with 64-bit elements.
24768 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24769 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24770 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24771 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24772 SDValue N00 = N0.getOperand(0);
24774 // EXTLOAD has a better solution on AVX2,
24775 // it may be replaced with X86ISD::VSEXT node.
24776 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24777 if (!ISD::isNormalLoad(N00.getNode()))
24780 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24781 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24783 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24789 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24790 TargetLowering::DAGCombinerInfo &DCI,
24791 const X86Subtarget *Subtarget) {
24792 SDValue N0 = N->getOperand(0);
24793 EVT VT = N->getValueType(0);
24795 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24796 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24797 // This exposes the sext to the sdivrem lowering, so that it directly extends
24798 // from AH (which we otherwise need to do contortions to access).
24799 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24800 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24802 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24803 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24804 N0.getOperand(0), N0.getOperand(1));
24805 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24806 return R.getValue(1);
24809 if (!DCI.isBeforeLegalizeOps())
24812 if (!Subtarget->hasFp256())
24815 if (VT.isVector() && VT.getSizeInBits() == 256) {
24816 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24824 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24825 const X86Subtarget* Subtarget) {
24827 EVT VT = N->getValueType(0);
24829 // Let legalize expand this if it isn't a legal type yet.
24830 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24833 EVT ScalarVT = VT.getScalarType();
24834 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24835 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24838 SDValue A = N->getOperand(0);
24839 SDValue B = N->getOperand(1);
24840 SDValue C = N->getOperand(2);
24842 bool NegA = (A.getOpcode() == ISD::FNEG);
24843 bool NegB = (B.getOpcode() == ISD::FNEG);
24844 bool NegC = (C.getOpcode() == ISD::FNEG);
24846 // Negative multiplication when NegA xor NegB
24847 bool NegMul = (NegA != NegB);
24849 A = A.getOperand(0);
24851 B = B.getOperand(0);
24853 C = C.getOperand(0);
24857 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24859 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24861 return DAG.getNode(Opcode, dl, VT, A, B, C);
24864 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24865 TargetLowering::DAGCombinerInfo &DCI,
24866 const X86Subtarget *Subtarget) {
24867 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24868 // (and (i32 x86isd::setcc_carry), 1)
24869 // This eliminates the zext. This transformation is necessary because
24870 // ISD::SETCC is always legalized to i8.
24872 SDValue N0 = N->getOperand(0);
24873 EVT VT = N->getValueType(0);
24875 if (N0.getOpcode() == ISD::AND &&
24877 N0.getOperand(0).hasOneUse()) {
24878 SDValue N00 = N0.getOperand(0);
24879 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24880 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24881 if (!C || C->getZExtValue() != 1)
24883 return DAG.getNode(ISD::AND, dl, VT,
24884 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24885 N00.getOperand(0), N00.getOperand(1)),
24886 DAG.getConstant(1, VT));
24890 if (N0.getOpcode() == ISD::TRUNCATE &&
24892 N0.getOperand(0).hasOneUse()) {
24893 SDValue N00 = N0.getOperand(0);
24894 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24895 return DAG.getNode(ISD::AND, dl, VT,
24896 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24897 N00.getOperand(0), N00.getOperand(1)),
24898 DAG.getConstant(1, VT));
24901 if (VT.is256BitVector()) {
24902 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24907 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24908 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24909 // This exposes the zext to the udivrem lowering, so that it directly extends
24910 // from AH (which we otherwise need to do contortions to access).
24911 if (N0.getOpcode() == ISD::UDIVREM &&
24912 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24913 (VT == MVT::i32 || VT == MVT::i64)) {
24914 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24915 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24916 N0.getOperand(0), N0.getOperand(1));
24917 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24918 return R.getValue(1);
24924 // Optimize x == -y --> x+y == 0
24925 // x != -y --> x+y != 0
24926 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24927 const X86Subtarget* Subtarget) {
24928 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24929 SDValue LHS = N->getOperand(0);
24930 SDValue RHS = N->getOperand(1);
24931 EVT VT = N->getValueType(0);
24934 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24935 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24936 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24937 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24938 LHS.getValueType(), RHS, LHS.getOperand(1));
24939 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24940 addV, DAG.getConstant(0, addV.getValueType()), CC);
24942 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24943 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24944 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24945 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24946 RHS.getValueType(), LHS, RHS.getOperand(1));
24947 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24948 addV, DAG.getConstant(0, addV.getValueType()), CC);
24951 if (VT.getScalarType() == MVT::i1) {
24952 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24953 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24954 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24955 if (!IsSEXT0 && !IsVZero0)
24957 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24958 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24959 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24961 if (!IsSEXT1 && !IsVZero1)
24964 if (IsSEXT0 && IsVZero1) {
24965 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24966 if (CC == ISD::SETEQ)
24967 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24968 return LHS.getOperand(0);
24970 if (IsSEXT1 && IsVZero0) {
24971 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24972 if (CC == ISD::SETEQ)
24973 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24974 return RHS.getOperand(0);
24981 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24982 const X86Subtarget *Subtarget) {
24984 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24985 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24986 "X86insertps is only defined for v4x32");
24988 SDValue Ld = N->getOperand(1);
24989 if (MayFoldLoad(Ld)) {
24990 // Extract the countS bits from the immediate so we can get the proper
24991 // address when narrowing the vector load to a specific element.
24992 // When the second source op is a memory address, interps doesn't use
24993 // countS and just gets an f32 from that address.
24994 unsigned DestIndex =
24995 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24996 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25000 // Create this as a scalar to vector to match the instruction pattern.
25001 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25002 // countS bits are ignored when loading from memory on insertps, which
25003 // means we don't need to explicitly set them to 0.
25004 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25005 LoadScalarToVector, N->getOperand(2));
25008 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25009 // as "sbb reg,reg", since it can be extended without zext and produces
25010 // an all-ones bit which is more useful than 0/1 in some cases.
25011 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25014 return DAG.getNode(ISD::AND, DL, VT,
25015 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25016 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25017 DAG.getConstant(1, VT));
25018 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25019 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25020 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25021 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25024 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25025 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25026 TargetLowering::DAGCombinerInfo &DCI,
25027 const X86Subtarget *Subtarget) {
25029 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25030 SDValue EFLAGS = N->getOperand(1);
25032 if (CC == X86::COND_A) {
25033 // Try to convert COND_A into COND_B in an attempt to facilitate
25034 // materializing "setb reg".
25036 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25037 // cannot take an immediate as its first operand.
25039 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25040 EFLAGS.getValueType().isInteger() &&
25041 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25042 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25043 EFLAGS.getNode()->getVTList(),
25044 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25045 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25046 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25050 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25051 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25053 if (CC == X86::COND_B)
25054 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25058 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25059 if (Flags.getNode()) {
25060 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25061 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25067 // Optimize branch condition evaluation.
25069 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25070 TargetLowering::DAGCombinerInfo &DCI,
25071 const X86Subtarget *Subtarget) {
25073 SDValue Chain = N->getOperand(0);
25074 SDValue Dest = N->getOperand(1);
25075 SDValue EFLAGS = N->getOperand(3);
25076 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25080 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25081 if (Flags.getNode()) {
25082 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25083 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25090 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25091 SelectionDAG &DAG) {
25092 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25093 // optimize away operation when it's from a constant.
25095 // The general transformation is:
25096 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25097 // AND(VECTOR_CMP(x,y), constant2)
25098 // constant2 = UNARYOP(constant)
25100 // Early exit if this isn't a vector operation, the operand of the
25101 // unary operation isn't a bitwise AND, or if the sizes of the operations
25102 // aren't the same.
25103 EVT VT = N->getValueType(0);
25104 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25105 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25106 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25109 // Now check that the other operand of the AND is a constant. We could
25110 // make the transformation for non-constant splats as well, but it's unclear
25111 // that would be a benefit as it would not eliminate any operations, just
25112 // perform one more step in scalar code before moving to the vector unit.
25113 if (BuildVectorSDNode *BV =
25114 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25115 // Bail out if the vector isn't a constant.
25116 if (!BV->isConstant())
25119 // Everything checks out. Build up the new and improved node.
25121 EVT IntVT = BV->getValueType(0);
25122 // Create a new constant of the appropriate type for the transformed
25124 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25125 // The AND node needs bitcasts to/from an integer vector type around it.
25126 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25127 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25128 N->getOperand(0)->getOperand(0), MaskConst);
25129 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25136 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25137 const X86TargetLowering *XTLI) {
25138 // First try to optimize away the conversion entirely when it's
25139 // conditionally from a constant. Vectors only.
25140 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25141 if (Res != SDValue())
25144 // Now move on to more general possibilities.
25145 SDValue Op0 = N->getOperand(0);
25146 EVT InVT = Op0->getValueType(0);
25148 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25149 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25151 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25152 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25153 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25156 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25157 // a 32-bit target where SSE doesn't support i64->FP operations.
25158 if (Op0.getOpcode() == ISD::LOAD) {
25159 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25160 EVT VT = Ld->getValueType(0);
25161 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25162 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25163 !XTLI->getSubtarget()->is64Bit() &&
25165 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25166 Ld->getChain(), Op0, DAG);
25167 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25174 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25175 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25176 X86TargetLowering::DAGCombinerInfo &DCI) {
25177 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25178 // the result is either zero or one (depending on the input carry bit).
25179 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25180 if (X86::isZeroNode(N->getOperand(0)) &&
25181 X86::isZeroNode(N->getOperand(1)) &&
25182 // We don't have a good way to replace an EFLAGS use, so only do this when
25184 SDValue(N, 1).use_empty()) {
25186 EVT VT = N->getValueType(0);
25187 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25188 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25189 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25190 DAG.getConstant(X86::COND_B,MVT::i8),
25192 DAG.getConstant(1, VT));
25193 return DCI.CombineTo(N, Res1, CarryOut);
25199 // fold (add Y, (sete X, 0)) -> adc 0, Y
25200 // (add Y, (setne X, 0)) -> sbb -1, Y
25201 // (sub (sete X, 0), Y) -> sbb 0, Y
25202 // (sub (setne X, 0), Y) -> adc -1, Y
25203 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25206 // Look through ZExts.
25207 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25208 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25211 SDValue SetCC = Ext.getOperand(0);
25212 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25215 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25216 if (CC != X86::COND_E && CC != X86::COND_NE)
25219 SDValue Cmp = SetCC.getOperand(1);
25220 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25221 !X86::isZeroNode(Cmp.getOperand(1)) ||
25222 !Cmp.getOperand(0).getValueType().isInteger())
25225 SDValue CmpOp0 = Cmp.getOperand(0);
25226 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25227 DAG.getConstant(1, CmpOp0.getValueType()));
25229 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25230 if (CC == X86::COND_NE)
25231 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25232 DL, OtherVal.getValueType(), OtherVal,
25233 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25234 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25235 DL, OtherVal.getValueType(), OtherVal,
25236 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25239 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25240 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25241 const X86Subtarget *Subtarget) {
25242 EVT VT = N->getValueType(0);
25243 SDValue Op0 = N->getOperand(0);
25244 SDValue Op1 = N->getOperand(1);
25246 // Try to synthesize horizontal adds from adds of shuffles.
25247 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25248 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25249 isHorizontalBinOp(Op0, Op1, true))
25250 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25252 return OptimizeConditionalInDecrement(N, DAG);
25255 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25256 const X86Subtarget *Subtarget) {
25257 SDValue Op0 = N->getOperand(0);
25258 SDValue Op1 = N->getOperand(1);
25260 // X86 can't encode an immediate LHS of a sub. See if we can push the
25261 // negation into a preceding instruction.
25262 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25263 // If the RHS of the sub is a XOR with one use and a constant, invert the
25264 // immediate. Then add one to the LHS of the sub so we can turn
25265 // X-Y -> X+~Y+1, saving one register.
25266 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25267 isa<ConstantSDNode>(Op1.getOperand(1))) {
25268 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25269 EVT VT = Op0.getValueType();
25270 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25272 DAG.getConstant(~XorC, VT));
25273 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25274 DAG.getConstant(C->getAPIntValue()+1, VT));
25278 // Try to synthesize horizontal adds from adds of shuffles.
25279 EVT VT = N->getValueType(0);
25280 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25281 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25282 isHorizontalBinOp(Op0, Op1, true))
25283 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25285 return OptimizeConditionalInDecrement(N, DAG);
25288 /// performVZEXTCombine - Performs build vector combines
25289 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25290 TargetLowering::DAGCombinerInfo &DCI,
25291 const X86Subtarget *Subtarget) {
25293 MVT VT = N->getSimpleValueType(0);
25294 SDValue Op = N->getOperand(0);
25295 MVT OpVT = Op.getSimpleValueType();
25296 MVT OpEltVT = OpVT.getVectorElementType();
25297 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25299 // (vzext (bitcast (vzext (x)) -> (vzext x)
25301 while (V.getOpcode() == ISD::BITCAST)
25302 V = V.getOperand(0);
25304 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25305 MVT InnerVT = V.getSimpleValueType();
25306 MVT InnerEltVT = InnerVT.getVectorElementType();
25308 // If the element sizes match exactly, we can just do one larger vzext. This
25309 // is always an exact type match as vzext operates on integer types.
25310 if (OpEltVT == InnerEltVT) {
25311 assert(OpVT == InnerVT && "Types must match for vzext!");
25312 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25315 // The only other way we can combine them is if only a single element of the
25316 // inner vzext is used in the input to the outer vzext.
25317 if (InnerEltVT.getSizeInBits() < InputBits)
25320 // In this case, the inner vzext is completely dead because we're going to
25321 // only look at bits inside of the low element. Just do the outer vzext on
25322 // a bitcast of the input to the inner.
25323 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25324 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25327 // Check if we can bypass extracting and re-inserting an element of an input
25328 // vector. Essentialy:
25329 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25330 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25331 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25332 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25333 SDValue ExtractedV = V.getOperand(0);
25334 SDValue OrigV = ExtractedV.getOperand(0);
25335 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25336 if (ExtractIdx->getZExtValue() == 0) {
25337 MVT OrigVT = OrigV.getSimpleValueType();
25338 // Extract a subvector if necessary...
25339 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25340 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25341 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25342 OrigVT.getVectorNumElements() / Ratio);
25343 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25344 DAG.getIntPtrConstant(0));
25346 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25347 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25354 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25355 DAGCombinerInfo &DCI) const {
25356 SelectionDAG &DAG = DCI.DAG;
25357 switch (N->getOpcode()) {
25359 case ISD::EXTRACT_VECTOR_ELT:
25360 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25363 case X86ISD::SHRUNKBLEND:
25364 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25365 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25366 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25367 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25368 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25369 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25372 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25373 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25374 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25375 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25376 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25377 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25378 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25379 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25380 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25382 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25384 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25385 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25386 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25387 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25388 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25389 case ISD::ANY_EXTEND:
25390 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25391 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25392 case ISD::SIGN_EXTEND_INREG:
25393 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25394 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25395 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25396 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25397 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25398 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25399 case X86ISD::SHUFP: // Handle all target specific shuffles
25400 case X86ISD::PALIGNR:
25401 case X86ISD::UNPCKH:
25402 case X86ISD::UNPCKL:
25403 case X86ISD::MOVHLPS:
25404 case X86ISD::MOVLHPS:
25405 case X86ISD::PSHUFB:
25406 case X86ISD::PSHUFD:
25407 case X86ISD::PSHUFHW:
25408 case X86ISD::PSHUFLW:
25409 case X86ISD::MOVSS:
25410 case X86ISD::MOVSD:
25411 case X86ISD::VPERMILPI:
25412 case X86ISD::VPERM2X128:
25413 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25414 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25415 case ISD::INTRINSIC_WO_CHAIN:
25416 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25417 case X86ISD::INSERTPS:
25418 return PerformINSERTPSCombine(N, DAG, Subtarget);
25419 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25425 /// isTypeDesirableForOp - Return true if the target has native support for
25426 /// the specified value type and it is 'desirable' to use the type for the
25427 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25428 /// instruction encodings are longer and some i16 instructions are slow.
25429 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25430 if (!isTypeLegal(VT))
25432 if (VT != MVT::i16)
25439 case ISD::SIGN_EXTEND:
25440 case ISD::ZERO_EXTEND:
25441 case ISD::ANY_EXTEND:
25454 /// IsDesirableToPromoteOp - This method query the target whether it is
25455 /// beneficial for dag combiner to promote the specified node. If true, it
25456 /// should return the desired promotion type by reference.
25457 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25458 EVT VT = Op.getValueType();
25459 if (VT != MVT::i16)
25462 bool Promote = false;
25463 bool Commute = false;
25464 switch (Op.getOpcode()) {
25467 LoadSDNode *LD = cast<LoadSDNode>(Op);
25468 // If the non-extending load has a single use and it's not live out, then it
25469 // might be folded.
25470 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25471 Op.hasOneUse()*/) {
25472 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25473 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25474 // The only case where we'd want to promote LOAD (rather then it being
25475 // promoted as an operand is when it's only use is liveout.
25476 if (UI->getOpcode() != ISD::CopyToReg)
25483 case ISD::SIGN_EXTEND:
25484 case ISD::ZERO_EXTEND:
25485 case ISD::ANY_EXTEND:
25490 SDValue N0 = Op.getOperand(0);
25491 // Look out for (store (shl (load), x)).
25492 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25505 SDValue N0 = Op.getOperand(0);
25506 SDValue N1 = Op.getOperand(1);
25507 if (!Commute && MayFoldLoad(N1))
25509 // Avoid disabling potential load folding opportunities.
25510 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25512 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25522 //===----------------------------------------------------------------------===//
25523 // X86 Inline Assembly Support
25524 //===----------------------------------------------------------------------===//
25527 // Helper to match a string separated by whitespace.
25528 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25529 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25531 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25532 StringRef piece(*args[i]);
25533 if (!s.startswith(piece)) // Check if the piece matches.
25536 s = s.substr(piece.size());
25537 StringRef::size_type pos = s.find_first_not_of(" \t");
25538 if (pos == 0) // We matched a prefix.
25546 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25549 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25551 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25552 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25553 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25554 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25556 if (AsmPieces.size() == 3)
25558 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25565 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25566 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25568 std::string AsmStr = IA->getAsmString();
25570 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25571 if (!Ty || Ty->getBitWidth() % 16 != 0)
25574 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25575 SmallVector<StringRef, 4> AsmPieces;
25576 SplitString(AsmStr, AsmPieces, ";\n");
25578 switch (AsmPieces.size()) {
25579 default: return false;
25581 // FIXME: this should verify that we are targeting a 486 or better. If not,
25582 // we will turn this bswap into something that will be lowered to logical
25583 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25584 // lower so don't worry about this.
25586 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25587 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25588 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25589 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25590 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25591 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25592 // No need to check constraints, nothing other than the equivalent of
25593 // "=r,0" would be valid here.
25594 return IntrinsicLowering::LowerToByteSwap(CI);
25597 // rorw $$8, ${0:w} --> llvm.bswap.i16
25598 if (CI->getType()->isIntegerTy(16) &&
25599 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25600 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25601 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25603 const std::string &ConstraintsStr = IA->getConstraintString();
25604 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25605 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25606 if (clobbersFlagRegisters(AsmPieces))
25607 return IntrinsicLowering::LowerToByteSwap(CI);
25611 if (CI->getType()->isIntegerTy(32) &&
25612 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25613 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25614 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25615 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25617 const std::string &ConstraintsStr = IA->getConstraintString();
25618 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25619 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25620 if (clobbersFlagRegisters(AsmPieces))
25621 return IntrinsicLowering::LowerToByteSwap(CI);
25624 if (CI->getType()->isIntegerTy(64)) {
25625 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25626 if (Constraints.size() >= 2 &&
25627 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25628 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25629 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25630 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25631 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25632 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25633 return IntrinsicLowering::LowerToByteSwap(CI);
25641 /// getConstraintType - Given a constraint letter, return the type of
25642 /// constraint it is for this target.
25643 X86TargetLowering::ConstraintType
25644 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25645 if (Constraint.size() == 1) {
25646 switch (Constraint[0]) {
25657 return C_RegisterClass;
25681 return TargetLowering::getConstraintType(Constraint);
25684 /// Examine constraint type and operand type and determine a weight value.
25685 /// This object must already have been set up with the operand type
25686 /// and the current alternative constraint selected.
25687 TargetLowering::ConstraintWeight
25688 X86TargetLowering::getSingleConstraintMatchWeight(
25689 AsmOperandInfo &info, const char *constraint) const {
25690 ConstraintWeight weight = CW_Invalid;
25691 Value *CallOperandVal = info.CallOperandVal;
25692 // If we don't have a value, we can't do a match,
25693 // but allow it at the lowest weight.
25694 if (!CallOperandVal)
25696 Type *type = CallOperandVal->getType();
25697 // Look at the constraint type.
25698 switch (*constraint) {
25700 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25711 if (CallOperandVal->getType()->isIntegerTy())
25712 weight = CW_SpecificReg;
25717 if (type->isFloatingPointTy())
25718 weight = CW_SpecificReg;
25721 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25722 weight = CW_SpecificReg;
25726 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25727 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25728 weight = CW_Register;
25731 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25732 if (C->getZExtValue() <= 31)
25733 weight = CW_Constant;
25737 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25738 if (C->getZExtValue() <= 63)
25739 weight = CW_Constant;
25743 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25744 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25745 weight = CW_Constant;
25749 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25750 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25751 weight = CW_Constant;
25755 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25756 if (C->getZExtValue() <= 3)
25757 weight = CW_Constant;
25761 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25762 if (C->getZExtValue() <= 0xff)
25763 weight = CW_Constant;
25768 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25769 weight = CW_Constant;
25773 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25774 if ((C->getSExtValue() >= -0x80000000LL) &&
25775 (C->getSExtValue() <= 0x7fffffffLL))
25776 weight = CW_Constant;
25780 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25781 if (C->getZExtValue() <= 0xffffffff)
25782 weight = CW_Constant;
25789 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25790 /// with another that has more specific requirements based on the type of the
25791 /// corresponding operand.
25792 const char *X86TargetLowering::
25793 LowerXConstraint(EVT ConstraintVT) const {
25794 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25795 // 'f' like normal targets.
25796 if (ConstraintVT.isFloatingPoint()) {
25797 if (Subtarget->hasSSE2())
25799 if (Subtarget->hasSSE1())
25803 return TargetLowering::LowerXConstraint(ConstraintVT);
25806 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25807 /// vector. If it is invalid, don't add anything to Ops.
25808 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25809 std::string &Constraint,
25810 std::vector<SDValue>&Ops,
25811 SelectionDAG &DAG) const {
25814 // Only support length 1 constraints for now.
25815 if (Constraint.length() > 1) return;
25817 char ConstraintLetter = Constraint[0];
25818 switch (ConstraintLetter) {
25821 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25822 if (C->getZExtValue() <= 31) {
25823 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25829 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25830 if (C->getZExtValue() <= 63) {
25831 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25837 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25838 if (isInt<8>(C->getSExtValue())) {
25839 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25845 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25846 if (C->getZExtValue() <= 255) {
25847 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25853 // 32-bit signed value
25854 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25855 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25856 C->getSExtValue())) {
25857 // Widen to 64 bits here to get it sign extended.
25858 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25861 // FIXME gcc accepts some relocatable values here too, but only in certain
25862 // memory models; it's complicated.
25867 // 32-bit unsigned value
25868 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25869 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25870 C->getZExtValue())) {
25871 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25875 // FIXME gcc accepts some relocatable values here too, but only in certain
25876 // memory models; it's complicated.
25880 // Literal immediates are always ok.
25881 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25882 // Widen to 64 bits here to get it sign extended.
25883 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25887 // In any sort of PIC mode addresses need to be computed at runtime by
25888 // adding in a register or some sort of table lookup. These can't
25889 // be used as immediates.
25890 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25893 // If we are in non-pic codegen mode, we allow the address of a global (with
25894 // an optional displacement) to be used with 'i'.
25895 GlobalAddressSDNode *GA = nullptr;
25896 int64_t Offset = 0;
25898 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25900 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25901 Offset += GA->getOffset();
25903 } else if (Op.getOpcode() == ISD::ADD) {
25904 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25905 Offset += C->getZExtValue();
25906 Op = Op.getOperand(0);
25909 } else if (Op.getOpcode() == ISD::SUB) {
25910 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25911 Offset += -C->getZExtValue();
25912 Op = Op.getOperand(0);
25917 // Otherwise, this isn't something we can handle, reject it.
25921 const GlobalValue *GV = GA->getGlobal();
25922 // If we require an extra load to get this address, as in PIC mode, we
25923 // can't accept it.
25924 if (isGlobalStubReference(
25925 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25928 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25929 GA->getValueType(0), Offset);
25934 if (Result.getNode()) {
25935 Ops.push_back(Result);
25938 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25941 std::pair<unsigned, const TargetRegisterClass*>
25942 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25944 // First, see if this is a constraint that directly corresponds to an LLVM
25946 if (Constraint.size() == 1) {
25947 // GCC Constraint Letters
25948 switch (Constraint[0]) {
25950 // TODO: Slight differences here in allocation order and leaving
25951 // RIP in the class. Do they matter any more here than they do
25952 // in the normal allocation?
25953 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25954 if (Subtarget->is64Bit()) {
25955 if (VT == MVT::i32 || VT == MVT::f32)
25956 return std::make_pair(0U, &X86::GR32RegClass);
25957 if (VT == MVT::i16)
25958 return std::make_pair(0U, &X86::GR16RegClass);
25959 if (VT == MVT::i8 || VT == MVT::i1)
25960 return std::make_pair(0U, &X86::GR8RegClass);
25961 if (VT == MVT::i64 || VT == MVT::f64)
25962 return std::make_pair(0U, &X86::GR64RegClass);
25965 // 32-bit fallthrough
25966 case 'Q': // Q_REGS
25967 if (VT == MVT::i32 || VT == MVT::f32)
25968 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25969 if (VT == MVT::i16)
25970 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25971 if (VT == MVT::i8 || VT == MVT::i1)
25972 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25973 if (VT == MVT::i64)
25974 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25976 case 'r': // GENERAL_REGS
25977 case 'l': // INDEX_REGS
25978 if (VT == MVT::i8 || VT == MVT::i1)
25979 return std::make_pair(0U, &X86::GR8RegClass);
25980 if (VT == MVT::i16)
25981 return std::make_pair(0U, &X86::GR16RegClass);
25982 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25983 return std::make_pair(0U, &X86::GR32RegClass);
25984 return std::make_pair(0U, &X86::GR64RegClass);
25985 case 'R': // LEGACY_REGS
25986 if (VT == MVT::i8 || VT == MVT::i1)
25987 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25988 if (VT == MVT::i16)
25989 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25990 if (VT == MVT::i32 || !Subtarget->is64Bit())
25991 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25992 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25993 case 'f': // FP Stack registers.
25994 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25995 // value to the correct fpstack register class.
25996 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25997 return std::make_pair(0U, &X86::RFP32RegClass);
25998 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25999 return std::make_pair(0U, &X86::RFP64RegClass);
26000 return std::make_pair(0U, &X86::RFP80RegClass);
26001 case 'y': // MMX_REGS if MMX allowed.
26002 if (!Subtarget->hasMMX()) break;
26003 return std::make_pair(0U, &X86::VR64RegClass);
26004 case 'Y': // SSE_REGS if SSE2 allowed
26005 if (!Subtarget->hasSSE2()) break;
26007 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26008 if (!Subtarget->hasSSE1()) break;
26010 switch (VT.SimpleTy) {
26012 // Scalar SSE types.
26015 return std::make_pair(0U, &X86::FR32RegClass);
26018 return std::make_pair(0U, &X86::FR64RegClass);
26026 return std::make_pair(0U, &X86::VR128RegClass);
26034 return std::make_pair(0U, &X86::VR256RegClass);
26039 return std::make_pair(0U, &X86::VR512RegClass);
26045 // Use the default implementation in TargetLowering to convert the register
26046 // constraint into a member of a register class.
26047 std::pair<unsigned, const TargetRegisterClass*> Res;
26048 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26050 // Not found as a standard register?
26052 // Map st(0) -> st(7) -> ST0
26053 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26054 tolower(Constraint[1]) == 's' &&
26055 tolower(Constraint[2]) == 't' &&
26056 Constraint[3] == '(' &&
26057 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26058 Constraint[5] == ')' &&
26059 Constraint[6] == '}') {
26061 Res.first = X86::FP0+Constraint[4]-'0';
26062 Res.second = &X86::RFP80RegClass;
26066 // GCC allows "st(0)" to be called just plain "st".
26067 if (StringRef("{st}").equals_lower(Constraint)) {
26068 Res.first = X86::FP0;
26069 Res.second = &X86::RFP80RegClass;
26074 if (StringRef("{flags}").equals_lower(Constraint)) {
26075 Res.first = X86::EFLAGS;
26076 Res.second = &X86::CCRRegClass;
26080 // 'A' means EAX + EDX.
26081 if (Constraint == "A") {
26082 Res.first = X86::EAX;
26083 Res.second = &X86::GR32_ADRegClass;
26089 // Otherwise, check to see if this is a register class of the wrong value
26090 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26091 // turn into {ax},{dx}.
26092 if (Res.second->hasType(VT))
26093 return Res; // Correct type already, nothing to do.
26095 // All of the single-register GCC register classes map their values onto
26096 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26097 // really want an 8-bit or 32-bit register, map to the appropriate register
26098 // class and return the appropriate register.
26099 if (Res.second == &X86::GR16RegClass) {
26100 if (VT == MVT::i8 || VT == MVT::i1) {
26101 unsigned DestReg = 0;
26102 switch (Res.first) {
26104 case X86::AX: DestReg = X86::AL; break;
26105 case X86::DX: DestReg = X86::DL; break;
26106 case X86::CX: DestReg = X86::CL; break;
26107 case X86::BX: DestReg = X86::BL; break;
26110 Res.first = DestReg;
26111 Res.second = &X86::GR8RegClass;
26113 } else if (VT == MVT::i32 || VT == MVT::f32) {
26114 unsigned DestReg = 0;
26115 switch (Res.first) {
26117 case X86::AX: DestReg = X86::EAX; break;
26118 case X86::DX: DestReg = X86::EDX; break;
26119 case X86::CX: DestReg = X86::ECX; break;
26120 case X86::BX: DestReg = X86::EBX; break;
26121 case X86::SI: DestReg = X86::ESI; break;
26122 case X86::DI: DestReg = X86::EDI; break;
26123 case X86::BP: DestReg = X86::EBP; break;
26124 case X86::SP: DestReg = X86::ESP; break;
26127 Res.first = DestReg;
26128 Res.second = &X86::GR32RegClass;
26130 } else if (VT == MVT::i64 || VT == MVT::f64) {
26131 unsigned DestReg = 0;
26132 switch (Res.first) {
26134 case X86::AX: DestReg = X86::RAX; break;
26135 case X86::DX: DestReg = X86::RDX; break;
26136 case X86::CX: DestReg = X86::RCX; break;
26137 case X86::BX: DestReg = X86::RBX; break;
26138 case X86::SI: DestReg = X86::RSI; break;
26139 case X86::DI: DestReg = X86::RDI; break;
26140 case X86::BP: DestReg = X86::RBP; break;
26141 case X86::SP: DestReg = X86::RSP; break;
26144 Res.first = DestReg;
26145 Res.second = &X86::GR64RegClass;
26148 } else if (Res.second == &X86::FR32RegClass ||
26149 Res.second == &X86::FR64RegClass ||
26150 Res.second == &X86::VR128RegClass ||
26151 Res.second == &X86::VR256RegClass ||
26152 Res.second == &X86::FR32XRegClass ||
26153 Res.second == &X86::FR64XRegClass ||
26154 Res.second == &X86::VR128XRegClass ||
26155 Res.second == &X86::VR256XRegClass ||
26156 Res.second == &X86::VR512RegClass) {
26157 // Handle references to XMM physical registers that got mapped into the
26158 // wrong class. This can happen with constraints like {xmm0} where the
26159 // target independent register mapper will just pick the first match it can
26160 // find, ignoring the required type.
26162 if (VT == MVT::f32 || VT == MVT::i32)
26163 Res.second = &X86::FR32RegClass;
26164 else if (VT == MVT::f64 || VT == MVT::i64)
26165 Res.second = &X86::FR64RegClass;
26166 else if (X86::VR128RegClass.hasType(VT))
26167 Res.second = &X86::VR128RegClass;
26168 else if (X86::VR256RegClass.hasType(VT))
26169 Res.second = &X86::VR256RegClass;
26170 else if (X86::VR512RegClass.hasType(VT))
26171 Res.second = &X86::VR512RegClass;
26177 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26179 // Scaling factors are not free at all.
26180 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26181 // will take 2 allocations in the out of order engine instead of 1
26182 // for plain addressing mode, i.e. inst (reg1).
26184 // vaddps (%rsi,%drx), %ymm0, %ymm1
26185 // Requires two allocations (one for the load, one for the computation)
26187 // vaddps (%rsi), %ymm0, %ymm1
26188 // Requires just 1 allocation, i.e., freeing allocations for other operations
26189 // and having less micro operations to execute.
26191 // For some X86 architectures, this is even worse because for instance for
26192 // stores, the complex addressing mode forces the instruction to use the
26193 // "load" ports instead of the dedicated "store" port.
26194 // E.g., on Haswell:
26195 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26196 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26197 if (isLegalAddressingMode(AM, Ty))
26198 // Scale represents reg2 * scale, thus account for 1
26199 // as soon as we use a second register.
26200 return AM.Scale != 0;
26204 bool X86TargetLowering::isTargetFTOL() const {
26205 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();