1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec,
69 EVT VT = Vec.getValueType();
70 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
71 EVT ElVT = VT.getVectorElementType();
72 int Factor = VT.getSizeInBits()/128;
73 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
74 VT.getVectorNumElements()/Factor);
76 // Extract from UNDEF is UNDEF.
77 if (Vec.getOpcode() == ISD::UNDEF)
78 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
80 if (isa<ConstantSDNode>(Idx)) {
81 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
83 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
84 // we can match to VEXTRACTF128.
85 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
87 // This is the index of the first element of the 128-bit chunk
89 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
92 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
93 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
102 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
103 /// sets things up to match to an AVX VINSERTF128 instruction or a
104 /// simple superregister reference. Idx is an index in the 128 bits
105 /// we want. It need not be aligned to a 128-bit bounday. That makes
106 /// lowering INSERT_VECTOR_ELT operations easier.
107 static SDValue Insert128BitVector(SDValue Result,
112 if (isa<ConstantSDNode>(Idx)) {
113 EVT VT = Vec.getValueType();
114 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
116 EVT ElVT = VT.getVectorElementType();
117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
118 EVT ResultVT = Result.getValueType();
120 // Insert the relevant 128 bits.
121 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
123 // This is the index of the first element of the 128-bit chunk
125 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
128 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
129 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X8664_MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetELF())
148 return new TargetLoweringObjectFileELF();
149 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
150 return new TargetLoweringObjectFileCOFF();
151 llvm_unreachable("unknown subtarget type");
154 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
155 : TargetLowering(TM, createTLOF(TM)) {
156 Subtarget = &TM.getSubtarget<X86Subtarget>();
157 X86ScalarSSEf64 = Subtarget->hasSSE2();
158 X86ScalarSSEf32 = Subtarget->hasSSE1();
159 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
161 RegInfo = TM.getRegisterInfo();
162 TD = getTargetData();
164 // Set up the TargetLowering object.
165 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
167 // X86 is weird, it always uses i8 for shift amounts and setcc results.
168 setBooleanContents(ZeroOrOneBooleanContent);
169 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
170 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
172 // For 64-bit since we have so many registers use the ILP scheduler, for
173 // 32-bit code use the register pressure specific scheduling.
174 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
175 if (Subtarget->is64Bit())
176 setSchedulingPreference(Sched::ILP);
177 else if (Subtarget->isAtom())
178 setSchedulingPreference(Sched::Hybrid);
180 setSchedulingPreference(Sched::RegPressure);
181 setStackPointerRegisterToSaveRestore(X86StackPtr);
183 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
184 // Setup Windows compiler runtime calls.
185 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
186 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
187 setLibcallName(RTLIB::SREM_I64, "_allrem");
188 setLibcallName(RTLIB::UREM_I64, "_aullrem");
189 setLibcallName(RTLIB::MUL_I64, "_allmul");
190 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
191 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
192 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
193 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
194 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
196 // The _ftol2 runtime function has an unusual calling conv, which
197 // is modeled by a special pseudo-instruction.
198 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
199 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
200 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
201 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
204 if (Subtarget->isTargetDarwin()) {
205 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
206 setUseUnderscoreSetJmp(false);
207 setUseUnderscoreLongJmp(false);
208 } else if (Subtarget->isTargetMingw()) {
209 // MS runtime is weird: it exports _setjmp, but longjmp!
210 setUseUnderscoreSetJmp(true);
211 setUseUnderscoreLongJmp(false);
213 setUseUnderscoreSetJmp(true);
214 setUseUnderscoreLongJmp(true);
217 // Set up the register classes.
218 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
219 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
220 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
221 if (Subtarget->is64Bit())
222 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
224 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
226 // We don't accept any truncstore of integer registers.
227 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
228 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
229 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
230 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
231 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
232 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
234 // SETOEQ and SETUNE require checking two conditions.
235 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
236 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
237 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
238 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
239 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
242 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
244 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
245 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
248 if (Subtarget->is64Bit()) {
249 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
251 } else if (!TM.Options.UseSoftFloat) {
252 // We have an algorithm for SSE2->double, and we turn this into a
253 // 64-bit FILD followed by conditional FADD for other targets.
254 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
255 // We have an algorithm for SSE2, and we turn this into a 64-bit
256 // FILD for other targets.
257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
260 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
262 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
263 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
265 if (!TM.Options.UseSoftFloat) {
266 // SSE has no i16 to fp conversion, only i32
267 if (X86ScalarSSEf32) {
268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
269 // f32 and f64 cases are Legal, f80 case is not
270 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
280 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
281 // are Legal, f80 is custom lowered.
282 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
285 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
287 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
288 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
290 if (X86ScalarSSEf32) {
291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
292 // f32 and f64 cases are Legal, f80 case is not
293 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
295 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
299 // Handle FP_TO_UINT by promoting the destination to a larger signed
301 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
302 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
305 if (Subtarget->is64Bit()) {
306 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
308 } else if (!TM.Options.UseSoftFloat) {
309 // Since AVX is a superset of SSE3, only check for SSE here.
310 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
311 // Expand FP_TO_UINT into a select.
312 // FIXME: We would like to use a Custom expander here eventually to do
313 // the optimal thing for SSE vs. the default expansion in the legalizer.
314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
316 // With SSE3 we can use fisttpll to convert to a signed i64; without
317 // SSE, we're stuck with a fistpll.
318 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
321 if (isTargetFTOL()) {
322 // Use the _ftol2 runtime function, which has a pseudo-instruction
323 // to handle its weird calling convention.
324 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
327 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
328 if (!X86ScalarSSEf64) {
329 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
330 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
331 if (Subtarget->is64Bit()) {
332 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
333 // Without SSE, i64->f64 goes through memory.
334 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
338 // Scalar integer divide and remainder are lowered to use operations that
339 // produce two results, to match the available instructions. This exposes
340 // the two-result form to trivial CSE, which is able to combine x/y and x%y
341 // into a single instruction.
343 // Scalar integer multiply-high is also lowered to use two-result
344 // operations, to match the available instructions. However, plain multiply
345 // (low) operations are left as Legal, as there are single-result
346 // instructions for this in x86. Using the two-result multiply instructions
347 // when both high and low results are needed must be arranged by dagcombine.
348 for (unsigned i = 0, e = 4; i != e; ++i) {
350 setOperationAction(ISD::MULHS, VT, Expand);
351 setOperationAction(ISD::MULHU, VT, Expand);
352 setOperationAction(ISD::SDIV, VT, Expand);
353 setOperationAction(ISD::UDIV, VT, Expand);
354 setOperationAction(ISD::SREM, VT, Expand);
355 setOperationAction(ISD::UREM, VT, Expand);
357 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
358 setOperationAction(ISD::ADDC, VT, Custom);
359 setOperationAction(ISD::ADDE, VT, Custom);
360 setOperationAction(ISD::SUBC, VT, Custom);
361 setOperationAction(ISD::SUBE, VT, Custom);
364 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
365 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
366 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
367 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
368 if (Subtarget->is64Bit())
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
373 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f32 , Expand);
375 setOperationAction(ISD::FREM , MVT::f64 , Expand);
376 setOperationAction(ISD::FREM , MVT::f80 , Expand);
377 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
379 // Promote the i8 variants and force them on up to i32 which has a shorter
381 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
382 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
384 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
385 if (Subtarget->hasBMI()) {
386 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
388 if (Subtarget->is64Bit())
389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
391 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
392 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
397 if (Subtarget->hasLZCNT()) {
398 // When promoting the i8 variants, force them to i32 for a shorter
400 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
401 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
402 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
403 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
406 if (Subtarget->is64Bit())
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
409 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
410 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
411 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
415 if (Subtarget->is64Bit()) {
416 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
421 if (Subtarget->hasPOPCNT()) {
422 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
424 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
425 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
426 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
427 if (Subtarget->is64Bit())
428 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
431 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
432 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
434 // These should be promoted to a larger select which is supported.
435 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
436 // X86 wants to expand cmov itself.
437 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
438 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
439 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
440 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
441 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
443 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
444 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
446 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
447 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
449 if (Subtarget->is64Bit()) {
450 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
451 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
453 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
456 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
457 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
458 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
459 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
460 if (Subtarget->is64Bit())
461 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
462 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
463 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
464 if (Subtarget->is64Bit()) {
465 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
466 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
467 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
468 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
469 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
471 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
472 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
473 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
474 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
475 if (Subtarget->is64Bit()) {
476 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
477 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
478 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
481 if (Subtarget->hasSSE1())
482 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
484 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
485 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
487 // On X86 and X86-64, atomic operations are lowered to locked instructions.
488 // Locked instructions, in turn, have implicit fence semantics (all memory
489 // operations are flushed before issuing the locked instruction, and they
490 // are not buffered), so we can fold away the common pattern of
491 // fence-atomic-fence.
492 setShouldFoldAtomicFences(true);
494 // Expand certain atomics
495 for (unsigned i = 0, e = 4; i != e; ++i) {
497 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
498 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
499 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
502 if (!Subtarget->is64Bit()) {
503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
513 if (Subtarget->hasCmpxchg16b()) {
514 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
517 // FIXME - use subtarget debug flags
518 if (!Subtarget->isTargetDarwin() &&
519 !Subtarget->isTargetELF() &&
520 !Subtarget->isTargetCygMing()) {
521 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
524 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
525 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
527 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
528 if (Subtarget->is64Bit()) {
529 setExceptionPointerRegister(X86::RAX);
530 setExceptionSelectorRegister(X86::RDX);
532 setExceptionPointerRegister(X86::EAX);
533 setExceptionSelectorRegister(X86::EDX);
535 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
538 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
539 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
541 setOperationAction(ISD::TRAP, MVT::Other, Legal);
543 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
544 setOperationAction(ISD::VASTART , MVT::Other, Custom);
545 setOperationAction(ISD::VAEND , MVT::Other, Expand);
546 if (Subtarget->is64Bit()) {
547 setOperationAction(ISD::VAARG , MVT::Other, Custom);
548 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
550 setOperationAction(ISD::VAARG , MVT::Other, Expand);
551 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
554 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
555 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
557 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
558 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
559 MVT::i64 : MVT::i32, Custom);
560 else if (TM.Options.EnableSegmentedStacks)
561 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
562 MVT::i64 : MVT::i32, Custom);
564 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
565 MVT::i64 : MVT::i32, Expand);
567 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
568 // f32 and f64 use SSE.
569 // Set up the FP register classes.
570 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
571 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
573 // Use ANDPD to simulate FABS.
574 setOperationAction(ISD::FABS , MVT::f64, Custom);
575 setOperationAction(ISD::FABS , MVT::f32, Custom);
577 // Use XORP to simulate FNEG.
578 setOperationAction(ISD::FNEG , MVT::f64, Custom);
579 setOperationAction(ISD::FNEG , MVT::f32, Custom);
581 // Use ANDPD and ORPD to simulate FCOPYSIGN.
582 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
583 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
585 // Lower this to FGETSIGNx86 plus an AND.
586 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
587 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
589 // We don't support sin/cos/fmod
590 setOperationAction(ISD::FSIN , MVT::f64, Expand);
591 setOperationAction(ISD::FCOS , MVT::f64, Expand);
592 setOperationAction(ISD::FSIN , MVT::f32, Expand);
593 setOperationAction(ISD::FCOS , MVT::f32, Expand);
595 // Expand FP immediates into loads from the stack, except for the special
597 addLegalFPImmediate(APFloat(+0.0)); // xorpd
598 addLegalFPImmediate(APFloat(+0.0f)); // xorps
599 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
600 // Use SSE for f32, x87 for f64.
601 // Set up the FP register classes.
602 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
603 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
605 // Use ANDPS to simulate FABS.
606 setOperationAction(ISD::FABS , MVT::f32, Custom);
608 // Use XORP to simulate FNEG.
609 setOperationAction(ISD::FNEG , MVT::f32, Custom);
611 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
613 // Use ANDPS and ORPS to simulate FCOPYSIGN.
614 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
615 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
617 // We don't support sin/cos/fmod
618 setOperationAction(ISD::FSIN , MVT::f32, Expand);
619 setOperationAction(ISD::FCOS , MVT::f32, Expand);
621 // Special cases we handle for FP constants.
622 addLegalFPImmediate(APFloat(+0.0f)); // xorps
623 addLegalFPImmediate(APFloat(+0.0)); // FLD0
624 addLegalFPImmediate(APFloat(+1.0)); // FLD1
625 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
626 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
628 if (!TM.Options.UnsafeFPMath) {
629 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
630 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
632 } else if (!TM.Options.UseSoftFloat) {
633 // f32 and f64 in x87.
634 // Set up the FP register classes.
635 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
636 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
638 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
639 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
640 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
641 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
643 if (!TM.Options.UnsafeFPMath) {
644 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
645 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
647 addLegalFPImmediate(APFloat(+0.0)); // FLD0
648 addLegalFPImmediate(APFloat(+1.0)); // FLD1
649 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
650 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
651 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
652 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
653 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
654 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
657 // We don't support FMA.
658 setOperationAction(ISD::FMA, MVT::f64, Expand);
659 setOperationAction(ISD::FMA, MVT::f32, Expand);
661 // Long double always uses X87.
662 if (!TM.Options.UseSoftFloat) {
663 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
664 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
665 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
667 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
668 addLegalFPImmediate(TmpFlt); // FLD0
670 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
673 APFloat TmpFlt2(+1.0);
674 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
676 addLegalFPImmediate(TmpFlt2); // FLD1
677 TmpFlt2.changeSign();
678 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
681 if (!TM.Options.UnsafeFPMath) {
682 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
683 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
686 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
687 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
688 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
689 setOperationAction(ISD::FRINT, MVT::f80, Expand);
690 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
691 setOperationAction(ISD::FMA, MVT::f80, Expand);
694 // Always use a library call for pow.
695 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
696 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
697 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
699 setOperationAction(ISD::FLOG, MVT::f80, Expand);
700 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
701 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
702 setOperationAction(ISD::FEXP, MVT::f80, Expand);
703 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
705 // First set operation action for all vector types to either promote
706 // (for widening) or expand (for scalarization). Then we will selectively
707 // turn on ones that can be effectively codegen'd.
708 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
709 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
710 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
725 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
727 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
728 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
762 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
767 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
768 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
769 setTruncStoreAction((MVT::SimpleValueType)VT,
770 (MVT::SimpleValueType)InnerVT, Expand);
771 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
773 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
776 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
777 // with -msoft-float, disable use of MMX as well.
778 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
779 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
780 // No operations on x86mmx supported, everything uses intrinsics.
783 // MMX-sized vectors (other than x86mmx) are expected to be expanded
784 // into smaller operations.
785 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
786 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
787 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
788 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
789 setOperationAction(ISD::AND, MVT::v8i8, Expand);
790 setOperationAction(ISD::AND, MVT::v4i16, Expand);
791 setOperationAction(ISD::AND, MVT::v2i32, Expand);
792 setOperationAction(ISD::AND, MVT::v1i64, Expand);
793 setOperationAction(ISD::OR, MVT::v8i8, Expand);
794 setOperationAction(ISD::OR, MVT::v4i16, Expand);
795 setOperationAction(ISD::OR, MVT::v2i32, Expand);
796 setOperationAction(ISD::OR, MVT::v1i64, Expand);
797 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
798 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
799 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
800 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
801 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
805 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
806 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
807 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
808 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
809 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
810 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
811 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
812 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
815 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
816 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
818 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
819 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
820 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
821 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
822 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
823 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
824 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
825 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
826 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
827 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
828 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
829 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
832 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
833 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
835 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
836 // registers cannot be used even for integer operations.
837 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
838 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
839 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
840 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
842 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
843 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
844 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
845 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
846 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
847 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
848 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
849 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
850 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
851 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
852 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
853 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
854 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
855 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
856 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
857 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
859 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
860 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
861 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
862 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
864 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
866 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
876 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
877 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
878 EVT VT = (MVT::SimpleValueType)i;
879 // Do not attempt to custom lower non-power-of-2 vectors
880 if (!isPowerOf2_32(VT.getVectorNumElements()))
882 // Do not attempt to custom lower non-128-bit vectors
883 if (!VT.is128BitVector())
885 setOperationAction(ISD::BUILD_VECTOR,
886 VT.getSimpleVT().SimpleTy, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE,
888 VT.getSimpleVT().SimpleTy, Custom);
889 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
890 VT.getSimpleVT().SimpleTy, Custom);
893 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
900 if (Subtarget->is64Bit()) {
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
902 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
905 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
906 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
907 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
910 // Do not attempt to promote non-128-bit vectors
911 if (!VT.is128BitVector())
914 setOperationAction(ISD::AND, SVT, Promote);
915 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
916 setOperationAction(ISD::OR, SVT, Promote);
917 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
918 setOperationAction(ISD::XOR, SVT, Promote);
919 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
920 setOperationAction(ISD::LOAD, SVT, Promote);
921 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
922 setOperationAction(ISD::SELECT, SVT, Promote);
923 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
926 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
938 if (Subtarget->hasSSE41()) {
939 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
940 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
941 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
942 setOperationAction(ISD::FRINT, MVT::f32, Legal);
943 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
944 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
945 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
946 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
947 setOperationAction(ISD::FRINT, MVT::f64, Legal);
948 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
950 // FIXME: Do we need to handle scalar-to-vector here?
951 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
954 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
955 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
957 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
959 // i8 and i16 vectors are custom , because the source register and source
960 // source memory operand types are not the same width. f32 vectors are
961 // custom since the immediate controlling the insert encodes additional
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
968 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
973 // FIXME: these should be Legal but thats only for the case where
974 // the index is constant. For now custom expand to deal with that.
975 if (Subtarget->is64Bit()) {
976 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
977 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
981 if (Subtarget->hasSSE2()) {
982 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
983 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
985 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
986 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
988 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
989 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
991 if (Subtarget->hasAVX2()) {
992 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
993 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
995 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
996 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
998 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1000 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1001 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1003 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1004 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1006 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1010 if (Subtarget->hasSSE42())
1011 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1013 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1014 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1015 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1016 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1017 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1018 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1019 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1021 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1022 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1023 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1025 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1027 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1028 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1032 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1034 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1035 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1037 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1039 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1040 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1041 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1051 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1053 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1054 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1056 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1059 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1060 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1061 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1062 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1064 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1065 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1066 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1068 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1069 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1070 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1071 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1073 if (Subtarget->hasAVX2()) {
1074 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1075 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1076 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1077 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1079 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1080 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1081 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1082 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1084 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1085 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1086 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1087 // Don't lower v32i8 because there is no 128-bit byte mul
1089 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1091 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1092 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1094 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1095 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1099 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1100 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1101 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1102 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1104 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1105 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1106 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1109 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1110 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1111 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1112 // Don't lower v32i8 because there is no 128-bit byte mul
1114 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1115 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1117 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1118 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1120 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1123 // Custom lower several nodes for 256-bit types.
1124 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1125 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1126 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1129 // Extract subvector is special because the value type
1130 // (result) is 128-bit but the source is 256-bit wide.
1131 if (VT.is128BitVector())
1132 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1134 // Do not attempt to custom lower other non-256-bit vectors
1135 if (!VT.is256BitVector())
1138 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1139 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1140 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1142 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1143 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1146 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1147 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1148 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1151 // Do not attempt to promote non-256-bit vectors
1152 if (!VT.is256BitVector())
1155 setOperationAction(ISD::AND, SVT, Promote);
1156 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1157 setOperationAction(ISD::OR, SVT, Promote);
1158 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1159 setOperationAction(ISD::XOR, SVT, Promote);
1160 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1161 setOperationAction(ISD::LOAD, SVT, Promote);
1162 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1163 setOperationAction(ISD::SELECT, SVT, Promote);
1164 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1168 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1169 // of this type with custom code.
1170 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1171 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1172 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1176 // We want to custom lower some of our intrinsics.
1177 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1180 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1181 // handle type legalization for these operations here.
1183 // FIXME: We really should do custom legalization for addition and
1184 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1185 // than generic legalization for 64-bit multiplication-with-overflow, though.
1186 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1187 // Add/Sub/Mul with overflow operations are custom lowered.
1189 setOperationAction(ISD::SADDO, VT, Custom);
1190 setOperationAction(ISD::UADDO, VT, Custom);
1191 setOperationAction(ISD::SSUBO, VT, Custom);
1192 setOperationAction(ISD::USUBO, VT, Custom);
1193 setOperationAction(ISD::SMULO, VT, Custom);
1194 setOperationAction(ISD::UMULO, VT, Custom);
1197 // There are no 8-bit 3-address imul/mul instructions
1198 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1199 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1201 if (!Subtarget->is64Bit()) {
1202 // These libcalls are not available in 32-bit.
1203 setLibcallName(RTLIB::SHL_I128, 0);
1204 setLibcallName(RTLIB::SRL_I128, 0);
1205 setLibcallName(RTLIB::SRA_I128, 0);
1208 // We have target-specific dag combine patterns for the following nodes:
1209 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1210 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1211 setTargetDAGCombine(ISD::VSELECT);
1212 setTargetDAGCombine(ISD::SELECT);
1213 setTargetDAGCombine(ISD::SHL);
1214 setTargetDAGCombine(ISD::SRA);
1215 setTargetDAGCombine(ISD::SRL);
1216 setTargetDAGCombine(ISD::OR);
1217 setTargetDAGCombine(ISD::AND);
1218 setTargetDAGCombine(ISD::ADD);
1219 setTargetDAGCombine(ISD::FADD);
1220 setTargetDAGCombine(ISD::FSUB);
1221 setTargetDAGCombine(ISD::SUB);
1222 setTargetDAGCombine(ISD::LOAD);
1223 setTargetDAGCombine(ISD::STORE);
1224 setTargetDAGCombine(ISD::ZERO_EXTEND);
1225 setTargetDAGCombine(ISD::SIGN_EXTEND);
1226 setTargetDAGCombine(ISD::TRUNCATE);
1227 setTargetDAGCombine(ISD::SINT_TO_FP);
1228 if (Subtarget->is64Bit())
1229 setTargetDAGCombine(ISD::MUL);
1230 if (Subtarget->hasBMI())
1231 setTargetDAGCombine(ISD::XOR);
1233 computeRegisterProperties();
1235 // On Darwin, -Os means optimize for size without hurting performance,
1236 // do not reduce the limit.
1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1243 setPrefLoopAlignment(4); // 2^4 bytes.
1244 benefitFromCodePlacementOpt = true;
1246 setPrefFunctionAlignment(4); // 2^4 bytes.
1250 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1251 if (!VT.isVector()) return MVT::i8;
1252 return VT.changeVectorElementTypeToInteger();
1256 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1257 /// the desired ByVal argument alignment.
1258 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1262 if (VTy->getBitWidth() == 128)
1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1265 unsigned EltAlign = 0;
1266 getMaxByValAlign(ATy->getElementType(), EltAlign);
1267 if (EltAlign > MaxAlign)
1268 MaxAlign = EltAlign;
1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1271 unsigned EltAlign = 0;
1272 getMaxByValAlign(STy->getElementType(i), EltAlign);
1273 if (EltAlign > MaxAlign)
1274 MaxAlign = EltAlign;
1282 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1283 /// function arguments in the caller parameter area. For X86, aggregates
1284 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1285 /// are at 4-byte boundaries.
1286 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1287 if (Subtarget->is64Bit()) {
1288 // Max of 8 and alignment of type.
1289 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1296 if (Subtarget->hasSSE1())
1297 getMaxByValAlign(Ty, Align);
1301 /// getOptimalMemOpType - Returns the target specific optimal type for load
1302 /// and store operations as a result of memset, memcpy, and memmove
1303 /// lowering. If DstAlign is zero that means it's safe to destination
1304 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1305 /// means there isn't a need to check it against alignment requirement,
1306 /// probably because the source does not need to be loaded. If
1307 /// 'IsZeroVal' is true, that means it's safe to return a
1308 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1309 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1310 /// constant so it does not need to be loaded.
1311 /// It returns EVT::Other if the type should be determined using generic
1312 /// target-independent logic.
1314 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1315 unsigned DstAlign, unsigned SrcAlign,
1318 MachineFunction &MF) const {
1319 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1320 // linux. This is because the stack realignment code can't handle certain
1321 // cases like PR2962. This should be removed when PR2962 is fixed.
1322 const Function *F = MF.getFunction();
1324 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1326 (Subtarget->isUnalignedMemAccessFast() ||
1327 ((DstAlign == 0 || DstAlign >= 16) &&
1328 (SrcAlign == 0 || SrcAlign >= 16))) &&
1329 Subtarget->getStackAlignment() >= 16) {
1330 if (Subtarget->getStackAlignment() >= 32) {
1331 if (Subtarget->hasAVX2())
1333 if (Subtarget->hasAVX())
1336 if (Subtarget->hasSSE2())
1338 if (Subtarget->hasSSE1())
1340 } else if (!MemcpyStrSrc && Size >= 8 &&
1341 !Subtarget->is64Bit() &&
1342 Subtarget->getStackAlignment() >= 8 &&
1343 Subtarget->hasSSE2()) {
1344 // Do not use f64 to lower memcpy if source is string constant. It's
1345 // better to use i32 to avoid the loads.
1349 if (Subtarget->is64Bit() && Size >= 8)
1354 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1355 /// current function. The returned value is a member of the
1356 /// MachineJumpTableInfo::JTEntryKind enum.
1357 unsigned X86TargetLowering::getJumpTableEncoding() const {
1358 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1360 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1361 Subtarget->isPICStyleGOT())
1362 return MachineJumpTableInfo::EK_Custom32;
1364 // Otherwise, use the normal jump table encoding heuristics.
1365 return TargetLowering::getJumpTableEncoding();
1369 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1370 const MachineBasicBlock *MBB,
1371 unsigned uid,MCContext &Ctx) const{
1372 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1373 Subtarget->isPICStyleGOT());
1374 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1376 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1377 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1380 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1382 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1383 SelectionDAG &DAG) const {
1384 if (!Subtarget->is64Bit())
1385 // This doesn't have DebugLoc associated with it, but is not really the
1386 // same as a Register.
1387 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1391 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1392 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1394 const MCExpr *X86TargetLowering::
1395 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1396 MCContext &Ctx) const {
1397 // X86-64 uses RIP relative addressing based on the jump table label.
1398 if (Subtarget->isPICStyleRIPRel())
1399 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1401 // Otherwise, the reference is relative to the PIC base.
1402 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1405 // FIXME: Why this routine is here? Move to RegInfo!
1406 std::pair<const TargetRegisterClass*, uint8_t>
1407 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1408 const TargetRegisterClass *RRC = 0;
1410 switch (VT.getSimpleVT().SimpleTy) {
1412 return TargetLowering::findRepresentativeClass(VT);
1413 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1414 RRC = (Subtarget->is64Bit()
1415 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1418 RRC = X86::VR64RegisterClass;
1420 case MVT::f32: case MVT::f64:
1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1422 case MVT::v4f32: case MVT::v2f64:
1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1425 RRC = X86::VR128RegisterClass;
1428 return std::make_pair(RRC, Cost);
1431 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1432 unsigned &Offset) const {
1433 if (!Subtarget->isTargetLinux())
1436 if (Subtarget->is64Bit()) {
1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1452 //===----------------------------------------------------------------------===//
1453 // Return Value Calling Convention Implementation
1454 //===----------------------------------------------------------------------===//
1456 #include "X86GenCallingConv.inc"
1459 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1460 MachineFunction &MF, bool isVarArg,
1461 const SmallVectorImpl<ISD::OutputArg> &Outs,
1462 LLVMContext &Context) const {
1463 SmallVector<CCValAssign, 16> RVLocs;
1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1466 return CCInfo.CheckReturn(Outs, RetCC_X86);
1470 X86TargetLowering::LowerReturn(SDValue Chain,
1471 CallingConv::ID CallConv, bool isVarArg,
1472 const SmallVectorImpl<ISD::OutputArg> &Outs,
1473 const SmallVectorImpl<SDValue> &OutVals,
1474 DebugLoc dl, SelectionDAG &DAG) const {
1475 MachineFunction &MF = DAG.getMachineFunction();
1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1478 SmallVector<CCValAssign, 16> RVLocs;
1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1480 RVLocs, *DAG.getContext());
1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1483 // Add the regs to the liveout set for the function.
1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1485 for (unsigned i = 0; i != RVLocs.size(); ++i)
1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1487 MRI.addLiveOut(RVLocs[i].getLocReg());
1491 SmallVector<SDValue, 6> RetOps;
1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1493 // Operand #1 = Bytes To Pop
1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1497 // Copy the result values into the output registers.
1498 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1499 CCValAssign &VA = RVLocs[i];
1500 assert(VA.isRegLoc() && "Can only return in registers!");
1501 SDValue ValToCopy = OutVals[i];
1502 EVT ValVT = ValToCopy.getValueType();
1504 // If this is x86-64, and we disabled SSE, we can't return FP values,
1505 // or SSE or MMX vectors.
1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1509 report_fatal_error("SSE register return with SSE disabled");
1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1512 // llvm-gcc has never done it right and no one has noticed, so this
1513 // should be OK for now.
1514 if (ValVT == MVT::f64 &&
1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1516 report_fatal_error("SSE2 register return with SSE2 disabled");
1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1519 // the RET instruction and handled by the FP Stackifier.
1520 if (VA.getLocReg() == X86::ST0 ||
1521 VA.getLocReg() == X86::ST1) {
1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1523 // change the value to the FP stack register class.
1524 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1526 RetOps.push_back(ValToCopy);
1527 // Don't emit a copytoreg.
1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1532 // which is returned in RAX / RDX.
1533 if (Subtarget->is64Bit()) {
1534 if (ValVT == MVT::x86mmx) {
1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1539 // If we don't have SSE2 available, convert to v4f32 so the generated
1540 // register is legal.
1541 if (!Subtarget->hasSSE2())
1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1548 Flag = Chain.getValue(1);
1551 // The x86-64 ABI for returning structs by value requires that we copy
1552 // the sret argument into %rax for the return. We saved the argument into
1553 // a virtual register in the entry block, so now we copy the value out
1555 if (Subtarget->is64Bit() &&
1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1557 MachineFunction &MF = DAG.getMachineFunction();
1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1559 unsigned Reg = FuncInfo->getSRetReturnReg();
1561 "SRetReturnReg should have been set in LowerFormalArguments().");
1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1565 Flag = Chain.getValue(1);
1567 // RAX now acts like a return value.
1568 MRI.addLiveOut(X86::RAX);
1571 RetOps[0] = Chain; // Update chain.
1573 // Add the flag if we have it.
1575 RetOps.push_back(Flag);
1577 return DAG.getNode(X86ISD::RET_FLAG, dl,
1578 MVT::Other, &RetOps[0], RetOps.size());
1581 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1582 if (N->getNumValues() != 1)
1584 if (!N->hasNUsesOfValue(1, 0))
1587 SDNode *Copy = *N->use_begin();
1588 if (Copy->getOpcode() == ISD::CopyToReg) {
1589 // If the copy has a glue operand, we conservatively assume it isn't safe to
1590 // perform a tail call.
1591 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1593 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1596 bool HasRet = false;
1597 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1599 if (UI->getOpcode() != X86ISD::RET_FLAG)
1608 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1609 ISD::NodeType ExtendKind) const {
1611 // TODO: Is this also valid on 32-bit?
1612 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1613 ReturnMVT = MVT::i8;
1615 ReturnMVT = MVT::i32;
1617 EVT MinVT = getRegisterType(Context, ReturnMVT);
1618 return VT.bitsLT(MinVT) ? MinVT : VT;
1621 /// LowerCallResult - Lower the result values of a call into the
1622 /// appropriate copies out of appropriate physical registers.
1625 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1626 CallingConv::ID CallConv, bool isVarArg,
1627 const SmallVectorImpl<ISD::InputArg> &Ins,
1628 DebugLoc dl, SelectionDAG &DAG,
1629 SmallVectorImpl<SDValue> &InVals) const {
1631 // Assign locations to each value returned by this call.
1632 SmallVector<CCValAssign, 16> RVLocs;
1633 bool Is64Bit = Subtarget->is64Bit();
1634 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1635 getTargetMachine(), RVLocs, *DAG.getContext());
1636 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1638 // Copy all of the result registers out of their specified physreg.
1639 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1640 CCValAssign &VA = RVLocs[i];
1641 EVT CopyVT = VA.getValVT();
1643 // If this is x86-64, and we disabled SSE, we can't return FP values
1644 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1645 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1646 report_fatal_error("SSE register return with SSE disabled");
1651 // If this is a call to a function that returns an fp value on the floating
1652 // point stack, we must guarantee the the value is popped from the stack, so
1653 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1654 // if the return value is not used. We use the FpPOP_RETVAL instruction
1656 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1657 // If we prefer to use the value in xmm registers, copy it out as f80 and
1658 // use a truncate to move it from fp stack reg to xmm reg.
1659 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1660 SDValue Ops[] = { Chain, InFlag };
1661 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1662 MVT::Other, MVT::Glue, Ops, 2), 1);
1663 Val = Chain.getValue(0);
1665 // Round the f80 to the right size, which also moves it to the appropriate
1667 if (CopyVT != VA.getValVT())
1668 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1669 // This truncation won't change the value.
1670 DAG.getIntPtrConstant(1));
1672 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1673 CopyVT, InFlag).getValue(1);
1674 Val = Chain.getValue(0);
1676 InFlag = Chain.getValue(2);
1677 InVals.push_back(Val);
1684 //===----------------------------------------------------------------------===//
1685 // C & StdCall & Fast Calling Convention implementation
1686 //===----------------------------------------------------------------------===//
1687 // StdCall calling convention seems to be standard for many Windows' API
1688 // routines and around. It differs from C calling convention just a little:
1689 // callee should clean up the stack, not caller. Symbols should be also
1690 // decorated in some fancy way :) It doesn't support any vector arguments.
1691 // For info on fast calling convention see Fast Calling Convention (tail call)
1692 // implementation LowerX86_32FastCCCallTo.
1694 /// CallIsStructReturn - Determines whether a call uses struct return
1696 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1700 return Outs[0].Flags.isSRet();
1703 /// ArgsAreStructReturn - Determines whether a function uses struct
1704 /// return semantics.
1706 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1710 return Ins[0].Flags.isSRet();
1713 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1714 /// by "Src" to address "Dst" with size and alignment information specified by
1715 /// the specific parameter attribute. The copy will be passed as a byval
1716 /// function parameter.
1718 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1719 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1721 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1723 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1724 /*isVolatile*/false, /*AlwaysInline=*/true,
1725 MachinePointerInfo(), MachinePointerInfo());
1728 /// IsTailCallConvention - Return true if the calling convention is one that
1729 /// supports tail call optimization.
1730 static bool IsTailCallConvention(CallingConv::ID CC) {
1731 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1734 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1735 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1739 CallingConv::ID CalleeCC = CS.getCallingConv();
1740 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1746 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1747 /// a tailcall target by changing its ABI.
1748 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1749 bool GuaranteedTailCallOpt) {
1750 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1754 X86TargetLowering::LowerMemArgument(SDValue Chain,
1755 CallingConv::ID CallConv,
1756 const SmallVectorImpl<ISD::InputArg> &Ins,
1757 DebugLoc dl, SelectionDAG &DAG,
1758 const CCValAssign &VA,
1759 MachineFrameInfo *MFI,
1761 // Create the nodes corresponding to a load from this parameter slot.
1762 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1763 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1764 getTargetMachine().Options.GuaranteedTailCallOpt);
1765 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1768 // If value is passed by pointer we have address passed instead of the value
1770 if (VA.getLocInfo() == CCValAssign::Indirect)
1771 ValVT = VA.getLocVT();
1773 ValVT = VA.getValVT();
1775 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1776 // changed with more analysis.
1777 // In case of tail call optimization mark all arguments mutable. Since they
1778 // could be overwritten by lowering of arguments in case of a tail call.
1779 if (Flags.isByVal()) {
1780 unsigned Bytes = Flags.getByValSize();
1781 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1782 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1783 return DAG.getFrameIndex(FI, getPointerTy());
1785 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1786 VA.getLocMemOffset(), isImmutable);
1787 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1788 return DAG.getLoad(ValVT, dl, Chain, FIN,
1789 MachinePointerInfo::getFixedStack(FI),
1790 false, false, false, 0);
1795 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1796 CallingConv::ID CallConv,
1798 const SmallVectorImpl<ISD::InputArg> &Ins,
1801 SmallVectorImpl<SDValue> &InVals)
1803 MachineFunction &MF = DAG.getMachineFunction();
1804 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1806 const Function* Fn = MF.getFunction();
1807 if (Fn->hasExternalLinkage() &&
1808 Subtarget->isTargetCygMing() &&
1809 Fn->getName() == "main")
1810 FuncInfo->setForceFramePointer(true);
1812 MachineFrameInfo *MFI = MF.getFrameInfo();
1813 bool Is64Bit = Subtarget->is64Bit();
1814 bool IsWindows = Subtarget->isTargetWindows();
1815 bool IsWin64 = Subtarget->isTargetWin64();
1817 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1818 "Var args not supported with calling convention fastcc or ghc");
1820 // Assign locations to all of the incoming arguments.
1821 SmallVector<CCValAssign, 16> ArgLocs;
1822 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1823 ArgLocs, *DAG.getContext());
1825 // Allocate shadow area for Win64
1827 CCInfo.AllocateStack(32, 8);
1830 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1832 unsigned LastVal = ~0U;
1834 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1835 CCValAssign &VA = ArgLocs[i];
1836 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1838 assert(VA.getValNo() != LastVal &&
1839 "Don't support value assigned to multiple locs yet");
1841 LastVal = VA.getValNo();
1843 if (VA.isRegLoc()) {
1844 EVT RegVT = VA.getLocVT();
1845 const TargetRegisterClass *RC;
1846 if (RegVT == MVT::i32)
1847 RC = X86::GR32RegisterClass;
1848 else if (Is64Bit && RegVT == MVT::i64)
1849 RC = X86::GR64RegisterClass;
1850 else if (RegVT == MVT::f32)
1851 RC = X86::FR32RegisterClass;
1852 else if (RegVT == MVT::f64)
1853 RC = X86::FR64RegisterClass;
1854 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1855 RC = X86::VR256RegisterClass;
1856 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1857 RC = X86::VR128RegisterClass;
1858 else if (RegVT == MVT::x86mmx)
1859 RC = X86::VR64RegisterClass;
1861 llvm_unreachable("Unknown argument type!");
1863 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1864 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1866 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1867 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1869 if (VA.getLocInfo() == CCValAssign::SExt)
1870 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1871 DAG.getValueType(VA.getValVT()));
1872 else if (VA.getLocInfo() == CCValAssign::ZExt)
1873 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1874 DAG.getValueType(VA.getValVT()));
1875 else if (VA.getLocInfo() == CCValAssign::BCvt)
1876 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1878 if (VA.isExtInLoc()) {
1879 // Handle MMX values passed in XMM regs.
1880 if (RegVT.isVector()) {
1881 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1884 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1887 assert(VA.isMemLoc());
1888 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1891 // If value is passed via pointer - do a load.
1892 if (VA.getLocInfo() == CCValAssign::Indirect)
1893 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1894 MachinePointerInfo(), false, false, false, 0);
1896 InVals.push_back(ArgValue);
1899 // The x86-64 ABI for returning structs by value requires that we copy
1900 // the sret argument into %rax for the return. Save the argument into
1901 // a virtual register so that we can access it from the return points.
1902 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1903 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1904 unsigned Reg = FuncInfo->getSRetReturnReg();
1906 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1907 FuncInfo->setSRetReturnReg(Reg);
1909 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1910 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1913 unsigned StackSize = CCInfo.getNextStackOffset();
1914 // Align stack specially for tail calls.
1915 if (FuncIsMadeTailCallSafe(CallConv,
1916 MF.getTarget().Options.GuaranteedTailCallOpt))
1917 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1919 // If the function takes variable number of arguments, make a frame index for
1920 // the start of the first vararg value... for expansion of llvm.va_start.
1922 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1923 CallConv != CallingConv::X86_ThisCall)) {
1924 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1927 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1929 // FIXME: We should really autogenerate these arrays
1930 static const uint16_t GPR64ArgRegsWin64[] = {
1931 X86::RCX, X86::RDX, X86::R8, X86::R9
1933 static const uint16_t GPR64ArgRegs64Bit[] = {
1934 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1936 static const uint16_t XMMArgRegs64Bit[] = {
1937 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1938 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1940 const uint16_t *GPR64ArgRegs;
1941 unsigned NumXMMRegs = 0;
1944 // The XMM registers which might contain var arg parameters are shadowed
1945 // in their paired GPR. So we only need to save the GPR to their home
1947 TotalNumIntRegs = 4;
1948 GPR64ArgRegs = GPR64ArgRegsWin64;
1950 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1951 GPR64ArgRegs = GPR64ArgRegs64Bit;
1953 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1956 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1959 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1960 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1961 "SSE register cannot be used when SSE is disabled!");
1962 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1963 NoImplicitFloatOps) &&
1964 "SSE register cannot be used when SSE is disabled!");
1965 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1966 !Subtarget->hasSSE1())
1967 // Kernel mode asks for SSE to be disabled, so don't push them
1969 TotalNumXMMRegs = 0;
1972 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1973 // Get to the caller-allocated home save location. Add 8 to account
1974 // for the return address.
1975 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1976 FuncInfo->setRegSaveFrameIndex(
1977 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1978 // Fixup to set vararg frame on shadow area (4 x i64).
1980 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1982 // For X86-64, if there are vararg parameters that are passed via
1983 // registers, then we must store them to their spots on the stack so
1984 // they may be loaded by deferencing the result of va_next.
1985 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1986 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1987 FuncInfo->setRegSaveFrameIndex(
1988 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1992 // Store the integer parameter registers.
1993 SmallVector<SDValue, 8> MemOps;
1994 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1996 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1997 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1998 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1999 DAG.getIntPtrConstant(Offset));
2000 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2001 X86::GR64RegisterClass);
2002 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2004 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2005 MachinePointerInfo::getFixedStack(
2006 FuncInfo->getRegSaveFrameIndex(), Offset),
2008 MemOps.push_back(Store);
2012 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2013 // Now store the XMM (fp + vector) parameter registers.
2014 SmallVector<SDValue, 11> SaveXMMOps;
2015 SaveXMMOps.push_back(Chain);
2017 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
2018 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2019 SaveXMMOps.push_back(ALVal);
2021 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2022 FuncInfo->getRegSaveFrameIndex()));
2023 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2024 FuncInfo->getVarArgsFPOffset()));
2026 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2027 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2028 X86::VR128RegisterClass);
2029 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2030 SaveXMMOps.push_back(Val);
2032 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2034 &SaveXMMOps[0], SaveXMMOps.size()));
2037 if (!MemOps.empty())
2038 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2039 &MemOps[0], MemOps.size());
2043 // Some CCs need callee pop.
2044 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2045 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2046 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2048 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2049 // If this is an sret function, the return should pop the hidden pointer.
2050 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2051 ArgsAreStructReturn(Ins))
2052 FuncInfo->setBytesToPopOnReturn(4);
2056 // RegSaveFrameIndex is X86-64 only.
2057 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2058 if (CallConv == CallingConv::X86_FastCall ||
2059 CallConv == CallingConv::X86_ThisCall)
2060 // fastcc functions can't have varargs.
2061 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2064 FuncInfo->setArgumentStackSize(StackSize);
2070 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2071 SDValue StackPtr, SDValue Arg,
2072 DebugLoc dl, SelectionDAG &DAG,
2073 const CCValAssign &VA,
2074 ISD::ArgFlagsTy Flags) const {
2075 unsigned LocMemOffset = VA.getLocMemOffset();
2076 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2077 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2078 if (Flags.isByVal())
2079 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2081 return DAG.getStore(Chain, dl, Arg, PtrOff,
2082 MachinePointerInfo::getStack(LocMemOffset),
2086 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2087 /// optimization is performed and it is required.
2089 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2090 SDValue &OutRetAddr, SDValue Chain,
2091 bool IsTailCall, bool Is64Bit,
2092 int FPDiff, DebugLoc dl) const {
2093 // Adjust the Return address stack slot.
2094 EVT VT = getPointerTy();
2095 OutRetAddr = getReturnAddressFrameIndex(DAG);
2097 // Load the "old" Return address.
2098 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2099 false, false, false, 0);
2100 return SDValue(OutRetAddr.getNode(), 1);
2103 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2104 /// optimization is performed and it is required (FPDiff!=0).
2106 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2107 SDValue Chain, SDValue RetAddrFrIdx,
2108 bool Is64Bit, int FPDiff, DebugLoc dl) {
2109 // Store the return address to the appropriate stack slot.
2110 if (!FPDiff) return Chain;
2111 // Calculate the new stack slot for the return address.
2112 int SlotSize = Is64Bit ? 8 : 4;
2113 int NewReturnAddrFI =
2114 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2115 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2116 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2117 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2118 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2124 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2125 CallingConv::ID CallConv, bool isVarArg,
2126 bool doesNotRet, bool &isTailCall,
2127 const SmallVectorImpl<ISD::OutputArg> &Outs,
2128 const SmallVectorImpl<SDValue> &OutVals,
2129 const SmallVectorImpl<ISD::InputArg> &Ins,
2130 DebugLoc dl, SelectionDAG &DAG,
2131 SmallVectorImpl<SDValue> &InVals) const {
2132 MachineFunction &MF = DAG.getMachineFunction();
2133 bool Is64Bit = Subtarget->is64Bit();
2134 bool IsWin64 = Subtarget->isTargetWin64();
2135 bool IsWindows = Subtarget->isTargetWindows();
2136 bool IsStructRet = CallIsStructReturn(Outs);
2137 bool IsSibcall = false;
2139 if (MF.getTarget().Options.DisableTailCalls)
2143 // Check if it's really possible to do a tail call.
2144 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2145 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2146 Outs, OutVals, Ins, DAG);
2148 // Sibcalls are automatically detected tailcalls which do not require
2150 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2157 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2158 "Var args not supported with calling convention fastcc or ghc");
2160 // Analyze operands of the call, assigning locations to each operand.
2161 SmallVector<CCValAssign, 16> ArgLocs;
2162 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2163 ArgLocs, *DAG.getContext());
2165 // Allocate shadow area for Win64
2167 CCInfo.AllocateStack(32, 8);
2170 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2172 // Get a count of how many bytes are to be pushed on the stack.
2173 unsigned NumBytes = CCInfo.getNextStackOffset();
2175 // This is a sibcall. The memory operands are available in caller's
2176 // own caller's stack.
2178 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2179 IsTailCallConvention(CallConv))
2180 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2183 if (isTailCall && !IsSibcall) {
2184 // Lower arguments at fp - stackoffset + fpdiff.
2185 unsigned NumBytesCallerPushed =
2186 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2187 FPDiff = NumBytesCallerPushed - NumBytes;
2189 // Set the delta of movement of the returnaddr stackslot.
2190 // But only set if delta is greater than previous delta.
2191 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2192 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2196 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2198 SDValue RetAddrFrIdx;
2199 // Load return address for tail calls.
2200 if (isTailCall && FPDiff)
2201 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2202 Is64Bit, FPDiff, dl);
2204 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2205 SmallVector<SDValue, 8> MemOpChains;
2208 // Walk the register/memloc assignments, inserting copies/loads. In the case
2209 // of tail call optimization arguments are handle later.
2210 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2211 CCValAssign &VA = ArgLocs[i];
2212 EVT RegVT = VA.getLocVT();
2213 SDValue Arg = OutVals[i];
2214 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2215 bool isByVal = Flags.isByVal();
2217 // Promote the value if needed.
2218 switch (VA.getLocInfo()) {
2219 default: llvm_unreachable("Unknown loc info!");
2220 case CCValAssign::Full: break;
2221 case CCValAssign::SExt:
2222 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2224 case CCValAssign::ZExt:
2225 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2227 case CCValAssign::AExt:
2228 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2229 // Special case: passing MMX values in XMM registers.
2230 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2231 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2232 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2234 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2236 case CCValAssign::BCvt:
2237 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2239 case CCValAssign::Indirect: {
2240 // Store the argument.
2241 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2242 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2243 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2244 MachinePointerInfo::getFixedStack(FI),
2251 if (VA.isRegLoc()) {
2252 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2253 if (isVarArg && IsWin64) {
2254 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2255 // shadow reg if callee is a varargs function.
2256 unsigned ShadowReg = 0;
2257 switch (VA.getLocReg()) {
2258 case X86::XMM0: ShadowReg = X86::RCX; break;
2259 case X86::XMM1: ShadowReg = X86::RDX; break;
2260 case X86::XMM2: ShadowReg = X86::R8; break;
2261 case X86::XMM3: ShadowReg = X86::R9; break;
2264 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2266 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2267 assert(VA.isMemLoc());
2268 if (StackPtr.getNode() == 0)
2269 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2270 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2271 dl, DAG, VA, Flags));
2275 if (!MemOpChains.empty())
2276 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2277 &MemOpChains[0], MemOpChains.size());
2279 // Build a sequence of copy-to-reg nodes chained together with token chain
2280 // and flag operands which copy the outgoing args into registers.
2282 // Tail call byval lowering might overwrite argument registers so in case of
2283 // tail call optimization the copies to registers are lowered later.
2285 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2286 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2287 RegsToPass[i].second, InFlag);
2288 InFlag = Chain.getValue(1);
2291 if (Subtarget->isPICStyleGOT()) {
2292 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2295 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2296 DAG.getNode(X86ISD::GlobalBaseReg,
2297 DebugLoc(), getPointerTy()),
2299 InFlag = Chain.getValue(1);
2301 // If we are tail calling and generating PIC/GOT style code load the
2302 // address of the callee into ECX. The value in ecx is used as target of
2303 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2304 // for tail calls on PIC/GOT architectures. Normally we would just put the
2305 // address of GOT into ebx and then call target@PLT. But for tail calls
2306 // ebx would be restored (since ebx is callee saved) before jumping to the
2309 // Note: The actual moving to ECX is done further down.
2310 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2311 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2312 !G->getGlobal()->hasProtectedVisibility())
2313 Callee = LowerGlobalAddress(Callee, DAG);
2314 else if (isa<ExternalSymbolSDNode>(Callee))
2315 Callee = LowerExternalSymbol(Callee, DAG);
2319 if (Is64Bit && isVarArg && !IsWin64) {
2320 // From AMD64 ABI document:
2321 // For calls that may call functions that use varargs or stdargs
2322 // (prototype-less calls or calls to functions containing ellipsis (...) in
2323 // the declaration) %al is used as hidden argument to specify the number
2324 // of SSE registers used. The contents of %al do not need to match exactly
2325 // the number of registers, but must be an ubound on the number of SSE
2326 // registers used and is in the range 0 - 8 inclusive.
2328 // Count the number of XMM registers allocated.
2329 static const uint16_t XMMArgRegs[] = {
2330 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2331 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2333 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2334 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2335 && "SSE registers cannot be used when SSE is disabled");
2337 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2338 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2339 InFlag = Chain.getValue(1);
2343 // For tail calls lower the arguments to the 'real' stack slot.
2345 // Force all the incoming stack arguments to be loaded from the stack
2346 // before any new outgoing arguments are stored to the stack, because the
2347 // outgoing stack slots may alias the incoming argument stack slots, and
2348 // the alias isn't otherwise explicit. This is slightly more conservative
2349 // than necessary, because it means that each store effectively depends
2350 // on every argument instead of just those arguments it would clobber.
2351 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2353 SmallVector<SDValue, 8> MemOpChains2;
2356 // Do not flag preceding copytoreg stuff together with the following stuff.
2358 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2359 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2360 CCValAssign &VA = ArgLocs[i];
2363 assert(VA.isMemLoc());
2364 SDValue Arg = OutVals[i];
2365 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2366 // Create frame index.
2367 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2368 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2369 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2370 FIN = DAG.getFrameIndex(FI, getPointerTy());
2372 if (Flags.isByVal()) {
2373 // Copy relative to framepointer.
2374 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2375 if (StackPtr.getNode() == 0)
2376 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2378 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2380 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2384 // Store relative to framepointer.
2385 MemOpChains2.push_back(
2386 DAG.getStore(ArgChain, dl, Arg, FIN,
2387 MachinePointerInfo::getFixedStack(FI),
2393 if (!MemOpChains2.empty())
2394 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2395 &MemOpChains2[0], MemOpChains2.size());
2397 // Copy arguments to their registers.
2398 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2399 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2400 RegsToPass[i].second, InFlag);
2401 InFlag = Chain.getValue(1);
2405 // Store the return address to the appropriate stack slot.
2406 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2410 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2411 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2412 // In the 64-bit large code model, we have to make all calls
2413 // through a register, since the call instruction's 32-bit
2414 // pc-relative offset may not be large enough to hold the whole
2416 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2417 // If the callee is a GlobalAddress node (quite common, every direct call
2418 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2421 // We should use extra load for direct calls to dllimported functions in
2423 const GlobalValue *GV = G->getGlobal();
2424 if (!GV->hasDLLImportLinkage()) {
2425 unsigned char OpFlags = 0;
2426 bool ExtraLoad = false;
2427 unsigned WrapperKind = ISD::DELETED_NODE;
2429 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2430 // external symbols most go through the PLT in PIC mode. If the symbol
2431 // has hidden or protected visibility, or if it is static or local, then
2432 // we don't need to use the PLT - we can directly call it.
2433 if (Subtarget->isTargetELF() &&
2434 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2435 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2436 OpFlags = X86II::MO_PLT;
2437 } else if (Subtarget->isPICStyleStubAny() &&
2438 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2439 (!Subtarget->getTargetTriple().isMacOSX() ||
2440 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2441 // PC-relative references to external symbols should go through $stub,
2442 // unless we're building with the leopard linker or later, which
2443 // automatically synthesizes these stubs.
2444 OpFlags = X86II::MO_DARWIN_STUB;
2445 } else if (Subtarget->isPICStyleRIPRel() &&
2446 isa<Function>(GV) &&
2447 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2448 // If the function is marked as non-lazy, generate an indirect call
2449 // which loads from the GOT directly. This avoids runtime overhead
2450 // at the cost of eager binding (and one extra byte of encoding).
2451 OpFlags = X86II::MO_GOTPCREL;
2452 WrapperKind = X86ISD::WrapperRIP;
2456 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2457 G->getOffset(), OpFlags);
2459 // Add a wrapper if needed.
2460 if (WrapperKind != ISD::DELETED_NODE)
2461 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2462 // Add extra indirection if needed.
2464 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2465 MachinePointerInfo::getGOT(),
2466 false, false, false, 0);
2468 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2469 unsigned char OpFlags = 0;
2471 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2472 // external symbols should go through the PLT.
2473 if (Subtarget->isTargetELF() &&
2474 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2475 OpFlags = X86II::MO_PLT;
2476 } else if (Subtarget->isPICStyleStubAny() &&
2477 (!Subtarget->getTargetTriple().isMacOSX() ||
2478 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2479 // PC-relative references to external symbols should go through $stub,
2480 // unless we're building with the leopard linker or later, which
2481 // automatically synthesizes these stubs.
2482 OpFlags = X86II::MO_DARWIN_STUB;
2485 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2489 // Returns a chain & a flag for retval copy to use.
2490 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2491 SmallVector<SDValue, 8> Ops;
2493 if (!IsSibcall && isTailCall) {
2494 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2495 DAG.getIntPtrConstant(0, true), InFlag);
2496 InFlag = Chain.getValue(1);
2499 Ops.push_back(Chain);
2500 Ops.push_back(Callee);
2503 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2505 // Add argument registers to the end of the list so that they are known live
2507 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2508 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2509 RegsToPass[i].second.getValueType()));
2511 // Add an implicit use GOT pointer in EBX.
2512 if (!isTailCall && Subtarget->isPICStyleGOT())
2513 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2515 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2516 if (Is64Bit && isVarArg && !IsWin64)
2517 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2519 // Add a register mask operand representing the call-preserved registers.
2520 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2521 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2522 assert(Mask && "Missing call preserved mask for calling convention");
2523 Ops.push_back(DAG.getRegisterMask(Mask));
2525 if (InFlag.getNode())
2526 Ops.push_back(InFlag);
2530 //// If this is the first return lowered for this function, add the regs
2531 //// to the liveout set for the function.
2532 // This isn't right, although it's probably harmless on x86; liveouts
2533 // should be computed from returns not tail calls. Consider a void
2534 // function making a tail call to a function returning int.
2535 return DAG.getNode(X86ISD::TC_RETURN, dl,
2536 NodeTys, &Ops[0], Ops.size());
2539 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2540 InFlag = Chain.getValue(1);
2542 // Create the CALLSEQ_END node.
2543 unsigned NumBytesForCalleeToPush;
2544 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2545 getTargetMachine().Options.GuaranteedTailCallOpt))
2546 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2547 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2549 // If this is a call to a struct-return function, the callee
2550 // pops the hidden struct pointer, so we have to push it back.
2551 // This is common for Darwin/X86, Linux & Mingw32 targets.
2552 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2553 NumBytesForCalleeToPush = 4;
2555 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2557 // Returns a flag for retval copy to use.
2559 Chain = DAG.getCALLSEQ_END(Chain,
2560 DAG.getIntPtrConstant(NumBytes, true),
2561 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2564 InFlag = Chain.getValue(1);
2567 // Handle result values, copying them out of physregs into vregs that we
2569 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2570 Ins, dl, DAG, InVals);
2574 //===----------------------------------------------------------------------===//
2575 // Fast Calling Convention (tail call) implementation
2576 //===----------------------------------------------------------------------===//
2578 // Like std call, callee cleans arguments, convention except that ECX is
2579 // reserved for storing the tail called function address. Only 2 registers are
2580 // free for argument passing (inreg). Tail call optimization is performed
2582 // * tailcallopt is enabled
2583 // * caller/callee are fastcc
2584 // On X86_64 architecture with GOT-style position independent code only local
2585 // (within module) calls are supported at the moment.
2586 // To keep the stack aligned according to platform abi the function
2587 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2588 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2589 // If a tail called function callee has more arguments than the caller the
2590 // caller needs to make sure that there is room to move the RETADDR to. This is
2591 // achieved by reserving an area the size of the argument delta right after the
2592 // original REtADDR, but before the saved framepointer or the spilled registers
2593 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2605 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2606 /// for a 16 byte align requirement.
2608 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2609 SelectionDAG& DAG) const {
2610 MachineFunction &MF = DAG.getMachineFunction();
2611 const TargetMachine &TM = MF.getTarget();
2612 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2613 unsigned StackAlignment = TFI.getStackAlignment();
2614 uint64_t AlignMask = StackAlignment - 1;
2615 int64_t Offset = StackSize;
2616 uint64_t SlotSize = TD->getPointerSize();
2617 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2618 // Number smaller than 12 so just add the difference.
2619 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2621 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2622 Offset = ((~AlignMask) & Offset) + StackAlignment +
2623 (StackAlignment-SlotSize);
2628 /// MatchingStackOffset - Return true if the given stack call argument is
2629 /// already available in the same position (relatively) of the caller's
2630 /// incoming argument stack.
2632 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2633 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2634 const X86InstrInfo *TII) {
2635 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2637 if (Arg.getOpcode() == ISD::CopyFromReg) {
2638 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2639 if (!TargetRegisterInfo::isVirtualRegister(VR))
2641 MachineInstr *Def = MRI->getVRegDef(VR);
2644 if (!Flags.isByVal()) {
2645 if (!TII->isLoadFromStackSlot(Def, FI))
2648 unsigned Opcode = Def->getOpcode();
2649 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2650 Def->getOperand(1).isFI()) {
2651 FI = Def->getOperand(1).getIndex();
2652 Bytes = Flags.getByValSize();
2656 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2657 if (Flags.isByVal())
2658 // ByVal argument is passed in as a pointer but it's now being
2659 // dereferenced. e.g.
2660 // define @foo(%struct.X* %A) {
2661 // tail call @bar(%struct.X* byval %A)
2664 SDValue Ptr = Ld->getBasePtr();
2665 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2668 FI = FINode->getIndex();
2669 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2670 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2671 FI = FINode->getIndex();
2672 Bytes = Flags.getByValSize();
2676 assert(FI != INT_MAX);
2677 if (!MFI->isFixedObjectIndex(FI))
2679 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2682 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2683 /// for tail call optimization. Targets which want to do tail call
2684 /// optimization should implement this function.
2686 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2687 CallingConv::ID CalleeCC,
2689 bool isCalleeStructRet,
2690 bool isCallerStructRet,
2691 const SmallVectorImpl<ISD::OutputArg> &Outs,
2692 const SmallVectorImpl<SDValue> &OutVals,
2693 const SmallVectorImpl<ISD::InputArg> &Ins,
2694 SelectionDAG& DAG) const {
2695 if (!IsTailCallConvention(CalleeCC) &&
2696 CalleeCC != CallingConv::C)
2699 // If -tailcallopt is specified, make fastcc functions tail-callable.
2700 const MachineFunction &MF = DAG.getMachineFunction();
2701 const Function *CallerF = DAG.getMachineFunction().getFunction();
2702 CallingConv::ID CallerCC = CallerF->getCallingConv();
2703 bool CCMatch = CallerCC == CalleeCC;
2705 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2706 if (IsTailCallConvention(CalleeCC) && CCMatch)
2711 // Look for obvious safe cases to perform tail call optimization that do not
2712 // require ABI changes. This is what gcc calls sibcall.
2714 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2715 // emit a special epilogue.
2716 if (RegInfo->needsStackRealignment(MF))
2719 // Also avoid sibcall optimization if either caller or callee uses struct
2720 // return semantics.
2721 if (isCalleeStructRet || isCallerStructRet)
2724 // An stdcall caller is expected to clean up its arguments; the callee
2725 // isn't going to do that.
2726 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2729 // Do not sibcall optimize vararg calls unless all arguments are passed via
2731 if (isVarArg && !Outs.empty()) {
2733 // Optimizing for varargs on Win64 is unlikely to be safe without
2734 // additional testing.
2735 if (Subtarget->isTargetWin64())
2738 SmallVector<CCValAssign, 16> ArgLocs;
2739 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2740 getTargetMachine(), ArgLocs, *DAG.getContext());
2742 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2743 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2744 if (!ArgLocs[i].isRegLoc())
2748 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2749 // stack. Therefore, if it's not used by the call it is not safe to optimize
2750 // this into a sibcall.
2751 bool Unused = false;
2752 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2759 SmallVector<CCValAssign, 16> RVLocs;
2760 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2761 getTargetMachine(), RVLocs, *DAG.getContext());
2762 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2763 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2764 CCValAssign &VA = RVLocs[i];
2765 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2770 // If the calling conventions do not match, then we'd better make sure the
2771 // results are returned in the same way as what the caller expects.
2773 SmallVector<CCValAssign, 16> RVLocs1;
2774 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2775 getTargetMachine(), RVLocs1, *DAG.getContext());
2776 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2778 SmallVector<CCValAssign, 16> RVLocs2;
2779 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2780 getTargetMachine(), RVLocs2, *DAG.getContext());
2781 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2783 if (RVLocs1.size() != RVLocs2.size())
2785 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2786 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2788 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2790 if (RVLocs1[i].isRegLoc()) {
2791 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2794 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2800 // If the callee takes no arguments then go on to check the results of the
2802 if (!Outs.empty()) {
2803 // Check if stack adjustment is needed. For now, do not do this if any
2804 // argument is passed on the stack.
2805 SmallVector<CCValAssign, 16> ArgLocs;
2806 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2807 getTargetMachine(), ArgLocs, *DAG.getContext());
2809 // Allocate shadow area for Win64
2810 if (Subtarget->isTargetWin64()) {
2811 CCInfo.AllocateStack(32, 8);
2814 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2815 if (CCInfo.getNextStackOffset()) {
2816 MachineFunction &MF = DAG.getMachineFunction();
2817 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2820 // Check if the arguments are already laid out in the right way as
2821 // the caller's fixed stack objects.
2822 MachineFrameInfo *MFI = MF.getFrameInfo();
2823 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2824 const X86InstrInfo *TII =
2825 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2826 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2827 CCValAssign &VA = ArgLocs[i];
2828 SDValue Arg = OutVals[i];
2829 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2830 if (VA.getLocInfo() == CCValAssign::Indirect)
2832 if (!VA.isRegLoc()) {
2833 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2840 // If the tailcall address may be in a register, then make sure it's
2841 // possible to register allocate for it. In 32-bit, the call address can
2842 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2843 // callee-saved registers are restored. These happen to be the same
2844 // registers used to pass 'inreg' arguments so watch out for those.
2845 if (!Subtarget->is64Bit() &&
2846 !isa<GlobalAddressSDNode>(Callee) &&
2847 !isa<ExternalSymbolSDNode>(Callee)) {
2848 unsigned NumInRegs = 0;
2849 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2850 CCValAssign &VA = ArgLocs[i];
2853 unsigned Reg = VA.getLocReg();
2856 case X86::EAX: case X86::EDX: case X86::ECX:
2857 if (++NumInRegs == 3)
2869 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2870 return X86::createFastISel(funcInfo);
2874 //===----------------------------------------------------------------------===//
2875 // Other Lowering Hooks
2876 //===----------------------------------------------------------------------===//
2878 static bool MayFoldLoad(SDValue Op) {
2879 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2882 static bool MayFoldIntoStore(SDValue Op) {
2883 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2886 static bool isTargetShuffle(unsigned Opcode) {
2888 default: return false;
2889 case X86ISD::PSHUFD:
2890 case X86ISD::PSHUFHW:
2891 case X86ISD::PSHUFLW:
2893 case X86ISD::PALIGN:
2894 case X86ISD::MOVLHPS:
2895 case X86ISD::MOVLHPD:
2896 case X86ISD::MOVHLPS:
2897 case X86ISD::MOVLPS:
2898 case X86ISD::MOVLPD:
2899 case X86ISD::MOVSHDUP:
2900 case X86ISD::MOVSLDUP:
2901 case X86ISD::MOVDDUP:
2904 case X86ISD::UNPCKL:
2905 case X86ISD::UNPCKH:
2906 case X86ISD::VPERMILP:
2907 case X86ISD::VPERM2X128:
2912 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2913 SDValue V1, SelectionDAG &DAG) {
2915 default: llvm_unreachable("Unknown x86 shuffle node");
2916 case X86ISD::MOVSHDUP:
2917 case X86ISD::MOVSLDUP:
2918 case X86ISD::MOVDDUP:
2919 return DAG.getNode(Opc, dl, VT, V1);
2923 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2924 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2926 default: llvm_unreachable("Unknown x86 shuffle node");
2927 case X86ISD::PSHUFD:
2928 case X86ISD::PSHUFHW:
2929 case X86ISD::PSHUFLW:
2930 case X86ISD::VPERMILP:
2931 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2935 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2936 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2938 default: llvm_unreachable("Unknown x86 shuffle node");
2939 case X86ISD::PALIGN:
2941 case X86ISD::VPERM2X128:
2942 return DAG.getNode(Opc, dl, VT, V1, V2,
2943 DAG.getConstant(TargetMask, MVT::i8));
2947 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2948 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2950 default: llvm_unreachable("Unknown x86 shuffle node");
2951 case X86ISD::MOVLHPS:
2952 case X86ISD::MOVLHPD:
2953 case X86ISD::MOVHLPS:
2954 case X86ISD::MOVLPS:
2955 case X86ISD::MOVLPD:
2958 case X86ISD::UNPCKL:
2959 case X86ISD::UNPCKH:
2960 return DAG.getNode(Opc, dl, VT, V1, V2);
2964 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2965 MachineFunction &MF = DAG.getMachineFunction();
2966 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2967 int ReturnAddrIndex = FuncInfo->getRAIndex();
2969 if (ReturnAddrIndex == 0) {
2970 // Set up a frame object for the return address.
2971 uint64_t SlotSize = TD->getPointerSize();
2972 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2974 FuncInfo->setRAIndex(ReturnAddrIndex);
2977 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2981 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2982 bool hasSymbolicDisplacement) {
2983 // Offset should fit into 32 bit immediate field.
2984 if (!isInt<32>(Offset))
2987 // If we don't have a symbolic displacement - we don't have any extra
2989 if (!hasSymbolicDisplacement)
2992 // FIXME: Some tweaks might be needed for medium code model.
2993 if (M != CodeModel::Small && M != CodeModel::Kernel)
2996 // For small code model we assume that latest object is 16MB before end of 31
2997 // bits boundary. We may also accept pretty large negative constants knowing
2998 // that all objects are in the positive half of address space.
2999 if (M == CodeModel::Small && Offset < 16*1024*1024)
3002 // For kernel code model we know that all object resist in the negative half
3003 // of 32bits address space. We may not accept negative offsets, since they may
3004 // be just off and we may accept pretty large positive ones.
3005 if (M == CodeModel::Kernel && Offset > 0)
3011 /// isCalleePop - Determines whether the callee is required to pop its
3012 /// own arguments. Callee pop is necessary to support tail calls.
3013 bool X86::isCalleePop(CallingConv::ID CallingConv,
3014 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3018 switch (CallingConv) {
3021 case CallingConv::X86_StdCall:
3023 case CallingConv::X86_FastCall:
3025 case CallingConv::X86_ThisCall:
3027 case CallingConv::Fast:
3029 case CallingConv::GHC:
3034 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3035 /// specific condition code, returning the condition code and the LHS/RHS of the
3036 /// comparison to make.
3037 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3038 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3040 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3041 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3042 // X > -1 -> X == 0, jump !sign.
3043 RHS = DAG.getConstant(0, RHS.getValueType());
3044 return X86::COND_NS;
3045 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3046 // X < 0 -> X == 0, jump on sign.
3048 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3050 RHS = DAG.getConstant(0, RHS.getValueType());
3051 return X86::COND_LE;
3055 switch (SetCCOpcode) {
3056 default: llvm_unreachable("Invalid integer condition!");
3057 case ISD::SETEQ: return X86::COND_E;
3058 case ISD::SETGT: return X86::COND_G;
3059 case ISD::SETGE: return X86::COND_GE;
3060 case ISD::SETLT: return X86::COND_L;
3061 case ISD::SETLE: return X86::COND_LE;
3062 case ISD::SETNE: return X86::COND_NE;
3063 case ISD::SETULT: return X86::COND_B;
3064 case ISD::SETUGT: return X86::COND_A;
3065 case ISD::SETULE: return X86::COND_BE;
3066 case ISD::SETUGE: return X86::COND_AE;
3070 // First determine if it is required or is profitable to flip the operands.
3072 // If LHS is a foldable load, but RHS is not, flip the condition.
3073 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3074 !ISD::isNON_EXTLoad(RHS.getNode())) {
3075 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3076 std::swap(LHS, RHS);
3079 switch (SetCCOpcode) {
3085 std::swap(LHS, RHS);
3089 // On a floating point condition, the flags are set as follows:
3091 // 0 | 0 | 0 | X > Y
3092 // 0 | 0 | 1 | X < Y
3093 // 1 | 0 | 0 | X == Y
3094 // 1 | 1 | 1 | unordered
3095 switch (SetCCOpcode) {
3096 default: llvm_unreachable("Condcode should be pre-legalized away");
3098 case ISD::SETEQ: return X86::COND_E;
3099 case ISD::SETOLT: // flipped
3101 case ISD::SETGT: return X86::COND_A;
3102 case ISD::SETOLE: // flipped
3104 case ISD::SETGE: return X86::COND_AE;
3105 case ISD::SETUGT: // flipped
3107 case ISD::SETLT: return X86::COND_B;
3108 case ISD::SETUGE: // flipped
3110 case ISD::SETLE: return X86::COND_BE;
3112 case ISD::SETNE: return X86::COND_NE;
3113 case ISD::SETUO: return X86::COND_P;
3114 case ISD::SETO: return X86::COND_NP;
3116 case ISD::SETUNE: return X86::COND_INVALID;
3120 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3121 /// code. Current x86 isa includes the following FP cmov instructions:
3122 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3123 static bool hasFPCMov(unsigned X86CC) {
3139 /// isFPImmLegal - Returns true if the target can instruction select the
3140 /// specified FP immediate natively. If false, the legalizer will
3141 /// materialize the FP immediate as a load from a constant pool.
3142 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3143 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3144 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3150 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3151 /// the specified range (L, H].
3152 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3153 return (Val < 0) || (Val >= Low && Val < Hi);
3156 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3157 /// specified value.
3158 static bool isUndefOrEqual(int Val, int CmpVal) {
3159 if (Val < 0 || Val == CmpVal)
3164 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3165 /// from position Pos and ending in Pos+Size, falls within the specified
3166 /// sequential range (L, L+Pos]. or is undef.
3167 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3168 int Pos, int Size, int Low) {
3169 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3170 if (!isUndefOrEqual(Mask[i], Low))
3175 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3176 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3177 /// the second operand.
3178 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3179 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3180 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3181 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3182 return (Mask[0] < 2 && Mask[1] < 2);
3186 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3187 /// is suitable for input to PSHUFHW.
3188 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3189 if (VT != MVT::v8i16)
3192 // Lower quadword copied in order or undef.
3193 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3196 // Upper quadword shuffled.
3197 for (unsigned i = 4; i != 8; ++i)
3198 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3204 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3205 /// is suitable for input to PSHUFLW.
3206 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3207 if (VT != MVT::v8i16)
3210 // Upper quadword copied in order.
3211 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3214 // Lower quadword shuffled.
3215 for (unsigned i = 0; i != 4; ++i)
3222 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3223 /// is suitable for input to PALIGNR.
3224 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3225 const X86Subtarget *Subtarget) {
3226 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3227 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3230 unsigned NumElts = VT.getVectorNumElements();
3231 unsigned NumLanes = VT.getSizeInBits()/128;
3232 unsigned NumLaneElts = NumElts/NumLanes;
3234 // Do not handle 64-bit element shuffles with palignr.
3235 if (NumLaneElts == 2)
3238 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3240 for (i = 0; i != NumLaneElts; ++i) {
3245 // Lane is all undef, go to next lane
3246 if (i == NumLaneElts)
3249 int Start = Mask[i+l];
3251 // Make sure its in this lane in one of the sources
3252 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3253 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3256 // If not lane 0, then we must match lane 0
3257 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3260 // Correct second source to be contiguous with first source
3261 if (Start >= (int)NumElts)
3262 Start -= NumElts - NumLaneElts;
3264 // Make sure we're shifting in the right direction.
3265 if (Start <= (int)(i+l))
3270 // Check the rest of the elements to see if they are consecutive.
3271 for (++i; i != NumLaneElts; ++i) {
3272 int Idx = Mask[i+l];
3274 // Make sure its in this lane
3275 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3276 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3279 // If not lane 0, then we must match lane 0
3280 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3283 if (Idx >= (int)NumElts)
3284 Idx -= NumElts - NumLaneElts;
3286 if (!isUndefOrEqual(Idx, Start+i))
3295 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3296 /// the two vector operands have swapped position.
3297 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3298 unsigned NumElems) {
3299 for (unsigned i = 0; i != NumElems; ++i) {
3303 else if (idx < (int)NumElems)
3304 Mask[i] = idx + NumElems;
3306 Mask[i] = idx - NumElems;
3310 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3311 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3312 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3313 /// reverse of what x86 shuffles want.
3314 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3315 bool Commuted = false) {
3316 if (!HasAVX && VT.getSizeInBits() == 256)
3319 unsigned NumElems = VT.getVectorNumElements();
3320 unsigned NumLanes = VT.getSizeInBits()/128;
3321 unsigned NumLaneElems = NumElems/NumLanes;
3323 if (NumLaneElems != 2 && NumLaneElems != 4)
3326 // VSHUFPSY divides the resulting vector into 4 chunks.
3327 // The sources are also splitted into 4 chunks, and each destination
3328 // chunk must come from a different source chunk.
3330 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3331 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3333 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3334 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3336 // VSHUFPDY divides the resulting vector into 4 chunks.
3337 // The sources are also splitted into 4 chunks, and each destination
3338 // chunk must come from a different source chunk.
3340 // SRC1 => X3 X2 X1 X0
3341 // SRC2 => Y3 Y2 Y1 Y0
3343 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3345 unsigned HalfLaneElems = NumLaneElems/2;
3346 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3347 for (unsigned i = 0; i != NumLaneElems; ++i) {
3348 int Idx = Mask[i+l];
3349 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3350 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3352 // For VSHUFPSY, the mask of the second half must be the same as the
3353 // first but with the appropriate offsets. This works in the same way as
3354 // VPERMILPS works with masks.
3355 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3357 if (!isUndefOrEqual(Idx, Mask[i]+l))
3365 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3366 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3367 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3368 unsigned NumElems = VT.getVectorNumElements();
3370 if (VT.getSizeInBits() != 128)
3376 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3377 return isUndefOrEqual(Mask[0], 6) &&
3378 isUndefOrEqual(Mask[1], 7) &&
3379 isUndefOrEqual(Mask[2], 2) &&
3380 isUndefOrEqual(Mask[3], 3);
3383 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3384 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3386 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3387 unsigned NumElems = VT.getVectorNumElements();
3389 if (VT.getSizeInBits() != 128)
3395 return isUndefOrEqual(Mask[0], 2) &&
3396 isUndefOrEqual(Mask[1], 3) &&
3397 isUndefOrEqual(Mask[2], 2) &&
3398 isUndefOrEqual(Mask[3], 3);
3401 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3402 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3403 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3404 if (VT.getSizeInBits() != 128)
3407 unsigned NumElems = VT.getVectorNumElements();
3409 if (NumElems != 2 && NumElems != 4)
3412 for (unsigned i = 0; i != NumElems/2; ++i)
3413 if (!isUndefOrEqual(Mask[i], i + NumElems))
3416 for (unsigned i = NumElems/2; i != NumElems; ++i)
3417 if (!isUndefOrEqual(Mask[i], i))
3423 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3424 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3425 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3426 unsigned NumElems = VT.getVectorNumElements();
3428 if ((NumElems != 2 && NumElems != 4)
3429 || VT.getSizeInBits() > 128)
3432 for (unsigned i = 0; i != NumElems/2; ++i)
3433 if (!isUndefOrEqual(Mask[i], i))
3436 for (unsigned i = 0; i != NumElems/2; ++i)
3437 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems))
3443 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3444 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3445 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3446 bool HasAVX2, bool V2IsSplat = false) {
3447 unsigned NumElts = VT.getVectorNumElements();
3449 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3450 "Unsupported vector type for unpckh");
3452 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3453 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3456 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3457 // independently on 128-bit lanes.
3458 unsigned NumLanes = VT.getSizeInBits()/128;
3459 unsigned NumLaneElts = NumElts/NumLanes;
3461 for (unsigned l = 0; l != NumLanes; ++l) {
3462 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3463 i != (l+1)*NumLaneElts;
3466 int BitI1 = Mask[i+1];
3467 if (!isUndefOrEqual(BitI, j))
3470 if (!isUndefOrEqual(BitI1, NumElts))
3473 if (!isUndefOrEqual(BitI1, j + NumElts))
3482 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3483 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3484 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3485 bool HasAVX2, bool V2IsSplat = false) {
3486 unsigned NumElts = VT.getVectorNumElements();
3488 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3489 "Unsupported vector type for unpckh");
3491 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3492 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3495 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3496 // independently on 128-bit lanes.
3497 unsigned NumLanes = VT.getSizeInBits()/128;
3498 unsigned NumLaneElts = NumElts/NumLanes;
3500 for (unsigned l = 0; l != NumLanes; ++l) {
3501 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3502 i != (l+1)*NumLaneElts; i += 2, ++j) {
3504 int BitI1 = Mask[i+1];
3505 if (!isUndefOrEqual(BitI, j))
3508 if (isUndefOrEqual(BitI1, NumElts))
3511 if (!isUndefOrEqual(BitI1, j+NumElts))
3519 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3520 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3522 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3524 unsigned NumElts = VT.getVectorNumElements();
3526 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3527 "Unsupported vector type for unpckh");
3529 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3530 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3533 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3534 // FIXME: Need a better way to get rid of this, there's no latency difference
3535 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3536 // the former later. We should also remove the "_undef" special mask.
3537 if (NumElts == 4 && VT.getSizeInBits() == 256)
3540 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3541 // independently on 128-bit lanes.
3542 unsigned NumLanes = VT.getSizeInBits()/128;
3543 unsigned NumLaneElts = NumElts/NumLanes;
3545 for (unsigned l = 0; l != NumLanes; ++l) {
3546 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3547 i != (l+1)*NumLaneElts;
3550 int BitI1 = Mask[i+1];
3552 if (!isUndefOrEqual(BitI, j))
3554 if (!isUndefOrEqual(BitI1, j))
3562 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3563 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3565 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3566 unsigned NumElts = VT.getVectorNumElements();
3568 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3569 "Unsupported vector type for unpckh");
3571 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3572 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3575 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3576 // independently on 128-bit lanes.
3577 unsigned NumLanes = VT.getSizeInBits()/128;
3578 unsigned NumLaneElts = NumElts/NumLanes;
3580 for (unsigned l = 0; l != NumLanes; ++l) {
3581 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3582 i != (l+1)*NumLaneElts; i += 2, ++j) {
3584 int BitI1 = Mask[i+1];
3585 if (!isUndefOrEqual(BitI, j))
3587 if (!isUndefOrEqual(BitI1, j))
3594 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3595 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3596 /// MOVSD, and MOVD, i.e. setting the lowest element.
3597 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3598 if (VT.getVectorElementType().getSizeInBits() < 32)
3600 if (VT.getSizeInBits() == 256)
3603 unsigned NumElts = VT.getVectorNumElements();
3605 if (!isUndefOrEqual(Mask[0], NumElts))
3608 for (unsigned i = 1; i != NumElts; ++i)
3609 if (!isUndefOrEqual(Mask[i], i))
3615 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3616 /// as permutations between 128-bit chunks or halves. As an example: this
3618 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3619 /// The first half comes from the second half of V1 and the second half from the
3620 /// the second half of V2.
3621 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3622 if (!HasAVX || VT.getSizeInBits() != 256)
3625 // The shuffle result is divided into half A and half B. In total the two
3626 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3627 // B must come from C, D, E or F.
3628 unsigned HalfSize = VT.getVectorNumElements()/2;
3629 bool MatchA = false, MatchB = false;
3631 // Check if A comes from one of C, D, E, F.
3632 for (unsigned Half = 0; Half != 4; ++Half) {
3633 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3639 // Check if B comes from one of C, D, E, F.
3640 for (unsigned Half = 0; Half != 4; ++Half) {
3641 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3647 return MatchA && MatchB;
3650 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3651 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3652 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3653 EVT VT = SVOp->getValueType(0);
3655 unsigned HalfSize = VT.getVectorNumElements()/2;
3657 unsigned FstHalf = 0, SndHalf = 0;
3658 for (unsigned i = 0; i < HalfSize; ++i) {
3659 if (SVOp->getMaskElt(i) > 0) {
3660 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3664 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3665 if (SVOp->getMaskElt(i) > 0) {
3666 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3671 return (FstHalf | (SndHalf << 4));
3674 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3675 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3676 /// Note that VPERMIL mask matching is different depending whether theunderlying
3677 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3678 /// to the same elements of the low, but to the higher half of the source.
3679 /// In VPERMILPD the two lanes could be shuffled independently of each other
3680 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3681 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3685 unsigned NumElts = VT.getVectorNumElements();
3686 // Only match 256-bit with 32/64-bit types
3687 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3690 unsigned NumLanes = VT.getSizeInBits()/128;
3691 unsigned LaneSize = NumElts/NumLanes;
3692 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3693 for (unsigned i = 0; i != LaneSize; ++i) {
3694 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3696 if (NumElts != 8 || l == 0)
3698 // VPERMILPS handling
3701 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3709 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3710 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3711 /// element of vector 2 and the other elements to come from vector 1 in order.
3712 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3713 bool V2IsSplat = false, bool V2IsUndef = false) {
3714 unsigned NumOps = VT.getVectorNumElements();
3715 if (VT.getSizeInBits() == 256)
3717 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3720 if (!isUndefOrEqual(Mask[0], 0))
3723 for (unsigned i = 1; i != NumOps; ++i)
3724 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3725 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3726 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3732 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3733 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3734 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3735 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3736 const X86Subtarget *Subtarget) {
3737 if (!Subtarget->hasSSE3())
3740 unsigned NumElems = VT.getVectorNumElements();
3742 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3743 (VT.getSizeInBits() == 256 && NumElems != 8))
3746 // "i+1" is the value the indexed mask element must have
3747 for (unsigned i = 0; i != NumElems; i += 2)
3748 if (!isUndefOrEqual(Mask[i], i+1) ||
3749 !isUndefOrEqual(Mask[i+1], i+1))
3755 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3756 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3757 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3758 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3759 const X86Subtarget *Subtarget) {
3760 if (!Subtarget->hasSSE3())
3763 unsigned NumElems = VT.getVectorNumElements();
3765 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3766 (VT.getSizeInBits() == 256 && NumElems != 8))
3769 // "i" is the value the indexed mask element must have
3770 for (unsigned i = 0; i != NumElems; i += 2)
3771 if (!isUndefOrEqual(Mask[i], i) ||
3772 !isUndefOrEqual(Mask[i+1], i))
3778 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3779 /// specifies a shuffle of elements that is suitable for input to 256-bit
3780 /// version of MOVDDUP.
3781 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3782 unsigned NumElts = VT.getVectorNumElements();
3784 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3787 for (unsigned i = 0; i != NumElts/2; ++i)
3788 if (!isUndefOrEqual(Mask[i], 0))
3790 for (unsigned i = NumElts/2; i != NumElts; ++i)
3791 if (!isUndefOrEqual(Mask[i], NumElts/2))
3796 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3797 /// specifies a shuffle of elements that is suitable for input to 128-bit
3798 /// version of MOVDDUP.
3799 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3800 if (VT.getSizeInBits() != 128)
3803 unsigned e = VT.getVectorNumElements() / 2;
3804 for (unsigned i = 0; i != e; ++i)
3805 if (!isUndefOrEqual(Mask[i], i))
3807 for (unsigned i = 0; i != e; ++i)
3808 if (!isUndefOrEqual(Mask[e+i], i))
3813 /// isVEXTRACTF128Index - Return true if the specified
3814 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3815 /// suitable for input to VEXTRACTF128.
3816 bool X86::isVEXTRACTF128Index(SDNode *N) {
3817 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3820 // The index should be aligned on a 128-bit boundary.
3822 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3824 unsigned VL = N->getValueType(0).getVectorNumElements();
3825 unsigned VBits = N->getValueType(0).getSizeInBits();
3826 unsigned ElSize = VBits / VL;
3827 bool Result = (Index * ElSize) % 128 == 0;
3832 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3833 /// operand specifies a subvector insert that is suitable for input to
3835 bool X86::isVINSERTF128Index(SDNode *N) {
3836 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3839 // The index should be aligned on a 128-bit boundary.
3841 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3843 unsigned VL = N->getValueType(0).getVectorNumElements();
3844 unsigned VBits = N->getValueType(0).getSizeInBits();
3845 unsigned ElSize = VBits / VL;
3846 bool Result = (Index * ElSize) % 128 == 0;
3851 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3852 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3853 /// Handles 128-bit and 256-bit.
3854 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3855 EVT VT = N->getValueType(0);
3857 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3858 "Unsupported vector type for PSHUF/SHUFP");
3860 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3861 // independently on 128-bit lanes.
3862 unsigned NumElts = VT.getVectorNumElements();
3863 unsigned NumLanes = VT.getSizeInBits()/128;
3864 unsigned NumLaneElts = NumElts/NumLanes;
3866 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3867 "Only supports 2 or 4 elements per lane");
3869 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3871 for (unsigned i = 0; i != NumElts; ++i) {
3872 int Elt = N->getMaskElt(i);
3873 if (Elt < 0) continue;
3875 unsigned ShAmt = i << Shift;
3876 if (ShAmt >= 8) ShAmt -= 8;
3877 Mask |= Elt << ShAmt;
3883 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3884 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3885 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3887 // 8 nodes, but we only care about the last 4.
3888 for (unsigned i = 7; i >= 4; --i) {
3889 int Val = N->getMaskElt(i);
3898 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3899 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3900 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3902 // 8 nodes, but we only care about the first 4.
3903 for (int i = 3; i >= 0; --i) {
3904 int Val = N->getMaskElt(i);
3913 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3914 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3915 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3916 EVT VT = SVOp->getValueType(0);
3917 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3919 unsigned NumElts = VT.getVectorNumElements();
3920 unsigned NumLanes = VT.getSizeInBits()/128;
3921 unsigned NumLaneElts = NumElts/NumLanes;
3925 for (i = 0; i != NumElts; ++i) {
3926 Val = SVOp->getMaskElt(i);
3930 if (Val >= (int)NumElts)
3931 Val -= NumElts - NumLaneElts;
3933 assert(Val - i > 0 && "PALIGNR imm should be positive");
3934 return (Val - i) * EltSize;
3937 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3938 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3940 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3941 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3942 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3945 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3947 EVT VecVT = N->getOperand(0).getValueType();
3948 EVT ElVT = VecVT.getVectorElementType();
3950 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3951 return Index / NumElemsPerChunk;
3954 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3955 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3957 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3958 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3959 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3962 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3964 EVT VecVT = N->getValueType(0);
3965 EVT ElVT = VecVT.getVectorElementType();
3967 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3968 return Index / NumElemsPerChunk;
3971 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3973 bool X86::isZeroNode(SDValue Elt) {
3974 return ((isa<ConstantSDNode>(Elt) &&
3975 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3976 (isa<ConstantFPSDNode>(Elt) &&
3977 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3980 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3981 /// their permute mask.
3982 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3983 SelectionDAG &DAG) {
3984 EVT VT = SVOp->getValueType(0);
3985 unsigned NumElems = VT.getVectorNumElements();
3986 SmallVector<int, 8> MaskVec;
3988 for (unsigned i = 0; i != NumElems; ++i) {
3989 int idx = SVOp->getMaskElt(i);
3991 MaskVec.push_back(idx);
3992 else if (idx < (int)NumElems)
3993 MaskVec.push_back(idx + NumElems);
3995 MaskVec.push_back(idx - NumElems);
3997 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3998 SVOp->getOperand(0), &MaskVec[0]);
4001 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4002 /// match movhlps. The lower half elements should come from upper half of
4003 /// V1 (and in order), and the upper half elements should come from the upper
4004 /// half of V2 (and in order).
4005 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4006 if (VT.getSizeInBits() != 128)
4008 if (VT.getVectorNumElements() != 4)
4010 for (unsigned i = 0, e = 2; i != e; ++i)
4011 if (!isUndefOrEqual(Mask[i], i+2))
4013 for (unsigned i = 2; i != 4; ++i)
4014 if (!isUndefOrEqual(Mask[i], i+4))
4019 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4020 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4022 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4023 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4025 N = N->getOperand(0).getNode();
4026 if (!ISD::isNON_EXTLoad(N))
4029 *LD = cast<LoadSDNode>(N);
4033 // Test whether the given value is a vector value which will be legalized
4035 static bool WillBeConstantPoolLoad(SDNode *N) {
4036 if (N->getOpcode() != ISD::BUILD_VECTOR)
4039 // Check for any non-constant elements.
4040 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4041 switch (N->getOperand(i).getNode()->getOpcode()) {
4043 case ISD::ConstantFP:
4050 // Vectors of all-zeros and all-ones are materialized with special
4051 // instructions rather than being loaded.
4052 return !ISD::isBuildVectorAllZeros(N) &&
4053 !ISD::isBuildVectorAllOnes(N);
4056 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4057 /// match movlp{s|d}. The lower half elements should come from lower half of
4058 /// V1 (and in order), and the upper half elements should come from the upper
4059 /// half of V2 (and in order). And since V1 will become the source of the
4060 /// MOVLP, it must be either a vector load or a scalar load to vector.
4061 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4062 ArrayRef<int> Mask, EVT VT) {
4063 if (VT.getSizeInBits() != 128)
4066 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4068 // Is V2 is a vector load, don't do this transformation. We will try to use
4069 // load folding shufps op.
4070 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4073 unsigned NumElems = VT.getVectorNumElements();
4075 if (NumElems != 2 && NumElems != 4)
4077 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4078 if (!isUndefOrEqual(Mask[i], i))
4080 for (unsigned i = NumElems/2; i != NumElems; ++i)
4081 if (!isUndefOrEqual(Mask[i], i+NumElems))
4086 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4088 static bool isSplatVector(SDNode *N) {
4089 if (N->getOpcode() != ISD::BUILD_VECTOR)
4092 SDValue SplatValue = N->getOperand(0);
4093 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4094 if (N->getOperand(i) != SplatValue)
4099 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4100 /// to an zero vector.
4101 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4102 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4103 SDValue V1 = N->getOperand(0);
4104 SDValue V2 = N->getOperand(1);
4105 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4106 for (unsigned i = 0; i != NumElems; ++i) {
4107 int Idx = N->getMaskElt(i);
4108 if (Idx >= (int)NumElems) {
4109 unsigned Opc = V2.getOpcode();
4110 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4112 if (Opc != ISD::BUILD_VECTOR ||
4113 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4115 } else if (Idx >= 0) {
4116 unsigned Opc = V1.getOpcode();
4117 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4119 if (Opc != ISD::BUILD_VECTOR ||
4120 !X86::isZeroNode(V1.getOperand(Idx)))
4127 /// getZeroVector - Returns a vector of specified type with all zero elements.
4129 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4130 SelectionDAG &DAG, DebugLoc dl) {
4131 assert(VT.isVector() && "Expected a vector type");
4133 // Always build SSE zero vectors as <4 x i32> bitcasted
4134 // to their dest type. This ensures they get CSE'd.
4136 if (VT.getSizeInBits() == 128) { // SSE
4137 if (Subtarget->hasSSE2()) { // SSE2
4138 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4139 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4141 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4142 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4144 } else if (VT.getSizeInBits() == 256) { // AVX
4145 if (Subtarget->hasAVX2()) { // AVX2
4146 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4147 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4148 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4150 // 256-bit logic and arithmetic instructions in AVX are all
4151 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4152 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4153 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4154 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4157 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4160 /// getOnesVector - Returns a vector of specified type with all bits set.
4161 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4162 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4163 /// Then bitcast to their original type, ensuring they get CSE'd.
4164 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4166 assert(VT.isVector() && "Expected a vector type");
4167 assert((VT.is128BitVector() || VT.is256BitVector())
4168 && "Expected a 128-bit or 256-bit vector type");
4170 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4172 if (VT.getSizeInBits() == 256) {
4173 if (HasAVX2) { // AVX2
4174 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4175 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4177 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4178 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4179 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4180 Vec = Insert128BitVector(InsV, Vec,
4181 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4184 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4187 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4190 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4191 /// that point to V2 points to its first element.
4192 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4193 for (unsigned i = 0; i != NumElems; ++i) {
4194 if (Mask[i] > (int)NumElems) {
4200 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4201 /// operation of specified width.
4202 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4204 unsigned NumElems = VT.getVectorNumElements();
4205 SmallVector<int, 8> Mask;
4206 Mask.push_back(NumElems);
4207 for (unsigned i = 1; i != NumElems; ++i)
4209 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4212 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4213 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4215 unsigned NumElems = VT.getVectorNumElements();
4216 SmallVector<int, 8> Mask;
4217 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4219 Mask.push_back(i + NumElems);
4221 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4224 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4225 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4227 unsigned NumElems = VT.getVectorNumElements();
4228 unsigned Half = NumElems/2;
4229 SmallVector<int, 8> Mask;
4230 for (unsigned i = 0; i != Half; ++i) {
4231 Mask.push_back(i + Half);
4232 Mask.push_back(i + NumElems + Half);
4234 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4237 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4238 // a generic shuffle instruction because the target has no such instructions.
4239 // Generate shuffles which repeat i16 and i8 several times until they can be
4240 // represented by v4f32 and then be manipulated by target suported shuffles.
4241 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4242 EVT VT = V.getValueType();
4243 int NumElems = VT.getVectorNumElements();
4244 DebugLoc dl = V.getDebugLoc();
4246 while (NumElems > 4) {
4247 if (EltNo < NumElems/2) {
4248 V = getUnpackl(DAG, dl, VT, V, V);
4250 V = getUnpackh(DAG, dl, VT, V, V);
4251 EltNo -= NumElems/2;
4258 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4259 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4260 EVT VT = V.getValueType();
4261 DebugLoc dl = V.getDebugLoc();
4262 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4263 && "Vector size not supported");
4265 if (VT.getSizeInBits() == 128) {
4266 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4267 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4268 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4271 // To use VPERMILPS to splat scalars, the second half of indicies must
4272 // refer to the higher part, which is a duplication of the lower one,
4273 // because VPERMILPS can only handle in-lane permutations.
4274 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4275 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4277 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4278 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4282 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4285 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4286 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4287 EVT SrcVT = SV->getValueType(0);
4288 SDValue V1 = SV->getOperand(0);
4289 DebugLoc dl = SV->getDebugLoc();
4291 int EltNo = SV->getSplatIndex();
4292 int NumElems = SrcVT.getVectorNumElements();
4293 unsigned Size = SrcVT.getSizeInBits();
4295 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4296 "Unknown how to promote splat for type");
4298 // Extract the 128-bit part containing the splat element and update
4299 // the splat element index when it refers to the higher register.
4301 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4302 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4304 EltNo -= NumElems/2;
4307 // All i16 and i8 vector types can't be used directly by a generic shuffle
4308 // instruction because the target has no such instruction. Generate shuffles
4309 // which repeat i16 and i8 several times until they fit in i32, and then can
4310 // be manipulated by target suported shuffles.
4311 EVT EltVT = SrcVT.getVectorElementType();
4312 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4313 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4315 // Recreate the 256-bit vector and place the same 128-bit vector
4316 // into the low and high part. This is necessary because we want
4317 // to use VPERM* to shuffle the vectors
4319 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4320 DAG.getConstant(0, MVT::i32), DAG, dl);
4321 V1 = Insert128BitVector(InsV, V1,
4322 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4325 return getLegalSplat(DAG, V1, EltNo);
4328 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4329 /// vector of zero or undef vector. This produces a shuffle where the low
4330 /// element of V2 is swizzled into the zero/undef vector, landing at element
4331 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4332 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4334 const X86Subtarget *Subtarget,
4335 SelectionDAG &DAG) {
4336 EVT VT = V2.getValueType();
4338 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4339 unsigned NumElems = VT.getVectorNumElements();
4340 SmallVector<int, 16> MaskVec;
4341 for (unsigned i = 0; i != NumElems; ++i)
4342 // If this is the insertion idx, put the low elt of V2 here.
4343 MaskVec.push_back(i == Idx ? NumElems : i);
4344 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4347 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4348 /// element of the result of the vector shuffle.
4349 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4352 return SDValue(); // Limit search depth.
4354 SDValue V = SDValue(N, 0);
4355 EVT VT = V.getValueType();
4356 unsigned Opcode = V.getOpcode();
4358 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4359 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4360 Index = SV->getMaskElt(Index);
4363 return DAG.getUNDEF(VT.getVectorElementType());
4365 unsigned NumElems = VT.getVectorNumElements();
4366 SDValue NewV = (Index < (int)NumElems) ? SV->getOperand(0)
4367 : SV->getOperand(1);
4368 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4371 // Recurse into target specific vector shuffles to find scalars.
4372 if (isTargetShuffle(Opcode)) {
4373 unsigned NumElems = VT.getVectorNumElements();
4374 SmallVector<unsigned, 16> ShuffleMask;
4379 ImmN = N->getOperand(N->getNumOperands()-1);
4380 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4383 case X86ISD::UNPCKH:
4384 DecodeUNPCKHMask(VT, ShuffleMask);
4386 case X86ISD::UNPCKL:
4387 DecodeUNPCKLMask(VT, ShuffleMask);
4389 case X86ISD::MOVHLPS:
4390 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4392 case X86ISD::MOVLHPS:
4393 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4395 case X86ISD::PSHUFD:
4396 case X86ISD::VPERMILP:
4397 ImmN = N->getOperand(N->getNumOperands()-1);
4398 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4401 case X86ISD::PSHUFHW:
4402 ImmN = N->getOperand(N->getNumOperands()-1);
4403 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4406 case X86ISD::PSHUFLW:
4407 ImmN = N->getOperand(N->getNumOperands()-1);
4408 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4412 case X86ISD::MOVSD: {
4413 // The index 0 always comes from the first element of the second source,
4414 // this is why MOVSS and MOVSD are used in the first place. The other
4415 // elements come from the other positions of the first source vector.
4416 unsigned OpNum = (Index == 0) ? 1 : 0;
4417 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4420 case X86ISD::VPERM2X128:
4421 ImmN = N->getOperand(N->getNumOperands()-1);
4422 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4425 case X86ISD::MOVDDUP:
4426 case X86ISD::MOVLHPD:
4427 case X86ISD::MOVLPD:
4428 case X86ISD::MOVLPS:
4429 case X86ISD::MOVSHDUP:
4430 case X86ISD::MOVSLDUP:
4431 case X86ISD::PALIGN:
4432 return SDValue(); // Not yet implemented.
4433 default: llvm_unreachable("unknown target shuffle node");
4436 Index = ShuffleMask[Index];
4438 return DAG.getUNDEF(VT.getVectorElementType());
4440 SDValue NewV = (Index < (int)NumElems) ? N->getOperand(0)
4442 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4446 // Actual nodes that may contain scalar elements
4447 if (Opcode == ISD::BITCAST) {
4448 V = V.getOperand(0);
4449 EVT SrcVT = V.getValueType();
4450 unsigned NumElems = VT.getVectorNumElements();
4452 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4456 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4457 return (Index == 0) ? V.getOperand(0)
4458 : DAG.getUNDEF(VT.getVectorElementType());
4460 if (V.getOpcode() == ISD::BUILD_VECTOR)
4461 return V.getOperand(Index);
4466 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4467 /// shuffle operation which come from a consecutively from a zero. The
4468 /// search can start in two different directions, from left or right.
4470 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4471 bool ZerosFromLeft, SelectionDAG &DAG) {
4474 while (i < NumElems) {
4475 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4476 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4477 if (!(Elt.getNode() &&
4478 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4486 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4487 /// MaskE correspond consecutively to elements from one of the vector operands,
4488 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4490 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4491 int OpIdx, int NumElems, unsigned &OpNum) {
4492 bool SeenV1 = false;
4493 bool SeenV2 = false;
4495 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4496 int Idx = SVOp->getMaskElt(i);
4497 // Ignore undef indicies
4506 // Only accept consecutive elements from the same vector
4507 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4511 OpNum = SeenV1 ? 0 : 1;
4515 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4516 /// logical left shift of a vector.
4517 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4518 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4519 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4520 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4521 false /* check zeros from right */, DAG);
4527 // Considering the elements in the mask that are not consecutive zeros,
4528 // check if they consecutively come from only one of the source vectors.
4530 // V1 = {X, A, B, C} 0
4532 // vector_shuffle V1, V2 <1, 2, 3, X>
4534 if (!isShuffleMaskConsecutive(SVOp,
4535 0, // Mask Start Index
4536 NumElems-NumZeros-1, // Mask End Index
4537 NumZeros, // Where to start looking in the src vector
4538 NumElems, // Number of elements in vector
4539 OpSrc)) // Which source operand ?
4544 ShVal = SVOp->getOperand(OpSrc);
4548 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4549 /// logical left shift of a vector.
4550 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4551 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4552 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4553 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4554 true /* check zeros from left */, DAG);
4560 // Considering the elements in the mask that are not consecutive zeros,
4561 // check if they consecutively come from only one of the source vectors.
4563 // 0 { A, B, X, X } = V2
4565 // vector_shuffle V1, V2 <X, X, 4, 5>
4567 if (!isShuffleMaskConsecutive(SVOp,
4568 NumZeros, // Mask Start Index
4569 NumElems-1, // Mask End Index
4570 0, // Where to start looking in the src vector
4571 NumElems, // Number of elements in vector
4572 OpSrc)) // Which source operand ?
4577 ShVal = SVOp->getOperand(OpSrc);
4581 /// isVectorShift - Returns true if the shuffle can be implemented as a
4582 /// logical left or right shift of a vector.
4583 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4584 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4585 // Although the logic below support any bitwidth size, there are no
4586 // shift instructions which handle more than 128-bit vectors.
4587 if (SVOp->getValueType(0).getSizeInBits() > 128)
4590 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4591 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4597 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4599 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4600 unsigned NumNonZero, unsigned NumZero,
4602 const X86Subtarget* Subtarget,
4603 const TargetLowering &TLI) {
4607 DebugLoc dl = Op.getDebugLoc();
4610 for (unsigned i = 0; i < 16; ++i) {
4611 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4612 if (ThisIsNonZero && First) {
4614 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4616 V = DAG.getUNDEF(MVT::v8i16);
4621 SDValue ThisElt(0, 0), LastElt(0, 0);
4622 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4623 if (LastIsNonZero) {
4624 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4625 MVT::i16, Op.getOperand(i-1));
4627 if (ThisIsNonZero) {
4628 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4629 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4630 ThisElt, DAG.getConstant(8, MVT::i8));
4632 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4636 if (ThisElt.getNode())
4637 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4638 DAG.getIntPtrConstant(i/2));
4642 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4645 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4647 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4648 unsigned NumNonZero, unsigned NumZero,
4650 const X86Subtarget* Subtarget,
4651 const TargetLowering &TLI) {
4655 DebugLoc dl = Op.getDebugLoc();
4658 for (unsigned i = 0; i < 8; ++i) {
4659 bool isNonZero = (NonZeros & (1 << i)) != 0;
4663 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4665 V = DAG.getUNDEF(MVT::v8i16);
4668 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4669 MVT::v8i16, V, Op.getOperand(i),
4670 DAG.getIntPtrConstant(i));
4677 /// getVShift - Return a vector logical shift node.
4679 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4680 unsigned NumBits, SelectionDAG &DAG,
4681 const TargetLowering &TLI, DebugLoc dl) {
4682 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4683 EVT ShVT = MVT::v2i64;
4684 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4685 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4686 return DAG.getNode(ISD::BITCAST, dl, VT,
4687 DAG.getNode(Opc, dl, ShVT, SrcOp,
4688 DAG.getConstant(NumBits,
4689 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4693 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4694 SelectionDAG &DAG) const {
4696 // Check if the scalar load can be widened into a vector load. And if
4697 // the address is "base + cst" see if the cst can be "absorbed" into
4698 // the shuffle mask.
4699 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4700 SDValue Ptr = LD->getBasePtr();
4701 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4703 EVT PVT = LD->getValueType(0);
4704 if (PVT != MVT::i32 && PVT != MVT::f32)
4709 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4710 FI = FINode->getIndex();
4712 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4713 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4714 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4715 Offset = Ptr.getConstantOperandVal(1);
4716 Ptr = Ptr.getOperand(0);
4721 // FIXME: 256-bit vector instructions don't require a strict alignment,
4722 // improve this code to support it better.
4723 unsigned RequiredAlign = VT.getSizeInBits()/8;
4724 SDValue Chain = LD->getChain();
4725 // Make sure the stack object alignment is at least 16 or 32.
4726 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4727 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4728 if (MFI->isFixedObjectIndex(FI)) {
4729 // Can't change the alignment. FIXME: It's possible to compute
4730 // the exact stack offset and reference FI + adjust offset instead.
4731 // If someone *really* cares about this. That's the way to implement it.
4734 MFI->setObjectAlignment(FI, RequiredAlign);
4738 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4739 // Ptr + (Offset & ~15).
4742 if ((Offset % RequiredAlign) & 3)
4744 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4746 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4747 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4749 int EltNo = (Offset - StartOffset) >> 2;
4750 int NumElems = VT.getVectorNumElements();
4752 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4753 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4754 LD->getPointerInfo().getWithOffset(StartOffset),
4755 false, false, false, 0);
4757 SmallVector<int, 8> Mask;
4758 for (int i = 0; i < NumElems; ++i)
4759 Mask.push_back(EltNo);
4761 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4767 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4768 /// vector of type 'VT', see if the elements can be replaced by a single large
4769 /// load which has the same value as a build_vector whose operands are 'elts'.
4771 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4773 /// FIXME: we'd also like to handle the case where the last elements are zero
4774 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4775 /// There's even a handy isZeroNode for that purpose.
4776 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4777 DebugLoc &DL, SelectionDAG &DAG) {
4778 EVT EltVT = VT.getVectorElementType();
4779 unsigned NumElems = Elts.size();
4781 LoadSDNode *LDBase = NULL;
4782 unsigned LastLoadedElt = -1U;
4784 // For each element in the initializer, see if we've found a load or an undef.
4785 // If we don't find an initial load element, or later load elements are
4786 // non-consecutive, bail out.
4787 for (unsigned i = 0; i < NumElems; ++i) {
4788 SDValue Elt = Elts[i];
4790 if (!Elt.getNode() ||
4791 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4794 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4796 LDBase = cast<LoadSDNode>(Elt.getNode());
4800 if (Elt.getOpcode() == ISD::UNDEF)
4803 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4804 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4809 // If we have found an entire vector of loads and undefs, then return a large
4810 // load of the entire vector width starting at the base pointer. If we found
4811 // consecutive loads for the low half, generate a vzext_load node.
4812 if (LastLoadedElt == NumElems - 1) {
4813 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4814 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4815 LDBase->getPointerInfo(),
4816 LDBase->isVolatile(), LDBase->isNonTemporal(),
4817 LDBase->isInvariant(), 0);
4818 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4819 LDBase->getPointerInfo(),
4820 LDBase->isVolatile(), LDBase->isNonTemporal(),
4821 LDBase->isInvariant(), LDBase->getAlignment());
4822 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4823 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4824 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4825 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4827 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4828 LDBase->getPointerInfo(),
4829 LDBase->getAlignment(),
4830 false/*isVolatile*/, true/*ReadMem*/,
4832 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4837 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4838 /// a vbroadcast node. We support two patterns:
4839 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4840 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4842 /// The scalar load node is returned when a pattern is found,
4843 /// or SDValue() otherwise.
4844 static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) {
4845 if (!Subtarget->hasAVX())
4848 EVT VT = Op.getValueType();
4851 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4852 V = V.getOperand(0);
4854 //A suspected load to be broadcasted.
4857 switch (V.getOpcode()) {
4859 // Unknown pattern found.
4862 case ISD::BUILD_VECTOR: {
4863 // The BUILD_VECTOR node must be a splat.
4864 if (!isSplatVector(V.getNode()))
4867 Ld = V.getOperand(0);
4869 // The suspected load node has several users. Make sure that all
4870 // of its users are from the BUILD_VECTOR node.
4871 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4876 case ISD::VECTOR_SHUFFLE: {
4877 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4879 // Shuffles must have a splat mask where the first element is
4881 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4884 SDValue Sc = Op.getOperand(0);
4885 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4888 Ld = Sc.getOperand(0);
4890 // The scalar_to_vector node and the suspected
4891 // load node must have exactly one user.
4892 if (!Sc.hasOneUse() || !Ld.hasOneUse())
4898 // The scalar source must be a normal load.
4899 if (!ISD::isNormalLoad(Ld.getNode()))
4902 // Reject loads that have uses of the chain result
4903 if (Ld->hasAnyUseOfValue(1))
4906 bool Is256 = VT.getSizeInBits() == 256;
4907 bool Is128 = VT.getSizeInBits() == 128;
4908 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4910 // VBroadcast to YMM
4911 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
4914 // VBroadcast to XMM
4915 if (Is128 && (ScalarSize == 32))
4918 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
4919 // double since there is vbroadcastsd xmm
4920 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
4921 // VBroadcast to YMM
4922 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
4925 // VBroadcast to XMM
4926 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
4930 // Unsupported broadcast.
4935 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4936 DebugLoc dl = Op.getDebugLoc();
4938 EVT VT = Op.getValueType();
4939 EVT ExtVT = VT.getVectorElementType();
4940 unsigned NumElems = Op.getNumOperands();
4942 // Vectors containing all zeros can be matched by pxor and xorps later
4943 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
4944 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
4945 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
4946 if (VT == MVT::v4i32 || VT == MVT::v8i32)
4949 return getZeroVector(VT, Subtarget, DAG, dl);
4952 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
4953 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
4954 // vpcmpeqd on 256-bit vectors.
4955 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
4956 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
4959 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
4962 SDValue LD = isVectorBroadcast(Op, Subtarget);
4964 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
4966 unsigned EVTBits = ExtVT.getSizeInBits();
4968 unsigned NumZero = 0;
4969 unsigned NumNonZero = 0;
4970 unsigned NonZeros = 0;
4971 bool IsAllConstants = true;
4972 SmallSet<SDValue, 8> Values;
4973 for (unsigned i = 0; i < NumElems; ++i) {
4974 SDValue Elt = Op.getOperand(i);
4975 if (Elt.getOpcode() == ISD::UNDEF)
4978 if (Elt.getOpcode() != ISD::Constant &&
4979 Elt.getOpcode() != ISD::ConstantFP)
4980 IsAllConstants = false;
4981 if (X86::isZeroNode(Elt))
4984 NonZeros |= (1 << i);
4989 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4990 if (NumNonZero == 0)
4991 return DAG.getUNDEF(VT);
4993 // Special case for single non-zero, non-undef, element.
4994 if (NumNonZero == 1) {
4995 unsigned Idx = CountTrailingZeros_32(NonZeros);
4996 SDValue Item = Op.getOperand(Idx);
4998 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4999 // the value are obviously zero, truncate the value to i32 and do the
5000 // insertion that way. Only do this if the value is non-constant or if the
5001 // value is a constant being inserted into element 0. It is cheaper to do
5002 // a constant pool load than it is to do a movd + shuffle.
5003 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5004 (!IsAllConstants || Idx == 0)) {
5005 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5007 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5008 EVT VecVT = MVT::v4i32;
5009 unsigned VecElts = 4;
5011 // Truncate the value (which may itself be a constant) to i32, and
5012 // convert it to a vector with movd (S2V+shuffle to zero extend).
5013 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5014 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5015 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5017 // Now we have our 32-bit value zero extended in the low element of
5018 // a vector. If Idx != 0, swizzle it into place.
5020 SmallVector<int, 4> Mask;
5021 Mask.push_back(Idx);
5022 for (unsigned i = 1; i != VecElts; ++i)
5024 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5025 DAG.getUNDEF(Item.getValueType()),
5028 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5032 // If we have a constant or non-constant insertion into the low element of
5033 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5034 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5035 // depending on what the source datatype is.
5038 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5040 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5041 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5042 if (VT.getSizeInBits() == 256) {
5043 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5044 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5045 Item, DAG.getIntPtrConstant(0));
5047 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5048 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5049 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5050 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5053 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5054 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5055 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5056 if (VT.getSizeInBits() == 256) {
5057 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5058 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5061 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5062 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5064 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5068 // Is it a vector logical left shift?
5069 if (NumElems == 2 && Idx == 1 &&
5070 X86::isZeroNode(Op.getOperand(0)) &&
5071 !X86::isZeroNode(Op.getOperand(1))) {
5072 unsigned NumBits = VT.getSizeInBits();
5073 return getVShift(true, VT,
5074 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5075 VT, Op.getOperand(1)),
5076 NumBits/2, DAG, *this, dl);
5079 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5082 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5083 // is a non-constant being inserted into an element other than the low one,
5084 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5085 // movd/movss) to move this into the low element, then shuffle it into
5087 if (EVTBits == 32) {
5088 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5090 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5091 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5092 SmallVector<int, 8> MaskVec;
5093 for (unsigned i = 0; i < NumElems; i++)
5094 MaskVec.push_back(i == Idx ? 0 : 1);
5095 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5099 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5100 if (Values.size() == 1) {
5101 if (EVTBits == 32) {
5102 // Instead of a shuffle like this:
5103 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5104 // Check if it's possible to issue this instead.
5105 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5106 unsigned Idx = CountTrailingZeros_32(NonZeros);
5107 SDValue Item = Op.getOperand(Idx);
5108 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5109 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5114 // A vector full of immediates; various special cases are already
5115 // handled, so this is best done with a single constant-pool load.
5119 // For AVX-length vectors, build the individual 128-bit pieces and use
5120 // shuffles to put them in place.
5121 if (VT.getSizeInBits() == 256) {
5122 SmallVector<SDValue, 32> V;
5123 for (unsigned i = 0; i != NumElems; ++i)
5124 V.push_back(Op.getOperand(i));
5126 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5128 // Build both the lower and upper subvector.
5129 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5130 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5133 // Recreate the wider vector with the lower and upper part.
5134 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5135 DAG.getConstant(0, MVT::i32), DAG, dl);
5136 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5140 // Let legalizer expand 2-wide build_vectors.
5141 if (EVTBits == 64) {
5142 if (NumNonZero == 1) {
5143 // One half is zero or undef.
5144 unsigned Idx = CountTrailingZeros_32(NonZeros);
5145 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5146 Op.getOperand(Idx));
5147 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5152 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5153 if (EVTBits == 8 && NumElems == 16) {
5154 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5156 if (V.getNode()) return V;
5159 if (EVTBits == 16 && NumElems == 8) {
5160 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5162 if (V.getNode()) return V;
5165 // If element VT is == 32 bits, turn it into a number of shuffles.
5166 SmallVector<SDValue, 8> V(NumElems);
5167 if (NumElems == 4 && NumZero > 0) {
5168 for (unsigned i = 0; i < 4; ++i) {
5169 bool isZero = !(NonZeros & (1 << i));
5171 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5173 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5176 for (unsigned i = 0; i < 2; ++i) {
5177 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5180 V[i] = V[i*2]; // Must be a zero vector.
5183 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5186 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5189 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5194 bool Reverse1 = (NonZeros & 0x3) == 2;
5195 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5199 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5200 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5202 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5205 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5206 // Check for a build vector of consecutive loads.
5207 for (unsigned i = 0; i < NumElems; ++i)
5208 V[i] = Op.getOperand(i);
5210 // Check for elements which are consecutive loads.
5211 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5215 // For SSE 4.1, use insertps to put the high elements into the low element.
5216 if (getSubtarget()->hasSSE41()) {
5218 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5219 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5221 Result = DAG.getUNDEF(VT);
5223 for (unsigned i = 1; i < NumElems; ++i) {
5224 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5225 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5226 Op.getOperand(i), DAG.getIntPtrConstant(i));
5231 // Otherwise, expand into a number of unpckl*, start by extending each of
5232 // our (non-undef) elements to the full vector width with the element in the
5233 // bottom slot of the vector (which generates no code for SSE).
5234 for (unsigned i = 0; i < NumElems; ++i) {
5235 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5236 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5238 V[i] = DAG.getUNDEF(VT);
5241 // Next, we iteratively mix elements, e.g. for v4f32:
5242 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5243 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5244 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5245 unsigned EltStride = NumElems >> 1;
5246 while (EltStride != 0) {
5247 for (unsigned i = 0; i < EltStride; ++i) {
5248 // If V[i+EltStride] is undef and this is the first round of mixing,
5249 // then it is safe to just drop this shuffle: V[i] is already in the
5250 // right place, the one element (since it's the first round) being
5251 // inserted as undef can be dropped. This isn't safe for successive
5252 // rounds because they will permute elements within both vectors.
5253 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5254 EltStride == NumElems/2)
5257 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5266 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5267 // them in a MMX register. This is better than doing a stack convert.
5268 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5269 DebugLoc dl = Op.getDebugLoc();
5270 EVT ResVT = Op.getValueType();
5272 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5273 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5275 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5276 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5277 InVec = Op.getOperand(1);
5278 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5279 unsigned NumElts = ResVT.getVectorNumElements();
5280 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5281 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5282 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5284 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5285 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5286 Mask[0] = 0; Mask[1] = 2;
5287 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5289 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5292 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5293 // to create 256-bit vectors from two other 128-bit ones.
5294 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5295 DebugLoc dl = Op.getDebugLoc();
5296 EVT ResVT = Op.getValueType();
5298 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5300 SDValue V1 = Op.getOperand(0);
5301 SDValue V2 = Op.getOperand(1);
5302 unsigned NumElems = ResVT.getVectorNumElements();
5304 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5305 DAG.getConstant(0, MVT::i32), DAG, dl);
5306 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5311 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5312 EVT ResVT = Op.getValueType();
5314 assert(Op.getNumOperands() == 2);
5315 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5316 "Unsupported CONCAT_VECTORS for value type");
5318 // We support concatenate two MMX registers and place them in a MMX register.
5319 // This is better than doing a stack convert.
5320 if (ResVT.is128BitVector())
5321 return LowerMMXCONCAT_VECTORS(Op, DAG);
5323 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5324 // from two other 128-bit ones.
5325 return LowerAVXCONCAT_VECTORS(Op, DAG);
5328 // v8i16 shuffles - Prefer shuffles in the following order:
5329 // 1. [all] pshuflw, pshufhw, optional move
5330 // 2. [ssse3] 1 x pshufb
5331 // 3. [ssse3] 2 x pshufb + 1 x por
5332 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5334 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5335 SelectionDAG &DAG) const {
5336 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5337 SDValue V1 = SVOp->getOperand(0);
5338 SDValue V2 = SVOp->getOperand(1);
5339 DebugLoc dl = SVOp->getDebugLoc();
5340 SmallVector<int, 8> MaskVals;
5342 // Determine if more than 1 of the words in each of the low and high quadwords
5343 // of the result come from the same quadword of one of the two inputs. Undef
5344 // mask values count as coming from any quadword, for better codegen.
5345 unsigned LoQuad[] = { 0, 0, 0, 0 };
5346 unsigned HiQuad[] = { 0, 0, 0, 0 };
5347 std::bitset<4> InputQuads;
5348 for (unsigned i = 0; i < 8; ++i) {
5349 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5350 int EltIdx = SVOp->getMaskElt(i);
5351 MaskVals.push_back(EltIdx);
5360 InputQuads.set(EltIdx / 4);
5363 int BestLoQuad = -1;
5364 unsigned MaxQuad = 1;
5365 for (unsigned i = 0; i < 4; ++i) {
5366 if (LoQuad[i] > MaxQuad) {
5368 MaxQuad = LoQuad[i];
5372 int BestHiQuad = -1;
5374 for (unsigned i = 0; i < 4; ++i) {
5375 if (HiQuad[i] > MaxQuad) {
5377 MaxQuad = HiQuad[i];
5381 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5382 // of the two input vectors, shuffle them into one input vector so only a
5383 // single pshufb instruction is necessary. If There are more than 2 input
5384 // quads, disable the next transformation since it does not help SSSE3.
5385 bool V1Used = InputQuads[0] || InputQuads[1];
5386 bool V2Used = InputQuads[2] || InputQuads[3];
5387 if (Subtarget->hasSSSE3()) {
5388 if (InputQuads.count() == 2 && V1Used && V2Used) {
5389 BestLoQuad = InputQuads[0] ? 0 : 1;
5390 BestHiQuad = InputQuads[2] ? 2 : 3;
5392 if (InputQuads.count() > 2) {
5398 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5399 // the shuffle mask. If a quad is scored as -1, that means that it contains
5400 // words from all 4 input quadwords.
5402 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5404 BestLoQuad < 0 ? 0 : BestLoQuad,
5405 BestHiQuad < 0 ? 1 : BestHiQuad
5407 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5408 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5409 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5410 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5412 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5413 // source words for the shuffle, to aid later transformations.
5414 bool AllWordsInNewV = true;
5415 bool InOrder[2] = { true, true };
5416 for (unsigned i = 0; i != 8; ++i) {
5417 int idx = MaskVals[i];
5419 InOrder[i/4] = false;
5420 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5422 AllWordsInNewV = false;
5426 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5427 if (AllWordsInNewV) {
5428 for (int i = 0; i != 8; ++i) {
5429 int idx = MaskVals[i];
5432 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5433 if ((idx != i) && idx < 4)
5435 if ((idx != i) && idx > 3)
5444 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5445 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5446 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5447 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5448 unsigned TargetMask = 0;
5449 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5450 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5451 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5452 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5453 getShufflePSHUFLWImmediate(SVOp);
5454 V1 = NewV.getOperand(0);
5455 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5459 // If we have SSSE3, and all words of the result are from 1 input vector,
5460 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5461 // is present, fall back to case 4.
5462 if (Subtarget->hasSSSE3()) {
5463 SmallVector<SDValue,16> pshufbMask;
5465 // If we have elements from both input vectors, set the high bit of the
5466 // shuffle mask element to zero out elements that come from V2 in the V1
5467 // mask, and elements that come from V1 in the V2 mask, so that the two
5468 // results can be OR'd together.
5469 bool TwoInputs = V1Used && V2Used;
5470 for (unsigned i = 0; i != 8; ++i) {
5471 int EltIdx = MaskVals[i] * 2;
5472 if (TwoInputs && (EltIdx >= 16)) {
5473 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5474 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5477 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5478 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5480 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5481 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5482 DAG.getNode(ISD::BUILD_VECTOR, dl,
5483 MVT::v16i8, &pshufbMask[0], 16));
5485 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5487 // Calculate the shuffle mask for the second input, shuffle it, and
5488 // OR it with the first shuffled input.
5490 for (unsigned i = 0; i != 8; ++i) {
5491 int EltIdx = MaskVals[i] * 2;
5493 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5494 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5497 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5498 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5500 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5501 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5502 DAG.getNode(ISD::BUILD_VECTOR, dl,
5503 MVT::v16i8, &pshufbMask[0], 16));
5504 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5505 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5508 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5509 // and update MaskVals with new element order.
5510 std::bitset<8> InOrder;
5511 if (BestLoQuad >= 0) {
5512 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5513 for (int i = 0; i != 4; ++i) {
5514 int idx = MaskVals[i];
5517 } else if ((idx / 4) == BestLoQuad) {
5522 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5525 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5526 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5527 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5529 getShufflePSHUFLWImmediate(SVOp), DAG);
5533 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5534 // and update MaskVals with the new element order.
5535 if (BestHiQuad >= 0) {
5536 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5537 for (unsigned i = 4; i != 8; ++i) {
5538 int idx = MaskVals[i];
5541 } else if ((idx / 4) == BestHiQuad) {
5542 MaskV[i] = (idx & 3) + 4;
5546 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5549 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5550 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5551 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5553 getShufflePSHUFHWImmediate(SVOp), DAG);
5557 // In case BestHi & BestLo were both -1, which means each quadword has a word
5558 // from each of the four input quadwords, calculate the InOrder bitvector now
5559 // before falling through to the insert/extract cleanup.
5560 if (BestLoQuad == -1 && BestHiQuad == -1) {
5562 for (int i = 0; i != 8; ++i)
5563 if (MaskVals[i] < 0 || MaskVals[i] == i)
5567 // The other elements are put in the right place using pextrw and pinsrw.
5568 for (unsigned i = 0; i != 8; ++i) {
5571 int EltIdx = MaskVals[i];
5574 SDValue ExtOp = (EltIdx < 8)
5575 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5576 DAG.getIntPtrConstant(EltIdx))
5577 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5578 DAG.getIntPtrConstant(EltIdx - 8));
5579 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5580 DAG.getIntPtrConstant(i));
5585 // v16i8 shuffles - Prefer shuffles in the following order:
5586 // 1. [ssse3] 1 x pshufb
5587 // 2. [ssse3] 2 x pshufb + 1 x por
5588 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5590 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5592 const X86TargetLowering &TLI) {
5593 SDValue V1 = SVOp->getOperand(0);
5594 SDValue V2 = SVOp->getOperand(1);
5595 DebugLoc dl = SVOp->getDebugLoc();
5596 ArrayRef<int> MaskVals = SVOp->getMask();
5598 // If we have SSSE3, case 1 is generated when all result bytes come from
5599 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5600 // present, fall back to case 3.
5601 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5604 for (unsigned i = 0; i < 16; ++i) {
5605 int EltIdx = MaskVals[i];
5614 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5615 if (TLI.getSubtarget()->hasSSSE3()) {
5616 SmallVector<SDValue,16> pshufbMask;
5618 // If all result elements are from one input vector, then only translate
5619 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5621 // Otherwise, we have elements from both input vectors, and must zero out
5622 // elements that come from V2 in the first mask, and V1 in the second mask
5623 // so that we can OR them together.
5624 bool TwoInputs = !(V1Only || V2Only);
5625 for (unsigned i = 0; i != 16; ++i) {
5626 int EltIdx = MaskVals[i];
5627 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5628 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5631 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5633 // If all the elements are from V2, assign it to V1 and return after
5634 // building the first pshufb.
5637 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5638 DAG.getNode(ISD::BUILD_VECTOR, dl,
5639 MVT::v16i8, &pshufbMask[0], 16));
5643 // Calculate the shuffle mask for the second input, shuffle it, and
5644 // OR it with the first shuffled input.
5646 for (unsigned i = 0; i != 16; ++i) {
5647 int EltIdx = MaskVals[i];
5649 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5652 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5654 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5655 DAG.getNode(ISD::BUILD_VECTOR, dl,
5656 MVT::v16i8, &pshufbMask[0], 16));
5657 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5660 // No SSSE3 - Calculate in place words and then fix all out of place words
5661 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5662 // the 16 different words that comprise the two doublequadword input vectors.
5663 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5664 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5665 SDValue NewV = V2Only ? V2 : V1;
5666 for (int i = 0; i != 8; ++i) {
5667 int Elt0 = MaskVals[i*2];
5668 int Elt1 = MaskVals[i*2+1];
5670 // This word of the result is all undef, skip it.
5671 if (Elt0 < 0 && Elt1 < 0)
5674 // This word of the result is already in the correct place, skip it.
5675 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5677 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5680 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5681 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5684 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5685 // using a single extract together, load it and store it.
5686 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5687 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5688 DAG.getIntPtrConstant(Elt1 / 2));
5689 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5690 DAG.getIntPtrConstant(i));
5694 // If Elt1 is defined, extract it from the appropriate source. If the
5695 // source byte is not also odd, shift the extracted word left 8 bits
5696 // otherwise clear the bottom 8 bits if we need to do an or.
5698 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5699 DAG.getIntPtrConstant(Elt1 / 2));
5700 if ((Elt1 & 1) == 0)
5701 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5703 TLI.getShiftAmountTy(InsElt.getValueType())));
5705 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5706 DAG.getConstant(0xFF00, MVT::i16));
5708 // If Elt0 is defined, extract it from the appropriate source. If the
5709 // source byte is not also even, shift the extracted word right 8 bits. If
5710 // Elt1 was also defined, OR the extracted values together before
5711 // inserting them in the result.
5713 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5714 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5715 if ((Elt0 & 1) != 0)
5716 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5718 TLI.getShiftAmountTy(InsElt0.getValueType())));
5720 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5721 DAG.getConstant(0x00FF, MVT::i16));
5722 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5725 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5726 DAG.getIntPtrConstant(i));
5728 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5731 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5732 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5733 /// done when every pair / quad of shuffle mask elements point to elements in
5734 /// the right sequence. e.g.
5735 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5737 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5738 SelectionDAG &DAG, DebugLoc dl) {
5739 EVT VT = SVOp->getValueType(0);
5740 SDValue V1 = SVOp->getOperand(0);
5741 SDValue V2 = SVOp->getOperand(1);
5742 unsigned NumElems = VT.getVectorNumElements();
5743 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5745 switch (VT.getSimpleVT().SimpleTy) {
5746 default: llvm_unreachable("Unexpected!");
5747 case MVT::v4f32: NewVT = MVT::v2f64; break;
5748 case MVT::v4i32: NewVT = MVT::v2i64; break;
5749 case MVT::v8i16: NewVT = MVT::v4i32; break;
5750 case MVT::v16i8: NewVT = MVT::v4i32; break;
5753 int Scale = NumElems / NewWidth;
5754 SmallVector<int, 8> MaskVec;
5755 for (unsigned i = 0; i < NumElems; i += Scale) {
5757 for (int j = 0; j < Scale; ++j) {
5758 int EltIdx = SVOp->getMaskElt(i+j);
5762 StartIdx = EltIdx - (EltIdx % Scale);
5763 if (EltIdx != StartIdx + j)
5767 MaskVec.push_back(-1);
5769 MaskVec.push_back(StartIdx / Scale);
5772 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5773 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5774 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5777 /// getVZextMovL - Return a zero-extending vector move low node.
5779 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5780 SDValue SrcOp, SelectionDAG &DAG,
5781 const X86Subtarget *Subtarget, DebugLoc dl) {
5782 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5783 LoadSDNode *LD = NULL;
5784 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5785 LD = dyn_cast<LoadSDNode>(SrcOp);
5787 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5789 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5790 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5791 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5792 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5793 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5795 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5796 return DAG.getNode(ISD::BITCAST, dl, VT,
5797 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5798 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5806 return DAG.getNode(ISD::BITCAST, dl, VT,
5807 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5808 DAG.getNode(ISD::BITCAST, dl,
5812 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5813 /// which could not be matched by any known target speficic shuffle
5815 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5816 EVT VT = SVOp->getValueType(0);
5818 unsigned NumElems = VT.getVectorNumElements();
5819 unsigned NumLaneElems = NumElems / 2;
5821 int MinRange[2][2] = { { static_cast<int>(NumElems),
5822 static_cast<int>(NumElems) },
5823 { static_cast<int>(NumElems),
5824 static_cast<int>(NumElems) } };
5825 int MaxRange[2][2] = { { -1, -1 }, { -1, -1 } };
5827 // Collect used ranges for each source in each lane
5828 for (unsigned l = 0; l < 2; ++l) {
5829 unsigned LaneStart = l*NumLaneElems;
5830 for (unsigned i = 0; i != NumLaneElems; ++i) {
5831 int Idx = SVOp->getMaskElt(i+LaneStart);
5836 if (Idx >= (int)NumElems) {
5841 if (Idx > MaxRange[l][Input])
5842 MaxRange[l][Input] = Idx;
5843 if (Idx < MinRange[l][Input])
5844 MinRange[l][Input] = Idx;
5848 // Make sure each range is 128-bits
5849 int ExtractIdx[2][2] = { { -1, -1 }, { -1, -1 } };
5850 for (unsigned l = 0; l < 2; ++l) {
5851 for (unsigned Input = 0; Input < 2; ++Input) {
5852 if (MinRange[l][Input] == (int)NumElems && MaxRange[l][Input] < 0)
5855 if (MinRange[l][Input] >= 0 && MaxRange[l][Input] < (int)NumLaneElems)
5856 ExtractIdx[l][Input] = 0;
5857 else if (MinRange[l][Input] >= (int)NumLaneElems &&
5858 MaxRange[l][Input] < (int)NumElems)
5859 ExtractIdx[l][Input] = NumLaneElems;
5865 DebugLoc dl = SVOp->getDebugLoc();
5866 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5867 EVT NVT = MVT::getVectorVT(EltVT, NumElems/2);
5870 for (unsigned l = 0; l < 2; ++l) {
5871 for (unsigned Input = 0; Input < 2; ++Input) {
5872 if (ExtractIdx[l][Input] >= 0)
5873 Ops[l][Input] = Extract128BitVector(SVOp->getOperand(Input),
5874 DAG.getConstant(ExtractIdx[l][Input], MVT::i32),
5877 Ops[l][Input] = DAG.getUNDEF(NVT);
5881 // Generate 128-bit shuffles
5882 SmallVector<int, 16> Mask1, Mask2;
5883 for (unsigned i = 0; i != NumLaneElems; ++i) {
5884 int Elt = SVOp->getMaskElt(i);
5885 if (Elt >= (int)NumElems) {
5886 Elt %= NumLaneElems;
5887 Elt += NumLaneElems;
5888 } else if (Elt >= 0) {
5889 Elt %= NumLaneElems;
5891 Mask1.push_back(Elt);
5893 for (unsigned i = NumLaneElems; i != NumElems; ++i) {
5894 int Elt = SVOp->getMaskElt(i);
5895 if (Elt >= (int)NumElems) {
5896 Elt %= NumLaneElems;
5897 Elt += NumLaneElems;
5898 } else if (Elt >= 0) {
5899 Elt %= NumLaneElems;
5901 Mask2.push_back(Elt);
5904 SDValue Shuf1 = DAG.getVectorShuffle(NVT, dl, Ops[0][0], Ops[0][1], &Mask1[0]);
5905 SDValue Shuf2 = DAG.getVectorShuffle(NVT, dl, Ops[1][0], Ops[1][1], &Mask2[0]);
5907 // Concatenate the result back
5908 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shuf1,
5909 DAG.getConstant(0, MVT::i32), DAG, dl);
5910 return Insert128BitVector(V, Shuf2, DAG.getConstant(NumElems/2, MVT::i32),
5914 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5915 /// 4 elements, and match them with several different shuffle types.
5917 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5918 SDValue V1 = SVOp->getOperand(0);
5919 SDValue V2 = SVOp->getOperand(1);
5920 DebugLoc dl = SVOp->getDebugLoc();
5921 EVT VT = SVOp->getValueType(0);
5923 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
5925 std::pair<int, int> Locs[4];
5926 int Mask1[] = { -1, -1, -1, -1 };
5927 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
5931 for (unsigned i = 0; i != 4; ++i) {
5932 int Idx = PermMask[i];
5934 Locs[i] = std::make_pair(-1, -1);
5936 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5938 Locs[i] = std::make_pair(0, NumLo);
5942 Locs[i] = std::make_pair(1, NumHi);
5944 Mask1[2+NumHi] = Idx;
5950 if (NumLo <= 2 && NumHi <= 2) {
5951 // If no more than two elements come from either vector. This can be
5952 // implemented with two shuffles. First shuffle gather the elements.
5953 // The second shuffle, which takes the first shuffle as both of its
5954 // vector operands, put the elements into the right order.
5955 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5957 int Mask2[] = { -1, -1, -1, -1 };
5959 for (unsigned i = 0; i != 4; ++i)
5960 if (Locs[i].first != -1) {
5961 unsigned Idx = (i < 2) ? 0 : 4;
5962 Idx += Locs[i].first * 2 + Locs[i].second;
5966 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
5967 } else if (NumLo == 3 || NumHi == 3) {
5968 // Otherwise, we must have three elements from one vector, call it X, and
5969 // one element from the other, call it Y. First, use a shufps to build an
5970 // intermediate vector with the one element from Y and the element from X
5971 // that will be in the same half in the final destination (the indexes don't
5972 // matter). Then, use a shufps to build the final vector, taking the half
5973 // containing the element from Y from the intermediate, and the other half
5976 // Normalize it so the 3 elements come from V1.
5977 CommuteVectorShuffleMask(PermMask, 4);
5981 // Find the element from V2.
5983 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5984 int Val = PermMask[HiIndex];
5991 Mask1[0] = PermMask[HiIndex];
5993 Mask1[2] = PermMask[HiIndex^1];
5995 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5998 Mask1[0] = PermMask[0];
5999 Mask1[1] = PermMask[1];
6000 Mask1[2] = HiIndex & 1 ? 6 : 4;
6001 Mask1[3] = HiIndex & 1 ? 4 : 6;
6002 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6004 Mask1[0] = HiIndex & 1 ? 2 : 0;
6005 Mask1[1] = HiIndex & 1 ? 0 : 2;
6006 Mask1[2] = PermMask[2];
6007 Mask1[3] = PermMask[3];
6012 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6016 // Break it into (shuffle shuffle_hi, shuffle_lo).
6017 int LoMask[] = { -1, -1, -1, -1 };
6018 int HiMask[] = { -1, -1, -1, -1 };
6020 int *MaskPtr = LoMask;
6021 unsigned MaskIdx = 0;
6024 for (unsigned i = 0; i != 4; ++i) {
6031 int Idx = PermMask[i];
6033 Locs[i] = std::make_pair(-1, -1);
6034 } else if (Idx < 4) {
6035 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6036 MaskPtr[LoIdx] = Idx;
6039 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6040 MaskPtr[HiIdx] = Idx;
6045 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6046 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6047 int MaskOps[] = { -1, -1, -1, -1 };
6048 for (unsigned i = 0; i != 4; ++i)
6049 if (Locs[i].first != -1)
6050 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6051 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6054 static bool MayFoldVectorLoad(SDValue V) {
6055 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6056 V = V.getOperand(0);
6057 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6058 V = V.getOperand(0);
6059 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6060 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6061 // BUILD_VECTOR (load), undef
6062 V = V.getOperand(0);
6068 // FIXME: the version above should always be used. Since there's
6069 // a bug where several vector shuffles can't be folded because the
6070 // DAG is not updated during lowering and a node claims to have two
6071 // uses while it only has one, use this version, and let isel match
6072 // another instruction if the load really happens to have more than
6073 // one use. Remove this version after this bug get fixed.
6074 // rdar://8434668, PR8156
6075 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6076 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6077 V = V.getOperand(0);
6078 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6079 V = V.getOperand(0);
6080 if (ISD::isNormalLoad(V.getNode()))
6085 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6086 /// a vector extract, and if both can be later optimized into a single load.
6087 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6088 /// here because otherwise a target specific shuffle node is going to be
6089 /// emitted for this shuffle, and the optimization not done.
6090 /// FIXME: This is probably not the best approach, but fix the problem
6091 /// until the right path is decided.
6093 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6094 const TargetLowering &TLI) {
6095 EVT VT = V.getValueType();
6096 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6098 // Be sure that the vector shuffle is present in a pattern like this:
6099 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6103 SDNode *N = *V.getNode()->use_begin();
6104 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6107 SDValue EltNo = N->getOperand(1);
6108 if (!isa<ConstantSDNode>(EltNo))
6111 // If the bit convert changed the number of elements, it is unsafe
6112 // to examine the mask.
6113 bool HasShuffleIntoBitcast = false;
6114 if (V.getOpcode() == ISD::BITCAST) {
6115 EVT SrcVT = V.getOperand(0).getValueType();
6116 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6118 V = V.getOperand(0);
6119 HasShuffleIntoBitcast = true;
6122 // Select the input vector, guarding against out of range extract vector.
6123 unsigned NumElems = VT.getVectorNumElements();
6124 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6125 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6126 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6128 // If we are accessing the upper part of a YMM register
6129 // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of
6130 // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point
6131 // because the legalization of N did not happen yet.
6132 if (Idx >= (int)NumElems/2 && VT.getSizeInBits() == 256)
6135 // Skip one more bit_convert if necessary
6136 if (V.getOpcode() == ISD::BITCAST) {
6139 V = V.getOperand(0);
6142 if (!ISD::isNormalLoad(V.getNode()))
6145 // Is the original load suitable?
6146 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6148 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6151 if (!HasShuffleIntoBitcast)
6154 // If there's a bitcast before the shuffle, check if the load type and
6155 // alignment is valid.
6156 unsigned Align = LN0->getAlignment();
6158 TLI.getTargetData()->getABITypeAlignment(
6159 VT.getTypeForEVT(*DAG.getContext()));
6161 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6168 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6169 EVT VT = Op.getValueType();
6171 // Canonizalize to v2f64.
6172 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6173 return DAG.getNode(ISD::BITCAST, dl, VT,
6174 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6179 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6181 SDValue V1 = Op.getOperand(0);
6182 SDValue V2 = Op.getOperand(1);
6183 EVT VT = Op.getValueType();
6185 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6187 if (HasSSE2 && VT == MVT::v2f64)
6188 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6190 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6191 return DAG.getNode(ISD::BITCAST, dl, VT,
6192 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6193 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6194 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6198 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6199 SDValue V1 = Op.getOperand(0);
6200 SDValue V2 = Op.getOperand(1);
6201 EVT VT = Op.getValueType();
6203 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6204 "unsupported shuffle type");
6206 if (V2.getOpcode() == ISD::UNDEF)
6210 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6214 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6215 SDValue V1 = Op.getOperand(0);
6216 SDValue V2 = Op.getOperand(1);
6217 EVT VT = Op.getValueType();
6218 unsigned NumElems = VT.getVectorNumElements();
6220 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6221 // operand of these instructions is only memory, so check if there's a
6222 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6224 bool CanFoldLoad = false;
6226 // Trivial case, when V2 comes from a load.
6227 if (MayFoldVectorLoad(V2))
6230 // When V1 is a load, it can be folded later into a store in isel, example:
6231 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6233 // (MOVLPSmr addr:$src1, VR128:$src2)
6234 // So, recognize this potential and also use MOVLPS or MOVLPD
6235 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6238 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6240 if (HasSSE2 && NumElems == 2)
6241 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6244 // If we don't care about the second element, procede to use movss.
6245 if (SVOp->getMaskElt(1) != -1)
6246 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6249 // movl and movlp will both match v2i64, but v2i64 is never matched by
6250 // movl earlier because we make it strict to avoid messing with the movlp load
6251 // folding logic (see the code above getMOVLP call). Match it here then,
6252 // this is horrible, but will stay like this until we move all shuffle
6253 // matching to x86 specific nodes. Note that for the 1st condition all
6254 // types are matched with movsd.
6256 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6257 // as to remove this logic from here, as much as possible
6258 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6259 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6260 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6263 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6265 // Invert the operand order and use SHUFPS to match it.
6266 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6267 getShuffleSHUFImmediate(SVOp), DAG);
6271 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6272 const TargetLowering &TLI,
6273 const X86Subtarget *Subtarget) {
6274 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6275 EVT VT = Op.getValueType();
6276 DebugLoc dl = Op.getDebugLoc();
6277 SDValue V1 = Op.getOperand(0);
6278 SDValue V2 = Op.getOperand(1);
6280 if (isZeroShuffle(SVOp))
6281 return getZeroVector(VT, Subtarget, DAG, dl);
6283 // Handle splat operations
6284 if (SVOp->isSplat()) {
6285 unsigned NumElem = VT.getVectorNumElements();
6286 int Size = VT.getSizeInBits();
6287 // Special case, this is the only place now where it's allowed to return
6288 // a vector_shuffle operation without using a target specific node, because
6289 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6290 // this be moved to DAGCombine instead?
6291 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6294 // Use vbroadcast whenever the splat comes from a foldable load
6295 SDValue LD = isVectorBroadcast(Op, Subtarget);
6297 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6299 // Handle splats by matching through known shuffle masks
6300 if ((Size == 128 && NumElem <= 4) ||
6301 (Size == 256 && NumElem < 8))
6304 // All remaning splats are promoted to target supported vector shuffles.
6305 return PromoteSplat(SVOp, DAG);
6308 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6310 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6311 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6312 if (NewOp.getNode())
6313 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6314 } else if ((VT == MVT::v4i32 ||
6315 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6316 // FIXME: Figure out a cleaner way to do this.
6317 // Try to make use of movq to zero out the top part.
6318 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6319 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6320 if (NewOp.getNode()) {
6321 EVT NewVT = NewOp.getValueType();
6322 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6323 NewVT, true, false))
6324 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6325 DAG, Subtarget, dl);
6327 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6328 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6329 if (NewOp.getNode()) {
6330 EVT NewVT = NewOp.getValueType();
6331 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6332 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6333 DAG, Subtarget, dl);
6341 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6342 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6343 SDValue V1 = Op.getOperand(0);
6344 SDValue V2 = Op.getOperand(1);
6345 EVT VT = Op.getValueType();
6346 DebugLoc dl = Op.getDebugLoc();
6347 unsigned NumElems = VT.getVectorNumElements();
6348 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6349 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6350 bool V1IsSplat = false;
6351 bool V2IsSplat = false;
6352 bool HasSSE2 = Subtarget->hasSSE2();
6353 bool HasAVX = Subtarget->hasAVX();
6354 bool HasAVX2 = Subtarget->hasAVX2();
6355 MachineFunction &MF = DAG.getMachineFunction();
6356 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6358 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6360 if (V1IsUndef && V2IsUndef)
6361 return DAG.getUNDEF(VT);
6363 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6365 // Vector shuffle lowering takes 3 steps:
6367 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6368 // narrowing and commutation of operands should be handled.
6369 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6371 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6372 // so the shuffle can be broken into other shuffles and the legalizer can
6373 // try the lowering again.
6375 // The general idea is that no vector_shuffle operation should be left to
6376 // be matched during isel, all of them must be converted to a target specific
6379 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6380 // narrowing and commutation of operands should be handled. The actual code
6381 // doesn't include all of those, work in progress...
6382 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6383 if (NewOp.getNode())
6386 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6388 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6389 // unpckh_undef). Only use pshufd if speed is more important than size.
6390 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6391 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6392 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6393 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6395 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6396 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6397 return getMOVDDup(Op, dl, V1, DAG);
6399 if (isMOVHLPS_v_undef_Mask(M, VT))
6400 return getMOVHighToLow(Op, dl, DAG);
6402 // Use to match splats
6403 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6404 (VT == MVT::v2f64 || VT == MVT::v2i64))
6405 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6407 if (isPSHUFDMask(M, VT)) {
6408 // The actual implementation will match the mask in the if above and then
6409 // during isel it can match several different instructions, not only pshufd
6410 // as its name says, sad but true, emulate the behavior for now...
6411 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6412 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6414 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6416 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6417 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6419 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6420 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6422 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6426 // Check if this can be converted into a logical shift.
6427 bool isLeft = false;
6430 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6431 if (isShift && ShVal.hasOneUse()) {
6432 // If the shifted value has multiple uses, it may be cheaper to use
6433 // v_set0 + movlhps or movhlps, etc.
6434 EVT EltVT = VT.getVectorElementType();
6435 ShAmt *= EltVT.getSizeInBits();
6436 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6439 if (isMOVLMask(M, VT)) {
6440 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6441 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6442 if (!isMOVLPMask(M, VT)) {
6443 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6444 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6446 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6447 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6451 // FIXME: fold these into legal mask.
6452 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6453 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6455 if (isMOVHLPSMask(M, VT))
6456 return getMOVHighToLow(Op, dl, DAG);
6458 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6459 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6461 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6462 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6464 if (isMOVLPMask(M, VT))
6465 return getMOVLP(Op, dl, DAG, HasSSE2);
6467 if (ShouldXformToMOVHLPS(M, VT) ||
6468 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6469 return CommuteVectorShuffle(SVOp, DAG);
6472 // No better options. Use a vshldq / vsrldq.
6473 EVT EltVT = VT.getVectorElementType();
6474 ShAmt *= EltVT.getSizeInBits();
6475 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6478 bool Commuted = false;
6479 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6480 // 1,1,1,1 -> v8i16 though.
6481 V1IsSplat = isSplatVector(V1.getNode());
6482 V2IsSplat = isSplatVector(V2.getNode());
6484 // Canonicalize the splat or undef, if present, to be on the RHS.
6485 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6486 CommuteVectorShuffleMask(M, NumElems);
6488 std::swap(V1IsSplat, V2IsSplat);
6492 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6493 // Shuffling low element of v1 into undef, just return v1.
6496 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6497 // the instruction selector will not match, so get a canonical MOVL with
6498 // swapped operands to undo the commute.
6499 return getMOVL(DAG, dl, VT, V2, V1);
6502 if (isUNPCKLMask(M, VT, HasAVX2))
6503 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6505 if (isUNPCKHMask(M, VT, HasAVX2))
6506 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6509 // Normalize mask so all entries that point to V2 points to its first
6510 // element then try to match unpck{h|l} again. If match, return a
6511 // new vector_shuffle with the corrected mask.p
6512 SmallVector<int, 8> NewMask(M.begin(), M.end());
6513 NormalizeMask(NewMask, NumElems);
6514 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) {
6515 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6516 } else if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) {
6517 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6522 // Commute is back and try unpck* again.
6523 // FIXME: this seems wrong.
6524 CommuteVectorShuffleMask(M, NumElems);
6526 std::swap(V1IsSplat, V2IsSplat);
6529 if (isUNPCKLMask(M, VT, HasAVX2))
6530 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6532 if (isUNPCKHMask(M, VT, HasAVX2))
6533 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6536 // Normalize the node to match x86 shuffle ops if needed
6537 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6538 return CommuteVectorShuffle(SVOp, DAG);
6540 // The checks below are all present in isShuffleMaskLegal, but they are
6541 // inlined here right now to enable us to directly emit target specific
6542 // nodes, and remove one by one until they don't return Op anymore.
6544 if (isPALIGNRMask(M, VT, Subtarget))
6545 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6546 getShufflePALIGNRImmediate(SVOp),
6549 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6550 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6551 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6552 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6555 if (isPSHUFHWMask(M, VT))
6556 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6557 getShufflePSHUFHWImmediate(SVOp),
6560 if (isPSHUFLWMask(M, VT))
6561 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6562 getShufflePSHUFLWImmediate(SVOp),
6565 if (isSHUFPMask(M, VT, HasAVX))
6566 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6567 getShuffleSHUFImmediate(SVOp), DAG);
6569 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6570 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6571 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6572 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6574 //===--------------------------------------------------------------------===//
6575 // Generate target specific nodes for 128 or 256-bit shuffles only
6576 // supported in the AVX instruction set.
6579 // Handle VMOVDDUPY permutations
6580 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6581 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6583 // Handle VPERMILPS/D* permutations
6584 if (isVPERMILPMask(M, VT, HasAVX)) {
6585 if (HasAVX2 && VT == MVT::v8i32)
6586 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6587 getShuffleSHUFImmediate(SVOp), DAG);
6588 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6589 getShuffleSHUFImmediate(SVOp), DAG);
6592 // Handle VPERM2F128/VPERM2I128 permutations
6593 if (isVPERM2X128Mask(M, VT, HasAVX))
6594 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6595 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6597 //===--------------------------------------------------------------------===//
6598 // Since no target specific shuffle was selected for this generic one,
6599 // lower it into other known shuffles. FIXME: this isn't true yet, but
6600 // this is the plan.
6603 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6604 if (VT == MVT::v8i16) {
6605 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6606 if (NewOp.getNode())
6610 if (VT == MVT::v16i8) {
6611 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6612 if (NewOp.getNode())
6616 // Handle all 128-bit wide vectors with 4 elements, and match them with
6617 // several different shuffle types.
6618 if (NumElems == 4 && VT.getSizeInBits() == 128)
6619 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6621 // Handle general 256-bit shuffles
6622 if (VT.is256BitVector())
6623 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6629 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6630 SelectionDAG &DAG) const {
6631 EVT VT = Op.getValueType();
6632 DebugLoc dl = Op.getDebugLoc();
6634 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6637 if (VT.getSizeInBits() == 8) {
6638 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6639 Op.getOperand(0), Op.getOperand(1));
6640 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6641 DAG.getValueType(VT));
6642 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6643 } else if (VT.getSizeInBits() == 16) {
6644 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6645 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6647 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6648 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6649 DAG.getNode(ISD::BITCAST, dl,
6653 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6654 Op.getOperand(0), Op.getOperand(1));
6655 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6656 DAG.getValueType(VT));
6657 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6658 } else if (VT == MVT::f32) {
6659 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6660 // the result back to FR32 register. It's only worth matching if the
6661 // result has a single use which is a store or a bitcast to i32. And in
6662 // the case of a store, it's not worth it if the index is a constant 0,
6663 // because a MOVSSmr can be used instead, which is smaller and faster.
6664 if (!Op.hasOneUse())
6666 SDNode *User = *Op.getNode()->use_begin();
6667 if ((User->getOpcode() != ISD::STORE ||
6668 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6669 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6670 (User->getOpcode() != ISD::BITCAST ||
6671 User->getValueType(0) != MVT::i32))
6673 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6674 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6677 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6678 } else if (VT == MVT::i32 || VT == MVT::i64) {
6679 // ExtractPS/pextrq works with constant index.
6680 if (isa<ConstantSDNode>(Op.getOperand(1)))
6688 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6689 SelectionDAG &DAG) const {
6690 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6693 SDValue Vec = Op.getOperand(0);
6694 EVT VecVT = Vec.getValueType();
6696 // If this is a 256-bit vector result, first extract the 128-bit vector and
6697 // then extract the element from the 128-bit vector.
6698 if (VecVT.getSizeInBits() == 256) {
6699 DebugLoc dl = Op.getNode()->getDebugLoc();
6700 unsigned NumElems = VecVT.getVectorNumElements();
6701 SDValue Idx = Op.getOperand(1);
6702 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6704 // Get the 128-bit vector.
6705 bool Upper = IdxVal >= NumElems/2;
6706 Vec = Extract128BitVector(Vec,
6707 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6709 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6710 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6713 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6715 if (Subtarget->hasSSE41()) {
6716 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6721 EVT VT = Op.getValueType();
6722 DebugLoc dl = Op.getDebugLoc();
6723 // TODO: handle v16i8.
6724 if (VT.getSizeInBits() == 16) {
6725 SDValue Vec = Op.getOperand(0);
6726 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6728 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6729 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6730 DAG.getNode(ISD::BITCAST, dl,
6733 // Transform it so it match pextrw which produces a 32-bit result.
6734 EVT EltVT = MVT::i32;
6735 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6736 Op.getOperand(0), Op.getOperand(1));
6737 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6738 DAG.getValueType(VT));
6739 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6740 } else if (VT.getSizeInBits() == 32) {
6741 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6745 // SHUFPS the element to the lowest double word, then movss.
6746 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6747 EVT VVT = Op.getOperand(0).getValueType();
6748 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6749 DAG.getUNDEF(VVT), Mask);
6750 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6751 DAG.getIntPtrConstant(0));
6752 } else if (VT.getSizeInBits() == 64) {
6753 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6754 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6755 // to match extract_elt for f64.
6756 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6760 // UNPCKHPD the element to the lowest double word, then movsd.
6761 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6762 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6763 int Mask[2] = { 1, -1 };
6764 EVT VVT = Op.getOperand(0).getValueType();
6765 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6766 DAG.getUNDEF(VVT), Mask);
6767 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6768 DAG.getIntPtrConstant(0));
6775 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6776 SelectionDAG &DAG) const {
6777 EVT VT = Op.getValueType();
6778 EVT EltVT = VT.getVectorElementType();
6779 DebugLoc dl = Op.getDebugLoc();
6781 SDValue N0 = Op.getOperand(0);
6782 SDValue N1 = Op.getOperand(1);
6783 SDValue N2 = Op.getOperand(2);
6785 if (VT.getSizeInBits() == 256)
6788 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6789 isa<ConstantSDNode>(N2)) {
6791 if (VT == MVT::v8i16)
6792 Opc = X86ISD::PINSRW;
6793 else if (VT == MVT::v16i8)
6794 Opc = X86ISD::PINSRB;
6796 Opc = X86ISD::PINSRB;
6798 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6800 if (N1.getValueType() != MVT::i32)
6801 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6802 if (N2.getValueType() != MVT::i32)
6803 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6804 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6805 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6806 // Bits [7:6] of the constant are the source select. This will always be
6807 // zero here. The DAG Combiner may combine an extract_elt index into these
6808 // bits. For example (insert (extract, 3), 2) could be matched by putting
6809 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6810 // Bits [5:4] of the constant are the destination select. This is the
6811 // value of the incoming immediate.
6812 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6813 // combine either bitwise AND or insert of float 0.0 to set these bits.
6814 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6815 // Create this as a scalar to vector..
6816 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6817 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6818 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6819 isa<ConstantSDNode>(N2)) {
6820 // PINSR* works with constant index.
6827 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6828 EVT VT = Op.getValueType();
6829 EVT EltVT = VT.getVectorElementType();
6831 DebugLoc dl = Op.getDebugLoc();
6832 SDValue N0 = Op.getOperand(0);
6833 SDValue N1 = Op.getOperand(1);
6834 SDValue N2 = Op.getOperand(2);
6836 // If this is a 256-bit vector result, first extract the 128-bit vector,
6837 // insert the element into the extracted half and then place it back.
6838 if (VT.getSizeInBits() == 256) {
6839 if (!isa<ConstantSDNode>(N2))
6842 // Get the desired 128-bit vector half.
6843 unsigned NumElems = VT.getVectorNumElements();
6844 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6845 bool Upper = IdxVal >= NumElems/2;
6846 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6847 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6849 // Insert the element into the desired half.
6850 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6851 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6853 // Insert the changed part back to the 256-bit vector
6854 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6857 if (Subtarget->hasSSE41())
6858 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6860 if (EltVT == MVT::i8)
6863 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6864 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6865 // as its second argument.
6866 if (N1.getValueType() != MVT::i32)
6867 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6868 if (N2.getValueType() != MVT::i32)
6869 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6870 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6876 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6877 LLVMContext *Context = DAG.getContext();
6878 DebugLoc dl = Op.getDebugLoc();
6879 EVT OpVT = Op.getValueType();
6881 // If this is a 256-bit vector result, first insert into a 128-bit
6882 // vector and then insert into the 256-bit vector.
6883 if (OpVT.getSizeInBits() > 128) {
6884 // Insert into a 128-bit vector.
6885 EVT VT128 = EVT::getVectorVT(*Context,
6886 OpVT.getVectorElementType(),
6887 OpVT.getVectorNumElements() / 2);
6889 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6891 // Insert the 128-bit vector.
6892 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6893 DAG.getConstant(0, MVT::i32),
6897 if (Op.getValueType() == MVT::v1i64 &&
6898 Op.getOperand(0).getValueType() == MVT::i64)
6899 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6901 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6902 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6903 "Expected an SSE type!");
6904 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6905 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6908 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6909 // a simple subregister reference or explicit instructions to grab
6910 // upper bits of a vector.
6912 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6913 if (Subtarget->hasAVX()) {
6914 DebugLoc dl = Op.getNode()->getDebugLoc();
6915 SDValue Vec = Op.getNode()->getOperand(0);
6916 SDValue Idx = Op.getNode()->getOperand(1);
6918 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
6919 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
6920 return Extract128BitVector(Vec, Idx, DAG, dl);
6926 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6927 // simple superregister reference or explicit instructions to insert
6928 // the upper bits of a vector.
6930 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6931 if (Subtarget->hasAVX()) {
6932 DebugLoc dl = Op.getNode()->getDebugLoc();
6933 SDValue Vec = Op.getNode()->getOperand(0);
6934 SDValue SubVec = Op.getNode()->getOperand(1);
6935 SDValue Idx = Op.getNode()->getOperand(2);
6937 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
6938 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
6939 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
6945 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
6946 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
6947 // one of the above mentioned nodes. It has to be wrapped because otherwise
6948 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
6949 // be used to form addressing mode. These wrapped nodes will be selected
6952 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
6953 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
6955 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6957 unsigned char OpFlag = 0;
6958 unsigned WrapperKind = X86ISD::Wrapper;
6959 CodeModel::Model M = getTargetMachine().getCodeModel();
6961 if (Subtarget->isPICStyleRIPRel() &&
6962 (M == CodeModel::Small || M == CodeModel::Kernel))
6963 WrapperKind = X86ISD::WrapperRIP;
6964 else if (Subtarget->isPICStyleGOT())
6965 OpFlag = X86II::MO_GOTOFF;
6966 else if (Subtarget->isPICStyleStubPIC())
6967 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6969 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
6971 CP->getOffset(), OpFlag);
6972 DebugLoc DL = CP->getDebugLoc();
6973 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6974 // With PIC, the address is actually $g + Offset.
6976 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6977 DAG.getNode(X86ISD::GlobalBaseReg,
6978 DebugLoc(), getPointerTy()),
6985 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
6986 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
6988 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6990 unsigned char OpFlag = 0;
6991 unsigned WrapperKind = X86ISD::Wrapper;
6992 CodeModel::Model M = getTargetMachine().getCodeModel();
6994 if (Subtarget->isPICStyleRIPRel() &&
6995 (M == CodeModel::Small || M == CodeModel::Kernel))
6996 WrapperKind = X86ISD::WrapperRIP;
6997 else if (Subtarget->isPICStyleGOT())
6998 OpFlag = X86II::MO_GOTOFF;
6999 else if (Subtarget->isPICStyleStubPIC())
7000 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7002 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7004 DebugLoc DL = JT->getDebugLoc();
7005 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7007 // With PIC, the address is actually $g + Offset.
7009 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7010 DAG.getNode(X86ISD::GlobalBaseReg,
7011 DebugLoc(), getPointerTy()),
7018 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7019 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7021 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7023 unsigned char OpFlag = 0;
7024 unsigned WrapperKind = X86ISD::Wrapper;
7025 CodeModel::Model M = getTargetMachine().getCodeModel();
7027 if (Subtarget->isPICStyleRIPRel() &&
7028 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7029 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7030 OpFlag = X86II::MO_GOTPCREL;
7031 WrapperKind = X86ISD::WrapperRIP;
7032 } else if (Subtarget->isPICStyleGOT()) {
7033 OpFlag = X86II::MO_GOT;
7034 } else if (Subtarget->isPICStyleStubPIC()) {
7035 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7036 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7037 OpFlag = X86II::MO_DARWIN_NONLAZY;
7040 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7042 DebugLoc DL = Op.getDebugLoc();
7043 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7046 // With PIC, the address is actually $g + Offset.
7047 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7048 !Subtarget->is64Bit()) {
7049 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7050 DAG.getNode(X86ISD::GlobalBaseReg,
7051 DebugLoc(), getPointerTy()),
7055 // For symbols that require a load from a stub to get the address, emit the
7057 if (isGlobalStubReference(OpFlag))
7058 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7059 MachinePointerInfo::getGOT(), false, false, false, 0);
7065 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7066 // Create the TargetBlockAddressAddress node.
7067 unsigned char OpFlags =
7068 Subtarget->ClassifyBlockAddressReference();
7069 CodeModel::Model M = getTargetMachine().getCodeModel();
7070 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7071 DebugLoc dl = Op.getDebugLoc();
7072 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7073 /*isTarget=*/true, OpFlags);
7075 if (Subtarget->isPICStyleRIPRel() &&
7076 (M == CodeModel::Small || M == CodeModel::Kernel))
7077 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7079 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7081 // With PIC, the address is actually $g + Offset.
7082 if (isGlobalRelativeToPICBase(OpFlags)) {
7083 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7084 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7092 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7094 SelectionDAG &DAG) const {
7095 // Create the TargetGlobalAddress node, folding in the constant
7096 // offset if it is legal.
7097 unsigned char OpFlags =
7098 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7099 CodeModel::Model M = getTargetMachine().getCodeModel();
7101 if (OpFlags == X86II::MO_NO_FLAG &&
7102 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7103 // A direct static reference to a global.
7104 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7107 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7110 if (Subtarget->isPICStyleRIPRel() &&
7111 (M == CodeModel::Small || M == CodeModel::Kernel))
7112 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7114 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7116 // With PIC, the address is actually $g + Offset.
7117 if (isGlobalRelativeToPICBase(OpFlags)) {
7118 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7119 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7123 // For globals that require a load from a stub to get the address, emit the
7125 if (isGlobalStubReference(OpFlags))
7126 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7127 MachinePointerInfo::getGOT(), false, false, false, 0);
7129 // If there was a non-zero offset that we didn't fold, create an explicit
7132 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7133 DAG.getConstant(Offset, getPointerTy()));
7139 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7140 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7141 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7142 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7146 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7147 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7148 unsigned char OperandFlags) {
7149 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7150 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7151 DebugLoc dl = GA->getDebugLoc();
7152 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7153 GA->getValueType(0),
7157 SDValue Ops[] = { Chain, TGA, *InFlag };
7158 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7160 SDValue Ops[] = { Chain, TGA };
7161 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7164 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7165 MFI->setAdjustsStack(true);
7167 SDValue Flag = Chain.getValue(1);
7168 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7171 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7173 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7176 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7177 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7178 DAG.getNode(X86ISD::GlobalBaseReg,
7179 DebugLoc(), PtrVT), InFlag);
7180 InFlag = Chain.getValue(1);
7182 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7185 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7187 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7189 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7190 X86::RAX, X86II::MO_TLSGD);
7193 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7194 // "local exec" model.
7195 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7196 const EVT PtrVT, TLSModel::Model model,
7198 DebugLoc dl = GA->getDebugLoc();
7200 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7201 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7202 is64Bit ? 257 : 256));
7204 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7205 DAG.getIntPtrConstant(0),
7206 MachinePointerInfo(Ptr),
7207 false, false, false, 0);
7209 unsigned char OperandFlags = 0;
7210 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7212 unsigned WrapperKind = X86ISD::Wrapper;
7213 if (model == TLSModel::LocalExec) {
7214 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7215 } else if (is64Bit) {
7216 assert(model == TLSModel::InitialExec);
7217 OperandFlags = X86II::MO_GOTTPOFF;
7218 WrapperKind = X86ISD::WrapperRIP;
7220 assert(model == TLSModel::InitialExec);
7221 OperandFlags = X86II::MO_INDNTPOFF;
7224 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7226 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7227 GA->getValueType(0),
7228 GA->getOffset(), OperandFlags);
7229 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7231 if (model == TLSModel::InitialExec)
7232 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7233 MachinePointerInfo::getGOT(), false, false, false, 0);
7235 // The address of the thread local variable is the add of the thread
7236 // pointer with the offset of the variable.
7237 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7241 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7243 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7244 const GlobalValue *GV = GA->getGlobal();
7246 if (Subtarget->isTargetELF()) {
7247 // TODO: implement the "local dynamic" model
7248 // TODO: implement the "initial exec"model for pic executables
7250 // If GV is an alias then use the aliasee for determining
7251 // thread-localness.
7252 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7253 GV = GA->resolveAliasedGlobal(false);
7255 TLSModel::Model model
7256 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7259 case TLSModel::GeneralDynamic:
7260 case TLSModel::LocalDynamic: // not implemented
7261 if (Subtarget->is64Bit())
7262 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7263 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7265 case TLSModel::InitialExec:
7266 case TLSModel::LocalExec:
7267 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7268 Subtarget->is64Bit());
7270 } else if (Subtarget->isTargetDarwin()) {
7271 // Darwin only has one model of TLS. Lower to that.
7272 unsigned char OpFlag = 0;
7273 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7274 X86ISD::WrapperRIP : X86ISD::Wrapper;
7276 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7278 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7279 !Subtarget->is64Bit();
7281 OpFlag = X86II::MO_TLVP_PIC_BASE;
7283 OpFlag = X86II::MO_TLVP;
7284 DebugLoc DL = Op.getDebugLoc();
7285 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7286 GA->getValueType(0),
7287 GA->getOffset(), OpFlag);
7288 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7290 // With PIC32, the address is actually $g + Offset.
7292 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7293 DAG.getNode(X86ISD::GlobalBaseReg,
7294 DebugLoc(), getPointerTy()),
7297 // Lowering the machine isd will make sure everything is in the right
7299 SDValue Chain = DAG.getEntryNode();
7300 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7301 SDValue Args[] = { Chain, Offset };
7302 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7304 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7305 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7306 MFI->setAdjustsStack(true);
7308 // And our return value (tls address) is in the standard call return value
7310 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7311 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7313 } else if (Subtarget->isTargetWindows()) {
7314 // Just use the implicit TLS architecture
7315 // Need to generate someting similar to:
7316 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7318 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7319 // mov rcx, qword [rdx+rcx*8]
7320 // mov eax, .tls$:tlsvar
7321 // [rax+rcx] contains the address
7322 // Windows 64bit: gs:0x58
7323 // Windows 32bit: fs:__tls_array
7325 // If GV is an alias then use the aliasee for determining
7326 // thread-localness.
7327 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7328 GV = GA->resolveAliasedGlobal(false);
7329 DebugLoc dl = GA->getDebugLoc();
7330 SDValue Chain = DAG.getEntryNode();
7332 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7333 // %gs:0x58 (64-bit).
7334 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7335 ? Type::getInt8PtrTy(*DAG.getContext(),
7337 : Type::getInt32PtrTy(*DAG.getContext(),
7340 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7341 Subtarget->is64Bit()
7342 ? DAG.getIntPtrConstant(0x58)
7343 : DAG.getExternalSymbol("_tls_array",
7345 MachinePointerInfo(Ptr),
7346 false, false, false, 0);
7348 // Load the _tls_index variable
7349 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7350 if (Subtarget->is64Bit())
7351 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7352 IDX, MachinePointerInfo(), MVT::i32,
7355 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7356 false, false, false, 0);
7358 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7360 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7362 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7363 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7364 false, false, false, 0);
7366 // Get the offset of start of .tls section
7367 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7368 GA->getValueType(0),
7369 GA->getOffset(), X86II::MO_SECREL);
7370 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7372 // The address of the thread local variable is the add of the thread
7373 // pointer with the offset of the variable.
7374 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7377 llvm_unreachable("TLS not implemented for this target.");
7381 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7382 /// and take a 2 x i32 value to shift plus a shift amount.
7383 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7384 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7385 EVT VT = Op.getValueType();
7386 unsigned VTBits = VT.getSizeInBits();
7387 DebugLoc dl = Op.getDebugLoc();
7388 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7389 SDValue ShOpLo = Op.getOperand(0);
7390 SDValue ShOpHi = Op.getOperand(1);
7391 SDValue ShAmt = Op.getOperand(2);
7392 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7393 DAG.getConstant(VTBits - 1, MVT::i8))
7394 : DAG.getConstant(0, VT);
7397 if (Op.getOpcode() == ISD::SHL_PARTS) {
7398 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7399 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7401 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7402 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7405 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7406 DAG.getConstant(VTBits, MVT::i8));
7407 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7408 AndNode, DAG.getConstant(0, MVT::i8));
7411 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7412 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7413 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7415 if (Op.getOpcode() == ISD::SHL_PARTS) {
7416 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7417 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7419 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7420 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7423 SDValue Ops[2] = { Lo, Hi };
7424 return DAG.getMergeValues(Ops, 2, dl);
7427 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7428 SelectionDAG &DAG) const {
7429 EVT SrcVT = Op.getOperand(0).getValueType();
7431 if (SrcVT.isVector())
7434 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7435 "Unknown SINT_TO_FP to lower!");
7437 // These are really Legal; return the operand so the caller accepts it as
7439 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7441 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7442 Subtarget->is64Bit()) {
7446 DebugLoc dl = Op.getDebugLoc();
7447 unsigned Size = SrcVT.getSizeInBits()/8;
7448 MachineFunction &MF = DAG.getMachineFunction();
7449 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7450 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7451 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7453 MachinePointerInfo::getFixedStack(SSFI),
7455 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7458 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7460 SelectionDAG &DAG) const {
7462 DebugLoc DL = Op.getDebugLoc();
7464 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7466 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7468 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7470 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7472 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7473 MachineMemOperand *MMO;
7475 int SSFI = FI->getIndex();
7477 DAG.getMachineFunction()
7478 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7479 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7481 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7482 StackSlot = StackSlot.getOperand(1);
7484 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7485 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7487 Tys, Ops, array_lengthof(Ops),
7491 Chain = Result.getValue(1);
7492 SDValue InFlag = Result.getValue(2);
7494 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7495 // shouldn't be necessary except that RFP cannot be live across
7496 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7497 MachineFunction &MF = DAG.getMachineFunction();
7498 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7499 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7500 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7501 Tys = DAG.getVTList(MVT::Other);
7503 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7505 MachineMemOperand *MMO =
7506 DAG.getMachineFunction()
7507 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7508 MachineMemOperand::MOStore, SSFISize, SSFISize);
7510 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7511 Ops, array_lengthof(Ops),
7512 Op.getValueType(), MMO);
7513 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7514 MachinePointerInfo::getFixedStack(SSFI),
7515 false, false, false, 0);
7521 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7522 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7523 SelectionDAG &DAG) const {
7524 // This algorithm is not obvious. Here it is what we're trying to output:
7527 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7528 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7532 pshufd $0x4e, %xmm0, %xmm1
7537 DebugLoc dl = Op.getDebugLoc();
7538 LLVMContext *Context = DAG.getContext();
7540 // Build some magic constants.
7541 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7542 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7543 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7545 SmallVector<Constant*,2> CV1;
7547 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7549 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7550 Constant *C1 = ConstantVector::get(CV1);
7551 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7553 // Load the 64-bit value into an XMM register.
7554 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7556 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7557 MachinePointerInfo::getConstantPool(),
7558 false, false, false, 16);
7559 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7560 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7563 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7564 MachinePointerInfo::getConstantPool(),
7565 false, false, false, 16);
7566 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7567 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7570 if (Subtarget->hasSSE3()) {
7571 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7572 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7574 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7575 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7577 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7578 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7582 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7583 DAG.getIntPtrConstant(0));
7586 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7587 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7588 SelectionDAG &DAG) const {
7589 DebugLoc dl = Op.getDebugLoc();
7590 // FP constant to bias correct the final result.
7591 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7594 // Load the 32-bit value into an XMM register.
7595 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7598 // Zero out the upper parts of the register.
7599 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7601 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7602 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7603 DAG.getIntPtrConstant(0));
7605 // Or the load with the bias.
7606 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7607 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7608 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7610 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7611 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7612 MVT::v2f64, Bias)));
7613 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7614 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7615 DAG.getIntPtrConstant(0));
7617 // Subtract the bias.
7618 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7620 // Handle final rounding.
7621 EVT DestVT = Op.getValueType();
7623 if (DestVT.bitsLT(MVT::f64)) {
7624 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7625 DAG.getIntPtrConstant(0));
7626 } else if (DestVT.bitsGT(MVT::f64)) {
7627 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7630 // Handle final rounding.
7634 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7635 SelectionDAG &DAG) const {
7636 SDValue N0 = Op.getOperand(0);
7637 DebugLoc dl = Op.getDebugLoc();
7639 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7640 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7641 // the optimization here.
7642 if (DAG.SignBitIsZero(N0))
7643 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7645 EVT SrcVT = N0.getValueType();
7646 EVT DstVT = Op.getValueType();
7647 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7648 return LowerUINT_TO_FP_i64(Op, DAG);
7649 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7650 return LowerUINT_TO_FP_i32(Op, DAG);
7651 else if (Subtarget->is64Bit() &&
7652 SrcVT == MVT::i64 && DstVT == MVT::f32)
7655 // Make a 64-bit buffer, and use it to build an FILD.
7656 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7657 if (SrcVT == MVT::i32) {
7658 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7659 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7660 getPointerTy(), StackSlot, WordOff);
7661 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7662 StackSlot, MachinePointerInfo(),
7664 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7665 OffsetSlot, MachinePointerInfo(),
7667 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7671 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7672 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7673 StackSlot, MachinePointerInfo(),
7675 // For i64 source, we need to add the appropriate power of 2 if the input
7676 // was negative. This is the same as the optimization in
7677 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7678 // we must be careful to do the computation in x87 extended precision, not
7679 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7680 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7681 MachineMemOperand *MMO =
7682 DAG.getMachineFunction()
7683 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7684 MachineMemOperand::MOLoad, 8, 8);
7686 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7687 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7688 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7691 APInt FF(32, 0x5F800000ULL);
7693 // Check whether the sign bit is set.
7694 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7695 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7698 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7699 SDValue FudgePtr = DAG.getConstantPool(
7700 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7703 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7704 SDValue Zero = DAG.getIntPtrConstant(0);
7705 SDValue Four = DAG.getIntPtrConstant(4);
7706 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7708 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7710 // Load the value out, extending it from f32 to f80.
7711 // FIXME: Avoid the extend by constructing the right constant pool?
7712 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7713 FudgePtr, MachinePointerInfo::getConstantPool(),
7714 MVT::f32, false, false, 4);
7715 // Extend everything to 80 bits to force it to be done on x87.
7716 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7717 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7720 std::pair<SDValue,SDValue> X86TargetLowering::
7721 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7722 DebugLoc DL = Op.getDebugLoc();
7724 EVT DstTy = Op.getValueType();
7726 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7727 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7731 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7732 DstTy.getSimpleVT() >= MVT::i16 &&
7733 "Unknown FP_TO_INT to lower!");
7735 // These are really Legal.
7736 if (DstTy == MVT::i32 &&
7737 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7738 return std::make_pair(SDValue(), SDValue());
7739 if (Subtarget->is64Bit() &&
7740 DstTy == MVT::i64 &&
7741 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7742 return std::make_pair(SDValue(), SDValue());
7744 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7745 // stack slot, or into the FTOL runtime function.
7746 MachineFunction &MF = DAG.getMachineFunction();
7747 unsigned MemSize = DstTy.getSizeInBits()/8;
7748 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7749 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7752 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7753 Opc = X86ISD::WIN_FTOL;
7755 switch (DstTy.getSimpleVT().SimpleTy) {
7756 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7757 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7758 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7759 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7762 SDValue Chain = DAG.getEntryNode();
7763 SDValue Value = Op.getOperand(0);
7764 EVT TheVT = Op.getOperand(0).getValueType();
7765 // FIXME This causes a redundant load/store if the SSE-class value is already
7766 // in memory, such as if it is on the callstack.
7767 if (isScalarFPTypeInSSEReg(TheVT)) {
7768 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7769 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7770 MachinePointerInfo::getFixedStack(SSFI),
7772 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7774 Chain, StackSlot, DAG.getValueType(TheVT)
7777 MachineMemOperand *MMO =
7778 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7779 MachineMemOperand::MOLoad, MemSize, MemSize);
7780 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7782 Chain = Value.getValue(1);
7783 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7784 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7787 MachineMemOperand *MMO =
7788 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7789 MachineMemOperand::MOStore, MemSize, MemSize);
7791 if (Opc != X86ISD::WIN_FTOL) {
7792 // Build the FP_TO_INT*_IN_MEM
7793 SDValue Ops[] = { Chain, Value, StackSlot };
7794 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7795 Ops, 3, DstTy, MMO);
7796 return std::make_pair(FIST, StackSlot);
7798 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7799 DAG.getVTList(MVT::Other, MVT::Glue),
7801 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7802 MVT::i32, ftol.getValue(1));
7803 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7804 MVT::i32, eax.getValue(2));
7805 SDValue Ops[] = { eax, edx };
7806 SDValue pair = IsReplace
7807 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7808 : DAG.getMergeValues(Ops, 2, DL);
7809 return std::make_pair(pair, SDValue());
7813 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7814 SelectionDAG &DAG) const {
7815 if (Op.getValueType().isVector())
7818 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7819 /*IsSigned=*/ true, /*IsReplace=*/ false);
7820 SDValue FIST = Vals.first, StackSlot = Vals.second;
7821 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7822 if (FIST.getNode() == 0) return Op;
7824 if (StackSlot.getNode())
7826 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7827 FIST, StackSlot, MachinePointerInfo(),
7828 false, false, false, 0);
7830 // The node is the result.
7834 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7835 SelectionDAG &DAG) const {
7836 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7837 /*IsSigned=*/ false, /*IsReplace=*/ false);
7838 SDValue FIST = Vals.first, StackSlot = Vals.second;
7839 assert(FIST.getNode() && "Unexpected failure");
7841 if (StackSlot.getNode())
7843 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7844 FIST, StackSlot, MachinePointerInfo(),
7845 false, false, false, 0);
7847 // The node is the result.
7851 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7852 SelectionDAG &DAG) const {
7853 LLVMContext *Context = DAG.getContext();
7854 DebugLoc dl = Op.getDebugLoc();
7855 EVT VT = Op.getValueType();
7858 EltVT = VT.getVectorElementType();
7860 if (EltVT == MVT::f64) {
7861 C = ConstantVector::getSplat(2,
7862 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7864 C = ConstantVector::getSplat(4,
7865 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7867 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7868 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7869 MachinePointerInfo::getConstantPool(),
7870 false, false, false, 16);
7871 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7874 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7875 LLVMContext *Context = DAG.getContext();
7876 DebugLoc dl = Op.getDebugLoc();
7877 EVT VT = Op.getValueType();
7879 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7880 if (VT.isVector()) {
7881 EltVT = VT.getVectorElementType();
7882 NumElts = VT.getVectorNumElements();
7885 if (EltVT == MVT::f64)
7886 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7888 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7889 C = ConstantVector::getSplat(NumElts, C);
7890 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7891 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7892 MachinePointerInfo::getConstantPool(),
7893 false, false, false, 16);
7894 if (VT.isVector()) {
7895 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7896 return DAG.getNode(ISD::BITCAST, dl, VT,
7897 DAG.getNode(ISD::XOR, dl, XORVT,
7898 DAG.getNode(ISD::BITCAST, dl, XORVT,
7900 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7902 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7906 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7907 LLVMContext *Context = DAG.getContext();
7908 SDValue Op0 = Op.getOperand(0);
7909 SDValue Op1 = Op.getOperand(1);
7910 DebugLoc dl = Op.getDebugLoc();
7911 EVT VT = Op.getValueType();
7912 EVT SrcVT = Op1.getValueType();
7914 // If second operand is smaller, extend it first.
7915 if (SrcVT.bitsLT(VT)) {
7916 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7919 // And if it is bigger, shrink it first.
7920 if (SrcVT.bitsGT(VT)) {
7921 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7925 // At this point the operands and the result should have the same
7926 // type, and that won't be f80 since that is not custom lowered.
7928 // First get the sign bit of second operand.
7929 SmallVector<Constant*,4> CV;
7930 if (SrcVT == MVT::f64) {
7931 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7932 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7934 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7935 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7936 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7937 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7939 Constant *C = ConstantVector::get(CV);
7940 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7941 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7942 MachinePointerInfo::getConstantPool(),
7943 false, false, false, 16);
7944 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7946 // Shift sign bit right or left if the two operands have different types.
7947 if (SrcVT.bitsGT(VT)) {
7948 // Op0 is MVT::f32, Op1 is MVT::f64.
7949 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7950 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7951 DAG.getConstant(32, MVT::i32));
7952 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7953 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7954 DAG.getIntPtrConstant(0));
7957 // Clear first operand sign bit.
7959 if (VT == MVT::f64) {
7960 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7961 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7963 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7964 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7965 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7966 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7968 C = ConstantVector::get(CV);
7969 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7970 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7971 MachinePointerInfo::getConstantPool(),
7972 false, false, false, 16);
7973 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7975 // Or the value with the sign bit.
7976 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
7979 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
7980 SDValue N0 = Op.getOperand(0);
7981 DebugLoc dl = Op.getDebugLoc();
7982 EVT VT = Op.getValueType();
7984 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
7985 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
7986 DAG.getConstant(1, VT));
7987 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
7990 /// Emit nodes that will be selected as "test Op0,Op0", or something
7992 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
7993 SelectionDAG &DAG) const {
7994 DebugLoc dl = Op.getDebugLoc();
7996 // CF and OF aren't always set the way we want. Determine which
7997 // of these we need.
7998 bool NeedCF = false;
7999 bool NeedOF = false;
8002 case X86::COND_A: case X86::COND_AE:
8003 case X86::COND_B: case X86::COND_BE:
8006 case X86::COND_G: case X86::COND_GE:
8007 case X86::COND_L: case X86::COND_LE:
8008 case X86::COND_O: case X86::COND_NO:
8013 // See if we can use the EFLAGS value from the operand instead of
8014 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8015 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8016 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8017 // Emit a CMP with 0, which is the TEST pattern.
8018 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8019 DAG.getConstant(0, Op.getValueType()));
8021 unsigned Opcode = 0;
8022 unsigned NumOperands = 0;
8023 switch (Op.getNode()->getOpcode()) {
8025 // Due to an isel shortcoming, be conservative if this add is likely to be
8026 // selected as part of a load-modify-store instruction. When the root node
8027 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8028 // uses of other nodes in the match, such as the ADD in this case. This
8029 // leads to the ADD being left around and reselected, with the result being
8030 // two adds in the output. Alas, even if none our users are stores, that
8031 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8032 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8033 // climbing the DAG back to the root, and it doesn't seem to be worth the
8035 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8036 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8037 if (UI->getOpcode() != ISD::CopyToReg &&
8038 UI->getOpcode() != ISD::SETCC &&
8039 UI->getOpcode() != ISD::STORE)
8042 if (ConstantSDNode *C =
8043 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8044 // An add of one will be selected as an INC.
8045 if (C->getAPIntValue() == 1) {
8046 Opcode = X86ISD::INC;
8051 // An add of negative one (subtract of one) will be selected as a DEC.
8052 if (C->getAPIntValue().isAllOnesValue()) {
8053 Opcode = X86ISD::DEC;
8059 // Otherwise use a regular EFLAGS-setting add.
8060 Opcode = X86ISD::ADD;
8064 // If the primary and result isn't used, don't bother using X86ISD::AND,
8065 // because a TEST instruction will be better.
8066 bool NonFlagUse = false;
8067 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8068 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8070 unsigned UOpNo = UI.getOperandNo();
8071 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8072 // Look pass truncate.
8073 UOpNo = User->use_begin().getOperandNo();
8074 User = *User->use_begin();
8077 if (User->getOpcode() != ISD::BRCOND &&
8078 User->getOpcode() != ISD::SETCC &&
8079 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8092 // Due to the ISEL shortcoming noted above, be conservative if this op is
8093 // likely to be selected as part of a load-modify-store instruction.
8094 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8095 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8096 if (UI->getOpcode() == ISD::STORE)
8099 // Otherwise use a regular EFLAGS-setting instruction.
8100 switch (Op.getNode()->getOpcode()) {
8101 default: llvm_unreachable("unexpected operator!");
8102 case ISD::SUB: Opcode = X86ISD::SUB; break;
8103 case ISD::OR: Opcode = X86ISD::OR; break;
8104 case ISD::XOR: Opcode = X86ISD::XOR; break;
8105 case ISD::AND: Opcode = X86ISD::AND; break;
8117 return SDValue(Op.getNode(), 1);
8124 // Emit a CMP with 0, which is the TEST pattern.
8125 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8126 DAG.getConstant(0, Op.getValueType()));
8128 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8129 SmallVector<SDValue, 4> Ops;
8130 for (unsigned i = 0; i != NumOperands; ++i)
8131 Ops.push_back(Op.getOperand(i));
8133 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8134 DAG.ReplaceAllUsesWith(Op, New);
8135 return SDValue(New.getNode(), 1);
8138 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8140 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8141 SelectionDAG &DAG) const {
8142 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8143 if (C->getAPIntValue() == 0)
8144 return EmitTest(Op0, X86CC, DAG);
8146 DebugLoc dl = Op0.getDebugLoc();
8147 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8150 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8151 /// if it's possible.
8152 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8153 DebugLoc dl, SelectionDAG &DAG) const {
8154 SDValue Op0 = And.getOperand(0);
8155 SDValue Op1 = And.getOperand(1);
8156 if (Op0.getOpcode() == ISD::TRUNCATE)
8157 Op0 = Op0.getOperand(0);
8158 if (Op1.getOpcode() == ISD::TRUNCATE)
8159 Op1 = Op1.getOperand(0);
8162 if (Op1.getOpcode() == ISD::SHL)
8163 std::swap(Op0, Op1);
8164 if (Op0.getOpcode() == ISD::SHL) {
8165 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8166 if (And00C->getZExtValue() == 1) {
8167 // If we looked past a truncate, check that it's only truncating away
8169 unsigned BitWidth = Op0.getValueSizeInBits();
8170 unsigned AndBitWidth = And.getValueSizeInBits();
8171 if (BitWidth > AndBitWidth) {
8172 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8173 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8174 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8178 RHS = Op0.getOperand(1);
8180 } else if (Op1.getOpcode() == ISD::Constant) {
8181 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8182 uint64_t AndRHSVal = AndRHS->getZExtValue();
8183 SDValue AndLHS = Op0;
8185 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8186 LHS = AndLHS.getOperand(0);
8187 RHS = AndLHS.getOperand(1);
8190 // Use BT if the immediate can't be encoded in a TEST instruction.
8191 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8193 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8197 if (LHS.getNode()) {
8198 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8199 // instruction. Since the shift amount is in-range-or-undefined, we know
8200 // that doing a bittest on the i32 value is ok. We extend to i32 because
8201 // the encoding for the i16 version is larger than the i32 version.
8202 // Also promote i16 to i32 for performance / code size reason.
8203 if (LHS.getValueType() == MVT::i8 ||
8204 LHS.getValueType() == MVT::i16)
8205 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8207 // If the operand types disagree, extend the shift amount to match. Since
8208 // BT ignores high bits (like shifts) we can use anyextend.
8209 if (LHS.getValueType() != RHS.getValueType())
8210 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8212 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8213 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8214 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8215 DAG.getConstant(Cond, MVT::i8), BT);
8221 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8223 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8225 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8226 SDValue Op0 = Op.getOperand(0);
8227 SDValue Op1 = Op.getOperand(1);
8228 DebugLoc dl = Op.getDebugLoc();
8229 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8231 // Optimize to BT if possible.
8232 // Lower (X & (1 << N)) == 0 to BT(X, N).
8233 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8234 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8235 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8236 Op1.getOpcode() == ISD::Constant &&
8237 cast<ConstantSDNode>(Op1)->isNullValue() &&
8238 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8239 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8240 if (NewSetCC.getNode())
8244 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8246 if (Op1.getOpcode() == ISD::Constant &&
8247 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8248 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8249 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8251 // If the input is a setcc, then reuse the input setcc or use a new one with
8252 // the inverted condition.
8253 if (Op0.getOpcode() == X86ISD::SETCC) {
8254 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8255 bool Invert = (CC == ISD::SETNE) ^
8256 cast<ConstantSDNode>(Op1)->isNullValue();
8257 if (!Invert) return Op0;
8259 CCode = X86::GetOppositeBranchCondition(CCode);
8260 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8261 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8265 bool isFP = Op1.getValueType().isFloatingPoint();
8266 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8267 if (X86CC == X86::COND_INVALID)
8270 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8271 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8272 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8275 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8276 // ones, and then concatenate the result back.
8277 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8278 EVT VT = Op.getValueType();
8280 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8281 "Unsupported value type for operation");
8283 int NumElems = VT.getVectorNumElements();
8284 DebugLoc dl = Op.getDebugLoc();
8285 SDValue CC = Op.getOperand(2);
8286 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8287 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8289 // Extract the LHS vectors
8290 SDValue LHS = Op.getOperand(0);
8291 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8292 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8294 // Extract the RHS vectors
8295 SDValue RHS = Op.getOperand(1);
8296 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8297 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8299 // Issue the operation on the smaller types and concatenate the result back
8300 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8301 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8302 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8303 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8304 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8308 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8310 SDValue Op0 = Op.getOperand(0);
8311 SDValue Op1 = Op.getOperand(1);
8312 SDValue CC = Op.getOperand(2);
8313 EVT VT = Op.getValueType();
8314 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8315 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8316 DebugLoc dl = Op.getDebugLoc();
8320 EVT EltVT = Op0.getValueType().getVectorElementType();
8321 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8325 // SSE Condition code mapping:
8334 switch (SetCCOpcode) {
8337 case ISD::SETEQ: SSECC = 0; break;
8339 case ISD::SETGT: Swap = true; // Fallthrough
8341 case ISD::SETOLT: SSECC = 1; break;
8343 case ISD::SETGE: Swap = true; // Fallthrough
8345 case ISD::SETOLE: SSECC = 2; break;
8346 case ISD::SETUO: SSECC = 3; break;
8348 case ISD::SETNE: SSECC = 4; break;
8349 case ISD::SETULE: Swap = true;
8350 case ISD::SETUGE: SSECC = 5; break;
8351 case ISD::SETULT: Swap = true;
8352 case ISD::SETUGT: SSECC = 6; break;
8353 case ISD::SETO: SSECC = 7; break;
8356 std::swap(Op0, Op1);
8358 // In the two special cases we can't handle, emit two comparisons.
8360 if (SetCCOpcode == ISD::SETUEQ) {
8362 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8363 DAG.getConstant(3, MVT::i8));
8364 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8365 DAG.getConstant(0, MVT::i8));
8366 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8367 } else if (SetCCOpcode == ISD::SETONE) {
8369 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8370 DAG.getConstant(7, MVT::i8));
8371 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8372 DAG.getConstant(4, MVT::i8));
8373 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8375 llvm_unreachable("Illegal FP comparison");
8377 // Handle all other FP comparisons here.
8378 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8379 DAG.getConstant(SSECC, MVT::i8));
8382 // Break 256-bit integer vector compare into smaller ones.
8383 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8384 return Lower256IntVSETCC(Op, DAG);
8386 // We are handling one of the integer comparisons here. Since SSE only has
8387 // GT and EQ comparisons for integer, swapping operands and multiple
8388 // operations may be required for some comparisons.
8390 bool Swap = false, Invert = false, FlipSigns = false;
8392 switch (SetCCOpcode) {
8394 case ISD::SETNE: Invert = true;
8395 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8396 case ISD::SETLT: Swap = true;
8397 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8398 case ISD::SETGE: Swap = true;
8399 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8400 case ISD::SETULT: Swap = true;
8401 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8402 case ISD::SETUGE: Swap = true;
8403 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8406 std::swap(Op0, Op1);
8408 // Check that the operation in question is available (most are plain SSE2,
8409 // but PCMPGTQ and PCMPEQQ have different requirements).
8410 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8412 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8415 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8416 // bits of the inputs before performing those operations.
8418 EVT EltVT = VT.getVectorElementType();
8419 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8421 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8422 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8424 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8425 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8428 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8430 // If the logical-not of the result is required, perform that now.
8432 Result = DAG.getNOT(dl, Result, VT);
8437 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8438 static bool isX86LogicalCmp(SDValue Op) {
8439 unsigned Opc = Op.getNode()->getOpcode();
8440 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8442 if (Op.getResNo() == 1 &&
8443 (Opc == X86ISD::ADD ||
8444 Opc == X86ISD::SUB ||
8445 Opc == X86ISD::ADC ||
8446 Opc == X86ISD::SBB ||
8447 Opc == X86ISD::SMUL ||
8448 Opc == X86ISD::UMUL ||
8449 Opc == X86ISD::INC ||
8450 Opc == X86ISD::DEC ||
8451 Opc == X86ISD::OR ||
8452 Opc == X86ISD::XOR ||
8453 Opc == X86ISD::AND))
8456 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8462 static bool isZero(SDValue V) {
8463 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8464 return C && C->isNullValue();
8467 static bool isAllOnes(SDValue V) {
8468 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8469 return C && C->isAllOnesValue();
8472 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8473 bool addTest = true;
8474 SDValue Cond = Op.getOperand(0);
8475 SDValue Op1 = Op.getOperand(1);
8476 SDValue Op2 = Op.getOperand(2);
8477 DebugLoc DL = Op.getDebugLoc();
8480 if (Cond.getOpcode() == ISD::SETCC) {
8481 SDValue NewCond = LowerSETCC(Cond, DAG);
8482 if (NewCond.getNode())
8486 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8487 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8488 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8489 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8490 if (Cond.getOpcode() == X86ISD::SETCC &&
8491 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8492 isZero(Cond.getOperand(1).getOperand(1))) {
8493 SDValue Cmp = Cond.getOperand(1);
8495 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8497 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8498 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8499 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8501 SDValue CmpOp0 = Cmp.getOperand(0);
8502 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8503 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8505 SDValue Res = // Res = 0 or -1.
8506 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8507 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8509 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8510 Res = DAG.getNOT(DL, Res, Res.getValueType());
8512 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8513 if (N2C == 0 || !N2C->isNullValue())
8514 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8519 // Look past (and (setcc_carry (cmp ...)), 1).
8520 if (Cond.getOpcode() == ISD::AND &&
8521 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8522 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8523 if (C && C->getAPIntValue() == 1)
8524 Cond = Cond.getOperand(0);
8527 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8528 // setting operand in place of the X86ISD::SETCC.
8529 unsigned CondOpcode = Cond.getOpcode();
8530 if (CondOpcode == X86ISD::SETCC ||
8531 CondOpcode == X86ISD::SETCC_CARRY) {
8532 CC = Cond.getOperand(0);
8534 SDValue Cmp = Cond.getOperand(1);
8535 unsigned Opc = Cmp.getOpcode();
8536 EVT VT = Op.getValueType();
8538 bool IllegalFPCMov = false;
8539 if (VT.isFloatingPoint() && !VT.isVector() &&
8540 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8541 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8543 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8544 Opc == X86ISD::BT) { // FIXME
8548 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8549 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8550 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8551 Cond.getOperand(0).getValueType() != MVT::i8)) {
8552 SDValue LHS = Cond.getOperand(0);
8553 SDValue RHS = Cond.getOperand(1);
8557 switch (CondOpcode) {
8558 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8559 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8560 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8561 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8562 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8563 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8564 default: llvm_unreachable("unexpected overflowing operator");
8566 if (CondOpcode == ISD::UMULO)
8567 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8570 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8572 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8574 if (CondOpcode == ISD::UMULO)
8575 Cond = X86Op.getValue(2);
8577 Cond = X86Op.getValue(1);
8579 CC = DAG.getConstant(X86Cond, MVT::i8);
8584 // Look pass the truncate.
8585 if (Cond.getOpcode() == ISD::TRUNCATE)
8586 Cond = Cond.getOperand(0);
8588 // We know the result of AND is compared against zero. Try to match
8590 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8591 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8592 if (NewSetCC.getNode()) {
8593 CC = NewSetCC.getOperand(0);
8594 Cond = NewSetCC.getOperand(1);
8601 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8602 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8605 // a < b ? -1 : 0 -> RES = ~setcc_carry
8606 // a < b ? 0 : -1 -> RES = setcc_carry
8607 // a >= b ? -1 : 0 -> RES = setcc_carry
8608 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8609 if (Cond.getOpcode() == X86ISD::CMP) {
8610 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8612 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8613 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8614 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8615 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8616 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8617 return DAG.getNOT(DL, Res, Res.getValueType());
8622 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8623 // condition is true.
8624 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8625 SDValue Ops[] = { Op2, Op1, CC, Cond };
8626 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8629 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8630 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8631 // from the AND / OR.
8632 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8633 Opc = Op.getOpcode();
8634 if (Opc != ISD::OR && Opc != ISD::AND)
8636 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8637 Op.getOperand(0).hasOneUse() &&
8638 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8639 Op.getOperand(1).hasOneUse());
8642 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8643 // 1 and that the SETCC node has a single use.
8644 static bool isXor1OfSetCC(SDValue Op) {
8645 if (Op.getOpcode() != ISD::XOR)
8647 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8648 if (N1C && N1C->getAPIntValue() == 1) {
8649 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8650 Op.getOperand(0).hasOneUse();
8655 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8656 bool addTest = true;
8657 SDValue Chain = Op.getOperand(0);
8658 SDValue Cond = Op.getOperand(1);
8659 SDValue Dest = Op.getOperand(2);
8660 DebugLoc dl = Op.getDebugLoc();
8662 bool Inverted = false;
8664 if (Cond.getOpcode() == ISD::SETCC) {
8665 // Check for setcc([su]{add,sub,mul}o == 0).
8666 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8667 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8668 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8669 Cond.getOperand(0).getResNo() == 1 &&
8670 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8671 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8672 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8673 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8674 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8675 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8677 Cond = Cond.getOperand(0);
8679 SDValue NewCond = LowerSETCC(Cond, DAG);
8680 if (NewCond.getNode())
8685 // FIXME: LowerXALUO doesn't handle these!!
8686 else if (Cond.getOpcode() == X86ISD::ADD ||
8687 Cond.getOpcode() == X86ISD::SUB ||
8688 Cond.getOpcode() == X86ISD::SMUL ||
8689 Cond.getOpcode() == X86ISD::UMUL)
8690 Cond = LowerXALUO(Cond, DAG);
8693 // Look pass (and (setcc_carry (cmp ...)), 1).
8694 if (Cond.getOpcode() == ISD::AND &&
8695 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8696 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8697 if (C && C->getAPIntValue() == 1)
8698 Cond = Cond.getOperand(0);
8701 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8702 // setting operand in place of the X86ISD::SETCC.
8703 unsigned CondOpcode = Cond.getOpcode();
8704 if (CondOpcode == X86ISD::SETCC ||
8705 CondOpcode == X86ISD::SETCC_CARRY) {
8706 CC = Cond.getOperand(0);
8708 SDValue Cmp = Cond.getOperand(1);
8709 unsigned Opc = Cmp.getOpcode();
8710 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8711 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8715 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8719 // These can only come from an arithmetic instruction with overflow,
8720 // e.g. SADDO, UADDO.
8721 Cond = Cond.getNode()->getOperand(1);
8727 CondOpcode = Cond.getOpcode();
8728 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8729 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8730 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8731 Cond.getOperand(0).getValueType() != MVT::i8)) {
8732 SDValue LHS = Cond.getOperand(0);
8733 SDValue RHS = Cond.getOperand(1);
8737 switch (CondOpcode) {
8738 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8739 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8740 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8741 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8742 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8743 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8744 default: llvm_unreachable("unexpected overflowing operator");
8747 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8748 if (CondOpcode == ISD::UMULO)
8749 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8752 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8754 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8756 if (CondOpcode == ISD::UMULO)
8757 Cond = X86Op.getValue(2);
8759 Cond = X86Op.getValue(1);
8761 CC = DAG.getConstant(X86Cond, MVT::i8);
8765 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8766 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8767 if (CondOpc == ISD::OR) {
8768 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8769 // two branches instead of an explicit OR instruction with a
8771 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8772 isX86LogicalCmp(Cmp)) {
8773 CC = Cond.getOperand(0).getOperand(0);
8774 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8775 Chain, Dest, CC, Cmp);
8776 CC = Cond.getOperand(1).getOperand(0);
8780 } else { // ISD::AND
8781 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8782 // two branches instead of an explicit AND instruction with a
8783 // separate test. However, we only do this if this block doesn't
8784 // have a fall-through edge, because this requires an explicit
8785 // jmp when the condition is false.
8786 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8787 isX86LogicalCmp(Cmp) &&
8788 Op.getNode()->hasOneUse()) {
8789 X86::CondCode CCode =
8790 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8791 CCode = X86::GetOppositeBranchCondition(CCode);
8792 CC = DAG.getConstant(CCode, MVT::i8);
8793 SDNode *User = *Op.getNode()->use_begin();
8794 // Look for an unconditional branch following this conditional branch.
8795 // We need this because we need to reverse the successors in order
8796 // to implement FCMP_OEQ.
8797 if (User->getOpcode() == ISD::BR) {
8798 SDValue FalseBB = User->getOperand(1);
8800 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8801 assert(NewBR == User);
8805 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8806 Chain, Dest, CC, Cmp);
8807 X86::CondCode CCode =
8808 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8809 CCode = X86::GetOppositeBranchCondition(CCode);
8810 CC = DAG.getConstant(CCode, MVT::i8);
8816 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8817 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8818 // It should be transformed during dag combiner except when the condition
8819 // is set by a arithmetics with overflow node.
8820 X86::CondCode CCode =
8821 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8822 CCode = X86::GetOppositeBranchCondition(CCode);
8823 CC = DAG.getConstant(CCode, MVT::i8);
8824 Cond = Cond.getOperand(0).getOperand(1);
8826 } else if (Cond.getOpcode() == ISD::SETCC &&
8827 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8828 // For FCMP_OEQ, we can emit
8829 // two branches instead of an explicit AND instruction with a
8830 // separate test. However, we only do this if this block doesn't
8831 // have a fall-through edge, because this requires an explicit
8832 // jmp when the condition is false.
8833 if (Op.getNode()->hasOneUse()) {
8834 SDNode *User = *Op.getNode()->use_begin();
8835 // Look for an unconditional branch following this conditional branch.
8836 // We need this because we need to reverse the successors in order
8837 // to implement FCMP_OEQ.
8838 if (User->getOpcode() == ISD::BR) {
8839 SDValue FalseBB = User->getOperand(1);
8841 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8842 assert(NewBR == User);
8846 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8847 Cond.getOperand(0), Cond.getOperand(1));
8848 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8849 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8850 Chain, Dest, CC, Cmp);
8851 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8856 } else if (Cond.getOpcode() == ISD::SETCC &&
8857 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8858 // For FCMP_UNE, we can emit
8859 // two branches instead of an explicit AND instruction with a
8860 // separate test. However, we only do this if this block doesn't
8861 // have a fall-through edge, because this requires an explicit
8862 // jmp when the condition is false.
8863 if (Op.getNode()->hasOneUse()) {
8864 SDNode *User = *Op.getNode()->use_begin();
8865 // Look for an unconditional branch following this conditional branch.
8866 // We need this because we need to reverse the successors in order
8867 // to implement FCMP_UNE.
8868 if (User->getOpcode() == ISD::BR) {
8869 SDValue FalseBB = User->getOperand(1);
8871 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8872 assert(NewBR == User);
8875 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8876 Cond.getOperand(0), Cond.getOperand(1));
8877 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8878 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8879 Chain, Dest, CC, Cmp);
8880 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8890 // Look pass the truncate.
8891 if (Cond.getOpcode() == ISD::TRUNCATE)
8892 Cond = Cond.getOperand(0);
8894 // We know the result of AND is compared against zero. Try to match
8896 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8897 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8898 if (NewSetCC.getNode()) {
8899 CC = NewSetCC.getOperand(0);
8900 Cond = NewSetCC.getOperand(1);
8907 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8908 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8910 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8911 Chain, Dest, CC, Cond);
8915 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8916 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8917 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8918 // that the guard pages used by the OS virtual memory manager are allocated in
8919 // correct sequence.
8921 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8922 SelectionDAG &DAG) const {
8923 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8924 getTargetMachine().Options.EnableSegmentedStacks) &&
8925 "This should be used only on Windows targets or when segmented stacks "
8927 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8928 DebugLoc dl = Op.getDebugLoc();
8931 SDValue Chain = Op.getOperand(0);
8932 SDValue Size = Op.getOperand(1);
8933 // FIXME: Ensure alignment here
8935 bool Is64Bit = Subtarget->is64Bit();
8936 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8938 if (getTargetMachine().Options.EnableSegmentedStacks) {
8939 MachineFunction &MF = DAG.getMachineFunction();
8940 MachineRegisterInfo &MRI = MF.getRegInfo();
8943 // The 64 bit implementation of segmented stacks needs to clobber both r10
8944 // r11. This makes it impossible to use it along with nested parameters.
8945 const Function *F = MF.getFunction();
8947 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8949 if (I->hasNestAttr())
8950 report_fatal_error("Cannot use segmented stacks with functions that "
8951 "have nested arguments.");
8954 const TargetRegisterClass *AddrRegClass =
8955 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8956 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8957 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8958 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8959 DAG.getRegister(Vreg, SPTy));
8960 SDValue Ops1[2] = { Value, Chain };
8961 return DAG.getMergeValues(Ops1, 2, dl);
8964 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8966 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8967 Flag = Chain.getValue(1);
8968 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8970 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8971 Flag = Chain.getValue(1);
8973 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8975 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8976 return DAG.getMergeValues(Ops1, 2, dl);
8980 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8981 MachineFunction &MF = DAG.getMachineFunction();
8982 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8984 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8985 DebugLoc DL = Op.getDebugLoc();
8987 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8988 // vastart just stores the address of the VarArgsFrameIndex slot into the
8989 // memory location argument.
8990 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8992 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8993 MachinePointerInfo(SV), false, false, 0);
8997 // gp_offset (0 - 6 * 8)
8998 // fp_offset (48 - 48 + 8 * 16)
8999 // overflow_arg_area (point to parameters coming in memory).
9001 SmallVector<SDValue, 8> MemOps;
9002 SDValue FIN = Op.getOperand(1);
9004 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9005 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9007 FIN, MachinePointerInfo(SV), false, false, 0);
9008 MemOps.push_back(Store);
9011 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9012 FIN, DAG.getIntPtrConstant(4));
9013 Store = DAG.getStore(Op.getOperand(0), DL,
9014 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9016 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9017 MemOps.push_back(Store);
9019 // Store ptr to overflow_arg_area
9020 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9021 FIN, DAG.getIntPtrConstant(4));
9022 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9024 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9025 MachinePointerInfo(SV, 8),
9027 MemOps.push_back(Store);
9029 // Store ptr to reg_save_area.
9030 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9031 FIN, DAG.getIntPtrConstant(8));
9032 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9034 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9035 MachinePointerInfo(SV, 16), false, false, 0);
9036 MemOps.push_back(Store);
9037 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9038 &MemOps[0], MemOps.size());
9041 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9042 assert(Subtarget->is64Bit() &&
9043 "LowerVAARG only handles 64-bit va_arg!");
9044 assert((Subtarget->isTargetLinux() ||
9045 Subtarget->isTargetDarwin()) &&
9046 "Unhandled target in LowerVAARG");
9047 assert(Op.getNode()->getNumOperands() == 4);
9048 SDValue Chain = Op.getOperand(0);
9049 SDValue SrcPtr = Op.getOperand(1);
9050 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9051 unsigned Align = Op.getConstantOperandVal(3);
9052 DebugLoc dl = Op.getDebugLoc();
9054 EVT ArgVT = Op.getNode()->getValueType(0);
9055 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9056 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9059 // Decide which area this value should be read from.
9060 // TODO: Implement the AMD64 ABI in its entirety. This simple
9061 // selection mechanism works only for the basic types.
9062 if (ArgVT == MVT::f80) {
9063 llvm_unreachable("va_arg for f80 not yet implemented");
9064 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9065 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9066 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9067 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9069 llvm_unreachable("Unhandled argument type in LowerVAARG");
9073 // Sanity Check: Make sure using fp_offset makes sense.
9074 assert(!getTargetMachine().Options.UseSoftFloat &&
9075 !(DAG.getMachineFunction()
9076 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9077 Subtarget->hasSSE1());
9080 // Insert VAARG_64 node into the DAG
9081 // VAARG_64 returns two values: Variable Argument Address, Chain
9082 SmallVector<SDValue, 11> InstOps;
9083 InstOps.push_back(Chain);
9084 InstOps.push_back(SrcPtr);
9085 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9086 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9087 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9088 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9089 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9090 VTs, &InstOps[0], InstOps.size(),
9092 MachinePointerInfo(SV),
9097 Chain = VAARG.getValue(1);
9099 // Load the next argument and return it
9100 return DAG.getLoad(ArgVT, dl,
9103 MachinePointerInfo(),
9104 false, false, false, 0);
9107 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9108 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9109 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9110 SDValue Chain = Op.getOperand(0);
9111 SDValue DstPtr = Op.getOperand(1);
9112 SDValue SrcPtr = Op.getOperand(2);
9113 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9114 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9115 DebugLoc DL = Op.getDebugLoc();
9117 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9118 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9120 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9123 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9124 // may or may not be a constant. Takes immediate version of shift as input.
9125 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9126 SDValue SrcOp, SDValue ShAmt,
9127 SelectionDAG &DAG) {
9128 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9130 if (isa<ConstantSDNode>(ShAmt)) {
9132 default: llvm_unreachable("Unknown target vector shift node");
9136 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9140 // Change opcode to non-immediate version
9142 default: llvm_unreachable("Unknown target vector shift node");
9143 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9144 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9145 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9148 // Need to build a vector containing shift amount
9149 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9152 ShOps[1] = DAG.getConstant(0, MVT::i32);
9153 ShOps[2] = DAG.getUNDEF(MVT::i32);
9154 ShOps[3] = DAG.getUNDEF(MVT::i32);
9155 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9156 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9157 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9161 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9162 DebugLoc dl = Op.getDebugLoc();
9163 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9165 default: return SDValue(); // Don't custom lower most intrinsics.
9166 // Comparison intrinsics.
9167 case Intrinsic::x86_sse_comieq_ss:
9168 case Intrinsic::x86_sse_comilt_ss:
9169 case Intrinsic::x86_sse_comile_ss:
9170 case Intrinsic::x86_sse_comigt_ss:
9171 case Intrinsic::x86_sse_comige_ss:
9172 case Intrinsic::x86_sse_comineq_ss:
9173 case Intrinsic::x86_sse_ucomieq_ss:
9174 case Intrinsic::x86_sse_ucomilt_ss:
9175 case Intrinsic::x86_sse_ucomile_ss:
9176 case Intrinsic::x86_sse_ucomigt_ss:
9177 case Intrinsic::x86_sse_ucomige_ss:
9178 case Intrinsic::x86_sse_ucomineq_ss:
9179 case Intrinsic::x86_sse2_comieq_sd:
9180 case Intrinsic::x86_sse2_comilt_sd:
9181 case Intrinsic::x86_sse2_comile_sd:
9182 case Intrinsic::x86_sse2_comigt_sd:
9183 case Intrinsic::x86_sse2_comige_sd:
9184 case Intrinsic::x86_sse2_comineq_sd:
9185 case Intrinsic::x86_sse2_ucomieq_sd:
9186 case Intrinsic::x86_sse2_ucomilt_sd:
9187 case Intrinsic::x86_sse2_ucomile_sd:
9188 case Intrinsic::x86_sse2_ucomigt_sd:
9189 case Intrinsic::x86_sse2_ucomige_sd:
9190 case Intrinsic::x86_sse2_ucomineq_sd: {
9192 ISD::CondCode CC = ISD::SETCC_INVALID;
9194 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9195 case Intrinsic::x86_sse_comieq_ss:
9196 case Intrinsic::x86_sse2_comieq_sd:
9200 case Intrinsic::x86_sse_comilt_ss:
9201 case Intrinsic::x86_sse2_comilt_sd:
9205 case Intrinsic::x86_sse_comile_ss:
9206 case Intrinsic::x86_sse2_comile_sd:
9210 case Intrinsic::x86_sse_comigt_ss:
9211 case Intrinsic::x86_sse2_comigt_sd:
9215 case Intrinsic::x86_sse_comige_ss:
9216 case Intrinsic::x86_sse2_comige_sd:
9220 case Intrinsic::x86_sse_comineq_ss:
9221 case Intrinsic::x86_sse2_comineq_sd:
9225 case Intrinsic::x86_sse_ucomieq_ss:
9226 case Intrinsic::x86_sse2_ucomieq_sd:
9227 Opc = X86ISD::UCOMI;
9230 case Intrinsic::x86_sse_ucomilt_ss:
9231 case Intrinsic::x86_sse2_ucomilt_sd:
9232 Opc = X86ISD::UCOMI;
9235 case Intrinsic::x86_sse_ucomile_ss:
9236 case Intrinsic::x86_sse2_ucomile_sd:
9237 Opc = X86ISD::UCOMI;
9240 case Intrinsic::x86_sse_ucomigt_ss:
9241 case Intrinsic::x86_sse2_ucomigt_sd:
9242 Opc = X86ISD::UCOMI;
9245 case Intrinsic::x86_sse_ucomige_ss:
9246 case Intrinsic::x86_sse2_ucomige_sd:
9247 Opc = X86ISD::UCOMI;
9250 case Intrinsic::x86_sse_ucomineq_ss:
9251 case Intrinsic::x86_sse2_ucomineq_sd:
9252 Opc = X86ISD::UCOMI;
9257 SDValue LHS = Op.getOperand(1);
9258 SDValue RHS = Op.getOperand(2);
9259 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9260 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9261 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9262 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9263 DAG.getConstant(X86CC, MVT::i8), Cond);
9264 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9266 // XOP comparison intrinsics
9267 case Intrinsic::x86_xop_vpcomltb:
9268 case Intrinsic::x86_xop_vpcomltw:
9269 case Intrinsic::x86_xop_vpcomltd:
9270 case Intrinsic::x86_xop_vpcomltq:
9271 case Intrinsic::x86_xop_vpcomltub:
9272 case Intrinsic::x86_xop_vpcomltuw:
9273 case Intrinsic::x86_xop_vpcomltud:
9274 case Intrinsic::x86_xop_vpcomltuq:
9275 case Intrinsic::x86_xop_vpcomleb:
9276 case Intrinsic::x86_xop_vpcomlew:
9277 case Intrinsic::x86_xop_vpcomled:
9278 case Intrinsic::x86_xop_vpcomleq:
9279 case Intrinsic::x86_xop_vpcomleub:
9280 case Intrinsic::x86_xop_vpcomleuw:
9281 case Intrinsic::x86_xop_vpcomleud:
9282 case Intrinsic::x86_xop_vpcomleuq:
9283 case Intrinsic::x86_xop_vpcomgtb:
9284 case Intrinsic::x86_xop_vpcomgtw:
9285 case Intrinsic::x86_xop_vpcomgtd:
9286 case Intrinsic::x86_xop_vpcomgtq:
9287 case Intrinsic::x86_xop_vpcomgtub:
9288 case Intrinsic::x86_xop_vpcomgtuw:
9289 case Intrinsic::x86_xop_vpcomgtud:
9290 case Intrinsic::x86_xop_vpcomgtuq:
9291 case Intrinsic::x86_xop_vpcomgeb:
9292 case Intrinsic::x86_xop_vpcomgew:
9293 case Intrinsic::x86_xop_vpcomged:
9294 case Intrinsic::x86_xop_vpcomgeq:
9295 case Intrinsic::x86_xop_vpcomgeub:
9296 case Intrinsic::x86_xop_vpcomgeuw:
9297 case Intrinsic::x86_xop_vpcomgeud:
9298 case Intrinsic::x86_xop_vpcomgeuq:
9299 case Intrinsic::x86_xop_vpcomeqb:
9300 case Intrinsic::x86_xop_vpcomeqw:
9301 case Intrinsic::x86_xop_vpcomeqd:
9302 case Intrinsic::x86_xop_vpcomeqq:
9303 case Intrinsic::x86_xop_vpcomequb:
9304 case Intrinsic::x86_xop_vpcomequw:
9305 case Intrinsic::x86_xop_vpcomequd:
9306 case Intrinsic::x86_xop_vpcomequq:
9307 case Intrinsic::x86_xop_vpcomneb:
9308 case Intrinsic::x86_xop_vpcomnew:
9309 case Intrinsic::x86_xop_vpcomned:
9310 case Intrinsic::x86_xop_vpcomneq:
9311 case Intrinsic::x86_xop_vpcomneub:
9312 case Intrinsic::x86_xop_vpcomneuw:
9313 case Intrinsic::x86_xop_vpcomneud:
9314 case Intrinsic::x86_xop_vpcomneuq:
9315 case Intrinsic::x86_xop_vpcomfalseb:
9316 case Intrinsic::x86_xop_vpcomfalsew:
9317 case Intrinsic::x86_xop_vpcomfalsed:
9318 case Intrinsic::x86_xop_vpcomfalseq:
9319 case Intrinsic::x86_xop_vpcomfalseub:
9320 case Intrinsic::x86_xop_vpcomfalseuw:
9321 case Intrinsic::x86_xop_vpcomfalseud:
9322 case Intrinsic::x86_xop_vpcomfalseuq:
9323 case Intrinsic::x86_xop_vpcomtrueb:
9324 case Intrinsic::x86_xop_vpcomtruew:
9325 case Intrinsic::x86_xop_vpcomtrued:
9326 case Intrinsic::x86_xop_vpcomtrueq:
9327 case Intrinsic::x86_xop_vpcomtrueub:
9328 case Intrinsic::x86_xop_vpcomtrueuw:
9329 case Intrinsic::x86_xop_vpcomtrueud:
9330 case Intrinsic::x86_xop_vpcomtrueuq: {
9335 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9336 case Intrinsic::x86_xop_vpcomltb:
9337 case Intrinsic::x86_xop_vpcomltw:
9338 case Intrinsic::x86_xop_vpcomltd:
9339 case Intrinsic::x86_xop_vpcomltq:
9341 Opc = X86ISD::VPCOM;
9343 case Intrinsic::x86_xop_vpcomltub:
9344 case Intrinsic::x86_xop_vpcomltuw:
9345 case Intrinsic::x86_xop_vpcomltud:
9346 case Intrinsic::x86_xop_vpcomltuq:
9348 Opc = X86ISD::VPCOMU;
9350 case Intrinsic::x86_xop_vpcomleb:
9351 case Intrinsic::x86_xop_vpcomlew:
9352 case Intrinsic::x86_xop_vpcomled:
9353 case Intrinsic::x86_xop_vpcomleq:
9355 Opc = X86ISD::VPCOM;
9357 case Intrinsic::x86_xop_vpcomleub:
9358 case Intrinsic::x86_xop_vpcomleuw:
9359 case Intrinsic::x86_xop_vpcomleud:
9360 case Intrinsic::x86_xop_vpcomleuq:
9362 Opc = X86ISD::VPCOMU;
9364 case Intrinsic::x86_xop_vpcomgtb:
9365 case Intrinsic::x86_xop_vpcomgtw:
9366 case Intrinsic::x86_xop_vpcomgtd:
9367 case Intrinsic::x86_xop_vpcomgtq:
9369 Opc = X86ISD::VPCOM;
9371 case Intrinsic::x86_xop_vpcomgtub:
9372 case Intrinsic::x86_xop_vpcomgtuw:
9373 case Intrinsic::x86_xop_vpcomgtud:
9374 case Intrinsic::x86_xop_vpcomgtuq:
9376 Opc = X86ISD::VPCOMU;
9378 case Intrinsic::x86_xop_vpcomgeb:
9379 case Intrinsic::x86_xop_vpcomgew:
9380 case Intrinsic::x86_xop_vpcomged:
9381 case Intrinsic::x86_xop_vpcomgeq:
9383 Opc = X86ISD::VPCOM;
9385 case Intrinsic::x86_xop_vpcomgeub:
9386 case Intrinsic::x86_xop_vpcomgeuw:
9387 case Intrinsic::x86_xop_vpcomgeud:
9388 case Intrinsic::x86_xop_vpcomgeuq:
9390 Opc = X86ISD::VPCOMU;
9392 case Intrinsic::x86_xop_vpcomeqb:
9393 case Intrinsic::x86_xop_vpcomeqw:
9394 case Intrinsic::x86_xop_vpcomeqd:
9395 case Intrinsic::x86_xop_vpcomeqq:
9397 Opc = X86ISD::VPCOM;
9399 case Intrinsic::x86_xop_vpcomequb:
9400 case Intrinsic::x86_xop_vpcomequw:
9401 case Intrinsic::x86_xop_vpcomequd:
9402 case Intrinsic::x86_xop_vpcomequq:
9404 Opc = X86ISD::VPCOMU;
9406 case Intrinsic::x86_xop_vpcomneb:
9407 case Intrinsic::x86_xop_vpcomnew:
9408 case Intrinsic::x86_xop_vpcomned:
9409 case Intrinsic::x86_xop_vpcomneq:
9411 Opc = X86ISD::VPCOM;
9413 case Intrinsic::x86_xop_vpcomneub:
9414 case Intrinsic::x86_xop_vpcomneuw:
9415 case Intrinsic::x86_xop_vpcomneud:
9416 case Intrinsic::x86_xop_vpcomneuq:
9418 Opc = X86ISD::VPCOMU;
9420 case Intrinsic::x86_xop_vpcomfalseb:
9421 case Intrinsic::x86_xop_vpcomfalsew:
9422 case Intrinsic::x86_xop_vpcomfalsed:
9423 case Intrinsic::x86_xop_vpcomfalseq:
9425 Opc = X86ISD::VPCOM;
9427 case Intrinsic::x86_xop_vpcomfalseub:
9428 case Intrinsic::x86_xop_vpcomfalseuw:
9429 case Intrinsic::x86_xop_vpcomfalseud:
9430 case Intrinsic::x86_xop_vpcomfalseuq:
9432 Opc = X86ISD::VPCOMU;
9434 case Intrinsic::x86_xop_vpcomtrueb:
9435 case Intrinsic::x86_xop_vpcomtruew:
9436 case Intrinsic::x86_xop_vpcomtrued:
9437 case Intrinsic::x86_xop_vpcomtrueq:
9439 Opc = X86ISD::VPCOM;
9441 case Intrinsic::x86_xop_vpcomtrueub:
9442 case Intrinsic::x86_xop_vpcomtrueuw:
9443 case Intrinsic::x86_xop_vpcomtrueud:
9444 case Intrinsic::x86_xop_vpcomtrueuq:
9446 Opc = X86ISD::VPCOMU;
9450 SDValue LHS = Op.getOperand(1);
9451 SDValue RHS = Op.getOperand(2);
9452 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9453 DAG.getConstant(CC, MVT::i8));
9456 // Arithmetic intrinsics.
9457 case Intrinsic::x86_sse2_pmulu_dq:
9458 case Intrinsic::x86_avx2_pmulu_dq:
9459 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9460 Op.getOperand(1), Op.getOperand(2));
9461 case Intrinsic::x86_sse3_hadd_ps:
9462 case Intrinsic::x86_sse3_hadd_pd:
9463 case Intrinsic::x86_avx_hadd_ps_256:
9464 case Intrinsic::x86_avx_hadd_pd_256:
9465 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9466 Op.getOperand(1), Op.getOperand(2));
9467 case Intrinsic::x86_sse3_hsub_ps:
9468 case Intrinsic::x86_sse3_hsub_pd:
9469 case Intrinsic::x86_avx_hsub_ps_256:
9470 case Intrinsic::x86_avx_hsub_pd_256:
9471 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9472 Op.getOperand(1), Op.getOperand(2));
9473 case Intrinsic::x86_ssse3_phadd_w_128:
9474 case Intrinsic::x86_ssse3_phadd_d_128:
9475 case Intrinsic::x86_avx2_phadd_w:
9476 case Intrinsic::x86_avx2_phadd_d:
9477 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9478 Op.getOperand(1), Op.getOperand(2));
9479 case Intrinsic::x86_ssse3_phsub_w_128:
9480 case Intrinsic::x86_ssse3_phsub_d_128:
9481 case Intrinsic::x86_avx2_phsub_w:
9482 case Intrinsic::x86_avx2_phsub_d:
9483 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9484 Op.getOperand(1), Op.getOperand(2));
9485 case Intrinsic::x86_avx2_psllv_d:
9486 case Intrinsic::x86_avx2_psllv_q:
9487 case Intrinsic::x86_avx2_psllv_d_256:
9488 case Intrinsic::x86_avx2_psllv_q_256:
9489 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9490 Op.getOperand(1), Op.getOperand(2));
9491 case Intrinsic::x86_avx2_psrlv_d:
9492 case Intrinsic::x86_avx2_psrlv_q:
9493 case Intrinsic::x86_avx2_psrlv_d_256:
9494 case Intrinsic::x86_avx2_psrlv_q_256:
9495 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9496 Op.getOperand(1), Op.getOperand(2));
9497 case Intrinsic::x86_avx2_psrav_d:
9498 case Intrinsic::x86_avx2_psrav_d_256:
9499 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9500 Op.getOperand(1), Op.getOperand(2));
9501 case Intrinsic::x86_ssse3_pshuf_b_128:
9502 case Intrinsic::x86_avx2_pshuf_b:
9503 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9504 Op.getOperand(1), Op.getOperand(2));
9505 case Intrinsic::x86_ssse3_psign_b_128:
9506 case Intrinsic::x86_ssse3_psign_w_128:
9507 case Intrinsic::x86_ssse3_psign_d_128:
9508 case Intrinsic::x86_avx2_psign_b:
9509 case Intrinsic::x86_avx2_psign_w:
9510 case Intrinsic::x86_avx2_psign_d:
9511 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9512 Op.getOperand(1), Op.getOperand(2));
9513 case Intrinsic::x86_sse41_insertps:
9514 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9515 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9516 case Intrinsic::x86_avx_vperm2f128_ps_256:
9517 case Intrinsic::x86_avx_vperm2f128_pd_256:
9518 case Intrinsic::x86_avx_vperm2f128_si_256:
9519 case Intrinsic::x86_avx2_vperm2i128:
9520 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9521 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9522 case Intrinsic::x86_avx_vpermil_ps:
9523 case Intrinsic::x86_avx_vpermil_pd:
9524 case Intrinsic::x86_avx_vpermil_ps_256:
9525 case Intrinsic::x86_avx_vpermil_pd_256:
9526 return DAG.getNode(X86ISD::VPERMILP, dl, Op.getValueType(),
9527 Op.getOperand(1), Op.getOperand(2));
9529 // ptest and testp intrinsics. The intrinsic these come from are designed to
9530 // return an integer value, not just an instruction so lower it to the ptest
9531 // or testp pattern and a setcc for the result.
9532 case Intrinsic::x86_sse41_ptestz:
9533 case Intrinsic::x86_sse41_ptestc:
9534 case Intrinsic::x86_sse41_ptestnzc:
9535 case Intrinsic::x86_avx_ptestz_256:
9536 case Intrinsic::x86_avx_ptestc_256:
9537 case Intrinsic::x86_avx_ptestnzc_256:
9538 case Intrinsic::x86_avx_vtestz_ps:
9539 case Intrinsic::x86_avx_vtestc_ps:
9540 case Intrinsic::x86_avx_vtestnzc_ps:
9541 case Intrinsic::x86_avx_vtestz_pd:
9542 case Intrinsic::x86_avx_vtestc_pd:
9543 case Intrinsic::x86_avx_vtestnzc_pd:
9544 case Intrinsic::x86_avx_vtestz_ps_256:
9545 case Intrinsic::x86_avx_vtestc_ps_256:
9546 case Intrinsic::x86_avx_vtestnzc_ps_256:
9547 case Intrinsic::x86_avx_vtestz_pd_256:
9548 case Intrinsic::x86_avx_vtestc_pd_256:
9549 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9550 bool IsTestPacked = false;
9553 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9554 case Intrinsic::x86_avx_vtestz_ps:
9555 case Intrinsic::x86_avx_vtestz_pd:
9556 case Intrinsic::x86_avx_vtestz_ps_256:
9557 case Intrinsic::x86_avx_vtestz_pd_256:
9558 IsTestPacked = true; // Fallthrough
9559 case Intrinsic::x86_sse41_ptestz:
9560 case Intrinsic::x86_avx_ptestz_256:
9562 X86CC = X86::COND_E;
9564 case Intrinsic::x86_avx_vtestc_ps:
9565 case Intrinsic::x86_avx_vtestc_pd:
9566 case Intrinsic::x86_avx_vtestc_ps_256:
9567 case Intrinsic::x86_avx_vtestc_pd_256:
9568 IsTestPacked = true; // Fallthrough
9569 case Intrinsic::x86_sse41_ptestc:
9570 case Intrinsic::x86_avx_ptestc_256:
9572 X86CC = X86::COND_B;
9574 case Intrinsic::x86_avx_vtestnzc_ps:
9575 case Intrinsic::x86_avx_vtestnzc_pd:
9576 case Intrinsic::x86_avx_vtestnzc_ps_256:
9577 case Intrinsic::x86_avx_vtestnzc_pd_256:
9578 IsTestPacked = true; // Fallthrough
9579 case Intrinsic::x86_sse41_ptestnzc:
9580 case Intrinsic::x86_avx_ptestnzc_256:
9582 X86CC = X86::COND_A;
9586 SDValue LHS = Op.getOperand(1);
9587 SDValue RHS = Op.getOperand(2);
9588 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9589 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9590 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9591 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9592 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9595 // SSE/AVX shift intrinsics
9596 case Intrinsic::x86_sse2_psll_w:
9597 case Intrinsic::x86_sse2_psll_d:
9598 case Intrinsic::x86_sse2_psll_q:
9599 case Intrinsic::x86_avx2_psll_w:
9600 case Intrinsic::x86_avx2_psll_d:
9601 case Intrinsic::x86_avx2_psll_q:
9602 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9603 Op.getOperand(1), Op.getOperand(2));
9604 case Intrinsic::x86_sse2_psrl_w:
9605 case Intrinsic::x86_sse2_psrl_d:
9606 case Intrinsic::x86_sse2_psrl_q:
9607 case Intrinsic::x86_avx2_psrl_w:
9608 case Intrinsic::x86_avx2_psrl_d:
9609 case Intrinsic::x86_avx2_psrl_q:
9610 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9611 Op.getOperand(1), Op.getOperand(2));
9612 case Intrinsic::x86_sse2_psra_w:
9613 case Intrinsic::x86_sse2_psra_d:
9614 case Intrinsic::x86_avx2_psra_w:
9615 case Intrinsic::x86_avx2_psra_d:
9616 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9617 Op.getOperand(1), Op.getOperand(2));
9618 case Intrinsic::x86_sse2_pslli_w:
9619 case Intrinsic::x86_sse2_pslli_d:
9620 case Intrinsic::x86_sse2_pslli_q:
9621 case Intrinsic::x86_avx2_pslli_w:
9622 case Intrinsic::x86_avx2_pslli_d:
9623 case Intrinsic::x86_avx2_pslli_q:
9624 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9625 Op.getOperand(1), Op.getOperand(2), DAG);
9626 case Intrinsic::x86_sse2_psrli_w:
9627 case Intrinsic::x86_sse2_psrli_d:
9628 case Intrinsic::x86_sse2_psrli_q:
9629 case Intrinsic::x86_avx2_psrli_w:
9630 case Intrinsic::x86_avx2_psrli_d:
9631 case Intrinsic::x86_avx2_psrli_q:
9632 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9633 Op.getOperand(1), Op.getOperand(2), DAG);
9634 case Intrinsic::x86_sse2_psrai_w:
9635 case Intrinsic::x86_sse2_psrai_d:
9636 case Intrinsic::x86_avx2_psrai_w:
9637 case Intrinsic::x86_avx2_psrai_d:
9638 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9639 Op.getOperand(1), Op.getOperand(2), DAG);
9640 // Fix vector shift instructions where the last operand is a non-immediate
9642 case Intrinsic::x86_mmx_pslli_w:
9643 case Intrinsic::x86_mmx_pslli_d:
9644 case Intrinsic::x86_mmx_pslli_q:
9645 case Intrinsic::x86_mmx_psrli_w:
9646 case Intrinsic::x86_mmx_psrli_d:
9647 case Intrinsic::x86_mmx_psrli_q:
9648 case Intrinsic::x86_mmx_psrai_w:
9649 case Intrinsic::x86_mmx_psrai_d: {
9650 SDValue ShAmt = Op.getOperand(2);
9651 if (isa<ConstantSDNode>(ShAmt))
9654 unsigned NewIntNo = 0;
9656 case Intrinsic::x86_mmx_pslli_w:
9657 NewIntNo = Intrinsic::x86_mmx_psll_w;
9659 case Intrinsic::x86_mmx_pslli_d:
9660 NewIntNo = Intrinsic::x86_mmx_psll_d;
9662 case Intrinsic::x86_mmx_pslli_q:
9663 NewIntNo = Intrinsic::x86_mmx_psll_q;
9665 case Intrinsic::x86_mmx_psrli_w:
9666 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9668 case Intrinsic::x86_mmx_psrli_d:
9669 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9671 case Intrinsic::x86_mmx_psrli_q:
9672 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9674 case Intrinsic::x86_mmx_psrai_w:
9675 NewIntNo = Intrinsic::x86_mmx_psra_w;
9677 case Intrinsic::x86_mmx_psrai_d:
9678 NewIntNo = Intrinsic::x86_mmx_psra_d;
9680 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9683 // The vector shift intrinsics with scalars uses 32b shift amounts but
9684 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9686 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9687 DAG.getConstant(0, MVT::i32));
9688 // FIXME this must be lowered to get rid of the invalid type.
9690 EVT VT = Op.getValueType();
9691 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9692 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9693 DAG.getConstant(NewIntNo, MVT::i32),
9694 Op.getOperand(1), ShAmt);
9699 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9700 SelectionDAG &DAG) const {
9701 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9702 MFI->setReturnAddressIsTaken(true);
9704 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9705 DebugLoc dl = Op.getDebugLoc();
9708 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9710 DAG.getConstant(TD->getPointerSize(),
9711 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9712 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9713 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9715 MachinePointerInfo(), false, false, false, 0);
9718 // Just load the return address.
9719 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9720 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9721 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9724 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9725 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9726 MFI->setFrameAddressIsTaken(true);
9728 EVT VT = Op.getValueType();
9729 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9730 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9731 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9732 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9734 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9735 MachinePointerInfo(),
9736 false, false, false, 0);
9740 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9741 SelectionDAG &DAG) const {
9742 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9745 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9746 MachineFunction &MF = DAG.getMachineFunction();
9747 SDValue Chain = Op.getOperand(0);
9748 SDValue Offset = Op.getOperand(1);
9749 SDValue Handler = Op.getOperand(2);
9750 DebugLoc dl = Op.getDebugLoc();
9752 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9753 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9755 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9757 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9758 DAG.getIntPtrConstant(TD->getPointerSize()));
9759 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9760 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9762 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9763 MF.getRegInfo().addLiveOut(StoreAddrReg);
9765 return DAG.getNode(X86ISD::EH_RETURN, dl,
9767 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9770 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9771 SelectionDAG &DAG) const {
9772 return Op.getOperand(0);
9775 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9776 SelectionDAG &DAG) const {
9777 SDValue Root = Op.getOperand(0);
9778 SDValue Trmp = Op.getOperand(1); // trampoline
9779 SDValue FPtr = Op.getOperand(2); // nested function
9780 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9781 DebugLoc dl = Op.getDebugLoc();
9783 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9785 if (Subtarget->is64Bit()) {
9786 SDValue OutChains[6];
9788 // Large code-model.
9789 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9790 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9792 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9793 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9795 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9797 // Load the pointer to the nested function into R11.
9798 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9799 SDValue Addr = Trmp;
9800 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9801 Addr, MachinePointerInfo(TrmpAddr),
9804 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9805 DAG.getConstant(2, MVT::i64));
9806 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9807 MachinePointerInfo(TrmpAddr, 2),
9810 // Load the 'nest' parameter value into R10.
9811 // R10 is specified in X86CallingConv.td
9812 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9813 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9814 DAG.getConstant(10, MVT::i64));
9815 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9816 Addr, MachinePointerInfo(TrmpAddr, 10),
9819 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9820 DAG.getConstant(12, MVT::i64));
9821 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9822 MachinePointerInfo(TrmpAddr, 12),
9825 // Jump to the nested function.
9826 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9827 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9828 DAG.getConstant(20, MVT::i64));
9829 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9830 Addr, MachinePointerInfo(TrmpAddr, 20),
9833 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9834 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9835 DAG.getConstant(22, MVT::i64));
9836 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9837 MachinePointerInfo(TrmpAddr, 22),
9840 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9842 const Function *Func =
9843 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9844 CallingConv::ID CC = Func->getCallingConv();
9849 llvm_unreachable("Unsupported calling convention");
9850 case CallingConv::C:
9851 case CallingConv::X86_StdCall: {
9852 // Pass 'nest' parameter in ECX.
9853 // Must be kept in sync with X86CallingConv.td
9856 // Check that ECX wasn't needed by an 'inreg' parameter.
9857 FunctionType *FTy = Func->getFunctionType();
9858 const AttrListPtr &Attrs = Func->getAttributes();
9860 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9861 unsigned InRegCount = 0;
9864 for (FunctionType::param_iterator I = FTy->param_begin(),
9865 E = FTy->param_end(); I != E; ++I, ++Idx)
9866 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9867 // FIXME: should only count parameters that are lowered to integers.
9868 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9870 if (InRegCount > 2) {
9871 report_fatal_error("Nest register in use - reduce number of inreg"
9877 case CallingConv::X86_FastCall:
9878 case CallingConv::X86_ThisCall:
9879 case CallingConv::Fast:
9880 // Pass 'nest' parameter in EAX.
9881 // Must be kept in sync with X86CallingConv.td
9886 SDValue OutChains[4];
9889 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9890 DAG.getConstant(10, MVT::i32));
9891 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9893 // This is storing the opcode for MOV32ri.
9894 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9895 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9896 OutChains[0] = DAG.getStore(Root, dl,
9897 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9898 Trmp, MachinePointerInfo(TrmpAddr),
9901 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9902 DAG.getConstant(1, MVT::i32));
9903 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9904 MachinePointerInfo(TrmpAddr, 1),
9907 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9908 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9909 DAG.getConstant(5, MVT::i32));
9910 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9911 MachinePointerInfo(TrmpAddr, 5),
9914 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9915 DAG.getConstant(6, MVT::i32));
9916 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9917 MachinePointerInfo(TrmpAddr, 6),
9920 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9924 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9925 SelectionDAG &DAG) const {
9927 The rounding mode is in bits 11:10 of FPSR, and has the following
9934 FLT_ROUNDS, on the other hand, expects the following:
9941 To perform the conversion, we do:
9942 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9945 MachineFunction &MF = DAG.getMachineFunction();
9946 const TargetMachine &TM = MF.getTarget();
9947 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9948 unsigned StackAlignment = TFI.getStackAlignment();
9949 EVT VT = Op.getValueType();
9950 DebugLoc DL = Op.getDebugLoc();
9952 // Save FP Control Word to stack slot
9953 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9954 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9957 MachineMemOperand *MMO =
9958 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9959 MachineMemOperand::MOStore, 2, 2);
9961 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9962 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9963 DAG.getVTList(MVT::Other),
9964 Ops, 2, MVT::i16, MMO);
9966 // Load FP Control Word from stack slot
9967 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9968 MachinePointerInfo(), false, false, false, 0);
9970 // Transform as necessary
9972 DAG.getNode(ISD::SRL, DL, MVT::i16,
9973 DAG.getNode(ISD::AND, DL, MVT::i16,
9974 CWD, DAG.getConstant(0x800, MVT::i16)),
9975 DAG.getConstant(11, MVT::i8));
9977 DAG.getNode(ISD::SRL, DL, MVT::i16,
9978 DAG.getNode(ISD::AND, DL, MVT::i16,
9979 CWD, DAG.getConstant(0x400, MVT::i16)),
9980 DAG.getConstant(9, MVT::i8));
9983 DAG.getNode(ISD::AND, DL, MVT::i16,
9984 DAG.getNode(ISD::ADD, DL, MVT::i16,
9985 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9986 DAG.getConstant(1, MVT::i16)),
9987 DAG.getConstant(3, MVT::i16));
9990 return DAG.getNode((VT.getSizeInBits() < 16 ?
9991 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9994 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9995 EVT VT = Op.getValueType();
9997 unsigned NumBits = VT.getSizeInBits();
9998 DebugLoc dl = Op.getDebugLoc();
10000 Op = Op.getOperand(0);
10001 if (VT == MVT::i8) {
10002 // Zero extend to i32 since there is not an i8 bsr.
10004 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10007 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10008 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10009 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10011 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10014 DAG.getConstant(NumBits+NumBits-1, OpVT),
10015 DAG.getConstant(X86::COND_E, MVT::i8),
10018 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10020 // Finally xor with NumBits-1.
10021 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10024 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10028 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10029 SelectionDAG &DAG) const {
10030 EVT VT = Op.getValueType();
10032 unsigned NumBits = VT.getSizeInBits();
10033 DebugLoc dl = Op.getDebugLoc();
10035 Op = Op.getOperand(0);
10036 if (VT == MVT::i8) {
10037 // Zero extend to i32 since there is not an i8 bsr.
10039 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10042 // Issue a bsr (scan bits in reverse).
10043 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10044 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10046 // And xor with NumBits-1.
10047 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10050 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10054 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10055 EVT VT = Op.getValueType();
10056 unsigned NumBits = VT.getSizeInBits();
10057 DebugLoc dl = Op.getDebugLoc();
10058 Op = Op.getOperand(0);
10060 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10061 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10062 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10064 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10067 DAG.getConstant(NumBits, VT),
10068 DAG.getConstant(X86::COND_E, MVT::i8),
10071 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10074 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10075 // ones, and then concatenate the result back.
10076 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10077 EVT VT = Op.getValueType();
10079 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10080 "Unsupported value type for operation");
10082 int NumElems = VT.getVectorNumElements();
10083 DebugLoc dl = Op.getDebugLoc();
10084 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10085 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10087 // Extract the LHS vectors
10088 SDValue LHS = Op.getOperand(0);
10089 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10090 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10092 // Extract the RHS vectors
10093 SDValue RHS = Op.getOperand(1);
10094 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
10095 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
10097 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10098 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10100 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10101 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10102 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10105 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10106 assert(Op.getValueType().getSizeInBits() == 256 &&
10107 Op.getValueType().isInteger() &&
10108 "Only handle AVX 256-bit vector integer operation");
10109 return Lower256IntArith(Op, DAG);
10112 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10113 assert(Op.getValueType().getSizeInBits() == 256 &&
10114 Op.getValueType().isInteger() &&
10115 "Only handle AVX 256-bit vector integer operation");
10116 return Lower256IntArith(Op, DAG);
10119 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10120 EVT VT = Op.getValueType();
10122 // Decompose 256-bit ops into smaller 128-bit ops.
10123 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10124 return Lower256IntArith(Op, DAG);
10126 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10127 "Only know how to lower V2I64/V4I64 multiply");
10129 DebugLoc dl = Op.getDebugLoc();
10131 // Ahi = psrlqi(a, 32);
10132 // Bhi = psrlqi(b, 32);
10134 // AloBlo = pmuludq(a, b);
10135 // AloBhi = pmuludq(a, Bhi);
10136 // AhiBlo = pmuludq(Ahi, b);
10138 // AloBhi = psllqi(AloBhi, 32);
10139 // AhiBlo = psllqi(AhiBlo, 32);
10140 // return AloBlo + AloBhi + AhiBlo;
10142 SDValue A = Op.getOperand(0);
10143 SDValue B = Op.getOperand(1);
10145 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10147 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10148 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10150 // Bit cast to 32-bit vectors for MULUDQ
10151 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10152 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10153 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10154 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10155 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10157 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10158 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10159 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10161 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10162 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10164 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10165 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10168 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10170 EVT VT = Op.getValueType();
10171 DebugLoc dl = Op.getDebugLoc();
10172 SDValue R = Op.getOperand(0);
10173 SDValue Amt = Op.getOperand(1);
10174 LLVMContext *Context = DAG.getContext();
10176 if (!Subtarget->hasSSE2())
10179 // Optimize shl/srl/sra with constant shift amount.
10180 if (isSplatVector(Amt.getNode())) {
10181 SDValue SclrAmt = Amt->getOperand(0);
10182 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10183 uint64_t ShiftAmt = C->getZExtValue();
10185 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10186 (Subtarget->hasAVX2() &&
10187 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10188 if (Op.getOpcode() == ISD::SHL)
10189 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10190 DAG.getConstant(ShiftAmt, MVT::i32));
10191 if (Op.getOpcode() == ISD::SRL)
10192 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10193 DAG.getConstant(ShiftAmt, MVT::i32));
10194 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10195 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10196 DAG.getConstant(ShiftAmt, MVT::i32));
10199 if (VT == MVT::v16i8) {
10200 if (Op.getOpcode() == ISD::SHL) {
10201 // Make a large shift.
10202 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10203 DAG.getConstant(ShiftAmt, MVT::i32));
10204 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10205 // Zero out the rightmost bits.
10206 SmallVector<SDValue, 16> V(16,
10207 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10209 return DAG.getNode(ISD::AND, dl, VT, SHL,
10210 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10212 if (Op.getOpcode() == ISD::SRL) {
10213 // Make a large shift.
10214 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10215 DAG.getConstant(ShiftAmt, MVT::i32));
10216 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10217 // Zero out the leftmost bits.
10218 SmallVector<SDValue, 16> V(16,
10219 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10221 return DAG.getNode(ISD::AND, dl, VT, SRL,
10222 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10224 if (Op.getOpcode() == ISD::SRA) {
10225 if (ShiftAmt == 7) {
10226 // R s>> 7 === R s< 0
10227 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10228 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10231 // R s>> a === ((R u>> a) ^ m) - m
10232 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10233 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10235 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10236 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10237 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10242 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10243 if (Op.getOpcode() == ISD::SHL) {
10244 // Make a large shift.
10245 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10246 DAG.getConstant(ShiftAmt, MVT::i32));
10247 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10248 // Zero out the rightmost bits.
10249 SmallVector<SDValue, 32> V(32,
10250 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10252 return DAG.getNode(ISD::AND, dl, VT, SHL,
10253 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10255 if (Op.getOpcode() == ISD::SRL) {
10256 // Make a large shift.
10257 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10258 DAG.getConstant(ShiftAmt, MVT::i32));
10259 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10260 // Zero out the leftmost bits.
10261 SmallVector<SDValue, 32> V(32,
10262 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10264 return DAG.getNode(ISD::AND, dl, VT, SRL,
10265 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10267 if (Op.getOpcode() == ISD::SRA) {
10268 if (ShiftAmt == 7) {
10269 // R s>> 7 === R s< 0
10270 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10271 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10274 // R s>> a === ((R u>> a) ^ m) - m
10275 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10276 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10278 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10279 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10280 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10287 // Lower SHL with variable shift amount.
10288 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10289 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10290 DAG.getConstant(23, MVT::i32));
10292 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10293 Constant *C = ConstantDataVector::get(*Context, CV);
10294 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10295 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10296 MachinePointerInfo::getConstantPool(),
10297 false, false, false, 16);
10299 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10300 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10301 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10302 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10304 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10305 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10308 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10309 DAG.getConstant(5, MVT::i32));
10310 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10312 // Turn 'a' into a mask suitable for VSELECT
10313 SDValue VSelM = DAG.getConstant(0x80, VT);
10314 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10315 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10317 SDValue CM1 = DAG.getConstant(0x0f, VT);
10318 SDValue CM2 = DAG.getConstant(0x3f, VT);
10320 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10321 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10322 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10323 DAG.getConstant(4, MVT::i32), DAG);
10324 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10325 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10328 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10329 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10330 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10332 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10333 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10334 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10335 DAG.getConstant(2, MVT::i32), DAG);
10336 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10337 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10340 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10341 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10342 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10344 // return VSELECT(r, r+r, a);
10345 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10346 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10350 // Decompose 256-bit shifts into smaller 128-bit shifts.
10351 if (VT.getSizeInBits() == 256) {
10352 unsigned NumElems = VT.getVectorNumElements();
10353 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10354 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10356 // Extract the two vectors
10357 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10358 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10361 // Recreate the shift amount vectors
10362 SDValue Amt1, Amt2;
10363 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10364 // Constant shift amount
10365 SmallVector<SDValue, 4> Amt1Csts;
10366 SmallVector<SDValue, 4> Amt2Csts;
10367 for (unsigned i = 0; i != NumElems/2; ++i)
10368 Amt1Csts.push_back(Amt->getOperand(i));
10369 for (unsigned i = NumElems/2; i != NumElems; ++i)
10370 Amt2Csts.push_back(Amt->getOperand(i));
10372 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10373 &Amt1Csts[0], NumElems/2);
10374 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10375 &Amt2Csts[0], NumElems/2);
10377 // Variable shift amount
10378 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10379 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10383 // Issue new vector shifts for the smaller types
10384 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10385 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10387 // Concatenate the result back
10388 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10394 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10395 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10396 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10397 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10398 // has only one use.
10399 SDNode *N = Op.getNode();
10400 SDValue LHS = N->getOperand(0);
10401 SDValue RHS = N->getOperand(1);
10402 unsigned BaseOp = 0;
10404 DebugLoc DL = Op.getDebugLoc();
10405 switch (Op.getOpcode()) {
10406 default: llvm_unreachable("Unknown ovf instruction!");
10408 // A subtract of one will be selected as a INC. Note that INC doesn't
10409 // set CF, so we can't do this for UADDO.
10410 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10412 BaseOp = X86ISD::INC;
10413 Cond = X86::COND_O;
10416 BaseOp = X86ISD::ADD;
10417 Cond = X86::COND_O;
10420 BaseOp = X86ISD::ADD;
10421 Cond = X86::COND_B;
10424 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10425 // set CF, so we can't do this for USUBO.
10426 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10428 BaseOp = X86ISD::DEC;
10429 Cond = X86::COND_O;
10432 BaseOp = X86ISD::SUB;
10433 Cond = X86::COND_O;
10436 BaseOp = X86ISD::SUB;
10437 Cond = X86::COND_B;
10440 BaseOp = X86ISD::SMUL;
10441 Cond = X86::COND_O;
10443 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10444 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10446 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10449 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10450 DAG.getConstant(X86::COND_O, MVT::i32),
10451 SDValue(Sum.getNode(), 2));
10453 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10457 // Also sets EFLAGS.
10458 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10459 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10462 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10463 DAG.getConstant(Cond, MVT::i32),
10464 SDValue(Sum.getNode(), 1));
10466 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10469 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10470 SelectionDAG &DAG) const {
10471 DebugLoc dl = Op.getDebugLoc();
10472 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10473 EVT VT = Op.getValueType();
10475 if (!Subtarget->hasSSE2() || !VT.isVector())
10478 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10479 ExtraVT.getScalarType().getSizeInBits();
10480 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10482 switch (VT.getSimpleVT().SimpleTy) {
10483 default: return SDValue();
10486 if (!Subtarget->hasAVX())
10488 if (!Subtarget->hasAVX2()) {
10489 // needs to be split
10490 int NumElems = VT.getVectorNumElements();
10491 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10492 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10494 // Extract the LHS vectors
10495 SDValue LHS = Op.getOperand(0);
10496 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10497 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10499 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10500 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10502 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10503 int ExtraNumElems = ExtraVT.getVectorNumElements();
10504 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10506 SDValue Extra = DAG.getValueType(ExtraVT);
10508 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10509 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10511 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10516 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10517 Op.getOperand(0), ShAmt, DAG);
10518 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10524 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10525 DebugLoc dl = Op.getDebugLoc();
10527 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10528 // There isn't any reason to disable it if the target processor supports it.
10529 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10530 SDValue Chain = Op.getOperand(0);
10531 SDValue Zero = DAG.getConstant(0, MVT::i32);
10533 DAG.getRegister(X86::ESP, MVT::i32), // Base
10534 DAG.getTargetConstant(1, MVT::i8), // Scale
10535 DAG.getRegister(0, MVT::i32), // Index
10536 DAG.getTargetConstant(0, MVT::i32), // Disp
10537 DAG.getRegister(0, MVT::i32), // Segment.
10542 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10543 array_lengthof(Ops));
10544 return SDValue(Res, 0);
10547 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10549 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10551 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10552 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10553 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10554 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10556 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10557 if (!Op1 && !Op2 && !Op3 && Op4)
10558 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10560 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10561 if (Op1 && !Op2 && !Op3 && !Op4)
10562 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10564 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10566 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10569 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10570 SelectionDAG &DAG) const {
10571 DebugLoc dl = Op.getDebugLoc();
10572 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10573 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10574 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10575 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10577 // The only fence that needs an instruction is a sequentially-consistent
10578 // cross-thread fence.
10579 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10580 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10581 // no-sse2). There isn't any reason to disable it if the target processor
10583 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10584 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10586 SDValue Chain = Op.getOperand(0);
10587 SDValue Zero = DAG.getConstant(0, MVT::i32);
10589 DAG.getRegister(X86::ESP, MVT::i32), // Base
10590 DAG.getTargetConstant(1, MVT::i8), // Scale
10591 DAG.getRegister(0, MVT::i32), // Index
10592 DAG.getTargetConstant(0, MVT::i32), // Disp
10593 DAG.getRegister(0, MVT::i32), // Segment.
10598 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10599 array_lengthof(Ops));
10600 return SDValue(Res, 0);
10603 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10604 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10608 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10609 EVT T = Op.getValueType();
10610 DebugLoc DL = Op.getDebugLoc();
10613 switch(T.getSimpleVT().SimpleTy) {
10614 default: llvm_unreachable("Invalid value type!");
10615 case MVT::i8: Reg = X86::AL; size = 1; break;
10616 case MVT::i16: Reg = X86::AX; size = 2; break;
10617 case MVT::i32: Reg = X86::EAX; size = 4; break;
10619 assert(Subtarget->is64Bit() && "Node not type legal!");
10620 Reg = X86::RAX; size = 8;
10623 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10624 Op.getOperand(2), SDValue());
10625 SDValue Ops[] = { cpIn.getValue(0),
10628 DAG.getTargetConstant(size, MVT::i8),
10629 cpIn.getValue(1) };
10630 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10631 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10632 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10635 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10639 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10640 SelectionDAG &DAG) const {
10641 assert(Subtarget->is64Bit() && "Result not type legalized?");
10642 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10643 SDValue TheChain = Op.getOperand(0);
10644 DebugLoc dl = Op.getDebugLoc();
10645 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10646 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10647 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10649 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10650 DAG.getConstant(32, MVT::i8));
10652 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10655 return DAG.getMergeValues(Ops, 2, dl);
10658 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10659 SelectionDAG &DAG) const {
10660 EVT SrcVT = Op.getOperand(0).getValueType();
10661 EVT DstVT = Op.getValueType();
10662 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10663 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10664 assert((DstVT == MVT::i64 ||
10665 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10666 "Unexpected custom BITCAST");
10667 // i64 <=> MMX conversions are Legal.
10668 if (SrcVT==MVT::i64 && DstVT.isVector())
10670 if (DstVT==MVT::i64 && SrcVT.isVector())
10672 // MMX <=> MMX conversions are Legal.
10673 if (SrcVT.isVector() && DstVT.isVector())
10675 // All other conversions need to be expanded.
10679 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10680 SDNode *Node = Op.getNode();
10681 DebugLoc dl = Node->getDebugLoc();
10682 EVT T = Node->getValueType(0);
10683 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10684 DAG.getConstant(0, T), Node->getOperand(2));
10685 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10686 cast<AtomicSDNode>(Node)->getMemoryVT(),
10687 Node->getOperand(0),
10688 Node->getOperand(1), negOp,
10689 cast<AtomicSDNode>(Node)->getSrcValue(),
10690 cast<AtomicSDNode>(Node)->getAlignment(),
10691 cast<AtomicSDNode>(Node)->getOrdering(),
10692 cast<AtomicSDNode>(Node)->getSynchScope());
10695 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10696 SDNode *Node = Op.getNode();
10697 DebugLoc dl = Node->getDebugLoc();
10698 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10700 // Convert seq_cst store -> xchg
10701 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10702 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10703 // (The only way to get a 16-byte store is cmpxchg16b)
10704 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10705 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10706 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10707 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10708 cast<AtomicSDNode>(Node)->getMemoryVT(),
10709 Node->getOperand(0),
10710 Node->getOperand(1), Node->getOperand(2),
10711 cast<AtomicSDNode>(Node)->getMemOperand(),
10712 cast<AtomicSDNode>(Node)->getOrdering(),
10713 cast<AtomicSDNode>(Node)->getSynchScope());
10714 return Swap.getValue(1);
10716 // Other atomic stores have a simple pattern.
10720 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10721 EVT VT = Op.getNode()->getValueType(0);
10723 // Let legalize expand this if it isn't a legal type yet.
10724 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10727 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10730 bool ExtraOp = false;
10731 switch (Op.getOpcode()) {
10732 default: llvm_unreachable("Invalid code");
10733 case ISD::ADDC: Opc = X86ISD::ADD; break;
10734 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10735 case ISD::SUBC: Opc = X86ISD::SUB; break;
10736 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10740 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10742 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10743 Op.getOperand(1), Op.getOperand(2));
10746 /// LowerOperation - Provide custom lowering hooks for some operations.
10748 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10749 switch (Op.getOpcode()) {
10750 default: llvm_unreachable("Should not custom lower this!");
10751 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10752 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10753 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10754 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10755 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10756 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10757 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10758 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10759 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10760 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10761 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10762 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10763 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10764 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10765 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10766 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10767 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10768 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10769 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10770 case ISD::SHL_PARTS:
10771 case ISD::SRA_PARTS:
10772 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10773 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10774 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10775 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10776 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10777 case ISD::FABS: return LowerFABS(Op, DAG);
10778 case ISD::FNEG: return LowerFNEG(Op, DAG);
10779 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10780 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10781 case ISD::SETCC: return LowerSETCC(Op, DAG);
10782 case ISD::SELECT: return LowerSELECT(Op, DAG);
10783 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10784 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10785 case ISD::VASTART: return LowerVASTART(Op, DAG);
10786 case ISD::VAARG: return LowerVAARG(Op, DAG);
10787 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10788 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10789 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10790 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10791 case ISD::FRAME_TO_ARGS_OFFSET:
10792 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10793 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10794 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10795 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10796 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10797 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10798 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10799 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10800 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10801 case ISD::MUL: return LowerMUL(Op, DAG);
10804 case ISD::SHL: return LowerShift(Op, DAG);
10810 case ISD::UMULO: return LowerXALUO(Op, DAG);
10811 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10812 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10816 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10817 case ISD::ADD: return LowerADD(Op, DAG);
10818 case ISD::SUB: return LowerSUB(Op, DAG);
10822 static void ReplaceATOMIC_LOAD(SDNode *Node,
10823 SmallVectorImpl<SDValue> &Results,
10824 SelectionDAG &DAG) {
10825 DebugLoc dl = Node->getDebugLoc();
10826 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10828 // Convert wide load -> cmpxchg8b/cmpxchg16b
10829 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10830 // (The only way to get a 16-byte load is cmpxchg16b)
10831 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10832 SDValue Zero = DAG.getConstant(0, VT);
10833 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10834 Node->getOperand(0),
10835 Node->getOperand(1), Zero, Zero,
10836 cast<AtomicSDNode>(Node)->getMemOperand(),
10837 cast<AtomicSDNode>(Node)->getOrdering(),
10838 cast<AtomicSDNode>(Node)->getSynchScope());
10839 Results.push_back(Swap.getValue(0));
10840 Results.push_back(Swap.getValue(1));
10843 void X86TargetLowering::
10844 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10845 SelectionDAG &DAG, unsigned NewOp) const {
10846 DebugLoc dl = Node->getDebugLoc();
10847 assert (Node->getValueType(0) == MVT::i64 &&
10848 "Only know how to expand i64 atomics");
10850 SDValue Chain = Node->getOperand(0);
10851 SDValue In1 = Node->getOperand(1);
10852 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10853 Node->getOperand(2), DAG.getIntPtrConstant(0));
10854 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10855 Node->getOperand(2), DAG.getIntPtrConstant(1));
10856 SDValue Ops[] = { Chain, In1, In2L, In2H };
10857 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10859 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10860 cast<MemSDNode>(Node)->getMemOperand());
10861 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10862 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10863 Results.push_back(Result.getValue(2));
10866 /// ReplaceNodeResults - Replace a node with an illegal result type
10867 /// with a new node built out of custom code.
10868 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10869 SmallVectorImpl<SDValue>&Results,
10870 SelectionDAG &DAG) const {
10871 DebugLoc dl = N->getDebugLoc();
10872 switch (N->getOpcode()) {
10874 llvm_unreachable("Do not know how to custom type legalize this operation!");
10875 case ISD::SIGN_EXTEND_INREG:
10880 // We don't want to expand or promote these.
10882 case ISD::FP_TO_SINT:
10883 case ISD::FP_TO_UINT: {
10884 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
10886 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
10889 std::pair<SDValue,SDValue> Vals =
10890 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
10891 SDValue FIST = Vals.first, StackSlot = Vals.second;
10892 if (FIST.getNode() != 0) {
10893 EVT VT = N->getValueType(0);
10894 // Return a load from the stack slot.
10895 if (StackSlot.getNode() != 0)
10896 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10897 MachinePointerInfo(),
10898 false, false, false, 0));
10900 Results.push_back(FIST);
10904 case ISD::READCYCLECOUNTER: {
10905 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10906 SDValue TheChain = N->getOperand(0);
10907 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10908 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10910 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10912 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10913 SDValue Ops[] = { eax, edx };
10914 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10915 Results.push_back(edx.getValue(1));
10918 case ISD::ATOMIC_CMP_SWAP: {
10919 EVT T = N->getValueType(0);
10920 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10921 bool Regs64bit = T == MVT::i128;
10922 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10923 SDValue cpInL, cpInH;
10924 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10925 DAG.getConstant(0, HalfT));
10926 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10927 DAG.getConstant(1, HalfT));
10928 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10929 Regs64bit ? X86::RAX : X86::EAX,
10931 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10932 Regs64bit ? X86::RDX : X86::EDX,
10933 cpInH, cpInL.getValue(1));
10934 SDValue swapInL, swapInH;
10935 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10936 DAG.getConstant(0, HalfT));
10937 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10938 DAG.getConstant(1, HalfT));
10939 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10940 Regs64bit ? X86::RBX : X86::EBX,
10941 swapInL, cpInH.getValue(1));
10942 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10943 Regs64bit ? X86::RCX : X86::ECX,
10944 swapInH, swapInL.getValue(1));
10945 SDValue Ops[] = { swapInH.getValue(0),
10947 swapInH.getValue(1) };
10948 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10949 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10950 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10951 X86ISD::LCMPXCHG8_DAG;
10952 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10954 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10955 Regs64bit ? X86::RAX : X86::EAX,
10956 HalfT, Result.getValue(1));
10957 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10958 Regs64bit ? X86::RDX : X86::EDX,
10959 HalfT, cpOutL.getValue(2));
10960 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10961 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10962 Results.push_back(cpOutH.getValue(1));
10965 case ISD::ATOMIC_LOAD_ADD:
10966 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10968 case ISD::ATOMIC_LOAD_AND:
10969 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10971 case ISD::ATOMIC_LOAD_NAND:
10972 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10974 case ISD::ATOMIC_LOAD_OR:
10975 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10977 case ISD::ATOMIC_LOAD_SUB:
10978 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10980 case ISD::ATOMIC_LOAD_XOR:
10981 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10983 case ISD::ATOMIC_SWAP:
10984 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10986 case ISD::ATOMIC_LOAD:
10987 ReplaceATOMIC_LOAD(N, Results, DAG);
10991 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10993 default: return NULL;
10994 case X86ISD::BSF: return "X86ISD::BSF";
10995 case X86ISD::BSR: return "X86ISD::BSR";
10996 case X86ISD::SHLD: return "X86ISD::SHLD";
10997 case X86ISD::SHRD: return "X86ISD::SHRD";
10998 case X86ISD::FAND: return "X86ISD::FAND";
10999 case X86ISD::FOR: return "X86ISD::FOR";
11000 case X86ISD::FXOR: return "X86ISD::FXOR";
11001 case X86ISD::FSRL: return "X86ISD::FSRL";
11002 case X86ISD::FILD: return "X86ISD::FILD";
11003 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11004 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11005 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11006 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11007 case X86ISD::FLD: return "X86ISD::FLD";
11008 case X86ISD::FST: return "X86ISD::FST";
11009 case X86ISD::CALL: return "X86ISD::CALL";
11010 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11011 case X86ISD::BT: return "X86ISD::BT";
11012 case X86ISD::CMP: return "X86ISD::CMP";
11013 case X86ISD::COMI: return "X86ISD::COMI";
11014 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11015 case X86ISD::SETCC: return "X86ISD::SETCC";
11016 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11017 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11018 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11019 case X86ISD::CMOV: return "X86ISD::CMOV";
11020 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11021 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11022 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11023 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11024 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11025 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11026 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11027 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11028 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11029 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11030 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11031 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11032 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11033 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11034 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11035 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11036 case X86ISD::HADD: return "X86ISD::HADD";
11037 case X86ISD::HSUB: return "X86ISD::HSUB";
11038 case X86ISD::FHADD: return "X86ISD::FHADD";
11039 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11040 case X86ISD::FMAX: return "X86ISD::FMAX";
11041 case X86ISD::FMIN: return "X86ISD::FMIN";
11042 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11043 case X86ISD::FRCP: return "X86ISD::FRCP";
11044 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11045 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11046 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11047 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11048 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11049 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11050 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11051 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11052 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11053 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11054 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11055 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11056 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11057 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11058 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11059 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11060 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11061 case X86ISD::VSHL: return "X86ISD::VSHL";
11062 case X86ISD::VSRL: return "X86ISD::VSRL";
11063 case X86ISD::VSRA: return "X86ISD::VSRA";
11064 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11065 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11066 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11067 case X86ISD::CMPP: return "X86ISD::CMPP";
11068 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11069 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11070 case X86ISD::ADD: return "X86ISD::ADD";
11071 case X86ISD::SUB: return "X86ISD::SUB";
11072 case X86ISD::ADC: return "X86ISD::ADC";
11073 case X86ISD::SBB: return "X86ISD::SBB";
11074 case X86ISD::SMUL: return "X86ISD::SMUL";
11075 case X86ISD::UMUL: return "X86ISD::UMUL";
11076 case X86ISD::INC: return "X86ISD::INC";
11077 case X86ISD::DEC: return "X86ISD::DEC";
11078 case X86ISD::OR: return "X86ISD::OR";
11079 case X86ISD::XOR: return "X86ISD::XOR";
11080 case X86ISD::AND: return "X86ISD::AND";
11081 case X86ISD::ANDN: return "X86ISD::ANDN";
11082 case X86ISD::BLSI: return "X86ISD::BLSI";
11083 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11084 case X86ISD::BLSR: return "X86ISD::BLSR";
11085 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11086 case X86ISD::PTEST: return "X86ISD::PTEST";
11087 case X86ISD::TESTP: return "X86ISD::TESTP";
11088 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11089 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11090 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11091 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11092 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11093 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11094 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11095 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11096 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11097 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11098 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11099 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11100 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11101 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11102 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11103 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11104 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11105 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11106 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11107 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11108 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11109 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11110 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11111 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11112 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11113 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11114 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11118 // isLegalAddressingMode - Return true if the addressing mode represented
11119 // by AM is legal for this target, for a load/store of the specified type.
11120 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11122 // X86 supports extremely general addressing modes.
11123 CodeModel::Model M = getTargetMachine().getCodeModel();
11124 Reloc::Model R = getTargetMachine().getRelocationModel();
11126 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11127 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11132 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11134 // If a reference to this global requires an extra load, we can't fold it.
11135 if (isGlobalStubReference(GVFlags))
11138 // If BaseGV requires a register for the PIC base, we cannot also have a
11139 // BaseReg specified.
11140 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11143 // If lower 4G is not available, then we must use rip-relative addressing.
11144 if ((M != CodeModel::Small || R != Reloc::Static) &&
11145 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11149 switch (AM.Scale) {
11155 // These scales always work.
11160 // These scales are formed with basereg+scalereg. Only accept if there is
11165 default: // Other stuff never works.
11173 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11174 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11176 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11177 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11178 if (NumBits1 <= NumBits2)
11183 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11184 if (!VT1.isInteger() || !VT2.isInteger())
11186 unsigned NumBits1 = VT1.getSizeInBits();
11187 unsigned NumBits2 = VT2.getSizeInBits();
11188 if (NumBits1 <= NumBits2)
11193 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11194 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11195 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11198 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11199 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11200 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11203 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11204 // i16 instructions are longer (0x66 prefix) and potentially slower.
11205 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11208 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11209 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11210 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11211 /// are assumed to be legal.
11213 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11215 // Very little shuffling can be done for 64-bit vectors right now.
11216 if (VT.getSizeInBits() == 64)
11219 // FIXME: pshufb, blends, shifts.
11220 return (VT.getVectorNumElements() == 2 ||
11221 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11222 isMOVLMask(M, VT) ||
11223 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11224 isPSHUFDMask(M, VT) ||
11225 isPSHUFHWMask(M, VT) ||
11226 isPSHUFLWMask(M, VT) ||
11227 isPALIGNRMask(M, VT, Subtarget) ||
11228 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11229 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11230 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11231 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11235 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11237 unsigned NumElts = VT.getVectorNumElements();
11238 // FIXME: This collection of masks seems suspect.
11241 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11242 return (isMOVLMask(Mask, VT) ||
11243 isCommutedMOVLMask(Mask, VT, true) ||
11244 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11245 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11250 //===----------------------------------------------------------------------===//
11251 // X86 Scheduler Hooks
11252 //===----------------------------------------------------------------------===//
11254 // private utility function
11255 MachineBasicBlock *
11256 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11257 MachineBasicBlock *MBB,
11264 const TargetRegisterClass *RC,
11265 bool invSrc) const {
11266 // For the atomic bitwise operator, we generate
11269 // ld t1 = [bitinstr.addr]
11270 // op t2 = t1, [bitinstr.val]
11272 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11274 // fallthrough -->nextMBB
11275 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11276 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11277 MachineFunction::iterator MBBIter = MBB;
11280 /// First build the CFG
11281 MachineFunction *F = MBB->getParent();
11282 MachineBasicBlock *thisMBB = MBB;
11283 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11284 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11285 F->insert(MBBIter, newMBB);
11286 F->insert(MBBIter, nextMBB);
11288 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11289 nextMBB->splice(nextMBB->begin(), thisMBB,
11290 llvm::next(MachineBasicBlock::iterator(bInstr)),
11292 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11294 // Update thisMBB to fall through to newMBB
11295 thisMBB->addSuccessor(newMBB);
11297 // newMBB jumps to itself and fall through to nextMBB
11298 newMBB->addSuccessor(nextMBB);
11299 newMBB->addSuccessor(newMBB);
11301 // Insert instructions into newMBB based on incoming instruction
11302 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11303 "unexpected number of operands");
11304 DebugLoc dl = bInstr->getDebugLoc();
11305 MachineOperand& destOper = bInstr->getOperand(0);
11306 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11307 int numArgs = bInstr->getNumOperands() - 1;
11308 for (int i=0; i < numArgs; ++i)
11309 argOpers[i] = &bInstr->getOperand(i+1);
11311 // x86 address has 4 operands: base, index, scale, and displacement
11312 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11313 int valArgIndx = lastAddrIndx + 1;
11315 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11316 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11317 for (int i=0; i <= lastAddrIndx; ++i)
11318 (*MIB).addOperand(*argOpers[i]);
11320 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11322 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11327 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11328 assert((argOpers[valArgIndx]->isReg() ||
11329 argOpers[valArgIndx]->isImm()) &&
11330 "invalid operand");
11331 if (argOpers[valArgIndx]->isReg())
11332 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11334 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11336 (*MIB).addOperand(*argOpers[valArgIndx]);
11338 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11341 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11342 for (int i=0; i <= lastAddrIndx; ++i)
11343 (*MIB).addOperand(*argOpers[i]);
11345 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11346 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11347 bInstr->memoperands_end());
11349 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11350 MIB.addReg(EAXreg);
11353 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11355 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11359 // private utility function: 64 bit atomics on 32 bit host.
11360 MachineBasicBlock *
11361 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11362 MachineBasicBlock *MBB,
11367 bool invSrc) const {
11368 // For the atomic bitwise operator, we generate
11369 // thisMBB (instructions are in pairs, except cmpxchg8b)
11370 // ld t1,t2 = [bitinstr.addr]
11372 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11373 // op t5, t6 <- out1, out2, [bitinstr.val]
11374 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11375 // mov ECX, EBX <- t5, t6
11376 // mov EAX, EDX <- t1, t2
11377 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11378 // mov t3, t4 <- EAX, EDX
11380 // result in out1, out2
11381 // fallthrough -->nextMBB
11383 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11384 const unsigned LoadOpc = X86::MOV32rm;
11385 const unsigned NotOpc = X86::NOT32r;
11386 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11387 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11388 MachineFunction::iterator MBBIter = MBB;
11391 /// First build the CFG
11392 MachineFunction *F = MBB->getParent();
11393 MachineBasicBlock *thisMBB = MBB;
11394 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11395 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11396 F->insert(MBBIter, newMBB);
11397 F->insert(MBBIter, nextMBB);
11399 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11400 nextMBB->splice(nextMBB->begin(), thisMBB,
11401 llvm::next(MachineBasicBlock::iterator(bInstr)),
11403 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11405 // Update thisMBB to fall through to newMBB
11406 thisMBB->addSuccessor(newMBB);
11408 // newMBB jumps to itself and fall through to nextMBB
11409 newMBB->addSuccessor(nextMBB);
11410 newMBB->addSuccessor(newMBB);
11412 DebugLoc dl = bInstr->getDebugLoc();
11413 // Insert instructions into newMBB based on incoming instruction
11414 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11415 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11416 "unexpected number of operands");
11417 MachineOperand& dest1Oper = bInstr->getOperand(0);
11418 MachineOperand& dest2Oper = bInstr->getOperand(1);
11419 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11420 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11421 argOpers[i] = &bInstr->getOperand(i+2);
11423 // We use some of the operands multiple times, so conservatively just
11424 // clear any kill flags that might be present.
11425 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11426 argOpers[i]->setIsKill(false);
11429 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11430 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11432 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11433 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11434 for (int i=0; i <= lastAddrIndx; ++i)
11435 (*MIB).addOperand(*argOpers[i]);
11436 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11437 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11438 // add 4 to displacement.
11439 for (int i=0; i <= lastAddrIndx-2; ++i)
11440 (*MIB).addOperand(*argOpers[i]);
11441 MachineOperand newOp3 = *(argOpers[3]);
11442 if (newOp3.isImm())
11443 newOp3.setImm(newOp3.getImm()+4);
11445 newOp3.setOffset(newOp3.getOffset()+4);
11446 (*MIB).addOperand(newOp3);
11447 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11449 // t3/4 are defined later, at the bottom of the loop
11450 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11451 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11452 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11453 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11454 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11455 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11457 // The subsequent operations should be using the destination registers of
11458 //the PHI instructions.
11460 t1 = F->getRegInfo().createVirtualRegister(RC);
11461 t2 = F->getRegInfo().createVirtualRegister(RC);
11462 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11463 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11465 t1 = dest1Oper.getReg();
11466 t2 = dest2Oper.getReg();
11469 int valArgIndx = lastAddrIndx + 1;
11470 assert((argOpers[valArgIndx]->isReg() ||
11471 argOpers[valArgIndx]->isImm()) &&
11472 "invalid operand");
11473 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11474 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11475 if (argOpers[valArgIndx]->isReg())
11476 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11478 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11479 if (regOpcL != X86::MOV32rr)
11481 (*MIB).addOperand(*argOpers[valArgIndx]);
11482 assert(argOpers[valArgIndx + 1]->isReg() ==
11483 argOpers[valArgIndx]->isReg());
11484 assert(argOpers[valArgIndx + 1]->isImm() ==
11485 argOpers[valArgIndx]->isImm());
11486 if (argOpers[valArgIndx + 1]->isReg())
11487 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11489 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11490 if (regOpcH != X86::MOV32rr)
11492 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11494 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11496 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11499 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11501 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11504 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11505 for (int i=0; i <= lastAddrIndx; ++i)
11506 (*MIB).addOperand(*argOpers[i]);
11508 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11509 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11510 bInstr->memoperands_end());
11512 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11513 MIB.addReg(X86::EAX);
11514 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11515 MIB.addReg(X86::EDX);
11518 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11520 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11524 // private utility function
11525 MachineBasicBlock *
11526 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11527 MachineBasicBlock *MBB,
11528 unsigned cmovOpc) const {
11529 // For the atomic min/max operator, we generate
11532 // ld t1 = [min/max.addr]
11533 // mov t2 = [min/max.val]
11535 // cmov[cond] t2 = t1
11537 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11539 // fallthrough -->nextMBB
11541 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11542 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11543 MachineFunction::iterator MBBIter = MBB;
11546 /// First build the CFG
11547 MachineFunction *F = MBB->getParent();
11548 MachineBasicBlock *thisMBB = MBB;
11549 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11550 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11551 F->insert(MBBIter, newMBB);
11552 F->insert(MBBIter, nextMBB);
11554 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11555 nextMBB->splice(nextMBB->begin(), thisMBB,
11556 llvm::next(MachineBasicBlock::iterator(mInstr)),
11558 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11560 // Update thisMBB to fall through to newMBB
11561 thisMBB->addSuccessor(newMBB);
11563 // newMBB jumps to newMBB and fall through to nextMBB
11564 newMBB->addSuccessor(nextMBB);
11565 newMBB->addSuccessor(newMBB);
11567 DebugLoc dl = mInstr->getDebugLoc();
11568 // Insert instructions into newMBB based on incoming instruction
11569 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11570 "unexpected number of operands");
11571 MachineOperand& destOper = mInstr->getOperand(0);
11572 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11573 int numArgs = mInstr->getNumOperands() - 1;
11574 for (int i=0; i < numArgs; ++i)
11575 argOpers[i] = &mInstr->getOperand(i+1);
11577 // x86 address has 4 operands: base, index, scale, and displacement
11578 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11579 int valArgIndx = lastAddrIndx + 1;
11581 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11582 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11583 for (int i=0; i <= lastAddrIndx; ++i)
11584 (*MIB).addOperand(*argOpers[i]);
11586 // We only support register and immediate values
11587 assert((argOpers[valArgIndx]->isReg() ||
11588 argOpers[valArgIndx]->isImm()) &&
11589 "invalid operand");
11591 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11592 if (argOpers[valArgIndx]->isReg())
11593 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11595 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11596 (*MIB).addOperand(*argOpers[valArgIndx]);
11598 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11601 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11606 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11607 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11611 // Cmp and exchange if none has modified the memory location
11612 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11613 for (int i=0; i <= lastAddrIndx; ++i)
11614 (*MIB).addOperand(*argOpers[i]);
11616 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11617 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11618 mInstr->memoperands_end());
11620 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11621 MIB.addReg(X86::EAX);
11624 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11626 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11630 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11631 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11632 // in the .td file.
11633 MachineBasicBlock *
11634 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11635 unsigned numArgs, bool memArg) const {
11636 assert(Subtarget->hasSSE42() &&
11637 "Target must have SSE4.2 or AVX features enabled");
11639 DebugLoc dl = MI->getDebugLoc();
11640 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11642 if (!Subtarget->hasAVX()) {
11644 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11646 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11649 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11651 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11654 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11655 for (unsigned i = 0; i < numArgs; ++i) {
11656 MachineOperand &Op = MI->getOperand(i+1);
11657 if (!(Op.isReg() && Op.isImplicit()))
11658 MIB.addOperand(Op);
11660 BuildMI(*BB, MI, dl,
11661 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11662 MI->getOperand(0).getReg())
11663 .addReg(X86::XMM0);
11665 MI->eraseFromParent();
11669 MachineBasicBlock *
11670 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11671 DebugLoc dl = MI->getDebugLoc();
11672 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11674 // Address into RAX/EAX, other two args into ECX, EDX.
11675 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11676 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11677 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11678 for (int i = 0; i < X86::AddrNumOperands; ++i)
11679 MIB.addOperand(MI->getOperand(i));
11681 unsigned ValOps = X86::AddrNumOperands;
11682 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11683 .addReg(MI->getOperand(ValOps).getReg());
11684 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11685 .addReg(MI->getOperand(ValOps+1).getReg());
11687 // The instruction doesn't actually take any operands though.
11688 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11690 MI->eraseFromParent(); // The pseudo is gone now.
11694 MachineBasicBlock *
11695 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11696 DebugLoc dl = MI->getDebugLoc();
11697 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11699 // First arg in ECX, the second in EAX.
11700 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11701 .addReg(MI->getOperand(0).getReg());
11702 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11703 .addReg(MI->getOperand(1).getReg());
11705 // The instruction doesn't actually take any operands though.
11706 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11708 MI->eraseFromParent(); // The pseudo is gone now.
11712 MachineBasicBlock *
11713 X86TargetLowering::EmitVAARG64WithCustomInserter(
11715 MachineBasicBlock *MBB) const {
11716 // Emit va_arg instruction on X86-64.
11718 // Operands to this pseudo-instruction:
11719 // 0 ) Output : destination address (reg)
11720 // 1-5) Input : va_list address (addr, i64mem)
11721 // 6 ) ArgSize : Size (in bytes) of vararg type
11722 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11723 // 8 ) Align : Alignment of type
11724 // 9 ) EFLAGS (implicit-def)
11726 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11727 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11729 unsigned DestReg = MI->getOperand(0).getReg();
11730 MachineOperand &Base = MI->getOperand(1);
11731 MachineOperand &Scale = MI->getOperand(2);
11732 MachineOperand &Index = MI->getOperand(3);
11733 MachineOperand &Disp = MI->getOperand(4);
11734 MachineOperand &Segment = MI->getOperand(5);
11735 unsigned ArgSize = MI->getOperand(6).getImm();
11736 unsigned ArgMode = MI->getOperand(7).getImm();
11737 unsigned Align = MI->getOperand(8).getImm();
11739 // Memory Reference
11740 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11741 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11742 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11744 // Machine Information
11745 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11746 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11747 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11748 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11749 DebugLoc DL = MI->getDebugLoc();
11751 // struct va_list {
11754 // i64 overflow_area (address)
11755 // i64 reg_save_area (address)
11757 // sizeof(va_list) = 24
11758 // alignment(va_list) = 8
11760 unsigned TotalNumIntRegs = 6;
11761 unsigned TotalNumXMMRegs = 8;
11762 bool UseGPOffset = (ArgMode == 1);
11763 bool UseFPOffset = (ArgMode == 2);
11764 unsigned MaxOffset = TotalNumIntRegs * 8 +
11765 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11767 /* Align ArgSize to a multiple of 8 */
11768 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11769 bool NeedsAlign = (Align > 8);
11771 MachineBasicBlock *thisMBB = MBB;
11772 MachineBasicBlock *overflowMBB;
11773 MachineBasicBlock *offsetMBB;
11774 MachineBasicBlock *endMBB;
11776 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11777 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11778 unsigned OffsetReg = 0;
11780 if (!UseGPOffset && !UseFPOffset) {
11781 // If we only pull from the overflow region, we don't create a branch.
11782 // We don't need to alter control flow.
11783 OffsetDestReg = 0; // unused
11784 OverflowDestReg = DestReg;
11787 overflowMBB = thisMBB;
11790 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11791 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11792 // If not, pull from overflow_area. (branch to overflowMBB)
11797 // offsetMBB overflowMBB
11802 // Registers for the PHI in endMBB
11803 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11804 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11806 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11807 MachineFunction *MF = MBB->getParent();
11808 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11809 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11810 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11812 MachineFunction::iterator MBBIter = MBB;
11815 // Insert the new basic blocks
11816 MF->insert(MBBIter, offsetMBB);
11817 MF->insert(MBBIter, overflowMBB);
11818 MF->insert(MBBIter, endMBB);
11820 // Transfer the remainder of MBB and its successor edges to endMBB.
11821 endMBB->splice(endMBB->begin(), thisMBB,
11822 llvm::next(MachineBasicBlock::iterator(MI)),
11824 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11826 // Make offsetMBB and overflowMBB successors of thisMBB
11827 thisMBB->addSuccessor(offsetMBB);
11828 thisMBB->addSuccessor(overflowMBB);
11830 // endMBB is a successor of both offsetMBB and overflowMBB
11831 offsetMBB->addSuccessor(endMBB);
11832 overflowMBB->addSuccessor(endMBB);
11834 // Load the offset value into a register
11835 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11836 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11840 .addDisp(Disp, UseFPOffset ? 4 : 0)
11841 .addOperand(Segment)
11842 .setMemRefs(MMOBegin, MMOEnd);
11844 // Check if there is enough room left to pull this argument.
11845 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11847 .addImm(MaxOffset + 8 - ArgSizeA8);
11849 // Branch to "overflowMBB" if offset >= max
11850 // Fall through to "offsetMBB" otherwise
11851 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11852 .addMBB(overflowMBB);
11855 // In offsetMBB, emit code to use the reg_save_area.
11857 assert(OffsetReg != 0);
11859 // Read the reg_save_area address.
11860 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11861 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11866 .addOperand(Segment)
11867 .setMemRefs(MMOBegin, MMOEnd);
11869 // Zero-extend the offset
11870 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11871 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11874 .addImm(X86::sub_32bit);
11876 // Add the offset to the reg_save_area to get the final address.
11877 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11878 .addReg(OffsetReg64)
11879 .addReg(RegSaveReg);
11881 // Compute the offset for the next argument
11882 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11883 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11885 .addImm(UseFPOffset ? 16 : 8);
11887 // Store it back into the va_list.
11888 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11892 .addDisp(Disp, UseFPOffset ? 4 : 0)
11893 .addOperand(Segment)
11894 .addReg(NextOffsetReg)
11895 .setMemRefs(MMOBegin, MMOEnd);
11898 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11903 // Emit code to use overflow area
11906 // Load the overflow_area address into a register.
11907 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11908 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11913 .addOperand(Segment)
11914 .setMemRefs(MMOBegin, MMOEnd);
11916 // If we need to align it, do so. Otherwise, just copy the address
11917 // to OverflowDestReg.
11919 // Align the overflow address
11920 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11921 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11923 // aligned_addr = (addr + (align-1)) & ~(align-1)
11924 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11925 .addReg(OverflowAddrReg)
11928 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11930 .addImm(~(uint64_t)(Align-1));
11932 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11933 .addReg(OverflowAddrReg);
11936 // Compute the next overflow address after this argument.
11937 // (the overflow address should be kept 8-byte aligned)
11938 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11939 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11940 .addReg(OverflowDestReg)
11941 .addImm(ArgSizeA8);
11943 // Store the new overflow address.
11944 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11949 .addOperand(Segment)
11950 .addReg(NextAddrReg)
11951 .setMemRefs(MMOBegin, MMOEnd);
11953 // If we branched, emit the PHI to the front of endMBB.
11955 BuildMI(*endMBB, endMBB->begin(), DL,
11956 TII->get(X86::PHI), DestReg)
11957 .addReg(OffsetDestReg).addMBB(offsetMBB)
11958 .addReg(OverflowDestReg).addMBB(overflowMBB);
11961 // Erase the pseudo instruction
11962 MI->eraseFromParent();
11967 MachineBasicBlock *
11968 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11970 MachineBasicBlock *MBB) const {
11971 // Emit code to save XMM registers to the stack. The ABI says that the
11972 // number of registers to save is given in %al, so it's theoretically
11973 // possible to do an indirect jump trick to avoid saving all of them,
11974 // however this code takes a simpler approach and just executes all
11975 // of the stores if %al is non-zero. It's less code, and it's probably
11976 // easier on the hardware branch predictor, and stores aren't all that
11977 // expensive anyway.
11979 // Create the new basic blocks. One block contains all the XMM stores,
11980 // and one block is the final destination regardless of whether any
11981 // stores were performed.
11982 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11983 MachineFunction *F = MBB->getParent();
11984 MachineFunction::iterator MBBIter = MBB;
11986 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11987 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11988 F->insert(MBBIter, XMMSaveMBB);
11989 F->insert(MBBIter, EndMBB);
11991 // Transfer the remainder of MBB and its successor edges to EndMBB.
11992 EndMBB->splice(EndMBB->begin(), MBB,
11993 llvm::next(MachineBasicBlock::iterator(MI)),
11995 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11997 // The original block will now fall through to the XMM save block.
11998 MBB->addSuccessor(XMMSaveMBB);
11999 // The XMMSaveMBB will fall through to the end block.
12000 XMMSaveMBB->addSuccessor(EndMBB);
12002 // Now add the instructions.
12003 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12004 DebugLoc DL = MI->getDebugLoc();
12006 unsigned CountReg = MI->getOperand(0).getReg();
12007 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12008 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12010 if (!Subtarget->isTargetWin64()) {
12011 // If %al is 0, branch around the XMM save block.
12012 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12013 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12014 MBB->addSuccessor(EndMBB);
12017 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12018 // In the XMM save block, save all the XMM argument registers.
12019 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12020 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12021 MachineMemOperand *MMO =
12022 F->getMachineMemOperand(
12023 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12024 MachineMemOperand::MOStore,
12025 /*Size=*/16, /*Align=*/16);
12026 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12027 .addFrameIndex(RegSaveFrameIndex)
12028 .addImm(/*Scale=*/1)
12029 .addReg(/*IndexReg=*/0)
12030 .addImm(/*Disp=*/Offset)
12031 .addReg(/*Segment=*/0)
12032 .addReg(MI->getOperand(i).getReg())
12033 .addMemOperand(MMO);
12036 MI->eraseFromParent(); // The pseudo instruction is gone now.
12041 // The EFLAGS operand of SelectItr might be missing a kill marker
12042 // because there were multiple uses of EFLAGS, and ISel didn't know
12043 // which to mark. Figure out whether SelectItr should have had a
12044 // kill marker, and set it if it should. Returns the correct kill
12046 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12047 MachineBasicBlock* BB,
12048 const TargetRegisterInfo* TRI) {
12049 // Scan forward through BB for a use/def of EFLAGS.
12050 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12051 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12052 const MachineInstr& mi = *miI;
12053 if (mi.readsRegister(X86::EFLAGS))
12055 if (mi.definesRegister(X86::EFLAGS))
12056 break; // Should have kill-flag - update below.
12059 // If we hit the end of the block, check whether EFLAGS is live into a
12061 if (miI == BB->end()) {
12062 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12063 sEnd = BB->succ_end();
12064 sItr != sEnd; ++sItr) {
12065 MachineBasicBlock* succ = *sItr;
12066 if (succ->isLiveIn(X86::EFLAGS))
12071 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12072 // out. SelectMI should have a kill flag on EFLAGS.
12073 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12077 MachineBasicBlock *
12078 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12079 MachineBasicBlock *BB) const {
12080 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12081 DebugLoc DL = MI->getDebugLoc();
12083 // To "insert" a SELECT_CC instruction, we actually have to insert the
12084 // diamond control-flow pattern. The incoming instruction knows the
12085 // destination vreg to set, the condition code register to branch on, the
12086 // true/false values to select between, and a branch opcode to use.
12087 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12088 MachineFunction::iterator It = BB;
12094 // cmpTY ccX, r1, r2
12096 // fallthrough --> copy0MBB
12097 MachineBasicBlock *thisMBB = BB;
12098 MachineFunction *F = BB->getParent();
12099 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12100 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12101 F->insert(It, copy0MBB);
12102 F->insert(It, sinkMBB);
12104 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12105 // live into the sink and copy blocks.
12106 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12107 if (!MI->killsRegister(X86::EFLAGS) &&
12108 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12109 copy0MBB->addLiveIn(X86::EFLAGS);
12110 sinkMBB->addLiveIn(X86::EFLAGS);
12113 // Transfer the remainder of BB and its successor edges to sinkMBB.
12114 sinkMBB->splice(sinkMBB->begin(), BB,
12115 llvm::next(MachineBasicBlock::iterator(MI)),
12117 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12119 // Add the true and fallthrough blocks as its successors.
12120 BB->addSuccessor(copy0MBB);
12121 BB->addSuccessor(sinkMBB);
12123 // Create the conditional branch instruction.
12125 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12126 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12129 // %FalseValue = ...
12130 // # fallthrough to sinkMBB
12131 copy0MBB->addSuccessor(sinkMBB);
12134 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12136 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12137 TII->get(X86::PHI), MI->getOperand(0).getReg())
12138 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12139 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12141 MI->eraseFromParent(); // The pseudo instruction is gone now.
12145 MachineBasicBlock *
12146 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12147 bool Is64Bit) const {
12148 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12149 DebugLoc DL = MI->getDebugLoc();
12150 MachineFunction *MF = BB->getParent();
12151 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12153 assert(getTargetMachine().Options.EnableSegmentedStacks);
12155 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12156 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12159 // ... [Till the alloca]
12160 // If stacklet is not large enough, jump to mallocMBB
12163 // Allocate by subtracting from RSP
12164 // Jump to continueMBB
12167 // Allocate by call to runtime
12171 // [rest of original BB]
12174 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12175 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12176 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12178 MachineRegisterInfo &MRI = MF->getRegInfo();
12179 const TargetRegisterClass *AddrRegClass =
12180 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12182 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12183 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12184 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12185 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12186 sizeVReg = MI->getOperand(1).getReg(),
12187 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12189 MachineFunction::iterator MBBIter = BB;
12192 MF->insert(MBBIter, bumpMBB);
12193 MF->insert(MBBIter, mallocMBB);
12194 MF->insert(MBBIter, continueMBB);
12196 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12197 (MachineBasicBlock::iterator(MI)), BB->end());
12198 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12200 // Add code to the main basic block to check if the stack limit has been hit,
12201 // and if so, jump to mallocMBB otherwise to bumpMBB.
12202 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12203 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12204 .addReg(tmpSPVReg).addReg(sizeVReg);
12205 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12206 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12207 .addReg(SPLimitVReg);
12208 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12210 // bumpMBB simply decreases the stack pointer, since we know the current
12211 // stacklet has enough space.
12212 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12213 .addReg(SPLimitVReg);
12214 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12215 .addReg(SPLimitVReg);
12216 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12218 // Calls into a routine in libgcc to allocate more space from the heap.
12219 const uint32_t *RegMask =
12220 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12222 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12224 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12225 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12226 .addRegMask(RegMask)
12227 .addReg(X86::RAX, RegState::ImplicitDefine);
12229 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12231 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12232 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12233 .addExternalSymbol("__morestack_allocate_stack_space")
12234 .addRegMask(RegMask)
12235 .addReg(X86::EAX, RegState::ImplicitDefine);
12239 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12242 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12243 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12244 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12246 // Set up the CFG correctly.
12247 BB->addSuccessor(bumpMBB);
12248 BB->addSuccessor(mallocMBB);
12249 mallocMBB->addSuccessor(continueMBB);
12250 bumpMBB->addSuccessor(continueMBB);
12252 // Take care of the PHI nodes.
12253 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12254 MI->getOperand(0).getReg())
12255 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12256 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12258 // Delete the original pseudo instruction.
12259 MI->eraseFromParent();
12262 return continueMBB;
12265 MachineBasicBlock *
12266 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12267 MachineBasicBlock *BB) const {
12268 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12269 DebugLoc DL = MI->getDebugLoc();
12271 assert(!Subtarget->isTargetEnvMacho());
12273 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12274 // non-trivial part is impdef of ESP.
12276 if (Subtarget->isTargetWin64()) {
12277 if (Subtarget->isTargetCygMing()) {
12278 // ___chkstk(Mingw64):
12279 // Clobbers R10, R11, RAX and EFLAGS.
12281 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12282 .addExternalSymbol("___chkstk")
12283 .addReg(X86::RAX, RegState::Implicit)
12284 .addReg(X86::RSP, RegState::Implicit)
12285 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12286 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12287 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12289 // __chkstk(MSVCRT): does not update stack pointer.
12290 // Clobbers R10, R11 and EFLAGS.
12291 // FIXME: RAX(allocated size) might be reused and not killed.
12292 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12293 .addExternalSymbol("__chkstk")
12294 .addReg(X86::RAX, RegState::Implicit)
12295 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12296 // RAX has the offset to subtracted from RSP.
12297 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12302 const char *StackProbeSymbol =
12303 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12305 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12306 .addExternalSymbol(StackProbeSymbol)
12307 .addReg(X86::EAX, RegState::Implicit)
12308 .addReg(X86::ESP, RegState::Implicit)
12309 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12310 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12311 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12314 MI->eraseFromParent(); // The pseudo instruction is gone now.
12318 MachineBasicBlock *
12319 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12320 MachineBasicBlock *BB) const {
12321 // This is pretty easy. We're taking the value that we received from
12322 // our load from the relocation, sticking it in either RDI (x86-64)
12323 // or EAX and doing an indirect call. The return value will then
12324 // be in the normal return register.
12325 const X86InstrInfo *TII
12326 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12327 DebugLoc DL = MI->getDebugLoc();
12328 MachineFunction *F = BB->getParent();
12330 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12331 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12333 // Get a register mask for the lowered call.
12334 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12335 // proper register mask.
12336 const uint32_t *RegMask =
12337 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12338 if (Subtarget->is64Bit()) {
12339 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12340 TII->get(X86::MOV64rm), X86::RDI)
12342 .addImm(0).addReg(0)
12343 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12344 MI->getOperand(3).getTargetFlags())
12346 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12347 addDirectMem(MIB, X86::RDI);
12348 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12349 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12350 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12351 TII->get(X86::MOV32rm), X86::EAX)
12353 .addImm(0).addReg(0)
12354 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12355 MI->getOperand(3).getTargetFlags())
12357 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12358 addDirectMem(MIB, X86::EAX);
12359 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12361 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12362 TII->get(X86::MOV32rm), X86::EAX)
12363 .addReg(TII->getGlobalBaseReg(F))
12364 .addImm(0).addReg(0)
12365 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12366 MI->getOperand(3).getTargetFlags())
12368 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12369 addDirectMem(MIB, X86::EAX);
12370 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12373 MI->eraseFromParent(); // The pseudo instruction is gone now.
12377 MachineBasicBlock *
12378 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12379 MachineBasicBlock *BB) const {
12380 switch (MI->getOpcode()) {
12381 default: llvm_unreachable("Unexpected instr type to insert");
12382 case X86::TAILJMPd64:
12383 case X86::TAILJMPr64:
12384 case X86::TAILJMPm64:
12385 llvm_unreachable("TAILJMP64 would not be touched here.");
12386 case X86::TCRETURNdi64:
12387 case X86::TCRETURNri64:
12388 case X86::TCRETURNmi64:
12390 case X86::WIN_ALLOCA:
12391 return EmitLoweredWinAlloca(MI, BB);
12392 case X86::SEG_ALLOCA_32:
12393 return EmitLoweredSegAlloca(MI, BB, false);
12394 case X86::SEG_ALLOCA_64:
12395 return EmitLoweredSegAlloca(MI, BB, true);
12396 case X86::TLSCall_32:
12397 case X86::TLSCall_64:
12398 return EmitLoweredTLSCall(MI, BB);
12399 case X86::CMOV_GR8:
12400 case X86::CMOV_FR32:
12401 case X86::CMOV_FR64:
12402 case X86::CMOV_V4F32:
12403 case X86::CMOV_V2F64:
12404 case X86::CMOV_V2I64:
12405 case X86::CMOV_V8F32:
12406 case X86::CMOV_V4F64:
12407 case X86::CMOV_V4I64:
12408 case X86::CMOV_GR16:
12409 case X86::CMOV_GR32:
12410 case X86::CMOV_RFP32:
12411 case X86::CMOV_RFP64:
12412 case X86::CMOV_RFP80:
12413 return EmitLoweredSelect(MI, BB);
12415 case X86::FP32_TO_INT16_IN_MEM:
12416 case X86::FP32_TO_INT32_IN_MEM:
12417 case X86::FP32_TO_INT64_IN_MEM:
12418 case X86::FP64_TO_INT16_IN_MEM:
12419 case X86::FP64_TO_INT32_IN_MEM:
12420 case X86::FP64_TO_INT64_IN_MEM:
12421 case X86::FP80_TO_INT16_IN_MEM:
12422 case X86::FP80_TO_INT32_IN_MEM:
12423 case X86::FP80_TO_INT64_IN_MEM: {
12424 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12425 DebugLoc DL = MI->getDebugLoc();
12427 // Change the floating point control register to use "round towards zero"
12428 // mode when truncating to an integer value.
12429 MachineFunction *F = BB->getParent();
12430 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12431 addFrameReference(BuildMI(*BB, MI, DL,
12432 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12434 // Load the old value of the high byte of the control word...
12436 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12437 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12440 // Set the high part to be round to zero...
12441 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12444 // Reload the modified control word now...
12445 addFrameReference(BuildMI(*BB, MI, DL,
12446 TII->get(X86::FLDCW16m)), CWFrameIdx);
12448 // Restore the memory image of control word to original value
12449 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12452 // Get the X86 opcode to use.
12454 switch (MI->getOpcode()) {
12455 default: llvm_unreachable("illegal opcode!");
12456 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12457 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12458 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12459 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12460 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12461 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12462 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12463 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12464 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12468 MachineOperand &Op = MI->getOperand(0);
12470 AM.BaseType = X86AddressMode::RegBase;
12471 AM.Base.Reg = Op.getReg();
12473 AM.BaseType = X86AddressMode::FrameIndexBase;
12474 AM.Base.FrameIndex = Op.getIndex();
12476 Op = MI->getOperand(1);
12478 AM.Scale = Op.getImm();
12479 Op = MI->getOperand(2);
12481 AM.IndexReg = Op.getImm();
12482 Op = MI->getOperand(3);
12483 if (Op.isGlobal()) {
12484 AM.GV = Op.getGlobal();
12486 AM.Disp = Op.getImm();
12488 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12489 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12491 // Reload the original control word now.
12492 addFrameReference(BuildMI(*BB, MI, DL,
12493 TII->get(X86::FLDCW16m)), CWFrameIdx);
12495 MI->eraseFromParent(); // The pseudo instruction is gone now.
12498 // String/text processing lowering.
12499 case X86::PCMPISTRM128REG:
12500 case X86::VPCMPISTRM128REG:
12501 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12502 case X86::PCMPISTRM128MEM:
12503 case X86::VPCMPISTRM128MEM:
12504 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12505 case X86::PCMPESTRM128REG:
12506 case X86::VPCMPESTRM128REG:
12507 return EmitPCMP(MI, BB, 5, false /* in mem */);
12508 case X86::PCMPESTRM128MEM:
12509 case X86::VPCMPESTRM128MEM:
12510 return EmitPCMP(MI, BB, 5, true /* in mem */);
12512 // Thread synchronization.
12514 return EmitMonitor(MI, BB);
12516 return EmitMwait(MI, BB);
12518 // Atomic Lowering.
12519 case X86::ATOMAND32:
12520 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12521 X86::AND32ri, X86::MOV32rm,
12523 X86::NOT32r, X86::EAX,
12524 X86::GR32RegisterClass);
12525 case X86::ATOMOR32:
12526 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12527 X86::OR32ri, X86::MOV32rm,
12529 X86::NOT32r, X86::EAX,
12530 X86::GR32RegisterClass);
12531 case X86::ATOMXOR32:
12532 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12533 X86::XOR32ri, X86::MOV32rm,
12535 X86::NOT32r, X86::EAX,
12536 X86::GR32RegisterClass);
12537 case X86::ATOMNAND32:
12538 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12539 X86::AND32ri, X86::MOV32rm,
12541 X86::NOT32r, X86::EAX,
12542 X86::GR32RegisterClass, true);
12543 case X86::ATOMMIN32:
12544 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12545 case X86::ATOMMAX32:
12546 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12547 case X86::ATOMUMIN32:
12548 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12549 case X86::ATOMUMAX32:
12550 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12552 case X86::ATOMAND16:
12553 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12554 X86::AND16ri, X86::MOV16rm,
12556 X86::NOT16r, X86::AX,
12557 X86::GR16RegisterClass);
12558 case X86::ATOMOR16:
12559 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12560 X86::OR16ri, X86::MOV16rm,
12562 X86::NOT16r, X86::AX,
12563 X86::GR16RegisterClass);
12564 case X86::ATOMXOR16:
12565 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12566 X86::XOR16ri, X86::MOV16rm,
12568 X86::NOT16r, X86::AX,
12569 X86::GR16RegisterClass);
12570 case X86::ATOMNAND16:
12571 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12572 X86::AND16ri, X86::MOV16rm,
12574 X86::NOT16r, X86::AX,
12575 X86::GR16RegisterClass, true);
12576 case X86::ATOMMIN16:
12577 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12578 case X86::ATOMMAX16:
12579 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12580 case X86::ATOMUMIN16:
12581 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12582 case X86::ATOMUMAX16:
12583 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12585 case X86::ATOMAND8:
12586 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12587 X86::AND8ri, X86::MOV8rm,
12589 X86::NOT8r, X86::AL,
12590 X86::GR8RegisterClass);
12592 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12593 X86::OR8ri, X86::MOV8rm,
12595 X86::NOT8r, X86::AL,
12596 X86::GR8RegisterClass);
12597 case X86::ATOMXOR8:
12598 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12599 X86::XOR8ri, X86::MOV8rm,
12601 X86::NOT8r, X86::AL,
12602 X86::GR8RegisterClass);
12603 case X86::ATOMNAND8:
12604 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12605 X86::AND8ri, X86::MOV8rm,
12607 X86::NOT8r, X86::AL,
12608 X86::GR8RegisterClass, true);
12609 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12610 // This group is for 64-bit host.
12611 case X86::ATOMAND64:
12612 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12613 X86::AND64ri32, X86::MOV64rm,
12615 X86::NOT64r, X86::RAX,
12616 X86::GR64RegisterClass);
12617 case X86::ATOMOR64:
12618 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12619 X86::OR64ri32, X86::MOV64rm,
12621 X86::NOT64r, X86::RAX,
12622 X86::GR64RegisterClass);
12623 case X86::ATOMXOR64:
12624 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12625 X86::XOR64ri32, X86::MOV64rm,
12627 X86::NOT64r, X86::RAX,
12628 X86::GR64RegisterClass);
12629 case X86::ATOMNAND64:
12630 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12631 X86::AND64ri32, X86::MOV64rm,
12633 X86::NOT64r, X86::RAX,
12634 X86::GR64RegisterClass, true);
12635 case X86::ATOMMIN64:
12636 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12637 case X86::ATOMMAX64:
12638 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12639 case X86::ATOMUMIN64:
12640 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12641 case X86::ATOMUMAX64:
12642 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12644 // This group does 64-bit operations on a 32-bit host.
12645 case X86::ATOMAND6432:
12646 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12647 X86::AND32rr, X86::AND32rr,
12648 X86::AND32ri, X86::AND32ri,
12650 case X86::ATOMOR6432:
12651 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12652 X86::OR32rr, X86::OR32rr,
12653 X86::OR32ri, X86::OR32ri,
12655 case X86::ATOMXOR6432:
12656 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12657 X86::XOR32rr, X86::XOR32rr,
12658 X86::XOR32ri, X86::XOR32ri,
12660 case X86::ATOMNAND6432:
12661 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12662 X86::AND32rr, X86::AND32rr,
12663 X86::AND32ri, X86::AND32ri,
12665 case X86::ATOMADD6432:
12666 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12667 X86::ADD32rr, X86::ADC32rr,
12668 X86::ADD32ri, X86::ADC32ri,
12670 case X86::ATOMSUB6432:
12671 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12672 X86::SUB32rr, X86::SBB32rr,
12673 X86::SUB32ri, X86::SBB32ri,
12675 case X86::ATOMSWAP6432:
12676 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12677 X86::MOV32rr, X86::MOV32rr,
12678 X86::MOV32ri, X86::MOV32ri,
12680 case X86::VASTART_SAVE_XMM_REGS:
12681 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12683 case X86::VAARG_64:
12684 return EmitVAARG64WithCustomInserter(MI, BB);
12688 //===----------------------------------------------------------------------===//
12689 // X86 Optimization Hooks
12690 //===----------------------------------------------------------------------===//
12692 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12696 const SelectionDAG &DAG,
12697 unsigned Depth) const {
12698 unsigned Opc = Op.getOpcode();
12699 assert((Opc >= ISD::BUILTIN_OP_END ||
12700 Opc == ISD::INTRINSIC_WO_CHAIN ||
12701 Opc == ISD::INTRINSIC_W_CHAIN ||
12702 Opc == ISD::INTRINSIC_VOID) &&
12703 "Should use MaskedValueIsZero if you don't know whether Op"
12704 " is a target node!");
12706 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12720 // These nodes' second result is a boolean.
12721 if (Op.getResNo() == 0)
12724 case X86ISD::SETCC:
12725 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12726 Mask.getBitWidth() - 1);
12728 case ISD::INTRINSIC_WO_CHAIN: {
12729 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12730 unsigned NumLoBits = 0;
12733 case Intrinsic::x86_sse_movmsk_ps:
12734 case Intrinsic::x86_avx_movmsk_ps_256:
12735 case Intrinsic::x86_sse2_movmsk_pd:
12736 case Intrinsic::x86_avx_movmsk_pd_256:
12737 case Intrinsic::x86_mmx_pmovmskb:
12738 case Intrinsic::x86_sse2_pmovmskb_128:
12739 case Intrinsic::x86_avx2_pmovmskb: {
12740 // High bits of movmskp{s|d}, pmovmskb are known zero.
12742 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12743 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12744 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12745 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12746 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12747 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12748 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12749 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12751 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12752 Mask.getBitWidth() - NumLoBits);
12761 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12762 unsigned Depth) const {
12763 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12764 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12765 return Op.getValueType().getScalarType().getSizeInBits();
12771 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12772 /// node is a GlobalAddress + offset.
12773 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12774 const GlobalValue* &GA,
12775 int64_t &Offset) const {
12776 if (N->getOpcode() == X86ISD::Wrapper) {
12777 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12778 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12779 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12783 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12786 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12787 /// same as extracting the high 128-bit part of 256-bit vector and then
12788 /// inserting the result into the low part of a new 256-bit vector
12789 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12790 EVT VT = SVOp->getValueType(0);
12791 int NumElems = VT.getVectorNumElements();
12793 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12794 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12795 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12796 SVOp->getMaskElt(j) >= 0)
12802 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12803 /// same as extracting the low 128-bit part of 256-bit vector and then
12804 /// inserting the result into the high part of a new 256-bit vector
12805 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12806 EVT VT = SVOp->getValueType(0);
12807 int NumElems = VT.getVectorNumElements();
12809 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12810 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12811 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12812 SVOp->getMaskElt(j) >= 0)
12818 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12819 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12820 TargetLowering::DAGCombinerInfo &DCI,
12821 const X86Subtarget* Subtarget) {
12822 DebugLoc dl = N->getDebugLoc();
12823 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12824 SDValue V1 = SVOp->getOperand(0);
12825 SDValue V2 = SVOp->getOperand(1);
12826 EVT VT = SVOp->getValueType(0);
12827 int NumElems = VT.getVectorNumElements();
12829 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12830 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12834 // V UNDEF BUILD_VECTOR UNDEF
12836 // CONCAT_VECTOR CONCAT_VECTOR
12839 // RESULT: V + zero extended
12841 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12842 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12843 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12846 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12849 // To match the shuffle mask, the first half of the mask should
12850 // be exactly the first vector, and all the rest a splat with the
12851 // first element of the second one.
12852 for (int i = 0; i < NumElems/2; ++i)
12853 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12854 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12857 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12858 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12859 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12860 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12862 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12864 Ld->getPointerInfo(),
12865 Ld->getAlignment(),
12866 false/*isVolatile*/, true/*ReadMem*/,
12867 false/*WriteMem*/);
12868 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12871 // Emit a zeroed vector and insert the desired subvector on its
12873 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12874 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12875 DAG.getConstant(0, MVT::i32), DAG, dl);
12876 return DCI.CombineTo(N, InsV);
12879 //===--------------------------------------------------------------------===//
12880 // Combine some shuffles into subvector extracts and inserts:
12883 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12884 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12885 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12887 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12888 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12889 return DCI.CombineTo(N, InsV);
12892 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12893 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12894 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12895 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12896 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12897 return DCI.CombineTo(N, InsV);
12903 /// PerformShuffleCombine - Performs several different shuffle combines.
12904 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12905 TargetLowering::DAGCombinerInfo &DCI,
12906 const X86Subtarget *Subtarget) {
12907 DebugLoc dl = N->getDebugLoc();
12908 EVT VT = N->getValueType(0);
12910 // Don't create instructions with illegal types after legalize types has run.
12911 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12912 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12915 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12916 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12917 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12918 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
12920 // Only handle 128 wide vector from here on.
12921 if (VT.getSizeInBits() != 128)
12924 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12925 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12926 // consecutive, non-overlapping, and in the right order.
12927 SmallVector<SDValue, 16> Elts;
12928 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12929 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12931 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12935 /// PerformTruncateCombine - Converts truncate operation to
12936 /// a sequence of vector shuffle operations.
12937 /// It is possible when we truncate 256-bit vector to 128-bit vector
12939 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
12940 DAGCombinerInfo &DCI) const {
12941 if (!DCI.isBeforeLegalizeOps())
12944 if (!Subtarget->hasAVX()) return SDValue();
12946 EVT VT = N->getValueType(0);
12947 SDValue Op = N->getOperand(0);
12948 EVT OpVT = Op.getValueType();
12949 DebugLoc dl = N->getDebugLoc();
12951 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
12953 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12954 DAG.getIntPtrConstant(0));
12956 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12957 DAG.getIntPtrConstant(2));
12959 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
12960 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
12963 int ShufMask1[] = {0, 2, 0, 0};
12965 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT),
12967 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT),
12971 int ShufMask2[] = {0, 1, 4, 5};
12973 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
12975 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
12977 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
12978 DAG.getIntPtrConstant(0));
12980 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
12981 DAG.getIntPtrConstant(4));
12983 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
12984 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
12987 int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12988 -1, -1, -1, -1, -1, -1, -1, -1};
12990 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo,
12991 DAG.getUNDEF(MVT::v16i8),
12993 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi,
12994 DAG.getUNDEF(MVT::v16i8),
12997 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
12998 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13001 int ShufMask2[] = {0, 1, 4, 5};
13003 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13004 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13010 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13011 /// generation and convert it from being a bunch of shuffles and extracts
13012 /// to a simple store and scalar loads to extract the elements.
13013 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13014 const TargetLowering &TLI) {
13015 SDValue InputVector = N->getOperand(0);
13017 // Only operate on vectors of 4 elements, where the alternative shuffling
13018 // gets to be more expensive.
13019 if (InputVector.getValueType() != MVT::v4i32)
13022 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13023 // single use which is a sign-extend or zero-extend, and all elements are
13025 SmallVector<SDNode *, 4> Uses;
13026 unsigned ExtractedElements = 0;
13027 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13028 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13029 if (UI.getUse().getResNo() != InputVector.getResNo())
13032 SDNode *Extract = *UI;
13033 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13036 if (Extract->getValueType(0) != MVT::i32)
13038 if (!Extract->hasOneUse())
13040 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13041 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13043 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13046 // Record which element was extracted.
13047 ExtractedElements |=
13048 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13050 Uses.push_back(Extract);
13053 // If not all the elements were used, this may not be worthwhile.
13054 if (ExtractedElements != 15)
13057 // Ok, we've now decided to do the transformation.
13058 DebugLoc dl = InputVector.getDebugLoc();
13060 // Store the value to a temporary stack slot.
13061 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13062 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13063 MachinePointerInfo(), false, false, 0);
13065 // Replace each use (extract) with a load of the appropriate element.
13066 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13067 UE = Uses.end(); UI != UE; ++UI) {
13068 SDNode *Extract = *UI;
13070 // cOMpute the element's address.
13071 SDValue Idx = Extract->getOperand(1);
13073 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13074 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13075 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13077 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13078 StackPtr, OffsetVal);
13080 // Load the scalar.
13081 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13082 ScalarAddr, MachinePointerInfo(),
13083 false, false, false, 0);
13085 // Replace the exact with the load.
13086 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13089 // The replacement was made in place; don't return anything.
13093 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13095 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13096 TargetLowering::DAGCombinerInfo &DCI,
13097 const X86Subtarget *Subtarget) {
13098 DebugLoc DL = N->getDebugLoc();
13099 SDValue Cond = N->getOperand(0);
13100 // Get the LHS/RHS of the select.
13101 SDValue LHS = N->getOperand(1);
13102 SDValue RHS = N->getOperand(2);
13103 EVT VT = LHS.getValueType();
13105 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13106 // instructions match the semantics of the common C idiom x<y?x:y but not
13107 // x<=y?x:y, because of how they handle negative zero (which can be
13108 // ignored in unsafe-math mode).
13109 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13110 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13111 (Subtarget->hasSSE2() ||
13112 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13113 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13115 unsigned Opcode = 0;
13116 // Check for x CC y ? x : y.
13117 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13118 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13122 // Converting this to a min would handle NaNs incorrectly, and swapping
13123 // the operands would cause it to handle comparisons between positive
13124 // and negative zero incorrectly.
13125 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13126 if (!DAG.getTarget().Options.UnsafeFPMath &&
13127 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13129 std::swap(LHS, RHS);
13131 Opcode = X86ISD::FMIN;
13134 // Converting this to a min would handle comparisons between positive
13135 // and negative zero incorrectly.
13136 if (!DAG.getTarget().Options.UnsafeFPMath &&
13137 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13139 Opcode = X86ISD::FMIN;
13142 // Converting this to a min would handle both negative zeros and NaNs
13143 // incorrectly, but we can swap the operands to fix both.
13144 std::swap(LHS, RHS);
13148 Opcode = X86ISD::FMIN;
13152 // Converting this to a max would handle comparisons between positive
13153 // and negative zero incorrectly.
13154 if (!DAG.getTarget().Options.UnsafeFPMath &&
13155 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13157 Opcode = X86ISD::FMAX;
13160 // Converting this to a max would handle NaNs incorrectly, and swapping
13161 // the operands would cause it to handle comparisons between positive
13162 // and negative zero incorrectly.
13163 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13164 if (!DAG.getTarget().Options.UnsafeFPMath &&
13165 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13167 std::swap(LHS, RHS);
13169 Opcode = X86ISD::FMAX;
13172 // Converting this to a max would handle both negative zeros and NaNs
13173 // incorrectly, but we can swap the operands to fix both.
13174 std::swap(LHS, RHS);
13178 Opcode = X86ISD::FMAX;
13181 // Check for x CC y ? y : x -- a min/max with reversed arms.
13182 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13183 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13187 // Converting this to a min would handle comparisons between positive
13188 // and negative zero incorrectly, and swapping the operands would
13189 // cause it to handle NaNs incorrectly.
13190 if (!DAG.getTarget().Options.UnsafeFPMath &&
13191 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13192 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13194 std::swap(LHS, RHS);
13196 Opcode = X86ISD::FMIN;
13199 // Converting this to a min would handle NaNs incorrectly.
13200 if (!DAG.getTarget().Options.UnsafeFPMath &&
13201 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13203 Opcode = X86ISD::FMIN;
13206 // Converting this to a min would handle both negative zeros and NaNs
13207 // incorrectly, but we can swap the operands to fix both.
13208 std::swap(LHS, RHS);
13212 Opcode = X86ISD::FMIN;
13216 // Converting this to a max would handle NaNs incorrectly.
13217 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13219 Opcode = X86ISD::FMAX;
13222 // Converting this to a max would handle comparisons between positive
13223 // and negative zero incorrectly, and swapping the operands would
13224 // cause it to handle NaNs incorrectly.
13225 if (!DAG.getTarget().Options.UnsafeFPMath &&
13226 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13227 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13229 std::swap(LHS, RHS);
13231 Opcode = X86ISD::FMAX;
13234 // Converting this to a max would handle both negative zeros and NaNs
13235 // incorrectly, but we can swap the operands to fix both.
13236 std::swap(LHS, RHS);
13240 Opcode = X86ISD::FMAX;
13246 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13249 // If this is a select between two integer constants, try to do some
13251 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13252 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13253 // Don't do this for crazy integer types.
13254 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13255 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13256 // so that TrueC (the true value) is larger than FalseC.
13257 bool NeedsCondInvert = false;
13259 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13260 // Efficiently invertible.
13261 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13262 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13263 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13264 NeedsCondInvert = true;
13265 std::swap(TrueC, FalseC);
13268 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13269 if (FalseC->getAPIntValue() == 0 &&
13270 TrueC->getAPIntValue().isPowerOf2()) {
13271 if (NeedsCondInvert) // Invert the condition if needed.
13272 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13273 DAG.getConstant(1, Cond.getValueType()));
13275 // Zero extend the condition if needed.
13276 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13278 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13279 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13280 DAG.getConstant(ShAmt, MVT::i8));
13283 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13284 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13285 if (NeedsCondInvert) // Invert the condition if needed.
13286 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13287 DAG.getConstant(1, Cond.getValueType()));
13289 // Zero extend the condition if needed.
13290 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13291 FalseC->getValueType(0), Cond);
13292 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13293 SDValue(FalseC, 0));
13296 // Optimize cases that will turn into an LEA instruction. This requires
13297 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13298 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13299 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13300 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13302 bool isFastMultiplier = false;
13304 switch ((unsigned char)Diff) {
13306 case 1: // result = add base, cond
13307 case 2: // result = lea base( , cond*2)
13308 case 3: // result = lea base(cond, cond*2)
13309 case 4: // result = lea base( , cond*4)
13310 case 5: // result = lea base(cond, cond*4)
13311 case 8: // result = lea base( , cond*8)
13312 case 9: // result = lea base(cond, cond*8)
13313 isFastMultiplier = true;
13318 if (isFastMultiplier) {
13319 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13320 if (NeedsCondInvert) // Invert the condition if needed.
13321 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13322 DAG.getConstant(1, Cond.getValueType()));
13324 // Zero extend the condition if needed.
13325 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13327 // Scale the condition by the difference.
13329 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13330 DAG.getConstant(Diff, Cond.getValueType()));
13332 // Add the base if non-zero.
13333 if (FalseC->getAPIntValue() != 0)
13334 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13335 SDValue(FalseC, 0));
13342 // Canonicalize max and min:
13343 // (x > y) ? x : y -> (x >= y) ? x : y
13344 // (x < y) ? x : y -> (x <= y) ? x : y
13345 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13346 // the need for an extra compare
13347 // against zero. e.g.
13348 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13350 // testl %edi, %edi
13352 // cmovgl %edi, %eax
13356 // cmovsl %eax, %edi
13357 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13358 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13359 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13360 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13365 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13366 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13367 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13368 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13373 // If we know that this node is legal then we know that it is going to be
13374 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13375 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13376 // to simplify previous instructions.
13377 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13378 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13379 !DCI.isBeforeLegalize() &&
13380 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13381 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13382 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13383 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13385 APInt KnownZero, KnownOne;
13386 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13387 DCI.isBeforeLegalizeOps());
13388 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13389 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13390 DCI.CommitTargetLoweringOpt(TLO);
13396 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13397 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13398 TargetLowering::DAGCombinerInfo &DCI) {
13399 DebugLoc DL = N->getDebugLoc();
13401 // If the flag operand isn't dead, don't touch this CMOV.
13402 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13405 SDValue FalseOp = N->getOperand(0);
13406 SDValue TrueOp = N->getOperand(1);
13407 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13408 SDValue Cond = N->getOperand(3);
13409 if (CC == X86::COND_E || CC == X86::COND_NE) {
13410 switch (Cond.getOpcode()) {
13414 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13415 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13416 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13420 // If this is a select between two integer constants, try to do some
13421 // optimizations. Note that the operands are ordered the opposite of SELECT
13423 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13424 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13425 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13426 // larger than FalseC (the false value).
13427 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13428 CC = X86::GetOppositeBranchCondition(CC);
13429 std::swap(TrueC, FalseC);
13432 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13433 // This is efficient for any integer data type (including i8/i16) and
13435 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13436 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13437 DAG.getConstant(CC, MVT::i8), Cond);
13439 // Zero extend the condition if needed.
13440 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13442 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13443 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13444 DAG.getConstant(ShAmt, MVT::i8));
13445 if (N->getNumValues() == 2) // Dead flag value?
13446 return DCI.CombineTo(N, Cond, SDValue());
13450 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13451 // for any integer data type, including i8/i16.
13452 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13453 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13454 DAG.getConstant(CC, MVT::i8), Cond);
13456 // Zero extend the condition if needed.
13457 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13458 FalseC->getValueType(0), Cond);
13459 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13460 SDValue(FalseC, 0));
13462 if (N->getNumValues() == 2) // Dead flag value?
13463 return DCI.CombineTo(N, Cond, SDValue());
13467 // Optimize cases that will turn into an LEA instruction. This requires
13468 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13469 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13470 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13471 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13473 bool isFastMultiplier = false;
13475 switch ((unsigned char)Diff) {
13477 case 1: // result = add base, cond
13478 case 2: // result = lea base( , cond*2)
13479 case 3: // result = lea base(cond, cond*2)
13480 case 4: // result = lea base( , cond*4)
13481 case 5: // result = lea base(cond, cond*4)
13482 case 8: // result = lea base( , cond*8)
13483 case 9: // result = lea base(cond, cond*8)
13484 isFastMultiplier = true;
13489 if (isFastMultiplier) {
13490 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13491 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13492 DAG.getConstant(CC, MVT::i8), Cond);
13493 // Zero extend the condition if needed.
13494 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13496 // Scale the condition by the difference.
13498 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13499 DAG.getConstant(Diff, Cond.getValueType()));
13501 // Add the base if non-zero.
13502 if (FalseC->getAPIntValue() != 0)
13503 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13504 SDValue(FalseC, 0));
13505 if (N->getNumValues() == 2) // Dead flag value?
13506 return DCI.CombineTo(N, Cond, SDValue());
13516 /// PerformMulCombine - Optimize a single multiply with constant into two
13517 /// in order to implement it with two cheaper instructions, e.g.
13518 /// LEA + SHL, LEA + LEA.
13519 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13520 TargetLowering::DAGCombinerInfo &DCI) {
13521 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13524 EVT VT = N->getValueType(0);
13525 if (VT != MVT::i64)
13528 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13531 uint64_t MulAmt = C->getZExtValue();
13532 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13535 uint64_t MulAmt1 = 0;
13536 uint64_t MulAmt2 = 0;
13537 if ((MulAmt % 9) == 0) {
13539 MulAmt2 = MulAmt / 9;
13540 } else if ((MulAmt % 5) == 0) {
13542 MulAmt2 = MulAmt / 5;
13543 } else if ((MulAmt % 3) == 0) {
13545 MulAmt2 = MulAmt / 3;
13548 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13549 DebugLoc DL = N->getDebugLoc();
13551 if (isPowerOf2_64(MulAmt2) &&
13552 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13553 // If second multiplifer is pow2, issue it first. We want the multiply by
13554 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13556 std::swap(MulAmt1, MulAmt2);
13559 if (isPowerOf2_64(MulAmt1))
13560 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13561 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13563 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13564 DAG.getConstant(MulAmt1, VT));
13566 if (isPowerOf2_64(MulAmt2))
13567 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13568 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13570 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13571 DAG.getConstant(MulAmt2, VT));
13573 // Do not add new nodes to DAG combiner worklist.
13574 DCI.CombineTo(N, NewMul, false);
13579 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13580 SDValue N0 = N->getOperand(0);
13581 SDValue N1 = N->getOperand(1);
13582 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13583 EVT VT = N0.getValueType();
13585 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13586 // since the result of setcc_c is all zero's or all ones.
13587 if (VT.isInteger() && !VT.isVector() &&
13588 N1C && N0.getOpcode() == ISD::AND &&
13589 N0.getOperand(1).getOpcode() == ISD::Constant) {
13590 SDValue N00 = N0.getOperand(0);
13591 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13592 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13593 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13594 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13595 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13596 APInt ShAmt = N1C->getAPIntValue();
13597 Mask = Mask.shl(ShAmt);
13599 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13600 N00, DAG.getConstant(Mask, VT));
13605 // Hardware support for vector shifts is sparse which makes us scalarize the
13606 // vector operations in many cases. Also, on sandybridge ADD is faster than
13608 // (shl V, 1) -> add V,V
13609 if (isSplatVector(N1.getNode())) {
13610 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13611 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13612 // We shift all of the values by one. In many cases we do not have
13613 // hardware support for this operation. This is better expressed as an ADD
13615 if (N1C && (1 == N1C->getZExtValue())) {
13616 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13623 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13625 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13626 TargetLowering::DAGCombinerInfo &DCI,
13627 const X86Subtarget *Subtarget) {
13628 EVT VT = N->getValueType(0);
13629 if (N->getOpcode() == ISD::SHL) {
13630 SDValue V = PerformSHLCombine(N, DAG);
13631 if (V.getNode()) return V;
13634 // On X86 with SSE2 support, we can transform this to a vector shift if
13635 // all elements are shifted by the same amount. We can't do this in legalize
13636 // because the a constant vector is typically transformed to a constant pool
13637 // so we have no knowledge of the shift amount.
13638 if (!Subtarget->hasSSE2())
13641 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13642 (!Subtarget->hasAVX2() ||
13643 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13646 SDValue ShAmtOp = N->getOperand(1);
13647 EVT EltVT = VT.getVectorElementType();
13648 DebugLoc DL = N->getDebugLoc();
13649 SDValue BaseShAmt = SDValue();
13650 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13651 unsigned NumElts = VT.getVectorNumElements();
13653 for (; i != NumElts; ++i) {
13654 SDValue Arg = ShAmtOp.getOperand(i);
13655 if (Arg.getOpcode() == ISD::UNDEF) continue;
13659 // Handle the case where the build_vector is all undef
13660 // FIXME: Should DAG allow this?
13664 for (; i != NumElts; ++i) {
13665 SDValue Arg = ShAmtOp.getOperand(i);
13666 if (Arg.getOpcode() == ISD::UNDEF) continue;
13667 if (Arg != BaseShAmt) {
13671 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13672 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13673 SDValue InVec = ShAmtOp.getOperand(0);
13674 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13675 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13677 for (; i != NumElts; ++i) {
13678 SDValue Arg = InVec.getOperand(i);
13679 if (Arg.getOpcode() == ISD::UNDEF) continue;
13683 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13684 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13685 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13686 if (C->getZExtValue() == SplatIdx)
13687 BaseShAmt = InVec.getOperand(1);
13690 if (BaseShAmt.getNode() == 0) {
13691 // Don't create instructions with illegal types after legalize
13693 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13694 !DCI.isBeforeLegalize())
13697 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13698 DAG.getIntPtrConstant(0));
13703 // The shift amount is an i32.
13704 if (EltVT.bitsGT(MVT::i32))
13705 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13706 else if (EltVT.bitsLT(MVT::i32))
13707 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13709 // The shift amount is identical so we can do a vector shift.
13710 SDValue ValOp = N->getOperand(0);
13711 switch (N->getOpcode()) {
13713 llvm_unreachable("Unknown shift opcode!");
13715 switch (VT.getSimpleVT().SimpleTy) {
13716 default: return SDValue();
13723 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13726 switch (VT.getSimpleVT().SimpleTy) {
13727 default: return SDValue();
13732 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13735 switch (VT.getSimpleVT().SimpleTy) {
13736 default: return SDValue();
13743 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13749 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13750 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13751 // and friends. Likewise for OR -> CMPNEQSS.
13752 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13753 TargetLowering::DAGCombinerInfo &DCI,
13754 const X86Subtarget *Subtarget) {
13757 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13758 // we're requiring SSE2 for both.
13759 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13760 SDValue N0 = N->getOperand(0);
13761 SDValue N1 = N->getOperand(1);
13762 SDValue CMP0 = N0->getOperand(1);
13763 SDValue CMP1 = N1->getOperand(1);
13764 DebugLoc DL = N->getDebugLoc();
13766 // The SETCCs should both refer to the same CMP.
13767 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13770 SDValue CMP00 = CMP0->getOperand(0);
13771 SDValue CMP01 = CMP0->getOperand(1);
13772 EVT VT = CMP00.getValueType();
13774 if (VT == MVT::f32 || VT == MVT::f64) {
13775 bool ExpectingFlags = false;
13776 // Check for any users that want flags:
13777 for (SDNode::use_iterator UI = N->use_begin(),
13779 !ExpectingFlags && UI != UE; ++UI)
13780 switch (UI->getOpcode()) {
13785 ExpectingFlags = true;
13787 case ISD::CopyToReg:
13788 case ISD::SIGN_EXTEND:
13789 case ISD::ZERO_EXTEND:
13790 case ISD::ANY_EXTEND:
13794 if (!ExpectingFlags) {
13795 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13796 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13798 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13799 X86::CondCode tmp = cc0;
13804 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13805 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13806 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13807 X86ISD::NodeType NTOperator = is64BitFP ?
13808 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13809 // FIXME: need symbolic constants for these magic numbers.
13810 // See X86ATTInstPrinter.cpp:printSSECC().
13811 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13812 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13813 DAG.getConstant(x86cc, MVT::i8));
13814 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13816 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13817 DAG.getConstant(1, MVT::i32));
13818 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13819 return OneBitOfTruth;
13827 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13828 /// so it can be folded inside ANDNP.
13829 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13830 EVT VT = N->getValueType(0);
13832 // Match direct AllOnes for 128 and 256-bit vectors
13833 if (ISD::isBuildVectorAllOnes(N))
13836 // Look through a bit convert.
13837 if (N->getOpcode() == ISD::BITCAST)
13838 N = N->getOperand(0).getNode();
13840 // Sometimes the operand may come from a insert_subvector building a 256-bit
13842 if (VT.getSizeInBits() == 256 &&
13843 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13844 SDValue V1 = N->getOperand(0);
13845 SDValue V2 = N->getOperand(1);
13847 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13848 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13849 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13850 ISD::isBuildVectorAllOnes(V2.getNode()))
13857 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13858 TargetLowering::DAGCombinerInfo &DCI,
13859 const X86Subtarget *Subtarget) {
13860 if (DCI.isBeforeLegalizeOps())
13863 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13867 EVT VT = N->getValueType(0);
13869 // Create ANDN, BLSI, and BLSR instructions
13870 // BLSI is X & (-X)
13871 // BLSR is X & (X-1)
13872 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13873 SDValue N0 = N->getOperand(0);
13874 SDValue N1 = N->getOperand(1);
13875 DebugLoc DL = N->getDebugLoc();
13877 // Check LHS for not
13878 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13879 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13880 // Check RHS for not
13881 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13882 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13884 // Check LHS for neg
13885 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13886 isZero(N0.getOperand(0)))
13887 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13889 // Check RHS for neg
13890 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13891 isZero(N1.getOperand(0)))
13892 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13894 // Check LHS for X-1
13895 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13896 isAllOnes(N0.getOperand(1)))
13897 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13899 // Check RHS for X-1
13900 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13901 isAllOnes(N1.getOperand(1)))
13902 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13907 // Want to form ANDNP nodes:
13908 // 1) In the hopes of then easily combining them with OR and AND nodes
13909 // to form PBLEND/PSIGN.
13910 // 2) To match ANDN packed intrinsics
13911 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13914 SDValue N0 = N->getOperand(0);
13915 SDValue N1 = N->getOperand(1);
13916 DebugLoc DL = N->getDebugLoc();
13918 // Check LHS for vnot
13919 if (N0.getOpcode() == ISD::XOR &&
13920 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13921 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13922 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13924 // Check RHS for vnot
13925 if (N1.getOpcode() == ISD::XOR &&
13926 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13927 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13928 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13933 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13934 TargetLowering::DAGCombinerInfo &DCI,
13935 const X86Subtarget *Subtarget) {
13936 if (DCI.isBeforeLegalizeOps())
13939 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13943 EVT VT = N->getValueType(0);
13945 SDValue N0 = N->getOperand(0);
13946 SDValue N1 = N->getOperand(1);
13948 // look for psign/blend
13949 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13950 if (!Subtarget->hasSSSE3() ||
13951 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13954 // Canonicalize pandn to RHS
13955 if (N0.getOpcode() == X86ISD::ANDNP)
13957 // or (and (m, y), (pandn m, x))
13958 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13959 SDValue Mask = N1.getOperand(0);
13960 SDValue X = N1.getOperand(1);
13962 if (N0.getOperand(0) == Mask)
13963 Y = N0.getOperand(1);
13964 if (N0.getOperand(1) == Mask)
13965 Y = N0.getOperand(0);
13967 // Check to see if the mask appeared in both the AND and ANDNP and
13971 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13972 if (Mask.getOpcode() != ISD::BITCAST ||
13973 X.getOpcode() != ISD::BITCAST ||
13974 Y.getOpcode() != ISD::BITCAST)
13977 // Look through mask bitcast.
13978 Mask = Mask.getOperand(0);
13979 EVT MaskVT = Mask.getValueType();
13981 // Validate that the Mask operand is a vector sra node.
13982 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13983 // there is no psrai.b
13984 if (Mask.getOpcode() != X86ISD::VSRAI)
13987 // Check that the SRA is all signbits.
13988 SDValue SraC = Mask.getOperand(1);
13989 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13990 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13991 if ((SraAmt + 1) != EltBits)
13994 DebugLoc DL = N->getDebugLoc();
13996 // Now we know we at least have a plendvb with the mask val. See if
13997 // we can form a psignb/w/d.
13998 // psign = x.type == y.type == mask.type && y = sub(0, x);
13999 X = X.getOperand(0);
14000 Y = Y.getOperand(0);
14001 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14002 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14003 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14004 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14005 "Unsupported VT for PSIGN");
14006 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14007 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14009 // PBLENDVB only available on SSE 4.1
14010 if (!Subtarget->hasSSE41())
14013 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14015 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14016 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14017 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14018 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14019 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14023 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14026 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14027 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14029 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14031 if (!N0.hasOneUse() || !N1.hasOneUse())
14034 SDValue ShAmt0 = N0.getOperand(1);
14035 if (ShAmt0.getValueType() != MVT::i8)
14037 SDValue ShAmt1 = N1.getOperand(1);
14038 if (ShAmt1.getValueType() != MVT::i8)
14040 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14041 ShAmt0 = ShAmt0.getOperand(0);
14042 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14043 ShAmt1 = ShAmt1.getOperand(0);
14045 DebugLoc DL = N->getDebugLoc();
14046 unsigned Opc = X86ISD::SHLD;
14047 SDValue Op0 = N0.getOperand(0);
14048 SDValue Op1 = N1.getOperand(0);
14049 if (ShAmt0.getOpcode() == ISD::SUB) {
14050 Opc = X86ISD::SHRD;
14051 std::swap(Op0, Op1);
14052 std::swap(ShAmt0, ShAmt1);
14055 unsigned Bits = VT.getSizeInBits();
14056 if (ShAmt1.getOpcode() == ISD::SUB) {
14057 SDValue Sum = ShAmt1.getOperand(0);
14058 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14059 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14060 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14061 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14062 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14063 return DAG.getNode(Opc, DL, VT,
14065 DAG.getNode(ISD::TRUNCATE, DL,
14068 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14069 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14071 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14072 return DAG.getNode(Opc, DL, VT,
14073 N0.getOperand(0), N1.getOperand(0),
14074 DAG.getNode(ISD::TRUNCATE, DL,
14081 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14082 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14083 TargetLowering::DAGCombinerInfo &DCI,
14084 const X86Subtarget *Subtarget) {
14085 if (DCI.isBeforeLegalizeOps())
14088 EVT VT = N->getValueType(0);
14090 if (VT != MVT::i32 && VT != MVT::i64)
14093 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14095 // Create BLSMSK instructions by finding X ^ (X-1)
14096 SDValue N0 = N->getOperand(0);
14097 SDValue N1 = N->getOperand(1);
14098 DebugLoc DL = N->getDebugLoc();
14100 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14101 isAllOnes(N0.getOperand(1)))
14102 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14104 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14105 isAllOnes(N1.getOperand(1)))
14106 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14111 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14112 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14113 const X86Subtarget *Subtarget) {
14114 LoadSDNode *Ld = cast<LoadSDNode>(N);
14115 EVT RegVT = Ld->getValueType(0);
14116 EVT MemVT = Ld->getMemoryVT();
14117 DebugLoc dl = Ld->getDebugLoc();
14118 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14120 ISD::LoadExtType Ext = Ld->getExtensionType();
14122 // If this is a vector EXT Load then attempt to optimize it using a
14123 // shuffle. We need SSE4 for the shuffles.
14124 // TODO: It is possible to support ZExt by zeroing the undef values
14125 // during the shuffle phase or after the shuffle.
14126 if (RegVT.isVector() && RegVT.isInteger() &&
14127 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14128 assert(MemVT != RegVT && "Cannot extend to the same type");
14129 assert(MemVT.isVector() && "Must load a vector from memory");
14131 unsigned NumElems = RegVT.getVectorNumElements();
14132 unsigned RegSz = RegVT.getSizeInBits();
14133 unsigned MemSz = MemVT.getSizeInBits();
14134 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14135 // All sizes must be a power of two
14136 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14138 // Attempt to load the original value using a single load op.
14139 // Find a scalar type which is equal to the loaded word size.
14140 MVT SclrLoadTy = MVT::i8;
14141 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14142 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14143 MVT Tp = (MVT::SimpleValueType)tp;
14144 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14150 // Proceed if a load word is found.
14151 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14153 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14154 RegSz/SclrLoadTy.getSizeInBits());
14156 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14157 RegSz/MemVT.getScalarType().getSizeInBits());
14158 // Can't shuffle using an illegal type.
14159 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14161 // Perform a single load.
14162 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14164 Ld->getPointerInfo(), Ld->isVolatile(),
14165 Ld->isNonTemporal(), Ld->isInvariant(),
14166 Ld->getAlignment());
14168 // Insert the word loaded into a vector.
14169 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14170 LoadUnitVecVT, ScalarLoad);
14172 // Bitcast the loaded value to a vector of the original element type, in
14173 // the size of the target vector type.
14174 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14176 unsigned SizeRatio = RegSz/MemSz;
14178 // Redistribute the loaded elements into the different locations.
14179 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14180 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14182 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14183 DAG.getUNDEF(SlicedVec.getValueType()),
14184 ShuffleVec.data());
14186 // Bitcast to the requested type.
14187 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14188 // Replace the original load with the new sequence
14189 // and return the new chain.
14190 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14191 return SDValue(ScalarLoad.getNode(), 1);
14197 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14198 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14199 const X86Subtarget *Subtarget) {
14200 StoreSDNode *St = cast<StoreSDNode>(N);
14201 EVT VT = St->getValue().getValueType();
14202 EVT StVT = St->getMemoryVT();
14203 DebugLoc dl = St->getDebugLoc();
14204 SDValue StoredVal = St->getOperand(1);
14205 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14207 // If we are saving a concatenation of two XMM registers, perform two stores.
14208 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14209 // 128-bit ones. If in the future the cost becomes only one memory access the
14210 // first version would be better.
14211 if (VT.getSizeInBits() == 256 &&
14212 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14213 StoredVal.getNumOperands() == 2) {
14215 SDValue Value0 = StoredVal.getOperand(0);
14216 SDValue Value1 = StoredVal.getOperand(1);
14218 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14219 SDValue Ptr0 = St->getBasePtr();
14220 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14222 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14223 St->getPointerInfo(), St->isVolatile(),
14224 St->isNonTemporal(), St->getAlignment());
14225 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14226 St->getPointerInfo(), St->isVolatile(),
14227 St->isNonTemporal(), St->getAlignment());
14228 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14231 // Optimize trunc store (of multiple scalars) to shuffle and store.
14232 // First, pack all of the elements in one place. Next, store to memory
14233 // in fewer chunks.
14234 if (St->isTruncatingStore() && VT.isVector()) {
14235 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14236 unsigned NumElems = VT.getVectorNumElements();
14237 assert(StVT != VT && "Cannot truncate to the same type");
14238 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14239 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14241 // From, To sizes and ElemCount must be pow of two
14242 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14243 // We are going to use the original vector elt for storing.
14244 // Accumulated smaller vector elements must be a multiple of the store size.
14245 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14247 unsigned SizeRatio = FromSz / ToSz;
14249 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14251 // Create a type on which we perform the shuffle
14252 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14253 StVT.getScalarType(), NumElems*SizeRatio);
14255 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14257 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14258 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14259 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14261 // Can't shuffle using an illegal type
14262 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14264 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14265 DAG.getUNDEF(WideVec.getValueType()),
14266 ShuffleVec.data());
14267 // At this point all of the data is stored at the bottom of the
14268 // register. We now need to save it to mem.
14270 // Find the largest store unit
14271 MVT StoreType = MVT::i8;
14272 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14273 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14274 MVT Tp = (MVT::SimpleValueType)tp;
14275 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14279 // Bitcast the original vector into a vector of store-size units
14280 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14281 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14282 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14283 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14284 SmallVector<SDValue, 8> Chains;
14285 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14286 TLI.getPointerTy());
14287 SDValue Ptr = St->getBasePtr();
14289 // Perform one or more big stores into memory.
14290 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14291 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14292 StoreType, ShuffWide,
14293 DAG.getIntPtrConstant(i));
14294 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14295 St->getPointerInfo(), St->isVolatile(),
14296 St->isNonTemporal(), St->getAlignment());
14297 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14298 Chains.push_back(Ch);
14301 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14306 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14307 // the FP state in cases where an emms may be missing.
14308 // A preferable solution to the general problem is to figure out the right
14309 // places to insert EMMS. This qualifies as a quick hack.
14311 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14312 if (VT.getSizeInBits() != 64)
14315 const Function *F = DAG.getMachineFunction().getFunction();
14316 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14317 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14318 && Subtarget->hasSSE2();
14319 if ((VT.isVector() ||
14320 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14321 isa<LoadSDNode>(St->getValue()) &&
14322 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14323 St->getChain().hasOneUse() && !St->isVolatile()) {
14324 SDNode* LdVal = St->getValue().getNode();
14325 LoadSDNode *Ld = 0;
14326 int TokenFactorIndex = -1;
14327 SmallVector<SDValue, 8> Ops;
14328 SDNode* ChainVal = St->getChain().getNode();
14329 // Must be a store of a load. We currently handle two cases: the load
14330 // is a direct child, and it's under an intervening TokenFactor. It is
14331 // possible to dig deeper under nested TokenFactors.
14332 if (ChainVal == LdVal)
14333 Ld = cast<LoadSDNode>(St->getChain());
14334 else if (St->getValue().hasOneUse() &&
14335 ChainVal->getOpcode() == ISD::TokenFactor) {
14336 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14337 if (ChainVal->getOperand(i).getNode() == LdVal) {
14338 TokenFactorIndex = i;
14339 Ld = cast<LoadSDNode>(St->getValue());
14341 Ops.push_back(ChainVal->getOperand(i));
14345 if (!Ld || !ISD::isNormalLoad(Ld))
14348 // If this is not the MMX case, i.e. we are just turning i64 load/store
14349 // into f64 load/store, avoid the transformation if there are multiple
14350 // uses of the loaded value.
14351 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14354 DebugLoc LdDL = Ld->getDebugLoc();
14355 DebugLoc StDL = N->getDebugLoc();
14356 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14357 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14359 if (Subtarget->is64Bit() || F64IsLegal) {
14360 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14361 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14362 Ld->getPointerInfo(), Ld->isVolatile(),
14363 Ld->isNonTemporal(), Ld->isInvariant(),
14364 Ld->getAlignment());
14365 SDValue NewChain = NewLd.getValue(1);
14366 if (TokenFactorIndex != -1) {
14367 Ops.push_back(NewChain);
14368 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14371 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14372 St->getPointerInfo(),
14373 St->isVolatile(), St->isNonTemporal(),
14374 St->getAlignment());
14377 // Otherwise, lower to two pairs of 32-bit loads / stores.
14378 SDValue LoAddr = Ld->getBasePtr();
14379 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14380 DAG.getConstant(4, MVT::i32));
14382 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14383 Ld->getPointerInfo(),
14384 Ld->isVolatile(), Ld->isNonTemporal(),
14385 Ld->isInvariant(), Ld->getAlignment());
14386 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14387 Ld->getPointerInfo().getWithOffset(4),
14388 Ld->isVolatile(), Ld->isNonTemporal(),
14390 MinAlign(Ld->getAlignment(), 4));
14392 SDValue NewChain = LoLd.getValue(1);
14393 if (TokenFactorIndex != -1) {
14394 Ops.push_back(LoLd);
14395 Ops.push_back(HiLd);
14396 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14400 LoAddr = St->getBasePtr();
14401 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14402 DAG.getConstant(4, MVT::i32));
14404 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14405 St->getPointerInfo(),
14406 St->isVolatile(), St->isNonTemporal(),
14407 St->getAlignment());
14408 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14409 St->getPointerInfo().getWithOffset(4),
14411 St->isNonTemporal(),
14412 MinAlign(St->getAlignment(), 4));
14413 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14418 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14419 /// and return the operands for the horizontal operation in LHS and RHS. A
14420 /// horizontal operation performs the binary operation on successive elements
14421 /// of its first operand, then on successive elements of its second operand,
14422 /// returning the resulting values in a vector. For example, if
14423 /// A = < float a0, float a1, float a2, float a3 >
14425 /// B = < float b0, float b1, float b2, float b3 >
14426 /// then the result of doing a horizontal operation on A and B is
14427 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14428 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14429 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14430 /// set to A, RHS to B, and the routine returns 'true'.
14431 /// Note that the binary operation should have the property that if one of the
14432 /// operands is UNDEF then the result is UNDEF.
14433 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14434 // Look for the following pattern: if
14435 // A = < float a0, float a1, float a2, float a3 >
14436 // B = < float b0, float b1, float b2, float b3 >
14438 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14439 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14440 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14441 // which is A horizontal-op B.
14443 // At least one of the operands should be a vector shuffle.
14444 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14445 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14448 EVT VT = LHS.getValueType();
14450 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14451 "Unsupported vector type for horizontal add/sub");
14453 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14454 // operate independently on 128-bit lanes.
14455 unsigned NumElts = VT.getVectorNumElements();
14456 unsigned NumLanes = VT.getSizeInBits()/128;
14457 unsigned NumLaneElts = NumElts / NumLanes;
14458 assert((NumLaneElts % 2 == 0) &&
14459 "Vector type should have an even number of elements in each lane");
14460 unsigned HalfLaneElts = NumLaneElts/2;
14462 // View LHS in the form
14463 // LHS = VECTOR_SHUFFLE A, B, LMask
14464 // If LHS is not a shuffle then pretend it is the shuffle
14465 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14466 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14469 SmallVector<int, 16> LMask(NumElts);
14470 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14471 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14472 A = LHS.getOperand(0);
14473 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14474 B = LHS.getOperand(1);
14475 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14476 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14478 if (LHS.getOpcode() != ISD::UNDEF)
14480 for (unsigned i = 0; i != NumElts; ++i)
14484 // Likewise, view RHS in the form
14485 // RHS = VECTOR_SHUFFLE C, D, RMask
14487 SmallVector<int, 16> RMask(NumElts);
14488 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14489 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14490 C = RHS.getOperand(0);
14491 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14492 D = RHS.getOperand(1);
14493 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14494 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14496 if (RHS.getOpcode() != ISD::UNDEF)
14498 for (unsigned i = 0; i != NumElts; ++i)
14502 // Check that the shuffles are both shuffling the same vectors.
14503 if (!(A == C && B == D) && !(A == D && B == C))
14506 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14507 if (!A.getNode() && !B.getNode())
14510 // If A and B occur in reverse order in RHS, then "swap" them (which means
14511 // rewriting the mask).
14513 CommuteVectorShuffleMask(RMask, NumElts);
14515 // At this point LHS and RHS are equivalent to
14516 // LHS = VECTOR_SHUFFLE A, B, LMask
14517 // RHS = VECTOR_SHUFFLE A, B, RMask
14518 // Check that the masks correspond to performing a horizontal operation.
14519 for (unsigned i = 0; i != NumElts; ++i) {
14520 int LIdx = LMask[i], RIdx = RMask[i];
14522 // Ignore any UNDEF components.
14523 if (LIdx < 0 || RIdx < 0 ||
14524 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14525 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14528 // Check that successive elements are being operated on. If not, this is
14529 // not a horizontal operation.
14530 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14531 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14532 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14533 if (!(LIdx == Index && RIdx == Index + 1) &&
14534 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14538 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14539 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14543 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14544 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14545 const X86Subtarget *Subtarget) {
14546 EVT VT = N->getValueType(0);
14547 SDValue LHS = N->getOperand(0);
14548 SDValue RHS = N->getOperand(1);
14550 // Try to synthesize horizontal adds from adds of shuffles.
14551 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14552 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14553 isHorizontalBinOp(LHS, RHS, true))
14554 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14558 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14559 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14560 const X86Subtarget *Subtarget) {
14561 EVT VT = N->getValueType(0);
14562 SDValue LHS = N->getOperand(0);
14563 SDValue RHS = N->getOperand(1);
14565 // Try to synthesize horizontal subs from subs of shuffles.
14566 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14567 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14568 isHorizontalBinOp(LHS, RHS, false))
14569 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14573 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14574 /// X86ISD::FXOR nodes.
14575 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14576 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14577 // F[X]OR(0.0, x) -> x
14578 // F[X]OR(x, 0.0) -> x
14579 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14580 if (C->getValueAPF().isPosZero())
14581 return N->getOperand(1);
14582 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14583 if (C->getValueAPF().isPosZero())
14584 return N->getOperand(0);
14588 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14589 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14590 // FAND(0.0, x) -> 0.0
14591 // FAND(x, 0.0) -> 0.0
14592 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14593 if (C->getValueAPF().isPosZero())
14594 return N->getOperand(0);
14595 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14596 if (C->getValueAPF().isPosZero())
14597 return N->getOperand(1);
14601 static SDValue PerformBTCombine(SDNode *N,
14603 TargetLowering::DAGCombinerInfo &DCI) {
14604 // BT ignores high bits in the bit index operand.
14605 SDValue Op1 = N->getOperand(1);
14606 if (Op1.hasOneUse()) {
14607 unsigned BitWidth = Op1.getValueSizeInBits();
14608 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14609 APInt KnownZero, KnownOne;
14610 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14611 !DCI.isBeforeLegalizeOps());
14612 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14613 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14614 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14615 DCI.CommitTargetLoweringOpt(TLO);
14620 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14621 SDValue Op = N->getOperand(0);
14622 if (Op.getOpcode() == ISD::BITCAST)
14623 Op = Op.getOperand(0);
14624 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14625 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14626 VT.getVectorElementType().getSizeInBits() ==
14627 OpVT.getVectorElementType().getSizeInBits()) {
14628 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14633 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14634 TargetLowering::DAGCombinerInfo &DCI,
14635 const X86Subtarget *Subtarget) {
14636 if (!DCI.isBeforeLegalizeOps())
14639 if (!Subtarget->hasAVX())
14642 // Optimize vectors in AVX mode
14643 // Sign extend v8i16 to v8i32 and
14646 // Divide input vector into two parts
14647 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14648 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14649 // concat the vectors to original VT
14651 EVT VT = N->getValueType(0);
14652 SDValue Op = N->getOperand(0);
14653 EVT OpVT = Op.getValueType();
14654 DebugLoc dl = N->getDebugLoc();
14656 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14657 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14659 unsigned NumElems = OpVT.getVectorNumElements();
14660 SmallVector<int,8> ShufMask1(NumElems, -1);
14661 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i;
14663 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14666 SmallVector<int,8> ShufMask2(NumElems, -1);
14667 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2;
14669 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14672 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14673 VT.getVectorNumElements()/2);
14675 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14676 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14678 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14683 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14684 const X86Subtarget *Subtarget) {
14685 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14686 // (and (i32 x86isd::setcc_carry), 1)
14687 // This eliminates the zext. This transformation is necessary because
14688 // ISD::SETCC is always legalized to i8.
14689 DebugLoc dl = N->getDebugLoc();
14690 SDValue N0 = N->getOperand(0);
14691 EVT VT = N->getValueType(0);
14692 EVT OpVT = N0.getValueType();
14694 if (N0.getOpcode() == ISD::AND &&
14696 N0.getOperand(0).hasOneUse()) {
14697 SDValue N00 = N0.getOperand(0);
14698 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14700 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14701 if (!C || C->getZExtValue() != 1)
14703 return DAG.getNode(ISD::AND, dl, VT,
14704 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14705 N00.getOperand(0), N00.getOperand(1)),
14706 DAG.getConstant(1, VT));
14708 // Optimize vectors in AVX mode:
14711 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14712 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14713 // Concat upper and lower parts.
14716 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14717 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14718 // Concat upper and lower parts.
14720 if (Subtarget->hasAVX()) {
14722 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14723 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14725 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
14726 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG);
14727 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG);
14729 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14730 VT.getVectorNumElements()/2);
14732 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14733 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14735 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14743 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14744 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14745 unsigned X86CC = N->getConstantOperandVal(0);
14746 SDValue EFLAG = N->getOperand(1);
14747 DebugLoc DL = N->getDebugLoc();
14749 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14750 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14752 if (X86CC == X86::COND_B)
14753 return DAG.getNode(ISD::AND, DL, MVT::i8,
14754 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14755 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14756 DAG.getConstant(1, MVT::i8));
14761 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14762 const X86TargetLowering *XTLI) {
14763 SDValue Op0 = N->getOperand(0);
14764 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14765 // a 32-bit target where SSE doesn't support i64->FP operations.
14766 if (Op0.getOpcode() == ISD::LOAD) {
14767 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14768 EVT VT = Ld->getValueType(0);
14769 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14770 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14771 !XTLI->getSubtarget()->is64Bit() &&
14772 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14773 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14774 Ld->getChain(), Op0, DAG);
14775 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14782 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14783 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14784 X86TargetLowering::DAGCombinerInfo &DCI) {
14785 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14786 // the result is either zero or one (depending on the input carry bit).
14787 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14788 if (X86::isZeroNode(N->getOperand(0)) &&
14789 X86::isZeroNode(N->getOperand(1)) &&
14790 // We don't have a good way to replace an EFLAGS use, so only do this when
14792 SDValue(N, 1).use_empty()) {
14793 DebugLoc DL = N->getDebugLoc();
14794 EVT VT = N->getValueType(0);
14795 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14796 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14797 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14798 DAG.getConstant(X86::COND_B,MVT::i8),
14800 DAG.getConstant(1, VT));
14801 return DCI.CombineTo(N, Res1, CarryOut);
14807 // fold (add Y, (sete X, 0)) -> adc 0, Y
14808 // (add Y, (setne X, 0)) -> sbb -1, Y
14809 // (sub (sete X, 0), Y) -> sbb 0, Y
14810 // (sub (setne X, 0), Y) -> adc -1, Y
14811 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14812 DebugLoc DL = N->getDebugLoc();
14814 // Look through ZExts.
14815 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14816 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14819 SDValue SetCC = Ext.getOperand(0);
14820 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14823 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14824 if (CC != X86::COND_E && CC != X86::COND_NE)
14827 SDValue Cmp = SetCC.getOperand(1);
14828 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14829 !X86::isZeroNode(Cmp.getOperand(1)) ||
14830 !Cmp.getOperand(0).getValueType().isInteger())
14833 SDValue CmpOp0 = Cmp.getOperand(0);
14834 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14835 DAG.getConstant(1, CmpOp0.getValueType()));
14837 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14838 if (CC == X86::COND_NE)
14839 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14840 DL, OtherVal.getValueType(), OtherVal,
14841 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14842 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14843 DL, OtherVal.getValueType(), OtherVal,
14844 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14847 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14848 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14849 const X86Subtarget *Subtarget) {
14850 EVT VT = N->getValueType(0);
14851 SDValue Op0 = N->getOperand(0);
14852 SDValue Op1 = N->getOperand(1);
14854 // Try to synthesize horizontal adds from adds of shuffles.
14855 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14856 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14857 isHorizontalBinOp(Op0, Op1, true))
14858 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14860 return OptimizeConditionalInDecrement(N, DAG);
14863 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14864 const X86Subtarget *Subtarget) {
14865 SDValue Op0 = N->getOperand(0);
14866 SDValue Op1 = N->getOperand(1);
14868 // X86 can't encode an immediate LHS of a sub. See if we can push the
14869 // negation into a preceding instruction.
14870 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14871 // If the RHS of the sub is a XOR with one use and a constant, invert the
14872 // immediate. Then add one to the LHS of the sub so we can turn
14873 // X-Y -> X+~Y+1, saving one register.
14874 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14875 isa<ConstantSDNode>(Op1.getOperand(1))) {
14876 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14877 EVT VT = Op0.getValueType();
14878 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14880 DAG.getConstant(~XorC, VT));
14881 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14882 DAG.getConstant(C->getAPIntValue()+1, VT));
14886 // Try to synthesize horizontal adds from adds of shuffles.
14887 EVT VT = N->getValueType(0);
14888 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14889 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14890 isHorizontalBinOp(Op0, Op1, true))
14891 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14893 return OptimizeConditionalInDecrement(N, DAG);
14896 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14897 DAGCombinerInfo &DCI) const {
14898 SelectionDAG &DAG = DCI.DAG;
14899 switch (N->getOpcode()) {
14901 case ISD::EXTRACT_VECTOR_ELT:
14902 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14904 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
14905 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14906 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14907 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14908 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14909 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14912 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
14913 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14914 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14915 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14916 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14917 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14918 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14919 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14920 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14922 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14923 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14924 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14925 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14926 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
14927 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
14928 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
14929 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14930 case X86ISD::SHUFP: // Handle all target specific shuffles
14931 case X86ISD::PALIGN:
14932 case X86ISD::UNPCKH:
14933 case X86ISD::UNPCKL:
14934 case X86ISD::MOVHLPS:
14935 case X86ISD::MOVLHPS:
14936 case X86ISD::PSHUFD:
14937 case X86ISD::PSHUFHW:
14938 case X86ISD::PSHUFLW:
14939 case X86ISD::MOVSS:
14940 case X86ISD::MOVSD:
14941 case X86ISD::VPERMILP:
14942 case X86ISD::VPERM2X128:
14943 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14949 /// isTypeDesirableForOp - Return true if the target has native support for
14950 /// the specified value type and it is 'desirable' to use the type for the
14951 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14952 /// instruction encodings are longer and some i16 instructions are slow.
14953 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14954 if (!isTypeLegal(VT))
14956 if (VT != MVT::i16)
14963 case ISD::SIGN_EXTEND:
14964 case ISD::ZERO_EXTEND:
14965 case ISD::ANY_EXTEND:
14978 /// IsDesirableToPromoteOp - This method query the target whether it is
14979 /// beneficial for dag combiner to promote the specified node. If true, it
14980 /// should return the desired promotion type by reference.
14981 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14982 EVT VT = Op.getValueType();
14983 if (VT != MVT::i16)
14986 bool Promote = false;
14987 bool Commute = false;
14988 switch (Op.getOpcode()) {
14991 LoadSDNode *LD = cast<LoadSDNode>(Op);
14992 // If the non-extending load has a single use and it's not live out, then it
14993 // might be folded.
14994 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14995 Op.hasOneUse()*/) {
14996 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14997 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14998 // The only case where we'd want to promote LOAD (rather then it being
14999 // promoted as an operand is when it's only use is liveout.
15000 if (UI->getOpcode() != ISD::CopyToReg)
15007 case ISD::SIGN_EXTEND:
15008 case ISD::ZERO_EXTEND:
15009 case ISD::ANY_EXTEND:
15014 SDValue N0 = Op.getOperand(0);
15015 // Look out for (store (shl (load), x)).
15016 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15029 SDValue N0 = Op.getOperand(0);
15030 SDValue N1 = Op.getOperand(1);
15031 if (!Commute && MayFoldLoad(N1))
15033 // Avoid disabling potential load folding opportunities.
15034 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15036 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15046 //===----------------------------------------------------------------------===//
15047 // X86 Inline Assembly Support
15048 //===----------------------------------------------------------------------===//
15051 // Helper to match a string separated by whitespace.
15052 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15053 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15055 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15056 StringRef piece(*args[i]);
15057 if (!s.startswith(piece)) // Check if the piece matches.
15060 s = s.substr(piece.size());
15061 StringRef::size_type pos = s.find_first_not_of(" \t");
15062 if (pos == 0) // We matched a prefix.
15070 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15073 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15074 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15076 std::string AsmStr = IA->getAsmString();
15078 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15079 if (!Ty || Ty->getBitWidth() % 16 != 0)
15082 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15083 SmallVector<StringRef, 4> AsmPieces;
15084 SplitString(AsmStr, AsmPieces, ";\n");
15086 switch (AsmPieces.size()) {
15087 default: return false;
15089 // FIXME: this should verify that we are targeting a 486 or better. If not,
15090 // we will turn this bswap into something that will be lowered to logical
15091 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15092 // lower so don't worry about this.
15094 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15095 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15096 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15097 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15098 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15099 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15100 // No need to check constraints, nothing other than the equivalent of
15101 // "=r,0" would be valid here.
15102 return IntrinsicLowering::LowerToByteSwap(CI);
15105 // rorw $$8, ${0:w} --> llvm.bswap.i16
15106 if (CI->getType()->isIntegerTy(16) &&
15107 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15108 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15109 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15111 const std::string &ConstraintsStr = IA->getConstraintString();
15112 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15113 std::sort(AsmPieces.begin(), AsmPieces.end());
15114 if (AsmPieces.size() == 4 &&
15115 AsmPieces[0] == "~{cc}" &&
15116 AsmPieces[1] == "~{dirflag}" &&
15117 AsmPieces[2] == "~{flags}" &&
15118 AsmPieces[3] == "~{fpsr}")
15119 return IntrinsicLowering::LowerToByteSwap(CI);
15123 if (CI->getType()->isIntegerTy(32) &&
15124 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15125 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15126 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15127 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15129 const std::string &ConstraintsStr = IA->getConstraintString();
15130 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15131 std::sort(AsmPieces.begin(), AsmPieces.end());
15132 if (AsmPieces.size() == 4 &&
15133 AsmPieces[0] == "~{cc}" &&
15134 AsmPieces[1] == "~{dirflag}" &&
15135 AsmPieces[2] == "~{flags}" &&
15136 AsmPieces[3] == "~{fpsr}")
15137 return IntrinsicLowering::LowerToByteSwap(CI);
15140 if (CI->getType()->isIntegerTy(64)) {
15141 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15142 if (Constraints.size() >= 2 &&
15143 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15144 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15145 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15146 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15147 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15148 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15149 return IntrinsicLowering::LowerToByteSwap(CI);
15159 /// getConstraintType - Given a constraint letter, return the type of
15160 /// constraint it is for this target.
15161 X86TargetLowering::ConstraintType
15162 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15163 if (Constraint.size() == 1) {
15164 switch (Constraint[0]) {
15175 return C_RegisterClass;
15199 return TargetLowering::getConstraintType(Constraint);
15202 /// Examine constraint type and operand type and determine a weight value.
15203 /// This object must already have been set up with the operand type
15204 /// and the current alternative constraint selected.
15205 TargetLowering::ConstraintWeight
15206 X86TargetLowering::getSingleConstraintMatchWeight(
15207 AsmOperandInfo &info, const char *constraint) const {
15208 ConstraintWeight weight = CW_Invalid;
15209 Value *CallOperandVal = info.CallOperandVal;
15210 // If we don't have a value, we can't do a match,
15211 // but allow it at the lowest weight.
15212 if (CallOperandVal == NULL)
15214 Type *type = CallOperandVal->getType();
15215 // Look at the constraint type.
15216 switch (*constraint) {
15218 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15229 if (CallOperandVal->getType()->isIntegerTy())
15230 weight = CW_SpecificReg;
15235 if (type->isFloatingPointTy())
15236 weight = CW_SpecificReg;
15239 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15240 weight = CW_SpecificReg;
15244 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15245 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15246 weight = CW_Register;
15249 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15250 if (C->getZExtValue() <= 31)
15251 weight = CW_Constant;
15255 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15256 if (C->getZExtValue() <= 63)
15257 weight = CW_Constant;
15261 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15262 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15263 weight = CW_Constant;
15267 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15268 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15269 weight = CW_Constant;
15273 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15274 if (C->getZExtValue() <= 3)
15275 weight = CW_Constant;
15279 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15280 if (C->getZExtValue() <= 0xff)
15281 weight = CW_Constant;
15286 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15287 weight = CW_Constant;
15291 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15292 if ((C->getSExtValue() >= -0x80000000LL) &&
15293 (C->getSExtValue() <= 0x7fffffffLL))
15294 weight = CW_Constant;
15298 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15299 if (C->getZExtValue() <= 0xffffffff)
15300 weight = CW_Constant;
15307 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15308 /// with another that has more specific requirements based on the type of the
15309 /// corresponding operand.
15310 const char *X86TargetLowering::
15311 LowerXConstraint(EVT ConstraintVT) const {
15312 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15313 // 'f' like normal targets.
15314 if (ConstraintVT.isFloatingPoint()) {
15315 if (Subtarget->hasSSE2())
15317 if (Subtarget->hasSSE1())
15321 return TargetLowering::LowerXConstraint(ConstraintVT);
15324 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15325 /// vector. If it is invalid, don't add anything to Ops.
15326 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15327 std::string &Constraint,
15328 std::vector<SDValue>&Ops,
15329 SelectionDAG &DAG) const {
15330 SDValue Result(0, 0);
15332 // Only support length 1 constraints for now.
15333 if (Constraint.length() > 1) return;
15335 char ConstraintLetter = Constraint[0];
15336 switch (ConstraintLetter) {
15339 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15340 if (C->getZExtValue() <= 31) {
15341 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15347 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15348 if (C->getZExtValue() <= 63) {
15349 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15355 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15356 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15357 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15363 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15364 if (C->getZExtValue() <= 255) {
15365 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15371 // 32-bit signed value
15372 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15373 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15374 C->getSExtValue())) {
15375 // Widen to 64 bits here to get it sign extended.
15376 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15379 // FIXME gcc accepts some relocatable values here too, but only in certain
15380 // memory models; it's complicated.
15385 // 32-bit unsigned value
15386 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15387 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15388 C->getZExtValue())) {
15389 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15393 // FIXME gcc accepts some relocatable values here too, but only in certain
15394 // memory models; it's complicated.
15398 // Literal immediates are always ok.
15399 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15400 // Widen to 64 bits here to get it sign extended.
15401 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15405 // In any sort of PIC mode addresses need to be computed at runtime by
15406 // adding in a register or some sort of table lookup. These can't
15407 // be used as immediates.
15408 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15411 // If we are in non-pic codegen mode, we allow the address of a global (with
15412 // an optional displacement) to be used with 'i'.
15413 GlobalAddressSDNode *GA = 0;
15414 int64_t Offset = 0;
15416 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15418 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15419 Offset += GA->getOffset();
15421 } else if (Op.getOpcode() == ISD::ADD) {
15422 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15423 Offset += C->getZExtValue();
15424 Op = Op.getOperand(0);
15427 } else if (Op.getOpcode() == ISD::SUB) {
15428 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15429 Offset += -C->getZExtValue();
15430 Op = Op.getOperand(0);
15435 // Otherwise, this isn't something we can handle, reject it.
15439 const GlobalValue *GV = GA->getGlobal();
15440 // If we require an extra load to get this address, as in PIC mode, we
15441 // can't accept it.
15442 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15443 getTargetMachine())))
15446 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15447 GA->getValueType(0), Offset);
15452 if (Result.getNode()) {
15453 Ops.push_back(Result);
15456 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15459 std::pair<unsigned, const TargetRegisterClass*>
15460 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15462 // First, see if this is a constraint that directly corresponds to an LLVM
15464 if (Constraint.size() == 1) {
15465 // GCC Constraint Letters
15466 switch (Constraint[0]) {
15468 // TODO: Slight differences here in allocation order and leaving
15469 // RIP in the class. Do they matter any more here than they do
15470 // in the normal allocation?
15471 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15472 if (Subtarget->is64Bit()) {
15473 if (VT == MVT::i32 || VT == MVT::f32)
15474 return std::make_pair(0U, X86::GR32RegisterClass);
15475 else if (VT == MVT::i16)
15476 return std::make_pair(0U, X86::GR16RegisterClass);
15477 else if (VT == MVT::i8 || VT == MVT::i1)
15478 return std::make_pair(0U, X86::GR8RegisterClass);
15479 else if (VT == MVT::i64 || VT == MVT::f64)
15480 return std::make_pair(0U, X86::GR64RegisterClass);
15483 // 32-bit fallthrough
15484 case 'Q': // Q_REGS
15485 if (VT == MVT::i32 || VT == MVT::f32)
15486 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15487 else if (VT == MVT::i16)
15488 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15489 else if (VT == MVT::i8 || VT == MVT::i1)
15490 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15491 else if (VT == MVT::i64)
15492 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15494 case 'r': // GENERAL_REGS
15495 case 'l': // INDEX_REGS
15496 if (VT == MVT::i8 || VT == MVT::i1)
15497 return std::make_pair(0U, X86::GR8RegisterClass);
15498 if (VT == MVT::i16)
15499 return std::make_pair(0U, X86::GR16RegisterClass);
15500 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15501 return std::make_pair(0U, X86::GR32RegisterClass);
15502 return std::make_pair(0U, X86::GR64RegisterClass);
15503 case 'R': // LEGACY_REGS
15504 if (VT == MVT::i8 || VT == MVT::i1)
15505 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15506 if (VT == MVT::i16)
15507 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15508 if (VT == MVT::i32 || !Subtarget->is64Bit())
15509 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15510 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15511 case 'f': // FP Stack registers.
15512 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15513 // value to the correct fpstack register class.
15514 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15515 return std::make_pair(0U, X86::RFP32RegisterClass);
15516 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15517 return std::make_pair(0U, X86::RFP64RegisterClass);
15518 return std::make_pair(0U, X86::RFP80RegisterClass);
15519 case 'y': // MMX_REGS if MMX allowed.
15520 if (!Subtarget->hasMMX()) break;
15521 return std::make_pair(0U, X86::VR64RegisterClass);
15522 case 'Y': // SSE_REGS if SSE2 allowed
15523 if (!Subtarget->hasSSE2()) break;
15525 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15526 if (!Subtarget->hasSSE1()) break;
15528 switch (VT.getSimpleVT().SimpleTy) {
15530 // Scalar SSE types.
15533 return std::make_pair(0U, X86::FR32RegisterClass);
15536 return std::make_pair(0U, X86::FR64RegisterClass);
15544 return std::make_pair(0U, X86::VR128RegisterClass);
15552 return std::make_pair(0U, X86::VR256RegisterClass);
15559 // Use the default implementation in TargetLowering to convert the register
15560 // constraint into a member of a register class.
15561 std::pair<unsigned, const TargetRegisterClass*> Res;
15562 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15564 // Not found as a standard register?
15565 if (Res.second == 0) {
15566 // Map st(0) -> st(7) -> ST0
15567 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15568 tolower(Constraint[1]) == 's' &&
15569 tolower(Constraint[2]) == 't' &&
15570 Constraint[3] == '(' &&
15571 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15572 Constraint[5] == ')' &&
15573 Constraint[6] == '}') {
15575 Res.first = X86::ST0+Constraint[4]-'0';
15576 Res.second = X86::RFP80RegisterClass;
15580 // GCC allows "st(0)" to be called just plain "st".
15581 if (StringRef("{st}").equals_lower(Constraint)) {
15582 Res.first = X86::ST0;
15583 Res.second = X86::RFP80RegisterClass;
15588 if (StringRef("{flags}").equals_lower(Constraint)) {
15589 Res.first = X86::EFLAGS;
15590 Res.second = X86::CCRRegisterClass;
15594 // 'A' means EAX + EDX.
15595 if (Constraint == "A") {
15596 Res.first = X86::EAX;
15597 Res.second = X86::GR32_ADRegisterClass;
15603 // Otherwise, check to see if this is a register class of the wrong value
15604 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15605 // turn into {ax},{dx}.
15606 if (Res.second->hasType(VT))
15607 return Res; // Correct type already, nothing to do.
15609 // All of the single-register GCC register classes map their values onto
15610 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15611 // really want an 8-bit or 32-bit register, map to the appropriate register
15612 // class and return the appropriate register.
15613 if (Res.second == X86::GR16RegisterClass) {
15614 if (VT == MVT::i8) {
15615 unsigned DestReg = 0;
15616 switch (Res.first) {
15618 case X86::AX: DestReg = X86::AL; break;
15619 case X86::DX: DestReg = X86::DL; break;
15620 case X86::CX: DestReg = X86::CL; break;
15621 case X86::BX: DestReg = X86::BL; break;
15624 Res.first = DestReg;
15625 Res.second = X86::GR8RegisterClass;
15627 } else if (VT == MVT::i32) {
15628 unsigned DestReg = 0;
15629 switch (Res.first) {
15631 case X86::AX: DestReg = X86::EAX; break;
15632 case X86::DX: DestReg = X86::EDX; break;
15633 case X86::CX: DestReg = X86::ECX; break;
15634 case X86::BX: DestReg = X86::EBX; break;
15635 case X86::SI: DestReg = X86::ESI; break;
15636 case X86::DI: DestReg = X86::EDI; break;
15637 case X86::BP: DestReg = X86::EBP; break;
15638 case X86::SP: DestReg = X86::ESP; break;
15641 Res.first = DestReg;
15642 Res.second = X86::GR32RegisterClass;
15644 } else if (VT == MVT::i64) {
15645 unsigned DestReg = 0;
15646 switch (Res.first) {
15648 case X86::AX: DestReg = X86::RAX; break;
15649 case X86::DX: DestReg = X86::RDX; break;
15650 case X86::CX: DestReg = X86::RCX; break;
15651 case X86::BX: DestReg = X86::RBX; break;
15652 case X86::SI: DestReg = X86::RSI; break;
15653 case X86::DI: DestReg = X86::RDI; break;
15654 case X86::BP: DestReg = X86::RBP; break;
15655 case X86::SP: DestReg = X86::RSP; break;
15658 Res.first = DestReg;
15659 Res.second = X86::GR64RegisterClass;
15662 } else if (Res.second == X86::FR32RegisterClass ||
15663 Res.second == X86::FR64RegisterClass ||
15664 Res.second == X86::VR128RegisterClass) {
15665 // Handle references to XMM physical registers that got mapped into the
15666 // wrong class. This can happen with constraints like {xmm0} where the
15667 // target independent register mapper will just pick the first match it can
15668 // find, ignoring the required type.
15669 if (VT == MVT::f32)
15670 Res.second = X86::FR32RegisterClass;
15671 else if (VT == MVT::f64)
15672 Res.second = X86::FR64RegisterClass;
15673 else if (X86::VR128RegisterClass->hasType(VT))
15674 Res.second = X86::VR128RegisterClass;