1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/GlobalAlias.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/ADT/VectorExtras.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/ADT/SmallSet.h"
42 #include "llvm/ADT/StringExtras.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/raw_ostream.h"
48 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
50 // Disable16Bit - 16-bit operations typically have a larger encoding than
51 // corresponding 32-bit instructions, and 16-bit code is slow on some
52 // processors. This is an experimental flag to disable 16-bit operations
53 // (which forces them to be Legalized to 32-bit operations).
55 Disable16Bit("disable-16bit", cl::Hidden,
56 cl::desc("Disable use of 16-bit instructions"));
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
62 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
63 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
64 default: llvm_unreachable("unknown subtarget type");
65 case X86Subtarget::isDarwin:
66 return new TargetLoweringObjectFileMachO();
67 case X86Subtarget::isELF:
68 return new TargetLoweringObjectFileELF();
69 case X86Subtarget::isMingw:
70 case X86Subtarget::isCygwin:
71 case X86Subtarget::isWindows:
72 return new TargetLoweringObjectFileCOFF();
77 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
78 : TargetLowering(TM, createTLOF(TM)) {
79 Subtarget = &TM.getSubtarget<X86Subtarget>();
80 X86ScalarSSEf64 = Subtarget->hasSSE2();
81 X86ScalarSSEf32 = Subtarget->hasSSE1();
82 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
84 RegInfo = TM.getRegisterInfo();
87 // Set up the TargetLowering object.
89 // X86 is weird, it always uses i8 for shift amounts and setcc results.
90 setShiftAmountType(MVT::i8);
91 setBooleanContents(ZeroOrOneBooleanContent);
92 setSchedulingPreference(SchedulingForRegPressure);
93 setStackPointerRegisterToSaveRestore(X86StackPtr);
95 if (Subtarget->isTargetDarwin()) {
96 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
97 setUseUnderscoreSetJmp(false);
98 setUseUnderscoreLongJmp(false);
99 } else if (Subtarget->isTargetMingw()) {
100 // MS runtime is weird: it exports _setjmp, but longjmp!
101 setUseUnderscoreSetJmp(true);
102 setUseUnderscoreLongJmp(false);
104 setUseUnderscoreSetJmp(true);
105 setUseUnderscoreLongJmp(true);
108 // Set up the register classes.
109 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
111 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
112 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
113 if (Subtarget->is64Bit())
114 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
116 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
118 // We don't accept any truncstore of integer registers.
119 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
121 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
122 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
124 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
125 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
126 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
128 // SETOEQ and SETUNE require checking two conditions.
129 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
130 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
131 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
132 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
133 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
136 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
138 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
139 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
140 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
142 if (Subtarget->is64Bit()) {
143 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
144 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
145 } else if (!UseSoftFloat) {
146 if (X86ScalarSSEf64) {
147 // We have an impenetrably clever algorithm for ui64->double only.
148 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
150 // We have an algorithm for SSE2, and we turn this into a 64-bit
151 // FILD for other targets.
152 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
155 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
157 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
158 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
161 // SSE has no i16 to fp conversion, only i32
162 if (X86ScalarSSEf32) {
163 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
164 // f32 and f64 cases are Legal, f80 case is not
165 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
167 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
168 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
172 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
175 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
176 // are Legal, f80 is custom lowered.
177 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
178 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
180 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
182 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
183 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
185 if (X86ScalarSSEf32) {
186 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
187 // f32 and f64 cases are Legal, f80 case is not
188 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
190 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
191 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
194 // Handle FP_TO_UINT by promoting the destination to a larger signed
196 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
197 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
198 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
200 if (Subtarget->is64Bit()) {
201 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
202 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
203 } else if (!UseSoftFloat) {
204 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
205 // Expand FP_TO_UINT into a select.
206 // FIXME: We would like to use a Custom expander here eventually to do
207 // the optimal thing for SSE vs. the default expansion in the legalizer.
208 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
210 // With SSE3 we can use fisttpll to convert to a signed i64; without
211 // SSE, we're stuck with a fistpll.
212 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
215 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
216 if (!X86ScalarSSEf64) {
217 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
218 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
221 // Scalar integer divide and remainder are lowered to use operations that
222 // produce two results, to match the available instructions. This exposes
223 // the two-result form to trivial CSE, which is able to combine x/y and x%y
224 // into a single instruction.
226 // Scalar integer multiply-high is also lowered to use two-result
227 // operations, to match the available instructions. However, plain multiply
228 // (low) operations are left as Legal, as there are single-result
229 // instructions for this in x86. Using the two-result multiply instructions
230 // when both high and low results are needed must be arranged by dagcombine.
231 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
232 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
233 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
234 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
235 setOperationAction(ISD::SREM , MVT::i8 , Expand);
236 setOperationAction(ISD::UREM , MVT::i8 , Expand);
237 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
238 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
239 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
240 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
241 setOperationAction(ISD::SREM , MVT::i16 , Expand);
242 setOperationAction(ISD::UREM , MVT::i16 , Expand);
243 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
244 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
245 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
246 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
247 setOperationAction(ISD::SREM , MVT::i32 , Expand);
248 setOperationAction(ISD::UREM , MVT::i32 , Expand);
249 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
250 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
251 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
252 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
253 setOperationAction(ISD::SREM , MVT::i64 , Expand);
254 setOperationAction(ISD::UREM , MVT::i64 , Expand);
256 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
257 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
258 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
259 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
260 if (Subtarget->is64Bit())
261 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
262 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
263 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
264 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
265 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
266 setOperationAction(ISD::FREM , MVT::f32 , Expand);
267 setOperationAction(ISD::FREM , MVT::f64 , Expand);
268 setOperationAction(ISD::FREM , MVT::f80 , Expand);
269 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
271 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
272 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
273 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
274 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
276 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
277 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
279 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
280 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
282 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
283 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
284 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
285 if (Subtarget->is64Bit()) {
286 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
287 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
288 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
291 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
292 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
294 // These should be promoted to a larger select which is supported.
295 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
296 // X86 wants to expand cmov itself.
297 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
299 setOperationAction(ISD::SELECT , MVT::i16 , Expand);
301 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
302 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
303 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
304 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
305 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
306 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
308 setOperationAction(ISD::SETCC , MVT::i16 , Expand);
310 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
311 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
312 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
313 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
314 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
315 if (Subtarget->is64Bit()) {
316 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
317 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
319 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
322 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
323 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
324 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
325 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
326 if (Subtarget->is64Bit())
327 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
328 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
329 if (Subtarget->is64Bit()) {
330 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
331 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
332 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
333 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
335 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
336 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
337 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
338 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
339 if (Subtarget->is64Bit()) {
340 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
341 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
342 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
345 if (Subtarget->hasSSE1())
346 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
348 if (!Subtarget->hasSSE2())
349 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
351 // Expand certain atomics
352 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
353 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
354 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
355 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
357 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
358 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
359 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
360 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
362 if (!Subtarget->is64Bit()) {
363 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
365 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
366 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
367 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
368 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
369 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
372 // Use the default ISD::DBG_STOPPOINT.
373 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
374 // FIXME - use subtarget debug flags
375 if (!Subtarget->isTargetDarwin() &&
376 !Subtarget->isTargetELF() &&
377 !Subtarget->isTargetCygMing()) {
378 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
379 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
382 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
383 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
384 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
385 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
386 if (Subtarget->is64Bit()) {
387 setExceptionPointerRegister(X86::RAX);
388 setExceptionSelectorRegister(X86::RDX);
390 setExceptionPointerRegister(X86::EAX);
391 setExceptionSelectorRegister(X86::EDX);
393 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
394 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
396 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
398 setOperationAction(ISD::TRAP, MVT::Other, Legal);
400 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
401 setOperationAction(ISD::VASTART , MVT::Other, Custom);
402 setOperationAction(ISD::VAEND , MVT::Other, Expand);
403 if (Subtarget->is64Bit()) {
404 setOperationAction(ISD::VAARG , MVT::Other, Custom);
405 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
407 setOperationAction(ISD::VAARG , MVT::Other, Expand);
408 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
411 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
412 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
413 if (Subtarget->is64Bit())
414 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
415 if (Subtarget->isTargetCygMing())
416 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
418 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
420 if (!UseSoftFloat && X86ScalarSSEf64) {
421 // f32 and f64 use SSE.
422 // Set up the FP register classes.
423 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
424 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
426 // Use ANDPD to simulate FABS.
427 setOperationAction(ISD::FABS , MVT::f64, Custom);
428 setOperationAction(ISD::FABS , MVT::f32, Custom);
430 // Use XORP to simulate FNEG.
431 setOperationAction(ISD::FNEG , MVT::f64, Custom);
432 setOperationAction(ISD::FNEG , MVT::f32, Custom);
434 // Use ANDPD and ORPD to simulate FCOPYSIGN.
435 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
436 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
438 // We don't support sin/cos/fmod
439 setOperationAction(ISD::FSIN , MVT::f64, Expand);
440 setOperationAction(ISD::FCOS , MVT::f64, Expand);
441 setOperationAction(ISD::FSIN , MVT::f32, Expand);
442 setOperationAction(ISD::FCOS , MVT::f32, Expand);
444 // Expand FP immediates into loads from the stack, except for the special
446 addLegalFPImmediate(APFloat(+0.0)); // xorpd
447 addLegalFPImmediate(APFloat(+0.0f)); // xorps
448 } else if (!UseSoftFloat && X86ScalarSSEf32) {
449 // Use SSE for f32, x87 for f64.
450 // Set up the FP register classes.
451 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
452 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
454 // Use ANDPS to simulate FABS.
455 setOperationAction(ISD::FABS , MVT::f32, Custom);
457 // Use XORP to simulate FNEG.
458 setOperationAction(ISD::FNEG , MVT::f32, Custom);
460 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
462 // Use ANDPS and ORPS to simulate FCOPYSIGN.
463 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
464 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
466 // We don't support sin/cos/fmod
467 setOperationAction(ISD::FSIN , MVT::f32, Expand);
468 setOperationAction(ISD::FCOS , MVT::f32, Expand);
470 // Special cases we handle for FP constants.
471 addLegalFPImmediate(APFloat(+0.0f)); // xorps
472 addLegalFPImmediate(APFloat(+0.0)); // FLD0
473 addLegalFPImmediate(APFloat(+1.0)); // FLD1
474 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
475 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
478 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
479 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
481 } else if (!UseSoftFloat) {
482 // f32 and f64 in x87.
483 // Set up the FP register classes.
484 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
485 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
487 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
488 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
489 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
490 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
493 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
494 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
496 addLegalFPImmediate(APFloat(+0.0)); // FLD0
497 addLegalFPImmediate(APFloat(+1.0)); // FLD1
498 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
499 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
500 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
501 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
502 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
503 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
506 // Long double always uses X87.
508 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
509 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
510 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
513 APFloat TmpFlt(+0.0);
514 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
516 addLegalFPImmediate(TmpFlt); // FLD0
518 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
519 APFloat TmpFlt2(+1.0);
520 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
522 addLegalFPImmediate(TmpFlt2); // FLD1
523 TmpFlt2.changeSign();
524 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
528 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
529 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
533 // Always use a library call for pow.
534 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
535 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
536 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
538 setOperationAction(ISD::FLOG, MVT::f80, Expand);
539 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
540 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
541 setOperationAction(ISD::FEXP, MVT::f80, Expand);
542 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
544 // First set operation action for all vector types to either promote
545 // (for widening) or expand (for scalarization). Then we will selectively
546 // turn on ones that can be effectively codegen'd.
547 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
548 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
549 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
564 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
565 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
599 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
600 // with -msoft-float, disable use of MMX as well.
601 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
602 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
603 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
604 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
605 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
606 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
608 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
609 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
610 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
611 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
613 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
614 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
615 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
616 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
618 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
619 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
621 setOperationAction(ISD::AND, MVT::v8i8, Promote);
622 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
623 setOperationAction(ISD::AND, MVT::v4i16, Promote);
624 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
625 setOperationAction(ISD::AND, MVT::v2i32, Promote);
626 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
627 setOperationAction(ISD::AND, MVT::v1i64, Legal);
629 setOperationAction(ISD::OR, MVT::v8i8, Promote);
630 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
631 setOperationAction(ISD::OR, MVT::v4i16, Promote);
632 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
633 setOperationAction(ISD::OR, MVT::v2i32, Promote);
634 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
635 setOperationAction(ISD::OR, MVT::v1i64, Legal);
637 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
638 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
639 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
640 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
641 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
642 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
643 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
645 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
646 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
647 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
648 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
649 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
650 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
651 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
652 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
653 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
655 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
656 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
657 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
658 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
659 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
661 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
662 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
663 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
664 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
666 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
667 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
668 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
669 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
671 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
673 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
674 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
675 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
676 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
677 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
678 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
679 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
680 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
681 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
684 if (!UseSoftFloat && Subtarget->hasSSE1()) {
685 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
687 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
688 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
689 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
690 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
691 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
692 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
693 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
694 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
695 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
696 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
697 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
698 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
701 if (!UseSoftFloat && Subtarget->hasSSE2()) {
702 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
704 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
705 // registers cannot be used even for integer operations.
706 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
707 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
708 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
709 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
711 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
712 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
713 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
714 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
715 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
716 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
717 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
718 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
719 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
720 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
721 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
722 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
723 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
724 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
725 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
726 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
728 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
729 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
730 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
731 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
733 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
734 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
735 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
736 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
737 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
739 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
740 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
741 EVT VT = (MVT::SimpleValueType)i;
742 // Do not attempt to custom lower non-power-of-2 vectors
743 if (!isPowerOf2_32(VT.getVectorNumElements()))
745 // Do not attempt to custom lower non-128-bit vectors
746 if (!VT.is128BitVector())
748 setOperationAction(ISD::BUILD_VECTOR,
749 VT.getSimpleVT().SimpleTy, Custom);
750 setOperationAction(ISD::VECTOR_SHUFFLE,
751 VT.getSimpleVT().SimpleTy, Custom);
752 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
753 VT.getSimpleVT().SimpleTy, Custom);
756 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
757 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
758 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
759 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
760 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
761 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
763 if (Subtarget->is64Bit()) {
764 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
765 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
768 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
769 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
770 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
773 // Do not attempt to promote non-128-bit vectors
774 if (!VT.is128BitVector()) {
777 setOperationAction(ISD::AND, SVT, Promote);
778 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
779 setOperationAction(ISD::OR, SVT, Promote);
780 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
781 setOperationAction(ISD::XOR, SVT, Promote);
782 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
783 setOperationAction(ISD::LOAD, SVT, Promote);
784 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
785 setOperationAction(ISD::SELECT, SVT, Promote);
786 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
789 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
791 // Custom lower v2i64 and v2f64 selects.
792 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
793 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
794 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
795 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
797 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
798 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
799 if (!DisableMMX && Subtarget->hasMMX()) {
800 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
801 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
805 if (Subtarget->hasSSE41()) {
806 // FIXME: Do we need to handle scalar-to-vector here?
807 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
809 // i8 and i16 vectors are custom , because the source register and source
810 // source memory operand types are not the same width. f32 vectors are
811 // custom since the immediate controlling the insert encodes additional
813 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
814 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
815 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
816 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
818 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
819 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
820 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
823 if (Subtarget->is64Bit()) {
824 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
825 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
829 if (Subtarget->hasSSE42()) {
830 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
833 if (!UseSoftFloat && Subtarget->hasAVX()) {
834 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
835 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
836 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
837 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
839 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
840 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
841 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
842 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
843 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
844 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
845 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
846 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
847 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
848 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
849 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
850 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
851 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
852 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
853 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
855 // Operations to consider commented out -v16i16 v32i8
856 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
857 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
858 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
859 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
860 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
861 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
862 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
863 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
864 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
865 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
866 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
867 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
868 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
869 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
871 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
872 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
873 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
874 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
876 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
877 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
878 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
879 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
880 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
882 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
883 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
884 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
885 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
886 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
887 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
890 // Not sure we want to do this since there are no 256-bit integer
893 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
894 // This includes 256-bit vectors
895 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
896 EVT VT = (MVT::SimpleValueType)i;
898 // Do not attempt to custom lower non-power-of-2 vectors
899 if (!isPowerOf2_32(VT.getVectorNumElements()))
902 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
903 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
904 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
907 if (Subtarget->is64Bit()) {
908 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
909 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
914 // Not sure we want to do this since there are no 256-bit integer
917 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
918 // Including 256-bit vectors
919 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
920 EVT VT = (MVT::SimpleValueType)i;
922 if (!VT.is256BitVector()) {
925 setOperationAction(ISD::AND, VT, Promote);
926 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
927 setOperationAction(ISD::OR, VT, Promote);
928 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
929 setOperationAction(ISD::XOR, VT, Promote);
930 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
931 setOperationAction(ISD::LOAD, VT, Promote);
932 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
933 setOperationAction(ISD::SELECT, VT, Promote);
934 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
937 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
941 // We want to custom lower some of our intrinsics.
942 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
944 // Add/Sub/Mul with overflow operations are custom lowered.
945 setOperationAction(ISD::SADDO, MVT::i32, Custom);
946 setOperationAction(ISD::SADDO, MVT::i64, Custom);
947 setOperationAction(ISD::UADDO, MVT::i32, Custom);
948 setOperationAction(ISD::UADDO, MVT::i64, Custom);
949 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
950 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
951 setOperationAction(ISD::USUBO, MVT::i32, Custom);
952 setOperationAction(ISD::USUBO, MVT::i64, Custom);
953 setOperationAction(ISD::SMULO, MVT::i32, Custom);
954 setOperationAction(ISD::SMULO, MVT::i64, Custom);
956 if (!Subtarget->is64Bit()) {
957 // These libcalls are not available in 32-bit.
958 setLibcallName(RTLIB::SHL_I128, 0);
959 setLibcallName(RTLIB::SRL_I128, 0);
960 setLibcallName(RTLIB::SRA_I128, 0);
963 // We have target-specific dag combine patterns for the following nodes:
964 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
965 setTargetDAGCombine(ISD::BUILD_VECTOR);
966 setTargetDAGCombine(ISD::SELECT);
967 setTargetDAGCombine(ISD::SHL);
968 setTargetDAGCombine(ISD::SRA);
969 setTargetDAGCombine(ISD::SRL);
970 setTargetDAGCombine(ISD::STORE);
971 setTargetDAGCombine(ISD::MEMBARRIER);
972 if (Subtarget->is64Bit())
973 setTargetDAGCombine(ISD::MUL);
975 computeRegisterProperties();
977 // FIXME: These should be based on subtarget info. Plus, the values should
978 // be smaller when we are in optimizing for size mode.
979 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
980 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
981 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
982 setPrefLoopAlignment(16);
983 benefitFromCodePlacementOpt = true;
987 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
992 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
993 /// the desired ByVal argument alignment.
994 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
997 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
998 if (VTy->getBitWidth() == 128)
1000 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1001 unsigned EltAlign = 0;
1002 getMaxByValAlign(ATy->getElementType(), EltAlign);
1003 if (EltAlign > MaxAlign)
1004 MaxAlign = EltAlign;
1005 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1006 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1007 unsigned EltAlign = 0;
1008 getMaxByValAlign(STy->getElementType(i), EltAlign);
1009 if (EltAlign > MaxAlign)
1010 MaxAlign = EltAlign;
1018 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1019 /// function arguments in the caller parameter area. For X86, aggregates
1020 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1021 /// are at 4-byte boundaries.
1022 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1023 if (Subtarget->is64Bit()) {
1024 // Max of 8 and alignment of type.
1025 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1032 if (Subtarget->hasSSE1())
1033 getMaxByValAlign(Ty, Align);
1037 /// getOptimalMemOpType - Returns the target specific optimal type for load
1038 /// and store operations as a result of memset, memcpy, and memmove
1039 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1042 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1043 bool isSrcConst, bool isSrcStr,
1044 SelectionDAG &DAG) const {
1045 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1046 // linux. This is because the stack realignment code can't handle certain
1047 // cases like PR2962. This should be removed when PR2962 is fixed.
1048 const Function *F = DAG.getMachineFunction().getFunction();
1049 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1050 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1051 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1053 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1056 if (Subtarget->is64Bit() && Size >= 8)
1061 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1063 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1064 SelectionDAG &DAG) const {
1065 if (usesGlobalOffsetTable())
1066 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1067 if (!Subtarget->is64Bit())
1068 // This doesn't have DebugLoc associated with it, but is not really the
1069 // same as a Register.
1070 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1075 /// getFunctionAlignment - Return the Log2 alignment of this function.
1076 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1077 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1080 //===----------------------------------------------------------------------===//
1081 // Return Value Calling Convention Implementation
1082 //===----------------------------------------------------------------------===//
1084 #include "X86GenCallingConv.inc"
1087 X86TargetLowering::LowerReturn(SDValue Chain,
1088 CallingConv::ID CallConv, bool isVarArg,
1089 const SmallVectorImpl<ISD::OutputArg> &Outs,
1090 DebugLoc dl, SelectionDAG &DAG) {
1092 SmallVector<CCValAssign, 16> RVLocs;
1093 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1094 RVLocs, *DAG.getContext());
1095 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1097 // If this is the first return lowered for this function, add the regs to the
1098 // liveout set for the function.
1099 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1100 for (unsigned i = 0; i != RVLocs.size(); ++i)
1101 if (RVLocs[i].isRegLoc())
1102 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1107 SmallVector<SDValue, 6> RetOps;
1108 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1109 // Operand #1 = Bytes To Pop
1110 RetOps.push_back(DAG.getTargetConstant(getBytesToPopOnReturn(), MVT::i16));
1112 // Copy the result values into the output registers.
1113 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1114 CCValAssign &VA = RVLocs[i];
1115 assert(VA.isRegLoc() && "Can only return in registers!");
1116 SDValue ValToCopy = Outs[i].Val;
1118 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1119 // the RET instruction and handled by the FP Stackifier.
1120 if (VA.getLocReg() == X86::ST0 ||
1121 VA.getLocReg() == X86::ST1) {
1122 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1123 // change the value to the FP stack register class.
1124 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1125 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1126 RetOps.push_back(ValToCopy);
1127 // Don't emit a copytoreg.
1131 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1132 // which is returned in RAX / RDX.
1133 if (Subtarget->is64Bit()) {
1134 EVT ValVT = ValToCopy.getValueType();
1135 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1136 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1137 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1138 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1142 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1143 Flag = Chain.getValue(1);
1146 // The x86-64 ABI for returning structs by value requires that we copy
1147 // the sret argument into %rax for the return. We saved the argument into
1148 // a virtual register in the entry block, so now we copy the value out
1150 if (Subtarget->is64Bit() &&
1151 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1152 MachineFunction &MF = DAG.getMachineFunction();
1153 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1154 unsigned Reg = FuncInfo->getSRetReturnReg();
1156 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1157 FuncInfo->setSRetReturnReg(Reg);
1159 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1161 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1162 Flag = Chain.getValue(1);
1165 RetOps[0] = Chain; // Update chain.
1167 // Add the flag if we have it.
1169 RetOps.push_back(Flag);
1171 return DAG.getNode(X86ISD::RET_FLAG, dl,
1172 MVT::Other, &RetOps[0], RetOps.size());
1175 /// LowerCallResult - Lower the result values of a call into the
1176 /// appropriate copies out of appropriate physical registers.
1179 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1180 CallingConv::ID CallConv, bool isVarArg,
1181 const SmallVectorImpl<ISD::InputArg> &Ins,
1182 DebugLoc dl, SelectionDAG &DAG,
1183 SmallVectorImpl<SDValue> &InVals) {
1185 // Assign locations to each value returned by this call.
1186 SmallVector<CCValAssign, 16> RVLocs;
1187 bool Is64Bit = Subtarget->is64Bit();
1188 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1189 RVLocs, *DAG.getContext());
1190 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1192 // Copy all of the result registers out of their specified physreg.
1193 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1194 CCValAssign &VA = RVLocs[i];
1195 EVT CopyVT = VA.getValVT();
1197 // If this is x86-64, and we disabled SSE, we can't return FP values
1198 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1199 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1200 llvm_report_error("SSE register return with SSE disabled");
1203 // If this is a call to a function that returns an fp value on the floating
1204 // point stack, but where we prefer to use the value in xmm registers, copy
1205 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1206 if ((VA.getLocReg() == X86::ST0 ||
1207 VA.getLocReg() == X86::ST1) &&
1208 isScalarFPTypeInSSEReg(VA.getValVT())) {
1213 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1214 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1215 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1216 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1217 MVT::v2i64, InFlag).getValue(1);
1218 Val = Chain.getValue(0);
1219 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1220 Val, DAG.getConstant(0, MVT::i64));
1222 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1223 MVT::i64, InFlag).getValue(1);
1224 Val = Chain.getValue(0);
1226 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1228 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1229 CopyVT, InFlag).getValue(1);
1230 Val = Chain.getValue(0);
1232 InFlag = Chain.getValue(2);
1234 if (CopyVT != VA.getValVT()) {
1235 // Round the F80 the right size, which also moves to the appropriate xmm
1237 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1238 // This truncation won't change the value.
1239 DAG.getIntPtrConstant(1));
1242 InVals.push_back(Val);
1249 //===----------------------------------------------------------------------===//
1250 // C & StdCall & Fast Calling Convention implementation
1251 //===----------------------------------------------------------------------===//
1252 // StdCall calling convention seems to be standard for many Windows' API
1253 // routines and around. It differs from C calling convention just a little:
1254 // callee should clean up the stack, not caller. Symbols should be also
1255 // decorated in some fancy way :) It doesn't support any vector arguments.
1256 // For info on fast calling convention see Fast Calling Convention (tail call)
1257 // implementation LowerX86_32FastCCCallTo.
1259 /// CallIsStructReturn - Determines whether a call uses struct return
1261 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1265 return Outs[0].Flags.isSRet();
1268 /// ArgsAreStructReturn - Determines whether a function uses struct
1269 /// return semantics.
1271 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1275 return Ins[0].Flags.isSRet();
1278 /// IsCalleePop - Determines whether the callee is required to pop its
1279 /// own arguments. Callee pop is necessary to support tail calls.
1280 bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){
1284 switch (CallingConv) {
1287 case CallingConv::X86_StdCall:
1288 return !Subtarget->is64Bit();
1289 case CallingConv::X86_FastCall:
1290 return !Subtarget->is64Bit();
1291 case CallingConv::Fast:
1292 return PerformTailCallOpt;
1296 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1297 /// given CallingConvention value.
1298 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1299 if (Subtarget->is64Bit()) {
1300 if (Subtarget->isTargetWin64())
1301 return CC_X86_Win64_C;
1306 if (CC == CallingConv::X86_FastCall)
1307 return CC_X86_32_FastCall;
1308 else if (CC == CallingConv::Fast)
1309 return CC_X86_32_FastCC;
1314 /// NameDecorationForCallConv - Selects the appropriate decoration to
1315 /// apply to a MachineFunction containing a given calling convention.
1317 X86TargetLowering::NameDecorationForCallConv(CallingConv::ID CallConv) {
1318 if (CallConv == CallingConv::X86_FastCall)
1320 else if (CallConv == CallingConv::X86_StdCall)
1326 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1327 /// by "Src" to address "Dst" with size and alignment information specified by
1328 /// the specific parameter attribute. The copy will be passed as a byval
1329 /// function parameter.
1331 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1332 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1334 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1335 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1336 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1340 X86TargetLowering::LowerMemArgument(SDValue Chain,
1341 CallingConv::ID CallConv,
1342 const SmallVectorImpl<ISD::InputArg> &Ins,
1343 DebugLoc dl, SelectionDAG &DAG,
1344 const CCValAssign &VA,
1345 MachineFrameInfo *MFI,
1348 // Create the nodes corresponding to a load from this parameter slot.
1349 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1350 bool AlwaysUseMutable = (CallConv==CallingConv::Fast) && PerformTailCallOpt;
1351 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1354 // If value is passed by pointer we have address passed instead of the value
1356 if (VA.getLocInfo() == CCValAssign::Indirect)
1357 ValVT = VA.getLocVT();
1359 ValVT = VA.getValVT();
1361 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1362 // changed with more analysis.
1363 // In case of tail call optimization mark all arguments mutable. Since they
1364 // could be overwritten by lowering of arguments in case of a tail call.
1365 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1366 VA.getLocMemOffset(), isImmutable);
1367 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1368 if (Flags.isByVal())
1370 return DAG.getLoad(ValVT, dl, Chain, FIN,
1371 PseudoSourceValue::getFixedStack(FI), 0);
1375 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1376 CallingConv::ID CallConv,
1378 const SmallVectorImpl<ISD::InputArg> &Ins,
1381 SmallVectorImpl<SDValue> &InVals) {
1383 MachineFunction &MF = DAG.getMachineFunction();
1384 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1386 const Function* Fn = MF.getFunction();
1387 if (Fn->hasExternalLinkage() &&
1388 Subtarget->isTargetCygMing() &&
1389 Fn->getName() == "main")
1390 FuncInfo->setForceFramePointer(true);
1392 // Decorate the function name.
1393 FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv));
1395 MachineFrameInfo *MFI = MF.getFrameInfo();
1396 bool Is64Bit = Subtarget->is64Bit();
1397 bool IsWin64 = Subtarget->isTargetWin64();
1399 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1400 "Var args not supported with calling convention fastcc");
1402 // Assign locations to all of the incoming arguments.
1403 SmallVector<CCValAssign, 16> ArgLocs;
1404 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1405 ArgLocs, *DAG.getContext());
1406 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1408 unsigned LastVal = ~0U;
1410 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1411 CCValAssign &VA = ArgLocs[i];
1412 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1414 assert(VA.getValNo() != LastVal &&
1415 "Don't support value assigned to multiple locs yet");
1416 LastVal = VA.getValNo();
1418 if (VA.isRegLoc()) {
1419 EVT RegVT = VA.getLocVT();
1420 TargetRegisterClass *RC = NULL;
1421 if (RegVT == MVT::i32)
1422 RC = X86::GR32RegisterClass;
1423 else if (Is64Bit && RegVT == MVT::i64)
1424 RC = X86::GR64RegisterClass;
1425 else if (RegVT == MVT::f32)
1426 RC = X86::FR32RegisterClass;
1427 else if (RegVT == MVT::f64)
1428 RC = X86::FR64RegisterClass;
1429 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1430 RC = X86::VR128RegisterClass;
1431 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1432 RC = X86::VR64RegisterClass;
1434 llvm_unreachable("Unknown argument type!");
1436 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1437 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1439 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1440 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1442 if (VA.getLocInfo() == CCValAssign::SExt)
1443 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1444 DAG.getValueType(VA.getValVT()));
1445 else if (VA.getLocInfo() == CCValAssign::ZExt)
1446 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1447 DAG.getValueType(VA.getValVT()));
1448 else if (VA.getLocInfo() == CCValAssign::BCvt)
1449 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1451 if (VA.isExtInLoc()) {
1452 // Handle MMX values passed in XMM regs.
1453 if (RegVT.isVector()) {
1454 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1455 ArgValue, DAG.getConstant(0, MVT::i64));
1456 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1458 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1461 assert(VA.isMemLoc());
1462 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1465 // If value is passed via pointer - do a load.
1466 if (VA.getLocInfo() == CCValAssign::Indirect)
1467 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0);
1469 InVals.push_back(ArgValue);
1472 // The x86-64 ABI for returning structs by value requires that we copy
1473 // the sret argument into %rax for the return. Save the argument into
1474 // a virtual register so that we can access it from the return points.
1475 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1477 unsigned Reg = FuncInfo->getSRetReturnReg();
1479 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1480 FuncInfo->setSRetReturnReg(Reg);
1482 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1483 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1486 unsigned StackSize = CCInfo.getNextStackOffset();
1487 // align stack specially for tail calls
1488 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1489 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1491 // If the function takes variable number of arguments, make a frame index for
1492 // the start of the first vararg value... for expansion of llvm.va_start.
1494 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1495 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1498 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1500 // FIXME: We should really autogenerate these arrays
1501 static const unsigned GPR64ArgRegsWin64[] = {
1502 X86::RCX, X86::RDX, X86::R8, X86::R9
1504 static const unsigned XMMArgRegsWin64[] = {
1505 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1507 static const unsigned GPR64ArgRegs64Bit[] = {
1508 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1510 static const unsigned XMMArgRegs64Bit[] = {
1511 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1512 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1514 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1517 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1518 GPR64ArgRegs = GPR64ArgRegsWin64;
1519 XMMArgRegs = XMMArgRegsWin64;
1521 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1522 GPR64ArgRegs = GPR64ArgRegs64Bit;
1523 XMMArgRegs = XMMArgRegs64Bit;
1525 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1527 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1530 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1531 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1532 "SSE register cannot be used when SSE is disabled!");
1533 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1534 "SSE register cannot be used when SSE is disabled!");
1535 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1536 // Kernel mode asks for SSE to be disabled, so don't push them
1538 TotalNumXMMRegs = 0;
1540 // For X86-64, if there are vararg parameters that are passed via
1541 // registers, then we must store them to their spots on the stack so they
1542 // may be loaded by deferencing the result of va_next.
1543 VarArgsGPOffset = NumIntRegs * 8;
1544 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1545 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1546 TotalNumXMMRegs * 16, 16);
1548 // Store the integer parameter registers.
1549 SmallVector<SDValue, 8> MemOps;
1550 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1551 unsigned Offset = VarArgsGPOffset;
1552 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1553 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1554 DAG.getIntPtrConstant(Offset));
1555 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1556 X86::GR64RegisterClass);
1557 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1559 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1560 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
1562 MemOps.push_back(Store);
1566 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1567 // Now store the XMM (fp + vector) parameter registers.
1568 SmallVector<SDValue, 11> SaveXMMOps;
1569 SaveXMMOps.push_back(Chain);
1571 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1572 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1573 SaveXMMOps.push_back(ALVal);
1575 SaveXMMOps.push_back(DAG.getIntPtrConstant(RegSaveFrameIndex));
1576 SaveXMMOps.push_back(DAG.getIntPtrConstant(VarArgsFPOffset));
1578 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1579 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1580 X86::VR128RegisterClass);
1581 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1582 SaveXMMOps.push_back(Val);
1584 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1586 &SaveXMMOps[0], SaveXMMOps.size()));
1589 if (!MemOps.empty())
1590 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1591 &MemOps[0], MemOps.size());
1595 // Some CCs need callee pop.
1596 if (IsCalleePop(isVarArg, CallConv)) {
1597 BytesToPopOnReturn = StackSize; // Callee pops everything.
1598 BytesCallerReserves = 0;
1600 BytesToPopOnReturn = 0; // Callee pops nothing.
1601 // If this is an sret function, the return should pop the hidden pointer.
1602 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1603 BytesToPopOnReturn = 4;
1604 BytesCallerReserves = StackSize;
1608 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1609 if (CallConv == CallingConv::X86_FastCall)
1610 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1613 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1619 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1620 SDValue StackPtr, SDValue Arg,
1621 DebugLoc dl, SelectionDAG &DAG,
1622 const CCValAssign &VA,
1623 ISD::ArgFlagsTy Flags) {
1624 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1625 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1626 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1627 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1628 if (Flags.isByVal()) {
1629 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1631 return DAG.getStore(Chain, dl, Arg, PtrOff,
1632 PseudoSourceValue::getStack(), LocMemOffset);
1635 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1636 /// optimization is performed and it is required.
1638 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1639 SDValue &OutRetAddr,
1645 if (!IsTailCall || FPDiff==0) return Chain;
1647 // Adjust the Return address stack slot.
1648 EVT VT = getPointerTy();
1649 OutRetAddr = getReturnAddressFrameIndex(DAG);
1651 // Load the "old" Return address.
1652 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1653 return SDValue(OutRetAddr.getNode(), 1);
1656 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1657 /// optimization is performed and it is required (FPDiff!=0).
1659 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1660 SDValue Chain, SDValue RetAddrFrIdx,
1661 bool Is64Bit, int FPDiff, DebugLoc dl) {
1662 // Store the return address to the appropriate stack slot.
1663 if (!FPDiff) return Chain;
1664 // Calculate the new stack slot for the return address.
1665 int SlotSize = Is64Bit ? 8 : 4;
1666 int NewReturnAddrFI =
1667 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1668 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1669 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1670 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1671 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1676 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1677 CallingConv::ID CallConv, bool isVarArg,
1679 const SmallVectorImpl<ISD::OutputArg> &Outs,
1680 const SmallVectorImpl<ISD::InputArg> &Ins,
1681 DebugLoc dl, SelectionDAG &DAG,
1682 SmallVectorImpl<SDValue> &InVals) {
1684 MachineFunction &MF = DAG.getMachineFunction();
1685 bool Is64Bit = Subtarget->is64Bit();
1686 bool IsStructRet = CallIsStructReturn(Outs);
1688 assert((!isTailCall ||
1689 (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
1690 "IsEligibleForTailCallOptimization missed a case!");
1691 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1692 "Var args not supported with calling convention fastcc");
1694 // Analyze operands of the call, assigning locations to each operand.
1695 SmallVector<CCValAssign, 16> ArgLocs;
1696 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1697 ArgLocs, *DAG.getContext());
1698 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1700 // Get a count of how many bytes are to be pushed on the stack.
1701 unsigned NumBytes = CCInfo.getNextStackOffset();
1702 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1703 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1707 // Lower arguments at fp - stackoffset + fpdiff.
1708 unsigned NumBytesCallerPushed =
1709 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1710 FPDiff = NumBytesCallerPushed - NumBytes;
1712 // Set the delta of movement of the returnaddr stackslot.
1713 // But only set if delta is greater than previous delta.
1714 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1715 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1718 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1720 SDValue RetAddrFrIdx;
1721 // Load return adress for tail calls.
1722 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit,
1725 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1726 SmallVector<SDValue, 8> MemOpChains;
1729 // Walk the register/memloc assignments, inserting copies/loads. In the case
1730 // of tail call optimization arguments are handle later.
1731 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1732 CCValAssign &VA = ArgLocs[i];
1733 EVT RegVT = VA.getLocVT();
1734 SDValue Arg = Outs[i].Val;
1735 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1736 bool isByVal = Flags.isByVal();
1738 // Promote the value if needed.
1739 switch (VA.getLocInfo()) {
1740 default: llvm_unreachable("Unknown loc info!");
1741 case CCValAssign::Full: break;
1742 case CCValAssign::SExt:
1743 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1745 case CCValAssign::ZExt:
1746 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1748 case CCValAssign::AExt:
1749 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1750 // Special case: passing MMX values in XMM registers.
1751 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1752 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1753 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1755 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1757 case CCValAssign::BCvt:
1758 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1760 case CCValAssign::Indirect: {
1761 // Store the argument.
1762 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1763 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1764 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1765 PseudoSourceValue::getFixedStack(FI), 0);
1771 if (VA.isRegLoc()) {
1772 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1774 if (!isTailCall || (isTailCall && isByVal)) {
1775 assert(VA.isMemLoc());
1776 if (StackPtr.getNode() == 0)
1777 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1779 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1780 dl, DAG, VA, Flags));
1785 if (!MemOpChains.empty())
1786 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1787 &MemOpChains[0], MemOpChains.size());
1789 // Build a sequence of copy-to-reg nodes chained together with token chain
1790 // and flag operands which copy the outgoing args into registers.
1792 // Tail call byval lowering might overwrite argument registers so in case of
1793 // tail call optimization the copies to registers are lowered later.
1795 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1796 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1797 RegsToPass[i].second, InFlag);
1798 InFlag = Chain.getValue(1);
1802 if (Subtarget->isPICStyleGOT()) {
1803 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1806 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1807 DAG.getNode(X86ISD::GlobalBaseReg,
1808 DebugLoc::getUnknownLoc(),
1811 InFlag = Chain.getValue(1);
1813 // If we are tail calling and generating PIC/GOT style code load the
1814 // address of the callee into ECX. The value in ecx is used as target of
1815 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1816 // for tail calls on PIC/GOT architectures. Normally we would just put the
1817 // address of GOT into ebx and then call target@PLT. But for tail calls
1818 // ebx would be restored (since ebx is callee saved) before jumping to the
1821 // Note: The actual moving to ECX is done further down.
1822 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1823 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1824 !G->getGlobal()->hasProtectedVisibility())
1825 Callee = LowerGlobalAddress(Callee, DAG);
1826 else if (isa<ExternalSymbolSDNode>(Callee))
1827 Callee = LowerExternalSymbol(Callee, DAG);
1831 if (Is64Bit && isVarArg) {
1832 // From AMD64 ABI document:
1833 // For calls that may call functions that use varargs or stdargs
1834 // (prototype-less calls or calls to functions containing ellipsis (...) in
1835 // the declaration) %al is used as hidden argument to specify the number
1836 // of SSE registers used. The contents of %al do not need to match exactly
1837 // the number of registers, but must be an ubound on the number of SSE
1838 // registers used and is in the range 0 - 8 inclusive.
1840 // FIXME: Verify this on Win64
1841 // Count the number of XMM registers allocated.
1842 static const unsigned XMMArgRegs[] = {
1843 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1844 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1846 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1847 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1848 && "SSE registers cannot be used when SSE is disabled");
1850 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1851 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1852 InFlag = Chain.getValue(1);
1856 // For tail calls lower the arguments to the 'real' stack slot.
1858 // Force all the incoming stack arguments to be loaded from the stack
1859 // before any new outgoing arguments are stored to the stack, because the
1860 // outgoing stack slots may alias the incoming argument stack slots, and
1861 // the alias isn't otherwise explicit. This is slightly more conservative
1862 // than necessary, because it means that each store effectively depends
1863 // on every argument instead of just those arguments it would clobber.
1864 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1866 SmallVector<SDValue, 8> MemOpChains2;
1869 // Do not flag preceeding copytoreg stuff together with the following stuff.
1871 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1872 CCValAssign &VA = ArgLocs[i];
1873 if (!VA.isRegLoc()) {
1874 assert(VA.isMemLoc());
1875 SDValue Arg = Outs[i].Val;
1876 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1877 // Create frame index.
1878 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1879 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1880 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1881 FIN = DAG.getFrameIndex(FI, getPointerTy());
1883 if (Flags.isByVal()) {
1884 // Copy relative to framepointer.
1885 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1886 if (StackPtr.getNode() == 0)
1887 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1889 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1891 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
1895 // Store relative to framepointer.
1896 MemOpChains2.push_back(
1897 DAG.getStore(ArgChain, dl, Arg, FIN,
1898 PseudoSourceValue::getFixedStack(FI), 0));
1903 if (!MemOpChains2.empty())
1904 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1905 &MemOpChains2[0], MemOpChains2.size());
1907 // Copy arguments to their registers.
1908 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1909 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1910 RegsToPass[i].second, InFlag);
1911 InFlag = Chain.getValue(1);
1915 // Store the return address to the appropriate stack slot.
1916 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1920 // If the callee is a GlobalAddress node (quite common, every direct call is)
1921 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1922 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1923 // We should use extra load for direct calls to dllimported functions in
1925 GlobalValue *GV = G->getGlobal();
1926 if (!GV->hasDLLImportLinkage()) {
1927 unsigned char OpFlags = 0;
1929 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1930 // external symbols most go through the PLT in PIC mode. If the symbol
1931 // has hidden or protected visibility, or if it is static or local, then
1932 // we don't need to use the PLT - we can directly call it.
1933 if (Subtarget->isTargetELF() &&
1934 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1935 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1936 OpFlags = X86II::MO_PLT;
1937 } else if (Subtarget->isPICStyleStubAny() &&
1938 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1939 Subtarget->getDarwinVers() < 9) {
1940 // PC-relative references to external symbols should go through $stub,
1941 // unless we're building with the leopard linker or later, which
1942 // automatically synthesizes these stubs.
1943 OpFlags = X86II::MO_DARWIN_STUB;
1946 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
1947 G->getOffset(), OpFlags);
1949 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1950 unsigned char OpFlags = 0;
1952 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
1953 // symbols should go through the PLT.
1954 if (Subtarget->isTargetELF() &&
1955 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1956 OpFlags = X86II::MO_PLT;
1957 } else if (Subtarget->isPICStyleStubAny() &&
1958 Subtarget->getDarwinVers() < 9) {
1959 // PC-relative references to external symbols should go through $stub,
1960 // unless we're building with the leopard linker or later, which
1961 // automatically synthesizes these stubs.
1962 OpFlags = X86II::MO_DARWIN_STUB;
1965 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
1967 } else if (isTailCall) {
1968 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
1970 Chain = DAG.getCopyToReg(Chain, dl,
1971 DAG.getRegister(Opc, getPointerTy()),
1973 Callee = DAG.getRegister(Opc, getPointerTy());
1974 // Add register as live out.
1975 MF.getRegInfo().addLiveOut(Opc);
1978 // Returns a chain & a flag for retval copy to use.
1979 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1980 SmallVector<SDValue, 8> Ops;
1983 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1984 DAG.getIntPtrConstant(0, true), InFlag);
1985 InFlag = Chain.getValue(1);
1988 Ops.push_back(Chain);
1989 Ops.push_back(Callee);
1992 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1994 // Add argument registers to the end of the list so that they are known live
1996 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1997 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1998 RegsToPass[i].second.getValueType()));
2000 // Add an implicit use GOT pointer in EBX.
2001 if (!isTailCall && Subtarget->isPICStyleGOT())
2002 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2004 // Add an implicit use of AL for x86 vararg functions.
2005 if (Is64Bit && isVarArg)
2006 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2008 if (InFlag.getNode())
2009 Ops.push_back(InFlag);
2012 // If this is the first return lowered for this function, add the regs
2013 // to the liveout set for the function.
2014 if (MF.getRegInfo().liveout_empty()) {
2015 SmallVector<CCValAssign, 16> RVLocs;
2016 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2018 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2019 for (unsigned i = 0; i != RVLocs.size(); ++i)
2020 if (RVLocs[i].isRegLoc())
2021 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2024 assert(((Callee.getOpcode() == ISD::Register &&
2025 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
2026 cast<RegisterSDNode>(Callee)->getReg() == X86::R9)) ||
2027 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2028 Callee.getOpcode() == ISD::TargetGlobalAddress) &&
2029 "Expecting an global address, external symbol, or register");
2031 return DAG.getNode(X86ISD::TC_RETURN, dl,
2032 NodeTys, &Ops[0], Ops.size());
2035 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2036 InFlag = Chain.getValue(1);
2038 // Create the CALLSEQ_END node.
2039 unsigned NumBytesForCalleeToPush;
2040 if (IsCalleePop(isVarArg, CallConv))
2041 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2042 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
2043 // If this is is a call to a struct-return function, the callee
2044 // pops the hidden struct pointer, so we have to push it back.
2045 // This is common for Darwin/X86, Linux & Mingw32 targets.
2046 NumBytesForCalleeToPush = 4;
2048 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2050 // Returns a flag for retval copy to use.
2051 Chain = DAG.getCALLSEQ_END(Chain,
2052 DAG.getIntPtrConstant(NumBytes, true),
2053 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2056 InFlag = Chain.getValue(1);
2058 // Handle result values, copying them out of physregs into vregs that we
2060 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2061 Ins, dl, DAG, InVals);
2065 //===----------------------------------------------------------------------===//
2066 // Fast Calling Convention (tail call) implementation
2067 //===----------------------------------------------------------------------===//
2069 // Like std call, callee cleans arguments, convention except that ECX is
2070 // reserved for storing the tail called function address. Only 2 registers are
2071 // free for argument passing (inreg). Tail call optimization is performed
2073 // * tailcallopt is enabled
2074 // * caller/callee are fastcc
2075 // On X86_64 architecture with GOT-style position independent code only local
2076 // (within module) calls are supported at the moment.
2077 // To keep the stack aligned according to platform abi the function
2078 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2079 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2080 // If a tail called function callee has more arguments than the caller the
2081 // caller needs to make sure that there is room to move the RETADDR to. This is
2082 // achieved by reserving an area the size of the argument delta right after the
2083 // original REtADDR, but before the saved framepointer or the spilled registers
2084 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2096 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2097 /// for a 16 byte align requirement.
2098 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2099 SelectionDAG& DAG) {
2100 MachineFunction &MF = DAG.getMachineFunction();
2101 const TargetMachine &TM = MF.getTarget();
2102 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2103 unsigned StackAlignment = TFI.getStackAlignment();
2104 uint64_t AlignMask = StackAlignment - 1;
2105 int64_t Offset = StackSize;
2106 uint64_t SlotSize = TD->getPointerSize();
2107 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2108 // Number smaller than 12 so just add the difference.
2109 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2111 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2112 Offset = ((~AlignMask) & Offset) + StackAlignment +
2113 (StackAlignment-SlotSize);
2118 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2119 /// for tail call optimization. Targets which want to do tail call
2120 /// optimization should implement this function.
2122 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2123 CallingConv::ID CalleeCC,
2125 const SmallVectorImpl<ISD::InputArg> &Ins,
2126 SelectionDAG& DAG) const {
2127 MachineFunction &MF = DAG.getMachineFunction();
2128 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2129 return CalleeCC == CallingConv::Fast && CallerCC == CalleeCC;
2133 X86TargetLowering::createFastISel(MachineFunction &mf,
2134 MachineModuleInfo *mmo,
2136 DenseMap<const Value *, unsigned> &vm,
2137 DenseMap<const BasicBlock *,
2138 MachineBasicBlock *> &bm,
2139 DenseMap<const AllocaInst *, int> &am
2141 , SmallSet<Instruction*, 8> &cil
2144 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2152 //===----------------------------------------------------------------------===//
2153 // Other Lowering Hooks
2154 //===----------------------------------------------------------------------===//
2157 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2158 MachineFunction &MF = DAG.getMachineFunction();
2159 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2160 int ReturnAddrIndex = FuncInfo->getRAIndex();
2162 if (ReturnAddrIndex == 0) {
2163 // Set up a frame object for the return address.
2164 uint64_t SlotSize = TD->getPointerSize();
2165 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
2166 FuncInfo->setRAIndex(ReturnAddrIndex);
2169 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2173 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2174 bool hasSymbolicDisplacement) {
2175 // Offset should fit into 32 bit immediate field.
2176 if (!isInt32(Offset))
2179 // If we don't have a symbolic displacement - we don't have any extra
2181 if (!hasSymbolicDisplacement)
2184 // FIXME: Some tweaks might be needed for medium code model.
2185 if (M != CodeModel::Small && M != CodeModel::Kernel)
2188 // For small code model we assume that latest object is 16MB before end of 31
2189 // bits boundary. We may also accept pretty large negative constants knowing
2190 // that all objects are in the positive half of address space.
2191 if (M == CodeModel::Small && Offset < 16*1024*1024)
2194 // For kernel code model we know that all object resist in the negative half
2195 // of 32bits address space. We may not accept negative offsets, since they may
2196 // be just off and we may accept pretty large positive ones.
2197 if (M == CodeModel::Kernel && Offset > 0)
2203 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2204 /// specific condition code, returning the condition code and the LHS/RHS of the
2205 /// comparison to make.
2206 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2207 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2209 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2210 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2211 // X > -1 -> X == 0, jump !sign.
2212 RHS = DAG.getConstant(0, RHS.getValueType());
2213 return X86::COND_NS;
2214 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2215 // X < 0 -> X == 0, jump on sign.
2217 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2219 RHS = DAG.getConstant(0, RHS.getValueType());
2220 return X86::COND_LE;
2224 switch (SetCCOpcode) {
2225 default: llvm_unreachable("Invalid integer condition!");
2226 case ISD::SETEQ: return X86::COND_E;
2227 case ISD::SETGT: return X86::COND_G;
2228 case ISD::SETGE: return X86::COND_GE;
2229 case ISD::SETLT: return X86::COND_L;
2230 case ISD::SETLE: return X86::COND_LE;
2231 case ISD::SETNE: return X86::COND_NE;
2232 case ISD::SETULT: return X86::COND_B;
2233 case ISD::SETUGT: return X86::COND_A;
2234 case ISD::SETULE: return X86::COND_BE;
2235 case ISD::SETUGE: return X86::COND_AE;
2239 // First determine if it is required or is profitable to flip the operands.
2241 // If LHS is a foldable load, but RHS is not, flip the condition.
2242 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2243 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2244 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2245 std::swap(LHS, RHS);
2248 switch (SetCCOpcode) {
2254 std::swap(LHS, RHS);
2258 // On a floating point condition, the flags are set as follows:
2260 // 0 | 0 | 0 | X > Y
2261 // 0 | 0 | 1 | X < Y
2262 // 1 | 0 | 0 | X == Y
2263 // 1 | 1 | 1 | unordered
2264 switch (SetCCOpcode) {
2265 default: llvm_unreachable("Condcode should be pre-legalized away");
2267 case ISD::SETEQ: return X86::COND_E;
2268 case ISD::SETOLT: // flipped
2270 case ISD::SETGT: return X86::COND_A;
2271 case ISD::SETOLE: // flipped
2273 case ISD::SETGE: return X86::COND_AE;
2274 case ISD::SETUGT: // flipped
2276 case ISD::SETLT: return X86::COND_B;
2277 case ISD::SETUGE: // flipped
2279 case ISD::SETLE: return X86::COND_BE;
2281 case ISD::SETNE: return X86::COND_NE;
2282 case ISD::SETUO: return X86::COND_P;
2283 case ISD::SETO: return X86::COND_NP;
2287 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2288 /// code. Current x86 isa includes the following FP cmov instructions:
2289 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2290 static bool hasFPCMov(unsigned X86CC) {
2306 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2307 /// the specified range (L, H].
2308 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2309 return (Val < 0) || (Val >= Low && Val < Hi);
2312 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2313 /// specified value.
2314 static bool isUndefOrEqual(int Val, int CmpVal) {
2315 if (Val < 0 || Val == CmpVal)
2320 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2321 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2322 /// the second operand.
2323 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2324 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2325 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2326 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2327 return (Mask[0] < 2 && Mask[1] < 2);
2331 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2332 SmallVector<int, 8> M;
2334 return ::isPSHUFDMask(M, N->getValueType(0));
2337 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2338 /// is suitable for input to PSHUFHW.
2339 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2340 if (VT != MVT::v8i16)
2343 // Lower quadword copied in order or undef.
2344 for (int i = 0; i != 4; ++i)
2345 if (Mask[i] >= 0 && Mask[i] != i)
2348 // Upper quadword shuffled.
2349 for (int i = 4; i != 8; ++i)
2350 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2356 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2357 SmallVector<int, 8> M;
2359 return ::isPSHUFHWMask(M, N->getValueType(0));
2362 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2363 /// is suitable for input to PSHUFLW.
2364 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2365 if (VT != MVT::v8i16)
2368 // Upper quadword copied in order.
2369 for (int i = 4; i != 8; ++i)
2370 if (Mask[i] >= 0 && Mask[i] != i)
2373 // Lower quadword shuffled.
2374 for (int i = 0; i != 4; ++i)
2381 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2382 SmallVector<int, 8> M;
2384 return ::isPSHUFLWMask(M, N->getValueType(0));
2387 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2388 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2389 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2390 int NumElems = VT.getVectorNumElements();
2391 if (NumElems != 2 && NumElems != 4)
2394 int Half = NumElems / 2;
2395 for (int i = 0; i < Half; ++i)
2396 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2398 for (int i = Half; i < NumElems; ++i)
2399 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2405 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2406 SmallVector<int, 8> M;
2408 return ::isSHUFPMask(M, N->getValueType(0));
2411 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2412 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2413 /// half elements to come from vector 1 (which would equal the dest.) and
2414 /// the upper half to come from vector 2.
2415 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2416 int NumElems = VT.getVectorNumElements();
2418 if (NumElems != 2 && NumElems != 4)
2421 int Half = NumElems / 2;
2422 for (int i = 0; i < Half; ++i)
2423 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2425 for (int i = Half; i < NumElems; ++i)
2426 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2431 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2432 SmallVector<int, 8> M;
2434 return isCommutedSHUFPMask(M, N->getValueType(0));
2437 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2438 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2439 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2440 if (N->getValueType(0).getVectorNumElements() != 4)
2443 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2444 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2445 isUndefOrEqual(N->getMaskElt(1), 7) &&
2446 isUndefOrEqual(N->getMaskElt(2), 2) &&
2447 isUndefOrEqual(N->getMaskElt(3), 3);
2450 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2451 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2452 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2453 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2455 if (NumElems != 2 && NumElems != 4)
2458 for (unsigned i = 0; i < NumElems/2; ++i)
2459 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2462 for (unsigned i = NumElems/2; i < NumElems; ++i)
2463 if (!isUndefOrEqual(N->getMaskElt(i), i))
2469 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2470 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2472 bool X86::isMOVHPMask(ShuffleVectorSDNode *N) {
2473 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2475 if (NumElems != 2 && NumElems != 4)
2478 for (unsigned i = 0; i < NumElems/2; ++i)
2479 if (!isUndefOrEqual(N->getMaskElt(i), i))
2482 for (unsigned i = 0; i < NumElems/2; ++i)
2483 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2489 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2490 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2492 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2493 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2498 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2499 isUndefOrEqual(N->getMaskElt(1), 3) &&
2500 isUndefOrEqual(N->getMaskElt(2), 2) &&
2501 isUndefOrEqual(N->getMaskElt(3), 3);
2504 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2505 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2506 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2507 bool V2IsSplat = false) {
2508 int NumElts = VT.getVectorNumElements();
2509 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2512 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2514 int BitI1 = Mask[i+1];
2515 if (!isUndefOrEqual(BitI, j))
2518 if (!isUndefOrEqual(BitI1, NumElts))
2521 if (!isUndefOrEqual(BitI1, j + NumElts))
2528 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2529 SmallVector<int, 8> M;
2531 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2534 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2535 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2536 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
2537 bool V2IsSplat = false) {
2538 int NumElts = VT.getVectorNumElements();
2539 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2542 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2544 int BitI1 = Mask[i+1];
2545 if (!isUndefOrEqual(BitI, j + NumElts/2))
2548 if (isUndefOrEqual(BitI1, NumElts))
2551 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2558 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2559 SmallVector<int, 8> M;
2561 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2564 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2565 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2567 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2568 int NumElems = VT.getVectorNumElements();
2569 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2572 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2574 int BitI1 = Mask[i+1];
2575 if (!isUndefOrEqual(BitI, j))
2577 if (!isUndefOrEqual(BitI1, j))
2583 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2584 SmallVector<int, 8> M;
2586 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2589 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2590 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2592 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
2593 int NumElems = VT.getVectorNumElements();
2594 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2597 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2599 int BitI1 = Mask[i+1];
2600 if (!isUndefOrEqual(BitI, j))
2602 if (!isUndefOrEqual(BitI1, j))
2608 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2609 SmallVector<int, 8> M;
2611 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2614 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2615 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2616 /// MOVSD, and MOVD, i.e. setting the lowest element.
2617 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2618 if (VT.getVectorElementType().getSizeInBits() < 32)
2621 int NumElts = VT.getVectorNumElements();
2623 if (!isUndefOrEqual(Mask[0], NumElts))
2626 for (int i = 1; i < NumElts; ++i)
2627 if (!isUndefOrEqual(Mask[i], i))
2633 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2634 SmallVector<int, 8> M;
2636 return ::isMOVLMask(M, N->getValueType(0));
2639 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2640 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2641 /// element of vector 2 and the other elements to come from vector 1 in order.
2642 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
2643 bool V2IsSplat = false, bool V2IsUndef = false) {
2644 int NumOps = VT.getVectorNumElements();
2645 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2648 if (!isUndefOrEqual(Mask[0], 0))
2651 for (int i = 1; i < NumOps; ++i)
2652 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2653 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2654 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2660 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2661 bool V2IsUndef = false) {
2662 SmallVector<int, 8> M;
2664 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2667 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2668 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2669 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2670 if (N->getValueType(0).getVectorNumElements() != 4)
2673 // Expect 1, 1, 3, 3
2674 for (unsigned i = 0; i < 2; ++i) {
2675 int Elt = N->getMaskElt(i);
2676 if (Elt >= 0 && Elt != 1)
2681 for (unsigned i = 2; i < 4; ++i) {
2682 int Elt = N->getMaskElt(i);
2683 if (Elt >= 0 && Elt != 3)
2688 // Don't use movshdup if it can be done with a shufps.
2689 // FIXME: verify that matching u, u, 3, 3 is what we want.
2693 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2694 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2695 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2696 if (N->getValueType(0).getVectorNumElements() != 4)
2699 // Expect 0, 0, 2, 2
2700 for (unsigned i = 0; i < 2; ++i)
2701 if (N->getMaskElt(i) > 0)
2705 for (unsigned i = 2; i < 4; ++i) {
2706 int Elt = N->getMaskElt(i);
2707 if (Elt >= 0 && Elt != 2)
2712 // Don't use movsldup if it can be done with a shufps.
2716 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2717 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2718 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2719 int e = N->getValueType(0).getVectorNumElements() / 2;
2721 for (int i = 0; i < e; ++i)
2722 if (!isUndefOrEqual(N->getMaskElt(i), i))
2724 for (int i = 0; i < e; ++i)
2725 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2730 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2731 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2733 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2734 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2735 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2737 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2739 for (int i = 0; i < NumOperands; ++i) {
2740 int Val = SVOp->getMaskElt(NumOperands-i-1);
2741 if (Val < 0) Val = 0;
2742 if (Val >= NumOperands) Val -= NumOperands;
2744 if (i != NumOperands - 1)
2750 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2751 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2753 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2754 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2756 // 8 nodes, but we only care about the last 4.
2757 for (unsigned i = 7; i >= 4; --i) {
2758 int Val = SVOp->getMaskElt(i);
2767 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2768 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2770 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2771 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2773 // 8 nodes, but we only care about the first 4.
2774 for (int i = 3; i >= 0; --i) {
2775 int Val = SVOp->getMaskElt(i);
2784 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2786 bool X86::isZeroNode(SDValue Elt) {
2787 return ((isa<ConstantSDNode>(Elt) &&
2788 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2789 (isa<ConstantFPSDNode>(Elt) &&
2790 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2793 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2794 /// their permute mask.
2795 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2796 SelectionDAG &DAG) {
2797 EVT VT = SVOp->getValueType(0);
2798 unsigned NumElems = VT.getVectorNumElements();
2799 SmallVector<int, 8> MaskVec;
2801 for (unsigned i = 0; i != NumElems; ++i) {
2802 int idx = SVOp->getMaskElt(i);
2804 MaskVec.push_back(idx);
2805 else if (idx < (int)NumElems)
2806 MaskVec.push_back(idx + NumElems);
2808 MaskVec.push_back(idx - NumElems);
2810 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2811 SVOp->getOperand(0), &MaskVec[0]);
2814 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2815 /// the two vector operands have swapped position.
2816 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
2817 unsigned NumElems = VT.getVectorNumElements();
2818 for (unsigned i = 0; i != NumElems; ++i) {
2822 else if (idx < (int)NumElems)
2823 Mask[i] = idx + NumElems;
2825 Mask[i] = idx - NumElems;
2829 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2830 /// match movhlps. The lower half elements should come from upper half of
2831 /// V1 (and in order), and the upper half elements should come from the upper
2832 /// half of V2 (and in order).
2833 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2834 if (Op->getValueType(0).getVectorNumElements() != 4)
2836 for (unsigned i = 0, e = 2; i != e; ++i)
2837 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
2839 for (unsigned i = 2; i != 4; ++i)
2840 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
2845 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2846 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2848 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2849 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2851 N = N->getOperand(0).getNode();
2852 if (!ISD::isNON_EXTLoad(N))
2855 *LD = cast<LoadSDNode>(N);
2859 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2860 /// match movlp{s|d}. The lower half elements should come from lower half of
2861 /// V1 (and in order), and the upper half elements should come from the upper
2862 /// half of V2 (and in order). And since V1 will become the source of the
2863 /// MOVLP, it must be either a vector load or a scalar load to vector.
2864 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2865 ShuffleVectorSDNode *Op) {
2866 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2868 // Is V2 is a vector load, don't do this transformation. We will try to use
2869 // load folding shufps op.
2870 if (ISD::isNON_EXTLoad(V2))
2873 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
2875 if (NumElems != 2 && NumElems != 4)
2877 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2878 if (!isUndefOrEqual(Op->getMaskElt(i), i))
2880 for (unsigned i = NumElems/2; i != NumElems; ++i)
2881 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
2886 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2888 static bool isSplatVector(SDNode *N) {
2889 if (N->getOpcode() != ISD::BUILD_VECTOR)
2892 SDValue SplatValue = N->getOperand(0);
2893 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2894 if (N->getOperand(i) != SplatValue)
2899 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2900 /// to an zero vector.
2901 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
2902 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
2903 SDValue V1 = N->getOperand(0);
2904 SDValue V2 = N->getOperand(1);
2905 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2906 for (unsigned i = 0; i != NumElems; ++i) {
2907 int Idx = N->getMaskElt(i);
2908 if (Idx >= (int)NumElems) {
2909 unsigned Opc = V2.getOpcode();
2910 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2912 if (Opc != ISD::BUILD_VECTOR ||
2913 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
2915 } else if (Idx >= 0) {
2916 unsigned Opc = V1.getOpcode();
2917 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2919 if (Opc != ISD::BUILD_VECTOR ||
2920 !X86::isZeroNode(V1.getOperand(Idx)))
2927 /// getZeroVector - Returns a vector of specified type with all zero elements.
2929 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
2931 assert(VT.isVector() && "Expected a vector type");
2933 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2934 // type. This ensures they get CSE'd.
2936 if (VT.getSizeInBits() == 64) { // MMX
2937 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2938 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2939 } else if (HasSSE2) { // SSE2
2940 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2941 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2943 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2944 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
2946 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2949 /// getOnesVector - Returns a vector of specified type with all bits set.
2951 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2952 assert(VT.isVector() && "Expected a vector type");
2954 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2955 // type. This ensures they get CSE'd.
2956 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2958 if (VT.getSizeInBits() == 64) // MMX
2959 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2961 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2962 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2966 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2967 /// that point to V2 points to its first element.
2968 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
2969 EVT VT = SVOp->getValueType(0);
2970 unsigned NumElems = VT.getVectorNumElements();
2972 bool Changed = false;
2973 SmallVector<int, 8> MaskVec;
2974 SVOp->getMask(MaskVec);
2976 for (unsigned i = 0; i != NumElems; ++i) {
2977 if (MaskVec[i] > (int)NumElems) {
2978 MaskVec[i] = NumElems;
2983 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
2984 SVOp->getOperand(1), &MaskVec[0]);
2985 return SDValue(SVOp, 0);
2988 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2989 /// operation of specified width.
2990 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
2992 unsigned NumElems = VT.getVectorNumElements();
2993 SmallVector<int, 8> Mask;
2994 Mask.push_back(NumElems);
2995 for (unsigned i = 1; i != NumElems; ++i)
2997 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3000 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3001 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3003 unsigned NumElems = VT.getVectorNumElements();
3004 SmallVector<int, 8> Mask;
3005 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3007 Mask.push_back(i + NumElems);
3009 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3012 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3013 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3015 unsigned NumElems = VT.getVectorNumElements();
3016 unsigned Half = NumElems/2;
3017 SmallVector<int, 8> Mask;
3018 for (unsigned i = 0; i != Half; ++i) {
3019 Mask.push_back(i + Half);
3020 Mask.push_back(i + NumElems + Half);
3022 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3025 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3026 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
3028 if (SV->getValueType(0).getVectorNumElements() <= 4)
3029 return SDValue(SV, 0);
3031 EVT PVT = MVT::v4f32;
3032 EVT VT = SV->getValueType(0);
3033 DebugLoc dl = SV->getDebugLoc();
3034 SDValue V1 = SV->getOperand(0);
3035 int NumElems = VT.getVectorNumElements();
3036 int EltNo = SV->getSplatIndex();
3038 // unpack elements to the correct location
3039 while (NumElems > 4) {
3040 if (EltNo < NumElems/2) {
3041 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3043 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3044 EltNo -= NumElems/2;
3049 // Perform the splat.
3050 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3051 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3052 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3053 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3056 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3057 /// vector of zero or undef vector. This produces a shuffle where the low
3058 /// element of V2 is swizzled into the zero/undef vector, landing at element
3059 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3060 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3061 bool isZero, bool HasSSE2,
3062 SelectionDAG &DAG) {
3063 EVT VT = V2.getValueType();
3065 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3066 unsigned NumElems = VT.getVectorNumElements();
3067 SmallVector<int, 16> MaskVec;
3068 for (unsigned i = 0; i != NumElems; ++i)
3069 // If this is the insertion idx, put the low elt of V2 here.
3070 MaskVec.push_back(i == Idx ? NumElems : i);
3071 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3074 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3075 /// a shuffle that is zero.
3077 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3078 bool Low, SelectionDAG &DAG) {
3079 unsigned NumZeros = 0;
3080 for (int i = 0; i < NumElems; ++i) {
3081 unsigned Index = Low ? i : NumElems-i-1;
3082 int Idx = SVOp->getMaskElt(Index);
3087 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3088 if (Elt.getNode() && X86::isZeroNode(Elt))
3096 /// isVectorShift - Returns true if the shuffle can be implemented as a
3097 /// logical left or right shift of a vector.
3098 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3099 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3100 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3101 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3104 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3107 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3111 bool SeenV1 = false;
3112 bool SeenV2 = false;
3113 for (int i = NumZeros; i < NumElems; ++i) {
3114 int Val = isLeft ? (i - NumZeros) : i;
3115 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3127 if (SeenV1 && SeenV2)
3130 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3136 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3138 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3139 unsigned NumNonZero, unsigned NumZero,
3140 SelectionDAG &DAG, TargetLowering &TLI) {
3144 DebugLoc dl = Op.getDebugLoc();
3147 for (unsigned i = 0; i < 16; ++i) {
3148 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3149 if (ThisIsNonZero && First) {
3151 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3153 V = DAG.getUNDEF(MVT::v8i16);
3158 SDValue ThisElt(0, 0), LastElt(0, 0);
3159 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3160 if (LastIsNonZero) {
3161 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3162 MVT::i16, Op.getOperand(i-1));
3164 if (ThisIsNonZero) {
3165 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3166 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3167 ThisElt, DAG.getConstant(8, MVT::i8));
3169 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3173 if (ThisElt.getNode())
3174 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3175 DAG.getIntPtrConstant(i/2));
3179 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3182 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3184 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3185 unsigned NumNonZero, unsigned NumZero,
3186 SelectionDAG &DAG, TargetLowering &TLI) {
3190 DebugLoc dl = Op.getDebugLoc();
3193 for (unsigned i = 0; i < 8; ++i) {
3194 bool isNonZero = (NonZeros & (1 << i)) != 0;
3198 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3200 V = DAG.getUNDEF(MVT::v8i16);
3203 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3204 MVT::v8i16, V, Op.getOperand(i),
3205 DAG.getIntPtrConstant(i));
3212 /// getVShift - Return a vector logical shift node.
3214 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3215 unsigned NumBits, SelectionDAG &DAG,
3216 const TargetLowering &TLI, DebugLoc dl) {
3217 bool isMMX = VT.getSizeInBits() == 64;
3218 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3219 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3220 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3221 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3222 DAG.getNode(Opc, dl, ShVT, SrcOp,
3223 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3227 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3228 DebugLoc dl = Op.getDebugLoc();
3229 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3230 if (ISD::isBuildVectorAllZeros(Op.getNode())
3231 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3232 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3233 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3234 // eliminated on x86-32 hosts.
3235 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3238 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3239 return getOnesVector(Op.getValueType(), DAG, dl);
3240 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3243 EVT VT = Op.getValueType();
3244 EVT ExtVT = VT.getVectorElementType();
3245 unsigned EVTBits = ExtVT.getSizeInBits();
3247 unsigned NumElems = Op.getNumOperands();
3248 unsigned NumZero = 0;
3249 unsigned NumNonZero = 0;
3250 unsigned NonZeros = 0;
3251 bool IsAllConstants = true;
3252 SmallSet<SDValue, 8> Values;
3253 for (unsigned i = 0; i < NumElems; ++i) {
3254 SDValue Elt = Op.getOperand(i);
3255 if (Elt.getOpcode() == ISD::UNDEF)
3258 if (Elt.getOpcode() != ISD::Constant &&
3259 Elt.getOpcode() != ISD::ConstantFP)
3260 IsAllConstants = false;
3261 if (X86::isZeroNode(Elt))
3264 NonZeros |= (1 << i);
3269 if (NumNonZero == 0) {
3270 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3271 return DAG.getUNDEF(VT);
3274 // Special case for single non-zero, non-undef, element.
3275 if (NumNonZero == 1) {
3276 unsigned Idx = CountTrailingZeros_32(NonZeros);
3277 SDValue Item = Op.getOperand(Idx);
3279 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3280 // the value are obviously zero, truncate the value to i32 and do the
3281 // insertion that way. Only do this if the value is non-constant or if the
3282 // value is a constant being inserted into element 0. It is cheaper to do
3283 // a constant pool load than it is to do a movd + shuffle.
3284 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
3285 (!IsAllConstants || Idx == 0)) {
3286 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3287 // Handle MMX and SSE both.
3288 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3289 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3291 // Truncate the value (which may itself be a constant) to i32, and
3292 // convert it to a vector with movd (S2V+shuffle to zero extend).
3293 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3294 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3295 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3296 Subtarget->hasSSE2(), DAG);
3298 // Now we have our 32-bit value zero extended in the low element of
3299 // a vector. If Idx != 0, swizzle it into place.
3301 SmallVector<int, 4> Mask;
3302 Mask.push_back(Idx);
3303 for (unsigned i = 1; i != VecElts; ++i)
3305 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3306 DAG.getUNDEF(Item.getValueType()),
3309 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3313 // If we have a constant or non-constant insertion into the low element of
3314 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3315 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3316 // depending on what the source datatype is.
3319 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3320 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
3321 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
3322 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3323 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3324 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3326 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
3327 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3328 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3329 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3330 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3331 Subtarget->hasSSE2(), DAG);
3332 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3336 // Is it a vector logical left shift?
3337 if (NumElems == 2 && Idx == 1 &&
3338 X86::isZeroNode(Op.getOperand(0)) &&
3339 !X86::isZeroNode(Op.getOperand(1))) {
3340 unsigned NumBits = VT.getSizeInBits();
3341 return getVShift(true, VT,
3342 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3343 VT, Op.getOperand(1)),
3344 NumBits/2, DAG, *this, dl);
3347 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3350 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3351 // is a non-constant being inserted into an element other than the low one,
3352 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3353 // movd/movss) to move this into the low element, then shuffle it into
3355 if (EVTBits == 32) {
3356 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3358 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3359 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3360 Subtarget->hasSSE2(), DAG);
3361 SmallVector<int, 8> MaskVec;
3362 for (unsigned i = 0; i < NumElems; i++)
3363 MaskVec.push_back(i == Idx ? 0 : 1);
3364 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3368 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3369 if (Values.size() == 1)
3372 // A vector full of immediates; various special cases are already
3373 // handled, so this is best done with a single constant-pool load.
3377 // Let legalizer expand 2-wide build_vectors.
3378 if (EVTBits == 64) {
3379 if (NumNonZero == 1) {
3380 // One half is zero or undef.
3381 unsigned Idx = CountTrailingZeros_32(NonZeros);
3382 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3383 Op.getOperand(Idx));
3384 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3385 Subtarget->hasSSE2(), DAG);
3390 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3391 if (EVTBits == 8 && NumElems == 16) {
3392 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3394 if (V.getNode()) return V;
3397 if (EVTBits == 16 && NumElems == 8) {
3398 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3400 if (V.getNode()) return V;
3403 // If element VT is == 32 bits, turn it into a number of shuffles.
3404 SmallVector<SDValue, 8> V;
3406 if (NumElems == 4 && NumZero > 0) {
3407 for (unsigned i = 0; i < 4; ++i) {
3408 bool isZero = !(NonZeros & (1 << i));
3410 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3412 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3415 for (unsigned i = 0; i < 2; ++i) {
3416 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3419 V[i] = V[i*2]; // Must be a zero vector.
3422 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3425 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3428 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3433 SmallVector<int, 8> MaskVec;
3434 bool Reverse = (NonZeros & 0x3) == 2;
3435 for (unsigned i = 0; i < 2; ++i)
3436 MaskVec.push_back(Reverse ? 1-i : i);
3437 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3438 for (unsigned i = 0; i < 2; ++i)
3439 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3440 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3443 if (Values.size() > 2) {
3444 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3445 // values to be inserted is equal to the number of elements, in which case
3446 // use the unpack code below in the hopes of matching the consecutive elts
3447 // load merge pattern for shuffles.
3448 // FIXME: We could probably just check that here directly.
3449 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3450 getSubtarget()->hasSSE41()) {
3451 V[0] = DAG.getUNDEF(VT);
3452 for (unsigned i = 0; i < NumElems; ++i)
3453 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3454 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3455 Op.getOperand(i), DAG.getIntPtrConstant(i));
3458 // Expand into a number of unpckl*.
3460 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3461 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3462 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3463 for (unsigned i = 0; i < NumElems; ++i)
3464 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3466 while (NumElems != 0) {
3467 for (unsigned i = 0; i < NumElems; ++i)
3468 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3477 // v8i16 shuffles - Prefer shuffles in the following order:
3478 // 1. [all] pshuflw, pshufhw, optional move
3479 // 2. [ssse3] 1 x pshufb
3480 // 3. [ssse3] 2 x pshufb + 1 x por
3481 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3483 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3484 SelectionDAG &DAG, X86TargetLowering &TLI) {
3485 SDValue V1 = SVOp->getOperand(0);
3486 SDValue V2 = SVOp->getOperand(1);
3487 DebugLoc dl = SVOp->getDebugLoc();
3488 SmallVector<int, 8> MaskVals;
3490 // Determine if more than 1 of the words in each of the low and high quadwords
3491 // of the result come from the same quadword of one of the two inputs. Undef
3492 // mask values count as coming from any quadword, for better codegen.
3493 SmallVector<unsigned, 4> LoQuad(4);
3494 SmallVector<unsigned, 4> HiQuad(4);
3495 BitVector InputQuads(4);
3496 for (unsigned i = 0; i < 8; ++i) {
3497 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3498 int EltIdx = SVOp->getMaskElt(i);
3499 MaskVals.push_back(EltIdx);
3508 InputQuads.set(EltIdx / 4);
3511 int BestLoQuad = -1;
3512 unsigned MaxQuad = 1;
3513 for (unsigned i = 0; i < 4; ++i) {
3514 if (LoQuad[i] > MaxQuad) {
3516 MaxQuad = LoQuad[i];
3520 int BestHiQuad = -1;
3522 for (unsigned i = 0; i < 4; ++i) {
3523 if (HiQuad[i] > MaxQuad) {
3525 MaxQuad = HiQuad[i];
3529 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3530 // of the two input vectors, shuffle them into one input vector so only a
3531 // single pshufb instruction is necessary. If There are more than 2 input
3532 // quads, disable the next transformation since it does not help SSSE3.
3533 bool V1Used = InputQuads[0] || InputQuads[1];
3534 bool V2Used = InputQuads[2] || InputQuads[3];
3535 if (TLI.getSubtarget()->hasSSSE3()) {
3536 if (InputQuads.count() == 2 && V1Used && V2Used) {
3537 BestLoQuad = InputQuads.find_first();
3538 BestHiQuad = InputQuads.find_next(BestLoQuad);
3540 if (InputQuads.count() > 2) {
3546 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3547 // the shuffle mask. If a quad is scored as -1, that means that it contains
3548 // words from all 4 input quadwords.
3550 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3551 SmallVector<int, 8> MaskV;
3552 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3553 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3554 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3555 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3556 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3557 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3559 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3560 // source words for the shuffle, to aid later transformations.
3561 bool AllWordsInNewV = true;
3562 bool InOrder[2] = { true, true };
3563 for (unsigned i = 0; i != 8; ++i) {
3564 int idx = MaskVals[i];
3566 InOrder[i/4] = false;
3567 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3569 AllWordsInNewV = false;
3573 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3574 if (AllWordsInNewV) {
3575 for (int i = 0; i != 8; ++i) {
3576 int idx = MaskVals[i];
3579 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3580 if ((idx != i) && idx < 4)
3582 if ((idx != i) && idx > 3)
3591 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3592 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3593 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3594 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3595 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3599 // If we have SSSE3, and all words of the result are from 1 input vector,
3600 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3601 // is present, fall back to case 4.
3602 if (TLI.getSubtarget()->hasSSSE3()) {
3603 SmallVector<SDValue,16> pshufbMask;
3605 // If we have elements from both input vectors, set the high bit of the
3606 // shuffle mask element to zero out elements that come from V2 in the V1
3607 // mask, and elements that come from V1 in the V2 mask, so that the two
3608 // results can be OR'd together.
3609 bool TwoInputs = V1Used && V2Used;
3610 for (unsigned i = 0; i != 8; ++i) {
3611 int EltIdx = MaskVals[i] * 2;
3612 if (TwoInputs && (EltIdx >= 16)) {
3613 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3614 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3617 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3618 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3620 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3621 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3622 DAG.getNode(ISD::BUILD_VECTOR, dl,
3623 MVT::v16i8, &pshufbMask[0], 16));
3625 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3627 // Calculate the shuffle mask for the second input, shuffle it, and
3628 // OR it with the first shuffled input.
3630 for (unsigned i = 0; i != 8; ++i) {
3631 int EltIdx = MaskVals[i] * 2;
3633 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3634 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3637 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3638 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3640 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3641 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3642 DAG.getNode(ISD::BUILD_VECTOR, dl,
3643 MVT::v16i8, &pshufbMask[0], 16));
3644 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3645 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3648 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3649 // and update MaskVals with new element order.
3650 BitVector InOrder(8);
3651 if (BestLoQuad >= 0) {
3652 SmallVector<int, 8> MaskV;
3653 for (int i = 0; i != 4; ++i) {
3654 int idx = MaskVals[i];
3656 MaskV.push_back(-1);
3658 } else if ((idx / 4) == BestLoQuad) {
3659 MaskV.push_back(idx & 3);
3662 MaskV.push_back(-1);
3665 for (unsigned i = 4; i != 8; ++i)
3667 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3671 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3672 // and update MaskVals with the new element order.
3673 if (BestHiQuad >= 0) {
3674 SmallVector<int, 8> MaskV;
3675 for (unsigned i = 0; i != 4; ++i)
3677 for (unsigned i = 4; i != 8; ++i) {
3678 int idx = MaskVals[i];
3680 MaskV.push_back(-1);
3682 } else if ((idx / 4) == BestHiQuad) {
3683 MaskV.push_back((idx & 3) + 4);
3686 MaskV.push_back(-1);
3689 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3693 // In case BestHi & BestLo were both -1, which means each quadword has a word
3694 // from each of the four input quadwords, calculate the InOrder bitvector now
3695 // before falling through to the insert/extract cleanup.
3696 if (BestLoQuad == -1 && BestHiQuad == -1) {
3698 for (int i = 0; i != 8; ++i)
3699 if (MaskVals[i] < 0 || MaskVals[i] == i)
3703 // The other elements are put in the right place using pextrw and pinsrw.
3704 for (unsigned i = 0; i != 8; ++i) {
3707 int EltIdx = MaskVals[i];
3710 SDValue ExtOp = (EltIdx < 8)
3711 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3712 DAG.getIntPtrConstant(EltIdx))
3713 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3714 DAG.getIntPtrConstant(EltIdx - 8));
3715 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3716 DAG.getIntPtrConstant(i));
3721 // v16i8 shuffles - Prefer shuffles in the following order:
3722 // 1. [ssse3] 1 x pshufb
3723 // 2. [ssse3] 2 x pshufb + 1 x por
3724 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3726 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3727 SelectionDAG &DAG, X86TargetLowering &TLI) {
3728 SDValue V1 = SVOp->getOperand(0);
3729 SDValue V2 = SVOp->getOperand(1);
3730 DebugLoc dl = SVOp->getDebugLoc();
3731 SmallVector<int, 16> MaskVals;
3732 SVOp->getMask(MaskVals);
3734 // If we have SSSE3, case 1 is generated when all result bytes come from
3735 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3736 // present, fall back to case 3.
3737 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3740 for (unsigned i = 0; i < 16; ++i) {
3741 int EltIdx = MaskVals[i];
3750 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3751 if (TLI.getSubtarget()->hasSSSE3()) {
3752 SmallVector<SDValue,16> pshufbMask;
3754 // If all result elements are from one input vector, then only translate
3755 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3757 // Otherwise, we have elements from both input vectors, and must zero out
3758 // elements that come from V2 in the first mask, and V1 in the second mask
3759 // so that we can OR them together.
3760 bool TwoInputs = !(V1Only || V2Only);
3761 for (unsigned i = 0; i != 16; ++i) {
3762 int EltIdx = MaskVals[i];
3763 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3764 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3767 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3769 // If all the elements are from V2, assign it to V1 and return after
3770 // building the first pshufb.
3773 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3774 DAG.getNode(ISD::BUILD_VECTOR, dl,
3775 MVT::v16i8, &pshufbMask[0], 16));
3779 // Calculate the shuffle mask for the second input, shuffle it, and
3780 // OR it with the first shuffled input.
3782 for (unsigned i = 0; i != 16; ++i) {
3783 int EltIdx = MaskVals[i];
3785 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3788 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3790 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3791 DAG.getNode(ISD::BUILD_VECTOR, dl,
3792 MVT::v16i8, &pshufbMask[0], 16));
3793 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3796 // No SSSE3 - Calculate in place words and then fix all out of place words
3797 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
3798 // the 16 different words that comprise the two doublequadword input vectors.
3799 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3800 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
3801 SDValue NewV = V2Only ? V2 : V1;
3802 for (int i = 0; i != 8; ++i) {
3803 int Elt0 = MaskVals[i*2];
3804 int Elt1 = MaskVals[i*2+1];
3806 // This word of the result is all undef, skip it.
3807 if (Elt0 < 0 && Elt1 < 0)
3810 // This word of the result is already in the correct place, skip it.
3811 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
3813 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
3816 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
3817 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
3820 // If Elt0 and Elt1 are defined, are consecutive, and can be load
3821 // using a single extract together, load it and store it.
3822 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
3823 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3824 DAG.getIntPtrConstant(Elt1 / 2));
3825 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3826 DAG.getIntPtrConstant(i));
3830 // If Elt1 is defined, extract it from the appropriate source. If the
3831 // source byte is not also odd, shift the extracted word left 8 bits
3832 // otherwise clear the bottom 8 bits if we need to do an or.
3834 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3835 DAG.getIntPtrConstant(Elt1 / 2));
3836 if ((Elt1 & 1) == 0)
3837 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
3838 DAG.getConstant(8, TLI.getShiftAmountTy()));
3840 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
3841 DAG.getConstant(0xFF00, MVT::i16));
3843 // If Elt0 is defined, extract it from the appropriate source. If the
3844 // source byte is not also even, shift the extracted word right 8 bits. If
3845 // Elt1 was also defined, OR the extracted values together before
3846 // inserting them in the result.
3848 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
3849 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
3850 if ((Elt0 & 1) != 0)
3851 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
3852 DAG.getConstant(8, TLI.getShiftAmountTy()));
3854 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
3855 DAG.getConstant(0x00FF, MVT::i16));
3856 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
3859 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3860 DAG.getIntPtrConstant(i));
3862 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
3865 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3866 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3867 /// done when every pair / quad of shuffle mask elements point to elements in
3868 /// the right sequence. e.g.
3869 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3871 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
3873 TargetLowering &TLI, DebugLoc dl) {
3874 EVT VT = SVOp->getValueType(0);
3875 SDValue V1 = SVOp->getOperand(0);
3876 SDValue V2 = SVOp->getOperand(1);
3877 unsigned NumElems = VT.getVectorNumElements();
3878 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3879 EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3880 EVT MaskEltVT = MaskVT.getVectorElementType();
3882 switch (VT.getSimpleVT().SimpleTy) {
3883 default: assert(false && "Unexpected!");
3884 case MVT::v4f32: NewVT = MVT::v2f64; break;
3885 case MVT::v4i32: NewVT = MVT::v2i64; break;
3886 case MVT::v8i16: NewVT = MVT::v4i32; break;
3887 case MVT::v16i8: NewVT = MVT::v4i32; break;
3890 if (NewWidth == 2) {
3896 int Scale = NumElems / NewWidth;
3897 SmallVector<int, 8> MaskVec;
3898 for (unsigned i = 0; i < NumElems; i += Scale) {
3900 for (int j = 0; j < Scale; ++j) {
3901 int EltIdx = SVOp->getMaskElt(i+j);
3905 StartIdx = EltIdx - (EltIdx % Scale);
3906 if (EltIdx != StartIdx + j)
3910 MaskVec.push_back(-1);
3912 MaskVec.push_back(StartIdx / Scale);
3915 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
3916 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
3917 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
3920 /// getVZextMovL - Return a zero-extending vector move low node.
3922 static SDValue getVZextMovL(EVT VT, EVT OpVT,
3923 SDValue SrcOp, SelectionDAG &DAG,
3924 const X86Subtarget *Subtarget, DebugLoc dl) {
3925 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3926 LoadSDNode *LD = NULL;
3927 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3928 LD = dyn_cast<LoadSDNode>(SrcOp);
3930 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3932 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3933 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
3934 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3935 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3936 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
3938 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3939 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3940 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3941 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3949 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3950 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3951 DAG.getNode(ISD::BIT_CONVERT, dl,
3955 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3958 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3959 SDValue V1 = SVOp->getOperand(0);
3960 SDValue V2 = SVOp->getOperand(1);
3961 DebugLoc dl = SVOp->getDebugLoc();
3962 EVT VT = SVOp->getValueType(0);
3964 SmallVector<std::pair<int, int>, 8> Locs;
3966 SmallVector<int, 8> Mask1(4U, -1);
3967 SmallVector<int, 8> PermMask;
3968 SVOp->getMask(PermMask);
3972 for (unsigned i = 0; i != 4; ++i) {
3973 int Idx = PermMask[i];
3975 Locs[i] = std::make_pair(-1, -1);
3977 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
3979 Locs[i] = std::make_pair(0, NumLo);
3983 Locs[i] = std::make_pair(1, NumHi);
3985 Mask1[2+NumHi] = Idx;
3991 if (NumLo <= 2 && NumHi <= 2) {
3992 // If no more than two elements come from either vector. This can be
3993 // implemented with two shuffles. First shuffle gather the elements.
3994 // The second shuffle, which takes the first shuffle as both of its
3995 // vector operands, put the elements into the right order.
3996 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
3998 SmallVector<int, 8> Mask2(4U, -1);
4000 for (unsigned i = 0; i != 4; ++i) {
4001 if (Locs[i].first == -1)
4004 unsigned Idx = (i < 2) ? 0 : 4;
4005 Idx += Locs[i].first * 2 + Locs[i].second;
4010 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4011 } else if (NumLo == 3 || NumHi == 3) {
4012 // Otherwise, we must have three elements from one vector, call it X, and
4013 // one element from the other, call it Y. First, use a shufps to build an
4014 // intermediate vector with the one element from Y and the element from X
4015 // that will be in the same half in the final destination (the indexes don't
4016 // matter). Then, use a shufps to build the final vector, taking the half
4017 // containing the element from Y from the intermediate, and the other half
4020 // Normalize it so the 3 elements come from V1.
4021 CommuteVectorShuffleMask(PermMask, VT);
4025 // Find the element from V2.
4027 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
4028 int Val = PermMask[HiIndex];
4035 Mask1[0] = PermMask[HiIndex];
4037 Mask1[2] = PermMask[HiIndex^1];
4039 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4042 Mask1[0] = PermMask[0];
4043 Mask1[1] = PermMask[1];
4044 Mask1[2] = HiIndex & 1 ? 6 : 4;
4045 Mask1[3] = HiIndex & 1 ? 4 : 6;
4046 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4048 Mask1[0] = HiIndex & 1 ? 2 : 0;
4049 Mask1[1] = HiIndex & 1 ? 0 : 2;
4050 Mask1[2] = PermMask[2];
4051 Mask1[3] = PermMask[3];
4056 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4060 // Break it into (shuffle shuffle_hi, shuffle_lo).
4062 SmallVector<int,8> LoMask(4U, -1);
4063 SmallVector<int,8> HiMask(4U, -1);
4065 SmallVector<int,8> *MaskPtr = &LoMask;
4066 unsigned MaskIdx = 0;
4069 for (unsigned i = 0; i != 4; ++i) {
4076 int Idx = PermMask[i];
4078 Locs[i] = std::make_pair(-1, -1);
4079 } else if (Idx < 4) {
4080 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4081 (*MaskPtr)[LoIdx] = Idx;
4084 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4085 (*MaskPtr)[HiIdx] = Idx;
4090 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4091 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4092 SmallVector<int, 8> MaskOps;
4093 for (unsigned i = 0; i != 4; ++i) {
4094 if (Locs[i].first == -1) {
4095 MaskOps.push_back(-1);
4097 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4098 MaskOps.push_back(Idx);
4101 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4105 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4106 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4107 SDValue V1 = Op.getOperand(0);
4108 SDValue V2 = Op.getOperand(1);
4109 EVT VT = Op.getValueType();
4110 DebugLoc dl = Op.getDebugLoc();
4111 unsigned NumElems = VT.getVectorNumElements();
4112 bool isMMX = VT.getSizeInBits() == 64;
4113 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4114 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4115 bool V1IsSplat = false;
4116 bool V2IsSplat = false;
4118 if (isZeroShuffle(SVOp))
4119 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4121 // Promote splats to v4f32.
4122 if (SVOp->isSplat()) {
4123 if (isMMX || NumElems < 4)
4125 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4128 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4130 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4131 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4132 if (NewOp.getNode())
4133 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4134 LowerVECTOR_SHUFFLE(NewOp, DAG));
4135 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4136 // FIXME: Figure out a cleaner way to do this.
4137 // Try to make use of movq to zero out the top part.
4138 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4139 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4140 if (NewOp.getNode()) {
4141 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4142 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4143 DAG, Subtarget, dl);
4145 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4146 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4147 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4148 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4149 DAG, Subtarget, dl);
4153 if (X86::isPSHUFDMask(SVOp))
4156 // Check if this can be converted into a logical shift.
4157 bool isLeft = false;
4160 bool isShift = getSubtarget()->hasSSE2() &&
4161 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4162 if (isShift && ShVal.hasOneUse()) {
4163 // If the shifted value has multiple uses, it may be cheaper to use
4164 // v_set0 + movlhps or movhlps, etc.
4165 EVT EVT = VT.getVectorElementType();
4166 ShAmt *= EVT.getSizeInBits();
4167 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4170 if (X86::isMOVLMask(SVOp)) {
4173 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4174 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4179 // FIXME: fold these into legal mask.
4180 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4181 X86::isMOVSLDUPMask(SVOp) ||
4182 X86::isMOVHLPSMask(SVOp) ||
4183 X86::isMOVHPMask(SVOp) ||
4184 X86::isMOVLPMask(SVOp)))
4187 if (ShouldXformToMOVHLPS(SVOp) ||
4188 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4189 return CommuteVectorShuffle(SVOp, DAG);
4192 // No better options. Use a vshl / vsrl.
4193 EVT EVT = VT.getVectorElementType();
4194 ShAmt *= EVT.getSizeInBits();
4195 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4198 bool Commuted = false;
4199 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4200 // 1,1,1,1 -> v8i16 though.
4201 V1IsSplat = isSplatVector(V1.getNode());
4202 V2IsSplat = isSplatVector(V2.getNode());
4204 // Canonicalize the splat or undef, if present, to be on the RHS.
4205 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4206 Op = CommuteVectorShuffle(SVOp, DAG);
4207 SVOp = cast<ShuffleVectorSDNode>(Op);
4208 V1 = SVOp->getOperand(0);
4209 V2 = SVOp->getOperand(1);
4210 std::swap(V1IsSplat, V2IsSplat);
4211 std::swap(V1IsUndef, V2IsUndef);
4215 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4216 // Shuffling low element of v1 into undef, just return v1.
4219 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4220 // the instruction selector will not match, so get a canonical MOVL with
4221 // swapped operands to undo the commute.
4222 return getMOVL(DAG, dl, VT, V2, V1);
4225 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4226 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4227 X86::isUNPCKLMask(SVOp) ||
4228 X86::isUNPCKHMask(SVOp))
4232 // Normalize mask so all entries that point to V2 points to its first
4233 // element then try to match unpck{h|l} again. If match, return a
4234 // new vector_shuffle with the corrected mask.
4235 SDValue NewMask = NormalizeMask(SVOp, DAG);
4236 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4237 if (NSVOp != SVOp) {
4238 if (X86::isUNPCKLMask(NSVOp, true)) {
4240 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4247 // Commute is back and try unpck* again.
4248 // FIXME: this seems wrong.
4249 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4250 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4251 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4252 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4253 X86::isUNPCKLMask(NewSVOp) ||
4254 X86::isUNPCKHMask(NewSVOp))
4258 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4260 // Normalize the node to match x86 shuffle ops if needed
4261 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4262 return CommuteVectorShuffle(SVOp, DAG);
4264 // Check for legal shuffle and return?
4265 SmallVector<int, 16> PermMask;
4266 SVOp->getMask(PermMask);
4267 if (isShuffleMaskLegal(PermMask, VT))
4270 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4271 if (VT == MVT::v8i16) {
4272 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4273 if (NewOp.getNode())
4277 if (VT == MVT::v16i8) {
4278 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4279 if (NewOp.getNode())
4283 // Handle all 4 wide cases with a number of shuffles except for MMX.
4284 if (NumElems == 4 && !isMMX)
4285 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4291 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4292 SelectionDAG &DAG) {
4293 EVT VT = Op.getValueType();
4294 DebugLoc dl = Op.getDebugLoc();
4295 if (VT.getSizeInBits() == 8) {
4296 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4297 Op.getOperand(0), Op.getOperand(1));
4298 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4299 DAG.getValueType(VT));
4300 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4301 } else if (VT.getSizeInBits() == 16) {
4302 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4303 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4305 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4306 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4307 DAG.getNode(ISD::BIT_CONVERT, dl,
4311 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4312 Op.getOperand(0), Op.getOperand(1));
4313 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4314 DAG.getValueType(VT));
4315 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4316 } else if (VT == MVT::f32) {
4317 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4318 // the result back to FR32 register. It's only worth matching if the
4319 // result has a single use which is a store or a bitcast to i32. And in
4320 // the case of a store, it's not worth it if the index is a constant 0,
4321 // because a MOVSSmr can be used instead, which is smaller and faster.
4322 if (!Op.hasOneUse())
4324 SDNode *User = *Op.getNode()->use_begin();
4325 if ((User->getOpcode() != ISD::STORE ||
4326 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4327 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4328 (User->getOpcode() != ISD::BIT_CONVERT ||
4329 User->getValueType(0) != MVT::i32))
4331 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4332 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4335 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4336 } else if (VT == MVT::i32) {
4337 // ExtractPS works with constant index.
4338 if (isa<ConstantSDNode>(Op.getOperand(1)))
4346 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4347 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4350 if (Subtarget->hasSSE41()) {
4351 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4356 EVT VT = Op.getValueType();
4357 DebugLoc dl = Op.getDebugLoc();
4358 // TODO: handle v16i8.
4359 if (VT.getSizeInBits() == 16) {
4360 SDValue Vec = Op.getOperand(0);
4361 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4363 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4364 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4365 DAG.getNode(ISD::BIT_CONVERT, dl,
4368 // Transform it so it match pextrw which produces a 32-bit result.
4369 EVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1);
4370 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
4371 Op.getOperand(0), Op.getOperand(1));
4372 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
4373 DAG.getValueType(VT));
4374 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4375 } else if (VT.getSizeInBits() == 32) {
4376 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4380 // SHUFPS the element to the lowest double word, then movss.
4381 int Mask[4] = { Idx, -1, -1, -1 };
4382 EVT VVT = Op.getOperand(0).getValueType();
4383 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4384 DAG.getUNDEF(VVT), Mask);
4385 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4386 DAG.getIntPtrConstant(0));
4387 } else if (VT.getSizeInBits() == 64) {
4388 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4389 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4390 // to match extract_elt for f64.
4391 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4395 // UNPCKHPD the element to the lowest double word, then movsd.
4396 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4397 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4398 int Mask[2] = { 1, -1 };
4399 EVT VVT = Op.getOperand(0).getValueType();
4400 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4401 DAG.getUNDEF(VVT), Mask);
4402 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4403 DAG.getIntPtrConstant(0));
4410 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4411 EVT VT = Op.getValueType();
4412 EVT EVT = VT.getVectorElementType();
4413 DebugLoc dl = Op.getDebugLoc();
4415 SDValue N0 = Op.getOperand(0);
4416 SDValue N1 = Op.getOperand(1);
4417 SDValue N2 = Op.getOperand(2);
4419 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4420 isa<ConstantSDNode>(N2)) {
4421 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4423 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4425 if (N1.getValueType() != MVT::i32)
4426 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4427 if (N2.getValueType() != MVT::i32)
4428 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4429 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4430 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4431 // Bits [7:6] of the constant are the source select. This will always be
4432 // zero here. The DAG Combiner may combine an extract_elt index into these
4433 // bits. For example (insert (extract, 3), 2) could be matched by putting
4434 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4435 // Bits [5:4] of the constant are the destination select. This is the
4436 // value of the incoming immediate.
4437 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4438 // combine either bitwise AND or insert of float 0.0 to set these bits.
4439 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4440 // Create this as a scalar to vector..
4441 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4442 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4443 } else if (EVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4444 // PINSR* works with constant index.
4451 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4452 EVT VT = Op.getValueType();
4453 EVT EVT = VT.getVectorElementType();
4455 if (Subtarget->hasSSE41())
4456 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4461 DebugLoc dl = Op.getDebugLoc();
4462 SDValue N0 = Op.getOperand(0);
4463 SDValue N1 = Op.getOperand(1);
4464 SDValue N2 = Op.getOperand(2);
4466 if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4467 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4468 // as its second argument.
4469 if (N1.getValueType() != MVT::i32)
4470 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4471 if (N2.getValueType() != MVT::i32)
4472 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4473 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4479 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4480 DebugLoc dl = Op.getDebugLoc();
4481 if (Op.getValueType() == MVT::v2f32)
4482 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4483 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4484 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4485 Op.getOperand(0))));
4487 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4488 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4490 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4491 EVT VT = MVT::v2i32;
4492 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4499 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4500 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4503 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4504 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4505 // one of the above mentioned nodes. It has to be wrapped because otherwise
4506 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4507 // be used to form addressing mode. These wrapped nodes will be selected
4510 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4511 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4513 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4515 unsigned char OpFlag = 0;
4516 unsigned WrapperKind = X86ISD::Wrapper;
4517 CodeModel::Model M = getTargetMachine().getCodeModel();
4519 if (Subtarget->isPICStyleRIPRel() &&
4520 (M == CodeModel::Small || M == CodeModel::Kernel))
4521 WrapperKind = X86ISD::WrapperRIP;
4522 else if (Subtarget->isPICStyleGOT())
4523 OpFlag = X86II::MO_GOTOFF;
4524 else if (Subtarget->isPICStyleStubPIC())
4525 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4527 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4529 CP->getOffset(), OpFlag);
4530 DebugLoc DL = CP->getDebugLoc();
4531 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4532 // With PIC, the address is actually $g + Offset.
4534 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4535 DAG.getNode(X86ISD::GlobalBaseReg,
4536 DebugLoc::getUnknownLoc(), getPointerTy()),
4543 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4544 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4546 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4548 unsigned char OpFlag = 0;
4549 unsigned WrapperKind = X86ISD::Wrapper;
4550 CodeModel::Model M = getTargetMachine().getCodeModel();
4552 if (Subtarget->isPICStyleRIPRel() &&
4553 (M == CodeModel::Small || M == CodeModel::Kernel))
4554 WrapperKind = X86ISD::WrapperRIP;
4555 else if (Subtarget->isPICStyleGOT())
4556 OpFlag = X86II::MO_GOTOFF;
4557 else if (Subtarget->isPICStyleStubPIC())
4558 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4560 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4562 DebugLoc DL = JT->getDebugLoc();
4563 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4565 // With PIC, the address is actually $g + Offset.
4567 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4568 DAG.getNode(X86ISD::GlobalBaseReg,
4569 DebugLoc::getUnknownLoc(), getPointerTy()),
4577 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4578 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4580 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4582 unsigned char OpFlag = 0;
4583 unsigned WrapperKind = X86ISD::Wrapper;
4584 CodeModel::Model M = getTargetMachine().getCodeModel();
4586 if (Subtarget->isPICStyleRIPRel() &&
4587 (M == CodeModel::Small || M == CodeModel::Kernel))
4588 WrapperKind = X86ISD::WrapperRIP;
4589 else if (Subtarget->isPICStyleGOT())
4590 OpFlag = X86II::MO_GOTOFF;
4591 else if (Subtarget->isPICStyleStubPIC())
4592 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4594 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4596 DebugLoc DL = Op.getDebugLoc();
4597 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4600 // With PIC, the address is actually $g + Offset.
4601 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4602 !Subtarget->is64Bit()) {
4603 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4604 DAG.getNode(X86ISD::GlobalBaseReg,
4605 DebugLoc::getUnknownLoc(),
4614 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4616 SelectionDAG &DAG) const {
4617 // Create the TargetGlobalAddress node, folding in the constant
4618 // offset if it is legal.
4619 unsigned char OpFlags =
4620 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
4621 CodeModel::Model M = getTargetMachine().getCodeModel();
4623 if (OpFlags == X86II::MO_NO_FLAG &&
4624 X86::isOffsetSuitableForCodeModel(Offset, M)) {
4625 // A direct static reference to a global.
4626 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4629 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
4632 if (Subtarget->isPICStyleRIPRel() &&
4633 (M == CodeModel::Small || M == CodeModel::Kernel))
4634 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4636 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4638 // With PIC, the address is actually $g + Offset.
4639 if (isGlobalRelativeToPICBase(OpFlags)) {
4640 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4641 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4645 // For globals that require a load from a stub to get the address, emit the
4647 if (isGlobalStubReference(OpFlags))
4648 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4649 PseudoSourceValue::getGOT(), 0);
4651 // If there was a non-zero offset that we didn't fold, create an explicit
4654 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4655 DAG.getConstant(Offset, getPointerTy()));
4661 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4662 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4663 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4664 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4668 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
4669 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
4670 unsigned char OperandFlags) {
4671 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4672 DebugLoc dl = GA->getDebugLoc();
4673 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4674 GA->getValueType(0),
4678 SDValue Ops[] = { Chain, TGA, *InFlag };
4679 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4681 SDValue Ops[] = { Chain, TGA };
4682 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4684 SDValue Flag = Chain.getValue(1);
4685 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
4688 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4690 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4693 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4694 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4695 DAG.getNode(X86ISD::GlobalBaseReg,
4696 DebugLoc::getUnknownLoc(),
4698 InFlag = Chain.getValue(1);
4700 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
4703 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4705 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4707 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4708 X86::RAX, X86II::MO_TLSGD);
4711 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4712 // "local exec" model.
4713 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4714 const EVT PtrVT, TLSModel::Model model,
4716 DebugLoc dl = GA->getDebugLoc();
4717 // Get the Thread Pointer
4718 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4719 DebugLoc::getUnknownLoc(), PtrVT,
4720 DAG.getRegister(is64Bit? X86::FS : X86::GS,
4723 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4726 unsigned char OperandFlags = 0;
4727 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
4729 unsigned WrapperKind = X86ISD::Wrapper;
4730 if (model == TLSModel::LocalExec) {
4731 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
4732 } else if (is64Bit) {
4733 assert(model == TLSModel::InitialExec);
4734 OperandFlags = X86II::MO_GOTTPOFF;
4735 WrapperKind = X86ISD::WrapperRIP;
4737 assert(model == TLSModel::InitialExec);
4738 OperandFlags = X86II::MO_INDNTPOFF;
4741 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4743 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4744 GA->getOffset(), OperandFlags);
4745 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
4747 if (model == TLSModel::InitialExec)
4748 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4749 PseudoSourceValue::getGOT(), 0);
4751 // The address of the thread local variable is the add of the thread
4752 // pointer with the offset of the variable.
4753 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
4757 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4758 // TODO: implement the "local dynamic" model
4759 // TODO: implement the "initial exec"model for pic executables
4760 assert(Subtarget->isTargetELF() &&
4761 "TLS not implemented for non-ELF targets");
4762 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4763 const GlobalValue *GV = GA->getGlobal();
4765 // If GV is an alias then use the aliasee for determining
4766 // thread-localness.
4767 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
4768 GV = GA->resolveAliasedGlobal(false);
4770 TLSModel::Model model = getTLSModel(GV,
4771 getTargetMachine().getRelocationModel());
4774 case TLSModel::GeneralDynamic:
4775 case TLSModel::LocalDynamic: // not implemented
4776 if (Subtarget->is64Bit())
4777 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4778 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4780 case TLSModel::InitialExec:
4781 case TLSModel::LocalExec:
4782 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
4783 Subtarget->is64Bit());
4786 llvm_unreachable("Unreachable");
4791 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4792 /// take a 2 x i32 value to shift plus a shift amount.
4793 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4794 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4795 EVT VT = Op.getValueType();
4796 unsigned VTBits = VT.getSizeInBits();
4797 DebugLoc dl = Op.getDebugLoc();
4798 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4799 SDValue ShOpLo = Op.getOperand(0);
4800 SDValue ShOpHi = Op.getOperand(1);
4801 SDValue ShAmt = Op.getOperand(2);
4802 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
4803 DAG.getConstant(VTBits - 1, MVT::i8))
4804 : DAG.getConstant(0, VT);
4807 if (Op.getOpcode() == ISD::SHL_PARTS) {
4808 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
4809 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4811 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
4812 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
4815 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
4816 DAG.getConstant(VTBits, MVT::i8));
4817 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
4818 AndNode, DAG.getConstant(0, MVT::i8));
4821 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4822 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4823 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4825 if (Op.getOpcode() == ISD::SHL_PARTS) {
4826 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4827 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4829 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4830 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4833 SDValue Ops[2] = { Lo, Hi };
4834 return DAG.getMergeValues(Ops, 2, dl);
4837 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4838 EVT SrcVT = Op.getOperand(0).getValueType();
4840 if (SrcVT.isVector()) {
4841 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
4847 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4848 "Unknown SINT_TO_FP to lower!");
4850 // These are really Legal; return the operand so the caller accepts it as
4852 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4854 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
4855 Subtarget->is64Bit()) {
4859 DebugLoc dl = Op.getDebugLoc();
4860 unsigned Size = SrcVT.getSizeInBits()/8;
4861 MachineFunction &MF = DAG.getMachineFunction();
4862 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4863 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4864 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
4866 PseudoSourceValue::getFixedStack(SSFI), 0);
4867 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
4870 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
4872 SelectionDAG &DAG) {
4874 DebugLoc dl = Op.getDebugLoc();
4876 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4878 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4880 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4881 SmallVector<SDValue, 8> Ops;
4882 Ops.push_back(Chain);
4883 Ops.push_back(StackSlot);
4884 Ops.push_back(DAG.getValueType(SrcVT));
4885 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
4886 Tys, &Ops[0], Ops.size());
4889 Chain = Result.getValue(1);
4890 SDValue InFlag = Result.getValue(2);
4892 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4893 // shouldn't be necessary except that RFP cannot be live across
4894 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4895 MachineFunction &MF = DAG.getMachineFunction();
4896 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4897 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4898 Tys = DAG.getVTList(MVT::Other);
4899 SmallVector<SDValue, 8> Ops;
4900 Ops.push_back(Chain);
4901 Ops.push_back(Result);
4902 Ops.push_back(StackSlot);
4903 Ops.push_back(DAG.getValueType(Op.getValueType()));
4904 Ops.push_back(InFlag);
4905 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
4906 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
4907 PseudoSourceValue::getFixedStack(SSFI), 0);
4913 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
4914 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
4915 // This algorithm is not obvious. Here it is in C code, more or less:
4917 double uint64_to_double( uint32_t hi, uint32_t lo ) {
4918 static const __m128i exp = { 0x4330000045300000ULL, 0 };
4919 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
4921 // Copy ints to xmm registers.
4922 __m128i xh = _mm_cvtsi32_si128( hi );
4923 __m128i xl = _mm_cvtsi32_si128( lo );
4925 // Combine into low half of a single xmm register.
4926 __m128i x = _mm_unpacklo_epi32( xh, xl );
4930 // Merge in appropriate exponents to give the integer bits the right
4932 x = _mm_unpacklo_epi32( x, exp );
4934 // Subtract away the biases to deal with the IEEE-754 double precision
4936 d = _mm_sub_pd( (__m128d) x, bias );
4938 // All conversions up to here are exact. The correctly rounded result is
4939 // calculated using the current rounding mode using the following
4941 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
4942 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
4943 // store doesn't really need to be here (except
4944 // maybe to zero the other double)
4949 DebugLoc dl = Op.getDebugLoc();
4950 LLVMContext *Context = DAG.getContext();
4952 // Build some magic constants.
4953 std::vector<Constant*> CV0;
4954 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
4955 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
4956 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
4957 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
4958 Constant *C0 = ConstantVector::get(CV0);
4959 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
4961 std::vector<Constant*> CV1;
4963 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
4965 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
4966 Constant *C1 = ConstantVector::get(CV1);
4967 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
4969 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4970 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4972 DAG.getIntPtrConstant(1)));
4973 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4974 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4976 DAG.getIntPtrConstant(0)));
4977 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
4978 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
4979 PseudoSourceValue::getConstantPool(), 0,
4981 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
4982 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
4983 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
4984 PseudoSourceValue::getConstantPool(), 0,
4986 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
4988 // Add the halves; easiest way is to swap them into another reg first.
4989 int ShufMask[2] = { 1, -1 };
4990 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
4991 DAG.getUNDEF(MVT::v2f64), ShufMask);
4992 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
4993 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
4994 DAG.getIntPtrConstant(0));
4997 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
4998 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
4999 DebugLoc dl = Op.getDebugLoc();
5000 // FP constant to bias correct the final result.
5001 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
5004 // Load the 32-bit value into an XMM register.
5005 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
5006 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5008 DAG.getIntPtrConstant(0)));
5010 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5011 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
5012 DAG.getIntPtrConstant(0));
5014 // Or the load with the bias.
5015 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
5016 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5017 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5019 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5020 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5021 MVT::v2f64, Bias)));
5022 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5023 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
5024 DAG.getIntPtrConstant(0));
5026 // Subtract the bias.
5027 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
5029 // Handle final rounding.
5030 EVT DestVT = Op.getValueType();
5032 if (DestVT.bitsLT(MVT::f64)) {
5033 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
5034 DAG.getIntPtrConstant(0));
5035 } else if (DestVT.bitsGT(MVT::f64)) {
5036 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
5039 // Handle final rounding.
5043 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5044 SDValue N0 = Op.getOperand(0);
5045 DebugLoc dl = Op.getDebugLoc();
5047 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5048 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5049 // the optimization here.
5050 if (DAG.SignBitIsZero(N0))
5051 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5053 EVT SrcVT = N0.getValueType();
5054 if (SrcVT == MVT::i64) {
5055 // We only handle SSE2 f64 target here; caller can expand the rest.
5056 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5059 return LowerUINT_TO_FP_i64(Op, DAG);
5060 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5061 return LowerUINT_TO_FP_i32(Op, DAG);
5064 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5066 // Make a 64-bit buffer, and use it to build an FILD.
5067 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5068 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5069 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5070 getPointerTy(), StackSlot, WordOff);
5071 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5072 StackSlot, NULL, 0);
5073 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5074 OffsetSlot, NULL, 0);
5075 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5078 std::pair<SDValue,SDValue> X86TargetLowering::
5079 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5080 DebugLoc dl = Op.getDebugLoc();
5082 EVT DstTy = Op.getValueType();
5085 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5089 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5090 DstTy.getSimpleVT() >= MVT::i16 &&
5091 "Unknown FP_TO_SINT to lower!");
5093 // These are really Legal.
5094 if (DstTy == MVT::i32 &&
5095 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5096 return std::make_pair(SDValue(), SDValue());
5097 if (Subtarget->is64Bit() &&
5098 DstTy == MVT::i64 &&
5099 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5100 return std::make_pair(SDValue(), SDValue());
5102 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5104 MachineFunction &MF = DAG.getMachineFunction();
5105 unsigned MemSize = DstTy.getSizeInBits()/8;
5106 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5107 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5110 switch (DstTy.getSimpleVT().SimpleTy) {
5111 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5112 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5113 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5114 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5117 SDValue Chain = DAG.getEntryNode();
5118 SDValue Value = Op.getOperand(0);
5119 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5120 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5121 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5122 PseudoSourceValue::getFixedStack(SSFI), 0);
5123 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5125 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5127 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5128 Chain = Value.getValue(1);
5129 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5130 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5133 // Build the FP_TO_INT*_IN_MEM
5134 SDValue Ops[] = { Chain, Value, StackSlot };
5135 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5137 return std::make_pair(FIST, StackSlot);
5140 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5141 if (Op.getValueType().isVector()) {
5142 if (Op.getValueType() == MVT::v2i32 &&
5143 Op.getOperand(0).getValueType() == MVT::v2f64) {
5149 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5150 SDValue FIST = Vals.first, StackSlot = Vals.second;
5151 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5152 if (FIST.getNode() == 0) return Op;
5155 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5156 FIST, StackSlot, NULL, 0);
5159 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5160 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5161 SDValue FIST = Vals.first, StackSlot = Vals.second;
5162 assert(FIST.getNode() && "Unexpected failure");
5165 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5166 FIST, StackSlot, NULL, 0);
5169 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5170 LLVMContext *Context = DAG.getContext();
5171 DebugLoc dl = Op.getDebugLoc();
5172 EVT VT = Op.getValueType();
5175 EltVT = VT.getVectorElementType();
5176 std::vector<Constant*> CV;
5177 if (EltVT == MVT::f64) {
5178 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5182 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5188 Constant *C = ConstantVector::get(CV);
5189 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5190 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5191 PseudoSourceValue::getConstantPool(), 0,
5193 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5196 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5197 LLVMContext *Context = DAG.getContext();
5198 DebugLoc dl = Op.getDebugLoc();
5199 EVT VT = Op.getValueType();
5201 if (VT.isVector()) {
5202 EltVT = VT.getVectorElementType();
5203 VT.getVectorNumElements();
5205 std::vector<Constant*> CV;
5206 if (EltVT == MVT::f64) {
5207 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5211 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5217 Constant *C = ConstantVector::get(CV);
5218 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5219 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5220 PseudoSourceValue::getConstantPool(), 0,
5222 if (VT.isVector()) {
5223 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5224 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5225 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5227 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5229 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5233 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5234 LLVMContext *Context = DAG.getContext();
5235 SDValue Op0 = Op.getOperand(0);
5236 SDValue Op1 = Op.getOperand(1);
5237 DebugLoc dl = Op.getDebugLoc();
5238 EVT VT = Op.getValueType();
5239 EVT SrcVT = Op1.getValueType();
5241 // If second operand is smaller, extend it first.
5242 if (SrcVT.bitsLT(VT)) {
5243 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5246 // And if it is bigger, shrink it first.
5247 if (SrcVT.bitsGT(VT)) {
5248 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5252 // At this point the operands and the result should have the same
5253 // type, and that won't be f80 since that is not custom lowered.
5255 // First get the sign bit of second operand.
5256 std::vector<Constant*> CV;
5257 if (SrcVT == MVT::f64) {
5258 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5259 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5261 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5262 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5263 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5264 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5266 Constant *C = ConstantVector::get(CV);
5267 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5268 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5269 PseudoSourceValue::getConstantPool(), 0,
5271 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5273 // Shift sign bit right or left if the two operands have different types.
5274 if (SrcVT.bitsGT(VT)) {
5275 // Op0 is MVT::f32, Op1 is MVT::f64.
5276 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5277 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5278 DAG.getConstant(32, MVT::i32));
5279 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5280 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5281 DAG.getIntPtrConstant(0));
5284 // Clear first operand sign bit.
5286 if (VT == MVT::f64) {
5287 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5288 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5290 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5291 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5292 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5293 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5295 C = ConstantVector::get(CV);
5296 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5297 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5298 PseudoSourceValue::getConstantPool(), 0,
5300 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5302 // Or the value with the sign bit.
5303 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5306 /// Emit nodes that will be selected as "test Op0,Op0", or something
5308 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5309 SelectionDAG &DAG) {
5310 DebugLoc dl = Op.getDebugLoc();
5312 // CF and OF aren't always set the way we want. Determine which
5313 // of these we need.
5314 bool NeedCF = false;
5315 bool NeedOF = false;
5317 case X86::COND_A: case X86::COND_AE:
5318 case X86::COND_B: case X86::COND_BE:
5321 case X86::COND_G: case X86::COND_GE:
5322 case X86::COND_L: case X86::COND_LE:
5323 case X86::COND_O: case X86::COND_NO:
5329 // See if we can use the EFLAGS value from the operand instead of
5330 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5331 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5332 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5333 unsigned Opcode = 0;
5334 unsigned NumOperands = 0;
5335 switch (Op.getNode()->getOpcode()) {
5337 // Due to an isel shortcoming, be conservative if this add is likely to
5338 // be selected as part of a load-modify-store instruction. When the root
5339 // node in a match is a store, isel doesn't know how to remap non-chain
5340 // non-flag uses of other nodes in the match, such as the ADD in this
5341 // case. This leads to the ADD being left around and reselected, with
5342 // the result being two adds in the output.
5343 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5344 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5345 if (UI->getOpcode() == ISD::STORE)
5347 if (ConstantSDNode *C =
5348 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5349 // An add of one will be selected as an INC.
5350 if (C->getAPIntValue() == 1) {
5351 Opcode = X86ISD::INC;
5355 // An add of negative one (subtract of one) will be selected as a DEC.
5356 if (C->getAPIntValue().isAllOnesValue()) {
5357 Opcode = X86ISD::DEC;
5362 // Otherwise use a regular EFLAGS-setting add.
5363 Opcode = X86ISD::ADD;
5367 // Due to the ISEL shortcoming noted above, be conservative if this sub is
5368 // likely to be selected as part of a load-modify-store instruction.
5369 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5370 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5371 if (UI->getOpcode() == ISD::STORE)
5373 // Otherwise use a regular EFLAGS-setting sub.
5374 Opcode = X86ISD::SUB;
5381 return SDValue(Op.getNode(), 1);
5387 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5388 SmallVector<SDValue, 4> Ops;
5389 for (unsigned i = 0; i != NumOperands; ++i)
5390 Ops.push_back(Op.getOperand(i));
5391 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5392 DAG.ReplaceAllUsesWith(Op, New);
5393 return SDValue(New.getNode(), 1);
5397 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5398 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5399 DAG.getConstant(0, Op.getValueType()));
5402 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5404 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5405 SelectionDAG &DAG) {
5406 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5407 if (C->getAPIntValue() == 0)
5408 return EmitTest(Op0, X86CC, DAG);
5410 DebugLoc dl = Op0.getDebugLoc();
5411 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5414 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5415 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5416 SDValue Op0 = Op.getOperand(0);
5417 SDValue Op1 = Op.getOperand(1);
5418 DebugLoc dl = Op.getDebugLoc();
5419 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5421 // Lower (X & (1 << N)) == 0 to BT(X, N).
5422 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5423 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5424 if (Op0.getOpcode() == ISD::AND &&
5426 Op1.getOpcode() == ISD::Constant &&
5427 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5428 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5430 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5431 if (ConstantSDNode *Op010C =
5432 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5433 if (Op010C->getZExtValue() == 1) {
5434 LHS = Op0.getOperand(0);
5435 RHS = Op0.getOperand(1).getOperand(1);
5437 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5438 if (ConstantSDNode *Op000C =
5439 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5440 if (Op000C->getZExtValue() == 1) {
5441 LHS = Op0.getOperand(1);
5442 RHS = Op0.getOperand(0).getOperand(1);
5444 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5445 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5446 SDValue AndLHS = Op0.getOperand(0);
5447 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5448 LHS = AndLHS.getOperand(0);
5449 RHS = AndLHS.getOperand(1);
5453 if (LHS.getNode()) {
5454 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5455 // instruction. Since the shift amount is in-range-or-undefined, we know
5456 // that doing a bittest on the i16 value is ok. We extend to i32 because
5457 // the encoding for the i16 version is larger than the i32 version.
5458 if (LHS.getValueType() == MVT::i8)
5459 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5461 // If the operand types disagree, extend the shift amount to match. Since
5462 // BT ignores high bits (like shifts) we can use anyextend.
5463 if (LHS.getValueType() != RHS.getValueType())
5464 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5466 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5467 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5468 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5469 DAG.getConstant(Cond, MVT::i8), BT);
5473 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5474 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5476 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5477 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5478 DAG.getConstant(X86CC, MVT::i8), Cond);
5481 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5483 SDValue Op0 = Op.getOperand(0);
5484 SDValue Op1 = Op.getOperand(1);
5485 SDValue CC = Op.getOperand(2);
5486 EVT VT = Op.getValueType();
5487 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5488 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5489 DebugLoc dl = Op.getDebugLoc();
5493 EVT VT0 = Op0.getValueType();
5494 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5495 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5498 switch (SetCCOpcode) {
5501 case ISD::SETEQ: SSECC = 0; break;
5503 case ISD::SETGT: Swap = true; // Fallthrough
5505 case ISD::SETOLT: SSECC = 1; break;
5507 case ISD::SETGE: Swap = true; // Fallthrough
5509 case ISD::SETOLE: SSECC = 2; break;
5510 case ISD::SETUO: SSECC = 3; break;
5512 case ISD::SETNE: SSECC = 4; break;
5513 case ISD::SETULE: Swap = true;
5514 case ISD::SETUGE: SSECC = 5; break;
5515 case ISD::SETULT: Swap = true;
5516 case ISD::SETUGT: SSECC = 6; break;
5517 case ISD::SETO: SSECC = 7; break;
5520 std::swap(Op0, Op1);
5522 // In the two special cases we can't handle, emit two comparisons.
5524 if (SetCCOpcode == ISD::SETUEQ) {
5526 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5527 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5528 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5530 else if (SetCCOpcode == ISD::SETONE) {
5532 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5533 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5534 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5536 llvm_unreachable("Illegal FP comparison");
5538 // Handle all other FP comparisons here.
5539 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5542 // We are handling one of the integer comparisons here. Since SSE only has
5543 // GT and EQ comparisons for integer, swapping operands and multiple
5544 // operations may be required for some comparisons.
5545 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5546 bool Swap = false, Invert = false, FlipSigns = false;
5548 switch (VT.getSimpleVT().SimpleTy) {
5551 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5553 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5555 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5556 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5559 switch (SetCCOpcode) {
5561 case ISD::SETNE: Invert = true;
5562 case ISD::SETEQ: Opc = EQOpc; break;
5563 case ISD::SETLT: Swap = true;
5564 case ISD::SETGT: Opc = GTOpc; break;
5565 case ISD::SETGE: Swap = true;
5566 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5567 case ISD::SETULT: Swap = true;
5568 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5569 case ISD::SETUGE: Swap = true;
5570 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5573 std::swap(Op0, Op1);
5575 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5576 // bits of the inputs before performing those operations.
5578 EVT EltVT = VT.getVectorElementType();
5579 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5581 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5582 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5584 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5585 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5588 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5590 // If the logical-not of the result is required, perform that now.
5592 Result = DAG.getNOT(dl, Result, VT);
5597 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5598 static bool isX86LogicalCmp(SDValue Op) {
5599 unsigned Opc = Op.getNode()->getOpcode();
5600 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5602 if (Op.getResNo() == 1 &&
5603 (Opc == X86ISD::ADD ||
5604 Opc == X86ISD::SUB ||
5605 Opc == X86ISD::SMUL ||
5606 Opc == X86ISD::UMUL ||
5607 Opc == X86ISD::INC ||
5608 Opc == X86ISD::DEC))
5614 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5615 bool addTest = true;
5616 SDValue Cond = Op.getOperand(0);
5617 DebugLoc dl = Op.getDebugLoc();
5620 if (Cond.getOpcode() == ISD::SETCC)
5621 Cond = LowerSETCC(Cond, DAG);
5623 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5624 // setting operand in place of the X86ISD::SETCC.
5625 if (Cond.getOpcode() == X86ISD::SETCC) {
5626 CC = Cond.getOperand(0);
5628 SDValue Cmp = Cond.getOperand(1);
5629 unsigned Opc = Cmp.getOpcode();
5630 EVT VT = Op.getValueType();
5632 bool IllegalFPCMov = false;
5633 if (VT.isFloatingPoint() && !VT.isVector() &&
5634 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5635 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5637 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5638 Opc == X86ISD::BT) { // FIXME
5645 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5646 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5649 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
5650 SmallVector<SDValue, 4> Ops;
5651 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5652 // condition is true.
5653 Ops.push_back(Op.getOperand(2));
5654 Ops.push_back(Op.getOperand(1));
5656 Ops.push_back(Cond);
5657 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
5660 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5661 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5662 // from the AND / OR.
5663 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5664 Opc = Op.getOpcode();
5665 if (Opc != ISD::OR && Opc != ISD::AND)
5667 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5668 Op.getOperand(0).hasOneUse() &&
5669 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5670 Op.getOperand(1).hasOneUse());
5673 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5674 // 1 and that the SETCC node has a single use.
5675 static bool isXor1OfSetCC(SDValue Op) {
5676 if (Op.getOpcode() != ISD::XOR)
5678 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5679 if (N1C && N1C->getAPIntValue() == 1) {
5680 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5681 Op.getOperand(0).hasOneUse();
5686 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5687 bool addTest = true;
5688 SDValue Chain = Op.getOperand(0);
5689 SDValue Cond = Op.getOperand(1);
5690 SDValue Dest = Op.getOperand(2);
5691 DebugLoc dl = Op.getDebugLoc();
5694 if (Cond.getOpcode() == ISD::SETCC)
5695 Cond = LowerSETCC(Cond, DAG);
5697 // FIXME: LowerXALUO doesn't handle these!!
5698 else if (Cond.getOpcode() == X86ISD::ADD ||
5699 Cond.getOpcode() == X86ISD::SUB ||
5700 Cond.getOpcode() == X86ISD::SMUL ||
5701 Cond.getOpcode() == X86ISD::UMUL)
5702 Cond = LowerXALUO(Cond, DAG);
5705 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5706 // setting operand in place of the X86ISD::SETCC.
5707 if (Cond.getOpcode() == X86ISD::SETCC) {
5708 CC = Cond.getOperand(0);
5710 SDValue Cmp = Cond.getOperand(1);
5711 unsigned Opc = Cmp.getOpcode();
5712 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5713 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
5717 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5721 // These can only come from an arithmetic instruction with overflow,
5722 // e.g. SADDO, UADDO.
5723 Cond = Cond.getNode()->getOperand(1);
5730 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5731 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5732 if (CondOpc == ISD::OR) {
5733 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5734 // two branches instead of an explicit OR instruction with a
5736 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5737 isX86LogicalCmp(Cmp)) {
5738 CC = Cond.getOperand(0).getOperand(0);
5739 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5740 Chain, Dest, CC, Cmp);
5741 CC = Cond.getOperand(1).getOperand(0);
5745 } else { // ISD::AND
5746 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5747 // two branches instead of an explicit AND instruction with a
5748 // separate test. However, we only do this if this block doesn't
5749 // have a fall-through edge, because this requires an explicit
5750 // jmp when the condition is false.
5751 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5752 isX86LogicalCmp(Cmp) &&
5753 Op.getNode()->hasOneUse()) {
5754 X86::CondCode CCode =
5755 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5756 CCode = X86::GetOppositeBranchCondition(CCode);
5757 CC = DAG.getConstant(CCode, MVT::i8);
5758 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5759 // Look for an unconditional branch following this conditional branch.
5760 // We need this because we need to reverse the successors in order
5761 // to implement FCMP_OEQ.
5762 if (User.getOpcode() == ISD::BR) {
5763 SDValue FalseBB = User.getOperand(1);
5765 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5766 assert(NewBR == User);
5769 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5770 Chain, Dest, CC, Cmp);
5771 X86::CondCode CCode =
5772 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5773 CCode = X86::GetOppositeBranchCondition(CCode);
5774 CC = DAG.getConstant(CCode, MVT::i8);
5780 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
5781 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
5782 // It should be transformed during dag combiner except when the condition
5783 // is set by a arithmetics with overflow node.
5784 X86::CondCode CCode =
5785 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5786 CCode = X86::GetOppositeBranchCondition(CCode);
5787 CC = DAG.getConstant(CCode, MVT::i8);
5788 Cond = Cond.getOperand(0).getOperand(1);
5794 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5795 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5797 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5798 Chain, Dest, CC, Cond);
5802 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5803 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5804 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5805 // that the guard pages used by the OS virtual memory manager are allocated in
5806 // correct sequence.
5808 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5809 SelectionDAG &DAG) {
5810 assert(Subtarget->isTargetCygMing() &&
5811 "This should be used only on Cygwin/Mingw targets");
5812 DebugLoc dl = Op.getDebugLoc();
5815 SDValue Chain = Op.getOperand(0);
5816 SDValue Size = Op.getOperand(1);
5817 // FIXME: Ensure alignment here
5821 EVT IntPtr = getPointerTy();
5822 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5824 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5826 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
5827 Flag = Chain.getValue(1);
5829 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5830 SDValue Ops[] = { Chain,
5831 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5832 DAG.getRegister(X86::EAX, IntPtr),
5833 DAG.getRegister(X86StackPtr, SPTy),
5835 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
5836 Flag = Chain.getValue(1);
5838 Chain = DAG.getCALLSEQ_END(Chain,
5839 DAG.getIntPtrConstant(0, true),
5840 DAG.getIntPtrConstant(0, true),
5843 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
5845 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5846 return DAG.getMergeValues(Ops1, 2, dl);
5850 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
5852 SDValue Dst, SDValue Src,
5853 SDValue Size, unsigned Align,
5855 uint64_t DstSVOff) {
5856 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5858 // If not DWORD aligned or size is more than the threshold, call the library.
5859 // The libc version is likely to be faster for these cases. It can use the
5860 // address value and run time information about the CPU.
5861 if ((Align & 3) != 0 ||
5863 ConstantSize->getZExtValue() >
5864 getSubtarget()->getMaxInlineSizeThreshold()) {
5865 SDValue InFlag(0, 0);
5867 // Check to see if there is a specialized entry-point for memory zeroing.
5868 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5870 if (const char *bzeroEntry = V &&
5871 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5872 EVT IntPtr = getPointerTy();
5873 const Type *IntPtrTy = TD->getIntPtrType(*DAG.getContext());
5874 TargetLowering::ArgListTy Args;
5875 TargetLowering::ArgListEntry Entry;
5877 Entry.Ty = IntPtrTy;
5878 Args.push_back(Entry);
5880 Args.push_back(Entry);
5881 std::pair<SDValue,SDValue> CallResult =
5882 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
5883 false, false, false, false,
5884 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
5885 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
5886 return CallResult.second;
5889 // Otherwise have the target-independent code call memset.
5893 uint64_t SizeVal = ConstantSize->getZExtValue();
5894 SDValue InFlag(0, 0);
5897 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5898 unsigned BytesLeft = 0;
5899 bool TwoRepStos = false;
5902 uint64_t Val = ValC->getZExtValue() & 255;
5904 // If the value is a constant, then we can potentially use larger sets.
5905 switch (Align & 3) {
5906 case 2: // WORD aligned
5909 Val = (Val << 8) | Val;
5911 case 0: // DWORD aligned
5914 Val = (Val << 8) | Val;
5915 Val = (Val << 16) | Val;
5916 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5919 Val = (Val << 32) | Val;
5922 default: // Byte aligned
5925 Count = DAG.getIntPtrConstant(SizeVal);
5929 if (AVT.bitsGT(MVT::i8)) {
5930 unsigned UBytes = AVT.getSizeInBits() / 8;
5931 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5932 BytesLeft = SizeVal % UBytes;
5935 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
5937 InFlag = Chain.getValue(1);
5940 Count = DAG.getIntPtrConstant(SizeVal);
5941 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
5942 InFlag = Chain.getValue(1);
5945 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5948 InFlag = Chain.getValue(1);
5949 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5952 InFlag = Chain.getValue(1);
5954 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5955 SmallVector<SDValue, 8> Ops;
5956 Ops.push_back(Chain);
5957 Ops.push_back(DAG.getValueType(AVT));
5958 Ops.push_back(InFlag);
5959 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5962 InFlag = Chain.getValue(1);
5964 EVT CVT = Count.getValueType();
5965 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
5966 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5967 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
5970 InFlag = Chain.getValue(1);
5971 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5973 Ops.push_back(Chain);
5974 Ops.push_back(DAG.getValueType(MVT::i8));
5975 Ops.push_back(InFlag);
5976 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5977 } else if (BytesLeft) {
5978 // Handle the last 1 - 7 bytes.
5979 unsigned Offset = SizeVal - BytesLeft;
5980 EVT AddrVT = Dst.getValueType();
5981 EVT SizeVT = Size.getValueType();
5983 Chain = DAG.getMemset(Chain, dl,
5984 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
5985 DAG.getConstant(Offset, AddrVT)),
5987 DAG.getConstant(BytesLeft, SizeVT),
5988 Align, DstSV, DstSVOff + Offset);
5991 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5996 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
5997 SDValue Chain, SDValue Dst, SDValue Src,
5998 SDValue Size, unsigned Align,
6000 const Value *DstSV, uint64_t DstSVOff,
6001 const Value *SrcSV, uint64_t SrcSVOff) {
6002 // This requires the copy size to be a constant, preferrably
6003 // within a subtarget-specific limit.
6004 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
6007 uint64_t SizeVal = ConstantSize->getZExtValue();
6008 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
6011 /// If not DWORD aligned, call the library.
6012 if ((Align & 3) != 0)
6017 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
6020 unsigned UBytes = AVT.getSizeInBits() / 8;
6021 unsigned CountVal = SizeVal / UBytes;
6022 SDValue Count = DAG.getIntPtrConstant(CountVal);
6023 unsigned BytesLeft = SizeVal % UBytes;
6025 SDValue InFlag(0, 0);
6026 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
6029 InFlag = Chain.getValue(1);
6030 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
6033 InFlag = Chain.getValue(1);
6034 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
6037 InFlag = Chain.getValue(1);
6039 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6040 SmallVector<SDValue, 8> Ops;
6041 Ops.push_back(Chain);
6042 Ops.push_back(DAG.getValueType(AVT));
6043 Ops.push_back(InFlag);
6044 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
6046 SmallVector<SDValue, 4> Results;
6047 Results.push_back(RepMovs);
6049 // Handle the last 1 - 7 bytes.
6050 unsigned Offset = SizeVal - BytesLeft;
6051 EVT DstVT = Dst.getValueType();
6052 EVT SrcVT = Src.getValueType();
6053 EVT SizeVT = Size.getValueType();
6054 Results.push_back(DAG.getMemcpy(Chain, dl,
6055 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6056 DAG.getConstant(Offset, DstVT)),
6057 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6058 DAG.getConstant(Offset, SrcVT)),
6059 DAG.getConstant(BytesLeft, SizeVT),
6060 Align, AlwaysInline,
6061 DstSV, DstSVOff + Offset,
6062 SrcSV, SrcSVOff + Offset));
6065 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6066 &Results[0], Results.size());
6069 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6070 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6071 DebugLoc dl = Op.getDebugLoc();
6073 if (!Subtarget->is64Bit()) {
6074 // vastart just stores the address of the VarArgsFrameIndex slot into the
6075 // memory location argument.
6076 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6077 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6081 // gp_offset (0 - 6 * 8)
6082 // fp_offset (48 - 48 + 8 * 16)
6083 // overflow_arg_area (point to parameters coming in memory).
6085 SmallVector<SDValue, 8> MemOps;
6086 SDValue FIN = Op.getOperand(1);
6088 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6089 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6091 MemOps.push_back(Store);
6094 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6095 FIN, DAG.getIntPtrConstant(4));
6096 Store = DAG.getStore(Op.getOperand(0), dl,
6097 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6099 MemOps.push_back(Store);
6101 // Store ptr to overflow_arg_area
6102 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6103 FIN, DAG.getIntPtrConstant(4));
6104 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6105 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6106 MemOps.push_back(Store);
6108 // Store ptr to reg_save_area.
6109 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6110 FIN, DAG.getIntPtrConstant(8));
6111 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6112 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6113 MemOps.push_back(Store);
6114 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6115 &MemOps[0], MemOps.size());
6118 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6119 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6120 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6121 SDValue Chain = Op.getOperand(0);
6122 SDValue SrcPtr = Op.getOperand(1);
6123 SDValue SrcSV = Op.getOperand(2);
6125 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6129 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6130 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6131 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6132 SDValue Chain = Op.getOperand(0);
6133 SDValue DstPtr = Op.getOperand(1);
6134 SDValue SrcPtr = Op.getOperand(2);
6135 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6136 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6137 DebugLoc dl = Op.getDebugLoc();
6139 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6140 DAG.getIntPtrConstant(24), 8, false,
6141 DstSV, 0, SrcSV, 0);
6145 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6146 DebugLoc dl = Op.getDebugLoc();
6147 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6149 default: return SDValue(); // Don't custom lower most intrinsics.
6150 // Comparison intrinsics.
6151 case Intrinsic::x86_sse_comieq_ss:
6152 case Intrinsic::x86_sse_comilt_ss:
6153 case Intrinsic::x86_sse_comile_ss:
6154 case Intrinsic::x86_sse_comigt_ss:
6155 case Intrinsic::x86_sse_comige_ss:
6156 case Intrinsic::x86_sse_comineq_ss:
6157 case Intrinsic::x86_sse_ucomieq_ss:
6158 case Intrinsic::x86_sse_ucomilt_ss:
6159 case Intrinsic::x86_sse_ucomile_ss:
6160 case Intrinsic::x86_sse_ucomigt_ss:
6161 case Intrinsic::x86_sse_ucomige_ss:
6162 case Intrinsic::x86_sse_ucomineq_ss:
6163 case Intrinsic::x86_sse2_comieq_sd:
6164 case Intrinsic::x86_sse2_comilt_sd:
6165 case Intrinsic::x86_sse2_comile_sd:
6166 case Intrinsic::x86_sse2_comigt_sd:
6167 case Intrinsic::x86_sse2_comige_sd:
6168 case Intrinsic::x86_sse2_comineq_sd:
6169 case Intrinsic::x86_sse2_ucomieq_sd:
6170 case Intrinsic::x86_sse2_ucomilt_sd:
6171 case Intrinsic::x86_sse2_ucomile_sd:
6172 case Intrinsic::x86_sse2_ucomigt_sd:
6173 case Intrinsic::x86_sse2_ucomige_sd:
6174 case Intrinsic::x86_sse2_ucomineq_sd: {
6176 ISD::CondCode CC = ISD::SETCC_INVALID;
6179 case Intrinsic::x86_sse_comieq_ss:
6180 case Intrinsic::x86_sse2_comieq_sd:
6184 case Intrinsic::x86_sse_comilt_ss:
6185 case Intrinsic::x86_sse2_comilt_sd:
6189 case Intrinsic::x86_sse_comile_ss:
6190 case Intrinsic::x86_sse2_comile_sd:
6194 case Intrinsic::x86_sse_comigt_ss:
6195 case Intrinsic::x86_sse2_comigt_sd:
6199 case Intrinsic::x86_sse_comige_ss:
6200 case Intrinsic::x86_sse2_comige_sd:
6204 case Intrinsic::x86_sse_comineq_ss:
6205 case Intrinsic::x86_sse2_comineq_sd:
6209 case Intrinsic::x86_sse_ucomieq_ss:
6210 case Intrinsic::x86_sse2_ucomieq_sd:
6211 Opc = X86ISD::UCOMI;
6214 case Intrinsic::x86_sse_ucomilt_ss:
6215 case Intrinsic::x86_sse2_ucomilt_sd:
6216 Opc = X86ISD::UCOMI;
6219 case Intrinsic::x86_sse_ucomile_ss:
6220 case Intrinsic::x86_sse2_ucomile_sd:
6221 Opc = X86ISD::UCOMI;
6224 case Intrinsic::x86_sse_ucomigt_ss:
6225 case Intrinsic::x86_sse2_ucomigt_sd:
6226 Opc = X86ISD::UCOMI;
6229 case Intrinsic::x86_sse_ucomige_ss:
6230 case Intrinsic::x86_sse2_ucomige_sd:
6231 Opc = X86ISD::UCOMI;
6234 case Intrinsic::x86_sse_ucomineq_ss:
6235 case Intrinsic::x86_sse2_ucomineq_sd:
6236 Opc = X86ISD::UCOMI;
6241 SDValue LHS = Op.getOperand(1);
6242 SDValue RHS = Op.getOperand(2);
6243 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6244 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6245 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6246 DAG.getConstant(X86CC, MVT::i8), Cond);
6247 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6249 // ptest intrinsics. The intrinsic these come from are designed to return
6250 // an integer value, not just an instruction so lower it to the ptest
6251 // pattern and a setcc for the result.
6252 case Intrinsic::x86_sse41_ptestz:
6253 case Intrinsic::x86_sse41_ptestc:
6254 case Intrinsic::x86_sse41_ptestnzc:{
6257 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6258 case Intrinsic::x86_sse41_ptestz:
6260 X86CC = X86::COND_E;
6262 case Intrinsic::x86_sse41_ptestc:
6264 X86CC = X86::COND_B;
6266 case Intrinsic::x86_sse41_ptestnzc:
6268 X86CC = X86::COND_A;
6272 SDValue LHS = Op.getOperand(1);
6273 SDValue RHS = Op.getOperand(2);
6274 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6275 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6276 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6277 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6280 // Fix vector shift instructions where the last operand is a non-immediate
6282 case Intrinsic::x86_sse2_pslli_w:
6283 case Intrinsic::x86_sse2_pslli_d:
6284 case Intrinsic::x86_sse2_pslli_q:
6285 case Intrinsic::x86_sse2_psrli_w:
6286 case Intrinsic::x86_sse2_psrli_d:
6287 case Intrinsic::x86_sse2_psrli_q:
6288 case Intrinsic::x86_sse2_psrai_w:
6289 case Intrinsic::x86_sse2_psrai_d:
6290 case Intrinsic::x86_mmx_pslli_w:
6291 case Intrinsic::x86_mmx_pslli_d:
6292 case Intrinsic::x86_mmx_pslli_q:
6293 case Intrinsic::x86_mmx_psrli_w:
6294 case Intrinsic::x86_mmx_psrli_d:
6295 case Intrinsic::x86_mmx_psrli_q:
6296 case Intrinsic::x86_mmx_psrai_w:
6297 case Intrinsic::x86_mmx_psrai_d: {
6298 SDValue ShAmt = Op.getOperand(2);
6299 if (isa<ConstantSDNode>(ShAmt))
6302 unsigned NewIntNo = 0;
6303 EVT ShAmtVT = MVT::v4i32;
6305 case Intrinsic::x86_sse2_pslli_w:
6306 NewIntNo = Intrinsic::x86_sse2_psll_w;
6308 case Intrinsic::x86_sse2_pslli_d:
6309 NewIntNo = Intrinsic::x86_sse2_psll_d;
6311 case Intrinsic::x86_sse2_pslli_q:
6312 NewIntNo = Intrinsic::x86_sse2_psll_q;
6314 case Intrinsic::x86_sse2_psrli_w:
6315 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6317 case Intrinsic::x86_sse2_psrli_d:
6318 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6320 case Intrinsic::x86_sse2_psrli_q:
6321 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6323 case Intrinsic::x86_sse2_psrai_w:
6324 NewIntNo = Intrinsic::x86_sse2_psra_w;
6326 case Intrinsic::x86_sse2_psrai_d:
6327 NewIntNo = Intrinsic::x86_sse2_psra_d;
6330 ShAmtVT = MVT::v2i32;
6332 case Intrinsic::x86_mmx_pslli_w:
6333 NewIntNo = Intrinsic::x86_mmx_psll_w;
6335 case Intrinsic::x86_mmx_pslli_d:
6336 NewIntNo = Intrinsic::x86_mmx_psll_d;
6338 case Intrinsic::x86_mmx_pslli_q:
6339 NewIntNo = Intrinsic::x86_mmx_psll_q;
6341 case Intrinsic::x86_mmx_psrli_w:
6342 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6344 case Intrinsic::x86_mmx_psrli_d:
6345 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6347 case Intrinsic::x86_mmx_psrli_q:
6348 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6350 case Intrinsic::x86_mmx_psrai_w:
6351 NewIntNo = Intrinsic::x86_mmx_psra_w;
6353 case Intrinsic::x86_mmx_psrai_d:
6354 NewIntNo = Intrinsic::x86_mmx_psra_d;
6356 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6362 // The vector shift intrinsics with scalars uses 32b shift amounts but
6363 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
6367 ShOps[1] = DAG.getConstant(0, MVT::i32);
6368 if (ShAmtVT == MVT::v4i32) {
6369 ShOps[2] = DAG.getUNDEF(MVT::i32);
6370 ShOps[3] = DAG.getUNDEF(MVT::i32);
6371 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
6373 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
6376 EVT VT = Op.getValueType();
6377 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
6378 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6379 DAG.getConstant(NewIntNo, MVT::i32),
6380 Op.getOperand(1), ShAmt);
6385 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6386 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6387 DebugLoc dl = Op.getDebugLoc();
6390 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6392 DAG.getConstant(TD->getPointerSize(),
6393 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6394 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6395 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6400 // Just load the return address.
6401 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6402 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6403 RetAddrFI, NULL, 0);
6406 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6407 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6408 MFI->setFrameAddressIsTaken(true);
6409 EVT VT = Op.getValueType();
6410 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6411 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6412 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6413 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6415 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6419 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6420 SelectionDAG &DAG) {
6421 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6424 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6426 MachineFunction &MF = DAG.getMachineFunction();
6427 SDValue Chain = Op.getOperand(0);
6428 SDValue Offset = Op.getOperand(1);
6429 SDValue Handler = Op.getOperand(2);
6430 DebugLoc dl = Op.getDebugLoc();
6432 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6434 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6436 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6437 DAG.getIntPtrConstant(-TD->getPointerSize()));
6438 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6439 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6440 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6441 MF.getRegInfo().addLiveOut(StoreAddrReg);
6443 return DAG.getNode(X86ISD::EH_RETURN, dl,
6445 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6448 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6449 SelectionDAG &DAG) {
6450 SDValue Root = Op.getOperand(0);
6451 SDValue Trmp = Op.getOperand(1); // trampoline
6452 SDValue FPtr = Op.getOperand(2); // nested function
6453 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6454 DebugLoc dl = Op.getDebugLoc();
6456 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6458 const X86InstrInfo *TII =
6459 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6461 if (Subtarget->is64Bit()) {
6462 SDValue OutChains[6];
6464 // Large code-model.
6466 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6467 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6469 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6470 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6472 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6474 // Load the pointer to the nested function into R11.
6475 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6476 SDValue Addr = Trmp;
6477 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6480 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6481 DAG.getConstant(2, MVT::i64));
6482 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6484 // Load the 'nest' parameter value into R10.
6485 // R10 is specified in X86CallingConv.td
6486 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6487 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6488 DAG.getConstant(10, MVT::i64));
6489 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6490 Addr, TrmpAddr, 10);
6492 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6493 DAG.getConstant(12, MVT::i64));
6494 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6496 // Jump to the nested function.
6497 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6498 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6499 DAG.getConstant(20, MVT::i64));
6500 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6501 Addr, TrmpAddr, 20);
6503 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6504 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6505 DAG.getConstant(22, MVT::i64));
6506 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6510 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6511 return DAG.getMergeValues(Ops, 2, dl);
6513 const Function *Func =
6514 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6515 CallingConv::ID CC = Func->getCallingConv();
6520 llvm_unreachable("Unsupported calling convention");
6521 case CallingConv::C:
6522 case CallingConv::X86_StdCall: {
6523 // Pass 'nest' parameter in ECX.
6524 // Must be kept in sync with X86CallingConv.td
6527 // Check that ECX wasn't needed by an 'inreg' parameter.
6528 const FunctionType *FTy = Func->getFunctionType();
6529 const AttrListPtr &Attrs = Func->getAttributes();
6531 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6532 unsigned InRegCount = 0;
6535 for (FunctionType::param_iterator I = FTy->param_begin(),
6536 E = FTy->param_end(); I != E; ++I, ++Idx)
6537 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6538 // FIXME: should only count parameters that are lowered to integers.
6539 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6541 if (InRegCount > 2) {
6542 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
6547 case CallingConv::X86_FastCall:
6548 case CallingConv::Fast:
6549 // Pass 'nest' parameter in EAX.
6550 // Must be kept in sync with X86CallingConv.td
6555 SDValue OutChains[4];
6558 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6559 DAG.getConstant(10, MVT::i32));
6560 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6562 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6563 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6564 OutChains[0] = DAG.getStore(Root, dl,
6565 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6568 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6569 DAG.getConstant(1, MVT::i32));
6570 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6572 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6573 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6574 DAG.getConstant(5, MVT::i32));
6575 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6576 TrmpAddr, 5, false, 1);
6578 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6579 DAG.getConstant(6, MVT::i32));
6580 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6583 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6584 return DAG.getMergeValues(Ops, 2, dl);
6588 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6590 The rounding mode is in bits 11:10 of FPSR, and has the following
6597 FLT_ROUNDS, on the other hand, expects the following:
6604 To perform the conversion, we do:
6605 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6608 MachineFunction &MF = DAG.getMachineFunction();
6609 const TargetMachine &TM = MF.getTarget();
6610 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6611 unsigned StackAlignment = TFI.getStackAlignment();
6612 EVT VT = Op.getValueType();
6613 DebugLoc dl = Op.getDebugLoc();
6615 // Save FP Control Word to stack slot
6616 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6617 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6619 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6620 DAG.getEntryNode(), StackSlot);
6622 // Load FP Control Word from stack slot
6623 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6625 // Transform as necessary
6627 DAG.getNode(ISD::SRL, dl, MVT::i16,
6628 DAG.getNode(ISD::AND, dl, MVT::i16,
6629 CWD, DAG.getConstant(0x800, MVT::i16)),
6630 DAG.getConstant(11, MVT::i8));
6632 DAG.getNode(ISD::SRL, dl, MVT::i16,
6633 DAG.getNode(ISD::AND, dl, MVT::i16,
6634 CWD, DAG.getConstant(0x400, MVT::i16)),
6635 DAG.getConstant(9, MVT::i8));
6638 DAG.getNode(ISD::AND, dl, MVT::i16,
6639 DAG.getNode(ISD::ADD, dl, MVT::i16,
6640 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6641 DAG.getConstant(1, MVT::i16)),
6642 DAG.getConstant(3, MVT::i16));
6645 return DAG.getNode((VT.getSizeInBits() < 16 ?
6646 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6649 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6650 EVT VT = Op.getValueType();
6652 unsigned NumBits = VT.getSizeInBits();
6653 DebugLoc dl = Op.getDebugLoc();
6655 Op = Op.getOperand(0);
6656 if (VT == MVT::i8) {
6657 // Zero extend to i32 since there is not an i8 bsr.
6659 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6662 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6663 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6664 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6666 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6667 SmallVector<SDValue, 4> Ops;
6669 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6670 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6671 Ops.push_back(Op.getValue(1));
6672 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6674 // Finally xor with NumBits-1.
6675 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6678 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6682 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6683 EVT VT = Op.getValueType();
6685 unsigned NumBits = VT.getSizeInBits();
6686 DebugLoc dl = Op.getDebugLoc();
6688 Op = Op.getOperand(0);
6689 if (VT == MVT::i8) {
6691 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6694 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6695 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6696 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
6698 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6699 SmallVector<SDValue, 4> Ops;
6701 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6702 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6703 Ops.push_back(Op.getValue(1));
6704 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6707 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6711 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6712 EVT VT = Op.getValueType();
6713 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6714 DebugLoc dl = Op.getDebugLoc();
6716 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6717 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6718 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6719 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6720 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6722 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6723 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6724 // return AloBlo + AloBhi + AhiBlo;
6726 SDValue A = Op.getOperand(0);
6727 SDValue B = Op.getOperand(1);
6729 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6730 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6731 A, DAG.getConstant(32, MVT::i32));
6732 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6733 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6734 B, DAG.getConstant(32, MVT::i32));
6735 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6736 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6738 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6739 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6741 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6742 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6744 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6745 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6746 AloBhi, DAG.getConstant(32, MVT::i32));
6747 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6748 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6749 AhiBlo, DAG.getConstant(32, MVT::i32));
6750 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
6751 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
6756 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6757 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6758 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6759 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6760 // has only one use.
6761 SDNode *N = Op.getNode();
6762 SDValue LHS = N->getOperand(0);
6763 SDValue RHS = N->getOperand(1);
6764 unsigned BaseOp = 0;
6766 DebugLoc dl = Op.getDebugLoc();
6768 switch (Op.getOpcode()) {
6769 default: llvm_unreachable("Unknown ovf instruction!");
6771 // A subtract of one will be selected as a INC. Note that INC doesn't
6772 // set CF, so we can't do this for UADDO.
6773 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6774 if (C->getAPIntValue() == 1) {
6775 BaseOp = X86ISD::INC;
6779 BaseOp = X86ISD::ADD;
6783 BaseOp = X86ISD::ADD;
6787 // A subtract of one will be selected as a DEC. Note that DEC doesn't
6788 // set CF, so we can't do this for USUBO.
6789 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6790 if (C->getAPIntValue() == 1) {
6791 BaseOp = X86ISD::DEC;
6795 BaseOp = X86ISD::SUB;
6799 BaseOp = X86ISD::SUB;
6803 BaseOp = X86ISD::SMUL;
6807 BaseOp = X86ISD::UMUL;
6812 // Also sets EFLAGS.
6813 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6814 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
6817 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
6818 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6820 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6824 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6825 EVT T = Op.getValueType();
6826 DebugLoc dl = Op.getDebugLoc();
6829 switch(T.getSimpleVT().SimpleTy) {
6831 assert(false && "Invalid value type!");
6832 case MVT::i8: Reg = X86::AL; size = 1; break;
6833 case MVT::i16: Reg = X86::AX; size = 2; break;
6834 case MVT::i32: Reg = X86::EAX; size = 4; break;
6836 assert(Subtarget->is64Bit() && "Node not type legal!");
6837 Reg = X86::RAX; size = 8;
6840 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
6841 Op.getOperand(2), SDValue());
6842 SDValue Ops[] = { cpIn.getValue(0),
6845 DAG.getTargetConstant(size, MVT::i8),
6847 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6848 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
6850 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
6854 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6855 SelectionDAG &DAG) {
6856 assert(Subtarget->is64Bit() && "Result not type legalized?");
6857 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6858 SDValue TheChain = Op.getOperand(0);
6859 DebugLoc dl = Op.getDebugLoc();
6860 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6861 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
6862 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
6864 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
6865 DAG.getConstant(32, MVT::i8));
6867 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
6870 return DAG.getMergeValues(Ops, 2, dl);
6873 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6874 SDNode *Node = Op.getNode();
6875 DebugLoc dl = Node->getDebugLoc();
6876 EVT T = Node->getValueType(0);
6877 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
6878 DAG.getConstant(0, T), Node->getOperand(2));
6879 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
6880 cast<AtomicSDNode>(Node)->getMemoryVT(),
6881 Node->getOperand(0),
6882 Node->getOperand(1), negOp,
6883 cast<AtomicSDNode>(Node)->getSrcValue(),
6884 cast<AtomicSDNode>(Node)->getAlignment());
6887 /// LowerOperation - Provide custom lowering hooks for some operations.
6889 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6890 switch (Op.getOpcode()) {
6891 default: llvm_unreachable("Should not custom lower this!");
6892 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
6893 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
6894 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6895 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6896 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6897 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6898 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6899 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6900 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6901 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6902 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6903 case ISD::SHL_PARTS:
6904 case ISD::SRA_PARTS:
6905 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6906 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6907 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6908 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6909 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
6910 case ISD::FABS: return LowerFABS(Op, DAG);
6911 case ISD::FNEG: return LowerFNEG(Op, DAG);
6912 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6913 case ISD::SETCC: return LowerSETCC(Op, DAG);
6914 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6915 case ISD::SELECT: return LowerSELECT(Op, DAG);
6916 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6917 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6918 case ISD::VASTART: return LowerVASTART(Op, DAG);
6919 case ISD::VAARG: return LowerVAARG(Op, DAG);
6920 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6921 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6922 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6923 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6924 case ISD::FRAME_TO_ARGS_OFFSET:
6925 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6926 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6927 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6928 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6929 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6930 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6931 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6932 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
6938 case ISD::UMULO: return LowerXALUO(Op, DAG);
6939 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
6943 void X86TargetLowering::
6944 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6945 SelectionDAG &DAG, unsigned NewOp) {
6946 EVT T = Node->getValueType(0);
6947 DebugLoc dl = Node->getDebugLoc();
6948 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6950 SDValue Chain = Node->getOperand(0);
6951 SDValue In1 = Node->getOperand(1);
6952 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6953 Node->getOperand(2), DAG.getIntPtrConstant(0));
6954 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6955 Node->getOperand(2), DAG.getIntPtrConstant(1));
6956 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6957 // have a MemOperand. Pass the info through as a normal operand.
6958 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6959 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6960 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6961 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
6962 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6963 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6964 Results.push_back(Result.getValue(2));
6967 /// ReplaceNodeResults - Replace a node with an illegal result type
6968 /// with a new node built out of custom code.
6969 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
6970 SmallVectorImpl<SDValue>&Results,
6971 SelectionDAG &DAG) {
6972 DebugLoc dl = N->getDebugLoc();
6973 switch (N->getOpcode()) {
6975 assert(false && "Do not know how to custom type legalize this operation!");
6977 case ISD::FP_TO_SINT: {
6978 std::pair<SDValue,SDValue> Vals =
6979 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
6980 SDValue FIST = Vals.first, StackSlot = Vals.second;
6981 if (FIST.getNode() != 0) {
6982 EVT VT = N->getValueType(0);
6983 // Return a load from the stack slot.
6984 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
6988 case ISD::READCYCLECOUNTER: {
6989 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6990 SDValue TheChain = N->getOperand(0);
6991 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6992 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
6994 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
6996 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
6997 SDValue Ops[] = { eax, edx };
6998 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
6999 Results.push_back(edx.getValue(1));
7002 case ISD::ATOMIC_CMP_SWAP: {
7003 EVT T = N->getValueType(0);
7004 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
7005 SDValue cpInL, cpInH;
7006 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7007 DAG.getConstant(0, MVT::i32));
7008 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
7009 DAG.getConstant(1, MVT::i32));
7010 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
7011 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
7013 SDValue swapInL, swapInH;
7014 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7015 DAG.getConstant(0, MVT::i32));
7016 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
7017 DAG.getConstant(1, MVT::i32));
7018 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
7020 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
7021 swapInL.getValue(1));
7022 SDValue Ops[] = { swapInH.getValue(0),
7024 swapInH.getValue(1) };
7025 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
7026 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
7027 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
7028 MVT::i32, Result.getValue(1));
7029 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
7030 MVT::i32, cpOutL.getValue(2));
7031 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
7032 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
7033 Results.push_back(cpOutH.getValue(1));
7036 case ISD::ATOMIC_LOAD_ADD:
7037 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
7039 case ISD::ATOMIC_LOAD_AND:
7040 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
7042 case ISD::ATOMIC_LOAD_NAND:
7043 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
7045 case ISD::ATOMIC_LOAD_OR:
7046 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
7048 case ISD::ATOMIC_LOAD_SUB:
7049 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
7051 case ISD::ATOMIC_LOAD_XOR:
7052 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
7054 case ISD::ATOMIC_SWAP:
7055 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7060 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7062 default: return NULL;
7063 case X86ISD::BSF: return "X86ISD::BSF";
7064 case X86ISD::BSR: return "X86ISD::BSR";
7065 case X86ISD::SHLD: return "X86ISD::SHLD";
7066 case X86ISD::SHRD: return "X86ISD::SHRD";
7067 case X86ISD::FAND: return "X86ISD::FAND";
7068 case X86ISD::FOR: return "X86ISD::FOR";
7069 case X86ISD::FXOR: return "X86ISD::FXOR";
7070 case X86ISD::FSRL: return "X86ISD::FSRL";
7071 case X86ISD::FILD: return "X86ISD::FILD";
7072 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7073 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7074 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7075 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7076 case X86ISD::FLD: return "X86ISD::FLD";
7077 case X86ISD::FST: return "X86ISD::FST";
7078 case X86ISD::CALL: return "X86ISD::CALL";
7079 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7080 case X86ISD::BT: return "X86ISD::BT";
7081 case X86ISD::CMP: return "X86ISD::CMP";
7082 case X86ISD::COMI: return "X86ISD::COMI";
7083 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7084 case X86ISD::SETCC: return "X86ISD::SETCC";
7085 case X86ISD::CMOV: return "X86ISD::CMOV";
7086 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7087 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7088 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7089 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7090 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7091 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7092 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7093 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7094 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7095 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7096 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7097 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7098 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7099 case X86ISD::FMAX: return "X86ISD::FMAX";
7100 case X86ISD::FMIN: return "X86ISD::FMIN";
7101 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7102 case X86ISD::FRCP: return "X86ISD::FRCP";
7103 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7104 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7105 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7106 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7107 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7108 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7109 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7110 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7111 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7112 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7113 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7114 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7115 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7116 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7117 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7118 case X86ISD::VSHL: return "X86ISD::VSHL";
7119 case X86ISD::VSRL: return "X86ISD::VSRL";
7120 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7121 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7122 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7123 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7124 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7125 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7126 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7127 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7128 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7129 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7130 case X86ISD::ADD: return "X86ISD::ADD";
7131 case X86ISD::SUB: return "X86ISD::SUB";
7132 case X86ISD::SMUL: return "X86ISD::SMUL";
7133 case X86ISD::UMUL: return "X86ISD::UMUL";
7134 case X86ISD::INC: return "X86ISD::INC";
7135 case X86ISD::DEC: return "X86ISD::DEC";
7136 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7137 case X86ISD::PTEST: return "X86ISD::PTEST";
7138 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
7142 // isLegalAddressingMode - Return true if the addressing mode represented
7143 // by AM is legal for this target, for a load/store of the specified type.
7144 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7145 const Type *Ty) const {
7146 // X86 supports extremely general addressing modes.
7147 CodeModel::Model M = getTargetMachine().getCodeModel();
7149 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7150 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7155 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7157 // If a reference to this global requires an extra load, we can't fold it.
7158 if (isGlobalStubReference(GVFlags))
7161 // If BaseGV requires a register for the PIC base, we cannot also have a
7162 // BaseReg specified.
7163 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7166 // If lower 4G is not available, then we must use rip-relative addressing.
7167 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7177 // These scales always work.
7182 // These scales are formed with basereg+scalereg. Only accept if there is
7187 default: // Other stuff never works.
7195 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7196 if (!Ty1->isInteger() || !Ty2->isInteger())
7198 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7199 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7200 if (NumBits1 <= NumBits2)
7202 return Subtarget->is64Bit() || NumBits1 < 64;
7205 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
7206 if (!VT1.isInteger() || !VT2.isInteger())
7208 unsigned NumBits1 = VT1.getSizeInBits();
7209 unsigned NumBits2 = VT2.getSizeInBits();
7210 if (NumBits1 <= NumBits2)
7212 return Subtarget->is64Bit() || NumBits1 < 64;
7215 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7216 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7217 return Ty1 == Type::getInt32Ty(Ty1->getContext()) &&
7218 Ty2 == Type::getInt64Ty(Ty1->getContext()) && Subtarget->is64Bit();
7221 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
7222 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7223 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7226 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
7227 // i16 instructions are longer (0x66 prefix) and potentially slower.
7228 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7231 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7232 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7233 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7234 /// are assumed to be legal.
7236 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7238 // Only do shuffles on 128-bit vector types for now.
7239 if (VT.getSizeInBits() == 64)
7242 // FIXME: pshufb, blends, palignr, shifts.
7243 return (VT.getVectorNumElements() == 2 ||
7244 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7245 isMOVLMask(M, VT) ||
7246 isSHUFPMask(M, VT) ||
7247 isPSHUFDMask(M, VT) ||
7248 isPSHUFHWMask(M, VT) ||
7249 isPSHUFLWMask(M, VT) ||
7250 isUNPCKLMask(M, VT) ||
7251 isUNPCKHMask(M, VT) ||
7252 isUNPCKL_v_undef_Mask(M, VT) ||
7253 isUNPCKH_v_undef_Mask(M, VT));
7257 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7259 unsigned NumElts = VT.getVectorNumElements();
7260 // FIXME: This collection of masks seems suspect.
7263 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7264 return (isMOVLMask(Mask, VT) ||
7265 isCommutedMOVLMask(Mask, VT, true) ||
7266 isSHUFPMask(Mask, VT) ||
7267 isCommutedSHUFPMask(Mask, VT));
7272 //===----------------------------------------------------------------------===//
7273 // X86 Scheduler Hooks
7274 //===----------------------------------------------------------------------===//
7276 // private utility function
7278 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7279 MachineBasicBlock *MBB,
7287 TargetRegisterClass *RC,
7288 bool invSrc) const {
7289 // For the atomic bitwise operator, we generate
7292 // ld t1 = [bitinstr.addr]
7293 // op t2 = t1, [bitinstr.val]
7295 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7297 // fallthrough -->nextMBB
7298 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7299 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7300 MachineFunction::iterator MBBIter = MBB;
7303 /// First build the CFG
7304 MachineFunction *F = MBB->getParent();
7305 MachineBasicBlock *thisMBB = MBB;
7306 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7307 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7308 F->insert(MBBIter, newMBB);
7309 F->insert(MBBIter, nextMBB);
7311 // Move all successors to thisMBB to nextMBB
7312 nextMBB->transferSuccessors(thisMBB);
7314 // Update thisMBB to fall through to newMBB
7315 thisMBB->addSuccessor(newMBB);
7317 // newMBB jumps to itself and fall through to nextMBB
7318 newMBB->addSuccessor(nextMBB);
7319 newMBB->addSuccessor(newMBB);
7321 // Insert instructions into newMBB based on incoming instruction
7322 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7323 "unexpected number of operands");
7324 DebugLoc dl = bInstr->getDebugLoc();
7325 MachineOperand& destOper = bInstr->getOperand(0);
7326 MachineOperand* argOpers[2 + X86AddrNumOperands];
7327 int numArgs = bInstr->getNumOperands() - 1;
7328 for (int i=0; i < numArgs; ++i)
7329 argOpers[i] = &bInstr->getOperand(i+1);
7331 // x86 address has 4 operands: base, index, scale, and displacement
7332 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7333 int valArgIndx = lastAddrIndx + 1;
7335 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7336 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7337 for (int i=0; i <= lastAddrIndx; ++i)
7338 (*MIB).addOperand(*argOpers[i]);
7340 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7342 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7347 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7348 assert((argOpers[valArgIndx]->isReg() ||
7349 argOpers[valArgIndx]->isImm()) &&
7351 if (argOpers[valArgIndx]->isReg())
7352 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7354 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7356 (*MIB).addOperand(*argOpers[valArgIndx]);
7358 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7361 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7362 for (int i=0; i <= lastAddrIndx; ++i)
7363 (*MIB).addOperand(*argOpers[i]);
7365 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7366 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7368 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7372 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7374 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7378 // private utility function: 64 bit atomics on 32 bit host.
7380 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7381 MachineBasicBlock *MBB,
7386 bool invSrc) const {
7387 // For the atomic bitwise operator, we generate
7388 // thisMBB (instructions are in pairs, except cmpxchg8b)
7389 // ld t1,t2 = [bitinstr.addr]
7391 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7392 // op t5, t6 <- out1, out2, [bitinstr.val]
7393 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7394 // mov ECX, EBX <- t5, t6
7395 // mov EAX, EDX <- t1, t2
7396 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7397 // mov t3, t4 <- EAX, EDX
7399 // result in out1, out2
7400 // fallthrough -->nextMBB
7402 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7403 const unsigned LoadOpc = X86::MOV32rm;
7404 const unsigned copyOpc = X86::MOV32rr;
7405 const unsigned NotOpc = X86::NOT32r;
7406 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7407 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7408 MachineFunction::iterator MBBIter = MBB;
7411 /// First build the CFG
7412 MachineFunction *F = MBB->getParent();
7413 MachineBasicBlock *thisMBB = MBB;
7414 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7415 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7416 F->insert(MBBIter, newMBB);
7417 F->insert(MBBIter, nextMBB);
7419 // Move all successors to thisMBB to nextMBB
7420 nextMBB->transferSuccessors(thisMBB);
7422 // Update thisMBB to fall through to newMBB
7423 thisMBB->addSuccessor(newMBB);
7425 // newMBB jumps to itself and fall through to nextMBB
7426 newMBB->addSuccessor(nextMBB);
7427 newMBB->addSuccessor(newMBB);
7429 DebugLoc dl = bInstr->getDebugLoc();
7430 // Insert instructions into newMBB based on incoming instruction
7431 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7432 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7433 "unexpected number of operands");
7434 MachineOperand& dest1Oper = bInstr->getOperand(0);
7435 MachineOperand& dest2Oper = bInstr->getOperand(1);
7436 MachineOperand* argOpers[2 + X86AddrNumOperands];
7437 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7438 argOpers[i] = &bInstr->getOperand(i+2);
7440 // x86 address has 4 operands: base, index, scale, and displacement
7441 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7443 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7444 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7445 for (int i=0; i <= lastAddrIndx; ++i)
7446 (*MIB).addOperand(*argOpers[i]);
7447 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7448 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7449 // add 4 to displacement.
7450 for (int i=0; i <= lastAddrIndx-2; ++i)
7451 (*MIB).addOperand(*argOpers[i]);
7452 MachineOperand newOp3 = *(argOpers[3]);
7454 newOp3.setImm(newOp3.getImm()+4);
7456 newOp3.setOffset(newOp3.getOffset()+4);
7457 (*MIB).addOperand(newOp3);
7458 (*MIB).addOperand(*argOpers[lastAddrIndx]);
7460 // t3/4 are defined later, at the bottom of the loop
7461 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7462 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7463 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7464 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7465 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7466 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7468 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7469 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7471 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7472 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7478 int valArgIndx = lastAddrIndx + 1;
7479 assert((argOpers[valArgIndx]->isReg() ||
7480 argOpers[valArgIndx]->isImm()) &&
7482 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7483 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7484 if (argOpers[valArgIndx]->isReg())
7485 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7487 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7488 if (regOpcL != X86::MOV32rr)
7490 (*MIB).addOperand(*argOpers[valArgIndx]);
7491 assert(argOpers[valArgIndx + 1]->isReg() ==
7492 argOpers[valArgIndx]->isReg());
7493 assert(argOpers[valArgIndx + 1]->isImm() ==
7494 argOpers[valArgIndx]->isImm());
7495 if (argOpers[valArgIndx + 1]->isReg())
7496 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7498 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7499 if (regOpcH != X86::MOV32rr)
7501 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7503 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7505 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7508 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7510 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7513 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7514 for (int i=0; i <= lastAddrIndx; ++i)
7515 (*MIB).addOperand(*argOpers[i]);
7517 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7518 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7520 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7521 MIB.addReg(X86::EAX);
7522 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7523 MIB.addReg(X86::EDX);
7526 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7528 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7532 // private utility function
7534 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7535 MachineBasicBlock *MBB,
7536 unsigned cmovOpc) const {
7537 // For the atomic min/max operator, we generate
7540 // ld t1 = [min/max.addr]
7541 // mov t2 = [min/max.val]
7543 // cmov[cond] t2 = t1
7545 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7547 // fallthrough -->nextMBB
7549 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7550 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7551 MachineFunction::iterator MBBIter = MBB;
7554 /// First build the CFG
7555 MachineFunction *F = MBB->getParent();
7556 MachineBasicBlock *thisMBB = MBB;
7557 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7558 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7559 F->insert(MBBIter, newMBB);
7560 F->insert(MBBIter, nextMBB);
7562 // Move all successors of thisMBB to nextMBB
7563 nextMBB->transferSuccessors(thisMBB);
7565 // Update thisMBB to fall through to newMBB
7566 thisMBB->addSuccessor(newMBB);
7568 // newMBB jumps to newMBB and fall through to nextMBB
7569 newMBB->addSuccessor(nextMBB);
7570 newMBB->addSuccessor(newMBB);
7572 DebugLoc dl = mInstr->getDebugLoc();
7573 // Insert instructions into newMBB based on incoming instruction
7574 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7575 "unexpected number of operands");
7576 MachineOperand& destOper = mInstr->getOperand(0);
7577 MachineOperand* argOpers[2 + X86AddrNumOperands];
7578 int numArgs = mInstr->getNumOperands() - 1;
7579 for (int i=0; i < numArgs; ++i)
7580 argOpers[i] = &mInstr->getOperand(i+1);
7582 // x86 address has 4 operands: base, index, scale, and displacement
7583 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7584 int valArgIndx = lastAddrIndx + 1;
7586 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7587 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7588 for (int i=0; i <= lastAddrIndx; ++i)
7589 (*MIB).addOperand(*argOpers[i]);
7591 // We only support register and immediate values
7592 assert((argOpers[valArgIndx]->isReg() ||
7593 argOpers[valArgIndx]->isImm()) &&
7596 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7597 if (argOpers[valArgIndx]->isReg())
7598 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7600 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7601 (*MIB).addOperand(*argOpers[valArgIndx]);
7603 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7606 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7611 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7612 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7616 // Cmp and exchange if none has modified the memory location
7617 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7618 for (int i=0; i <= lastAddrIndx; ++i)
7619 (*MIB).addOperand(*argOpers[i]);
7621 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7622 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
7624 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7625 MIB.addReg(X86::EAX);
7628 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7630 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7634 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
7635 // all of this code can be replaced with that in the .td file.
7637 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
7638 unsigned numArgs, bool memArg) const {
7640 MachineFunction *F = BB->getParent();
7641 DebugLoc dl = MI->getDebugLoc();
7642 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7647 Opc = numArgs == 3 ?
7648 X86::PCMPISTRM128rm :
7649 X86::PCMPESTRM128rm;
7651 Opc = numArgs == 3 ?
7652 X86::PCMPISTRM128rr :
7653 X86::PCMPESTRM128rr;
7656 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
7658 for (unsigned i = 0; i < numArgs; ++i) {
7659 MachineOperand &Op = MI->getOperand(i+1);
7661 if (!(Op.isReg() && Op.isImplicit()))
7665 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
7668 F->DeleteMachineInstr(MI);
7674 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
7676 MachineBasicBlock *MBB) const {
7677 // Emit code to save XMM registers to the stack. The ABI says that the
7678 // number of registers to save is given in %al, so it's theoretically
7679 // possible to do an indirect jump trick to avoid saving all of them,
7680 // however this code takes a simpler approach and just executes all
7681 // of the stores if %al is non-zero. It's less code, and it's probably
7682 // easier on the hardware branch predictor, and stores aren't all that
7683 // expensive anyway.
7685 // Create the new basic blocks. One block contains all the XMM stores,
7686 // and one block is the final destination regardless of whether any
7687 // stores were performed.
7688 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7689 MachineFunction *F = MBB->getParent();
7690 MachineFunction::iterator MBBIter = MBB;
7692 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
7693 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
7694 F->insert(MBBIter, XMMSaveMBB);
7695 F->insert(MBBIter, EndMBB);
7698 // Move any original successors of MBB to the end block.
7699 EndMBB->transferSuccessors(MBB);
7700 // The original block will now fall through to the XMM save block.
7701 MBB->addSuccessor(XMMSaveMBB);
7702 // The XMMSaveMBB will fall through to the end block.
7703 XMMSaveMBB->addSuccessor(EndMBB);
7705 // Now add the instructions.
7706 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7707 DebugLoc DL = MI->getDebugLoc();
7709 unsigned CountReg = MI->getOperand(0).getReg();
7710 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
7711 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
7713 if (!Subtarget->isTargetWin64()) {
7714 // If %al is 0, branch around the XMM save block.
7715 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
7716 BuildMI(MBB, DL, TII->get(X86::JE)).addMBB(EndMBB);
7717 MBB->addSuccessor(EndMBB);
7720 // In the XMM save block, save all the XMM argument registers.
7721 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
7722 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
7723 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
7724 .addFrameIndex(RegSaveFrameIndex)
7725 .addImm(/*Scale=*/1)
7726 .addReg(/*IndexReg=*/0)
7727 .addImm(/*Disp=*/Offset)
7728 .addReg(/*Segment=*/0)
7729 .addReg(MI->getOperand(i).getReg())
7730 .addMemOperand(MachineMemOperand(
7731 PseudoSourceValue::getFixedStack(RegSaveFrameIndex),
7732 MachineMemOperand::MOStore, Offset,
7733 /*Size=*/16, /*Align=*/16));
7736 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7742 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
7743 MachineBasicBlock *BB) const {
7744 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7745 DebugLoc DL = MI->getDebugLoc();
7747 // To "insert" a SELECT_CC instruction, we actually have to insert the
7748 // diamond control-flow pattern. The incoming instruction knows the
7749 // destination vreg to set, the condition code register to branch on, the
7750 // true/false values to select between, and a branch opcode to use.
7751 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7752 MachineFunction::iterator It = BB;
7758 // cmpTY ccX, r1, r2
7760 // fallthrough --> copy0MBB
7761 MachineBasicBlock *thisMBB = BB;
7762 MachineFunction *F = BB->getParent();
7763 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7764 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7766 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7767 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
7768 F->insert(It, copy0MBB);
7769 F->insert(It, sinkMBB);
7770 // Update machine-CFG edges by transferring all successors of the current
7771 // block to the new block which will contain the Phi node for the select.
7772 sinkMBB->transferSuccessors(BB);
7774 // Add the true and fallthrough blocks as its successors.
7775 BB->addSuccessor(copy0MBB);
7776 BB->addSuccessor(sinkMBB);
7779 // %FalseValue = ...
7780 // # fallthrough to sinkMBB
7783 // Update machine-CFG edges
7784 BB->addSuccessor(sinkMBB);
7787 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7790 BuildMI(BB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg())
7791 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7792 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7794 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7800 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7801 MachineBasicBlock *BB) const {
7802 switch (MI->getOpcode()) {
7803 default: assert(false && "Unexpected instr type to insert");
7805 case X86::CMOV_V1I64:
7806 case X86::CMOV_FR32:
7807 case X86::CMOV_FR64:
7808 case X86::CMOV_V4F32:
7809 case X86::CMOV_V2F64:
7810 case X86::CMOV_V2I64:
7811 return EmitLoweredSelect(MI, BB);
7813 case X86::FP32_TO_INT16_IN_MEM:
7814 case X86::FP32_TO_INT32_IN_MEM:
7815 case X86::FP32_TO_INT64_IN_MEM:
7816 case X86::FP64_TO_INT16_IN_MEM:
7817 case X86::FP64_TO_INT32_IN_MEM:
7818 case X86::FP64_TO_INT64_IN_MEM:
7819 case X86::FP80_TO_INT16_IN_MEM:
7820 case X86::FP80_TO_INT32_IN_MEM:
7821 case X86::FP80_TO_INT64_IN_MEM: {
7822 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7823 DebugLoc DL = MI->getDebugLoc();
7825 // Change the floating point control register to use "round towards zero"
7826 // mode when truncating to an integer value.
7827 MachineFunction *F = BB->getParent();
7828 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7829 addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7831 // Load the old value of the high byte of the control word...
7833 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7834 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW),
7837 // Set the high part to be round to zero...
7838 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
7841 // Reload the modified control word now...
7842 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
7844 // Restore the memory image of control word to original value
7845 addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
7848 // Get the X86 opcode to use.
7850 switch (MI->getOpcode()) {
7851 default: llvm_unreachable("illegal opcode!");
7852 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7853 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7854 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7855 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7856 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7857 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
7858 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7859 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7860 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
7864 MachineOperand &Op = MI->getOperand(0);
7866 AM.BaseType = X86AddressMode::RegBase;
7867 AM.Base.Reg = Op.getReg();
7869 AM.BaseType = X86AddressMode::FrameIndexBase;
7870 AM.Base.FrameIndex = Op.getIndex();
7872 Op = MI->getOperand(1);
7874 AM.Scale = Op.getImm();
7875 Op = MI->getOperand(2);
7877 AM.IndexReg = Op.getImm();
7878 Op = MI->getOperand(3);
7879 if (Op.isGlobal()) {
7880 AM.GV = Op.getGlobal();
7882 AM.Disp = Op.getImm();
7884 addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM)
7885 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
7887 // Reload the original control word now.
7888 addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx);
7890 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7893 // String/text processing lowering.
7894 case X86::PCMPISTRM128REG:
7895 return EmitPCMP(MI, BB, 3, false /* in-mem */);
7896 case X86::PCMPISTRM128MEM:
7897 return EmitPCMP(MI, BB, 3, true /* in-mem */);
7898 case X86::PCMPESTRM128REG:
7899 return EmitPCMP(MI, BB, 5, false /* in mem */);
7900 case X86::PCMPESTRM128MEM:
7901 return EmitPCMP(MI, BB, 5, true /* in mem */);
7904 case X86::ATOMAND32:
7905 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7906 X86::AND32ri, X86::MOV32rm,
7907 X86::LCMPXCHG32, X86::MOV32rr,
7908 X86::NOT32r, X86::EAX,
7909 X86::GR32RegisterClass);
7911 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7912 X86::OR32ri, X86::MOV32rm,
7913 X86::LCMPXCHG32, X86::MOV32rr,
7914 X86::NOT32r, X86::EAX,
7915 X86::GR32RegisterClass);
7916 case X86::ATOMXOR32:
7917 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7918 X86::XOR32ri, X86::MOV32rm,
7919 X86::LCMPXCHG32, X86::MOV32rr,
7920 X86::NOT32r, X86::EAX,
7921 X86::GR32RegisterClass);
7922 case X86::ATOMNAND32:
7923 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7924 X86::AND32ri, X86::MOV32rm,
7925 X86::LCMPXCHG32, X86::MOV32rr,
7926 X86::NOT32r, X86::EAX,
7927 X86::GR32RegisterClass, true);
7928 case X86::ATOMMIN32:
7929 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7930 case X86::ATOMMAX32:
7931 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7932 case X86::ATOMUMIN32:
7933 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7934 case X86::ATOMUMAX32:
7935 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7937 case X86::ATOMAND16:
7938 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7939 X86::AND16ri, X86::MOV16rm,
7940 X86::LCMPXCHG16, X86::MOV16rr,
7941 X86::NOT16r, X86::AX,
7942 X86::GR16RegisterClass);
7944 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7945 X86::OR16ri, X86::MOV16rm,
7946 X86::LCMPXCHG16, X86::MOV16rr,
7947 X86::NOT16r, X86::AX,
7948 X86::GR16RegisterClass);
7949 case X86::ATOMXOR16:
7950 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7951 X86::XOR16ri, X86::MOV16rm,
7952 X86::LCMPXCHG16, X86::MOV16rr,
7953 X86::NOT16r, X86::AX,
7954 X86::GR16RegisterClass);
7955 case X86::ATOMNAND16:
7956 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7957 X86::AND16ri, X86::MOV16rm,
7958 X86::LCMPXCHG16, X86::MOV16rr,
7959 X86::NOT16r, X86::AX,
7960 X86::GR16RegisterClass, true);
7961 case X86::ATOMMIN16:
7962 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7963 case X86::ATOMMAX16:
7964 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7965 case X86::ATOMUMIN16:
7966 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7967 case X86::ATOMUMAX16:
7968 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7971 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7972 X86::AND8ri, X86::MOV8rm,
7973 X86::LCMPXCHG8, X86::MOV8rr,
7974 X86::NOT8r, X86::AL,
7975 X86::GR8RegisterClass);
7977 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
7978 X86::OR8ri, X86::MOV8rm,
7979 X86::LCMPXCHG8, X86::MOV8rr,
7980 X86::NOT8r, X86::AL,
7981 X86::GR8RegisterClass);
7983 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7984 X86::XOR8ri, X86::MOV8rm,
7985 X86::LCMPXCHG8, X86::MOV8rr,
7986 X86::NOT8r, X86::AL,
7987 X86::GR8RegisterClass);
7988 case X86::ATOMNAND8:
7989 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7990 X86::AND8ri, X86::MOV8rm,
7991 X86::LCMPXCHG8, X86::MOV8rr,
7992 X86::NOT8r, X86::AL,
7993 X86::GR8RegisterClass, true);
7994 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
7995 // This group is for 64-bit host.
7996 case X86::ATOMAND64:
7997 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7998 X86::AND64ri32, X86::MOV64rm,
7999 X86::LCMPXCHG64, X86::MOV64rr,
8000 X86::NOT64r, X86::RAX,
8001 X86::GR64RegisterClass);
8003 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
8004 X86::OR64ri32, X86::MOV64rm,
8005 X86::LCMPXCHG64, X86::MOV64rr,
8006 X86::NOT64r, X86::RAX,
8007 X86::GR64RegisterClass);
8008 case X86::ATOMXOR64:
8009 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
8010 X86::XOR64ri32, X86::MOV64rm,
8011 X86::LCMPXCHG64, X86::MOV64rr,
8012 X86::NOT64r, X86::RAX,
8013 X86::GR64RegisterClass);
8014 case X86::ATOMNAND64:
8015 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
8016 X86::AND64ri32, X86::MOV64rm,
8017 X86::LCMPXCHG64, X86::MOV64rr,
8018 X86::NOT64r, X86::RAX,
8019 X86::GR64RegisterClass, true);
8020 case X86::ATOMMIN64:
8021 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
8022 case X86::ATOMMAX64:
8023 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
8024 case X86::ATOMUMIN64:
8025 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
8026 case X86::ATOMUMAX64:
8027 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
8029 // This group does 64-bit operations on a 32-bit host.
8030 case X86::ATOMAND6432:
8031 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8032 X86::AND32rr, X86::AND32rr,
8033 X86::AND32ri, X86::AND32ri,
8035 case X86::ATOMOR6432:
8036 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8037 X86::OR32rr, X86::OR32rr,
8038 X86::OR32ri, X86::OR32ri,
8040 case X86::ATOMXOR6432:
8041 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8042 X86::XOR32rr, X86::XOR32rr,
8043 X86::XOR32ri, X86::XOR32ri,
8045 case X86::ATOMNAND6432:
8046 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8047 X86::AND32rr, X86::AND32rr,
8048 X86::AND32ri, X86::AND32ri,
8050 case X86::ATOMADD6432:
8051 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8052 X86::ADD32rr, X86::ADC32rr,
8053 X86::ADD32ri, X86::ADC32ri,
8055 case X86::ATOMSUB6432:
8056 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8057 X86::SUB32rr, X86::SBB32rr,
8058 X86::SUB32ri, X86::SBB32ri,
8060 case X86::ATOMSWAP6432:
8061 return EmitAtomicBit6432WithCustomInserter(MI, BB,
8062 X86::MOV32rr, X86::MOV32rr,
8063 X86::MOV32ri, X86::MOV32ri,
8065 case X86::VASTART_SAVE_XMM_REGS:
8066 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
8070 //===----------------------------------------------------------------------===//
8071 // X86 Optimization Hooks
8072 //===----------------------------------------------------------------------===//
8074 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8078 const SelectionDAG &DAG,
8079 unsigned Depth) const {
8080 unsigned Opc = Op.getOpcode();
8081 assert((Opc >= ISD::BUILTIN_OP_END ||
8082 Opc == ISD::INTRINSIC_WO_CHAIN ||
8083 Opc == ISD::INTRINSIC_W_CHAIN ||
8084 Opc == ISD::INTRINSIC_VOID) &&
8085 "Should use MaskedValueIsZero if you don't know whether Op"
8086 " is a target node!");
8088 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
8097 // These nodes' second result is a boolean.
8098 if (Op.getResNo() == 0)
8102 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
8103 Mask.getBitWidth() - 1);
8108 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
8109 /// node is a GlobalAddress + offset.
8110 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
8111 GlobalValue* &GA, int64_t &Offset) const{
8112 if (N->getOpcode() == X86ISD::Wrapper) {
8113 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
8114 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
8115 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
8119 return TargetLowering::isGAPlusOffset(N, GA, Offset);
8122 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
8123 const TargetLowering &TLI) {
8126 if (TLI.isGAPlusOffset(Base, GV, Offset))
8127 return (GV->getAlignment() >= N && (Offset % N) == 0);
8128 // DAG combine handles the stack object case.
8132 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
8133 EVT EVT, LoadSDNode *&LDBase,
8134 unsigned &LastLoadedElt,
8135 SelectionDAG &DAG, MachineFrameInfo *MFI,
8136 const TargetLowering &TLI) {
8138 LastLoadedElt = -1U;
8139 for (unsigned i = 0; i < NumElems; ++i) {
8140 if (N->getMaskElt(i) < 0) {
8146 SDValue Elt = DAG.getShuffleScalarElt(N, i);
8147 if (!Elt.getNode() ||
8148 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
8151 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
8153 LDBase = cast<LoadSDNode>(Elt.getNode());
8157 if (Elt.getOpcode() == ISD::UNDEF)
8160 LoadSDNode *LD = cast<LoadSDNode>(Elt);
8161 if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI))
8168 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
8169 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
8170 /// if the load addresses are consecutive, non-overlapping, and in the right
8171 /// order. In the case of v2i64, it will see if it can rewrite the
8172 /// shuffle to be an appropriate build vector so it can take advantage of
8173 // performBuildVectorCombine.
8174 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
8175 const TargetLowering &TLI) {
8176 DebugLoc dl = N->getDebugLoc();
8177 EVT VT = N->getValueType(0);
8178 EVT EVT = VT.getVectorElementType();
8179 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8180 unsigned NumElems = VT.getVectorNumElements();
8182 if (VT.getSizeInBits() != 128)
8185 // Try to combine a vector_shuffle into a 128-bit load.
8186 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8187 LoadSDNode *LD = NULL;
8188 unsigned LastLoadedElt;
8189 if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, LD, LastLoadedElt, DAG,
8193 if (LastLoadedElt == NumElems - 1) {
8194 if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI))
8195 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8196 LD->getSrcValue(), LD->getSrcValueOffset(),
8198 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8199 LD->getSrcValue(), LD->getSrcValueOffset(),
8200 LD->isVolatile(), LD->getAlignment());
8201 } else if (NumElems == 4 && LastLoadedElt == 1) {
8202 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8203 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8204 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8205 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8210 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8211 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8212 const X86Subtarget *Subtarget) {
8213 DebugLoc DL = N->getDebugLoc();
8214 SDValue Cond = N->getOperand(0);
8215 // Get the LHS/RHS of the select.
8216 SDValue LHS = N->getOperand(1);
8217 SDValue RHS = N->getOperand(2);
8219 // If we have SSE[12] support, try to form min/max nodes.
8220 if (Subtarget->hasSSE2() &&
8221 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8222 Cond.getOpcode() == ISD::SETCC) {
8223 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8225 unsigned Opcode = 0;
8226 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8229 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
8232 if (!UnsafeFPMath) break;
8234 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
8236 Opcode = X86ISD::FMIN;
8239 case ISD::SETOGT: // (X > Y) ? X : Y -> max
8242 if (!UnsafeFPMath) break;
8244 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
8246 Opcode = X86ISD::FMAX;
8249 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8253 // This can use a min only if the LHS isn't NaN.
8254 if (DAG.isKnownNeverNaN(LHS))
8255 Opcode = X86ISD::FMIN;
8256 else if (DAG.isKnownNeverNaN(RHS)) {
8257 Opcode = X86ISD::FMIN;
8258 // Put the potential NaN in the RHS so that SSE will preserve it.
8259 std::swap(LHS, RHS);
8263 case ISD::SETUGT: // (X > Y) ? Y : X -> min
8265 if (!UnsafeFPMath) break;
8267 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
8269 Opcode = X86ISD::FMIN;
8273 // This can use a max only if the LHS isn't NaN.
8274 if (DAG.isKnownNeverNaN(LHS))
8275 Opcode = X86ISD::FMAX;
8276 else if (DAG.isKnownNeverNaN(RHS)) {
8277 Opcode = X86ISD::FMAX;
8278 // Put the potential NaN in the RHS so that SSE will preserve it.
8279 std::swap(LHS, RHS);
8283 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
8285 if (!UnsafeFPMath) break;
8287 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
8289 Opcode = X86ISD::FMAX;
8295 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8298 // If this is a select between two integer constants, try to do some
8300 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8301 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8302 // Don't do this for crazy integer types.
8303 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8304 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8305 // so that TrueC (the true value) is larger than FalseC.
8306 bool NeedsCondInvert = false;
8308 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8309 // Efficiently invertible.
8310 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8311 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8312 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8313 NeedsCondInvert = true;
8314 std::swap(TrueC, FalseC);
8317 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8318 if (FalseC->getAPIntValue() == 0 &&
8319 TrueC->getAPIntValue().isPowerOf2()) {
8320 if (NeedsCondInvert) // Invert the condition if needed.
8321 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8322 DAG.getConstant(1, Cond.getValueType()));
8324 // Zero extend the condition if needed.
8325 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8327 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8328 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8329 DAG.getConstant(ShAmt, MVT::i8));
8332 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8333 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8334 if (NeedsCondInvert) // Invert the condition if needed.
8335 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8336 DAG.getConstant(1, Cond.getValueType()));
8338 // Zero extend the condition if needed.
8339 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8340 FalseC->getValueType(0), Cond);
8341 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8342 SDValue(FalseC, 0));
8345 // Optimize cases that will turn into an LEA instruction. This requires
8346 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8347 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8348 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8349 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8351 bool isFastMultiplier = false;
8353 switch ((unsigned char)Diff) {
8355 case 1: // result = add base, cond
8356 case 2: // result = lea base( , cond*2)
8357 case 3: // result = lea base(cond, cond*2)
8358 case 4: // result = lea base( , cond*4)
8359 case 5: // result = lea base(cond, cond*4)
8360 case 8: // result = lea base( , cond*8)
8361 case 9: // result = lea base(cond, cond*8)
8362 isFastMultiplier = true;
8367 if (isFastMultiplier) {
8368 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8369 if (NeedsCondInvert) // Invert the condition if needed.
8370 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8371 DAG.getConstant(1, Cond.getValueType()));
8373 // Zero extend the condition if needed.
8374 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8376 // Scale the condition by the difference.
8378 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8379 DAG.getConstant(Diff, Cond.getValueType()));
8381 // Add the base if non-zero.
8382 if (FalseC->getAPIntValue() != 0)
8383 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8384 SDValue(FalseC, 0));
8394 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8395 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8396 TargetLowering::DAGCombinerInfo &DCI) {
8397 DebugLoc DL = N->getDebugLoc();
8399 // If the flag operand isn't dead, don't touch this CMOV.
8400 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8403 // If this is a select between two integer constants, try to do some
8404 // optimizations. Note that the operands are ordered the opposite of SELECT
8406 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8407 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8408 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8409 // larger than FalseC (the false value).
8410 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8412 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8413 CC = X86::GetOppositeBranchCondition(CC);
8414 std::swap(TrueC, FalseC);
8417 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
8418 // This is efficient for any integer data type (including i8/i16) and
8420 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8421 SDValue Cond = N->getOperand(3);
8422 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8423 DAG.getConstant(CC, MVT::i8), Cond);
8425 // Zero extend the condition if needed.
8426 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8428 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8429 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8430 DAG.getConstant(ShAmt, MVT::i8));
8431 if (N->getNumValues() == 2) // Dead flag value?
8432 return DCI.CombineTo(N, Cond, SDValue());
8436 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8437 // for any integer data type, including i8/i16.
8438 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8439 SDValue Cond = N->getOperand(3);
8440 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8441 DAG.getConstant(CC, MVT::i8), Cond);
8443 // Zero extend the condition if needed.
8444 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8445 FalseC->getValueType(0), Cond);
8446 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8447 SDValue(FalseC, 0));
8449 if (N->getNumValues() == 2) // Dead flag value?
8450 return DCI.CombineTo(N, Cond, SDValue());
8454 // Optimize cases that will turn into an LEA instruction. This requires
8455 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8456 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8457 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8458 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8460 bool isFastMultiplier = false;
8462 switch ((unsigned char)Diff) {
8464 case 1: // result = add base, cond
8465 case 2: // result = lea base( , cond*2)
8466 case 3: // result = lea base(cond, cond*2)
8467 case 4: // result = lea base( , cond*4)
8468 case 5: // result = lea base(cond, cond*4)
8469 case 8: // result = lea base( , cond*8)
8470 case 9: // result = lea base(cond, cond*8)
8471 isFastMultiplier = true;
8476 if (isFastMultiplier) {
8477 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8478 SDValue Cond = N->getOperand(3);
8479 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8480 DAG.getConstant(CC, MVT::i8), Cond);
8481 // Zero extend the condition if needed.
8482 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8484 // Scale the condition by the difference.
8486 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8487 DAG.getConstant(Diff, Cond.getValueType()));
8489 // Add the base if non-zero.
8490 if (FalseC->getAPIntValue() != 0)
8491 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8492 SDValue(FalseC, 0));
8493 if (N->getNumValues() == 2) // Dead flag value?
8494 return DCI.CombineTo(N, Cond, SDValue());
8504 /// PerformMulCombine - Optimize a single multiply with constant into two
8505 /// in order to implement it with two cheaper instructions, e.g.
8506 /// LEA + SHL, LEA + LEA.
8507 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8508 TargetLowering::DAGCombinerInfo &DCI) {
8509 if (DAG.getMachineFunction().
8510 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8513 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8516 EVT VT = N->getValueType(0);
8520 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8523 uint64_t MulAmt = C->getZExtValue();
8524 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8527 uint64_t MulAmt1 = 0;
8528 uint64_t MulAmt2 = 0;
8529 if ((MulAmt % 9) == 0) {
8531 MulAmt2 = MulAmt / 9;
8532 } else if ((MulAmt % 5) == 0) {
8534 MulAmt2 = MulAmt / 5;
8535 } else if ((MulAmt % 3) == 0) {
8537 MulAmt2 = MulAmt / 3;
8540 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8541 DebugLoc DL = N->getDebugLoc();
8543 if (isPowerOf2_64(MulAmt2) &&
8544 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8545 // If second multiplifer is pow2, issue it first. We want the multiply by
8546 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8548 std::swap(MulAmt1, MulAmt2);
8551 if (isPowerOf2_64(MulAmt1))
8552 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8553 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8555 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
8556 DAG.getConstant(MulAmt1, VT));
8558 if (isPowerOf2_64(MulAmt2))
8559 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8560 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8562 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
8563 DAG.getConstant(MulAmt2, VT));
8565 // Do not add new nodes to DAG combiner worklist.
8566 DCI.CombineTo(N, NewMul, false);
8572 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
8574 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
8575 const X86Subtarget *Subtarget) {
8576 // On X86 with SSE2 support, we can transform this to a vector shift if
8577 // all elements are shifted by the same amount. We can't do this in legalize
8578 // because the a constant vector is typically transformed to a constant pool
8579 // so we have no knowledge of the shift amount.
8580 if (!Subtarget->hasSSE2())
8583 EVT VT = N->getValueType(0);
8584 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
8587 SDValue ShAmtOp = N->getOperand(1);
8588 EVT EltVT = VT.getVectorElementType();
8589 DebugLoc DL = N->getDebugLoc();
8590 SDValue BaseShAmt = SDValue();
8591 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
8592 unsigned NumElts = VT.getVectorNumElements();
8594 for (; i != NumElts; ++i) {
8595 SDValue Arg = ShAmtOp.getOperand(i);
8596 if (Arg.getOpcode() == ISD::UNDEF) continue;
8600 for (; i != NumElts; ++i) {
8601 SDValue Arg = ShAmtOp.getOperand(i);
8602 if (Arg.getOpcode() == ISD::UNDEF) continue;
8603 if (Arg != BaseShAmt) {
8607 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
8608 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
8609 SDValue InVec = ShAmtOp.getOperand(0);
8610 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
8611 unsigned NumElts = InVec.getValueType().getVectorNumElements();
8613 for (; i != NumElts; ++i) {
8614 SDValue Arg = InVec.getOperand(i);
8615 if (Arg.getOpcode() == ISD::UNDEF) continue;
8619 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
8620 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
8621 unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
8622 if (C->getZExtValue() == SplatIdx)
8623 BaseShAmt = InVec.getOperand(1);
8626 if (BaseShAmt.getNode() == 0)
8627 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
8628 DAG.getIntPtrConstant(0));
8632 // The shift amount is an i32.
8633 if (EltVT.bitsGT(MVT::i32))
8634 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
8635 else if (EltVT.bitsLT(MVT::i32))
8636 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
8638 // The shift amount is identical so we can do a vector shift.
8639 SDValue ValOp = N->getOperand(0);
8640 switch (N->getOpcode()) {
8642 llvm_unreachable("Unknown shift opcode!");
8645 if (VT == MVT::v2i64)
8646 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8647 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8649 if (VT == MVT::v4i32)
8650 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8651 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8653 if (VT == MVT::v8i16)
8654 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8655 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8659 if (VT == MVT::v4i32)
8660 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8661 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
8663 if (VT == MVT::v8i16)
8664 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8665 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
8669 if (VT == MVT::v2i64)
8670 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8671 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8673 if (VT == MVT::v4i32)
8674 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8675 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
8677 if (VT == MVT::v8i16)
8678 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8679 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
8686 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
8687 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
8688 const X86Subtarget *Subtarget) {
8689 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
8690 // the FP state in cases where an emms may be missing.
8691 // A preferable solution to the general problem is to figure out the right
8692 // places to insert EMMS. This qualifies as a quick hack.
8694 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
8695 StoreSDNode *St = cast<StoreSDNode>(N);
8696 EVT VT = St->getValue().getValueType();
8697 if (VT.getSizeInBits() != 64)
8700 const Function *F = DAG.getMachineFunction().getFunction();
8701 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
8702 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
8703 && Subtarget->hasSSE2();
8704 if ((VT.isVector() ||
8705 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
8706 isa<LoadSDNode>(St->getValue()) &&
8707 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
8708 St->getChain().hasOneUse() && !St->isVolatile()) {
8709 SDNode* LdVal = St->getValue().getNode();
8711 int TokenFactorIndex = -1;
8712 SmallVector<SDValue, 8> Ops;
8713 SDNode* ChainVal = St->getChain().getNode();
8714 // Must be a store of a load. We currently handle two cases: the load
8715 // is a direct child, and it's under an intervening TokenFactor. It is
8716 // possible to dig deeper under nested TokenFactors.
8717 if (ChainVal == LdVal)
8718 Ld = cast<LoadSDNode>(St->getChain());
8719 else if (St->getValue().hasOneUse() &&
8720 ChainVal->getOpcode() == ISD::TokenFactor) {
8721 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
8722 if (ChainVal->getOperand(i).getNode() == LdVal) {
8723 TokenFactorIndex = i;
8724 Ld = cast<LoadSDNode>(St->getValue());
8726 Ops.push_back(ChainVal->getOperand(i));
8730 if (!Ld || !ISD::isNormalLoad(Ld))
8733 // If this is not the MMX case, i.e. we are just turning i64 load/store
8734 // into f64 load/store, avoid the transformation if there are multiple
8735 // uses of the loaded value.
8736 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
8739 DebugLoc LdDL = Ld->getDebugLoc();
8740 DebugLoc StDL = N->getDebugLoc();
8741 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
8742 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
8744 if (Subtarget->is64Bit() || F64IsLegal) {
8745 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
8746 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
8747 Ld->getBasePtr(), Ld->getSrcValue(),
8748 Ld->getSrcValueOffset(), Ld->isVolatile(),
8749 Ld->getAlignment());
8750 SDValue NewChain = NewLd.getValue(1);
8751 if (TokenFactorIndex != -1) {
8752 Ops.push_back(NewChain);
8753 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8756 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
8757 St->getSrcValue(), St->getSrcValueOffset(),
8758 St->isVolatile(), St->getAlignment());
8761 // Otherwise, lower to two pairs of 32-bit loads / stores.
8762 SDValue LoAddr = Ld->getBasePtr();
8763 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
8764 DAG.getConstant(4, MVT::i32));
8766 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
8767 Ld->getSrcValue(), Ld->getSrcValueOffset(),
8768 Ld->isVolatile(), Ld->getAlignment());
8769 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
8770 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
8772 MinAlign(Ld->getAlignment(), 4));
8774 SDValue NewChain = LoLd.getValue(1);
8775 if (TokenFactorIndex != -1) {
8776 Ops.push_back(LoLd);
8777 Ops.push_back(HiLd);
8778 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8782 LoAddr = St->getBasePtr();
8783 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
8784 DAG.getConstant(4, MVT::i32));
8786 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
8787 St->getSrcValue(), St->getSrcValueOffset(),
8788 St->isVolatile(), St->getAlignment());
8789 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
8791 St->getSrcValueOffset() + 4,
8793 MinAlign(St->getAlignment(), 4));
8794 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
8799 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
8800 /// X86ISD::FXOR nodes.
8801 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
8802 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
8803 // F[X]OR(0.0, x) -> x
8804 // F[X]OR(x, 0.0) -> x
8805 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8806 if (C->getValueAPF().isPosZero())
8807 return N->getOperand(1);
8808 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8809 if (C->getValueAPF().isPosZero())
8810 return N->getOperand(0);
8814 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
8815 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
8816 // FAND(0.0, x) -> 0.0
8817 // FAND(x, 0.0) -> 0.0
8818 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8819 if (C->getValueAPF().isPosZero())
8820 return N->getOperand(0);
8821 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8822 if (C->getValueAPF().isPosZero())
8823 return N->getOperand(1);
8827 static SDValue PerformBTCombine(SDNode *N,
8829 TargetLowering::DAGCombinerInfo &DCI) {
8830 // BT ignores high bits in the bit index operand.
8831 SDValue Op1 = N->getOperand(1);
8832 if (Op1.hasOneUse()) {
8833 unsigned BitWidth = Op1.getValueSizeInBits();
8834 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
8835 APInt KnownZero, KnownOne;
8836 TargetLowering::TargetLoweringOpt TLO(DAG);
8837 TargetLowering &TLI = DAG.getTargetLoweringInfo();
8838 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
8839 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
8840 DCI.CommitTargetLoweringOpt(TLO);
8845 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
8846 SDValue Op = N->getOperand(0);
8847 if (Op.getOpcode() == ISD::BIT_CONVERT)
8848 Op = Op.getOperand(0);
8849 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
8850 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
8851 VT.getVectorElementType().getSizeInBits() ==
8852 OpVT.getVectorElementType().getSizeInBits()) {
8853 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
8858 // On X86 and X86-64, atomic operations are lowered to locked instructions.
8859 // Locked instructions, in turn, have implicit fence semantics (all memory
8860 // operations are flushed before issuing the locked instruction, and the
8861 // are not buffered), so we can fold away the common pattern of
8862 // fence-atomic-fence.
8863 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
8864 SDValue atomic = N->getOperand(0);
8865 switch (atomic.getOpcode()) {
8866 case ISD::ATOMIC_CMP_SWAP:
8867 case ISD::ATOMIC_SWAP:
8868 case ISD::ATOMIC_LOAD_ADD:
8869 case ISD::ATOMIC_LOAD_SUB:
8870 case ISD::ATOMIC_LOAD_AND:
8871 case ISD::ATOMIC_LOAD_OR:
8872 case ISD::ATOMIC_LOAD_XOR:
8873 case ISD::ATOMIC_LOAD_NAND:
8874 case ISD::ATOMIC_LOAD_MIN:
8875 case ISD::ATOMIC_LOAD_MAX:
8876 case ISD::ATOMIC_LOAD_UMIN:
8877 case ISD::ATOMIC_LOAD_UMAX:
8883 SDValue fence = atomic.getOperand(0);
8884 if (fence.getOpcode() != ISD::MEMBARRIER)
8887 switch (atomic.getOpcode()) {
8888 case ISD::ATOMIC_CMP_SWAP:
8889 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8890 atomic.getOperand(1), atomic.getOperand(2),
8891 atomic.getOperand(3));
8892 case ISD::ATOMIC_SWAP:
8893 case ISD::ATOMIC_LOAD_ADD:
8894 case ISD::ATOMIC_LOAD_SUB:
8895 case ISD::ATOMIC_LOAD_AND:
8896 case ISD::ATOMIC_LOAD_OR:
8897 case ISD::ATOMIC_LOAD_XOR:
8898 case ISD::ATOMIC_LOAD_NAND:
8899 case ISD::ATOMIC_LOAD_MIN:
8900 case ISD::ATOMIC_LOAD_MAX:
8901 case ISD::ATOMIC_LOAD_UMIN:
8902 case ISD::ATOMIC_LOAD_UMAX:
8903 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8904 atomic.getOperand(1), atomic.getOperand(2));
8910 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
8911 DAGCombinerInfo &DCI) const {
8912 SelectionDAG &DAG = DCI.DAG;
8913 switch (N->getOpcode()) {
8915 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
8916 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
8917 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
8918 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
8921 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
8922 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
8924 case X86ISD::FOR: return PerformFORCombine(N, DAG);
8925 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
8926 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
8927 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
8928 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
8934 //===----------------------------------------------------------------------===//
8935 // X86 Inline Assembly Support
8936 //===----------------------------------------------------------------------===//
8938 static bool LowerToBSwap(CallInst *CI) {
8939 // FIXME: this should verify that we are targetting a 486 or better. If not,
8940 // we will turn this bswap into something that will be lowered to logical ops
8941 // instead of emitting the bswap asm. For now, we don't support 486 or lower
8942 // so don't worry about this.
8944 // Verify this is a simple bswap.
8945 if (CI->getNumOperands() != 2 ||
8946 CI->getType() != CI->getOperand(1)->getType() ||
8947 !CI->getType()->isInteger())
8950 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
8951 if (!Ty || Ty->getBitWidth() % 16 != 0)
8954 // Okay, we can do this xform, do so now.
8955 const Type *Tys[] = { Ty };
8956 Module *M = CI->getParent()->getParent()->getParent();
8957 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
8959 Value *Op = CI->getOperand(1);
8960 Op = CallInst::Create(Int, Op, CI->getName(), CI);
8962 CI->replaceAllUsesWith(Op);
8963 CI->eraseFromParent();
8967 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
8968 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
8969 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
8971 std::string AsmStr = IA->getAsmString();
8973 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
8974 std::vector<std::string> AsmPieces;
8975 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
8977 switch (AsmPieces.size()) {
8978 default: return false;
8980 AsmStr = AsmPieces[0];
8982 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
8985 if (AsmPieces.size() == 2 &&
8986 (AsmPieces[0] == "bswap" ||
8987 AsmPieces[0] == "bswapq" ||
8988 AsmPieces[0] == "bswapl") &&
8989 (AsmPieces[1] == "$0" ||
8990 AsmPieces[1] == "${0:q}")) {
8991 // No need to check constraints, nothing other than the equivalent of
8992 // "=r,0" would be valid here.
8993 return LowerToBSwap(CI);
8995 // rorw $$8, ${0:w} --> llvm.bswap.i16
8996 if (CI->getType() == Type::getInt16Ty(CI->getContext()) &&
8997 AsmPieces.size() == 3 &&
8998 AsmPieces[0] == "rorw" &&
8999 AsmPieces[1] == "$$8," &&
9000 AsmPieces[2] == "${0:w}" &&
9001 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
9002 return LowerToBSwap(CI);
9006 if (CI->getType() == Type::getInt64Ty(CI->getContext()) &&
9007 Constraints.size() >= 2 &&
9008 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
9009 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
9010 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
9011 std::vector<std::string> Words;
9012 SplitString(AsmPieces[0], Words, " \t");
9013 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
9015 SplitString(AsmPieces[1], Words, " \t");
9016 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
9018 SplitString(AsmPieces[2], Words, " \t,");
9019 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
9020 Words[2] == "%edx") {
9021 return LowerToBSwap(CI);
9033 /// getConstraintType - Given a constraint letter, return the type of
9034 /// constraint it is for this target.
9035 X86TargetLowering::ConstraintType
9036 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
9037 if (Constraint.size() == 1) {
9038 switch (Constraint[0]) {
9050 return C_RegisterClass;
9058 return TargetLowering::getConstraintType(Constraint);
9061 /// LowerXConstraint - try to replace an X constraint, which matches anything,
9062 /// with another that has more specific requirements based on the type of the
9063 /// corresponding operand.
9064 const char *X86TargetLowering::
9065 LowerXConstraint(EVT ConstraintVT) const {
9066 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
9067 // 'f' like normal targets.
9068 if (ConstraintVT.isFloatingPoint()) {
9069 if (Subtarget->hasSSE2())
9071 if (Subtarget->hasSSE1())
9075 return TargetLowering::LowerXConstraint(ConstraintVT);
9078 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9079 /// vector. If it is invalid, don't add anything to Ops.
9080 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9083 std::vector<SDValue>&Ops,
9084 SelectionDAG &DAG) const {
9085 SDValue Result(0, 0);
9087 switch (Constraint) {
9090 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9091 if (C->getZExtValue() <= 31) {
9092 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9098 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9099 if (C->getZExtValue() <= 63) {
9100 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9106 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9107 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
9108 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9114 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9115 if (C->getZExtValue() <= 255) {
9116 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9122 // 32-bit signed value
9123 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9124 const ConstantInt *CI = C->getConstantIntValue();
9125 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9126 C->getSExtValue())) {
9127 // Widen to 64 bits here to get it sign extended.
9128 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
9131 // FIXME gcc accepts some relocatable values here too, but only in certain
9132 // memory models; it's complicated.
9137 // 32-bit unsigned value
9138 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
9139 const ConstantInt *CI = C->getConstantIntValue();
9140 if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
9141 C->getZExtValue())) {
9142 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
9146 // FIXME gcc accepts some relocatable values here too, but only in certain
9147 // memory models; it's complicated.
9151 // Literal immediates are always ok.
9152 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
9153 // Widen to 64 bits here to get it sign extended.
9154 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
9158 // If we are in non-pic codegen mode, we allow the address of a global (with
9159 // an optional displacement) to be used with 'i'.
9160 GlobalAddressSDNode *GA = 0;
9163 // Match either (GA), (GA+C), (GA+C1+C2), etc.
9165 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
9166 Offset += GA->getOffset();
9168 } else if (Op.getOpcode() == ISD::ADD) {
9169 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9170 Offset += C->getZExtValue();
9171 Op = Op.getOperand(0);
9174 } else if (Op.getOpcode() == ISD::SUB) {
9175 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
9176 Offset += -C->getZExtValue();
9177 Op = Op.getOperand(0);
9182 // Otherwise, this isn't something we can handle, reject it.
9186 GlobalValue *GV = GA->getGlobal();
9187 // If we require an extra load to get this address, as in PIC mode, we
9189 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
9190 getTargetMachine())))
9194 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
9196 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
9202 if (Result.getNode()) {
9203 Ops.push_back(Result);
9206 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
9210 std::vector<unsigned> X86TargetLowering::
9211 getRegClassForInlineAsmConstraint(const std::string &Constraint,
9213 if (Constraint.size() == 1) {
9214 // FIXME: not handling fp-stack yet!
9215 switch (Constraint[0]) { // GCC X86 Constraint Letters
9216 default: break; // Unknown constraint letter
9217 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
9218 if (Subtarget->is64Bit()) {
9220 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
9221 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
9222 X86::R10D,X86::R11D,X86::R12D,
9223 X86::R13D,X86::R14D,X86::R15D,
9224 X86::EBP, X86::ESP, 0);
9225 else if (VT == MVT::i16)
9226 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
9227 X86::SI, X86::DI, X86::R8W,X86::R9W,
9228 X86::R10W,X86::R11W,X86::R12W,
9229 X86::R13W,X86::R14W,X86::R15W,
9230 X86::BP, X86::SP, 0);
9231 else if (VT == MVT::i8)
9232 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
9233 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
9234 X86::R10B,X86::R11B,X86::R12B,
9235 X86::R13B,X86::R14B,X86::R15B,
9236 X86::BPL, X86::SPL, 0);
9238 else if (VT == MVT::i64)
9239 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
9240 X86::RSI, X86::RDI, X86::R8, X86::R9,
9241 X86::R10, X86::R11, X86::R12,
9242 X86::R13, X86::R14, X86::R15,
9243 X86::RBP, X86::RSP, 0);
9247 // 32-bit fallthrough
9250 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
9251 else if (VT == MVT::i16)
9252 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
9253 else if (VT == MVT::i8)
9254 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
9255 else if (VT == MVT::i64)
9256 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
9261 return std::vector<unsigned>();
9264 std::pair<unsigned, const TargetRegisterClass*>
9265 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9267 // First, see if this is a constraint that directly corresponds to an LLVM
9269 if (Constraint.size() == 1) {
9270 // GCC Constraint Letters
9271 switch (Constraint[0]) {
9273 case 'r': // GENERAL_REGS
9274 case 'R': // LEGACY_REGS
9275 case 'l': // INDEX_REGS
9277 return std::make_pair(0U, X86::GR8RegisterClass);
9279 return std::make_pair(0U, X86::GR16RegisterClass);
9280 if (VT == MVT::i32 || !Subtarget->is64Bit())
9281 return std::make_pair(0U, X86::GR32RegisterClass);
9282 return std::make_pair(0U, X86::GR64RegisterClass);
9283 case 'f': // FP Stack registers.
9284 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
9285 // value to the correct fpstack register class.
9286 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
9287 return std::make_pair(0U, X86::RFP32RegisterClass);
9288 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
9289 return std::make_pair(0U, X86::RFP64RegisterClass);
9290 return std::make_pair(0U, X86::RFP80RegisterClass);
9291 case 'y': // MMX_REGS if MMX allowed.
9292 if (!Subtarget->hasMMX()) break;
9293 return std::make_pair(0U, X86::VR64RegisterClass);
9294 case 'Y': // SSE_REGS if SSE2 allowed
9295 if (!Subtarget->hasSSE2()) break;
9297 case 'x': // SSE_REGS if SSE1 allowed
9298 if (!Subtarget->hasSSE1()) break;
9300 switch (VT.getSimpleVT().SimpleTy) {
9302 // Scalar SSE types.
9305 return std::make_pair(0U, X86::FR32RegisterClass);
9308 return std::make_pair(0U, X86::FR64RegisterClass);
9316 return std::make_pair(0U, X86::VR128RegisterClass);
9322 // Use the default implementation in TargetLowering to convert the register
9323 // constraint into a member of a register class.
9324 std::pair<unsigned, const TargetRegisterClass*> Res;
9325 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9327 // Not found as a standard register?
9328 if (Res.second == 0) {
9329 // GCC calls "st(0)" just plain "st".
9330 if (StringsEqualNoCase("{st}", Constraint)) {
9331 Res.first = X86::ST0;
9332 Res.second = X86::RFP80RegisterClass;
9334 // 'A' means EAX + EDX.
9335 if (Constraint == "A") {
9336 Res.first = X86::EAX;
9337 Res.second = X86::GR32_ADRegisterClass;
9342 // Otherwise, check to see if this is a register class of the wrong value
9343 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
9344 // turn into {ax},{dx}.
9345 if (Res.second->hasType(VT))
9346 return Res; // Correct type already, nothing to do.
9348 // All of the single-register GCC register classes map their values onto
9349 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
9350 // really want an 8-bit or 32-bit register, map to the appropriate register
9351 // class and return the appropriate register.
9352 if (Res.second == X86::GR16RegisterClass) {
9353 if (VT == MVT::i8) {
9354 unsigned DestReg = 0;
9355 switch (Res.first) {
9357 case X86::AX: DestReg = X86::AL; break;
9358 case X86::DX: DestReg = X86::DL; break;
9359 case X86::CX: DestReg = X86::CL; break;
9360 case X86::BX: DestReg = X86::BL; break;
9363 Res.first = DestReg;
9364 Res.second = X86::GR8RegisterClass;
9366 } else if (VT == MVT::i32) {
9367 unsigned DestReg = 0;
9368 switch (Res.first) {
9370 case X86::AX: DestReg = X86::EAX; break;
9371 case X86::DX: DestReg = X86::EDX; break;
9372 case X86::CX: DestReg = X86::ECX; break;
9373 case X86::BX: DestReg = X86::EBX; break;
9374 case X86::SI: DestReg = X86::ESI; break;
9375 case X86::DI: DestReg = X86::EDI; break;
9376 case X86::BP: DestReg = X86::EBP; break;
9377 case X86::SP: DestReg = X86::ESP; break;
9380 Res.first = DestReg;
9381 Res.second = X86::GR32RegisterClass;
9383 } else if (VT == MVT::i64) {
9384 unsigned DestReg = 0;
9385 switch (Res.first) {
9387 case X86::AX: DestReg = X86::RAX; break;
9388 case X86::DX: DestReg = X86::RDX; break;
9389 case X86::CX: DestReg = X86::RCX; break;
9390 case X86::BX: DestReg = X86::RBX; break;
9391 case X86::SI: DestReg = X86::RSI; break;
9392 case X86::DI: DestReg = X86::RDI; break;
9393 case X86::BP: DestReg = X86::RBP; break;
9394 case X86::SP: DestReg = X86::RSP; break;
9397 Res.first = DestReg;
9398 Res.second = X86::GR64RegisterClass;
9401 } else if (Res.second == X86::FR32RegisterClass ||
9402 Res.second == X86::FR64RegisterClass ||
9403 Res.second == X86::VR128RegisterClass) {
9404 // Handle references to XMM physical registers that got mapped into the
9405 // wrong class. This can happen with constraints like {xmm0} where the
9406 // target independent register mapper will just pick the first match it can
9407 // find, ignoring the required type.
9409 Res.second = X86::FR32RegisterClass;
9410 else if (VT == MVT::f64)
9411 Res.second = X86::FR64RegisterClass;
9412 else if (X86::VR128RegisterClass->hasType(VT))
9413 Res.second = X86::VR128RegisterClass;
9419 //===----------------------------------------------------------------------===//
9420 // X86 Widen vector type
9421 //===----------------------------------------------------------------------===//
9423 /// getWidenVectorType: given a vector type, returns the type to widen
9424 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9425 /// If there is no vector type that we want to widen to, returns MVT::Other
9426 /// When and where to widen is target dependent based on the cost of
9427 /// scalarizing vs using the wider vector type.
9429 EVT X86TargetLowering::getWidenVectorType(EVT VT) const {
9430 assert(VT.isVector());
9431 if (isTypeLegal(VT))
9434 // TODO: In computeRegisterProperty, we can compute the list of legal vector
9435 // type based on element type. This would speed up our search (though
9436 // it may not be worth it since the size of the list is relatively
9438 EVT EltVT = VT.getVectorElementType();
9439 unsigned NElts = VT.getVectorNumElements();
9441 // On X86, it make sense to widen any vector wider than 1
9445 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
9446 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9447 EVT SVT = (MVT::SimpleValueType)nVT;
9449 if (isTypeLegal(SVT) &&
9450 SVT.getVectorElementType() == EltVT &&
9451 SVT.getVectorNumElements() > NElts)