1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/Dwarf.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetOptions.h"
55 using namespace dwarf;
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
63 static SDValue Insert128BitVector(SDValue Result,
69 static SDValue Extract128BitVector(SDValue Vec,
74 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
75 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
76 /// simple subregister reference. Idx is an index in the 128 bits we
77 /// want. It need not be aligned to a 128-bit bounday. That makes
78 /// lowering EXTRACT_VECTOR_ELT operations easier.
79 static SDValue Extract128BitVector(SDValue Vec,
83 EVT VT = Vec.getValueType();
84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
85 EVT ElVT = VT.getVectorElementType();
86 int Factor = VT.getSizeInBits()/128;
87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
88 VT.getVectorNumElements()/Factor);
90 // Extract from UNDEF is UNDEF.
91 if (Vec.getOpcode() == ISD::UNDEF)
92 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
94 if (isa<ConstantSDNode>(Idx)) {
95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
98 // we can match to VEXTRACTF128.
99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
101 // This is the index of the first element of the 128-bit chunk
103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
116 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
117 /// sets things up to match to an AVX VINSERTF128 instruction or a
118 /// simple superregister reference. Idx is an index in the 128 bits
119 /// we want. It need not be aligned to a 128-bit bounday. That makes
120 /// lowering INSERT_VECTOR_ELT operations easier.
121 static SDValue Insert128BitVector(SDValue Result,
126 if (isa<ConstantSDNode>(Idx)) {
127 EVT VT = Vec.getValueType();
128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
130 EVT ElVT = VT.getVectorElementType();
131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
132 EVT ResultVT = Result.getValueType();
134 // Insert the relevant 128 bits.
135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
137 // This is the index of the first element of the 128-bit chunk
139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
151 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
153 bool is64Bit = Subtarget->is64Bit();
155 if (Subtarget->isTargetEnvMacho()) {
157 return new X8664_MachoTargetObjectFile();
158 return new TargetLoweringObjectFileMachO();
161 if (Subtarget->isTargetELF())
162 return new TargetLoweringObjectFileELF();
163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
164 return new TargetLoweringObjectFileCOFF();
165 llvm_unreachable("unknown subtarget type");
168 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
169 : TargetLowering(TM, createTLOF(TM)) {
170 Subtarget = &TM.getSubtarget<X86Subtarget>();
171 X86ScalarSSEf64 = Subtarget->hasXMMInt();
172 X86ScalarSSEf32 = Subtarget->hasXMM();
173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
175 RegInfo = TM.getRegisterInfo();
176 TD = getTargetData();
178 // Set up the TargetLowering object.
179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
181 // X86 is weird, it always uses i8 for shift amounts and setcc results.
182 setBooleanContents(ZeroOrOneBooleanContent);
183 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
184 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
186 // For 64-bit since we have so many registers use the ILP scheduler, for
187 // 32-bit code use the register pressure specific scheduling.
188 if (Subtarget->is64Bit())
189 setSchedulingPreference(Sched::ILP);
191 setSchedulingPreference(Sched::RegPressure);
192 setStackPointerRegisterToSaveRestore(X86StackPtr);
194 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
195 // Setup Windows compiler runtime calls.
196 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
197 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
198 setLibcallName(RTLIB::SREM_I64, "_allrem");
199 setLibcallName(RTLIB::UREM_I64, "_aullrem");
200 setLibcallName(RTLIB::MUL_I64, "_allmul");
201 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
202 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
203 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
207 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
208 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
209 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
212 if (Subtarget->isTargetDarwin()) {
213 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
214 setUseUnderscoreSetJmp(false);
215 setUseUnderscoreLongJmp(false);
216 } else if (Subtarget->isTargetMingw()) {
217 // MS runtime is weird: it exports _setjmp, but longjmp!
218 setUseUnderscoreSetJmp(true);
219 setUseUnderscoreLongJmp(false);
221 setUseUnderscoreSetJmp(true);
222 setUseUnderscoreLongJmp(true);
225 // Set up the register classes.
226 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
227 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
228 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
229 if (Subtarget->is64Bit())
230 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
232 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
234 // We don't accept any truncstore of integer registers.
235 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
236 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
237 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
238 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
239 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
240 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
242 // SETOEQ and SETUNE require checking two conditions.
243 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
244 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
245 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
246 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
247 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
248 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
250 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
252 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
253 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
254 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
258 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
259 } else if (!TM.Options.UseSoftFloat) {
260 // We have an algorithm for SSE2->double, and we turn this into a
261 // 64-bit FILD followed by conditional FADD for other targets.
262 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
263 // We have an algorithm for SSE2, and we turn this into a 64-bit
264 // FILD for other targets.
265 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
268 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
270 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
271 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
273 if (!TM.Options.UseSoftFloat) {
274 // SSE has no i16 to fp conversion, only i32
275 if (X86ScalarSSEf32) {
276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
277 // f32 and f64 cases are Legal, f80 case is not
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
280 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
284 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
288 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
289 // are Legal, f80 is custom lowered.
290 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
291 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
293 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
295 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
298 if (X86ScalarSSEf32) {
299 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
300 // f32 and f64 cases are Legal, f80 case is not
301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
303 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
304 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
307 // Handle FP_TO_UINT by promoting the destination to a larger signed
309 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
310 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
311 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
313 if (Subtarget->is64Bit()) {
314 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
316 } else if (!TM.Options.UseSoftFloat) {
317 // Since AVX is a superset of SSE3, only check for SSE here.
318 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
319 // Expand FP_TO_UINT into a select.
320 // FIXME: We would like to use a Custom expander here eventually to do
321 // the optimal thing for SSE vs. the default expansion in the legalizer.
322 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
324 // With SSE3 we can use fisttpll to convert to a signed i64; without
325 // SSE, we're stuck with a fistpll.
326 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
329 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
330 if (!X86ScalarSSEf64) {
331 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
332 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
335 // Without SSE, i64->f64 goes through memory.
336 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
340 // Scalar integer divide and remainder are lowered to use operations that
341 // produce two results, to match the available instructions. This exposes
342 // the two-result form to trivial CSE, which is able to combine x/y and x%y
343 // into a single instruction.
345 // Scalar integer multiply-high is also lowered to use two-result
346 // operations, to match the available instructions. However, plain multiply
347 // (low) operations are left as Legal, as there are single-result
348 // instructions for this in x86. Using the two-result multiply instructions
349 // when both high and low results are needed must be arranged by dagcombine.
350 for (unsigned i = 0, e = 4; i != e; ++i) {
352 setOperationAction(ISD::MULHS, VT, Expand);
353 setOperationAction(ISD::MULHU, VT, Expand);
354 setOperationAction(ISD::SDIV, VT, Expand);
355 setOperationAction(ISD::UDIV, VT, Expand);
356 setOperationAction(ISD::SREM, VT, Expand);
357 setOperationAction(ISD::UREM, VT, Expand);
359 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
360 setOperationAction(ISD::ADDC, VT, Custom);
361 setOperationAction(ISD::ADDE, VT, Custom);
362 setOperationAction(ISD::SUBC, VT, Custom);
363 setOperationAction(ISD::SUBE, VT, Custom);
366 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
367 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
368 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
369 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
370 if (Subtarget->is64Bit())
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
375 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
376 setOperationAction(ISD::FREM , MVT::f32 , Expand);
377 setOperationAction(ISD::FREM , MVT::f64 , Expand);
378 setOperationAction(ISD::FREM , MVT::f80 , Expand);
379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
381 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Expand);
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i16 , Expand);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
384 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i64 , Expand);
385 if (Subtarget->hasBMI()) {
386 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
388 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
389 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
390 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
391 if (Subtarget->is64Bit())
392 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
395 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i8 , Expand);
396 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i16 , Expand);
397 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
398 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i64 , Expand);
399 if (Subtarget->hasLZCNT()) {
400 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
402 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
403 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
404 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
405 if (Subtarget->is64Bit())
406 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
409 if (Subtarget->hasPOPCNT()) {
410 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
412 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
413 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
414 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
415 if (Subtarget->is64Bit())
416 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
419 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
420 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
422 // These should be promoted to a larger select which is supported.
423 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
424 // X86 wants to expand cmov itself.
425 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
426 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
427 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
428 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
429 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
430 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
431 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
432 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
433 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
434 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
435 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
436 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
437 if (Subtarget->is64Bit()) {
438 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
439 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
441 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
444 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
445 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
446 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
447 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
448 if (Subtarget->is64Bit())
449 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
450 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
451 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
452 if (Subtarget->is64Bit()) {
453 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
454 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
455 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
456 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
457 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
459 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
460 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
461 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
462 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
463 if (Subtarget->is64Bit()) {
464 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
465 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
466 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
469 if (Subtarget->hasXMM())
470 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
472 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
473 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
475 // On X86 and X86-64, atomic operations are lowered to locked instructions.
476 // Locked instructions, in turn, have implicit fence semantics (all memory
477 // operations are flushed before issuing the locked instruction, and they
478 // are not buffered), so we can fold away the common pattern of
479 // fence-atomic-fence.
480 setShouldFoldAtomicFences(true);
482 // Expand certain atomics
483 for (unsigned i = 0, e = 4; i != e; ++i) {
485 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
486 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
487 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
490 if (!Subtarget->is64Bit()) {
491 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
492 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
493 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
494 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
495 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
496 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
497 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
498 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
501 if (Subtarget->hasCmpxchg16b()) {
502 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
505 // FIXME - use subtarget debug flags
506 if (!Subtarget->isTargetDarwin() &&
507 !Subtarget->isTargetELF() &&
508 !Subtarget->isTargetCygMing()) {
509 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
512 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
513 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
514 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
515 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
516 if (Subtarget->is64Bit()) {
517 setExceptionPointerRegister(X86::RAX);
518 setExceptionSelectorRegister(X86::RDX);
520 setExceptionPointerRegister(X86::EAX);
521 setExceptionSelectorRegister(X86::EDX);
523 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
524 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
526 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
527 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
529 setOperationAction(ISD::TRAP, MVT::Other, Legal);
531 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
532 setOperationAction(ISD::VASTART , MVT::Other, Custom);
533 setOperationAction(ISD::VAEND , MVT::Other, Expand);
534 if (Subtarget->is64Bit()) {
535 setOperationAction(ISD::VAARG , MVT::Other, Custom);
536 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
538 setOperationAction(ISD::VAARG , MVT::Other, Expand);
539 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
542 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
543 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
545 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
546 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
547 MVT::i64 : MVT::i32, Custom);
548 else if (TM.Options.EnableSegmentedStacks)
549 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
550 MVT::i64 : MVT::i32, Custom);
552 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
553 MVT::i64 : MVT::i32, Expand);
555 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
556 // f32 and f64 use SSE.
557 // Set up the FP register classes.
558 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
559 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
561 // Use ANDPD to simulate FABS.
562 setOperationAction(ISD::FABS , MVT::f64, Custom);
563 setOperationAction(ISD::FABS , MVT::f32, Custom);
565 // Use XORP to simulate FNEG.
566 setOperationAction(ISD::FNEG , MVT::f64, Custom);
567 setOperationAction(ISD::FNEG , MVT::f32, Custom);
569 // Use ANDPD and ORPD to simulate FCOPYSIGN.
570 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
571 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
573 // Lower this to FGETSIGNx86 plus an AND.
574 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
575 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
577 // We don't support sin/cos/fmod
578 setOperationAction(ISD::FSIN , MVT::f64, Expand);
579 setOperationAction(ISD::FCOS , MVT::f64, Expand);
580 setOperationAction(ISD::FSIN , MVT::f32, Expand);
581 setOperationAction(ISD::FCOS , MVT::f32, Expand);
583 // Expand FP immediates into loads from the stack, except for the special
585 addLegalFPImmediate(APFloat(+0.0)); // xorpd
586 addLegalFPImmediate(APFloat(+0.0f)); // xorps
587 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
588 // Use SSE for f32, x87 for f64.
589 // Set up the FP register classes.
590 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
591 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
593 // Use ANDPS to simulate FABS.
594 setOperationAction(ISD::FABS , MVT::f32, Custom);
596 // Use XORP to simulate FNEG.
597 setOperationAction(ISD::FNEG , MVT::f32, Custom);
599 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
601 // Use ANDPS and ORPS to simulate FCOPYSIGN.
602 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
603 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
605 // We don't support sin/cos/fmod
606 setOperationAction(ISD::FSIN , MVT::f32, Expand);
607 setOperationAction(ISD::FCOS , MVT::f32, Expand);
609 // Special cases we handle for FP constants.
610 addLegalFPImmediate(APFloat(+0.0f)); // xorps
611 addLegalFPImmediate(APFloat(+0.0)); // FLD0
612 addLegalFPImmediate(APFloat(+1.0)); // FLD1
613 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
614 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
616 if (!TM.Options.UnsafeFPMath) {
617 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
618 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
620 } else if (!TM.Options.UseSoftFloat) {
621 // f32 and f64 in x87.
622 // Set up the FP register classes.
623 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
624 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
626 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
627 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
628 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
629 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
631 if (!TM.Options.UnsafeFPMath) {
632 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
633 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
635 addLegalFPImmediate(APFloat(+0.0)); // FLD0
636 addLegalFPImmediate(APFloat(+1.0)); // FLD1
637 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
638 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
639 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
640 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
641 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
642 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
645 // We don't support FMA.
646 setOperationAction(ISD::FMA, MVT::f64, Expand);
647 setOperationAction(ISD::FMA, MVT::f32, Expand);
649 // Long double always uses X87.
650 if (!TM.Options.UseSoftFloat) {
651 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
652 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
653 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
655 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
656 addLegalFPImmediate(TmpFlt); // FLD0
658 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
661 APFloat TmpFlt2(+1.0);
662 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
664 addLegalFPImmediate(TmpFlt2); // FLD1
665 TmpFlt2.changeSign();
666 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
669 if (!TM.Options.UnsafeFPMath) {
670 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
671 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
674 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
675 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
676 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
677 setOperationAction(ISD::FRINT, MVT::f80, Expand);
678 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
679 setOperationAction(ISD::FMA, MVT::f80, Expand);
682 // Always use a library call for pow.
683 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
684 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
685 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
687 setOperationAction(ISD::FLOG, MVT::f80, Expand);
688 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
689 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
690 setOperationAction(ISD::FEXP, MVT::f80, Expand);
691 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
693 // First set operation action for all vector types to either promote
694 // (for widening) or expand (for scalarization). Then we will selectively
695 // turn on ones that can be effectively codegen'd.
696 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
697 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
698 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
713 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
715 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
716 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
750 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
755 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
756 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
757 setTruncStoreAction((MVT::SimpleValueType)VT,
758 (MVT::SimpleValueType)InnerVT, Expand);
759 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
760 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
761 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
764 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
765 // with -msoft-float, disable use of MMX as well.
766 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
767 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
768 // No operations on x86mmx supported, everything uses intrinsics.
771 // MMX-sized vectors (other than x86mmx) are expected to be expanded
772 // into smaller operations.
773 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
774 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
775 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
776 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
777 setOperationAction(ISD::AND, MVT::v8i8, Expand);
778 setOperationAction(ISD::AND, MVT::v4i16, Expand);
779 setOperationAction(ISD::AND, MVT::v2i32, Expand);
780 setOperationAction(ISD::AND, MVT::v1i64, Expand);
781 setOperationAction(ISD::OR, MVT::v8i8, Expand);
782 setOperationAction(ISD::OR, MVT::v4i16, Expand);
783 setOperationAction(ISD::OR, MVT::v2i32, Expand);
784 setOperationAction(ISD::OR, MVT::v1i64, Expand);
785 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
786 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
787 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
788 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
789 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
790 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
791 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
792 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
793 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
794 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
795 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
796 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
797 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
798 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
799 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
800 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
801 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
803 if (!TM.Options.UseSoftFloat && Subtarget->hasXMM()) {
804 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
806 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
807 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
808 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
809 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
810 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
811 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
812 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
813 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
814 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
815 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
816 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
817 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
820 if (!TM.Options.UseSoftFloat && Subtarget->hasXMMInt()) {
821 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
823 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
824 // registers cannot be used even for integer operations.
825 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
826 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
827 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
828 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
830 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
831 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
832 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
833 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
834 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
835 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
836 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
837 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
838 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
839 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
840 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
841 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
842 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
843 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
844 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
845 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
847 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
848 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
849 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
850 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
852 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
853 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
854 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
855 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
856 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
858 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
859 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
860 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
861 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
862 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
864 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
865 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
866 EVT VT = (MVT::SimpleValueType)i;
867 // Do not attempt to custom lower non-power-of-2 vectors
868 if (!isPowerOf2_32(VT.getVectorNumElements()))
870 // Do not attempt to custom lower non-128-bit vectors
871 if (!VT.is128BitVector())
873 setOperationAction(ISD::BUILD_VECTOR,
874 VT.getSimpleVT().SimpleTy, Custom);
875 setOperationAction(ISD::VECTOR_SHUFFLE,
876 VT.getSimpleVT().SimpleTy, Custom);
877 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
878 VT.getSimpleVT().SimpleTy, Custom);
881 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
882 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
884 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
885 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
886 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
888 if (Subtarget->is64Bit()) {
889 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
890 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
893 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
894 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
895 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
898 // Do not attempt to promote non-128-bit vectors
899 if (!VT.is128BitVector())
902 setOperationAction(ISD::AND, SVT, Promote);
903 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
904 setOperationAction(ISD::OR, SVT, Promote);
905 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
906 setOperationAction(ISD::XOR, SVT, Promote);
907 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
908 setOperationAction(ISD::LOAD, SVT, Promote);
909 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
910 setOperationAction(ISD::SELECT, SVT, Promote);
911 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
914 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
916 // Custom lower v2i64 and v2f64 selects.
917 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
918 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
919 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
920 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
922 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
926 if (Subtarget->hasSSE41orAVX()) {
927 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
928 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
929 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
930 setOperationAction(ISD::FRINT, MVT::f32, Legal);
931 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
932 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
933 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
934 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
935 setOperationAction(ISD::FRINT, MVT::f64, Legal);
936 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
938 // FIXME: Do we need to handle scalar-to-vector here?
939 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
941 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
942 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
943 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
944 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
945 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
947 // i8 and i16 vectors are custom , because the source register and source
948 // source memory operand types are not the same width. f32 vectors are
949 // custom since the immediate controlling the insert encodes additional
951 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
952 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
953 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
954 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
957 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
958 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
959 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
961 // FIXME: these should be Legal but thats only for the case where
962 // the index is constant. For now custom expand to deal with that
963 if (Subtarget->is64Bit()) {
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
969 if (Subtarget->hasXMMInt()) {
970 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
971 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
973 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
974 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
976 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
977 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
979 if (Subtarget->hasAVX2()) {
980 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
981 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
983 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
984 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
986 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
988 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
989 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
991 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
992 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
994 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
998 if (Subtarget->hasSSE42orAVX())
999 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1001 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1002 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1003 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1004 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1005 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1006 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1007 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1009 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1010 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1011 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1013 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1014 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1015 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1016 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1017 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1018 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1020 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1021 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1022 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1023 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1024 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1025 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1027 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1028 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1029 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1031 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1032 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1033 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1034 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1035 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1036 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1038 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1039 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1041 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1042 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1044 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1045 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1047 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1048 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1049 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1050 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1052 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1053 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1054 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1056 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1057 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1058 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1059 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1061 if (Subtarget->hasAVX2()) {
1062 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1063 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1064 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1065 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1067 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1068 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1069 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1070 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1072 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1073 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1074 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1075 // Don't lower v32i8 because there is no 128-bit byte mul
1077 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1079 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1080 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1082 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1083 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1085 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1087 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1088 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1089 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1090 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1092 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1093 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1094 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1095 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1097 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1098 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1099 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1100 // Don't lower v32i8 because there is no 128-bit byte mul
1102 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1103 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1105 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1108 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1111 // Custom lower several nodes for 256-bit types.
1112 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1113 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1114 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1117 // Extract subvector is special because the value type
1118 // (result) is 128-bit but the source is 256-bit wide.
1119 if (VT.is128BitVector())
1120 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1122 // Do not attempt to custom lower other non-256-bit vectors
1123 if (!VT.is256BitVector())
1126 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1127 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1128 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1129 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1130 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1131 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1134 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1135 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1136 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1139 // Do not attempt to promote non-256-bit vectors
1140 if (!VT.is256BitVector())
1143 setOperationAction(ISD::AND, SVT, Promote);
1144 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1145 setOperationAction(ISD::OR, SVT, Promote);
1146 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1147 setOperationAction(ISD::XOR, SVT, Promote);
1148 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1149 setOperationAction(ISD::LOAD, SVT, Promote);
1150 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1151 setOperationAction(ISD::SELECT, SVT, Promote);
1152 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1156 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1157 // of this type with custom code.
1158 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1159 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1160 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1163 // We want to custom lower some of our intrinsics.
1164 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1167 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1168 // handle type legalization for these operations here.
1170 // FIXME: We really should do custom legalization for addition and
1171 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1172 // than generic legalization for 64-bit multiplication-with-overflow, though.
1173 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1174 // Add/Sub/Mul with overflow operations are custom lowered.
1176 setOperationAction(ISD::SADDO, VT, Custom);
1177 setOperationAction(ISD::UADDO, VT, Custom);
1178 setOperationAction(ISD::SSUBO, VT, Custom);
1179 setOperationAction(ISD::USUBO, VT, Custom);
1180 setOperationAction(ISD::SMULO, VT, Custom);
1181 setOperationAction(ISD::UMULO, VT, Custom);
1184 // There are no 8-bit 3-address imul/mul instructions
1185 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1186 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1188 if (!Subtarget->is64Bit()) {
1189 // These libcalls are not available in 32-bit.
1190 setLibcallName(RTLIB::SHL_I128, 0);
1191 setLibcallName(RTLIB::SRL_I128, 0);
1192 setLibcallName(RTLIB::SRA_I128, 0);
1195 // We have target-specific dag combine patterns for the following nodes:
1196 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1197 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1198 setTargetDAGCombine(ISD::BUILD_VECTOR);
1199 setTargetDAGCombine(ISD::VSELECT);
1200 setTargetDAGCombine(ISD::SELECT);
1201 setTargetDAGCombine(ISD::SHL);
1202 setTargetDAGCombine(ISD::SRA);
1203 setTargetDAGCombine(ISD::SRL);
1204 setTargetDAGCombine(ISD::OR);
1205 setTargetDAGCombine(ISD::AND);
1206 setTargetDAGCombine(ISD::ADD);
1207 setTargetDAGCombine(ISD::FADD);
1208 setTargetDAGCombine(ISD::FSUB);
1209 setTargetDAGCombine(ISD::SUB);
1210 setTargetDAGCombine(ISD::LOAD);
1211 setTargetDAGCombine(ISD::STORE);
1212 setTargetDAGCombine(ISD::ZERO_EXTEND);
1213 setTargetDAGCombine(ISD::SINT_TO_FP);
1214 if (Subtarget->is64Bit())
1215 setTargetDAGCombine(ISD::MUL);
1216 if (Subtarget->hasBMI())
1217 setTargetDAGCombine(ISD::XOR);
1219 computeRegisterProperties();
1221 // On Darwin, -Os means optimize for size without hurting performance,
1222 // do not reduce the limit.
1223 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1224 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1225 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1226 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1227 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1228 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1229 setPrefLoopAlignment(4); // 2^4 bytes.
1230 benefitFromCodePlacementOpt = true;
1232 setPrefFunctionAlignment(4); // 2^4 bytes.
1236 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1237 if (!VT.isVector()) return MVT::i8;
1238 return VT.changeVectorElementTypeToInteger();
1242 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1243 /// the desired ByVal argument alignment.
1244 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1247 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1248 if (VTy->getBitWidth() == 128)
1250 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1251 unsigned EltAlign = 0;
1252 getMaxByValAlign(ATy->getElementType(), EltAlign);
1253 if (EltAlign > MaxAlign)
1254 MaxAlign = EltAlign;
1255 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1256 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1257 unsigned EltAlign = 0;
1258 getMaxByValAlign(STy->getElementType(i), EltAlign);
1259 if (EltAlign > MaxAlign)
1260 MaxAlign = EltAlign;
1268 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1269 /// function arguments in the caller parameter area. For X86, aggregates
1270 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1271 /// are at 4-byte boundaries.
1272 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1273 if (Subtarget->is64Bit()) {
1274 // Max of 8 and alignment of type.
1275 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1282 if (Subtarget->hasXMM())
1283 getMaxByValAlign(Ty, Align);
1287 /// getOptimalMemOpType - Returns the target specific optimal type for load
1288 /// and store operations as a result of memset, memcpy, and memmove
1289 /// lowering. If DstAlign is zero that means it's safe to destination
1290 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1291 /// means there isn't a need to check it against alignment requirement,
1292 /// probably because the source does not need to be loaded. If
1293 /// 'IsZeroVal' is true, that means it's safe to return a
1294 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1295 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1296 /// constant so it does not need to be loaded.
1297 /// It returns EVT::Other if the type should be determined using generic
1298 /// target-independent logic.
1300 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1301 unsigned DstAlign, unsigned SrcAlign,
1304 MachineFunction &MF) const {
1305 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1306 // linux. This is because the stack realignment code can't handle certain
1307 // cases like PR2962. This should be removed when PR2962 is fixed.
1308 const Function *F = MF.getFunction();
1310 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1312 (Subtarget->isUnalignedMemAccessFast() ||
1313 ((DstAlign == 0 || DstAlign >= 16) &&
1314 (SrcAlign == 0 || SrcAlign >= 16))) &&
1315 Subtarget->getStackAlignment() >= 16) {
1316 if (Subtarget->hasAVX() &&
1317 Subtarget->getStackAlignment() >= 32)
1319 if (Subtarget->hasXMMInt())
1321 if (Subtarget->hasXMM())
1323 } else if (!MemcpyStrSrc && Size >= 8 &&
1324 !Subtarget->is64Bit() &&
1325 Subtarget->getStackAlignment() >= 8 &&
1326 Subtarget->hasXMMInt()) {
1327 // Do not use f64 to lower memcpy if source is string constant. It's
1328 // better to use i32 to avoid the loads.
1332 if (Subtarget->is64Bit() && Size >= 8)
1337 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1338 /// current function. The returned value is a member of the
1339 /// MachineJumpTableInfo::JTEntryKind enum.
1340 unsigned X86TargetLowering::getJumpTableEncoding() const {
1341 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1343 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1344 Subtarget->isPICStyleGOT())
1345 return MachineJumpTableInfo::EK_Custom32;
1347 // Otherwise, use the normal jump table encoding heuristics.
1348 return TargetLowering::getJumpTableEncoding();
1352 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1353 const MachineBasicBlock *MBB,
1354 unsigned uid,MCContext &Ctx) const{
1355 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1356 Subtarget->isPICStyleGOT());
1357 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1359 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1360 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1363 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1365 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1366 SelectionDAG &DAG) const {
1367 if (!Subtarget->is64Bit())
1368 // This doesn't have DebugLoc associated with it, but is not really the
1369 // same as a Register.
1370 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1374 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1375 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1377 const MCExpr *X86TargetLowering::
1378 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1379 MCContext &Ctx) const {
1380 // X86-64 uses RIP relative addressing based on the jump table label.
1381 if (Subtarget->isPICStyleRIPRel())
1382 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1384 // Otherwise, the reference is relative to the PIC base.
1385 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1388 // FIXME: Why this routine is here? Move to RegInfo!
1389 std::pair<const TargetRegisterClass*, uint8_t>
1390 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1391 const TargetRegisterClass *RRC = 0;
1393 switch (VT.getSimpleVT().SimpleTy) {
1395 return TargetLowering::findRepresentativeClass(VT);
1396 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1397 RRC = (Subtarget->is64Bit()
1398 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1401 RRC = X86::VR64RegisterClass;
1403 case MVT::f32: case MVT::f64:
1404 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1405 case MVT::v4f32: case MVT::v2f64:
1406 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1408 RRC = X86::VR128RegisterClass;
1411 return std::make_pair(RRC, Cost);
1414 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1415 unsigned &Offset) const {
1416 if (!Subtarget->isTargetLinux())
1419 if (Subtarget->is64Bit()) {
1420 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1422 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1435 //===----------------------------------------------------------------------===//
1436 // Return Value Calling Convention Implementation
1437 //===----------------------------------------------------------------------===//
1439 #include "X86GenCallingConv.inc"
1442 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1443 MachineFunction &MF, bool isVarArg,
1444 const SmallVectorImpl<ISD::OutputArg> &Outs,
1445 LLVMContext &Context) const {
1446 SmallVector<CCValAssign, 16> RVLocs;
1447 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1449 return CCInfo.CheckReturn(Outs, RetCC_X86);
1453 X86TargetLowering::LowerReturn(SDValue Chain,
1454 CallingConv::ID CallConv, bool isVarArg,
1455 const SmallVectorImpl<ISD::OutputArg> &Outs,
1456 const SmallVectorImpl<SDValue> &OutVals,
1457 DebugLoc dl, SelectionDAG &DAG) const {
1458 MachineFunction &MF = DAG.getMachineFunction();
1459 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1461 SmallVector<CCValAssign, 16> RVLocs;
1462 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1463 RVLocs, *DAG.getContext());
1464 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1466 // Add the regs to the liveout set for the function.
1467 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1468 for (unsigned i = 0; i != RVLocs.size(); ++i)
1469 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1470 MRI.addLiveOut(RVLocs[i].getLocReg());
1474 SmallVector<SDValue, 6> RetOps;
1475 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1476 // Operand #1 = Bytes To Pop
1477 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1480 // Copy the result values into the output registers.
1481 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1482 CCValAssign &VA = RVLocs[i];
1483 assert(VA.isRegLoc() && "Can only return in registers!");
1484 SDValue ValToCopy = OutVals[i];
1485 EVT ValVT = ValToCopy.getValueType();
1487 // If this is x86-64, and we disabled SSE, we can't return FP values,
1488 // or SSE or MMX vectors.
1489 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1490 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1491 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1492 report_fatal_error("SSE register return with SSE disabled");
1494 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1495 // llvm-gcc has never done it right and no one has noticed, so this
1496 // should be OK for now.
1497 if (ValVT == MVT::f64 &&
1498 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1499 report_fatal_error("SSE2 register return with SSE2 disabled");
1501 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1502 // the RET instruction and handled by the FP Stackifier.
1503 if (VA.getLocReg() == X86::ST0 ||
1504 VA.getLocReg() == X86::ST1) {
1505 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1506 // change the value to the FP stack register class.
1507 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1508 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1509 RetOps.push_back(ValToCopy);
1510 // Don't emit a copytoreg.
1514 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1515 // which is returned in RAX / RDX.
1516 if (Subtarget->is64Bit()) {
1517 if (ValVT == MVT::x86mmx) {
1518 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1519 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1520 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1522 // If we don't have SSE2 available, convert to v4f32 so the generated
1523 // register is legal.
1524 if (!Subtarget->hasXMMInt())
1525 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1530 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1531 Flag = Chain.getValue(1);
1534 // The x86-64 ABI for returning structs by value requires that we copy
1535 // the sret argument into %rax for the return. We saved the argument into
1536 // a virtual register in the entry block, so now we copy the value out
1538 if (Subtarget->is64Bit() &&
1539 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1540 MachineFunction &MF = DAG.getMachineFunction();
1541 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1542 unsigned Reg = FuncInfo->getSRetReturnReg();
1544 "SRetReturnReg should have been set in LowerFormalArguments().");
1545 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1547 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1548 Flag = Chain.getValue(1);
1550 // RAX now acts like a return value.
1551 MRI.addLiveOut(X86::RAX);
1554 RetOps[0] = Chain; // Update chain.
1556 // Add the flag if we have it.
1558 RetOps.push_back(Flag);
1560 return DAG.getNode(X86ISD::RET_FLAG, dl,
1561 MVT::Other, &RetOps[0], RetOps.size());
1564 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1565 if (N->getNumValues() != 1)
1567 if (!N->hasNUsesOfValue(1, 0))
1570 SDNode *Copy = *N->use_begin();
1571 if (Copy->getOpcode() != ISD::CopyToReg &&
1572 Copy->getOpcode() != ISD::FP_EXTEND)
1575 bool HasRet = false;
1576 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1578 if (UI->getOpcode() != X86ISD::RET_FLAG)
1587 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1588 ISD::NodeType ExtendKind) const {
1590 // TODO: Is this also valid on 32-bit?
1591 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1592 ReturnMVT = MVT::i8;
1594 ReturnMVT = MVT::i32;
1596 EVT MinVT = getRegisterType(Context, ReturnMVT);
1597 return VT.bitsLT(MinVT) ? MinVT : VT;
1600 /// LowerCallResult - Lower the result values of a call into the
1601 /// appropriate copies out of appropriate physical registers.
1604 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1605 CallingConv::ID CallConv, bool isVarArg,
1606 const SmallVectorImpl<ISD::InputArg> &Ins,
1607 DebugLoc dl, SelectionDAG &DAG,
1608 SmallVectorImpl<SDValue> &InVals) const {
1610 // Assign locations to each value returned by this call.
1611 SmallVector<CCValAssign, 16> RVLocs;
1612 bool Is64Bit = Subtarget->is64Bit();
1613 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1614 getTargetMachine(), RVLocs, *DAG.getContext());
1615 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1617 // Copy all of the result registers out of their specified physreg.
1618 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1619 CCValAssign &VA = RVLocs[i];
1620 EVT CopyVT = VA.getValVT();
1622 // If this is x86-64, and we disabled SSE, we can't return FP values
1623 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1624 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1625 report_fatal_error("SSE register return with SSE disabled");
1630 // If this is a call to a function that returns an fp value on the floating
1631 // point stack, we must guarantee the the value is popped from the stack, so
1632 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1633 // if the return value is not used. We use the FpPOP_RETVAL instruction
1635 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1636 // If we prefer to use the value in xmm registers, copy it out as f80 and
1637 // use a truncate to move it from fp stack reg to xmm reg.
1638 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1639 SDValue Ops[] = { Chain, InFlag };
1640 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1641 MVT::Other, MVT::Glue, Ops, 2), 1);
1642 Val = Chain.getValue(0);
1644 // Round the f80 to the right size, which also moves it to the appropriate
1646 if (CopyVT != VA.getValVT())
1647 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1648 // This truncation won't change the value.
1649 DAG.getIntPtrConstant(1));
1651 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1652 CopyVT, InFlag).getValue(1);
1653 Val = Chain.getValue(0);
1655 InFlag = Chain.getValue(2);
1656 InVals.push_back(Val);
1663 //===----------------------------------------------------------------------===//
1664 // C & StdCall & Fast Calling Convention implementation
1665 //===----------------------------------------------------------------------===//
1666 // StdCall calling convention seems to be standard for many Windows' API
1667 // routines and around. It differs from C calling convention just a little:
1668 // callee should clean up the stack, not caller. Symbols should be also
1669 // decorated in some fancy way :) It doesn't support any vector arguments.
1670 // For info on fast calling convention see Fast Calling Convention (tail call)
1671 // implementation LowerX86_32FastCCCallTo.
1673 /// CallIsStructReturn - Determines whether a call uses struct return
1675 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1679 return Outs[0].Flags.isSRet();
1682 /// ArgsAreStructReturn - Determines whether a function uses struct
1683 /// return semantics.
1685 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1689 return Ins[0].Flags.isSRet();
1692 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1693 /// by "Src" to address "Dst" with size and alignment information specified by
1694 /// the specific parameter attribute. The copy will be passed as a byval
1695 /// function parameter.
1697 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1698 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1700 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1702 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1703 /*isVolatile*/false, /*AlwaysInline=*/true,
1704 MachinePointerInfo(), MachinePointerInfo());
1707 /// IsTailCallConvention - Return true if the calling convention is one that
1708 /// supports tail call optimization.
1709 static bool IsTailCallConvention(CallingConv::ID CC) {
1710 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1713 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1714 if (!CI->isTailCall())
1718 CallingConv::ID CalleeCC = CS.getCallingConv();
1719 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1725 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1726 /// a tailcall target by changing its ABI.
1727 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1728 bool GuaranteedTailCallOpt) {
1729 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1733 X86TargetLowering::LowerMemArgument(SDValue Chain,
1734 CallingConv::ID CallConv,
1735 const SmallVectorImpl<ISD::InputArg> &Ins,
1736 DebugLoc dl, SelectionDAG &DAG,
1737 const CCValAssign &VA,
1738 MachineFrameInfo *MFI,
1740 // Create the nodes corresponding to a load from this parameter slot.
1741 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1742 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1743 getTargetMachine().Options.GuaranteedTailCallOpt);
1744 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1747 // If value is passed by pointer we have address passed instead of the value
1749 if (VA.getLocInfo() == CCValAssign::Indirect)
1750 ValVT = VA.getLocVT();
1752 ValVT = VA.getValVT();
1754 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1755 // changed with more analysis.
1756 // In case of tail call optimization mark all arguments mutable. Since they
1757 // could be overwritten by lowering of arguments in case of a tail call.
1758 if (Flags.isByVal()) {
1759 unsigned Bytes = Flags.getByValSize();
1760 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1761 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1762 return DAG.getFrameIndex(FI, getPointerTy());
1764 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1765 VA.getLocMemOffset(), isImmutable);
1766 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1767 return DAG.getLoad(ValVT, dl, Chain, FIN,
1768 MachinePointerInfo::getFixedStack(FI),
1769 false, false, false, 0);
1774 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1775 CallingConv::ID CallConv,
1777 const SmallVectorImpl<ISD::InputArg> &Ins,
1780 SmallVectorImpl<SDValue> &InVals)
1782 MachineFunction &MF = DAG.getMachineFunction();
1783 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1785 const Function* Fn = MF.getFunction();
1786 if (Fn->hasExternalLinkage() &&
1787 Subtarget->isTargetCygMing() &&
1788 Fn->getName() == "main")
1789 FuncInfo->setForceFramePointer(true);
1791 MachineFrameInfo *MFI = MF.getFrameInfo();
1792 bool Is64Bit = Subtarget->is64Bit();
1793 bool IsWin64 = Subtarget->isTargetWin64();
1795 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1796 "Var args not supported with calling convention fastcc or ghc");
1798 // Assign locations to all of the incoming arguments.
1799 SmallVector<CCValAssign, 16> ArgLocs;
1800 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1801 ArgLocs, *DAG.getContext());
1803 // Allocate shadow area for Win64
1805 CCInfo.AllocateStack(32, 8);
1808 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1810 unsigned LastVal = ~0U;
1812 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1813 CCValAssign &VA = ArgLocs[i];
1814 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1816 assert(VA.getValNo() != LastVal &&
1817 "Don't support value assigned to multiple locs yet");
1819 LastVal = VA.getValNo();
1821 if (VA.isRegLoc()) {
1822 EVT RegVT = VA.getLocVT();
1823 TargetRegisterClass *RC = NULL;
1824 if (RegVT == MVT::i32)
1825 RC = X86::GR32RegisterClass;
1826 else if (Is64Bit && RegVT == MVT::i64)
1827 RC = X86::GR64RegisterClass;
1828 else if (RegVT == MVT::f32)
1829 RC = X86::FR32RegisterClass;
1830 else if (RegVT == MVT::f64)
1831 RC = X86::FR64RegisterClass;
1832 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1833 RC = X86::VR256RegisterClass;
1834 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1835 RC = X86::VR128RegisterClass;
1836 else if (RegVT == MVT::x86mmx)
1837 RC = X86::VR64RegisterClass;
1839 llvm_unreachable("Unknown argument type!");
1841 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1842 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1844 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1845 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1847 if (VA.getLocInfo() == CCValAssign::SExt)
1848 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1849 DAG.getValueType(VA.getValVT()));
1850 else if (VA.getLocInfo() == CCValAssign::ZExt)
1851 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1852 DAG.getValueType(VA.getValVT()));
1853 else if (VA.getLocInfo() == CCValAssign::BCvt)
1854 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1856 if (VA.isExtInLoc()) {
1857 // Handle MMX values passed in XMM regs.
1858 if (RegVT.isVector()) {
1859 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1862 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1865 assert(VA.isMemLoc());
1866 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1869 // If value is passed via pointer - do a load.
1870 if (VA.getLocInfo() == CCValAssign::Indirect)
1871 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1872 MachinePointerInfo(), false, false, false, 0);
1874 InVals.push_back(ArgValue);
1877 // The x86-64 ABI for returning structs by value requires that we copy
1878 // the sret argument into %rax for the return. Save the argument into
1879 // a virtual register so that we can access it from the return points.
1880 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1881 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1882 unsigned Reg = FuncInfo->getSRetReturnReg();
1884 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1885 FuncInfo->setSRetReturnReg(Reg);
1887 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1888 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1891 unsigned StackSize = CCInfo.getNextStackOffset();
1892 // Align stack specially for tail calls.
1893 if (FuncIsMadeTailCallSafe(CallConv,
1894 MF.getTarget().Options.GuaranteedTailCallOpt))
1895 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1897 // If the function takes variable number of arguments, make a frame index for
1898 // the start of the first vararg value... for expansion of llvm.va_start.
1900 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1901 CallConv != CallingConv::X86_ThisCall)) {
1902 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1905 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1907 // FIXME: We should really autogenerate these arrays
1908 static const unsigned GPR64ArgRegsWin64[] = {
1909 X86::RCX, X86::RDX, X86::R8, X86::R9
1911 static const unsigned GPR64ArgRegs64Bit[] = {
1912 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1914 static const unsigned XMMArgRegs64Bit[] = {
1915 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1916 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1918 const unsigned *GPR64ArgRegs;
1919 unsigned NumXMMRegs = 0;
1922 // The XMM registers which might contain var arg parameters are shadowed
1923 // in their paired GPR. So we only need to save the GPR to their home
1925 TotalNumIntRegs = 4;
1926 GPR64ArgRegs = GPR64ArgRegsWin64;
1928 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1929 GPR64ArgRegs = GPR64ArgRegs64Bit;
1931 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1933 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1936 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1937 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1938 "SSE register cannot be used when SSE is disabled!");
1939 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1940 NoImplicitFloatOps) &&
1941 "SSE register cannot be used when SSE is disabled!");
1942 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1943 !Subtarget->hasXMM())
1944 // Kernel mode asks for SSE to be disabled, so don't push them
1946 TotalNumXMMRegs = 0;
1949 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1950 // Get to the caller-allocated home save location. Add 8 to account
1951 // for the return address.
1952 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1953 FuncInfo->setRegSaveFrameIndex(
1954 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1955 // Fixup to set vararg frame on shadow area (4 x i64).
1957 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1959 // For X86-64, if there are vararg parameters that are passed via
1960 // registers, then we must store them to their spots on the stack so they
1961 // may be loaded by deferencing the result of va_next.
1962 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1963 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1964 FuncInfo->setRegSaveFrameIndex(
1965 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1969 // Store the integer parameter registers.
1970 SmallVector<SDValue, 8> MemOps;
1971 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1973 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1974 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1975 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1976 DAG.getIntPtrConstant(Offset));
1977 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1978 X86::GR64RegisterClass);
1979 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1981 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1982 MachinePointerInfo::getFixedStack(
1983 FuncInfo->getRegSaveFrameIndex(), Offset),
1985 MemOps.push_back(Store);
1989 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1990 // Now store the XMM (fp + vector) parameter registers.
1991 SmallVector<SDValue, 11> SaveXMMOps;
1992 SaveXMMOps.push_back(Chain);
1994 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1995 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1996 SaveXMMOps.push_back(ALVal);
1998 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1999 FuncInfo->getRegSaveFrameIndex()));
2000 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2001 FuncInfo->getVarArgsFPOffset()));
2003 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2004 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2005 X86::VR128RegisterClass);
2006 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2007 SaveXMMOps.push_back(Val);
2009 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2011 &SaveXMMOps[0], SaveXMMOps.size()));
2014 if (!MemOps.empty())
2015 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2016 &MemOps[0], MemOps.size());
2020 // Some CCs need callee pop.
2021 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2022 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2023 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2025 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2026 // If this is an sret function, the return should pop the hidden pointer.
2027 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
2028 FuncInfo->setBytesToPopOnReturn(4);
2032 // RegSaveFrameIndex is X86-64 only.
2033 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2034 if (CallConv == CallingConv::X86_FastCall ||
2035 CallConv == CallingConv::X86_ThisCall)
2036 // fastcc functions can't have varargs.
2037 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2040 FuncInfo->setArgumentStackSize(StackSize);
2046 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2047 SDValue StackPtr, SDValue Arg,
2048 DebugLoc dl, SelectionDAG &DAG,
2049 const CCValAssign &VA,
2050 ISD::ArgFlagsTy Flags) const {
2051 unsigned LocMemOffset = VA.getLocMemOffset();
2052 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2053 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2054 if (Flags.isByVal())
2055 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2057 return DAG.getStore(Chain, dl, Arg, PtrOff,
2058 MachinePointerInfo::getStack(LocMemOffset),
2062 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2063 /// optimization is performed and it is required.
2065 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2066 SDValue &OutRetAddr, SDValue Chain,
2067 bool IsTailCall, bool Is64Bit,
2068 int FPDiff, DebugLoc dl) const {
2069 // Adjust the Return address stack slot.
2070 EVT VT = getPointerTy();
2071 OutRetAddr = getReturnAddressFrameIndex(DAG);
2073 // Load the "old" Return address.
2074 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2075 false, false, false, 0);
2076 return SDValue(OutRetAddr.getNode(), 1);
2079 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2080 /// optimization is performed and it is required (FPDiff!=0).
2082 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2083 SDValue Chain, SDValue RetAddrFrIdx,
2084 bool Is64Bit, int FPDiff, DebugLoc dl) {
2085 // Store the return address to the appropriate stack slot.
2086 if (!FPDiff) return Chain;
2087 // Calculate the new stack slot for the return address.
2088 int SlotSize = Is64Bit ? 8 : 4;
2089 int NewReturnAddrFI =
2090 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2091 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2092 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2093 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2094 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2100 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2101 CallingConv::ID CallConv, bool isVarArg,
2103 const SmallVectorImpl<ISD::OutputArg> &Outs,
2104 const SmallVectorImpl<SDValue> &OutVals,
2105 const SmallVectorImpl<ISD::InputArg> &Ins,
2106 DebugLoc dl, SelectionDAG &DAG,
2107 SmallVectorImpl<SDValue> &InVals) const {
2108 MachineFunction &MF = DAG.getMachineFunction();
2109 bool Is64Bit = Subtarget->is64Bit();
2110 bool IsWin64 = Subtarget->isTargetWin64();
2111 bool IsStructRet = CallIsStructReturn(Outs);
2112 bool IsSibcall = false;
2115 // Check if it's really possible to do a tail call.
2116 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2117 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2118 Outs, OutVals, Ins, DAG);
2120 // Sibcalls are automatically detected tailcalls which do not require
2122 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2129 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2130 "Var args not supported with calling convention fastcc or ghc");
2132 // Analyze operands of the call, assigning locations to each operand.
2133 SmallVector<CCValAssign, 16> ArgLocs;
2134 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2135 ArgLocs, *DAG.getContext());
2137 // Allocate shadow area for Win64
2139 CCInfo.AllocateStack(32, 8);
2142 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2144 // Get a count of how many bytes are to be pushed on the stack.
2145 unsigned NumBytes = CCInfo.getNextStackOffset();
2147 // This is a sibcall. The memory operands are available in caller's
2148 // own caller's stack.
2150 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2151 IsTailCallConvention(CallConv))
2152 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2155 if (isTailCall && !IsSibcall) {
2156 // Lower arguments at fp - stackoffset + fpdiff.
2157 unsigned NumBytesCallerPushed =
2158 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2159 FPDiff = NumBytesCallerPushed - NumBytes;
2161 // Set the delta of movement of the returnaddr stackslot.
2162 // But only set if delta is greater than previous delta.
2163 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2164 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2168 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2170 SDValue RetAddrFrIdx;
2171 // Load return address for tail calls.
2172 if (isTailCall && FPDiff)
2173 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2174 Is64Bit, FPDiff, dl);
2176 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2177 SmallVector<SDValue, 8> MemOpChains;
2180 // Walk the register/memloc assignments, inserting copies/loads. In the case
2181 // of tail call optimization arguments are handle later.
2182 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2183 CCValAssign &VA = ArgLocs[i];
2184 EVT RegVT = VA.getLocVT();
2185 SDValue Arg = OutVals[i];
2186 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2187 bool isByVal = Flags.isByVal();
2189 // Promote the value if needed.
2190 switch (VA.getLocInfo()) {
2191 default: llvm_unreachable("Unknown loc info!");
2192 case CCValAssign::Full: break;
2193 case CCValAssign::SExt:
2194 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2196 case CCValAssign::ZExt:
2197 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2199 case CCValAssign::AExt:
2200 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2201 // Special case: passing MMX values in XMM registers.
2202 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2203 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2204 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2206 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2208 case CCValAssign::BCvt:
2209 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2211 case CCValAssign::Indirect: {
2212 // Store the argument.
2213 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2214 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2215 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2216 MachinePointerInfo::getFixedStack(FI),
2223 if (VA.isRegLoc()) {
2224 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2225 if (isVarArg && IsWin64) {
2226 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2227 // shadow reg if callee is a varargs function.
2228 unsigned ShadowReg = 0;
2229 switch (VA.getLocReg()) {
2230 case X86::XMM0: ShadowReg = X86::RCX; break;
2231 case X86::XMM1: ShadowReg = X86::RDX; break;
2232 case X86::XMM2: ShadowReg = X86::R8; break;
2233 case X86::XMM3: ShadowReg = X86::R9; break;
2236 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2238 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2239 assert(VA.isMemLoc());
2240 if (StackPtr.getNode() == 0)
2241 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2242 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2243 dl, DAG, VA, Flags));
2247 if (!MemOpChains.empty())
2248 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2249 &MemOpChains[0], MemOpChains.size());
2251 // Build a sequence of copy-to-reg nodes chained together with token chain
2252 // and flag operands which copy the outgoing args into registers.
2254 // Tail call byval lowering might overwrite argument registers so in case of
2255 // tail call optimization the copies to registers are lowered later.
2257 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2258 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2259 RegsToPass[i].second, InFlag);
2260 InFlag = Chain.getValue(1);
2263 if (Subtarget->isPICStyleGOT()) {
2264 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2267 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2268 DAG.getNode(X86ISD::GlobalBaseReg,
2269 DebugLoc(), getPointerTy()),
2271 InFlag = Chain.getValue(1);
2273 // If we are tail calling and generating PIC/GOT style code load the
2274 // address of the callee into ECX. The value in ecx is used as target of
2275 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2276 // for tail calls on PIC/GOT architectures. Normally we would just put the
2277 // address of GOT into ebx and then call target@PLT. But for tail calls
2278 // ebx would be restored (since ebx is callee saved) before jumping to the
2281 // Note: The actual moving to ECX is done further down.
2282 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2283 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2284 !G->getGlobal()->hasProtectedVisibility())
2285 Callee = LowerGlobalAddress(Callee, DAG);
2286 else if (isa<ExternalSymbolSDNode>(Callee))
2287 Callee = LowerExternalSymbol(Callee, DAG);
2291 if (Is64Bit && isVarArg && !IsWin64) {
2292 // From AMD64 ABI document:
2293 // For calls that may call functions that use varargs or stdargs
2294 // (prototype-less calls or calls to functions containing ellipsis (...) in
2295 // the declaration) %al is used as hidden argument to specify the number
2296 // of SSE registers used. The contents of %al do not need to match exactly
2297 // the number of registers, but must be an ubound on the number of SSE
2298 // registers used and is in the range 0 - 8 inclusive.
2300 // Count the number of XMM registers allocated.
2301 static const unsigned XMMArgRegs[] = {
2302 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2303 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2305 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2306 assert((Subtarget->hasXMM() || !NumXMMRegs)
2307 && "SSE registers cannot be used when SSE is disabled");
2309 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2310 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2311 InFlag = Chain.getValue(1);
2315 // For tail calls lower the arguments to the 'real' stack slot.
2317 // Force all the incoming stack arguments to be loaded from the stack
2318 // before any new outgoing arguments are stored to the stack, because the
2319 // outgoing stack slots may alias the incoming argument stack slots, and
2320 // the alias isn't otherwise explicit. This is slightly more conservative
2321 // than necessary, because it means that each store effectively depends
2322 // on every argument instead of just those arguments it would clobber.
2323 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2325 SmallVector<SDValue, 8> MemOpChains2;
2328 // Do not flag preceding copytoreg stuff together with the following stuff.
2330 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2331 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2332 CCValAssign &VA = ArgLocs[i];
2335 assert(VA.isMemLoc());
2336 SDValue Arg = OutVals[i];
2337 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2338 // Create frame index.
2339 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2340 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2341 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2342 FIN = DAG.getFrameIndex(FI, getPointerTy());
2344 if (Flags.isByVal()) {
2345 // Copy relative to framepointer.
2346 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2347 if (StackPtr.getNode() == 0)
2348 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2350 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2352 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2356 // Store relative to framepointer.
2357 MemOpChains2.push_back(
2358 DAG.getStore(ArgChain, dl, Arg, FIN,
2359 MachinePointerInfo::getFixedStack(FI),
2365 if (!MemOpChains2.empty())
2366 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2367 &MemOpChains2[0], MemOpChains2.size());
2369 // Copy arguments to their registers.
2370 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2371 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2372 RegsToPass[i].second, InFlag);
2373 InFlag = Chain.getValue(1);
2377 // Store the return address to the appropriate stack slot.
2378 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2382 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2383 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2384 // In the 64-bit large code model, we have to make all calls
2385 // through a register, since the call instruction's 32-bit
2386 // pc-relative offset may not be large enough to hold the whole
2388 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2389 // If the callee is a GlobalAddress node (quite common, every direct call
2390 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2393 // We should use extra load for direct calls to dllimported functions in
2395 const GlobalValue *GV = G->getGlobal();
2396 if (!GV->hasDLLImportLinkage()) {
2397 unsigned char OpFlags = 0;
2398 bool ExtraLoad = false;
2399 unsigned WrapperKind = ISD::DELETED_NODE;
2401 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2402 // external symbols most go through the PLT in PIC mode. If the symbol
2403 // has hidden or protected visibility, or if it is static or local, then
2404 // we don't need to use the PLT - we can directly call it.
2405 if (Subtarget->isTargetELF() &&
2406 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2407 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2408 OpFlags = X86II::MO_PLT;
2409 } else if (Subtarget->isPICStyleStubAny() &&
2410 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2411 (!Subtarget->getTargetTriple().isMacOSX() ||
2412 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2413 // PC-relative references to external symbols should go through $stub,
2414 // unless we're building with the leopard linker or later, which
2415 // automatically synthesizes these stubs.
2416 OpFlags = X86II::MO_DARWIN_STUB;
2417 } else if (Subtarget->isPICStyleRIPRel() &&
2418 isa<Function>(GV) &&
2419 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2420 // If the function is marked as non-lazy, generate an indirect call
2421 // which loads from the GOT directly. This avoids runtime overhead
2422 // at the cost of eager binding (and one extra byte of encoding).
2423 OpFlags = X86II::MO_GOTPCREL;
2424 WrapperKind = X86ISD::WrapperRIP;
2428 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2429 G->getOffset(), OpFlags);
2431 // Add a wrapper if needed.
2432 if (WrapperKind != ISD::DELETED_NODE)
2433 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2434 // Add extra indirection if needed.
2436 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2437 MachinePointerInfo::getGOT(),
2438 false, false, false, 0);
2440 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2441 unsigned char OpFlags = 0;
2443 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2444 // external symbols should go through the PLT.
2445 if (Subtarget->isTargetELF() &&
2446 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2447 OpFlags = X86II::MO_PLT;
2448 } else if (Subtarget->isPICStyleStubAny() &&
2449 (!Subtarget->getTargetTriple().isMacOSX() ||
2450 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2451 // PC-relative references to external symbols should go through $stub,
2452 // unless we're building with the leopard linker or later, which
2453 // automatically synthesizes these stubs.
2454 OpFlags = X86II::MO_DARWIN_STUB;
2457 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2461 // Returns a chain & a flag for retval copy to use.
2462 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2463 SmallVector<SDValue, 8> Ops;
2465 if (!IsSibcall && isTailCall) {
2466 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2467 DAG.getIntPtrConstant(0, true), InFlag);
2468 InFlag = Chain.getValue(1);
2471 Ops.push_back(Chain);
2472 Ops.push_back(Callee);
2475 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2477 // Add argument registers to the end of the list so that they are known live
2479 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2480 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2481 RegsToPass[i].second.getValueType()));
2483 // Add an implicit use GOT pointer in EBX.
2484 if (!isTailCall && Subtarget->isPICStyleGOT())
2485 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2487 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2488 if (Is64Bit && isVarArg && !IsWin64)
2489 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2491 if (InFlag.getNode())
2492 Ops.push_back(InFlag);
2496 //// If this is the first return lowered for this function, add the regs
2497 //// to the liveout set for the function.
2498 // This isn't right, although it's probably harmless on x86; liveouts
2499 // should be computed from returns not tail calls. Consider a void
2500 // function making a tail call to a function returning int.
2501 return DAG.getNode(X86ISD::TC_RETURN, dl,
2502 NodeTys, &Ops[0], Ops.size());
2505 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2506 InFlag = Chain.getValue(1);
2508 // Create the CALLSEQ_END node.
2509 unsigned NumBytesForCalleeToPush;
2510 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2511 getTargetMachine().Options.GuaranteedTailCallOpt))
2512 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2513 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2514 // If this is a call to a struct-return function, the callee
2515 // pops the hidden struct pointer, so we have to push it back.
2516 // This is common for Darwin/X86, Linux & Mingw32 targets.
2517 NumBytesForCalleeToPush = 4;
2519 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2521 // Returns a flag for retval copy to use.
2523 Chain = DAG.getCALLSEQ_END(Chain,
2524 DAG.getIntPtrConstant(NumBytes, true),
2525 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2528 InFlag = Chain.getValue(1);
2531 // Handle result values, copying them out of physregs into vregs that we
2533 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2534 Ins, dl, DAG, InVals);
2538 //===----------------------------------------------------------------------===//
2539 // Fast Calling Convention (tail call) implementation
2540 //===----------------------------------------------------------------------===//
2542 // Like std call, callee cleans arguments, convention except that ECX is
2543 // reserved for storing the tail called function address. Only 2 registers are
2544 // free for argument passing (inreg). Tail call optimization is performed
2546 // * tailcallopt is enabled
2547 // * caller/callee are fastcc
2548 // On X86_64 architecture with GOT-style position independent code only local
2549 // (within module) calls are supported at the moment.
2550 // To keep the stack aligned according to platform abi the function
2551 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2552 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2553 // If a tail called function callee has more arguments than the caller the
2554 // caller needs to make sure that there is room to move the RETADDR to. This is
2555 // achieved by reserving an area the size of the argument delta right after the
2556 // original REtADDR, but before the saved framepointer or the spilled registers
2557 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2569 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2570 /// for a 16 byte align requirement.
2572 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2573 SelectionDAG& DAG) const {
2574 MachineFunction &MF = DAG.getMachineFunction();
2575 const TargetMachine &TM = MF.getTarget();
2576 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2577 unsigned StackAlignment = TFI.getStackAlignment();
2578 uint64_t AlignMask = StackAlignment - 1;
2579 int64_t Offset = StackSize;
2580 uint64_t SlotSize = TD->getPointerSize();
2581 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2582 // Number smaller than 12 so just add the difference.
2583 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2585 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2586 Offset = ((~AlignMask) & Offset) + StackAlignment +
2587 (StackAlignment-SlotSize);
2592 /// MatchingStackOffset - Return true if the given stack call argument is
2593 /// already available in the same position (relatively) of the caller's
2594 /// incoming argument stack.
2596 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2597 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2598 const X86InstrInfo *TII) {
2599 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2601 if (Arg.getOpcode() == ISD::CopyFromReg) {
2602 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2603 if (!TargetRegisterInfo::isVirtualRegister(VR))
2605 MachineInstr *Def = MRI->getVRegDef(VR);
2608 if (!Flags.isByVal()) {
2609 if (!TII->isLoadFromStackSlot(Def, FI))
2612 unsigned Opcode = Def->getOpcode();
2613 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2614 Def->getOperand(1).isFI()) {
2615 FI = Def->getOperand(1).getIndex();
2616 Bytes = Flags.getByValSize();
2620 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2621 if (Flags.isByVal())
2622 // ByVal argument is passed in as a pointer but it's now being
2623 // dereferenced. e.g.
2624 // define @foo(%struct.X* %A) {
2625 // tail call @bar(%struct.X* byval %A)
2628 SDValue Ptr = Ld->getBasePtr();
2629 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2632 FI = FINode->getIndex();
2633 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2634 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2635 FI = FINode->getIndex();
2636 Bytes = Flags.getByValSize();
2640 assert(FI != INT_MAX);
2641 if (!MFI->isFixedObjectIndex(FI))
2643 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2646 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2647 /// for tail call optimization. Targets which want to do tail call
2648 /// optimization should implement this function.
2650 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2651 CallingConv::ID CalleeCC,
2653 bool isCalleeStructRet,
2654 bool isCallerStructRet,
2655 const SmallVectorImpl<ISD::OutputArg> &Outs,
2656 const SmallVectorImpl<SDValue> &OutVals,
2657 const SmallVectorImpl<ISD::InputArg> &Ins,
2658 SelectionDAG& DAG) const {
2659 if (!IsTailCallConvention(CalleeCC) &&
2660 CalleeCC != CallingConv::C)
2663 // If -tailcallopt is specified, make fastcc functions tail-callable.
2664 const MachineFunction &MF = DAG.getMachineFunction();
2665 const Function *CallerF = DAG.getMachineFunction().getFunction();
2666 CallingConv::ID CallerCC = CallerF->getCallingConv();
2667 bool CCMatch = CallerCC == CalleeCC;
2669 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2670 if (IsTailCallConvention(CalleeCC) && CCMatch)
2675 // Look for obvious safe cases to perform tail call optimization that do not
2676 // require ABI changes. This is what gcc calls sibcall.
2678 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2679 // emit a special epilogue.
2680 if (RegInfo->needsStackRealignment(MF))
2683 // Also avoid sibcall optimization if either caller or callee uses struct
2684 // return semantics.
2685 if (isCalleeStructRet || isCallerStructRet)
2688 // An stdcall caller is expected to clean up its arguments; the callee
2689 // isn't going to do that.
2690 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2693 // Do not sibcall optimize vararg calls unless all arguments are passed via
2695 if (isVarArg && !Outs.empty()) {
2697 // Optimizing for varargs on Win64 is unlikely to be safe without
2698 // additional testing.
2699 if (Subtarget->isTargetWin64())
2702 SmallVector<CCValAssign, 16> ArgLocs;
2703 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2704 getTargetMachine(), ArgLocs, *DAG.getContext());
2706 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2707 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2708 if (!ArgLocs[i].isRegLoc())
2712 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2713 // Therefore if it's not used by the call it is not safe to optimize this into
2715 bool Unused = false;
2716 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2723 SmallVector<CCValAssign, 16> RVLocs;
2724 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2725 getTargetMachine(), RVLocs, *DAG.getContext());
2726 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2727 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2728 CCValAssign &VA = RVLocs[i];
2729 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2734 // If the calling conventions do not match, then we'd better make sure the
2735 // results are returned in the same way as what the caller expects.
2737 SmallVector<CCValAssign, 16> RVLocs1;
2738 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2739 getTargetMachine(), RVLocs1, *DAG.getContext());
2740 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2742 SmallVector<CCValAssign, 16> RVLocs2;
2743 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2744 getTargetMachine(), RVLocs2, *DAG.getContext());
2745 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2747 if (RVLocs1.size() != RVLocs2.size())
2749 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2750 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2752 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2754 if (RVLocs1[i].isRegLoc()) {
2755 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2758 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2764 // If the callee takes no arguments then go on to check the results of the
2766 if (!Outs.empty()) {
2767 // Check if stack adjustment is needed. For now, do not do this if any
2768 // argument is passed on the stack.
2769 SmallVector<CCValAssign, 16> ArgLocs;
2770 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2771 getTargetMachine(), ArgLocs, *DAG.getContext());
2773 // Allocate shadow area for Win64
2774 if (Subtarget->isTargetWin64()) {
2775 CCInfo.AllocateStack(32, 8);
2778 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2779 if (CCInfo.getNextStackOffset()) {
2780 MachineFunction &MF = DAG.getMachineFunction();
2781 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2784 // Check if the arguments are already laid out in the right way as
2785 // the caller's fixed stack objects.
2786 MachineFrameInfo *MFI = MF.getFrameInfo();
2787 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2788 const X86InstrInfo *TII =
2789 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2790 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2791 CCValAssign &VA = ArgLocs[i];
2792 SDValue Arg = OutVals[i];
2793 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2794 if (VA.getLocInfo() == CCValAssign::Indirect)
2796 if (!VA.isRegLoc()) {
2797 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2804 // If the tailcall address may be in a register, then make sure it's
2805 // possible to register allocate for it. In 32-bit, the call address can
2806 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2807 // callee-saved registers are restored. These happen to be the same
2808 // registers used to pass 'inreg' arguments so watch out for those.
2809 if (!Subtarget->is64Bit() &&
2810 !isa<GlobalAddressSDNode>(Callee) &&
2811 !isa<ExternalSymbolSDNode>(Callee)) {
2812 unsigned NumInRegs = 0;
2813 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2814 CCValAssign &VA = ArgLocs[i];
2817 unsigned Reg = VA.getLocReg();
2820 case X86::EAX: case X86::EDX: case X86::ECX:
2821 if (++NumInRegs == 3)
2833 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2834 return X86::createFastISel(funcInfo);
2838 //===----------------------------------------------------------------------===//
2839 // Other Lowering Hooks
2840 //===----------------------------------------------------------------------===//
2842 static bool MayFoldLoad(SDValue Op) {
2843 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2846 static bool MayFoldIntoStore(SDValue Op) {
2847 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2850 static bool isTargetShuffle(unsigned Opcode) {
2852 default: return false;
2853 case X86ISD::PSHUFD:
2854 case X86ISD::PSHUFHW:
2855 case X86ISD::PSHUFLW:
2856 case X86ISD::SHUFPD:
2857 case X86ISD::PALIGN:
2858 case X86ISD::SHUFPS:
2859 case X86ISD::MOVLHPS:
2860 case X86ISD::MOVLHPD:
2861 case X86ISD::MOVHLPS:
2862 case X86ISD::MOVLPS:
2863 case X86ISD::MOVLPD:
2864 case X86ISD::MOVSHDUP:
2865 case X86ISD::MOVSLDUP:
2866 case X86ISD::MOVDDUP:
2869 case X86ISD::UNPCKL:
2870 case X86ISD::UNPCKH:
2871 case X86ISD::VPERMILP:
2872 case X86ISD::VPERM2X128:
2878 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2879 SDValue V1, SelectionDAG &DAG) {
2881 default: llvm_unreachable("Unknown x86 shuffle node");
2882 case X86ISD::MOVSHDUP:
2883 case X86ISD::MOVSLDUP:
2884 case X86ISD::MOVDDUP:
2885 return DAG.getNode(Opc, dl, VT, V1);
2891 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2892 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2894 default: llvm_unreachable("Unknown x86 shuffle node");
2895 case X86ISD::PSHUFD:
2896 case X86ISD::PSHUFHW:
2897 case X86ISD::PSHUFLW:
2898 case X86ISD::VPERMILP:
2899 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2905 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2906 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2908 default: llvm_unreachable("Unknown x86 shuffle node");
2909 case X86ISD::PALIGN:
2910 case X86ISD::SHUFPD:
2911 case X86ISD::SHUFPS:
2912 case X86ISD::VPERM2X128:
2913 return DAG.getNode(Opc, dl, VT, V1, V2,
2914 DAG.getConstant(TargetMask, MVT::i8));
2919 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2920 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2922 default: llvm_unreachable("Unknown x86 shuffle node");
2923 case X86ISD::MOVLHPS:
2924 case X86ISD::MOVLHPD:
2925 case X86ISD::MOVHLPS:
2926 case X86ISD::MOVLPS:
2927 case X86ISD::MOVLPD:
2930 case X86ISD::UNPCKL:
2931 case X86ISD::UNPCKH:
2932 return DAG.getNode(Opc, dl, VT, V1, V2);
2937 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2938 MachineFunction &MF = DAG.getMachineFunction();
2939 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2940 int ReturnAddrIndex = FuncInfo->getRAIndex();
2942 if (ReturnAddrIndex == 0) {
2943 // Set up a frame object for the return address.
2944 uint64_t SlotSize = TD->getPointerSize();
2945 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2947 FuncInfo->setRAIndex(ReturnAddrIndex);
2950 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2954 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2955 bool hasSymbolicDisplacement) {
2956 // Offset should fit into 32 bit immediate field.
2957 if (!isInt<32>(Offset))
2960 // If we don't have a symbolic displacement - we don't have any extra
2962 if (!hasSymbolicDisplacement)
2965 // FIXME: Some tweaks might be needed for medium code model.
2966 if (M != CodeModel::Small && M != CodeModel::Kernel)
2969 // For small code model we assume that latest object is 16MB before end of 31
2970 // bits boundary. We may also accept pretty large negative constants knowing
2971 // that all objects are in the positive half of address space.
2972 if (M == CodeModel::Small && Offset < 16*1024*1024)
2975 // For kernel code model we know that all object resist in the negative half
2976 // of 32bits address space. We may not accept negative offsets, since they may
2977 // be just off and we may accept pretty large positive ones.
2978 if (M == CodeModel::Kernel && Offset > 0)
2984 /// isCalleePop - Determines whether the callee is required to pop its
2985 /// own arguments. Callee pop is necessary to support tail calls.
2986 bool X86::isCalleePop(CallingConv::ID CallingConv,
2987 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2991 switch (CallingConv) {
2994 case CallingConv::X86_StdCall:
2996 case CallingConv::X86_FastCall:
2998 case CallingConv::X86_ThisCall:
3000 case CallingConv::Fast:
3002 case CallingConv::GHC:
3007 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3008 /// specific condition code, returning the condition code and the LHS/RHS of the
3009 /// comparison to make.
3010 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3011 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3013 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3014 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3015 // X > -1 -> X == 0, jump !sign.
3016 RHS = DAG.getConstant(0, RHS.getValueType());
3017 return X86::COND_NS;
3018 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3019 // X < 0 -> X == 0, jump on sign.
3021 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3023 RHS = DAG.getConstant(0, RHS.getValueType());
3024 return X86::COND_LE;
3028 switch (SetCCOpcode) {
3029 default: llvm_unreachable("Invalid integer condition!");
3030 case ISD::SETEQ: return X86::COND_E;
3031 case ISD::SETGT: return X86::COND_G;
3032 case ISD::SETGE: return X86::COND_GE;
3033 case ISD::SETLT: return X86::COND_L;
3034 case ISD::SETLE: return X86::COND_LE;
3035 case ISD::SETNE: return X86::COND_NE;
3036 case ISD::SETULT: return X86::COND_B;
3037 case ISD::SETUGT: return X86::COND_A;
3038 case ISD::SETULE: return X86::COND_BE;
3039 case ISD::SETUGE: return X86::COND_AE;
3043 // First determine if it is required or is profitable to flip the operands.
3045 // If LHS is a foldable load, but RHS is not, flip the condition.
3046 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3047 !ISD::isNON_EXTLoad(RHS.getNode())) {
3048 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3049 std::swap(LHS, RHS);
3052 switch (SetCCOpcode) {
3058 std::swap(LHS, RHS);
3062 // On a floating point condition, the flags are set as follows:
3064 // 0 | 0 | 0 | X > Y
3065 // 0 | 0 | 1 | X < Y
3066 // 1 | 0 | 0 | X == Y
3067 // 1 | 1 | 1 | unordered
3068 switch (SetCCOpcode) {
3069 default: llvm_unreachable("Condcode should be pre-legalized away");
3071 case ISD::SETEQ: return X86::COND_E;
3072 case ISD::SETOLT: // flipped
3074 case ISD::SETGT: return X86::COND_A;
3075 case ISD::SETOLE: // flipped
3077 case ISD::SETGE: return X86::COND_AE;
3078 case ISD::SETUGT: // flipped
3080 case ISD::SETLT: return X86::COND_B;
3081 case ISD::SETUGE: // flipped
3083 case ISD::SETLE: return X86::COND_BE;
3085 case ISD::SETNE: return X86::COND_NE;
3086 case ISD::SETUO: return X86::COND_P;
3087 case ISD::SETO: return X86::COND_NP;
3089 case ISD::SETUNE: return X86::COND_INVALID;
3093 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3094 /// code. Current x86 isa includes the following FP cmov instructions:
3095 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3096 static bool hasFPCMov(unsigned X86CC) {
3112 /// isFPImmLegal - Returns true if the target can instruction select the
3113 /// specified FP immediate natively. If false, the legalizer will
3114 /// materialize the FP immediate as a load from a constant pool.
3115 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3116 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3117 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3123 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3124 /// the specified range (L, H].
3125 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3126 return (Val < 0) || (Val >= Low && Val < Hi);
3129 /// isUndefOrInRange - Return true if every element in Mask, begining
3130 /// from position Pos and ending in Pos+Size, falls within the specified
3131 /// range (L, L+Pos]. or is undef.
3132 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3133 int Pos, int Size, int Low, int Hi) {
3134 for (int i = Pos, e = Pos+Size; i != e; ++i)
3135 if (!isUndefOrInRange(Mask[i], Low, Hi))
3140 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3141 /// specified value.
3142 static bool isUndefOrEqual(int Val, int CmpVal) {
3143 if (Val < 0 || Val == CmpVal)
3148 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3149 /// from position Pos and ending in Pos+Size, falls within the specified
3150 /// sequential range (L, L+Pos]. or is undef.
3151 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3152 int Pos, int Size, int Low) {
3153 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3154 if (!isUndefOrEqual(Mask[i], Low))
3159 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3160 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3161 /// the second operand.
3162 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3163 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3164 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3165 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3166 return (Mask[0] < 2 && Mask[1] < 2);
3170 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3171 SmallVector<int, 8> M;
3173 return ::isPSHUFDMask(M, N->getValueType(0));
3176 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3177 /// is suitable for input to PSHUFHW.
3178 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3179 if (VT != MVT::v8i16)
3182 // Lower quadword copied in order or undef.
3183 for (int i = 0; i != 4; ++i)
3184 if (Mask[i] >= 0 && Mask[i] != i)
3187 // Upper quadword shuffled.
3188 for (int i = 4; i != 8; ++i)
3189 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3195 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3196 SmallVector<int, 8> M;
3198 return ::isPSHUFHWMask(M, N->getValueType(0));
3201 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3202 /// is suitable for input to PSHUFLW.
3203 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3204 if (VT != MVT::v8i16)
3207 // Upper quadword copied in order.
3208 for (int i = 4; i != 8; ++i)
3209 if (Mask[i] >= 0 && Mask[i] != i)
3212 // Lower quadword shuffled.
3213 for (int i = 0; i != 4; ++i)
3220 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3221 SmallVector<int, 8> M;
3223 return ::isPSHUFLWMask(M, N->getValueType(0));
3226 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3227 /// is suitable for input to PALIGNR.
3228 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3229 bool hasSSSE3OrAVX) {
3230 int i, e = VT.getVectorNumElements();
3231 if (VT.getSizeInBits() != 128)
3234 // Do not handle v2i64 / v2f64 shuffles with palignr.
3235 if (e < 4 || !hasSSSE3OrAVX)
3238 for (i = 0; i != e; ++i)
3242 // All undef, not a palignr.
3246 // Make sure we're shifting in the right direction.
3250 int s = Mask[i] - i;
3252 // Check the rest of the elements to see if they are consecutive.
3253 for (++i; i != e; ++i) {
3255 if (m >= 0 && m != s+i)
3261 /// isVSHUFPYMask - Return true if the specified VECTOR_SHUFFLE operand
3262 /// specifies a shuffle of elements that is suitable for input to 256-bit
3264 static bool isVSHUFPYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3265 bool HasAVX, bool Commuted = false) {
3266 int NumElems = VT.getVectorNumElements();
3268 if (!HasAVX || VT.getSizeInBits() != 256)
3271 if (NumElems != 4 && NumElems != 8)
3274 // VSHUFPSY divides the resulting vector into 4 chunks.
3275 // The sources are also splitted into 4 chunks, and each destination
3276 // chunk must come from a different source chunk.
3278 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3279 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3281 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3282 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3284 // VSHUFPDY divides the resulting vector into 4 chunks.
3285 // The sources are also splitted into 4 chunks, and each destination
3286 // chunk must come from a different source chunk.
3288 // SRC1 => X3 X2 X1 X0
3289 // SRC2 => Y3 Y2 Y1 Y0
3291 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3293 unsigned QuarterSize = NumElems/4;
3294 unsigned HalfSize = QuarterSize*2;
3295 for (unsigned l = 0; l != 2; ++l) {
3296 unsigned LaneStart = l*HalfSize;
3297 for (unsigned s = 0; s != 2; ++s) {
3298 unsigned QuarterStart = s*QuarterSize;
3299 unsigned Src = (Commuted) ? (1-s) : s;
3300 unsigned SrcStart = Src*NumElems + LaneStart;
3301 for (unsigned i = 0; i != QuarterSize; ++i) {
3302 int Idx = Mask[i+QuarterStart+LaneStart];
3303 if (!isUndefOrInRange(Idx, SrcStart, SrcStart+HalfSize))
3305 // For VSHUFPSY, the mask of the second half must be the same as the first
3306 // but with the appropriate offsets. This works in the same way as
3307 // VPERMILPS works with masks.
3308 if (NumElems == 4 || l == 0 || Mask[i+QuarterStart] < 0)
3310 if (!isUndefOrEqual(Idx, Mask[i+QuarterStart]+HalfSize))
3319 /// getShuffleVSHUFPYImmediate - Return the appropriate immediate to shuffle
3320 /// the specified VECTOR_MASK mask with VSHUFPSY/VSHUFPDY instructions.
3321 static unsigned getShuffleVSHUFPYImmediate(SDNode *N) {
3322 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3323 EVT VT = SVOp->getValueType(0);
3324 int NumElems = VT.getVectorNumElements();
3326 assert(VT.getSizeInBits() == 256 && "Only supports 256-bit types");
3327 assert((NumElems == 4 || NumElems == 8) && "Only supports v4 and v8 types");
3329 int HalfSize = NumElems/2;
3330 unsigned Mul = (NumElems == 8) ? 2 : 1;
3332 for (int i = 0; i != NumElems; ++i) {
3333 int Elt = SVOp->getMaskElt(i);
3338 // For VSHUFPSY, the mask of the first half must be equal to the second one.
3339 if (NumElems == 8) Shamt %= HalfSize;
3340 Mask |= Elt << (Shamt*Mul);
3346 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3347 /// the two vector operands have swapped position.
3348 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3349 unsigned NumElems) {
3350 for (unsigned i = 0; i != NumElems; ++i) {
3354 else if (idx < (int)NumElems)
3355 Mask[i] = idx + NumElems;
3357 Mask[i] = idx - NumElems;
3361 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3362 /// specifies a shuffle of elements that is suitable for input to 128-bit
3363 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3364 /// reverse of what x86 shuffles want.
3365 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT,
3366 bool Commuted = false) {
3367 unsigned NumElems = VT.getVectorNumElements();
3369 if (VT.getSizeInBits() != 128)
3372 if (NumElems != 2 && NumElems != 4)
3375 unsigned Half = NumElems / 2;
3376 unsigned SrcStart = Commuted ? NumElems : 0;
3377 for (unsigned i = 0; i != Half; ++i)
3378 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems))
3380 SrcStart = Commuted ? 0 : NumElems;
3381 for (unsigned i = Half; i != NumElems; ++i)
3382 if (!isUndefOrInRange(Mask[i], SrcStart, SrcStart+NumElems))
3388 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3389 SmallVector<int, 8> M;
3391 return ::isSHUFPMask(M, N->getValueType(0));
3394 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3395 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3396 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3397 EVT VT = N->getValueType(0);
3398 unsigned NumElems = VT.getVectorNumElements();
3400 if (VT.getSizeInBits() != 128)
3406 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3407 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3408 isUndefOrEqual(N->getMaskElt(1), 7) &&
3409 isUndefOrEqual(N->getMaskElt(2), 2) &&
3410 isUndefOrEqual(N->getMaskElt(3), 3);
3413 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3414 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3416 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3417 EVT VT = N->getValueType(0);
3418 unsigned NumElems = VT.getVectorNumElements();
3420 if (VT.getSizeInBits() != 128)
3426 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3427 isUndefOrEqual(N->getMaskElt(1), 3) &&
3428 isUndefOrEqual(N->getMaskElt(2), 2) &&
3429 isUndefOrEqual(N->getMaskElt(3), 3);
3432 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3433 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3434 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3435 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3437 if (NumElems != 2 && NumElems != 4)
3440 for (unsigned i = 0; i < NumElems/2; ++i)
3441 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3444 for (unsigned i = NumElems/2; i < NumElems; ++i)
3445 if (!isUndefOrEqual(N->getMaskElt(i), i))
3451 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3452 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3453 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3454 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3456 if ((NumElems != 2 && NumElems != 4)
3457 || N->getValueType(0).getSizeInBits() > 128)
3460 for (unsigned i = 0; i < NumElems/2; ++i)
3461 if (!isUndefOrEqual(N->getMaskElt(i), i))
3464 for (unsigned i = 0; i < NumElems/2; ++i)
3465 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3471 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3472 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3473 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3474 bool HasAVX2, bool V2IsSplat = false) {
3475 unsigned NumElts = VT.getVectorNumElements();
3477 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3478 "Unsupported vector type for unpckh");
3480 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3481 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3484 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3485 // independently on 128-bit lanes.
3486 unsigned NumLanes = VT.getSizeInBits()/128;
3487 unsigned NumLaneElts = NumElts/NumLanes;
3489 for (unsigned l = 0; l != NumLanes; ++l) {
3490 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3491 i != (l+1)*NumLaneElts;
3494 int BitI1 = Mask[i+1];
3495 if (!isUndefOrEqual(BitI, j))
3498 if (!isUndefOrEqual(BitI1, NumElts))
3501 if (!isUndefOrEqual(BitI1, j + NumElts))
3510 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3511 SmallVector<int, 8> M;
3513 return ::isUNPCKLMask(M, N->getValueType(0), HasAVX2, V2IsSplat);
3516 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3517 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3518 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3519 bool HasAVX2, bool V2IsSplat = false) {
3520 unsigned NumElts = VT.getVectorNumElements();
3522 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3523 "Unsupported vector type for unpckh");
3525 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3526 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3529 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3530 // independently on 128-bit lanes.
3531 unsigned NumLanes = VT.getSizeInBits()/128;
3532 unsigned NumLaneElts = NumElts/NumLanes;
3534 for (unsigned l = 0; l != NumLanes; ++l) {
3535 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3536 i != (l+1)*NumLaneElts; i += 2, ++j) {
3538 int BitI1 = Mask[i+1];
3539 if (!isUndefOrEqual(BitI, j))
3542 if (isUndefOrEqual(BitI1, NumElts))
3545 if (!isUndefOrEqual(BitI1, j+NumElts))
3553 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3554 SmallVector<int, 8> M;
3556 return ::isUNPCKHMask(M, N->getValueType(0), HasAVX2, V2IsSplat);
3559 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3560 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3562 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3564 unsigned NumElts = VT.getVectorNumElements();
3566 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3567 "Unsupported vector type for unpckh");
3569 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3570 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3573 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3574 // FIXME: Need a better way to get rid of this, there's no latency difference
3575 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3576 // the former later. We should also remove the "_undef" special mask.
3577 if (NumElts == 4 && VT.getSizeInBits() == 256)
3580 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3581 // independently on 128-bit lanes.
3582 unsigned NumLanes = VT.getSizeInBits()/128;
3583 unsigned NumLaneElts = NumElts/NumLanes;
3585 for (unsigned l = 0; l != NumLanes; ++l) {
3586 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3587 i != (l+1)*NumLaneElts;
3590 int BitI1 = Mask[i+1];
3592 if (!isUndefOrEqual(BitI, j))
3594 if (!isUndefOrEqual(BitI1, j))
3602 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3603 SmallVector<int, 8> M;
3605 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0), HasAVX2);
3608 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3609 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3611 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3613 unsigned NumElts = VT.getVectorNumElements();
3615 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3616 "Unsupported vector type for unpckh");
3618 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3619 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3622 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3623 // independently on 128-bit lanes.
3624 unsigned NumLanes = VT.getSizeInBits()/128;
3625 unsigned NumLaneElts = NumElts/NumLanes;
3627 for (unsigned l = 0; l != NumLanes; ++l) {
3628 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3629 i != (l+1)*NumLaneElts; i += 2, ++j) {
3631 int BitI1 = Mask[i+1];
3632 if (!isUndefOrEqual(BitI, j))
3634 if (!isUndefOrEqual(BitI1, j))
3641 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3642 SmallVector<int, 8> M;
3644 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0), HasAVX2);
3647 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3648 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3649 /// MOVSD, and MOVD, i.e. setting the lowest element.
3650 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3651 if (VT.getVectorElementType().getSizeInBits() < 32)
3654 int NumElts = VT.getVectorNumElements();
3656 if (!isUndefOrEqual(Mask[0], NumElts))
3659 for (int i = 1; i < NumElts; ++i)
3660 if (!isUndefOrEqual(Mask[i], i))
3666 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3667 SmallVector<int, 8> M;
3669 return ::isMOVLMask(M, N->getValueType(0));
3672 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3673 /// as permutations between 128-bit chunks or halves. As an example: this
3675 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3676 /// The first half comes from the second half of V1 and the second half from the
3677 /// the second half of V2.
3678 static bool isVPERM2X128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3680 if (!HasAVX || VT.getSizeInBits() != 256)
3683 // The shuffle result is divided into half A and half B. In total the two
3684 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3685 // B must come from C, D, E or F.
3686 int HalfSize = VT.getVectorNumElements()/2;
3687 bool MatchA = false, MatchB = false;
3689 // Check if A comes from one of C, D, E, F.
3690 for (int Half = 0; Half < 4; ++Half) {
3691 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3697 // Check if B comes from one of C, D, E, F.
3698 for (int Half = 0; Half < 4; ++Half) {
3699 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3705 return MatchA && MatchB;
3708 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3709 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3710 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3711 EVT VT = SVOp->getValueType(0);
3713 int HalfSize = VT.getVectorNumElements()/2;
3715 int FstHalf = 0, SndHalf = 0;
3716 for (int i = 0; i < HalfSize; ++i) {
3717 if (SVOp->getMaskElt(i) > 0) {
3718 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3722 for (int i = HalfSize; i < HalfSize*2; ++i) {
3723 if (SVOp->getMaskElt(i) > 0) {
3724 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3729 return (FstHalf | (SndHalf << 4));
3732 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3733 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3734 /// Note that VPERMIL mask matching is different depending whether theunderlying
3735 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3736 /// to the same elements of the low, but to the higher half of the source.
3737 /// In VPERMILPD the two lanes could be shuffled independently of each other
3738 /// with the same restriction that lanes can't be crossed.
3739 static bool isVPERMILPMask(const SmallVectorImpl<int> &Mask, EVT VT,
3741 int NumElts = VT.getVectorNumElements();
3742 int NumLanes = VT.getSizeInBits()/128;
3747 // Only match 256-bit with 32/64-bit types
3748 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3751 int LaneSize = NumElts/NumLanes;
3752 for (int l = 0; l != NumLanes; ++l) {
3753 int LaneStart = l*LaneSize;
3754 for (int i = 0; i != LaneSize; ++i) {
3755 if (!isUndefOrInRange(Mask[i+LaneStart], LaneStart, LaneStart+LaneSize))
3757 if (NumElts == 4 || l == 0)
3759 // VPERMILPS handling
3762 if (!isUndefOrEqual(Mask[i+LaneStart], Mask[i]+LaneSize))
3770 /// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle
3771 /// the specified VECTOR_MASK mask with VPERMILPS/D* instructions.
3772 static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) {
3773 EVT VT = SVOp->getValueType(0);
3775 int NumElts = VT.getVectorNumElements();
3776 int NumLanes = VT.getSizeInBits()/128;
3777 int LaneSize = NumElts/NumLanes;
3779 // Although the mask is equal for both lanes do it twice to get the cases
3780 // where a mask will match because the same mask element is undef on the
3781 // first half but valid on the second. This would get pathological cases
3782 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3783 unsigned Shift = (LaneSize == 4) ? 2 : 1;
3785 for (int i = 0; i != NumElts; ++i) {
3786 int MaskElt = SVOp->getMaskElt(i);
3789 MaskElt %= LaneSize;
3791 // VPERMILPSY, the mask of the first half must be equal to the second one
3792 if (NumElts == 8) Shamt %= LaneSize;
3793 Mask |= MaskElt << (Shamt*Shift);
3799 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3800 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3801 /// element of vector 2 and the other elements to come from vector 1 in order.
3802 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3803 bool V2IsSplat = false, bool V2IsUndef = false) {
3804 int NumOps = VT.getVectorNumElements();
3805 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3808 if (!isUndefOrEqual(Mask[0], 0))
3811 for (int i = 1; i < NumOps; ++i)
3812 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3813 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3814 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3820 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3821 bool V2IsUndef = false) {
3822 SmallVector<int, 8> M;
3824 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3827 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3828 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3829 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3830 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3831 const X86Subtarget *Subtarget) {
3832 if (!Subtarget->hasSSE3orAVX())
3835 // The second vector must be undef
3836 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3839 EVT VT = N->getValueType(0);
3840 unsigned NumElems = VT.getVectorNumElements();
3842 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3843 (VT.getSizeInBits() == 256 && NumElems != 8))
3846 // "i+1" is the value the indexed mask element must have
3847 for (unsigned i = 0; i < NumElems; i += 2)
3848 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3849 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3855 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3856 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3857 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3858 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3859 const X86Subtarget *Subtarget) {
3860 if (!Subtarget->hasSSE3orAVX())
3863 // The second vector must be undef
3864 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3867 EVT VT = N->getValueType(0);
3868 unsigned NumElems = VT.getVectorNumElements();
3870 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3871 (VT.getSizeInBits() == 256 && NumElems != 8))
3874 // "i" is the value the indexed mask element must have
3875 for (unsigned i = 0; i < NumElems; i += 2)
3876 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3877 !isUndefOrEqual(N->getMaskElt(i+1), i))
3883 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3884 /// specifies a shuffle of elements that is suitable for input to 256-bit
3885 /// version of MOVDDUP.
3886 static bool isMOVDDUPYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3888 int NumElts = VT.getVectorNumElements();
3890 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3893 for (int i = 0; i != NumElts/2; ++i)
3894 if (!isUndefOrEqual(Mask[i], 0))
3896 for (int i = NumElts/2; i != NumElts; ++i)
3897 if (!isUndefOrEqual(Mask[i], NumElts/2))
3902 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3903 /// specifies a shuffle of elements that is suitable for input to 128-bit
3904 /// version of MOVDDUP.
3905 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3906 EVT VT = N->getValueType(0);
3908 if (VT.getSizeInBits() != 128)
3911 int e = VT.getVectorNumElements() / 2;
3912 for (int i = 0; i < e; ++i)
3913 if (!isUndefOrEqual(N->getMaskElt(i), i))
3915 for (int i = 0; i < e; ++i)
3916 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3921 /// isVEXTRACTF128Index - Return true if the specified
3922 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3923 /// suitable for input to VEXTRACTF128.
3924 bool X86::isVEXTRACTF128Index(SDNode *N) {
3925 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3928 // The index should be aligned on a 128-bit boundary.
3930 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3932 unsigned VL = N->getValueType(0).getVectorNumElements();
3933 unsigned VBits = N->getValueType(0).getSizeInBits();
3934 unsigned ElSize = VBits / VL;
3935 bool Result = (Index * ElSize) % 128 == 0;
3940 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3941 /// operand specifies a subvector insert that is suitable for input to
3943 bool X86::isVINSERTF128Index(SDNode *N) {
3944 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3947 // The index should be aligned on a 128-bit boundary.
3949 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3951 unsigned VL = N->getValueType(0).getVectorNumElements();
3952 unsigned VBits = N->getValueType(0).getSizeInBits();
3953 unsigned ElSize = VBits / VL;
3954 bool Result = (Index * ElSize) % 128 == 0;
3959 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3960 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3961 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3962 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3963 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3965 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3967 for (int i = 0; i < NumOperands; ++i) {
3968 int Val = SVOp->getMaskElt(NumOperands-i-1);
3969 if (Val < 0) Val = 0;
3970 if (Val >= NumOperands) Val -= NumOperands;
3972 if (i != NumOperands - 1)
3978 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3979 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3980 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3981 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3983 // 8 nodes, but we only care about the last 4.
3984 for (unsigned i = 7; i >= 4; --i) {
3985 int Val = SVOp->getMaskElt(i);
3994 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3995 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3996 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3997 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3999 // 8 nodes, but we only care about the first 4.
4000 for (int i = 3; i >= 0; --i) {
4001 int Val = SVOp->getMaskElt(i);
4010 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4011 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4012 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4013 EVT VT = SVOp->getValueType(0);
4014 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4018 for (i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4019 Val = SVOp->getMaskElt(i);
4023 assert(Val - i > 0 && "PALIGNR imm should be positive");
4024 return (Val - i) * EltSize;
4027 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4028 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4030 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4031 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4032 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4035 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4037 EVT VecVT = N->getOperand(0).getValueType();
4038 EVT ElVT = VecVT.getVectorElementType();
4040 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4041 return Index / NumElemsPerChunk;
4044 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4045 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4047 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4048 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4049 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4052 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4054 EVT VecVT = N->getValueType(0);
4055 EVT ElVT = VecVT.getVectorElementType();
4057 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4058 return Index / NumElemsPerChunk;
4061 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4063 bool X86::isZeroNode(SDValue Elt) {
4064 return ((isa<ConstantSDNode>(Elt) &&
4065 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4066 (isa<ConstantFPSDNode>(Elt) &&
4067 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4070 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4071 /// their permute mask.
4072 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4073 SelectionDAG &DAG) {
4074 EVT VT = SVOp->getValueType(0);
4075 unsigned NumElems = VT.getVectorNumElements();
4076 SmallVector<int, 8> MaskVec;
4078 for (unsigned i = 0; i != NumElems; ++i) {
4079 int idx = SVOp->getMaskElt(i);
4081 MaskVec.push_back(idx);
4082 else if (idx < (int)NumElems)
4083 MaskVec.push_back(idx + NumElems);
4085 MaskVec.push_back(idx - NumElems);
4087 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4088 SVOp->getOperand(0), &MaskVec[0]);
4091 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4092 /// match movhlps. The lower half elements should come from upper half of
4093 /// V1 (and in order), and the upper half elements should come from the upper
4094 /// half of V2 (and in order).
4095 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4096 EVT VT = Op->getValueType(0);
4097 if (VT.getSizeInBits() != 128)
4099 if (VT.getVectorNumElements() != 4)
4101 for (unsigned i = 0, e = 2; i != e; ++i)
4102 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4104 for (unsigned i = 2; i != 4; ++i)
4105 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4110 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4111 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4113 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4114 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4116 N = N->getOperand(0).getNode();
4117 if (!ISD::isNON_EXTLoad(N))
4120 *LD = cast<LoadSDNode>(N);
4124 // Test whether the given value is a vector value which will be legalized
4126 static bool WillBeConstantPoolLoad(SDNode *N) {
4127 if (N->getOpcode() != ISD::BUILD_VECTOR)
4130 // Check for any non-constant elements.
4131 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4132 switch (N->getOperand(i).getNode()->getOpcode()) {
4134 case ISD::ConstantFP:
4141 // Vectors of all-zeros and all-ones are materialized with special
4142 // instructions rather than being loaded.
4143 return !ISD::isBuildVectorAllZeros(N) &&
4144 !ISD::isBuildVectorAllOnes(N);
4147 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4148 /// match movlp{s|d}. The lower half elements should come from lower half of
4149 /// V1 (and in order), and the upper half elements should come from the upper
4150 /// half of V2 (and in order). And since V1 will become the source of the
4151 /// MOVLP, it must be either a vector load or a scalar load to vector.
4152 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4153 ShuffleVectorSDNode *Op) {
4154 EVT VT = Op->getValueType(0);
4155 if (VT.getSizeInBits() != 128)
4158 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4160 // Is V2 is a vector load, don't do this transformation. We will try to use
4161 // load folding shufps op.
4162 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4165 unsigned NumElems = VT.getVectorNumElements();
4167 if (NumElems != 2 && NumElems != 4)
4169 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4170 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4172 for (unsigned i = NumElems/2; i != NumElems; ++i)
4173 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4178 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4180 static bool isSplatVector(SDNode *N) {
4181 if (N->getOpcode() != ISD::BUILD_VECTOR)
4184 SDValue SplatValue = N->getOperand(0);
4185 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4186 if (N->getOperand(i) != SplatValue)
4191 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4192 /// to an zero vector.
4193 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4194 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4195 SDValue V1 = N->getOperand(0);
4196 SDValue V2 = N->getOperand(1);
4197 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4198 for (unsigned i = 0; i != NumElems; ++i) {
4199 int Idx = N->getMaskElt(i);
4200 if (Idx >= (int)NumElems) {
4201 unsigned Opc = V2.getOpcode();
4202 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4204 if (Opc != ISD::BUILD_VECTOR ||
4205 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4207 } else if (Idx >= 0) {
4208 unsigned Opc = V1.getOpcode();
4209 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4211 if (Opc != ISD::BUILD_VECTOR ||
4212 !X86::isZeroNode(V1.getOperand(Idx)))
4219 /// getZeroVector - Returns a vector of specified type with all zero elements.
4221 static SDValue getZeroVector(EVT VT, bool HasXMMInt, SelectionDAG &DAG,
4223 assert(VT.isVector() && "Expected a vector type");
4225 // Always build SSE zero vectors as <4 x i32> bitcasted
4226 // to their dest type. This ensures they get CSE'd.
4228 if (VT.getSizeInBits() == 128) { // SSE
4229 if (HasXMMInt) { // SSE2
4230 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4231 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4233 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4234 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4236 } else if (VT.getSizeInBits() == 256) { // AVX
4237 // 256-bit logic and arithmetic instructions in AVX are
4238 // all floating-point, no support for integer ops. Default
4239 // to emitting fp zeroed vectors then.
4240 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4241 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4242 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4244 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4247 /// getOnesVector - Returns a vector of specified type with all bits set.
4248 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4249 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4250 /// Then bitcast to their original type, ensuring they get CSE'd.
4251 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4253 assert(VT.isVector() && "Expected a vector type");
4254 assert((VT.is128BitVector() || VT.is256BitVector())
4255 && "Expected a 128-bit or 256-bit vector type");
4257 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4259 if (VT.getSizeInBits() == 256) {
4260 if (HasAVX2) { // AVX2
4261 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4262 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4264 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4265 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4266 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4267 Vec = Insert128BitVector(InsV, Vec,
4268 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4271 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4274 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4277 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4278 /// that point to V2 points to its first element.
4279 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4280 EVT VT = SVOp->getValueType(0);
4281 unsigned NumElems = VT.getVectorNumElements();
4283 bool Changed = false;
4284 SmallVector<int, 8> MaskVec;
4285 SVOp->getMask(MaskVec);
4287 for (unsigned i = 0; i != NumElems; ++i) {
4288 if (MaskVec[i] > (int)NumElems) {
4289 MaskVec[i] = NumElems;
4294 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4295 SVOp->getOperand(1), &MaskVec[0]);
4296 return SDValue(SVOp, 0);
4299 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4300 /// operation of specified width.
4301 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4303 unsigned NumElems = VT.getVectorNumElements();
4304 SmallVector<int, 8> Mask;
4305 Mask.push_back(NumElems);
4306 for (unsigned i = 1; i != NumElems; ++i)
4308 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4311 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4312 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4314 unsigned NumElems = VT.getVectorNumElements();
4315 SmallVector<int, 8> Mask;
4316 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4318 Mask.push_back(i + NumElems);
4320 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4323 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4324 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4326 unsigned NumElems = VT.getVectorNumElements();
4327 unsigned Half = NumElems/2;
4328 SmallVector<int, 8> Mask;
4329 for (unsigned i = 0; i != Half; ++i) {
4330 Mask.push_back(i + Half);
4331 Mask.push_back(i + NumElems + Half);
4333 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4336 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4337 // a generic shuffle instruction because the target has no such instructions.
4338 // Generate shuffles which repeat i16 and i8 several times until they can be
4339 // represented by v4f32 and then be manipulated by target suported shuffles.
4340 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4341 EVT VT = V.getValueType();
4342 int NumElems = VT.getVectorNumElements();
4343 DebugLoc dl = V.getDebugLoc();
4345 while (NumElems > 4) {
4346 if (EltNo < NumElems/2) {
4347 V = getUnpackl(DAG, dl, VT, V, V);
4349 V = getUnpackh(DAG, dl, VT, V, V);
4350 EltNo -= NumElems/2;
4357 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4358 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4359 EVT VT = V.getValueType();
4360 DebugLoc dl = V.getDebugLoc();
4361 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4362 && "Vector size not supported");
4364 if (VT.getSizeInBits() == 128) {
4365 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4366 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4367 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4370 // To use VPERMILPS to splat scalars, the second half of indicies must
4371 // refer to the higher part, which is a duplication of the lower one,
4372 // because VPERMILPS can only handle in-lane permutations.
4373 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4374 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4376 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4377 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4381 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4384 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4385 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4386 EVT SrcVT = SV->getValueType(0);
4387 SDValue V1 = SV->getOperand(0);
4388 DebugLoc dl = SV->getDebugLoc();
4390 int EltNo = SV->getSplatIndex();
4391 int NumElems = SrcVT.getVectorNumElements();
4392 unsigned Size = SrcVT.getSizeInBits();
4394 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4395 "Unknown how to promote splat for type");
4397 // Extract the 128-bit part containing the splat element and update
4398 // the splat element index when it refers to the higher register.
4400 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4401 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4403 EltNo -= NumElems/2;
4406 // All i16 and i8 vector types can't be used directly by a generic shuffle
4407 // instruction because the target has no such instruction. Generate shuffles
4408 // which repeat i16 and i8 several times until they fit in i32, and then can
4409 // be manipulated by target suported shuffles.
4410 EVT EltVT = SrcVT.getVectorElementType();
4411 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4412 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4414 // Recreate the 256-bit vector and place the same 128-bit vector
4415 // into the low and high part. This is necessary because we want
4416 // to use VPERM* to shuffle the vectors
4418 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4419 DAG.getConstant(0, MVT::i32), DAG, dl);
4420 V1 = Insert128BitVector(InsV, V1,
4421 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4424 return getLegalSplat(DAG, V1, EltNo);
4427 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4428 /// vector of zero or undef vector. This produces a shuffle where the low
4429 /// element of V2 is swizzled into the zero/undef vector, landing at element
4430 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4431 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4432 bool isZero, bool HasXMMInt,
4433 SelectionDAG &DAG) {
4434 EVT VT = V2.getValueType();
4436 ? getZeroVector(VT, HasXMMInt, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4437 unsigned NumElems = VT.getVectorNumElements();
4438 SmallVector<int, 16> MaskVec;
4439 for (unsigned i = 0; i != NumElems; ++i)
4440 // If this is the insertion idx, put the low elt of V2 here.
4441 MaskVec.push_back(i == Idx ? NumElems : i);
4442 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4445 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4446 /// element of the result of the vector shuffle.
4447 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4450 return SDValue(); // Limit search depth.
4452 SDValue V = SDValue(N, 0);
4453 EVT VT = V.getValueType();
4454 unsigned Opcode = V.getOpcode();
4456 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4457 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4458 Index = SV->getMaskElt(Index);
4461 return DAG.getUNDEF(VT.getVectorElementType());
4463 int NumElems = VT.getVectorNumElements();
4464 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4465 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4468 // Recurse into target specific vector shuffles to find scalars.
4469 if (isTargetShuffle(Opcode)) {
4470 int NumElems = VT.getVectorNumElements();
4471 SmallVector<unsigned, 16> ShuffleMask;
4475 case X86ISD::SHUFPS:
4476 case X86ISD::SHUFPD:
4477 ImmN = N->getOperand(N->getNumOperands()-1);
4478 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4481 case X86ISD::UNPCKH:
4482 DecodeUNPCKHMask(VT, ShuffleMask);
4484 case X86ISD::UNPCKL:
4485 DecodeUNPCKLMask(VT, ShuffleMask);
4487 case X86ISD::MOVHLPS:
4488 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4490 case X86ISD::MOVLHPS:
4491 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4493 case X86ISD::PSHUFD:
4494 ImmN = N->getOperand(N->getNumOperands()-1);
4495 DecodePSHUFMask(NumElems,
4496 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4499 case X86ISD::PSHUFHW:
4500 ImmN = N->getOperand(N->getNumOperands()-1);
4501 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4504 case X86ISD::PSHUFLW:
4505 ImmN = N->getOperand(N->getNumOperands()-1);
4506 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4510 case X86ISD::MOVSD: {
4511 // The index 0 always comes from the first element of the second source,
4512 // this is why MOVSS and MOVSD are used in the first place. The other
4513 // elements come from the other positions of the first source vector.
4514 unsigned OpNum = (Index == 0) ? 1 : 0;
4515 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4518 case X86ISD::VPERMILP:
4519 ImmN = N->getOperand(N->getNumOperands()-1);
4520 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4523 case X86ISD::VPERM2X128:
4524 ImmN = N->getOperand(N->getNumOperands()-1);
4525 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4528 case X86ISD::MOVDDUP:
4529 case X86ISD::MOVLHPD:
4530 case X86ISD::MOVLPD:
4531 case X86ISD::MOVLPS:
4532 case X86ISD::MOVSHDUP:
4533 case X86ISD::MOVSLDUP:
4534 case X86ISD::PALIGN:
4535 return SDValue(); // Not yet implemented.
4537 assert(0 && "unknown target shuffle node");
4541 Index = ShuffleMask[Index];
4543 return DAG.getUNDEF(VT.getVectorElementType());
4545 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4546 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4550 // Actual nodes that may contain scalar elements
4551 if (Opcode == ISD::BITCAST) {
4552 V = V.getOperand(0);
4553 EVT SrcVT = V.getValueType();
4554 unsigned NumElems = VT.getVectorNumElements();
4556 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4560 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4561 return (Index == 0) ? V.getOperand(0)
4562 : DAG.getUNDEF(VT.getVectorElementType());
4564 if (V.getOpcode() == ISD::BUILD_VECTOR)
4565 return V.getOperand(Index);
4570 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4571 /// shuffle operation which come from a consecutively from a zero. The
4572 /// search can start in two different directions, from left or right.
4574 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4575 bool ZerosFromLeft, SelectionDAG &DAG) {
4578 while (i < NumElems) {
4579 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4580 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4581 if (!(Elt.getNode() &&
4582 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4590 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4591 /// MaskE correspond consecutively to elements from one of the vector operands,
4592 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4594 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4595 int OpIdx, int NumElems, unsigned &OpNum) {
4596 bool SeenV1 = false;
4597 bool SeenV2 = false;
4599 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4600 int Idx = SVOp->getMaskElt(i);
4601 // Ignore undef indicies
4610 // Only accept consecutive elements from the same vector
4611 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4615 OpNum = SeenV1 ? 0 : 1;
4619 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4620 /// logical left shift of a vector.
4621 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4622 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4623 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4624 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4625 false /* check zeros from right */, DAG);
4631 // Considering the elements in the mask that are not consecutive zeros,
4632 // check if they consecutively come from only one of the source vectors.
4634 // V1 = {X, A, B, C} 0
4636 // vector_shuffle V1, V2 <1, 2, 3, X>
4638 if (!isShuffleMaskConsecutive(SVOp,
4639 0, // Mask Start Index
4640 NumElems-NumZeros-1, // Mask End Index
4641 NumZeros, // Where to start looking in the src vector
4642 NumElems, // Number of elements in vector
4643 OpSrc)) // Which source operand ?
4648 ShVal = SVOp->getOperand(OpSrc);
4652 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4653 /// logical left shift of a vector.
4654 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4655 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4656 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4657 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4658 true /* check zeros from left */, DAG);
4664 // Considering the elements in the mask that are not consecutive zeros,
4665 // check if they consecutively come from only one of the source vectors.
4667 // 0 { A, B, X, X } = V2
4669 // vector_shuffle V1, V2 <X, X, 4, 5>
4671 if (!isShuffleMaskConsecutive(SVOp,
4672 NumZeros, // Mask Start Index
4673 NumElems-1, // Mask End Index
4674 0, // Where to start looking in the src vector
4675 NumElems, // Number of elements in vector
4676 OpSrc)) // Which source operand ?
4681 ShVal = SVOp->getOperand(OpSrc);
4685 /// isVectorShift - Returns true if the shuffle can be implemented as a
4686 /// logical left or right shift of a vector.
4687 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4688 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4689 // Although the logic below support any bitwidth size, there are no
4690 // shift instructions which handle more than 128-bit vectors.
4691 if (SVOp->getValueType(0).getSizeInBits() > 128)
4694 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4695 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4701 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4703 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4704 unsigned NumNonZero, unsigned NumZero,
4706 const TargetLowering &TLI) {
4710 DebugLoc dl = Op.getDebugLoc();
4713 for (unsigned i = 0; i < 16; ++i) {
4714 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4715 if (ThisIsNonZero && First) {
4717 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4719 V = DAG.getUNDEF(MVT::v8i16);
4724 SDValue ThisElt(0, 0), LastElt(0, 0);
4725 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4726 if (LastIsNonZero) {
4727 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4728 MVT::i16, Op.getOperand(i-1));
4730 if (ThisIsNonZero) {
4731 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4732 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4733 ThisElt, DAG.getConstant(8, MVT::i8));
4735 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4739 if (ThisElt.getNode())
4740 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4741 DAG.getIntPtrConstant(i/2));
4745 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4748 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4750 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4751 unsigned NumNonZero, unsigned NumZero,
4753 const TargetLowering &TLI) {
4757 DebugLoc dl = Op.getDebugLoc();
4760 for (unsigned i = 0; i < 8; ++i) {
4761 bool isNonZero = (NonZeros & (1 << i)) != 0;
4765 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4767 V = DAG.getUNDEF(MVT::v8i16);
4770 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4771 MVT::v8i16, V, Op.getOperand(i),
4772 DAG.getIntPtrConstant(i));
4779 /// getVShift - Return a vector logical shift node.
4781 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4782 unsigned NumBits, SelectionDAG &DAG,
4783 const TargetLowering &TLI, DebugLoc dl) {
4784 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4785 EVT ShVT = MVT::v2i64;
4786 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4787 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4788 return DAG.getNode(ISD::BITCAST, dl, VT,
4789 DAG.getNode(Opc, dl, ShVT, SrcOp,
4790 DAG.getConstant(NumBits,
4791 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4795 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4796 SelectionDAG &DAG) const {
4798 // Check if the scalar load can be widened into a vector load. And if
4799 // the address is "base + cst" see if the cst can be "absorbed" into
4800 // the shuffle mask.
4801 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4802 SDValue Ptr = LD->getBasePtr();
4803 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4805 EVT PVT = LD->getValueType(0);
4806 if (PVT != MVT::i32 && PVT != MVT::f32)
4811 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4812 FI = FINode->getIndex();
4814 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4815 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4816 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4817 Offset = Ptr.getConstantOperandVal(1);
4818 Ptr = Ptr.getOperand(0);
4823 // FIXME: 256-bit vector instructions don't require a strict alignment,
4824 // improve this code to support it better.
4825 unsigned RequiredAlign = VT.getSizeInBits()/8;
4826 SDValue Chain = LD->getChain();
4827 // Make sure the stack object alignment is at least 16 or 32.
4828 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4829 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4830 if (MFI->isFixedObjectIndex(FI)) {
4831 // Can't change the alignment. FIXME: It's possible to compute
4832 // the exact stack offset and reference FI + adjust offset instead.
4833 // If someone *really* cares about this. That's the way to implement it.
4836 MFI->setObjectAlignment(FI, RequiredAlign);
4840 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4841 // Ptr + (Offset & ~15).
4844 if ((Offset % RequiredAlign) & 3)
4846 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4848 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4849 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4851 int EltNo = (Offset - StartOffset) >> 2;
4852 int NumElems = VT.getVectorNumElements();
4854 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4855 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4856 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4857 LD->getPointerInfo().getWithOffset(StartOffset),
4858 false, false, false, 0);
4860 // Canonicalize it to a v4i32 or v8i32 shuffle.
4861 SmallVector<int, 8> Mask;
4862 for (int i = 0; i < NumElems; ++i)
4863 Mask.push_back(EltNo);
4865 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4866 return DAG.getNode(ISD::BITCAST, dl, NVT,
4867 DAG.getVectorShuffle(CanonVT, dl, V1,
4868 DAG.getUNDEF(CanonVT),&Mask[0]));
4874 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4875 /// vector of type 'VT', see if the elements can be replaced by a single large
4876 /// load which has the same value as a build_vector whose operands are 'elts'.
4878 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4880 /// FIXME: we'd also like to handle the case where the last elements are zero
4881 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4882 /// There's even a handy isZeroNode for that purpose.
4883 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4884 DebugLoc &DL, SelectionDAG &DAG) {
4885 EVT EltVT = VT.getVectorElementType();
4886 unsigned NumElems = Elts.size();
4888 LoadSDNode *LDBase = NULL;
4889 unsigned LastLoadedElt = -1U;
4891 // For each element in the initializer, see if we've found a load or an undef.
4892 // If we don't find an initial load element, or later load elements are
4893 // non-consecutive, bail out.
4894 for (unsigned i = 0; i < NumElems; ++i) {
4895 SDValue Elt = Elts[i];
4897 if (!Elt.getNode() ||
4898 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4901 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4903 LDBase = cast<LoadSDNode>(Elt.getNode());
4907 if (Elt.getOpcode() == ISD::UNDEF)
4910 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4911 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4916 // If we have found an entire vector of loads and undefs, then return a large
4917 // load of the entire vector width starting at the base pointer. If we found
4918 // consecutive loads for the low half, generate a vzext_load node.
4919 if (LastLoadedElt == NumElems - 1) {
4920 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4921 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4922 LDBase->getPointerInfo(),
4923 LDBase->isVolatile(), LDBase->isNonTemporal(),
4924 LDBase->isInvariant(), 0);
4925 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4926 LDBase->getPointerInfo(),
4927 LDBase->isVolatile(), LDBase->isNonTemporal(),
4928 LDBase->isInvariant(), LDBase->getAlignment());
4929 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4930 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4931 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4932 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4934 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4935 LDBase->getPointerInfo(),
4936 LDBase->getAlignment(),
4937 false/*isVolatile*/, true/*ReadMem*/,
4939 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4944 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4945 /// a vbroadcast node. We support two patterns:
4946 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4947 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4949 /// The scalar load node is returned when a pattern is found,
4950 /// or SDValue() otherwise.
4951 static SDValue isVectorBroadcast(SDValue &Op, bool hasAVX2) {
4952 EVT VT = Op.getValueType();
4955 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4956 V = V.getOperand(0);
4958 //A suspected load to be broadcasted.
4961 switch (V.getOpcode()) {
4963 // Unknown pattern found.
4966 case ISD::BUILD_VECTOR: {
4967 // The BUILD_VECTOR node must be a splat.
4968 if (!isSplatVector(V.getNode()))
4971 Ld = V.getOperand(0);
4973 // The suspected load node has several users. Make sure that all
4974 // of its users are from the BUILD_VECTOR node.
4975 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4980 case ISD::VECTOR_SHUFFLE: {
4981 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4983 // Shuffles must have a splat mask where the first element is
4985 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4988 SDValue Sc = Op.getOperand(0);
4989 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4992 Ld = Sc.getOperand(0);
4994 // The scalar_to_vector node and the suspected
4995 // load node must have exactly one user.
4996 if (!Sc.hasOneUse() || !Ld.hasOneUse())
5002 // The scalar source must be a normal load.
5003 if (!ISD::isNormalLoad(Ld.getNode()))
5006 bool Is256 = VT.getSizeInBits() == 256;
5007 bool Is128 = VT.getSizeInBits() == 128;
5008 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5011 // VBroadcast to YMM
5012 if (Is256 && (ScalarSize == 8 || ScalarSize == 16 ||
5013 ScalarSize == 32 || ScalarSize == 64 ))
5016 // VBroadcast to XMM
5017 if (Is128 && (ScalarSize == 8 || ScalarSize == 32 ||
5018 ScalarSize == 16 || ScalarSize == 64 ))
5022 // VBroadcast to YMM
5023 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
5026 // VBroadcast to XMM
5027 if (Is128 && (ScalarSize == 32))
5031 // Unsupported broadcast.
5036 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5037 DebugLoc dl = Op.getDebugLoc();
5039 EVT VT = Op.getValueType();
5040 EVT ExtVT = VT.getVectorElementType();
5041 unsigned NumElems = Op.getNumOperands();
5043 // Vectors containing all zeros can be matched by pxor and xorps later
5044 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5045 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5046 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5047 if (Op.getValueType() == MVT::v4i32 ||
5048 Op.getValueType() == MVT::v8i32)
5051 return getZeroVector(Op.getValueType(), Subtarget->hasXMMInt(), DAG, dl);
5054 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5055 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5056 // vpcmpeqd on 256-bit vectors.
5057 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5058 if (Op.getValueType() == MVT::v4i32 ||
5059 (Op.getValueType() == MVT::v8i32 && Subtarget->hasAVX2()))
5062 return getOnesVector(Op.getValueType(), Subtarget->hasAVX2(), DAG, dl);
5065 SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2());
5066 if (Subtarget->hasAVX() && LD.getNode())
5067 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
5069 unsigned EVTBits = ExtVT.getSizeInBits();
5071 unsigned NumZero = 0;
5072 unsigned NumNonZero = 0;
5073 unsigned NonZeros = 0;
5074 bool IsAllConstants = true;
5075 SmallSet<SDValue, 8> Values;
5076 for (unsigned i = 0; i < NumElems; ++i) {
5077 SDValue Elt = Op.getOperand(i);
5078 if (Elt.getOpcode() == ISD::UNDEF)
5081 if (Elt.getOpcode() != ISD::Constant &&
5082 Elt.getOpcode() != ISD::ConstantFP)
5083 IsAllConstants = false;
5084 if (X86::isZeroNode(Elt))
5087 NonZeros |= (1 << i);
5092 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5093 if (NumNonZero == 0)
5094 return DAG.getUNDEF(VT);
5096 // Special case for single non-zero, non-undef, element.
5097 if (NumNonZero == 1) {
5098 unsigned Idx = CountTrailingZeros_32(NonZeros);
5099 SDValue Item = Op.getOperand(Idx);
5101 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5102 // the value are obviously zero, truncate the value to i32 and do the
5103 // insertion that way. Only do this if the value is non-constant or if the
5104 // value is a constant being inserted into element 0. It is cheaper to do
5105 // a constant pool load than it is to do a movd + shuffle.
5106 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5107 (!IsAllConstants || Idx == 0)) {
5108 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5110 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5111 EVT VecVT = MVT::v4i32;
5112 unsigned VecElts = 4;
5114 // Truncate the value (which may itself be a constant) to i32, and
5115 // convert it to a vector with movd (S2V+shuffle to zero extend).
5116 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5117 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5118 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5119 Subtarget->hasXMMInt(), DAG);
5121 // Now we have our 32-bit value zero extended in the low element of
5122 // a vector. If Idx != 0, swizzle it into place.
5124 SmallVector<int, 4> Mask;
5125 Mask.push_back(Idx);
5126 for (unsigned i = 1; i != VecElts; ++i)
5128 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5129 DAG.getUNDEF(Item.getValueType()),
5132 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5136 // If we have a constant or non-constant insertion into the low element of
5137 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5138 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5139 // depending on what the source datatype is.
5142 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5143 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5144 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5145 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5146 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5147 return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(),
5149 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5150 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5151 unsigned NumBits = VT.getSizeInBits();
5152 assert((NumBits == 128 || NumBits == 256) &&
5153 "Expected an SSE or AVX value type!");
5154 EVT MiddleVT = NumBits == 128 ? MVT::v4i32 : MVT::v8i32;
5155 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
5156 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5157 Subtarget->hasXMMInt(), DAG);
5158 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5162 // Is it a vector logical left shift?
5163 if (NumElems == 2 && Idx == 1 &&
5164 X86::isZeroNode(Op.getOperand(0)) &&
5165 !X86::isZeroNode(Op.getOperand(1))) {
5166 unsigned NumBits = VT.getSizeInBits();
5167 return getVShift(true, VT,
5168 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5169 VT, Op.getOperand(1)),
5170 NumBits/2, DAG, *this, dl);
5173 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5176 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5177 // is a non-constant being inserted into an element other than the low one,
5178 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5179 // movd/movss) to move this into the low element, then shuffle it into
5181 if (EVTBits == 32) {
5182 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5184 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5185 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
5186 Subtarget->hasXMMInt(), DAG);
5187 SmallVector<int, 8> MaskVec;
5188 for (unsigned i = 0; i < NumElems; i++)
5189 MaskVec.push_back(i == Idx ? 0 : 1);
5190 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5194 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5195 if (Values.size() == 1) {
5196 if (EVTBits == 32) {
5197 // Instead of a shuffle like this:
5198 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5199 // Check if it's possible to issue this instead.
5200 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5201 unsigned Idx = CountTrailingZeros_32(NonZeros);
5202 SDValue Item = Op.getOperand(Idx);
5203 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5204 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5209 // A vector full of immediates; various special cases are already
5210 // handled, so this is best done with a single constant-pool load.
5214 // For AVX-length vectors, build the individual 128-bit pieces and use
5215 // shuffles to put them in place.
5216 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5217 SmallVector<SDValue, 32> V;
5218 for (unsigned i = 0; i < NumElems; ++i)
5219 V.push_back(Op.getOperand(i));
5221 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5223 // Build both the lower and upper subvector.
5224 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5225 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5228 // Recreate the wider vector with the lower and upper part.
5229 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5230 DAG.getConstant(0, MVT::i32), DAG, dl);
5231 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5235 // Let legalizer expand 2-wide build_vectors.
5236 if (EVTBits == 64) {
5237 if (NumNonZero == 1) {
5238 // One half is zero or undef.
5239 unsigned Idx = CountTrailingZeros_32(NonZeros);
5240 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5241 Op.getOperand(Idx));
5242 return getShuffleVectorZeroOrUndef(V2, Idx, true,
5243 Subtarget->hasXMMInt(), DAG);
5248 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5249 if (EVTBits == 8 && NumElems == 16) {
5250 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5252 if (V.getNode()) return V;
5255 if (EVTBits == 16 && NumElems == 8) {
5256 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5258 if (V.getNode()) return V;
5261 // If element VT is == 32 bits, turn it into a number of shuffles.
5262 SmallVector<SDValue, 8> V;
5264 if (NumElems == 4 && NumZero > 0) {
5265 for (unsigned i = 0; i < 4; ++i) {
5266 bool isZero = !(NonZeros & (1 << i));
5268 V[i] = getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl);
5270 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5273 for (unsigned i = 0; i < 2; ++i) {
5274 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5277 V[i] = V[i*2]; // Must be a zero vector.
5280 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5283 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5286 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5291 SmallVector<int, 8> MaskVec;
5292 bool Reverse = (NonZeros & 0x3) == 2;
5293 for (unsigned i = 0; i < 2; ++i)
5294 MaskVec.push_back(Reverse ? 1-i : i);
5295 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5296 for (unsigned i = 0; i < 2; ++i)
5297 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5298 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5301 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5302 // Check for a build vector of consecutive loads.
5303 for (unsigned i = 0; i < NumElems; ++i)
5304 V[i] = Op.getOperand(i);
5306 // Check for elements which are consecutive loads.
5307 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5311 // For SSE 4.1, use insertps to put the high elements into the low element.
5312 if (getSubtarget()->hasSSE41orAVX()) {
5314 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5315 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5317 Result = DAG.getUNDEF(VT);
5319 for (unsigned i = 1; i < NumElems; ++i) {
5320 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5321 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5322 Op.getOperand(i), DAG.getIntPtrConstant(i));
5327 // Otherwise, expand into a number of unpckl*, start by extending each of
5328 // our (non-undef) elements to the full vector width with the element in the
5329 // bottom slot of the vector (which generates no code for SSE).
5330 for (unsigned i = 0; i < NumElems; ++i) {
5331 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5332 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5334 V[i] = DAG.getUNDEF(VT);
5337 // Next, we iteratively mix elements, e.g. for v4f32:
5338 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5339 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5340 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5341 unsigned EltStride = NumElems >> 1;
5342 while (EltStride != 0) {
5343 for (unsigned i = 0; i < EltStride; ++i) {
5344 // If V[i+EltStride] is undef and this is the first round of mixing,
5345 // then it is safe to just drop this shuffle: V[i] is already in the
5346 // right place, the one element (since it's the first round) being
5347 // inserted as undef can be dropped. This isn't safe for successive
5348 // rounds because they will permute elements within both vectors.
5349 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5350 EltStride == NumElems/2)
5353 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5362 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5363 // them in a MMX register. This is better than doing a stack convert.
5364 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5365 DebugLoc dl = Op.getDebugLoc();
5366 EVT ResVT = Op.getValueType();
5368 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5369 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5371 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5372 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5373 InVec = Op.getOperand(1);
5374 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5375 unsigned NumElts = ResVT.getVectorNumElements();
5376 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5377 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5378 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5380 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5381 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5382 Mask[0] = 0; Mask[1] = 2;
5383 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5385 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5388 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5389 // to create 256-bit vectors from two other 128-bit ones.
5390 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5391 DebugLoc dl = Op.getDebugLoc();
5392 EVT ResVT = Op.getValueType();
5394 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5396 SDValue V1 = Op.getOperand(0);
5397 SDValue V2 = Op.getOperand(1);
5398 unsigned NumElems = ResVT.getVectorNumElements();
5400 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5401 DAG.getConstant(0, MVT::i32), DAG, dl);
5402 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5407 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5408 EVT ResVT = Op.getValueType();
5410 assert(Op.getNumOperands() == 2);
5411 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5412 "Unsupported CONCAT_VECTORS for value type");
5414 // We support concatenate two MMX registers and place them in a MMX register.
5415 // This is better than doing a stack convert.
5416 if (ResVT.is128BitVector())
5417 return LowerMMXCONCAT_VECTORS(Op, DAG);
5419 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5420 // from two other 128-bit ones.
5421 return LowerAVXCONCAT_VECTORS(Op, DAG);
5424 // v8i16 shuffles - Prefer shuffles in the following order:
5425 // 1. [all] pshuflw, pshufhw, optional move
5426 // 2. [ssse3] 1 x pshufb
5427 // 3. [ssse3] 2 x pshufb + 1 x por
5428 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5430 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5431 SelectionDAG &DAG) const {
5432 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5433 SDValue V1 = SVOp->getOperand(0);
5434 SDValue V2 = SVOp->getOperand(1);
5435 DebugLoc dl = SVOp->getDebugLoc();
5436 SmallVector<int, 8> MaskVals;
5438 // Determine if more than 1 of the words in each of the low and high quadwords
5439 // of the result come from the same quadword of one of the two inputs. Undef
5440 // mask values count as coming from any quadword, for better codegen.
5441 unsigned LoQuad[] = { 0, 0, 0, 0 };
5442 unsigned HiQuad[] = { 0, 0, 0, 0 };
5443 BitVector InputQuads(4);
5444 for (unsigned i = 0; i < 8; ++i) {
5445 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5446 int EltIdx = SVOp->getMaskElt(i);
5447 MaskVals.push_back(EltIdx);
5456 InputQuads.set(EltIdx / 4);
5459 int BestLoQuad = -1;
5460 unsigned MaxQuad = 1;
5461 for (unsigned i = 0; i < 4; ++i) {
5462 if (LoQuad[i] > MaxQuad) {
5464 MaxQuad = LoQuad[i];
5468 int BestHiQuad = -1;
5470 for (unsigned i = 0; i < 4; ++i) {
5471 if (HiQuad[i] > MaxQuad) {
5473 MaxQuad = HiQuad[i];
5477 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5478 // of the two input vectors, shuffle them into one input vector so only a
5479 // single pshufb instruction is necessary. If There are more than 2 input
5480 // quads, disable the next transformation since it does not help SSSE3.
5481 bool V1Used = InputQuads[0] || InputQuads[1];
5482 bool V2Used = InputQuads[2] || InputQuads[3];
5483 if (Subtarget->hasSSSE3orAVX()) {
5484 if (InputQuads.count() == 2 && V1Used && V2Used) {
5485 BestLoQuad = InputQuads.find_first();
5486 BestHiQuad = InputQuads.find_next(BestLoQuad);
5488 if (InputQuads.count() > 2) {
5494 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5495 // the shuffle mask. If a quad is scored as -1, that means that it contains
5496 // words from all 4 input quadwords.
5498 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5499 SmallVector<int, 8> MaskV;
5500 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5501 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5502 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5503 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5504 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5505 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5507 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5508 // source words for the shuffle, to aid later transformations.
5509 bool AllWordsInNewV = true;
5510 bool InOrder[2] = { true, true };
5511 for (unsigned i = 0; i != 8; ++i) {
5512 int idx = MaskVals[i];
5514 InOrder[i/4] = false;
5515 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5517 AllWordsInNewV = false;
5521 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5522 if (AllWordsInNewV) {
5523 for (int i = 0; i != 8; ++i) {
5524 int idx = MaskVals[i];
5527 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5528 if ((idx != i) && idx < 4)
5530 if ((idx != i) && idx > 3)
5539 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5540 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5541 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5542 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5543 unsigned TargetMask = 0;
5544 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5545 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5546 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5547 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5548 V1 = NewV.getOperand(0);
5549 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5553 // If we have SSSE3, and all words of the result are from 1 input vector,
5554 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5555 // is present, fall back to case 4.
5556 if (Subtarget->hasSSSE3orAVX()) {
5557 SmallVector<SDValue,16> pshufbMask;
5559 // If we have elements from both input vectors, set the high bit of the
5560 // shuffle mask element to zero out elements that come from V2 in the V1
5561 // mask, and elements that come from V1 in the V2 mask, so that the two
5562 // results can be OR'd together.
5563 bool TwoInputs = V1Used && V2Used;
5564 for (unsigned i = 0; i != 8; ++i) {
5565 int EltIdx = MaskVals[i] * 2;
5566 if (TwoInputs && (EltIdx >= 16)) {
5567 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5568 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5571 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5572 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5574 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5575 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5576 DAG.getNode(ISD::BUILD_VECTOR, dl,
5577 MVT::v16i8, &pshufbMask[0], 16));
5579 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5581 // Calculate the shuffle mask for the second input, shuffle it, and
5582 // OR it with the first shuffled input.
5584 for (unsigned i = 0; i != 8; ++i) {
5585 int EltIdx = MaskVals[i] * 2;
5587 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5588 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5591 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5592 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5594 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5595 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5596 DAG.getNode(ISD::BUILD_VECTOR, dl,
5597 MVT::v16i8, &pshufbMask[0], 16));
5598 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5599 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5602 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5603 // and update MaskVals with new element order.
5604 BitVector InOrder(8);
5605 if (BestLoQuad >= 0) {
5606 SmallVector<int, 8> MaskV;
5607 for (int i = 0; i != 4; ++i) {
5608 int idx = MaskVals[i];
5610 MaskV.push_back(-1);
5612 } else if ((idx / 4) == BestLoQuad) {
5613 MaskV.push_back(idx & 3);
5616 MaskV.push_back(-1);
5619 for (unsigned i = 4; i != 8; ++i)
5621 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5624 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3orAVX())
5625 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5627 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5631 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5632 // and update MaskVals with the new element order.
5633 if (BestHiQuad >= 0) {
5634 SmallVector<int, 8> MaskV;
5635 for (unsigned i = 0; i != 4; ++i)
5637 for (unsigned i = 4; i != 8; ++i) {
5638 int idx = MaskVals[i];
5640 MaskV.push_back(-1);
5642 } else if ((idx / 4) == BestHiQuad) {
5643 MaskV.push_back((idx & 3) + 4);
5646 MaskV.push_back(-1);
5649 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5652 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3orAVX())
5653 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5655 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5659 // In case BestHi & BestLo were both -1, which means each quadword has a word
5660 // from each of the four input quadwords, calculate the InOrder bitvector now
5661 // before falling through to the insert/extract cleanup.
5662 if (BestLoQuad == -1 && BestHiQuad == -1) {
5664 for (int i = 0; i != 8; ++i)
5665 if (MaskVals[i] < 0 || MaskVals[i] == i)
5669 // The other elements are put in the right place using pextrw and pinsrw.
5670 for (unsigned i = 0; i != 8; ++i) {
5673 int EltIdx = MaskVals[i];
5676 SDValue ExtOp = (EltIdx < 8)
5677 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5678 DAG.getIntPtrConstant(EltIdx))
5679 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5680 DAG.getIntPtrConstant(EltIdx - 8));
5681 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5682 DAG.getIntPtrConstant(i));
5687 // v16i8 shuffles - Prefer shuffles in the following order:
5688 // 1. [ssse3] 1 x pshufb
5689 // 2. [ssse3] 2 x pshufb + 1 x por
5690 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5692 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5694 const X86TargetLowering &TLI) {
5695 SDValue V1 = SVOp->getOperand(0);
5696 SDValue V2 = SVOp->getOperand(1);
5697 DebugLoc dl = SVOp->getDebugLoc();
5698 SmallVector<int, 16> MaskVals;
5699 SVOp->getMask(MaskVals);
5701 // If we have SSSE3, case 1 is generated when all result bytes come from
5702 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5703 // present, fall back to case 3.
5704 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5707 for (unsigned i = 0; i < 16; ++i) {
5708 int EltIdx = MaskVals[i];
5717 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5718 if (TLI.getSubtarget()->hasSSSE3orAVX()) {
5719 SmallVector<SDValue,16> pshufbMask;
5721 // If all result elements are from one input vector, then only translate
5722 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5724 // Otherwise, we have elements from both input vectors, and must zero out
5725 // elements that come from V2 in the first mask, and V1 in the second mask
5726 // so that we can OR them together.
5727 bool TwoInputs = !(V1Only || V2Only);
5728 for (unsigned i = 0; i != 16; ++i) {
5729 int EltIdx = MaskVals[i];
5730 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5731 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5734 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5736 // If all the elements are from V2, assign it to V1 and return after
5737 // building the first pshufb.
5740 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5741 DAG.getNode(ISD::BUILD_VECTOR, dl,
5742 MVT::v16i8, &pshufbMask[0], 16));
5746 // Calculate the shuffle mask for the second input, shuffle it, and
5747 // OR it with the first shuffled input.
5749 for (unsigned i = 0; i != 16; ++i) {
5750 int EltIdx = MaskVals[i];
5752 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5755 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5757 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5758 DAG.getNode(ISD::BUILD_VECTOR, dl,
5759 MVT::v16i8, &pshufbMask[0], 16));
5760 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5763 // No SSSE3 - Calculate in place words and then fix all out of place words
5764 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5765 // the 16 different words that comprise the two doublequadword input vectors.
5766 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5767 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5768 SDValue NewV = V2Only ? V2 : V1;
5769 for (int i = 0; i != 8; ++i) {
5770 int Elt0 = MaskVals[i*2];
5771 int Elt1 = MaskVals[i*2+1];
5773 // This word of the result is all undef, skip it.
5774 if (Elt0 < 0 && Elt1 < 0)
5777 // This word of the result is already in the correct place, skip it.
5778 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5780 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5783 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5784 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5787 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5788 // using a single extract together, load it and store it.
5789 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5790 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5791 DAG.getIntPtrConstant(Elt1 / 2));
5792 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5793 DAG.getIntPtrConstant(i));
5797 // If Elt1 is defined, extract it from the appropriate source. If the
5798 // source byte is not also odd, shift the extracted word left 8 bits
5799 // otherwise clear the bottom 8 bits if we need to do an or.
5801 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5802 DAG.getIntPtrConstant(Elt1 / 2));
5803 if ((Elt1 & 1) == 0)
5804 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5806 TLI.getShiftAmountTy(InsElt.getValueType())));
5808 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5809 DAG.getConstant(0xFF00, MVT::i16));
5811 // If Elt0 is defined, extract it from the appropriate source. If the
5812 // source byte is not also even, shift the extracted word right 8 bits. If
5813 // Elt1 was also defined, OR the extracted values together before
5814 // inserting them in the result.
5816 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5817 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5818 if ((Elt0 & 1) != 0)
5819 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5821 TLI.getShiftAmountTy(InsElt0.getValueType())));
5823 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5824 DAG.getConstant(0x00FF, MVT::i16));
5825 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5828 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5829 DAG.getIntPtrConstant(i));
5831 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5834 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5835 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5836 /// done when every pair / quad of shuffle mask elements point to elements in
5837 /// the right sequence. e.g.
5838 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5840 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5841 SelectionDAG &DAG, DebugLoc dl) {
5842 EVT VT = SVOp->getValueType(0);
5843 SDValue V1 = SVOp->getOperand(0);
5844 SDValue V2 = SVOp->getOperand(1);
5845 unsigned NumElems = VT.getVectorNumElements();
5846 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5848 switch (VT.getSimpleVT().SimpleTy) {
5849 default: assert(false && "Unexpected!");
5850 case MVT::v4f32: NewVT = MVT::v2f64; break;
5851 case MVT::v4i32: NewVT = MVT::v2i64; break;
5852 case MVT::v8i16: NewVT = MVT::v4i32; break;
5853 case MVT::v16i8: NewVT = MVT::v4i32; break;
5856 int Scale = NumElems / NewWidth;
5857 SmallVector<int, 8> MaskVec;
5858 for (unsigned i = 0; i < NumElems; i += Scale) {
5860 for (int j = 0; j < Scale; ++j) {
5861 int EltIdx = SVOp->getMaskElt(i+j);
5865 StartIdx = EltIdx - (EltIdx % Scale);
5866 if (EltIdx != StartIdx + j)
5870 MaskVec.push_back(-1);
5872 MaskVec.push_back(StartIdx / Scale);
5875 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5876 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5877 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5880 /// getVZextMovL - Return a zero-extending vector move low node.
5882 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5883 SDValue SrcOp, SelectionDAG &DAG,
5884 const X86Subtarget *Subtarget, DebugLoc dl) {
5885 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5886 LoadSDNode *LD = NULL;
5887 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5888 LD = dyn_cast<LoadSDNode>(SrcOp);
5890 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5892 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5893 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5894 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5895 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5896 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5898 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5899 return DAG.getNode(ISD::BITCAST, dl, VT,
5900 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5901 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5909 return DAG.getNode(ISD::BITCAST, dl, VT,
5910 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5911 DAG.getNode(ISD::BITCAST, dl,
5915 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5916 /// shuffle node referes to only one lane in the sources.
5917 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5918 EVT VT = SVOp->getValueType(0);
5919 int NumElems = VT.getVectorNumElements();
5920 int HalfSize = NumElems/2;
5921 SmallVector<int, 16> M;
5923 bool MatchA = false, MatchB = false;
5925 for (int l = 0; l < NumElems*2; l += HalfSize) {
5926 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5932 for (int l = 0; l < NumElems*2; l += HalfSize) {
5933 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5939 return MatchA && MatchB;
5942 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5943 /// which could not be matched by any known target speficic shuffle
5945 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5946 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5947 // If each half of a vector shuffle node referes to only one lane in the
5948 // source vectors, extract each used 128-bit lane and shuffle them using
5949 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5950 // the work to the legalizer.
5951 DebugLoc dl = SVOp->getDebugLoc();
5952 EVT VT = SVOp->getValueType(0);
5953 int NumElems = VT.getVectorNumElements();
5954 int HalfSize = NumElems/2;
5956 // Extract the reference for each half
5957 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5958 int FstVecOpNum = 0, SndVecOpNum = 0;
5959 for (int i = 0; i < HalfSize; ++i) {
5960 int Elt = SVOp->getMaskElt(i);
5961 if (SVOp->getMaskElt(i) < 0)
5963 FstVecOpNum = Elt/NumElems;
5964 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5967 for (int i = HalfSize; i < NumElems; ++i) {
5968 int Elt = SVOp->getMaskElt(i);
5969 if (SVOp->getMaskElt(i) < 0)
5971 SndVecOpNum = Elt/NumElems;
5972 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5976 // Extract the subvectors
5977 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5978 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5979 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5980 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5982 // Generate 128-bit shuffles
5983 SmallVector<int, 16> MaskV1, MaskV2;
5984 for (int i = 0; i < HalfSize; ++i) {
5985 int Elt = SVOp->getMaskElt(i);
5986 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5988 for (int i = HalfSize; i < NumElems; ++i) {
5989 int Elt = SVOp->getMaskElt(i);
5990 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5993 EVT NVT = V1.getValueType();
5994 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5995 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
5997 // Concatenate the result back
5998 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
5999 DAG.getConstant(0, MVT::i32), DAG, dl);
6000 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
6007 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6008 /// 4 elements, and match them with several different shuffle types.
6010 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6011 SDValue V1 = SVOp->getOperand(0);
6012 SDValue V2 = SVOp->getOperand(1);
6013 DebugLoc dl = SVOp->getDebugLoc();
6014 EVT VT = SVOp->getValueType(0);
6016 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6018 SmallVector<std::pair<int, int>, 8> Locs;
6020 SmallVector<int, 8> Mask1(4U, -1);
6021 SmallVector<int, 8> PermMask;
6022 SVOp->getMask(PermMask);
6026 for (unsigned i = 0; i != 4; ++i) {
6027 int Idx = PermMask[i];
6029 Locs[i] = std::make_pair(-1, -1);
6031 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6033 Locs[i] = std::make_pair(0, NumLo);
6037 Locs[i] = std::make_pair(1, NumHi);
6039 Mask1[2+NumHi] = Idx;
6045 if (NumLo <= 2 && NumHi <= 2) {
6046 // If no more than two elements come from either vector. This can be
6047 // implemented with two shuffles. First shuffle gather the elements.
6048 // The second shuffle, which takes the first shuffle as both of its
6049 // vector operands, put the elements into the right order.
6050 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6052 SmallVector<int, 8> Mask2(4U, -1);
6054 for (unsigned i = 0; i != 4; ++i) {
6055 if (Locs[i].first == -1)
6058 unsigned Idx = (i < 2) ? 0 : 4;
6059 Idx += Locs[i].first * 2 + Locs[i].second;
6064 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6065 } else if (NumLo == 3 || NumHi == 3) {
6066 // Otherwise, we must have three elements from one vector, call it X, and
6067 // one element from the other, call it Y. First, use a shufps to build an
6068 // intermediate vector with the one element from Y and the element from X
6069 // that will be in the same half in the final destination (the indexes don't
6070 // matter). Then, use a shufps to build the final vector, taking the half
6071 // containing the element from Y from the intermediate, and the other half
6074 // Normalize it so the 3 elements come from V1.
6075 CommuteVectorShuffleMask(PermMask, 4);
6079 // Find the element from V2.
6081 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6082 int Val = PermMask[HiIndex];
6089 Mask1[0] = PermMask[HiIndex];
6091 Mask1[2] = PermMask[HiIndex^1];
6093 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6096 Mask1[0] = PermMask[0];
6097 Mask1[1] = PermMask[1];
6098 Mask1[2] = HiIndex & 1 ? 6 : 4;
6099 Mask1[3] = HiIndex & 1 ? 4 : 6;
6100 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6102 Mask1[0] = HiIndex & 1 ? 2 : 0;
6103 Mask1[1] = HiIndex & 1 ? 0 : 2;
6104 Mask1[2] = PermMask[2];
6105 Mask1[3] = PermMask[3];
6110 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6114 // Break it into (shuffle shuffle_hi, shuffle_lo).
6117 SmallVector<int,8> LoMask(4U, -1);
6118 SmallVector<int,8> HiMask(4U, -1);
6120 SmallVector<int,8> *MaskPtr = &LoMask;
6121 unsigned MaskIdx = 0;
6124 for (unsigned i = 0; i != 4; ++i) {
6131 int Idx = PermMask[i];
6133 Locs[i] = std::make_pair(-1, -1);
6134 } else if (Idx < 4) {
6135 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6136 (*MaskPtr)[LoIdx] = Idx;
6139 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6140 (*MaskPtr)[HiIdx] = Idx;
6145 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6146 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6147 SmallVector<int, 8> MaskOps;
6148 for (unsigned i = 0; i != 4; ++i) {
6149 if (Locs[i].first == -1) {
6150 MaskOps.push_back(-1);
6152 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6153 MaskOps.push_back(Idx);
6156 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6159 static bool MayFoldVectorLoad(SDValue V) {
6160 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6161 V = V.getOperand(0);
6162 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6163 V = V.getOperand(0);
6164 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6165 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6166 // BUILD_VECTOR (load), undef
6167 V = V.getOperand(0);
6173 // FIXME: the version above should always be used. Since there's
6174 // a bug where several vector shuffles can't be folded because the
6175 // DAG is not updated during lowering and a node claims to have two
6176 // uses while it only has one, use this version, and let isel match
6177 // another instruction if the load really happens to have more than
6178 // one use. Remove this version after this bug get fixed.
6179 // rdar://8434668, PR8156
6180 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6181 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6182 V = V.getOperand(0);
6183 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6184 V = V.getOperand(0);
6185 if (ISD::isNormalLoad(V.getNode()))
6190 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6191 /// a vector extract, and if both can be later optimized into a single load.
6192 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6193 /// here because otherwise a target specific shuffle node is going to be
6194 /// emitted for this shuffle, and the optimization not done.
6195 /// FIXME: This is probably not the best approach, but fix the problem
6196 /// until the right path is decided.
6198 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6199 const TargetLowering &TLI) {
6200 EVT VT = V.getValueType();
6201 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6203 // Be sure that the vector shuffle is present in a pattern like this:
6204 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6208 SDNode *N = *V.getNode()->use_begin();
6209 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6212 SDValue EltNo = N->getOperand(1);
6213 if (!isa<ConstantSDNode>(EltNo))
6216 // If the bit convert changed the number of elements, it is unsafe
6217 // to examine the mask.
6218 bool HasShuffleIntoBitcast = false;
6219 if (V.getOpcode() == ISD::BITCAST) {
6220 EVT SrcVT = V.getOperand(0).getValueType();
6221 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6223 V = V.getOperand(0);
6224 HasShuffleIntoBitcast = true;
6227 // Select the input vector, guarding against out of range extract vector.
6228 unsigned NumElems = VT.getVectorNumElements();
6229 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6230 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6231 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6233 // Skip one more bit_convert if necessary
6234 if (V.getOpcode() == ISD::BITCAST)
6235 V = V.getOperand(0);
6237 if (ISD::isNormalLoad(V.getNode())) {
6238 // Is the original load suitable?
6239 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6241 // FIXME: avoid the multi-use bug that is preventing lots of
6242 // of foldings to be detected, this is still wrong of course, but
6243 // give the temporary desired behavior, and if it happens that
6244 // the load has real more uses, during isel it will not fold, and
6245 // will generate poor code.
6246 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
6249 if (!HasShuffleIntoBitcast)
6252 // If there's a bitcast before the shuffle, check if the load type and
6253 // alignment is valid.
6254 unsigned Align = LN0->getAlignment();
6256 TLI.getTargetData()->getABITypeAlignment(
6257 VT.getTypeForEVT(*DAG.getContext()));
6259 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6267 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6268 EVT VT = Op.getValueType();
6270 // Canonizalize to v2f64.
6271 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6272 return DAG.getNode(ISD::BITCAST, dl, VT,
6273 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6278 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6280 SDValue V1 = Op.getOperand(0);
6281 SDValue V2 = Op.getOperand(1);
6282 EVT VT = Op.getValueType();
6284 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6286 if (HasXMMInt && VT == MVT::v2f64)
6287 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6289 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6290 return DAG.getNode(ISD::BITCAST, dl, VT,
6291 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6292 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6293 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6297 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6298 SDValue V1 = Op.getOperand(0);
6299 SDValue V2 = Op.getOperand(1);
6300 EVT VT = Op.getValueType();
6302 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6303 "unsupported shuffle type");
6305 if (V2.getOpcode() == ISD::UNDEF)
6309 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6312 static inline unsigned getSHUFPOpcode(EVT VT) {
6313 switch(VT.getSimpleVT().SimpleTy) {
6314 case MVT::v8i32: // Use fp unit for int unpack.
6316 case MVT::v4i32: // Use fp unit for int unpack.
6317 case MVT::v4f32: return X86ISD::SHUFPS;
6318 case MVT::v4i64: // Use fp unit for int unpack.
6320 case MVT::v2i64: // Use fp unit for int unpack.
6321 case MVT::v2f64: return X86ISD::SHUFPD;
6323 llvm_unreachable("Unknown type for shufp*");
6329 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasXMMInt) {
6330 SDValue V1 = Op.getOperand(0);
6331 SDValue V2 = Op.getOperand(1);
6332 EVT VT = Op.getValueType();
6333 unsigned NumElems = VT.getVectorNumElements();
6335 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6336 // operand of these instructions is only memory, so check if there's a
6337 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6339 bool CanFoldLoad = false;
6341 // Trivial case, when V2 comes from a load.
6342 if (MayFoldVectorLoad(V2))
6345 // When V1 is a load, it can be folded later into a store in isel, example:
6346 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6348 // (MOVLPSmr addr:$src1, VR128:$src2)
6349 // So, recognize this potential and also use MOVLPS or MOVLPD
6350 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6353 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6355 if (HasXMMInt && NumElems == 2)
6356 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6359 // If we don't care about the second element, procede to use movss.
6360 if (SVOp->getMaskElt(1) != -1)
6361 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6364 // movl and movlp will both match v2i64, but v2i64 is never matched by
6365 // movl earlier because we make it strict to avoid messing with the movlp load
6366 // folding logic (see the code above getMOVLP call). Match it here then,
6367 // this is horrible, but will stay like this until we move all shuffle
6368 // matching to x86 specific nodes. Note that for the 1st condition all
6369 // types are matched with movsd.
6371 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6372 // as to remove this logic from here, as much as possible
6373 if (NumElems == 2 || !X86::isMOVLMask(SVOp))
6374 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6375 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6378 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6380 // Invert the operand order and use SHUFPS to match it.
6381 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1,
6382 X86::getShuffleSHUFImmediate(SVOp), DAG);
6386 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6387 const TargetLowering &TLI,
6388 const X86Subtarget *Subtarget) {
6389 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6390 EVT VT = Op.getValueType();
6391 DebugLoc dl = Op.getDebugLoc();
6392 SDValue V1 = Op.getOperand(0);
6393 SDValue V2 = Op.getOperand(1);
6395 if (isZeroShuffle(SVOp))
6396 return getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl);
6398 // Handle splat operations
6399 if (SVOp->isSplat()) {
6400 unsigned NumElem = VT.getVectorNumElements();
6401 int Size = VT.getSizeInBits();
6402 // Special case, this is the only place now where it's allowed to return
6403 // a vector_shuffle operation without using a target specific node, because
6404 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6405 // this be moved to DAGCombine instead?
6406 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6409 // Use vbroadcast whenever the splat comes from a foldable load
6410 SDValue LD = isVectorBroadcast(Op, Subtarget->hasAVX2());
6411 if (Subtarget->hasAVX() && LD.getNode())
6412 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6414 // Handle splats by matching through known shuffle masks
6415 if ((Size == 128 && NumElem <= 4) ||
6416 (Size == 256 && NumElem < 8))
6419 // All remaning splats are promoted to target supported vector shuffles.
6420 return PromoteSplat(SVOp, DAG);
6423 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6425 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6426 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6427 if (NewOp.getNode())
6428 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6429 } else if ((VT == MVT::v4i32 ||
6430 (VT == MVT::v4f32 && Subtarget->hasXMMInt()))) {
6431 // FIXME: Figure out a cleaner way to do this.
6432 // Try to make use of movq to zero out the top part.
6433 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6434 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6435 if (NewOp.getNode()) {
6436 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6437 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6438 DAG, Subtarget, dl);
6440 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6441 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6442 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6443 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6444 DAG, Subtarget, dl);
6451 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6452 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6453 SDValue V1 = Op.getOperand(0);
6454 SDValue V2 = Op.getOperand(1);
6455 EVT VT = Op.getValueType();
6456 DebugLoc dl = Op.getDebugLoc();
6457 unsigned NumElems = VT.getVectorNumElements();
6458 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6459 bool V1IsSplat = false;
6460 bool V2IsSplat = false;
6461 bool HasXMMInt = Subtarget->hasXMMInt();
6462 bool HasAVX = Subtarget->hasAVX();
6463 bool HasAVX2 = Subtarget->hasAVX2();
6464 MachineFunction &MF = DAG.getMachineFunction();
6465 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6467 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6469 assert(V1.getOpcode() != ISD::UNDEF && "Op 1 of shuffle should not be undef");
6471 // Vector shuffle lowering takes 3 steps:
6473 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6474 // narrowing and commutation of operands should be handled.
6475 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6477 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6478 // so the shuffle can be broken into other shuffles and the legalizer can
6479 // try the lowering again.
6481 // The general idea is that no vector_shuffle operation should be left to
6482 // be matched during isel, all of them must be converted to a target specific
6485 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6486 // narrowing and commutation of operands should be handled. The actual code
6487 // doesn't include all of those, work in progress...
6488 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6489 if (NewOp.getNode())
6492 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6493 // unpckh_undef). Only use pshufd if speed is more important than size.
6494 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2))
6495 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6496 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2))
6497 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6499 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3orAVX() &&
6500 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6501 return getMOVDDup(Op, dl, V1, DAG);
6503 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6504 return getMOVHighToLow(Op, dl, DAG);
6506 // Use to match splats
6507 if (HasXMMInt && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef &&
6508 (VT == MVT::v2f64 || VT == MVT::v2i64))
6509 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6511 if (X86::isPSHUFDMask(SVOp)) {
6512 // The actual implementation will match the mask in the if above and then
6513 // during isel it can match several different instructions, not only pshufd
6514 // as its name says, sad but true, emulate the behavior for now...
6515 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6516 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6518 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6520 if (HasXMMInt && (VT == MVT::v4f32 || VT == MVT::v4i32))
6521 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6523 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1,
6527 // Check if this can be converted into a logical shift.
6528 bool isLeft = false;
6531 bool isShift = HasXMMInt && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6532 if (isShift && ShVal.hasOneUse()) {
6533 // If the shifted value has multiple uses, it may be cheaper to use
6534 // v_set0 + movlhps or movhlps, etc.
6535 EVT EltVT = VT.getVectorElementType();
6536 ShAmt *= EltVT.getSizeInBits();
6537 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6540 if (X86::isMOVLMask(SVOp)) {
6541 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6542 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6543 if (!X86::isMOVLPMask(SVOp)) {
6544 if (HasXMMInt && (VT == MVT::v2i64 || VT == MVT::v2f64))
6545 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6547 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6548 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6552 // FIXME: fold these into legal mask.
6553 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2))
6554 return getMOVLowToHigh(Op, dl, DAG, HasXMMInt);
6556 if (X86::isMOVHLPSMask(SVOp))
6557 return getMOVHighToLow(Op, dl, DAG);
6559 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6560 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6562 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6563 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6565 if (X86::isMOVLPMask(SVOp))
6566 return getMOVLP(Op, dl, DAG, HasXMMInt);
6568 if (ShouldXformToMOVHLPS(SVOp) ||
6569 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6570 return CommuteVectorShuffle(SVOp, DAG);
6573 // No better options. Use a vshl / vsrl.
6574 EVT EltVT = VT.getVectorElementType();
6575 ShAmt *= EltVT.getSizeInBits();
6576 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6579 bool Commuted = false;
6580 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6581 // 1,1,1,1 -> v8i16 though.
6582 V1IsSplat = isSplatVector(V1.getNode());
6583 V2IsSplat = isSplatVector(V2.getNode());
6585 // Canonicalize the splat or undef, if present, to be on the RHS.
6586 if (V1IsSplat && !V2IsSplat) {
6587 Op = CommuteVectorShuffle(SVOp, DAG);
6588 SVOp = cast<ShuffleVectorSDNode>(Op);
6589 V1 = SVOp->getOperand(0);
6590 V2 = SVOp->getOperand(1);
6591 std::swap(V1IsSplat, V2IsSplat);
6595 SmallVector<int, 32> M;
6598 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6599 // Shuffling low element of v1 into undef, just return v1.
6602 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6603 // the instruction selector will not match, so get a canonical MOVL with
6604 // swapped operands to undo the commute.
6605 return getMOVL(DAG, dl, VT, V2, V1);
6608 if (isUNPCKLMask(M, VT, HasAVX2))
6609 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6611 if (isUNPCKHMask(M, VT, HasAVX2))
6612 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6615 // Normalize mask so all entries that point to V2 points to its first
6616 // element then try to match unpck{h|l} again. If match, return a
6617 // new vector_shuffle with the corrected mask.
6618 SDValue NewMask = NormalizeMask(SVOp, DAG);
6619 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6620 if (NSVOp != SVOp) {
6621 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) {
6623 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) {
6630 // Commute is back and try unpck* again.
6631 // FIXME: this seems wrong.
6632 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6633 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6635 if (X86::isUNPCKLMask(NewSVOp, HasAVX2))
6636 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG);
6638 if (X86::isUNPCKHMask(NewSVOp, HasAVX2))
6639 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG);
6642 // Normalize the node to match x86 shuffle ops if needed
6643 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true) ||
6644 isVSHUFPYMask(M, VT, HasAVX, /* Commuted */ true)))
6645 return CommuteVectorShuffle(SVOp, DAG);
6647 // The checks below are all present in isShuffleMaskLegal, but they are
6648 // inlined here right now to enable us to directly emit target specific
6649 // nodes, and remove one by one until they don't return Op anymore.
6651 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX()))
6652 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6653 getShufflePALIGNRImmediate(SVOp),
6656 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6657 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6658 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6659 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6662 if (isPSHUFHWMask(M, VT))
6663 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6664 X86::getShufflePSHUFHWImmediate(SVOp),
6667 if (isPSHUFLWMask(M, VT))
6668 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6669 X86::getShufflePSHUFLWImmediate(SVOp),
6672 if (isSHUFPMask(M, VT))
6673 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6674 X86::getShuffleSHUFImmediate(SVOp), DAG);
6676 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6677 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6678 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6679 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6681 //===--------------------------------------------------------------------===//
6682 // Generate target specific nodes for 128 or 256-bit shuffles only
6683 // supported in the AVX instruction set.
6686 // Handle VMOVDDUPY permutations
6687 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6688 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6690 // Handle VPERMILPS/D* permutations
6691 if (isVPERMILPMask(M, VT, HasAVX))
6692 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6693 getShuffleVPERMILPImmediate(SVOp), DAG);
6695 // Handle VPERM2F128/VPERM2I128 permutations
6696 if (isVPERM2X128Mask(M, VT, HasAVX))
6697 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6698 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6700 // Handle VSHUFPS/DY permutations
6701 if (isVSHUFPYMask(M, VT, HasAVX))
6702 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6703 getShuffleVSHUFPYImmediate(SVOp), DAG);
6705 //===--------------------------------------------------------------------===//
6706 // Since no target specific shuffle was selected for this generic one,
6707 // lower it into other known shuffles. FIXME: this isn't true yet, but
6708 // this is the plan.
6711 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6712 if (VT == MVT::v8i16) {
6713 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6714 if (NewOp.getNode())
6718 if (VT == MVT::v16i8) {
6719 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6720 if (NewOp.getNode())
6724 // Handle all 128-bit wide vectors with 4 elements, and match them with
6725 // several different shuffle types.
6726 if (NumElems == 4 && VT.getSizeInBits() == 128)
6727 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6729 // Handle general 256-bit shuffles
6730 if (VT.is256BitVector())
6731 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6737 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6738 SelectionDAG &DAG) const {
6739 EVT VT = Op.getValueType();
6740 DebugLoc dl = Op.getDebugLoc();
6742 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6745 if (VT.getSizeInBits() == 8) {
6746 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6747 Op.getOperand(0), Op.getOperand(1));
6748 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6749 DAG.getValueType(VT));
6750 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6751 } else if (VT.getSizeInBits() == 16) {
6752 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6753 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6755 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6756 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6757 DAG.getNode(ISD::BITCAST, dl,
6761 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6762 Op.getOperand(0), Op.getOperand(1));
6763 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6764 DAG.getValueType(VT));
6765 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6766 } else if (VT == MVT::f32) {
6767 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6768 // the result back to FR32 register. It's only worth matching if the
6769 // result has a single use which is a store or a bitcast to i32. And in
6770 // the case of a store, it's not worth it if the index is a constant 0,
6771 // because a MOVSSmr can be used instead, which is smaller and faster.
6772 if (!Op.hasOneUse())
6774 SDNode *User = *Op.getNode()->use_begin();
6775 if ((User->getOpcode() != ISD::STORE ||
6776 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6777 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6778 (User->getOpcode() != ISD::BITCAST ||
6779 User->getValueType(0) != MVT::i32))
6781 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6782 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6785 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6786 } else if (VT == MVT::i32 || VT == MVT::i64) {
6787 // ExtractPS/pextrq works with constant index.
6788 if (isa<ConstantSDNode>(Op.getOperand(1)))
6796 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6797 SelectionDAG &DAG) const {
6798 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6801 SDValue Vec = Op.getOperand(0);
6802 EVT VecVT = Vec.getValueType();
6804 // If this is a 256-bit vector result, first extract the 128-bit vector and
6805 // then extract the element from the 128-bit vector.
6806 if (VecVT.getSizeInBits() == 256) {
6807 DebugLoc dl = Op.getNode()->getDebugLoc();
6808 unsigned NumElems = VecVT.getVectorNumElements();
6809 SDValue Idx = Op.getOperand(1);
6810 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6812 // Get the 128-bit vector.
6813 bool Upper = IdxVal >= NumElems/2;
6814 Vec = Extract128BitVector(Vec,
6815 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6817 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6818 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6821 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6823 if (Subtarget->hasSSE41orAVX()) {
6824 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6829 EVT VT = Op.getValueType();
6830 DebugLoc dl = Op.getDebugLoc();
6831 // TODO: handle v16i8.
6832 if (VT.getSizeInBits() == 16) {
6833 SDValue Vec = Op.getOperand(0);
6834 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6836 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6837 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6838 DAG.getNode(ISD::BITCAST, dl,
6841 // Transform it so it match pextrw which produces a 32-bit result.
6842 EVT EltVT = MVT::i32;
6843 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6844 Op.getOperand(0), Op.getOperand(1));
6845 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6846 DAG.getValueType(VT));
6847 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6848 } else if (VT.getSizeInBits() == 32) {
6849 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6853 // SHUFPS the element to the lowest double word, then movss.
6854 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6855 EVT VVT = Op.getOperand(0).getValueType();
6856 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6857 DAG.getUNDEF(VVT), Mask);
6858 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6859 DAG.getIntPtrConstant(0));
6860 } else if (VT.getSizeInBits() == 64) {
6861 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6862 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6863 // to match extract_elt for f64.
6864 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6868 // UNPCKHPD the element to the lowest double word, then movsd.
6869 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6870 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6871 int Mask[2] = { 1, -1 };
6872 EVT VVT = Op.getOperand(0).getValueType();
6873 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6874 DAG.getUNDEF(VVT), Mask);
6875 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6876 DAG.getIntPtrConstant(0));
6883 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6884 SelectionDAG &DAG) const {
6885 EVT VT = Op.getValueType();
6886 EVT EltVT = VT.getVectorElementType();
6887 DebugLoc dl = Op.getDebugLoc();
6889 SDValue N0 = Op.getOperand(0);
6890 SDValue N1 = Op.getOperand(1);
6891 SDValue N2 = Op.getOperand(2);
6893 if (VT.getSizeInBits() == 256)
6896 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6897 isa<ConstantSDNode>(N2)) {
6899 if (VT == MVT::v8i16)
6900 Opc = X86ISD::PINSRW;
6901 else if (VT == MVT::v16i8)
6902 Opc = X86ISD::PINSRB;
6904 Opc = X86ISD::PINSRB;
6906 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6908 if (N1.getValueType() != MVT::i32)
6909 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6910 if (N2.getValueType() != MVT::i32)
6911 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6912 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6913 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6914 // Bits [7:6] of the constant are the source select. This will always be
6915 // zero here. The DAG Combiner may combine an extract_elt index into these
6916 // bits. For example (insert (extract, 3), 2) could be matched by putting
6917 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6918 // Bits [5:4] of the constant are the destination select. This is the
6919 // value of the incoming immediate.
6920 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6921 // combine either bitwise AND or insert of float 0.0 to set these bits.
6922 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6923 // Create this as a scalar to vector..
6924 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6925 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6926 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6927 isa<ConstantSDNode>(N2)) {
6928 // PINSR* works with constant index.
6935 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6936 EVT VT = Op.getValueType();
6937 EVT EltVT = VT.getVectorElementType();
6939 DebugLoc dl = Op.getDebugLoc();
6940 SDValue N0 = Op.getOperand(0);
6941 SDValue N1 = Op.getOperand(1);
6942 SDValue N2 = Op.getOperand(2);
6944 // If this is a 256-bit vector result, first extract the 128-bit vector,
6945 // insert the element into the extracted half and then place it back.
6946 if (VT.getSizeInBits() == 256) {
6947 if (!isa<ConstantSDNode>(N2))
6950 // Get the desired 128-bit vector half.
6951 unsigned NumElems = VT.getVectorNumElements();
6952 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6953 bool Upper = IdxVal >= NumElems/2;
6954 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6955 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6957 // Insert the element into the desired half.
6958 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6959 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6961 // Insert the changed part back to the 256-bit vector
6962 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6965 if (Subtarget->hasSSE41orAVX())
6966 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6968 if (EltVT == MVT::i8)
6971 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6972 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6973 // as its second argument.
6974 if (N1.getValueType() != MVT::i32)
6975 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6976 if (N2.getValueType() != MVT::i32)
6977 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6978 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6984 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6985 LLVMContext *Context = DAG.getContext();
6986 DebugLoc dl = Op.getDebugLoc();
6987 EVT OpVT = Op.getValueType();
6989 // If this is a 256-bit vector result, first insert into a 128-bit
6990 // vector and then insert into the 256-bit vector.
6991 if (OpVT.getSizeInBits() > 128) {
6992 // Insert into a 128-bit vector.
6993 EVT VT128 = EVT::getVectorVT(*Context,
6994 OpVT.getVectorElementType(),
6995 OpVT.getVectorNumElements() / 2);
6997 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6999 // Insert the 128-bit vector.
7000 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
7001 DAG.getConstant(0, MVT::i32),
7005 if (Op.getValueType() == MVT::v1i64 &&
7006 Op.getOperand(0).getValueType() == MVT::i64)
7007 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7009 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7010 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
7011 "Expected an SSE type!");
7012 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7013 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7016 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7017 // a simple subregister reference or explicit instructions to grab
7018 // upper bits of a vector.
7020 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7021 if (Subtarget->hasAVX()) {
7022 DebugLoc dl = Op.getNode()->getDebugLoc();
7023 SDValue Vec = Op.getNode()->getOperand(0);
7024 SDValue Idx = Op.getNode()->getOperand(1);
7026 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7027 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7028 return Extract128BitVector(Vec, Idx, DAG, dl);
7034 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7035 // simple superregister reference or explicit instructions to insert
7036 // the upper bits of a vector.
7038 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7039 if (Subtarget->hasAVX()) {
7040 DebugLoc dl = Op.getNode()->getDebugLoc();
7041 SDValue Vec = Op.getNode()->getOperand(0);
7042 SDValue SubVec = Op.getNode()->getOperand(1);
7043 SDValue Idx = Op.getNode()->getOperand(2);
7045 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7046 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7047 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7053 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7054 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7055 // one of the above mentioned nodes. It has to be wrapped because otherwise
7056 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7057 // be used to form addressing mode. These wrapped nodes will be selected
7060 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7061 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7063 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7065 unsigned char OpFlag = 0;
7066 unsigned WrapperKind = X86ISD::Wrapper;
7067 CodeModel::Model M = getTargetMachine().getCodeModel();
7069 if (Subtarget->isPICStyleRIPRel() &&
7070 (M == CodeModel::Small || M == CodeModel::Kernel))
7071 WrapperKind = X86ISD::WrapperRIP;
7072 else if (Subtarget->isPICStyleGOT())
7073 OpFlag = X86II::MO_GOTOFF;
7074 else if (Subtarget->isPICStyleStubPIC())
7075 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7077 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7079 CP->getOffset(), OpFlag);
7080 DebugLoc DL = CP->getDebugLoc();
7081 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7082 // With PIC, the address is actually $g + Offset.
7084 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7085 DAG.getNode(X86ISD::GlobalBaseReg,
7086 DebugLoc(), getPointerTy()),
7093 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7094 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7096 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7098 unsigned char OpFlag = 0;
7099 unsigned WrapperKind = X86ISD::Wrapper;
7100 CodeModel::Model M = getTargetMachine().getCodeModel();
7102 if (Subtarget->isPICStyleRIPRel() &&
7103 (M == CodeModel::Small || M == CodeModel::Kernel))
7104 WrapperKind = X86ISD::WrapperRIP;
7105 else if (Subtarget->isPICStyleGOT())
7106 OpFlag = X86II::MO_GOTOFF;
7107 else if (Subtarget->isPICStyleStubPIC())
7108 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7110 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7112 DebugLoc DL = JT->getDebugLoc();
7113 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7115 // With PIC, the address is actually $g + Offset.
7117 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7118 DAG.getNode(X86ISD::GlobalBaseReg,
7119 DebugLoc(), getPointerTy()),
7126 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7127 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7129 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7131 unsigned char OpFlag = 0;
7132 unsigned WrapperKind = X86ISD::Wrapper;
7133 CodeModel::Model M = getTargetMachine().getCodeModel();
7135 if (Subtarget->isPICStyleRIPRel() &&
7136 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7137 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7138 OpFlag = X86II::MO_GOTPCREL;
7139 WrapperKind = X86ISD::WrapperRIP;
7140 } else if (Subtarget->isPICStyleGOT()) {
7141 OpFlag = X86II::MO_GOT;
7142 } else if (Subtarget->isPICStyleStubPIC()) {
7143 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7144 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7145 OpFlag = X86II::MO_DARWIN_NONLAZY;
7148 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7150 DebugLoc DL = Op.getDebugLoc();
7151 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7154 // With PIC, the address is actually $g + Offset.
7155 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7156 !Subtarget->is64Bit()) {
7157 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7158 DAG.getNode(X86ISD::GlobalBaseReg,
7159 DebugLoc(), getPointerTy()),
7163 // For symbols that require a load from a stub to get the address, emit the
7165 if (isGlobalStubReference(OpFlag))
7166 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7167 MachinePointerInfo::getGOT(), false, false, false, 0);
7173 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7174 // Create the TargetBlockAddressAddress node.
7175 unsigned char OpFlags =
7176 Subtarget->ClassifyBlockAddressReference();
7177 CodeModel::Model M = getTargetMachine().getCodeModel();
7178 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7179 DebugLoc dl = Op.getDebugLoc();
7180 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7181 /*isTarget=*/true, OpFlags);
7183 if (Subtarget->isPICStyleRIPRel() &&
7184 (M == CodeModel::Small || M == CodeModel::Kernel))
7185 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7187 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7189 // With PIC, the address is actually $g + Offset.
7190 if (isGlobalRelativeToPICBase(OpFlags)) {
7191 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7192 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7200 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7202 SelectionDAG &DAG) const {
7203 // Create the TargetGlobalAddress node, folding in the constant
7204 // offset if it is legal.
7205 unsigned char OpFlags =
7206 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7207 CodeModel::Model M = getTargetMachine().getCodeModel();
7209 if (OpFlags == X86II::MO_NO_FLAG &&
7210 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7211 // A direct static reference to a global.
7212 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7215 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7218 if (Subtarget->isPICStyleRIPRel() &&
7219 (M == CodeModel::Small || M == CodeModel::Kernel))
7220 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7222 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7224 // With PIC, the address is actually $g + Offset.
7225 if (isGlobalRelativeToPICBase(OpFlags)) {
7226 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7227 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7231 // For globals that require a load from a stub to get the address, emit the
7233 if (isGlobalStubReference(OpFlags))
7234 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7235 MachinePointerInfo::getGOT(), false, false, false, 0);
7237 // If there was a non-zero offset that we didn't fold, create an explicit
7240 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7241 DAG.getConstant(Offset, getPointerTy()));
7247 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7248 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7249 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7250 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7254 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7255 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7256 unsigned char OperandFlags) {
7257 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7258 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7259 DebugLoc dl = GA->getDebugLoc();
7260 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7261 GA->getValueType(0),
7265 SDValue Ops[] = { Chain, TGA, *InFlag };
7266 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7268 SDValue Ops[] = { Chain, TGA };
7269 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7272 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7273 MFI->setAdjustsStack(true);
7275 SDValue Flag = Chain.getValue(1);
7276 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7279 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7281 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7284 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7285 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7286 DAG.getNode(X86ISD::GlobalBaseReg,
7287 DebugLoc(), PtrVT), InFlag);
7288 InFlag = Chain.getValue(1);
7290 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7293 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7295 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7297 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7298 X86::RAX, X86II::MO_TLSGD);
7301 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7302 // "local exec" model.
7303 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7304 const EVT PtrVT, TLSModel::Model model,
7306 DebugLoc dl = GA->getDebugLoc();
7308 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7309 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7310 is64Bit ? 257 : 256));
7312 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7313 DAG.getIntPtrConstant(0),
7314 MachinePointerInfo(Ptr),
7315 false, false, false, 0);
7317 unsigned char OperandFlags = 0;
7318 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7320 unsigned WrapperKind = X86ISD::Wrapper;
7321 if (model == TLSModel::LocalExec) {
7322 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7323 } else if (is64Bit) {
7324 assert(model == TLSModel::InitialExec);
7325 OperandFlags = X86II::MO_GOTTPOFF;
7326 WrapperKind = X86ISD::WrapperRIP;
7328 assert(model == TLSModel::InitialExec);
7329 OperandFlags = X86II::MO_INDNTPOFF;
7332 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7334 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7335 GA->getValueType(0),
7336 GA->getOffset(), OperandFlags);
7337 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7339 if (model == TLSModel::InitialExec)
7340 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7341 MachinePointerInfo::getGOT(), false, false, false, 0);
7343 // The address of the thread local variable is the add of the thread
7344 // pointer with the offset of the variable.
7345 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7349 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7351 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7352 const GlobalValue *GV = GA->getGlobal();
7354 if (Subtarget->isTargetELF()) {
7355 // TODO: implement the "local dynamic" model
7356 // TODO: implement the "initial exec"model for pic executables
7358 // If GV is an alias then use the aliasee for determining
7359 // thread-localness.
7360 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7361 GV = GA->resolveAliasedGlobal(false);
7363 TLSModel::Model model
7364 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7367 case TLSModel::GeneralDynamic:
7368 case TLSModel::LocalDynamic: // not implemented
7369 if (Subtarget->is64Bit())
7370 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7371 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7373 case TLSModel::InitialExec:
7374 case TLSModel::LocalExec:
7375 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7376 Subtarget->is64Bit());
7378 } else if (Subtarget->isTargetDarwin()) {
7379 // Darwin only has one model of TLS. Lower to that.
7380 unsigned char OpFlag = 0;
7381 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7382 X86ISD::WrapperRIP : X86ISD::Wrapper;
7384 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7386 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7387 !Subtarget->is64Bit();
7389 OpFlag = X86II::MO_TLVP_PIC_BASE;
7391 OpFlag = X86II::MO_TLVP;
7392 DebugLoc DL = Op.getDebugLoc();
7393 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7394 GA->getValueType(0),
7395 GA->getOffset(), OpFlag);
7396 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7398 // With PIC32, the address is actually $g + Offset.
7400 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7401 DAG.getNode(X86ISD::GlobalBaseReg,
7402 DebugLoc(), getPointerTy()),
7405 // Lowering the machine isd will make sure everything is in the right
7407 SDValue Chain = DAG.getEntryNode();
7408 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7409 SDValue Args[] = { Chain, Offset };
7410 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7412 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7413 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7414 MFI->setAdjustsStack(true);
7416 // And our return value (tls address) is in the standard call return value
7418 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7419 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7424 "TLS not implemented for this target.");
7426 llvm_unreachable("Unreachable");
7431 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7432 /// take a 2 x i32 value to shift plus a shift amount.
7433 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7434 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7435 EVT VT = Op.getValueType();
7436 unsigned VTBits = VT.getSizeInBits();
7437 DebugLoc dl = Op.getDebugLoc();
7438 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7439 SDValue ShOpLo = Op.getOperand(0);
7440 SDValue ShOpHi = Op.getOperand(1);
7441 SDValue ShAmt = Op.getOperand(2);
7442 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7443 DAG.getConstant(VTBits - 1, MVT::i8))
7444 : DAG.getConstant(0, VT);
7447 if (Op.getOpcode() == ISD::SHL_PARTS) {
7448 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7449 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7451 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7452 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7455 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7456 DAG.getConstant(VTBits, MVT::i8));
7457 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7458 AndNode, DAG.getConstant(0, MVT::i8));
7461 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7462 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7463 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7465 if (Op.getOpcode() == ISD::SHL_PARTS) {
7466 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7467 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7469 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7470 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7473 SDValue Ops[2] = { Lo, Hi };
7474 return DAG.getMergeValues(Ops, 2, dl);
7477 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7478 SelectionDAG &DAG) const {
7479 EVT SrcVT = Op.getOperand(0).getValueType();
7481 if (SrcVT.isVector())
7484 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7485 "Unknown SINT_TO_FP to lower!");
7487 // These are really Legal; return the operand so the caller accepts it as
7489 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7491 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7492 Subtarget->is64Bit()) {
7496 DebugLoc dl = Op.getDebugLoc();
7497 unsigned Size = SrcVT.getSizeInBits()/8;
7498 MachineFunction &MF = DAG.getMachineFunction();
7499 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7500 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7501 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7503 MachinePointerInfo::getFixedStack(SSFI),
7505 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7508 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7510 SelectionDAG &DAG) const {
7512 DebugLoc DL = Op.getDebugLoc();
7514 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7516 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7518 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7520 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7522 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7523 MachineMemOperand *MMO;
7525 int SSFI = FI->getIndex();
7527 DAG.getMachineFunction()
7528 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7529 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7531 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7532 StackSlot = StackSlot.getOperand(1);
7534 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7535 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7537 Tys, Ops, array_lengthof(Ops),
7541 Chain = Result.getValue(1);
7542 SDValue InFlag = Result.getValue(2);
7544 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7545 // shouldn't be necessary except that RFP cannot be live across
7546 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7547 MachineFunction &MF = DAG.getMachineFunction();
7548 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7549 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7550 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7551 Tys = DAG.getVTList(MVT::Other);
7553 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7555 MachineMemOperand *MMO =
7556 DAG.getMachineFunction()
7557 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7558 MachineMemOperand::MOStore, SSFISize, SSFISize);
7560 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7561 Ops, array_lengthof(Ops),
7562 Op.getValueType(), MMO);
7563 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7564 MachinePointerInfo::getFixedStack(SSFI),
7565 false, false, false, 0);
7571 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7572 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7573 SelectionDAG &DAG) const {
7574 // This algorithm is not obvious. Here it is in C code, more or less:
7576 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7577 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7578 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7580 // Copy ints to xmm registers.
7581 __m128i xh = _mm_cvtsi32_si128( hi );
7582 __m128i xl = _mm_cvtsi32_si128( lo );
7584 // Combine into low half of a single xmm register.
7585 __m128i x = _mm_unpacklo_epi32( xh, xl );
7589 // Merge in appropriate exponents to give the integer bits the right
7591 x = _mm_unpacklo_epi32( x, exp );
7593 // Subtract away the biases to deal with the IEEE-754 double precision
7595 d = _mm_sub_pd( (__m128d) x, bias );
7597 // All conversions up to here are exact. The correctly rounded result is
7598 // calculated using the current rounding mode using the following
7600 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7601 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7602 // store doesn't really need to be here (except
7603 // maybe to zero the other double)
7608 DebugLoc dl = Op.getDebugLoc();
7609 LLVMContext *Context = DAG.getContext();
7611 // Build some magic constants.
7612 SmallVector<Constant*,4> CV0;
7613 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7614 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7615 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7616 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7617 Constant *C0 = ConstantVector::get(CV0);
7618 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7620 SmallVector<Constant*,2> CV1;
7622 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7624 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7625 Constant *C1 = ConstantVector::get(CV1);
7626 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7628 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7629 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7631 DAG.getIntPtrConstant(1)));
7632 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7633 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7635 DAG.getIntPtrConstant(0)));
7636 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7637 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7638 MachinePointerInfo::getConstantPool(),
7639 false, false, false, 16);
7640 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7641 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7642 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7643 MachinePointerInfo::getConstantPool(),
7644 false, false, false, 16);
7645 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7647 // Add the halves; easiest way is to swap them into another reg first.
7648 int ShufMask[2] = { 1, -1 };
7649 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7650 DAG.getUNDEF(MVT::v2f64), ShufMask);
7651 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7652 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7653 DAG.getIntPtrConstant(0));
7656 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7657 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7658 SelectionDAG &DAG) const {
7659 DebugLoc dl = Op.getDebugLoc();
7660 // FP constant to bias correct the final result.
7661 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7664 // Load the 32-bit value into an XMM register.
7665 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7668 // Zero out the upper parts of the register.
7669 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasXMMInt(),
7672 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7673 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7674 DAG.getIntPtrConstant(0));
7676 // Or the load with the bias.
7677 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7678 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7679 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7681 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7682 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7683 MVT::v2f64, Bias)));
7684 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7685 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7686 DAG.getIntPtrConstant(0));
7688 // Subtract the bias.
7689 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7691 // Handle final rounding.
7692 EVT DestVT = Op.getValueType();
7694 if (DestVT.bitsLT(MVT::f64)) {
7695 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7696 DAG.getIntPtrConstant(0));
7697 } else if (DestVT.bitsGT(MVT::f64)) {
7698 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7701 // Handle final rounding.
7705 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7706 SelectionDAG &DAG) const {
7707 SDValue N0 = Op.getOperand(0);
7708 DebugLoc dl = Op.getDebugLoc();
7710 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7711 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7712 // the optimization here.
7713 if (DAG.SignBitIsZero(N0))
7714 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7716 EVT SrcVT = N0.getValueType();
7717 EVT DstVT = Op.getValueType();
7718 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7719 return LowerUINT_TO_FP_i64(Op, DAG);
7720 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7721 return LowerUINT_TO_FP_i32(Op, DAG);
7723 // Make a 64-bit buffer, and use it to build an FILD.
7724 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7725 if (SrcVT == MVT::i32) {
7726 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7727 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7728 getPointerTy(), StackSlot, WordOff);
7729 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7730 StackSlot, MachinePointerInfo(),
7732 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7733 OffsetSlot, MachinePointerInfo(),
7735 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7739 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7740 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7741 StackSlot, MachinePointerInfo(),
7743 // For i64 source, we need to add the appropriate power of 2 if the input
7744 // was negative. This is the same as the optimization in
7745 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7746 // we must be careful to do the computation in x87 extended precision, not
7747 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7748 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7749 MachineMemOperand *MMO =
7750 DAG.getMachineFunction()
7751 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7752 MachineMemOperand::MOLoad, 8, 8);
7754 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7755 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7756 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7759 APInt FF(32, 0x5F800000ULL);
7761 // Check whether the sign bit is set.
7762 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7763 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7766 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7767 SDValue FudgePtr = DAG.getConstantPool(
7768 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7771 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7772 SDValue Zero = DAG.getIntPtrConstant(0);
7773 SDValue Four = DAG.getIntPtrConstant(4);
7774 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7776 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7778 // Load the value out, extending it from f32 to f80.
7779 // FIXME: Avoid the extend by constructing the right constant pool?
7780 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7781 FudgePtr, MachinePointerInfo::getConstantPool(),
7782 MVT::f32, false, false, 4);
7783 // Extend everything to 80 bits to force it to be done on x87.
7784 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7785 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7788 std::pair<SDValue,SDValue> X86TargetLowering::
7789 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7790 DebugLoc DL = Op.getDebugLoc();
7792 EVT DstTy = Op.getValueType();
7795 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7799 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7800 DstTy.getSimpleVT() >= MVT::i16 &&
7801 "Unknown FP_TO_SINT to lower!");
7803 // These are really Legal.
7804 if (DstTy == MVT::i32 &&
7805 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7806 return std::make_pair(SDValue(), SDValue());
7807 if (Subtarget->is64Bit() &&
7808 DstTy == MVT::i64 &&
7809 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7810 return std::make_pair(SDValue(), SDValue());
7812 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7814 MachineFunction &MF = DAG.getMachineFunction();
7815 unsigned MemSize = DstTy.getSizeInBits()/8;
7816 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7817 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7822 switch (DstTy.getSimpleVT().SimpleTy) {
7823 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7824 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7825 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7826 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7829 SDValue Chain = DAG.getEntryNode();
7830 SDValue Value = Op.getOperand(0);
7831 EVT TheVT = Op.getOperand(0).getValueType();
7832 if (isScalarFPTypeInSSEReg(TheVT)) {
7833 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7834 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7835 MachinePointerInfo::getFixedStack(SSFI),
7837 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7839 Chain, StackSlot, DAG.getValueType(TheVT)
7842 MachineMemOperand *MMO =
7843 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7844 MachineMemOperand::MOLoad, MemSize, MemSize);
7845 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7847 Chain = Value.getValue(1);
7848 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7849 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7852 MachineMemOperand *MMO =
7853 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7854 MachineMemOperand::MOStore, MemSize, MemSize);
7856 // Build the FP_TO_INT*_IN_MEM
7857 SDValue Ops[] = { Chain, Value, StackSlot };
7858 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7859 Ops, 3, DstTy, MMO);
7861 return std::make_pair(FIST, StackSlot);
7864 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7865 SelectionDAG &DAG) const {
7866 if (Op.getValueType().isVector())
7869 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7870 SDValue FIST = Vals.first, StackSlot = Vals.second;
7871 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7872 if (FIST.getNode() == 0) return Op;
7875 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7876 FIST, StackSlot, MachinePointerInfo(),
7877 false, false, false, 0);
7880 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7881 SelectionDAG &DAG) const {
7882 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7883 SDValue FIST = Vals.first, StackSlot = Vals.second;
7884 assert(FIST.getNode() && "Unexpected failure");
7887 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7888 FIST, StackSlot, MachinePointerInfo(),
7889 false, false, false, 0);
7892 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7893 SelectionDAG &DAG) const {
7894 LLVMContext *Context = DAG.getContext();
7895 DebugLoc dl = Op.getDebugLoc();
7896 EVT VT = Op.getValueType();
7899 EltVT = VT.getVectorElementType();
7900 SmallVector<Constant*,4> CV;
7901 if (EltVT == MVT::f64) {
7902 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7905 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7908 Constant *C = ConstantVector::get(CV);
7909 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7910 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7911 MachinePointerInfo::getConstantPool(),
7912 false, false, false, 16);
7913 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7916 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7917 LLVMContext *Context = DAG.getContext();
7918 DebugLoc dl = Op.getDebugLoc();
7919 EVT VT = Op.getValueType();
7921 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7922 if (VT.isVector()) {
7923 EltVT = VT.getVectorElementType();
7924 NumElts = VT.getVectorNumElements();
7926 SmallVector<Constant*,8> CV;
7927 if (EltVT == MVT::f64) {
7928 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7929 CV.assign(NumElts, C);
7931 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7932 CV.assign(NumElts, C);
7934 Constant *C = ConstantVector::get(CV);
7935 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7936 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7937 MachinePointerInfo::getConstantPool(),
7938 false, false, false, 16);
7939 if (VT.isVector()) {
7940 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7941 return DAG.getNode(ISD::BITCAST, dl, VT,
7942 DAG.getNode(ISD::XOR, dl, XORVT,
7943 DAG.getNode(ISD::BITCAST, dl, XORVT,
7945 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7947 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7951 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7952 LLVMContext *Context = DAG.getContext();
7953 SDValue Op0 = Op.getOperand(0);
7954 SDValue Op1 = Op.getOperand(1);
7955 DebugLoc dl = Op.getDebugLoc();
7956 EVT VT = Op.getValueType();
7957 EVT SrcVT = Op1.getValueType();
7959 // If second operand is smaller, extend it first.
7960 if (SrcVT.bitsLT(VT)) {
7961 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7964 // And if it is bigger, shrink it first.
7965 if (SrcVT.bitsGT(VT)) {
7966 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7970 // At this point the operands and the result should have the same
7971 // type, and that won't be f80 since that is not custom lowered.
7973 // First get the sign bit of second operand.
7974 SmallVector<Constant*,4> CV;
7975 if (SrcVT == MVT::f64) {
7976 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7977 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7979 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7980 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7981 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7982 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7984 Constant *C = ConstantVector::get(CV);
7985 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7986 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7987 MachinePointerInfo::getConstantPool(),
7988 false, false, false, 16);
7989 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7991 // Shift sign bit right or left if the two operands have different types.
7992 if (SrcVT.bitsGT(VT)) {
7993 // Op0 is MVT::f32, Op1 is MVT::f64.
7994 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7995 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7996 DAG.getConstant(32, MVT::i32));
7997 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7998 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7999 DAG.getIntPtrConstant(0));
8002 // Clear first operand sign bit.
8004 if (VT == MVT::f64) {
8005 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8006 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8008 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8009 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8010 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8011 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8013 C = ConstantVector::get(CV);
8014 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8015 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8016 MachinePointerInfo::getConstantPool(),
8017 false, false, false, 16);
8018 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8020 // Or the value with the sign bit.
8021 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8024 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8025 SDValue N0 = Op.getOperand(0);
8026 DebugLoc dl = Op.getDebugLoc();
8027 EVT VT = Op.getValueType();
8029 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8030 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8031 DAG.getConstant(1, VT));
8032 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8035 /// Emit nodes that will be selected as "test Op0,Op0", or something
8037 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8038 SelectionDAG &DAG) const {
8039 DebugLoc dl = Op.getDebugLoc();
8041 // CF and OF aren't always set the way we want. Determine which
8042 // of these we need.
8043 bool NeedCF = false;
8044 bool NeedOF = false;
8047 case X86::COND_A: case X86::COND_AE:
8048 case X86::COND_B: case X86::COND_BE:
8051 case X86::COND_G: case X86::COND_GE:
8052 case X86::COND_L: case X86::COND_LE:
8053 case X86::COND_O: case X86::COND_NO:
8058 // See if we can use the EFLAGS value from the operand instead of
8059 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8060 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8061 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8062 // Emit a CMP with 0, which is the TEST pattern.
8063 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8064 DAG.getConstant(0, Op.getValueType()));
8066 unsigned Opcode = 0;
8067 unsigned NumOperands = 0;
8068 switch (Op.getNode()->getOpcode()) {
8070 // Due to an isel shortcoming, be conservative if this add is likely to be
8071 // selected as part of a load-modify-store instruction. When the root node
8072 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8073 // uses of other nodes in the match, such as the ADD in this case. This
8074 // leads to the ADD being left around and reselected, with the result being
8075 // two adds in the output. Alas, even if none our users are stores, that
8076 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8077 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8078 // climbing the DAG back to the root, and it doesn't seem to be worth the
8080 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8081 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8082 if (UI->getOpcode() != ISD::CopyToReg &&
8083 UI->getOpcode() != ISD::SETCC &&
8084 UI->getOpcode() != ISD::STORE)
8087 if (ConstantSDNode *C =
8088 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8089 // An add of one will be selected as an INC.
8090 if (C->getAPIntValue() == 1) {
8091 Opcode = X86ISD::INC;
8096 // An add of negative one (subtract of one) will be selected as a DEC.
8097 if (C->getAPIntValue().isAllOnesValue()) {
8098 Opcode = X86ISD::DEC;
8104 // Otherwise use a regular EFLAGS-setting add.
8105 Opcode = X86ISD::ADD;
8109 // If the primary and result isn't used, don't bother using X86ISD::AND,
8110 // because a TEST instruction will be better.
8111 bool NonFlagUse = false;
8112 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8113 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8115 unsigned UOpNo = UI.getOperandNo();
8116 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8117 // Look pass truncate.
8118 UOpNo = User->use_begin().getOperandNo();
8119 User = *User->use_begin();
8122 if (User->getOpcode() != ISD::BRCOND &&
8123 User->getOpcode() != ISD::SETCC &&
8124 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8137 // Due to the ISEL shortcoming noted above, be conservative if this op is
8138 // likely to be selected as part of a load-modify-store instruction.
8139 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8140 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8141 if (UI->getOpcode() == ISD::STORE)
8144 // Otherwise use a regular EFLAGS-setting instruction.
8145 switch (Op.getNode()->getOpcode()) {
8146 default: llvm_unreachable("unexpected operator!");
8147 case ISD::SUB: Opcode = X86ISD::SUB; break;
8148 case ISD::OR: Opcode = X86ISD::OR; break;
8149 case ISD::XOR: Opcode = X86ISD::XOR; break;
8150 case ISD::AND: Opcode = X86ISD::AND; break;
8162 return SDValue(Op.getNode(), 1);
8169 // Emit a CMP with 0, which is the TEST pattern.
8170 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8171 DAG.getConstant(0, Op.getValueType()));
8173 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8174 SmallVector<SDValue, 4> Ops;
8175 for (unsigned i = 0; i != NumOperands; ++i)
8176 Ops.push_back(Op.getOperand(i));
8178 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8179 DAG.ReplaceAllUsesWith(Op, New);
8180 return SDValue(New.getNode(), 1);
8183 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8185 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8186 SelectionDAG &DAG) const {
8187 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8188 if (C->getAPIntValue() == 0)
8189 return EmitTest(Op0, X86CC, DAG);
8191 DebugLoc dl = Op0.getDebugLoc();
8192 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8195 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8196 /// if it's possible.
8197 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8198 DebugLoc dl, SelectionDAG &DAG) const {
8199 SDValue Op0 = And.getOperand(0);
8200 SDValue Op1 = And.getOperand(1);
8201 if (Op0.getOpcode() == ISD::TRUNCATE)
8202 Op0 = Op0.getOperand(0);
8203 if (Op1.getOpcode() == ISD::TRUNCATE)
8204 Op1 = Op1.getOperand(0);
8207 if (Op1.getOpcode() == ISD::SHL)
8208 std::swap(Op0, Op1);
8209 if (Op0.getOpcode() == ISD::SHL) {
8210 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8211 if (And00C->getZExtValue() == 1) {
8212 // If we looked past a truncate, check that it's only truncating away
8214 unsigned BitWidth = Op0.getValueSizeInBits();
8215 unsigned AndBitWidth = And.getValueSizeInBits();
8216 if (BitWidth > AndBitWidth) {
8217 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8218 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8219 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8223 RHS = Op0.getOperand(1);
8225 } else if (Op1.getOpcode() == ISD::Constant) {
8226 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8227 uint64_t AndRHSVal = AndRHS->getZExtValue();
8228 SDValue AndLHS = Op0;
8230 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8231 LHS = AndLHS.getOperand(0);
8232 RHS = AndLHS.getOperand(1);
8235 // Use BT if the immediate can't be encoded in a TEST instruction.
8236 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8238 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8242 if (LHS.getNode()) {
8243 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8244 // instruction. Since the shift amount is in-range-or-undefined, we know
8245 // that doing a bittest on the i32 value is ok. We extend to i32 because
8246 // the encoding for the i16 version is larger than the i32 version.
8247 // Also promote i16 to i32 for performance / code size reason.
8248 if (LHS.getValueType() == MVT::i8 ||
8249 LHS.getValueType() == MVT::i16)
8250 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8252 // If the operand types disagree, extend the shift amount to match. Since
8253 // BT ignores high bits (like shifts) we can use anyextend.
8254 if (LHS.getValueType() != RHS.getValueType())
8255 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8257 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8258 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8259 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8260 DAG.getConstant(Cond, MVT::i8), BT);
8266 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8268 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8270 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8271 SDValue Op0 = Op.getOperand(0);
8272 SDValue Op1 = Op.getOperand(1);
8273 DebugLoc dl = Op.getDebugLoc();
8274 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8276 // Optimize to BT if possible.
8277 // Lower (X & (1 << N)) == 0 to BT(X, N).
8278 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8279 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8280 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8281 Op1.getOpcode() == ISD::Constant &&
8282 cast<ConstantSDNode>(Op1)->isNullValue() &&
8283 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8284 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8285 if (NewSetCC.getNode())
8289 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8291 if (Op1.getOpcode() == ISD::Constant &&
8292 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8293 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8294 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8296 // If the input is a setcc, then reuse the input setcc or use a new one with
8297 // the inverted condition.
8298 if (Op0.getOpcode() == X86ISD::SETCC) {
8299 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8300 bool Invert = (CC == ISD::SETNE) ^
8301 cast<ConstantSDNode>(Op1)->isNullValue();
8302 if (!Invert) return Op0;
8304 CCode = X86::GetOppositeBranchCondition(CCode);
8305 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8306 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8310 bool isFP = Op1.getValueType().isFloatingPoint();
8311 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8312 if (X86CC == X86::COND_INVALID)
8315 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8316 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8317 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8320 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8321 // ones, and then concatenate the result back.
8322 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8323 EVT VT = Op.getValueType();
8325 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8326 "Unsupported value type for operation");
8328 int NumElems = VT.getVectorNumElements();
8329 DebugLoc dl = Op.getDebugLoc();
8330 SDValue CC = Op.getOperand(2);
8331 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8332 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8334 // Extract the LHS vectors
8335 SDValue LHS = Op.getOperand(0);
8336 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8337 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8339 // Extract the RHS vectors
8340 SDValue RHS = Op.getOperand(1);
8341 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8342 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8344 // Issue the operation on the smaller types and concatenate the result back
8345 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8346 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8347 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8348 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8349 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8353 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8355 SDValue Op0 = Op.getOperand(0);
8356 SDValue Op1 = Op.getOperand(1);
8357 SDValue CC = Op.getOperand(2);
8358 EVT VT = Op.getValueType();
8359 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8360 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8361 DebugLoc dl = Op.getDebugLoc();
8365 EVT EltVT = Op0.getValueType().getVectorElementType();
8366 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8368 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8371 // SSE Condition code mapping:
8380 switch (SetCCOpcode) {
8383 case ISD::SETEQ: SSECC = 0; break;
8385 case ISD::SETGT: Swap = true; // Fallthrough
8387 case ISD::SETOLT: SSECC = 1; break;
8389 case ISD::SETGE: Swap = true; // Fallthrough
8391 case ISD::SETOLE: SSECC = 2; break;
8392 case ISD::SETUO: SSECC = 3; break;
8394 case ISD::SETNE: SSECC = 4; break;
8395 case ISD::SETULE: Swap = true;
8396 case ISD::SETUGE: SSECC = 5; break;
8397 case ISD::SETULT: Swap = true;
8398 case ISD::SETUGT: SSECC = 6; break;
8399 case ISD::SETO: SSECC = 7; break;
8402 std::swap(Op0, Op1);
8404 // In the two special cases we can't handle, emit two comparisons.
8406 if (SetCCOpcode == ISD::SETUEQ) {
8408 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8409 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8410 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8411 } else if (SetCCOpcode == ISD::SETONE) {
8413 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8414 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8415 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8417 llvm_unreachable("Illegal FP comparison");
8419 // Handle all other FP comparisons here.
8420 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8423 // Break 256-bit integer vector compare into smaller ones.
8424 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8425 return Lower256IntVSETCC(Op, DAG);
8427 // We are handling one of the integer comparisons here. Since SSE only has
8428 // GT and EQ comparisons for integer, swapping operands and multiple
8429 // operations may be required for some comparisons.
8430 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8431 bool Swap = false, Invert = false, FlipSigns = false;
8433 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
8435 case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8436 case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8437 case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8438 case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8441 switch (SetCCOpcode) {
8443 case ISD::SETNE: Invert = true;
8444 case ISD::SETEQ: Opc = EQOpc; break;
8445 case ISD::SETLT: Swap = true;
8446 case ISD::SETGT: Opc = GTOpc; break;
8447 case ISD::SETGE: Swap = true;
8448 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8449 case ISD::SETULT: Swap = true;
8450 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8451 case ISD::SETUGE: Swap = true;
8452 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8455 std::swap(Op0, Op1);
8457 // Check that the operation in question is available (most are plain SSE2,
8458 // but PCMPGTQ and PCMPEQQ have different requirements).
8459 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42orAVX())
8461 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41orAVX())
8464 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8465 // bits of the inputs before performing those operations.
8467 EVT EltVT = VT.getVectorElementType();
8468 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8470 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8471 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8473 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8474 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8477 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8479 // If the logical-not of the result is required, perform that now.
8481 Result = DAG.getNOT(dl, Result, VT);
8486 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8487 static bool isX86LogicalCmp(SDValue Op) {
8488 unsigned Opc = Op.getNode()->getOpcode();
8489 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8491 if (Op.getResNo() == 1 &&
8492 (Opc == X86ISD::ADD ||
8493 Opc == X86ISD::SUB ||
8494 Opc == X86ISD::ADC ||
8495 Opc == X86ISD::SBB ||
8496 Opc == X86ISD::SMUL ||
8497 Opc == X86ISD::UMUL ||
8498 Opc == X86ISD::INC ||
8499 Opc == X86ISD::DEC ||
8500 Opc == X86ISD::OR ||
8501 Opc == X86ISD::XOR ||
8502 Opc == X86ISD::AND))
8505 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8511 static bool isZero(SDValue V) {
8512 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8513 return C && C->isNullValue();
8516 static bool isAllOnes(SDValue V) {
8517 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8518 return C && C->isAllOnesValue();
8521 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8522 bool addTest = true;
8523 SDValue Cond = Op.getOperand(0);
8524 SDValue Op1 = Op.getOperand(1);
8525 SDValue Op2 = Op.getOperand(2);
8526 DebugLoc DL = Op.getDebugLoc();
8529 if (Cond.getOpcode() == ISD::SETCC) {
8530 SDValue NewCond = LowerSETCC(Cond, DAG);
8531 if (NewCond.getNode())
8535 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8536 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8537 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8538 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8539 if (Cond.getOpcode() == X86ISD::SETCC &&
8540 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8541 isZero(Cond.getOperand(1).getOperand(1))) {
8542 SDValue Cmp = Cond.getOperand(1);
8544 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8546 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8547 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8548 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8550 SDValue CmpOp0 = Cmp.getOperand(0);
8551 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8552 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8554 SDValue Res = // Res = 0 or -1.
8555 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8556 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8558 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8559 Res = DAG.getNOT(DL, Res, Res.getValueType());
8561 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8562 if (N2C == 0 || !N2C->isNullValue())
8563 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8568 // Look past (and (setcc_carry (cmp ...)), 1).
8569 if (Cond.getOpcode() == ISD::AND &&
8570 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8571 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8572 if (C && C->getAPIntValue() == 1)
8573 Cond = Cond.getOperand(0);
8576 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8577 // setting operand in place of the X86ISD::SETCC.
8578 unsigned CondOpcode = Cond.getOpcode();
8579 if (CondOpcode == X86ISD::SETCC ||
8580 CondOpcode == X86ISD::SETCC_CARRY) {
8581 CC = Cond.getOperand(0);
8583 SDValue Cmp = Cond.getOperand(1);
8584 unsigned Opc = Cmp.getOpcode();
8585 EVT VT = Op.getValueType();
8587 bool IllegalFPCMov = false;
8588 if (VT.isFloatingPoint() && !VT.isVector() &&
8589 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8590 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8592 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8593 Opc == X86ISD::BT) { // FIXME
8597 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8598 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8599 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8600 Cond.getOperand(0).getValueType() != MVT::i8)) {
8601 SDValue LHS = Cond.getOperand(0);
8602 SDValue RHS = Cond.getOperand(1);
8606 switch (CondOpcode) {
8607 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8608 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8609 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8610 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8611 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8612 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8613 default: llvm_unreachable("unexpected overflowing operator");
8615 if (CondOpcode == ISD::UMULO)
8616 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8619 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8621 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8623 if (CondOpcode == ISD::UMULO)
8624 Cond = X86Op.getValue(2);
8626 Cond = X86Op.getValue(1);
8628 CC = DAG.getConstant(X86Cond, MVT::i8);
8633 // Look pass the truncate.
8634 if (Cond.getOpcode() == ISD::TRUNCATE)
8635 Cond = Cond.getOperand(0);
8637 // We know the result of AND is compared against zero. Try to match
8639 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8640 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8641 if (NewSetCC.getNode()) {
8642 CC = NewSetCC.getOperand(0);
8643 Cond = NewSetCC.getOperand(1);
8650 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8651 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8654 // a < b ? -1 : 0 -> RES = ~setcc_carry
8655 // a < b ? 0 : -1 -> RES = setcc_carry
8656 // a >= b ? -1 : 0 -> RES = setcc_carry
8657 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8658 if (Cond.getOpcode() == X86ISD::CMP) {
8659 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8661 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8662 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8663 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8664 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8665 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8666 return DAG.getNOT(DL, Res, Res.getValueType());
8671 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8672 // condition is true.
8673 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8674 SDValue Ops[] = { Op2, Op1, CC, Cond };
8675 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8678 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8679 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8680 // from the AND / OR.
8681 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8682 Opc = Op.getOpcode();
8683 if (Opc != ISD::OR && Opc != ISD::AND)
8685 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8686 Op.getOperand(0).hasOneUse() &&
8687 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8688 Op.getOperand(1).hasOneUse());
8691 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8692 // 1 and that the SETCC node has a single use.
8693 static bool isXor1OfSetCC(SDValue Op) {
8694 if (Op.getOpcode() != ISD::XOR)
8696 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8697 if (N1C && N1C->getAPIntValue() == 1) {
8698 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8699 Op.getOperand(0).hasOneUse();
8704 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8705 bool addTest = true;
8706 SDValue Chain = Op.getOperand(0);
8707 SDValue Cond = Op.getOperand(1);
8708 SDValue Dest = Op.getOperand(2);
8709 DebugLoc dl = Op.getDebugLoc();
8711 bool Inverted = false;
8713 if (Cond.getOpcode() == ISD::SETCC) {
8714 // Check for setcc([su]{add,sub,mul}o == 0).
8715 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8716 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8717 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8718 Cond.getOperand(0).getResNo() == 1 &&
8719 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8720 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8721 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8722 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8723 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8724 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8726 Cond = Cond.getOperand(0);
8728 SDValue NewCond = LowerSETCC(Cond, DAG);
8729 if (NewCond.getNode())
8734 // FIXME: LowerXALUO doesn't handle these!!
8735 else if (Cond.getOpcode() == X86ISD::ADD ||
8736 Cond.getOpcode() == X86ISD::SUB ||
8737 Cond.getOpcode() == X86ISD::SMUL ||
8738 Cond.getOpcode() == X86ISD::UMUL)
8739 Cond = LowerXALUO(Cond, DAG);
8742 // Look pass (and (setcc_carry (cmp ...)), 1).
8743 if (Cond.getOpcode() == ISD::AND &&
8744 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8745 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8746 if (C && C->getAPIntValue() == 1)
8747 Cond = Cond.getOperand(0);
8750 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8751 // setting operand in place of the X86ISD::SETCC.
8752 unsigned CondOpcode = Cond.getOpcode();
8753 if (CondOpcode == X86ISD::SETCC ||
8754 CondOpcode == X86ISD::SETCC_CARRY) {
8755 CC = Cond.getOperand(0);
8757 SDValue Cmp = Cond.getOperand(1);
8758 unsigned Opc = Cmp.getOpcode();
8759 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8760 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8764 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8768 // These can only come from an arithmetic instruction with overflow,
8769 // e.g. SADDO, UADDO.
8770 Cond = Cond.getNode()->getOperand(1);
8776 CondOpcode = Cond.getOpcode();
8777 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8778 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8779 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8780 Cond.getOperand(0).getValueType() != MVT::i8)) {
8781 SDValue LHS = Cond.getOperand(0);
8782 SDValue RHS = Cond.getOperand(1);
8786 switch (CondOpcode) {
8787 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8788 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8789 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8790 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8791 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8792 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8793 default: llvm_unreachable("unexpected overflowing operator");
8796 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8797 if (CondOpcode == ISD::UMULO)
8798 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8801 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8803 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8805 if (CondOpcode == ISD::UMULO)
8806 Cond = X86Op.getValue(2);
8808 Cond = X86Op.getValue(1);
8810 CC = DAG.getConstant(X86Cond, MVT::i8);
8814 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8815 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8816 if (CondOpc == ISD::OR) {
8817 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8818 // two branches instead of an explicit OR instruction with a
8820 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8821 isX86LogicalCmp(Cmp)) {
8822 CC = Cond.getOperand(0).getOperand(0);
8823 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8824 Chain, Dest, CC, Cmp);
8825 CC = Cond.getOperand(1).getOperand(0);
8829 } else { // ISD::AND
8830 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8831 // two branches instead of an explicit AND instruction with a
8832 // separate test. However, we only do this if this block doesn't
8833 // have a fall-through edge, because this requires an explicit
8834 // jmp when the condition is false.
8835 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8836 isX86LogicalCmp(Cmp) &&
8837 Op.getNode()->hasOneUse()) {
8838 X86::CondCode CCode =
8839 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8840 CCode = X86::GetOppositeBranchCondition(CCode);
8841 CC = DAG.getConstant(CCode, MVT::i8);
8842 SDNode *User = *Op.getNode()->use_begin();
8843 // Look for an unconditional branch following this conditional branch.
8844 // We need this because we need to reverse the successors in order
8845 // to implement FCMP_OEQ.
8846 if (User->getOpcode() == ISD::BR) {
8847 SDValue FalseBB = User->getOperand(1);
8849 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8850 assert(NewBR == User);
8854 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8855 Chain, Dest, CC, Cmp);
8856 X86::CondCode CCode =
8857 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8858 CCode = X86::GetOppositeBranchCondition(CCode);
8859 CC = DAG.getConstant(CCode, MVT::i8);
8865 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8866 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8867 // It should be transformed during dag combiner except when the condition
8868 // is set by a arithmetics with overflow node.
8869 X86::CondCode CCode =
8870 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8871 CCode = X86::GetOppositeBranchCondition(CCode);
8872 CC = DAG.getConstant(CCode, MVT::i8);
8873 Cond = Cond.getOperand(0).getOperand(1);
8875 } else if (Cond.getOpcode() == ISD::SETCC &&
8876 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8877 // For FCMP_OEQ, we can emit
8878 // two branches instead of an explicit AND instruction with a
8879 // separate test. However, we only do this if this block doesn't
8880 // have a fall-through edge, because this requires an explicit
8881 // jmp when the condition is false.
8882 if (Op.getNode()->hasOneUse()) {
8883 SDNode *User = *Op.getNode()->use_begin();
8884 // Look for an unconditional branch following this conditional branch.
8885 // We need this because we need to reverse the successors in order
8886 // to implement FCMP_OEQ.
8887 if (User->getOpcode() == ISD::BR) {
8888 SDValue FalseBB = User->getOperand(1);
8890 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8891 assert(NewBR == User);
8895 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8896 Cond.getOperand(0), Cond.getOperand(1));
8897 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8898 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8899 Chain, Dest, CC, Cmp);
8900 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8905 } else if (Cond.getOpcode() == ISD::SETCC &&
8906 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8907 // For FCMP_UNE, we can emit
8908 // two branches instead of an explicit AND instruction with a
8909 // separate test. However, we only do this if this block doesn't
8910 // have a fall-through edge, because this requires an explicit
8911 // jmp when the condition is false.
8912 if (Op.getNode()->hasOneUse()) {
8913 SDNode *User = *Op.getNode()->use_begin();
8914 // Look for an unconditional branch following this conditional branch.
8915 // We need this because we need to reverse the successors in order
8916 // to implement FCMP_UNE.
8917 if (User->getOpcode() == ISD::BR) {
8918 SDValue FalseBB = User->getOperand(1);
8920 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8921 assert(NewBR == User);
8924 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8925 Cond.getOperand(0), Cond.getOperand(1));
8926 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8927 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8928 Chain, Dest, CC, Cmp);
8929 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8939 // Look pass the truncate.
8940 if (Cond.getOpcode() == ISD::TRUNCATE)
8941 Cond = Cond.getOperand(0);
8943 // We know the result of AND is compared against zero. Try to match
8945 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8946 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8947 if (NewSetCC.getNode()) {
8948 CC = NewSetCC.getOperand(0);
8949 Cond = NewSetCC.getOperand(1);
8956 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8957 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8959 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8960 Chain, Dest, CC, Cond);
8964 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8965 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8966 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8967 // that the guard pages used by the OS virtual memory manager are allocated in
8968 // correct sequence.
8970 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8971 SelectionDAG &DAG) const {
8972 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8973 getTargetMachine().Options.EnableSegmentedStacks) &&
8974 "This should be used only on Windows targets or when segmented stacks "
8976 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8977 DebugLoc dl = Op.getDebugLoc();
8980 SDValue Chain = Op.getOperand(0);
8981 SDValue Size = Op.getOperand(1);
8982 // FIXME: Ensure alignment here
8984 bool Is64Bit = Subtarget->is64Bit();
8985 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8987 if (getTargetMachine().Options.EnableSegmentedStacks) {
8988 MachineFunction &MF = DAG.getMachineFunction();
8989 MachineRegisterInfo &MRI = MF.getRegInfo();
8992 // The 64 bit implementation of segmented stacks needs to clobber both r10
8993 // r11. This makes it impossible to use it along with nested parameters.
8994 const Function *F = MF.getFunction();
8996 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8998 if (I->hasNestAttr())
8999 report_fatal_error("Cannot use segmented stacks with functions that "
9000 "have nested arguments.");
9003 const TargetRegisterClass *AddrRegClass =
9004 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9005 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9006 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9007 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9008 DAG.getRegister(Vreg, SPTy));
9009 SDValue Ops1[2] = { Value, Chain };
9010 return DAG.getMergeValues(Ops1, 2, dl);
9013 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9015 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9016 Flag = Chain.getValue(1);
9017 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9019 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9020 Flag = Chain.getValue(1);
9022 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9024 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9025 return DAG.getMergeValues(Ops1, 2, dl);
9029 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9030 MachineFunction &MF = DAG.getMachineFunction();
9031 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9033 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9034 DebugLoc DL = Op.getDebugLoc();
9036 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9037 // vastart just stores the address of the VarArgsFrameIndex slot into the
9038 // memory location argument.
9039 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9041 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9042 MachinePointerInfo(SV), false, false, 0);
9046 // gp_offset (0 - 6 * 8)
9047 // fp_offset (48 - 48 + 8 * 16)
9048 // overflow_arg_area (point to parameters coming in memory).
9050 SmallVector<SDValue, 8> MemOps;
9051 SDValue FIN = Op.getOperand(1);
9053 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9054 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9056 FIN, MachinePointerInfo(SV), false, false, 0);
9057 MemOps.push_back(Store);
9060 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9061 FIN, DAG.getIntPtrConstant(4));
9062 Store = DAG.getStore(Op.getOperand(0), DL,
9063 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9065 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9066 MemOps.push_back(Store);
9068 // Store ptr to overflow_arg_area
9069 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9070 FIN, DAG.getIntPtrConstant(4));
9071 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9073 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9074 MachinePointerInfo(SV, 8),
9076 MemOps.push_back(Store);
9078 // Store ptr to reg_save_area.
9079 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9080 FIN, DAG.getIntPtrConstant(8));
9081 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9083 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9084 MachinePointerInfo(SV, 16), false, false, 0);
9085 MemOps.push_back(Store);
9086 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9087 &MemOps[0], MemOps.size());
9090 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9091 assert(Subtarget->is64Bit() &&
9092 "LowerVAARG only handles 64-bit va_arg!");
9093 assert((Subtarget->isTargetLinux() ||
9094 Subtarget->isTargetDarwin()) &&
9095 "Unhandled target in LowerVAARG");
9096 assert(Op.getNode()->getNumOperands() == 4);
9097 SDValue Chain = Op.getOperand(0);
9098 SDValue SrcPtr = Op.getOperand(1);
9099 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9100 unsigned Align = Op.getConstantOperandVal(3);
9101 DebugLoc dl = Op.getDebugLoc();
9103 EVT ArgVT = Op.getNode()->getValueType(0);
9104 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9105 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9108 // Decide which area this value should be read from.
9109 // TODO: Implement the AMD64 ABI in its entirety. This simple
9110 // selection mechanism works only for the basic types.
9111 if (ArgVT == MVT::f80) {
9112 llvm_unreachable("va_arg for f80 not yet implemented");
9113 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9114 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9115 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9116 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9118 llvm_unreachable("Unhandled argument type in LowerVAARG");
9122 // Sanity Check: Make sure using fp_offset makes sense.
9123 assert(!getTargetMachine().Options.UseSoftFloat &&
9124 !(DAG.getMachineFunction()
9125 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9126 Subtarget->hasXMM());
9129 // Insert VAARG_64 node into the DAG
9130 // VAARG_64 returns two values: Variable Argument Address, Chain
9131 SmallVector<SDValue, 11> InstOps;
9132 InstOps.push_back(Chain);
9133 InstOps.push_back(SrcPtr);
9134 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9135 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9136 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9137 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9138 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9139 VTs, &InstOps[0], InstOps.size(),
9141 MachinePointerInfo(SV),
9146 Chain = VAARG.getValue(1);
9148 // Load the next argument and return it
9149 return DAG.getLoad(ArgVT, dl,
9152 MachinePointerInfo(),
9153 false, false, false, 0);
9156 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9157 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9158 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9159 SDValue Chain = Op.getOperand(0);
9160 SDValue DstPtr = Op.getOperand(1);
9161 SDValue SrcPtr = Op.getOperand(2);
9162 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9163 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9164 DebugLoc DL = Op.getDebugLoc();
9166 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9167 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9169 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9173 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9174 DebugLoc dl = Op.getDebugLoc();
9175 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9177 default: return SDValue(); // Don't custom lower most intrinsics.
9178 // Comparison intrinsics.
9179 case Intrinsic::x86_sse_comieq_ss:
9180 case Intrinsic::x86_sse_comilt_ss:
9181 case Intrinsic::x86_sse_comile_ss:
9182 case Intrinsic::x86_sse_comigt_ss:
9183 case Intrinsic::x86_sse_comige_ss:
9184 case Intrinsic::x86_sse_comineq_ss:
9185 case Intrinsic::x86_sse_ucomieq_ss:
9186 case Intrinsic::x86_sse_ucomilt_ss:
9187 case Intrinsic::x86_sse_ucomile_ss:
9188 case Intrinsic::x86_sse_ucomigt_ss:
9189 case Intrinsic::x86_sse_ucomige_ss:
9190 case Intrinsic::x86_sse_ucomineq_ss:
9191 case Intrinsic::x86_sse2_comieq_sd:
9192 case Intrinsic::x86_sse2_comilt_sd:
9193 case Intrinsic::x86_sse2_comile_sd:
9194 case Intrinsic::x86_sse2_comigt_sd:
9195 case Intrinsic::x86_sse2_comige_sd:
9196 case Intrinsic::x86_sse2_comineq_sd:
9197 case Intrinsic::x86_sse2_ucomieq_sd:
9198 case Intrinsic::x86_sse2_ucomilt_sd:
9199 case Intrinsic::x86_sse2_ucomile_sd:
9200 case Intrinsic::x86_sse2_ucomigt_sd:
9201 case Intrinsic::x86_sse2_ucomige_sd:
9202 case Intrinsic::x86_sse2_ucomineq_sd: {
9204 ISD::CondCode CC = ISD::SETCC_INVALID;
9207 case Intrinsic::x86_sse_comieq_ss:
9208 case Intrinsic::x86_sse2_comieq_sd:
9212 case Intrinsic::x86_sse_comilt_ss:
9213 case Intrinsic::x86_sse2_comilt_sd:
9217 case Intrinsic::x86_sse_comile_ss:
9218 case Intrinsic::x86_sse2_comile_sd:
9222 case Intrinsic::x86_sse_comigt_ss:
9223 case Intrinsic::x86_sse2_comigt_sd:
9227 case Intrinsic::x86_sse_comige_ss:
9228 case Intrinsic::x86_sse2_comige_sd:
9232 case Intrinsic::x86_sse_comineq_ss:
9233 case Intrinsic::x86_sse2_comineq_sd:
9237 case Intrinsic::x86_sse_ucomieq_ss:
9238 case Intrinsic::x86_sse2_ucomieq_sd:
9239 Opc = X86ISD::UCOMI;
9242 case Intrinsic::x86_sse_ucomilt_ss:
9243 case Intrinsic::x86_sse2_ucomilt_sd:
9244 Opc = X86ISD::UCOMI;
9247 case Intrinsic::x86_sse_ucomile_ss:
9248 case Intrinsic::x86_sse2_ucomile_sd:
9249 Opc = X86ISD::UCOMI;
9252 case Intrinsic::x86_sse_ucomigt_ss:
9253 case Intrinsic::x86_sse2_ucomigt_sd:
9254 Opc = X86ISD::UCOMI;
9257 case Intrinsic::x86_sse_ucomige_ss:
9258 case Intrinsic::x86_sse2_ucomige_sd:
9259 Opc = X86ISD::UCOMI;
9262 case Intrinsic::x86_sse_ucomineq_ss:
9263 case Intrinsic::x86_sse2_ucomineq_sd:
9264 Opc = X86ISD::UCOMI;
9269 SDValue LHS = Op.getOperand(1);
9270 SDValue RHS = Op.getOperand(2);
9271 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9272 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9273 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9274 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9275 DAG.getConstant(X86CC, MVT::i8), Cond);
9276 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9278 // Arithmetic intrinsics.
9279 case Intrinsic::x86_sse3_hadd_ps:
9280 case Intrinsic::x86_sse3_hadd_pd:
9281 case Intrinsic::x86_avx_hadd_ps_256:
9282 case Intrinsic::x86_avx_hadd_pd_256:
9283 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9284 Op.getOperand(1), Op.getOperand(2));
9285 case Intrinsic::x86_sse3_hsub_ps:
9286 case Intrinsic::x86_sse3_hsub_pd:
9287 case Intrinsic::x86_avx_hsub_ps_256:
9288 case Intrinsic::x86_avx_hsub_pd_256:
9289 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9290 Op.getOperand(1), Op.getOperand(2));
9291 case Intrinsic::x86_avx2_psllv_d:
9292 case Intrinsic::x86_avx2_psllv_q:
9293 case Intrinsic::x86_avx2_psllv_d_256:
9294 case Intrinsic::x86_avx2_psllv_q_256:
9295 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9296 Op.getOperand(1), Op.getOperand(2));
9297 case Intrinsic::x86_avx2_psrlv_d:
9298 case Intrinsic::x86_avx2_psrlv_q:
9299 case Intrinsic::x86_avx2_psrlv_d_256:
9300 case Intrinsic::x86_avx2_psrlv_q_256:
9301 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9302 Op.getOperand(1), Op.getOperand(2));
9303 case Intrinsic::x86_avx2_psrav_d:
9304 case Intrinsic::x86_avx2_psrav_d_256:
9305 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9306 Op.getOperand(1), Op.getOperand(2));
9308 // ptest and testp intrinsics. The intrinsic these come from are designed to
9309 // return an integer value, not just an instruction so lower it to the ptest
9310 // or testp pattern and a setcc for the result.
9311 case Intrinsic::x86_sse41_ptestz:
9312 case Intrinsic::x86_sse41_ptestc:
9313 case Intrinsic::x86_sse41_ptestnzc:
9314 case Intrinsic::x86_avx_ptestz_256:
9315 case Intrinsic::x86_avx_ptestc_256:
9316 case Intrinsic::x86_avx_ptestnzc_256:
9317 case Intrinsic::x86_avx_vtestz_ps:
9318 case Intrinsic::x86_avx_vtestc_ps:
9319 case Intrinsic::x86_avx_vtestnzc_ps:
9320 case Intrinsic::x86_avx_vtestz_pd:
9321 case Intrinsic::x86_avx_vtestc_pd:
9322 case Intrinsic::x86_avx_vtestnzc_pd:
9323 case Intrinsic::x86_avx_vtestz_ps_256:
9324 case Intrinsic::x86_avx_vtestc_ps_256:
9325 case Intrinsic::x86_avx_vtestnzc_ps_256:
9326 case Intrinsic::x86_avx_vtestz_pd_256:
9327 case Intrinsic::x86_avx_vtestc_pd_256:
9328 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9329 bool IsTestPacked = false;
9332 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9333 case Intrinsic::x86_avx_vtestz_ps:
9334 case Intrinsic::x86_avx_vtestz_pd:
9335 case Intrinsic::x86_avx_vtestz_ps_256:
9336 case Intrinsic::x86_avx_vtestz_pd_256:
9337 IsTestPacked = true; // Fallthrough
9338 case Intrinsic::x86_sse41_ptestz:
9339 case Intrinsic::x86_avx_ptestz_256:
9341 X86CC = X86::COND_E;
9343 case Intrinsic::x86_avx_vtestc_ps:
9344 case Intrinsic::x86_avx_vtestc_pd:
9345 case Intrinsic::x86_avx_vtestc_ps_256:
9346 case Intrinsic::x86_avx_vtestc_pd_256:
9347 IsTestPacked = true; // Fallthrough
9348 case Intrinsic::x86_sse41_ptestc:
9349 case Intrinsic::x86_avx_ptestc_256:
9351 X86CC = X86::COND_B;
9353 case Intrinsic::x86_avx_vtestnzc_ps:
9354 case Intrinsic::x86_avx_vtestnzc_pd:
9355 case Intrinsic::x86_avx_vtestnzc_ps_256:
9356 case Intrinsic::x86_avx_vtestnzc_pd_256:
9357 IsTestPacked = true; // Fallthrough
9358 case Intrinsic::x86_sse41_ptestnzc:
9359 case Intrinsic::x86_avx_ptestnzc_256:
9361 X86CC = X86::COND_A;
9365 SDValue LHS = Op.getOperand(1);
9366 SDValue RHS = Op.getOperand(2);
9367 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9368 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9369 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9370 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9371 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9374 // Fix vector shift instructions where the last operand is a non-immediate
9376 case Intrinsic::x86_avx2_pslli_w:
9377 case Intrinsic::x86_avx2_pslli_d:
9378 case Intrinsic::x86_avx2_pslli_q:
9379 case Intrinsic::x86_avx2_psrli_w:
9380 case Intrinsic::x86_avx2_psrli_d:
9381 case Intrinsic::x86_avx2_psrli_q:
9382 case Intrinsic::x86_avx2_psrai_w:
9383 case Intrinsic::x86_avx2_psrai_d:
9384 case Intrinsic::x86_sse2_pslli_w:
9385 case Intrinsic::x86_sse2_pslli_d:
9386 case Intrinsic::x86_sse2_pslli_q:
9387 case Intrinsic::x86_sse2_psrli_w:
9388 case Intrinsic::x86_sse2_psrli_d:
9389 case Intrinsic::x86_sse2_psrli_q:
9390 case Intrinsic::x86_sse2_psrai_w:
9391 case Intrinsic::x86_sse2_psrai_d:
9392 case Intrinsic::x86_mmx_pslli_w:
9393 case Intrinsic::x86_mmx_pslli_d:
9394 case Intrinsic::x86_mmx_pslli_q:
9395 case Intrinsic::x86_mmx_psrli_w:
9396 case Intrinsic::x86_mmx_psrli_d:
9397 case Intrinsic::x86_mmx_psrli_q:
9398 case Intrinsic::x86_mmx_psrai_w:
9399 case Intrinsic::x86_mmx_psrai_d: {
9400 SDValue ShAmt = Op.getOperand(2);
9401 if (isa<ConstantSDNode>(ShAmt))
9404 unsigned NewIntNo = 0;
9405 EVT ShAmtVT = MVT::v4i32;
9407 case Intrinsic::x86_sse2_pslli_w:
9408 NewIntNo = Intrinsic::x86_sse2_psll_w;
9410 case Intrinsic::x86_sse2_pslli_d:
9411 NewIntNo = Intrinsic::x86_sse2_psll_d;
9413 case Intrinsic::x86_sse2_pslli_q:
9414 NewIntNo = Intrinsic::x86_sse2_psll_q;
9416 case Intrinsic::x86_sse2_psrli_w:
9417 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9419 case Intrinsic::x86_sse2_psrli_d:
9420 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9422 case Intrinsic::x86_sse2_psrli_q:
9423 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9425 case Intrinsic::x86_sse2_psrai_w:
9426 NewIntNo = Intrinsic::x86_sse2_psra_w;
9428 case Intrinsic::x86_sse2_psrai_d:
9429 NewIntNo = Intrinsic::x86_sse2_psra_d;
9431 case Intrinsic::x86_avx2_pslli_w:
9432 NewIntNo = Intrinsic::x86_avx2_psll_w;
9434 case Intrinsic::x86_avx2_pslli_d:
9435 NewIntNo = Intrinsic::x86_avx2_psll_d;
9437 case Intrinsic::x86_avx2_pslli_q:
9438 NewIntNo = Intrinsic::x86_avx2_psll_q;
9440 case Intrinsic::x86_avx2_psrli_w:
9441 NewIntNo = Intrinsic::x86_avx2_psrl_w;
9443 case Intrinsic::x86_avx2_psrli_d:
9444 NewIntNo = Intrinsic::x86_avx2_psrl_d;
9446 case Intrinsic::x86_avx2_psrli_q:
9447 NewIntNo = Intrinsic::x86_avx2_psrl_q;
9449 case Intrinsic::x86_avx2_psrai_w:
9450 NewIntNo = Intrinsic::x86_avx2_psra_w;
9452 case Intrinsic::x86_avx2_psrai_d:
9453 NewIntNo = Intrinsic::x86_avx2_psra_d;
9456 ShAmtVT = MVT::v2i32;
9458 case Intrinsic::x86_mmx_pslli_w:
9459 NewIntNo = Intrinsic::x86_mmx_psll_w;
9461 case Intrinsic::x86_mmx_pslli_d:
9462 NewIntNo = Intrinsic::x86_mmx_psll_d;
9464 case Intrinsic::x86_mmx_pslli_q:
9465 NewIntNo = Intrinsic::x86_mmx_psll_q;
9467 case Intrinsic::x86_mmx_psrli_w:
9468 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9470 case Intrinsic::x86_mmx_psrli_d:
9471 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9473 case Intrinsic::x86_mmx_psrli_q:
9474 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9476 case Intrinsic::x86_mmx_psrai_w:
9477 NewIntNo = Intrinsic::x86_mmx_psra_w;
9479 case Intrinsic::x86_mmx_psrai_d:
9480 NewIntNo = Intrinsic::x86_mmx_psra_d;
9482 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9488 // The vector shift intrinsics with scalars uses 32b shift amounts but
9489 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9493 ShOps[1] = DAG.getConstant(0, MVT::i32);
9494 if (ShAmtVT == MVT::v4i32) {
9495 ShOps[2] = DAG.getUNDEF(MVT::i32);
9496 ShOps[3] = DAG.getUNDEF(MVT::i32);
9497 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9499 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9500 // FIXME this must be lowered to get rid of the invalid type.
9503 EVT VT = Op.getValueType();
9504 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9505 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9506 DAG.getConstant(NewIntNo, MVT::i32),
9507 Op.getOperand(1), ShAmt);
9512 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9513 SelectionDAG &DAG) const {
9514 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9515 MFI->setReturnAddressIsTaken(true);
9517 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9518 DebugLoc dl = Op.getDebugLoc();
9521 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9523 DAG.getConstant(TD->getPointerSize(),
9524 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9525 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9526 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9528 MachinePointerInfo(), false, false, false, 0);
9531 // Just load the return address.
9532 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9533 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9534 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9537 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9538 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9539 MFI->setFrameAddressIsTaken(true);
9541 EVT VT = Op.getValueType();
9542 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9543 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9544 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9545 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9547 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9548 MachinePointerInfo(),
9549 false, false, false, 0);
9553 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9554 SelectionDAG &DAG) const {
9555 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9558 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9559 MachineFunction &MF = DAG.getMachineFunction();
9560 SDValue Chain = Op.getOperand(0);
9561 SDValue Offset = Op.getOperand(1);
9562 SDValue Handler = Op.getOperand(2);
9563 DebugLoc dl = Op.getDebugLoc();
9565 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9566 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9568 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9570 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9571 DAG.getIntPtrConstant(TD->getPointerSize()));
9572 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9573 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9575 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9576 MF.getRegInfo().addLiveOut(StoreAddrReg);
9578 return DAG.getNode(X86ISD::EH_RETURN, dl,
9580 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9583 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9584 SelectionDAG &DAG) const {
9585 return Op.getOperand(0);
9588 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9589 SelectionDAG &DAG) const {
9590 SDValue Root = Op.getOperand(0);
9591 SDValue Trmp = Op.getOperand(1); // trampoline
9592 SDValue FPtr = Op.getOperand(2); // nested function
9593 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9594 DebugLoc dl = Op.getDebugLoc();
9596 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9598 if (Subtarget->is64Bit()) {
9599 SDValue OutChains[6];
9601 // Large code-model.
9602 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9603 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9605 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9606 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9608 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9610 // Load the pointer to the nested function into R11.
9611 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9612 SDValue Addr = Trmp;
9613 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9614 Addr, MachinePointerInfo(TrmpAddr),
9617 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9618 DAG.getConstant(2, MVT::i64));
9619 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9620 MachinePointerInfo(TrmpAddr, 2),
9623 // Load the 'nest' parameter value into R10.
9624 // R10 is specified in X86CallingConv.td
9625 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9626 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9627 DAG.getConstant(10, MVT::i64));
9628 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9629 Addr, MachinePointerInfo(TrmpAddr, 10),
9632 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9633 DAG.getConstant(12, MVT::i64));
9634 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9635 MachinePointerInfo(TrmpAddr, 12),
9638 // Jump to the nested function.
9639 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9640 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9641 DAG.getConstant(20, MVT::i64));
9642 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9643 Addr, MachinePointerInfo(TrmpAddr, 20),
9646 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9647 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9648 DAG.getConstant(22, MVT::i64));
9649 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9650 MachinePointerInfo(TrmpAddr, 22),
9653 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9655 const Function *Func =
9656 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9657 CallingConv::ID CC = Func->getCallingConv();
9662 llvm_unreachable("Unsupported calling convention");
9663 case CallingConv::C:
9664 case CallingConv::X86_StdCall: {
9665 // Pass 'nest' parameter in ECX.
9666 // Must be kept in sync with X86CallingConv.td
9669 // Check that ECX wasn't needed by an 'inreg' parameter.
9670 FunctionType *FTy = Func->getFunctionType();
9671 const AttrListPtr &Attrs = Func->getAttributes();
9673 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9674 unsigned InRegCount = 0;
9677 for (FunctionType::param_iterator I = FTy->param_begin(),
9678 E = FTy->param_end(); I != E; ++I, ++Idx)
9679 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9680 // FIXME: should only count parameters that are lowered to integers.
9681 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9683 if (InRegCount > 2) {
9684 report_fatal_error("Nest register in use - reduce number of inreg"
9690 case CallingConv::X86_FastCall:
9691 case CallingConv::X86_ThisCall:
9692 case CallingConv::Fast:
9693 // Pass 'nest' parameter in EAX.
9694 // Must be kept in sync with X86CallingConv.td
9699 SDValue OutChains[4];
9702 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9703 DAG.getConstant(10, MVT::i32));
9704 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9706 // This is storing the opcode for MOV32ri.
9707 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9708 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9709 OutChains[0] = DAG.getStore(Root, dl,
9710 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9711 Trmp, MachinePointerInfo(TrmpAddr),
9714 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9715 DAG.getConstant(1, MVT::i32));
9716 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9717 MachinePointerInfo(TrmpAddr, 1),
9720 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9721 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9722 DAG.getConstant(5, MVT::i32));
9723 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9724 MachinePointerInfo(TrmpAddr, 5),
9727 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9728 DAG.getConstant(6, MVT::i32));
9729 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9730 MachinePointerInfo(TrmpAddr, 6),
9733 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9737 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9738 SelectionDAG &DAG) const {
9740 The rounding mode is in bits 11:10 of FPSR, and has the following
9747 FLT_ROUNDS, on the other hand, expects the following:
9754 To perform the conversion, we do:
9755 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9758 MachineFunction &MF = DAG.getMachineFunction();
9759 const TargetMachine &TM = MF.getTarget();
9760 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9761 unsigned StackAlignment = TFI.getStackAlignment();
9762 EVT VT = Op.getValueType();
9763 DebugLoc DL = Op.getDebugLoc();
9765 // Save FP Control Word to stack slot
9766 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9767 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9770 MachineMemOperand *MMO =
9771 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9772 MachineMemOperand::MOStore, 2, 2);
9774 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9775 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9776 DAG.getVTList(MVT::Other),
9777 Ops, 2, MVT::i16, MMO);
9779 // Load FP Control Word from stack slot
9780 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9781 MachinePointerInfo(), false, false, false, 0);
9783 // Transform as necessary
9785 DAG.getNode(ISD::SRL, DL, MVT::i16,
9786 DAG.getNode(ISD::AND, DL, MVT::i16,
9787 CWD, DAG.getConstant(0x800, MVT::i16)),
9788 DAG.getConstant(11, MVT::i8));
9790 DAG.getNode(ISD::SRL, DL, MVT::i16,
9791 DAG.getNode(ISD::AND, DL, MVT::i16,
9792 CWD, DAG.getConstant(0x400, MVT::i16)),
9793 DAG.getConstant(9, MVT::i8));
9796 DAG.getNode(ISD::AND, DL, MVT::i16,
9797 DAG.getNode(ISD::ADD, DL, MVT::i16,
9798 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9799 DAG.getConstant(1, MVT::i16)),
9800 DAG.getConstant(3, MVT::i16));
9803 return DAG.getNode((VT.getSizeInBits() < 16 ?
9804 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9807 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9808 EVT VT = Op.getValueType();
9810 unsigned NumBits = VT.getSizeInBits();
9811 DebugLoc dl = Op.getDebugLoc();
9813 Op = Op.getOperand(0);
9814 if (VT == MVT::i8) {
9815 // Zero extend to i32 since there is not an i8 bsr.
9817 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9820 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9821 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9822 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9824 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9827 DAG.getConstant(NumBits+NumBits-1, OpVT),
9828 DAG.getConstant(X86::COND_E, MVT::i8),
9831 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9833 // Finally xor with NumBits-1.
9834 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9837 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9841 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9842 EVT VT = Op.getValueType();
9844 unsigned NumBits = VT.getSizeInBits();
9845 DebugLoc dl = Op.getDebugLoc();
9847 Op = Op.getOperand(0);
9848 if (VT == MVT::i8) {
9850 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9853 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9854 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9855 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9857 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9860 DAG.getConstant(NumBits, OpVT),
9861 DAG.getConstant(X86::COND_E, MVT::i8),
9864 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9867 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9871 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9872 // ones, and then concatenate the result back.
9873 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9874 EVT VT = Op.getValueType();
9876 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9877 "Unsupported value type for operation");
9879 int NumElems = VT.getVectorNumElements();
9880 DebugLoc dl = Op.getDebugLoc();
9881 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9882 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9884 // Extract the LHS vectors
9885 SDValue LHS = Op.getOperand(0);
9886 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9887 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9889 // Extract the RHS vectors
9890 SDValue RHS = Op.getOperand(1);
9891 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9892 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9894 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9895 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9897 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9898 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9899 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9902 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9903 assert(Op.getValueType().getSizeInBits() == 256 &&
9904 Op.getValueType().isInteger() &&
9905 "Only handle AVX 256-bit vector integer operation");
9906 return Lower256IntArith(Op, DAG);
9909 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9910 assert(Op.getValueType().getSizeInBits() == 256 &&
9911 Op.getValueType().isInteger() &&
9912 "Only handle AVX 256-bit vector integer operation");
9913 return Lower256IntArith(Op, DAG);
9916 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9917 EVT VT = Op.getValueType();
9919 // Decompose 256-bit ops into smaller 128-bit ops.
9920 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
9921 return Lower256IntArith(Op, DAG);
9923 DebugLoc dl = Op.getDebugLoc();
9925 SDValue A = Op.getOperand(0);
9926 SDValue B = Op.getOperand(1);
9928 if (VT == MVT::v4i64) {
9929 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2");
9931 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32);
9932 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32);
9933 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b );
9934 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi );
9935 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b );
9937 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 );
9938 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 );
9939 // return AloBlo + AloBhi + AhiBlo;
9941 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9942 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9943 A, DAG.getConstant(32, MVT::i32));
9944 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9945 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9946 B, DAG.getConstant(32, MVT::i32));
9947 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9948 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9950 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9951 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9953 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9954 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9956 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9957 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9958 AloBhi, DAG.getConstant(32, MVT::i32));
9959 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9960 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9961 AhiBlo, DAG.getConstant(32, MVT::i32));
9962 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9963 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9967 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9969 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9970 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9971 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9972 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9973 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9975 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9976 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9977 // return AloBlo + AloBhi + AhiBlo;
9979 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9980 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9981 A, DAG.getConstant(32, MVT::i32));
9982 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9983 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9984 B, DAG.getConstant(32, MVT::i32));
9985 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9986 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9988 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9989 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9991 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9992 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9994 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9995 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9996 AloBhi, DAG.getConstant(32, MVT::i32));
9997 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9998 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9999 AhiBlo, DAG.getConstant(32, MVT::i32));
10000 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10001 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10005 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10007 EVT VT = Op.getValueType();
10008 DebugLoc dl = Op.getDebugLoc();
10009 SDValue R = Op.getOperand(0);
10010 SDValue Amt = Op.getOperand(1);
10011 LLVMContext *Context = DAG.getContext();
10013 if (!Subtarget->hasXMMInt())
10016 // Optimize shl/srl/sra with constant shift amount.
10017 if (isSplatVector(Amt.getNode())) {
10018 SDValue SclrAmt = Amt->getOperand(0);
10019 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10020 uint64_t ShiftAmt = C->getZExtValue();
10022 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SHL) {
10023 // Make a large shift.
10025 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10026 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10027 R, DAG.getConstant(ShiftAmt, MVT::i32));
10028 // Zero out the rightmost bits.
10029 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U << ShiftAmt),
10031 return DAG.getNode(ISD::AND, dl, VT, SHL,
10032 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10035 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
10036 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10037 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10038 R, DAG.getConstant(ShiftAmt, MVT::i32));
10040 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
10041 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10042 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10043 R, DAG.getConstant(ShiftAmt, MVT::i32));
10045 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
10046 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10047 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10048 R, DAG.getConstant(ShiftAmt, MVT::i32));
10050 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRL) {
10051 // Make a large shift.
10053 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10054 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10055 R, DAG.getConstant(ShiftAmt, MVT::i32));
10056 // Zero out the leftmost bits.
10057 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10059 return DAG.getNode(ISD::AND, dl, VT, SRL,
10060 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10063 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
10064 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10065 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10066 R, DAG.getConstant(ShiftAmt, MVT::i32));
10068 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
10069 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10070 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
10071 R, DAG.getConstant(ShiftAmt, MVT::i32));
10073 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
10074 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10075 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10076 R, DAG.getConstant(ShiftAmt, MVT::i32));
10078 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
10079 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10080 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
10081 R, DAG.getConstant(ShiftAmt, MVT::i32));
10083 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
10084 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10085 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
10086 R, DAG.getConstant(ShiftAmt, MVT::i32));
10088 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRA) {
10089 if (ShiftAmt == 7) {
10090 // R s>> 7 === R s< 0
10091 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
10092 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
10095 // R s>> a === ((R u>> a) ^ m) - m
10096 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10097 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10099 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10100 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10101 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10105 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10106 if (Op.getOpcode() == ISD::SHL) {
10107 // Make a large shift.
10109 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10110 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
10111 R, DAG.getConstant(ShiftAmt, MVT::i32));
10112 // Zero out the rightmost bits.
10113 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U << ShiftAmt),
10115 return DAG.getNode(ISD::AND, dl, VT, SHL,
10116 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10118 if (Op.getOpcode() == ISD::SRL) {
10119 // Make a large shift.
10121 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10122 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
10123 R, DAG.getConstant(ShiftAmt, MVT::i32));
10124 // Zero out the leftmost bits.
10125 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10127 return DAG.getNode(ISD::AND, dl, VT, SRL,
10128 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10130 if (Op.getOpcode() == ISD::SRA) {
10131 if (ShiftAmt == 7) {
10132 // R s>> 7 === R s< 0
10133 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
10134 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
10137 // R s>> a === ((R u>> a) ^ m) - m
10138 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10139 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10141 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10142 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10143 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10150 // Lower SHL with variable shift amount.
10151 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10152 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10153 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10154 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
10156 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
10158 std::vector<Constant*> CV(4, CI);
10159 Constant *C = ConstantVector::get(CV);
10160 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10161 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10162 MachinePointerInfo::getConstantPool(),
10163 false, false, false, 16);
10165 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10166 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10167 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10168 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10170 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10171 assert((Subtarget->hasSSE2() || Subtarget->hasAVX()) &&
10172 "Need SSE2 for pslli/pcmpeq.");
10175 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10176 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10177 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
10179 // Turn 'a' into a mask suitable for VSELECT
10180 SDValue VSelM = DAG.getConstant(0x80, VT);
10181 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10182 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10183 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10186 SDValue CM1 = DAG.getConstant(0x0f, VT);
10187 SDValue CM2 = DAG.getConstant(0x3f, VT);
10189 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10190 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10191 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10192 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10193 DAG.getConstant(4, MVT::i32));
10194 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10197 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10198 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10199 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10200 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10203 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10204 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10205 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10206 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10207 DAG.getConstant(2, MVT::i32));
10208 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10211 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10212 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10213 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10214 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10217 // return VSELECT(r, r+r, a);
10218 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10219 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10223 // Decompose 256-bit shifts into smaller 128-bit shifts.
10224 if (VT.getSizeInBits() == 256) {
10225 int NumElems = VT.getVectorNumElements();
10226 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10227 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10229 // Extract the two vectors
10230 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10231 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10234 // Recreate the shift amount vectors
10235 SDValue Amt1, Amt2;
10236 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10237 // Constant shift amount
10238 SmallVector<SDValue, 4> Amt1Csts;
10239 SmallVector<SDValue, 4> Amt2Csts;
10240 for (int i = 0; i < NumElems/2; ++i)
10241 Amt1Csts.push_back(Amt->getOperand(i));
10242 for (int i = NumElems/2; i < NumElems; ++i)
10243 Amt2Csts.push_back(Amt->getOperand(i));
10245 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10246 &Amt1Csts[0], NumElems/2);
10247 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10248 &Amt2Csts[0], NumElems/2);
10250 // Variable shift amount
10251 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10252 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10256 // Issue new vector shifts for the smaller types
10257 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10258 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10260 // Concatenate the result back
10261 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10267 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10268 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10269 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10270 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10271 // has only one use.
10272 SDNode *N = Op.getNode();
10273 SDValue LHS = N->getOperand(0);
10274 SDValue RHS = N->getOperand(1);
10275 unsigned BaseOp = 0;
10277 DebugLoc DL = Op.getDebugLoc();
10278 switch (Op.getOpcode()) {
10279 default: llvm_unreachable("Unknown ovf instruction!");
10281 // A subtract of one will be selected as a INC. Note that INC doesn't
10282 // set CF, so we can't do this for UADDO.
10283 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10285 BaseOp = X86ISD::INC;
10286 Cond = X86::COND_O;
10289 BaseOp = X86ISD::ADD;
10290 Cond = X86::COND_O;
10293 BaseOp = X86ISD::ADD;
10294 Cond = X86::COND_B;
10297 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10298 // set CF, so we can't do this for USUBO.
10299 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10301 BaseOp = X86ISD::DEC;
10302 Cond = X86::COND_O;
10305 BaseOp = X86ISD::SUB;
10306 Cond = X86::COND_O;
10309 BaseOp = X86ISD::SUB;
10310 Cond = X86::COND_B;
10313 BaseOp = X86ISD::SMUL;
10314 Cond = X86::COND_O;
10316 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10317 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10319 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10322 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10323 DAG.getConstant(X86::COND_O, MVT::i32),
10324 SDValue(Sum.getNode(), 2));
10326 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10330 // Also sets EFLAGS.
10331 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10332 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10335 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10336 DAG.getConstant(Cond, MVT::i32),
10337 SDValue(Sum.getNode(), 1));
10339 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10342 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
10343 DebugLoc dl = Op.getDebugLoc();
10344 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10345 EVT VT = Op.getValueType();
10347 if (Subtarget->hasXMMInt() && VT.isVector()) {
10348 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10349 ExtraVT.getScalarType().getSizeInBits();
10350 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10352 unsigned SHLIntrinsicsID = 0;
10353 unsigned SRAIntrinsicsID = 0;
10354 switch (VT.getSimpleVT().SimpleTy) {
10358 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
10359 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
10362 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
10363 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
10367 if (!Subtarget->hasAVX())
10369 if (!Subtarget->hasAVX2()) {
10370 // needs to be split
10371 int NumElems = VT.getVectorNumElements();
10372 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10373 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10375 // Extract the LHS vectors
10376 SDValue LHS = Op.getOperand(0);
10377 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10378 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10380 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10381 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10383 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10384 int ExtraNumElems = ExtraVT.getVectorNumElements();
10385 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10387 SDValue Extra = DAG.getValueType(ExtraVT);
10389 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10390 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10392 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10394 if (VT == MVT::v8i32) {
10395 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_d;
10396 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_d;
10398 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_w;
10399 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_w;
10403 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10404 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
10405 Op.getOperand(0), ShAmt);
10407 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10408 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
10416 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10417 DebugLoc dl = Op.getDebugLoc();
10419 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10420 // There isn't any reason to disable it if the target processor supports it.
10421 if (!Subtarget->hasXMMInt() && !Subtarget->is64Bit()) {
10422 SDValue Chain = Op.getOperand(0);
10423 SDValue Zero = DAG.getConstant(0, MVT::i32);
10425 DAG.getRegister(X86::ESP, MVT::i32), // Base
10426 DAG.getTargetConstant(1, MVT::i8), // Scale
10427 DAG.getRegister(0, MVT::i32), // Index
10428 DAG.getTargetConstant(0, MVT::i32), // Disp
10429 DAG.getRegister(0, MVT::i32), // Segment.
10434 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10435 array_lengthof(Ops));
10436 return SDValue(Res, 0);
10439 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10441 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10443 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10444 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10445 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10446 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10448 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10449 if (!Op1 && !Op2 && !Op3 && Op4)
10450 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10452 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10453 if (Op1 && !Op2 && !Op3 && !Op4)
10454 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10456 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10458 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10461 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10462 SelectionDAG &DAG) const {
10463 DebugLoc dl = Op.getDebugLoc();
10464 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10465 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10466 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10467 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10469 // The only fence that needs an instruction is a sequentially-consistent
10470 // cross-thread fence.
10471 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10472 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10473 // no-sse2). There isn't any reason to disable it if the target processor
10475 if (Subtarget->hasXMMInt() || Subtarget->is64Bit())
10476 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10478 SDValue Chain = Op.getOperand(0);
10479 SDValue Zero = DAG.getConstant(0, MVT::i32);
10481 DAG.getRegister(X86::ESP, MVT::i32), // Base
10482 DAG.getTargetConstant(1, MVT::i8), // Scale
10483 DAG.getRegister(0, MVT::i32), // Index
10484 DAG.getTargetConstant(0, MVT::i32), // Disp
10485 DAG.getRegister(0, MVT::i32), // Segment.
10490 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10491 array_lengthof(Ops));
10492 return SDValue(Res, 0);
10495 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10496 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10500 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10501 EVT T = Op.getValueType();
10502 DebugLoc DL = Op.getDebugLoc();
10505 switch(T.getSimpleVT().SimpleTy) {
10507 assert(false && "Invalid value type!");
10508 case MVT::i8: Reg = X86::AL; size = 1; break;
10509 case MVT::i16: Reg = X86::AX; size = 2; break;
10510 case MVT::i32: Reg = X86::EAX; size = 4; break;
10512 assert(Subtarget->is64Bit() && "Node not type legal!");
10513 Reg = X86::RAX; size = 8;
10516 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10517 Op.getOperand(2), SDValue());
10518 SDValue Ops[] = { cpIn.getValue(0),
10521 DAG.getTargetConstant(size, MVT::i8),
10522 cpIn.getValue(1) };
10523 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10524 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10525 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10528 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10532 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10533 SelectionDAG &DAG) const {
10534 assert(Subtarget->is64Bit() && "Result not type legalized?");
10535 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10536 SDValue TheChain = Op.getOperand(0);
10537 DebugLoc dl = Op.getDebugLoc();
10538 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10539 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10540 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10542 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10543 DAG.getConstant(32, MVT::i8));
10545 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10548 return DAG.getMergeValues(Ops, 2, dl);
10551 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10552 SelectionDAG &DAG) const {
10553 EVT SrcVT = Op.getOperand(0).getValueType();
10554 EVT DstVT = Op.getValueType();
10555 assert(Subtarget->is64Bit() && !Subtarget->hasXMMInt() &&
10556 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10557 assert((DstVT == MVT::i64 ||
10558 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10559 "Unexpected custom BITCAST");
10560 // i64 <=> MMX conversions are Legal.
10561 if (SrcVT==MVT::i64 && DstVT.isVector())
10563 if (DstVT==MVT::i64 && SrcVT.isVector())
10565 // MMX <=> MMX conversions are Legal.
10566 if (SrcVT.isVector() && DstVT.isVector())
10568 // All other conversions need to be expanded.
10572 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10573 SDNode *Node = Op.getNode();
10574 DebugLoc dl = Node->getDebugLoc();
10575 EVT T = Node->getValueType(0);
10576 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10577 DAG.getConstant(0, T), Node->getOperand(2));
10578 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10579 cast<AtomicSDNode>(Node)->getMemoryVT(),
10580 Node->getOperand(0),
10581 Node->getOperand(1), negOp,
10582 cast<AtomicSDNode>(Node)->getSrcValue(),
10583 cast<AtomicSDNode>(Node)->getAlignment(),
10584 cast<AtomicSDNode>(Node)->getOrdering(),
10585 cast<AtomicSDNode>(Node)->getSynchScope());
10588 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10589 SDNode *Node = Op.getNode();
10590 DebugLoc dl = Node->getDebugLoc();
10591 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10593 // Convert seq_cst store -> xchg
10594 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10595 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10596 // (The only way to get a 16-byte store is cmpxchg16b)
10597 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10598 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10599 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10600 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10601 cast<AtomicSDNode>(Node)->getMemoryVT(),
10602 Node->getOperand(0),
10603 Node->getOperand(1), Node->getOperand(2),
10604 cast<AtomicSDNode>(Node)->getMemOperand(),
10605 cast<AtomicSDNode>(Node)->getOrdering(),
10606 cast<AtomicSDNode>(Node)->getSynchScope());
10607 return Swap.getValue(1);
10609 // Other atomic stores have a simple pattern.
10613 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10614 EVT VT = Op.getNode()->getValueType(0);
10616 // Let legalize expand this if it isn't a legal type yet.
10617 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10620 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10623 bool ExtraOp = false;
10624 switch (Op.getOpcode()) {
10625 default: assert(0 && "Invalid code");
10626 case ISD::ADDC: Opc = X86ISD::ADD; break;
10627 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10628 case ISD::SUBC: Opc = X86ISD::SUB; break;
10629 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10633 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10635 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10636 Op.getOperand(1), Op.getOperand(2));
10639 /// LowerOperation - Provide custom lowering hooks for some operations.
10641 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10642 switch (Op.getOpcode()) {
10643 default: llvm_unreachable("Should not custom lower this!");
10644 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10645 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10646 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10647 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10648 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10649 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10650 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10651 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10652 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10653 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10654 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10655 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10656 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10657 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10658 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10659 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10660 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10661 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10662 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10663 case ISD::SHL_PARTS:
10664 case ISD::SRA_PARTS:
10665 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10666 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10667 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10668 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10669 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10670 case ISD::FABS: return LowerFABS(Op, DAG);
10671 case ISD::FNEG: return LowerFNEG(Op, DAG);
10672 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10673 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10674 case ISD::SETCC: return LowerSETCC(Op, DAG);
10675 case ISD::SELECT: return LowerSELECT(Op, DAG);
10676 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10677 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10678 case ISD::VASTART: return LowerVASTART(Op, DAG);
10679 case ISD::VAARG: return LowerVAARG(Op, DAG);
10680 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10681 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10682 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10683 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10684 case ISD::FRAME_TO_ARGS_OFFSET:
10685 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10686 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10687 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10688 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10689 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10690 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10691 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10692 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10693 case ISD::MUL: return LowerMUL(Op, DAG);
10696 case ISD::SHL: return LowerShift(Op, DAG);
10702 case ISD::UMULO: return LowerXALUO(Op, DAG);
10703 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10704 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10708 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10709 case ISD::ADD: return LowerADD(Op, DAG);
10710 case ISD::SUB: return LowerSUB(Op, DAG);
10714 static void ReplaceATOMIC_LOAD(SDNode *Node,
10715 SmallVectorImpl<SDValue> &Results,
10716 SelectionDAG &DAG) {
10717 DebugLoc dl = Node->getDebugLoc();
10718 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10720 // Convert wide load -> cmpxchg8b/cmpxchg16b
10721 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10722 // (The only way to get a 16-byte load is cmpxchg16b)
10723 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10724 SDValue Zero = DAG.getConstant(0, VT);
10725 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10726 Node->getOperand(0),
10727 Node->getOperand(1), Zero, Zero,
10728 cast<AtomicSDNode>(Node)->getMemOperand(),
10729 cast<AtomicSDNode>(Node)->getOrdering(),
10730 cast<AtomicSDNode>(Node)->getSynchScope());
10731 Results.push_back(Swap.getValue(0));
10732 Results.push_back(Swap.getValue(1));
10735 void X86TargetLowering::
10736 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10737 SelectionDAG &DAG, unsigned NewOp) const {
10738 DebugLoc dl = Node->getDebugLoc();
10739 assert (Node->getValueType(0) == MVT::i64 &&
10740 "Only know how to expand i64 atomics");
10742 SDValue Chain = Node->getOperand(0);
10743 SDValue In1 = Node->getOperand(1);
10744 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10745 Node->getOperand(2), DAG.getIntPtrConstant(0));
10746 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10747 Node->getOperand(2), DAG.getIntPtrConstant(1));
10748 SDValue Ops[] = { Chain, In1, In2L, In2H };
10749 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10751 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10752 cast<MemSDNode>(Node)->getMemOperand());
10753 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10754 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10755 Results.push_back(Result.getValue(2));
10758 /// ReplaceNodeResults - Replace a node with an illegal result type
10759 /// with a new node built out of custom code.
10760 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10761 SmallVectorImpl<SDValue>&Results,
10762 SelectionDAG &DAG) const {
10763 DebugLoc dl = N->getDebugLoc();
10764 switch (N->getOpcode()) {
10766 assert(false && "Do not know how to custom type legalize this operation!");
10768 case ISD::SIGN_EXTEND_INREG:
10773 // We don't want to expand or promote these.
10775 case ISD::FP_TO_SINT: {
10776 std::pair<SDValue,SDValue> Vals =
10777 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10778 SDValue FIST = Vals.first, StackSlot = Vals.second;
10779 if (FIST.getNode() != 0) {
10780 EVT VT = N->getValueType(0);
10781 // Return a load from the stack slot.
10782 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10783 MachinePointerInfo(),
10784 false, false, false, 0));
10788 case ISD::READCYCLECOUNTER: {
10789 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10790 SDValue TheChain = N->getOperand(0);
10791 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10792 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10794 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10796 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10797 SDValue Ops[] = { eax, edx };
10798 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10799 Results.push_back(edx.getValue(1));
10802 case ISD::ATOMIC_CMP_SWAP: {
10803 EVT T = N->getValueType(0);
10804 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10805 bool Regs64bit = T == MVT::i128;
10806 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10807 SDValue cpInL, cpInH;
10808 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10809 DAG.getConstant(0, HalfT));
10810 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10811 DAG.getConstant(1, HalfT));
10812 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10813 Regs64bit ? X86::RAX : X86::EAX,
10815 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10816 Regs64bit ? X86::RDX : X86::EDX,
10817 cpInH, cpInL.getValue(1));
10818 SDValue swapInL, swapInH;
10819 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10820 DAG.getConstant(0, HalfT));
10821 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10822 DAG.getConstant(1, HalfT));
10823 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10824 Regs64bit ? X86::RBX : X86::EBX,
10825 swapInL, cpInH.getValue(1));
10826 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10827 Regs64bit ? X86::RCX : X86::ECX,
10828 swapInH, swapInL.getValue(1));
10829 SDValue Ops[] = { swapInH.getValue(0),
10831 swapInH.getValue(1) };
10832 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10833 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10834 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10835 X86ISD::LCMPXCHG8_DAG;
10836 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10838 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10839 Regs64bit ? X86::RAX : X86::EAX,
10840 HalfT, Result.getValue(1));
10841 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10842 Regs64bit ? X86::RDX : X86::EDX,
10843 HalfT, cpOutL.getValue(2));
10844 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10845 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10846 Results.push_back(cpOutH.getValue(1));
10849 case ISD::ATOMIC_LOAD_ADD:
10850 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10852 case ISD::ATOMIC_LOAD_AND:
10853 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10855 case ISD::ATOMIC_LOAD_NAND:
10856 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10858 case ISD::ATOMIC_LOAD_OR:
10859 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10861 case ISD::ATOMIC_LOAD_SUB:
10862 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10864 case ISD::ATOMIC_LOAD_XOR:
10865 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10867 case ISD::ATOMIC_SWAP:
10868 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10870 case ISD::ATOMIC_LOAD:
10871 ReplaceATOMIC_LOAD(N, Results, DAG);
10875 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10877 default: return NULL;
10878 case X86ISD::BSF: return "X86ISD::BSF";
10879 case X86ISD::BSR: return "X86ISD::BSR";
10880 case X86ISD::SHLD: return "X86ISD::SHLD";
10881 case X86ISD::SHRD: return "X86ISD::SHRD";
10882 case X86ISD::FAND: return "X86ISD::FAND";
10883 case X86ISD::FOR: return "X86ISD::FOR";
10884 case X86ISD::FXOR: return "X86ISD::FXOR";
10885 case X86ISD::FSRL: return "X86ISD::FSRL";
10886 case X86ISD::FILD: return "X86ISD::FILD";
10887 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10888 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10889 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10890 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10891 case X86ISD::FLD: return "X86ISD::FLD";
10892 case X86ISD::FST: return "X86ISD::FST";
10893 case X86ISD::CALL: return "X86ISD::CALL";
10894 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10895 case X86ISD::BT: return "X86ISD::BT";
10896 case X86ISD::CMP: return "X86ISD::CMP";
10897 case X86ISD::COMI: return "X86ISD::COMI";
10898 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10899 case X86ISD::SETCC: return "X86ISD::SETCC";
10900 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10901 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10902 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10903 case X86ISD::CMOV: return "X86ISD::CMOV";
10904 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10905 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10906 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10907 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10908 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10909 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10910 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10911 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10912 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10913 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10914 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10915 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10916 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10917 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10918 case X86ISD::PSIGN: return "X86ISD::PSIGN";
10919 case X86ISD::BLENDV: return "X86ISD::BLENDV";
10920 case X86ISD::HADD: return "X86ISD::HADD";
10921 case X86ISD::HSUB: return "X86ISD::HSUB";
10922 case X86ISD::FHADD: return "X86ISD::FHADD";
10923 case X86ISD::FHSUB: return "X86ISD::FHSUB";
10924 case X86ISD::FMAX: return "X86ISD::FMAX";
10925 case X86ISD::FMIN: return "X86ISD::FMIN";
10926 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10927 case X86ISD::FRCP: return "X86ISD::FRCP";
10928 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10929 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10930 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10931 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10932 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10933 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10934 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10935 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10936 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10937 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10938 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10939 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10940 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10941 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10942 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10943 case X86ISD::VSHL: return "X86ISD::VSHL";
10944 case X86ISD::VSRL: return "X86ISD::VSRL";
10945 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10946 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10947 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10948 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10949 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10950 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10951 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10952 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10953 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10954 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10955 case X86ISD::ADD: return "X86ISD::ADD";
10956 case X86ISD::SUB: return "X86ISD::SUB";
10957 case X86ISD::ADC: return "X86ISD::ADC";
10958 case X86ISD::SBB: return "X86ISD::SBB";
10959 case X86ISD::SMUL: return "X86ISD::SMUL";
10960 case X86ISD::UMUL: return "X86ISD::UMUL";
10961 case X86ISD::INC: return "X86ISD::INC";
10962 case X86ISD::DEC: return "X86ISD::DEC";
10963 case X86ISD::OR: return "X86ISD::OR";
10964 case X86ISD::XOR: return "X86ISD::XOR";
10965 case X86ISD::AND: return "X86ISD::AND";
10966 case X86ISD::ANDN: return "X86ISD::ANDN";
10967 case X86ISD::BLSI: return "X86ISD::BLSI";
10968 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
10969 case X86ISD::BLSR: return "X86ISD::BLSR";
10970 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10971 case X86ISD::PTEST: return "X86ISD::PTEST";
10972 case X86ISD::TESTP: return "X86ISD::TESTP";
10973 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10974 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10975 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10976 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10977 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10978 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10979 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10980 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10981 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10982 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10983 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10984 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10985 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10986 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10987 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10988 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10989 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10990 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10991 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10992 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10993 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
10994 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
10995 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10996 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
10997 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
10998 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10999 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11000 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11001 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11002 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11006 // isLegalAddressingMode - Return true if the addressing mode represented
11007 // by AM is legal for this target, for a load/store of the specified type.
11008 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11010 // X86 supports extremely general addressing modes.
11011 CodeModel::Model M = getTargetMachine().getCodeModel();
11012 Reloc::Model R = getTargetMachine().getRelocationModel();
11014 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11015 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11020 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11022 // If a reference to this global requires an extra load, we can't fold it.
11023 if (isGlobalStubReference(GVFlags))
11026 // If BaseGV requires a register for the PIC base, we cannot also have a
11027 // BaseReg specified.
11028 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11031 // If lower 4G is not available, then we must use rip-relative addressing.
11032 if ((M != CodeModel::Small || R != Reloc::Static) &&
11033 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11037 switch (AM.Scale) {
11043 // These scales always work.
11048 // These scales are formed with basereg+scalereg. Only accept if there is
11053 default: // Other stuff never works.
11061 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11062 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11064 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11065 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11066 if (NumBits1 <= NumBits2)
11071 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11072 if (!VT1.isInteger() || !VT2.isInteger())
11074 unsigned NumBits1 = VT1.getSizeInBits();
11075 unsigned NumBits2 = VT2.getSizeInBits();
11076 if (NumBits1 <= NumBits2)
11081 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11082 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11083 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11086 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11087 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11088 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11091 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11092 // i16 instructions are longer (0x66 prefix) and potentially slower.
11093 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11096 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11097 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11098 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11099 /// are assumed to be legal.
11101 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11103 // Very little shuffling can be done for 64-bit vectors right now.
11104 if (VT.getSizeInBits() == 64)
11107 // FIXME: pshufb, blends, shifts.
11108 return (VT.getVectorNumElements() == 2 ||
11109 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11110 isMOVLMask(M, VT) ||
11111 isSHUFPMask(M, VT) ||
11112 isPSHUFDMask(M, VT) ||
11113 isPSHUFHWMask(M, VT) ||
11114 isPSHUFLWMask(M, VT) ||
11115 isPALIGNRMask(M, VT, Subtarget->hasSSSE3orAVX()) ||
11116 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11117 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11118 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11119 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11123 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11125 unsigned NumElts = VT.getVectorNumElements();
11126 // FIXME: This collection of masks seems suspect.
11129 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11130 return (isMOVLMask(Mask, VT) ||
11131 isCommutedMOVLMask(Mask, VT, true) ||
11132 isSHUFPMask(Mask, VT) ||
11133 isSHUFPMask(Mask, VT, /* Commuted */ true));
11138 //===----------------------------------------------------------------------===//
11139 // X86 Scheduler Hooks
11140 //===----------------------------------------------------------------------===//
11142 // private utility function
11143 MachineBasicBlock *
11144 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11145 MachineBasicBlock *MBB,
11152 TargetRegisterClass *RC,
11153 bool invSrc) const {
11154 // For the atomic bitwise operator, we generate
11157 // ld t1 = [bitinstr.addr]
11158 // op t2 = t1, [bitinstr.val]
11160 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11162 // fallthrough -->nextMBB
11163 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11164 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11165 MachineFunction::iterator MBBIter = MBB;
11168 /// First build the CFG
11169 MachineFunction *F = MBB->getParent();
11170 MachineBasicBlock *thisMBB = MBB;
11171 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11172 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11173 F->insert(MBBIter, newMBB);
11174 F->insert(MBBIter, nextMBB);
11176 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11177 nextMBB->splice(nextMBB->begin(), thisMBB,
11178 llvm::next(MachineBasicBlock::iterator(bInstr)),
11180 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11182 // Update thisMBB to fall through to newMBB
11183 thisMBB->addSuccessor(newMBB);
11185 // newMBB jumps to itself and fall through to nextMBB
11186 newMBB->addSuccessor(nextMBB);
11187 newMBB->addSuccessor(newMBB);
11189 // Insert instructions into newMBB based on incoming instruction
11190 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11191 "unexpected number of operands");
11192 DebugLoc dl = bInstr->getDebugLoc();
11193 MachineOperand& destOper = bInstr->getOperand(0);
11194 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11195 int numArgs = bInstr->getNumOperands() - 1;
11196 for (int i=0; i < numArgs; ++i)
11197 argOpers[i] = &bInstr->getOperand(i+1);
11199 // x86 address has 4 operands: base, index, scale, and displacement
11200 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11201 int valArgIndx = lastAddrIndx + 1;
11203 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11204 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11205 for (int i=0; i <= lastAddrIndx; ++i)
11206 (*MIB).addOperand(*argOpers[i]);
11208 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11210 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11215 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11216 assert((argOpers[valArgIndx]->isReg() ||
11217 argOpers[valArgIndx]->isImm()) &&
11218 "invalid operand");
11219 if (argOpers[valArgIndx]->isReg())
11220 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11222 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11224 (*MIB).addOperand(*argOpers[valArgIndx]);
11226 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11229 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11230 for (int i=0; i <= lastAddrIndx; ++i)
11231 (*MIB).addOperand(*argOpers[i]);
11233 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11234 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11235 bInstr->memoperands_end());
11237 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11238 MIB.addReg(EAXreg);
11241 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11243 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11247 // private utility function: 64 bit atomics on 32 bit host.
11248 MachineBasicBlock *
11249 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11250 MachineBasicBlock *MBB,
11255 bool invSrc) const {
11256 // For the atomic bitwise operator, we generate
11257 // thisMBB (instructions are in pairs, except cmpxchg8b)
11258 // ld t1,t2 = [bitinstr.addr]
11260 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11261 // op t5, t6 <- out1, out2, [bitinstr.val]
11262 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11263 // mov ECX, EBX <- t5, t6
11264 // mov EAX, EDX <- t1, t2
11265 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11266 // mov t3, t4 <- EAX, EDX
11268 // result in out1, out2
11269 // fallthrough -->nextMBB
11271 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11272 const unsigned LoadOpc = X86::MOV32rm;
11273 const unsigned NotOpc = X86::NOT32r;
11274 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11275 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11276 MachineFunction::iterator MBBIter = MBB;
11279 /// First build the CFG
11280 MachineFunction *F = MBB->getParent();
11281 MachineBasicBlock *thisMBB = MBB;
11282 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11283 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11284 F->insert(MBBIter, newMBB);
11285 F->insert(MBBIter, nextMBB);
11287 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11288 nextMBB->splice(nextMBB->begin(), thisMBB,
11289 llvm::next(MachineBasicBlock::iterator(bInstr)),
11291 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11293 // Update thisMBB to fall through to newMBB
11294 thisMBB->addSuccessor(newMBB);
11296 // newMBB jumps to itself and fall through to nextMBB
11297 newMBB->addSuccessor(nextMBB);
11298 newMBB->addSuccessor(newMBB);
11300 DebugLoc dl = bInstr->getDebugLoc();
11301 // Insert instructions into newMBB based on incoming instruction
11302 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11303 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11304 "unexpected number of operands");
11305 MachineOperand& dest1Oper = bInstr->getOperand(0);
11306 MachineOperand& dest2Oper = bInstr->getOperand(1);
11307 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11308 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11309 argOpers[i] = &bInstr->getOperand(i+2);
11311 // We use some of the operands multiple times, so conservatively just
11312 // clear any kill flags that might be present.
11313 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11314 argOpers[i]->setIsKill(false);
11317 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11318 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11320 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11321 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11322 for (int i=0; i <= lastAddrIndx; ++i)
11323 (*MIB).addOperand(*argOpers[i]);
11324 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11325 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11326 // add 4 to displacement.
11327 for (int i=0; i <= lastAddrIndx-2; ++i)
11328 (*MIB).addOperand(*argOpers[i]);
11329 MachineOperand newOp3 = *(argOpers[3]);
11330 if (newOp3.isImm())
11331 newOp3.setImm(newOp3.getImm()+4);
11333 newOp3.setOffset(newOp3.getOffset()+4);
11334 (*MIB).addOperand(newOp3);
11335 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11337 // t3/4 are defined later, at the bottom of the loop
11338 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11339 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11340 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11341 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11342 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11343 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11345 // The subsequent operations should be using the destination registers of
11346 //the PHI instructions.
11348 t1 = F->getRegInfo().createVirtualRegister(RC);
11349 t2 = F->getRegInfo().createVirtualRegister(RC);
11350 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11351 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11353 t1 = dest1Oper.getReg();
11354 t2 = dest2Oper.getReg();
11357 int valArgIndx = lastAddrIndx + 1;
11358 assert((argOpers[valArgIndx]->isReg() ||
11359 argOpers[valArgIndx]->isImm()) &&
11360 "invalid operand");
11361 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11362 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11363 if (argOpers[valArgIndx]->isReg())
11364 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11366 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11367 if (regOpcL != X86::MOV32rr)
11369 (*MIB).addOperand(*argOpers[valArgIndx]);
11370 assert(argOpers[valArgIndx + 1]->isReg() ==
11371 argOpers[valArgIndx]->isReg());
11372 assert(argOpers[valArgIndx + 1]->isImm() ==
11373 argOpers[valArgIndx]->isImm());
11374 if (argOpers[valArgIndx + 1]->isReg())
11375 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11377 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11378 if (regOpcH != X86::MOV32rr)
11380 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11382 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11384 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11387 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11389 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11392 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11393 for (int i=0; i <= lastAddrIndx; ++i)
11394 (*MIB).addOperand(*argOpers[i]);
11396 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11397 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11398 bInstr->memoperands_end());
11400 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11401 MIB.addReg(X86::EAX);
11402 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11403 MIB.addReg(X86::EDX);
11406 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11408 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11412 // private utility function
11413 MachineBasicBlock *
11414 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11415 MachineBasicBlock *MBB,
11416 unsigned cmovOpc) const {
11417 // For the atomic min/max operator, we generate
11420 // ld t1 = [min/max.addr]
11421 // mov t2 = [min/max.val]
11423 // cmov[cond] t2 = t1
11425 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11427 // fallthrough -->nextMBB
11429 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11430 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11431 MachineFunction::iterator MBBIter = MBB;
11434 /// First build the CFG
11435 MachineFunction *F = MBB->getParent();
11436 MachineBasicBlock *thisMBB = MBB;
11437 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11438 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11439 F->insert(MBBIter, newMBB);
11440 F->insert(MBBIter, nextMBB);
11442 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11443 nextMBB->splice(nextMBB->begin(), thisMBB,
11444 llvm::next(MachineBasicBlock::iterator(mInstr)),
11446 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11448 // Update thisMBB to fall through to newMBB
11449 thisMBB->addSuccessor(newMBB);
11451 // newMBB jumps to newMBB and fall through to nextMBB
11452 newMBB->addSuccessor(nextMBB);
11453 newMBB->addSuccessor(newMBB);
11455 DebugLoc dl = mInstr->getDebugLoc();
11456 // Insert instructions into newMBB based on incoming instruction
11457 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11458 "unexpected number of operands");
11459 MachineOperand& destOper = mInstr->getOperand(0);
11460 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11461 int numArgs = mInstr->getNumOperands() - 1;
11462 for (int i=0; i < numArgs; ++i)
11463 argOpers[i] = &mInstr->getOperand(i+1);
11465 // x86 address has 4 operands: base, index, scale, and displacement
11466 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11467 int valArgIndx = lastAddrIndx + 1;
11469 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11470 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11471 for (int i=0; i <= lastAddrIndx; ++i)
11472 (*MIB).addOperand(*argOpers[i]);
11474 // We only support register and immediate values
11475 assert((argOpers[valArgIndx]->isReg() ||
11476 argOpers[valArgIndx]->isImm()) &&
11477 "invalid operand");
11479 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11480 if (argOpers[valArgIndx]->isReg())
11481 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11483 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11484 (*MIB).addOperand(*argOpers[valArgIndx]);
11486 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11489 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11494 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11495 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11499 // Cmp and exchange if none has modified the memory location
11500 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11501 for (int i=0; i <= lastAddrIndx; ++i)
11502 (*MIB).addOperand(*argOpers[i]);
11504 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11505 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11506 mInstr->memoperands_end());
11508 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11509 MIB.addReg(X86::EAX);
11512 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11514 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11518 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11519 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11520 // in the .td file.
11521 MachineBasicBlock *
11522 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11523 unsigned numArgs, bool memArg) const {
11524 assert(Subtarget->hasSSE42orAVX() &&
11525 "Target must have SSE4.2 or AVX features enabled");
11527 DebugLoc dl = MI->getDebugLoc();
11528 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11530 if (!Subtarget->hasAVX()) {
11532 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11534 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11537 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11539 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11542 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11543 for (unsigned i = 0; i < numArgs; ++i) {
11544 MachineOperand &Op = MI->getOperand(i+1);
11545 if (!(Op.isReg() && Op.isImplicit()))
11546 MIB.addOperand(Op);
11548 BuildMI(*BB, MI, dl,
11549 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11550 MI->getOperand(0).getReg())
11551 .addReg(X86::XMM0);
11553 MI->eraseFromParent();
11557 MachineBasicBlock *
11558 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11559 DebugLoc dl = MI->getDebugLoc();
11560 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11562 // Address into RAX/EAX, other two args into ECX, EDX.
11563 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11564 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11565 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11566 for (int i = 0; i < X86::AddrNumOperands; ++i)
11567 MIB.addOperand(MI->getOperand(i));
11569 unsigned ValOps = X86::AddrNumOperands;
11570 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11571 .addReg(MI->getOperand(ValOps).getReg());
11572 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11573 .addReg(MI->getOperand(ValOps+1).getReg());
11575 // The instruction doesn't actually take any operands though.
11576 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11578 MI->eraseFromParent(); // The pseudo is gone now.
11582 MachineBasicBlock *
11583 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11584 DebugLoc dl = MI->getDebugLoc();
11585 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11587 // First arg in ECX, the second in EAX.
11588 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11589 .addReg(MI->getOperand(0).getReg());
11590 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11591 .addReg(MI->getOperand(1).getReg());
11593 // The instruction doesn't actually take any operands though.
11594 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11596 MI->eraseFromParent(); // The pseudo is gone now.
11600 MachineBasicBlock *
11601 X86TargetLowering::EmitVAARG64WithCustomInserter(
11603 MachineBasicBlock *MBB) const {
11604 // Emit va_arg instruction on X86-64.
11606 // Operands to this pseudo-instruction:
11607 // 0 ) Output : destination address (reg)
11608 // 1-5) Input : va_list address (addr, i64mem)
11609 // 6 ) ArgSize : Size (in bytes) of vararg type
11610 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11611 // 8 ) Align : Alignment of type
11612 // 9 ) EFLAGS (implicit-def)
11614 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11615 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11617 unsigned DestReg = MI->getOperand(0).getReg();
11618 MachineOperand &Base = MI->getOperand(1);
11619 MachineOperand &Scale = MI->getOperand(2);
11620 MachineOperand &Index = MI->getOperand(3);
11621 MachineOperand &Disp = MI->getOperand(4);
11622 MachineOperand &Segment = MI->getOperand(5);
11623 unsigned ArgSize = MI->getOperand(6).getImm();
11624 unsigned ArgMode = MI->getOperand(7).getImm();
11625 unsigned Align = MI->getOperand(8).getImm();
11627 // Memory Reference
11628 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11629 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11630 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11632 // Machine Information
11633 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11634 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11635 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11636 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11637 DebugLoc DL = MI->getDebugLoc();
11639 // struct va_list {
11642 // i64 overflow_area (address)
11643 // i64 reg_save_area (address)
11645 // sizeof(va_list) = 24
11646 // alignment(va_list) = 8
11648 unsigned TotalNumIntRegs = 6;
11649 unsigned TotalNumXMMRegs = 8;
11650 bool UseGPOffset = (ArgMode == 1);
11651 bool UseFPOffset = (ArgMode == 2);
11652 unsigned MaxOffset = TotalNumIntRegs * 8 +
11653 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11655 /* Align ArgSize to a multiple of 8 */
11656 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11657 bool NeedsAlign = (Align > 8);
11659 MachineBasicBlock *thisMBB = MBB;
11660 MachineBasicBlock *overflowMBB;
11661 MachineBasicBlock *offsetMBB;
11662 MachineBasicBlock *endMBB;
11664 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11665 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11666 unsigned OffsetReg = 0;
11668 if (!UseGPOffset && !UseFPOffset) {
11669 // If we only pull from the overflow region, we don't create a branch.
11670 // We don't need to alter control flow.
11671 OffsetDestReg = 0; // unused
11672 OverflowDestReg = DestReg;
11675 overflowMBB = thisMBB;
11678 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11679 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11680 // If not, pull from overflow_area. (branch to overflowMBB)
11685 // offsetMBB overflowMBB
11690 // Registers for the PHI in endMBB
11691 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11692 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11694 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11695 MachineFunction *MF = MBB->getParent();
11696 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11697 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11698 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11700 MachineFunction::iterator MBBIter = MBB;
11703 // Insert the new basic blocks
11704 MF->insert(MBBIter, offsetMBB);
11705 MF->insert(MBBIter, overflowMBB);
11706 MF->insert(MBBIter, endMBB);
11708 // Transfer the remainder of MBB and its successor edges to endMBB.
11709 endMBB->splice(endMBB->begin(), thisMBB,
11710 llvm::next(MachineBasicBlock::iterator(MI)),
11712 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11714 // Make offsetMBB and overflowMBB successors of thisMBB
11715 thisMBB->addSuccessor(offsetMBB);
11716 thisMBB->addSuccessor(overflowMBB);
11718 // endMBB is a successor of both offsetMBB and overflowMBB
11719 offsetMBB->addSuccessor(endMBB);
11720 overflowMBB->addSuccessor(endMBB);
11722 // Load the offset value into a register
11723 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11724 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11728 .addDisp(Disp, UseFPOffset ? 4 : 0)
11729 .addOperand(Segment)
11730 .setMemRefs(MMOBegin, MMOEnd);
11732 // Check if there is enough room left to pull this argument.
11733 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11735 .addImm(MaxOffset + 8 - ArgSizeA8);
11737 // Branch to "overflowMBB" if offset >= max
11738 // Fall through to "offsetMBB" otherwise
11739 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11740 .addMBB(overflowMBB);
11743 // In offsetMBB, emit code to use the reg_save_area.
11745 assert(OffsetReg != 0);
11747 // Read the reg_save_area address.
11748 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11749 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11754 .addOperand(Segment)
11755 .setMemRefs(MMOBegin, MMOEnd);
11757 // Zero-extend the offset
11758 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11759 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11762 .addImm(X86::sub_32bit);
11764 // Add the offset to the reg_save_area to get the final address.
11765 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11766 .addReg(OffsetReg64)
11767 .addReg(RegSaveReg);
11769 // Compute the offset for the next argument
11770 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11771 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11773 .addImm(UseFPOffset ? 16 : 8);
11775 // Store it back into the va_list.
11776 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11780 .addDisp(Disp, UseFPOffset ? 4 : 0)
11781 .addOperand(Segment)
11782 .addReg(NextOffsetReg)
11783 .setMemRefs(MMOBegin, MMOEnd);
11786 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11791 // Emit code to use overflow area
11794 // Load the overflow_area address into a register.
11795 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11796 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11801 .addOperand(Segment)
11802 .setMemRefs(MMOBegin, MMOEnd);
11804 // If we need to align it, do so. Otherwise, just copy the address
11805 // to OverflowDestReg.
11807 // Align the overflow address
11808 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11809 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11811 // aligned_addr = (addr + (align-1)) & ~(align-1)
11812 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11813 .addReg(OverflowAddrReg)
11816 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11818 .addImm(~(uint64_t)(Align-1));
11820 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11821 .addReg(OverflowAddrReg);
11824 // Compute the next overflow address after this argument.
11825 // (the overflow address should be kept 8-byte aligned)
11826 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11827 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11828 .addReg(OverflowDestReg)
11829 .addImm(ArgSizeA8);
11831 // Store the new overflow address.
11832 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11837 .addOperand(Segment)
11838 .addReg(NextAddrReg)
11839 .setMemRefs(MMOBegin, MMOEnd);
11841 // If we branched, emit the PHI to the front of endMBB.
11843 BuildMI(*endMBB, endMBB->begin(), DL,
11844 TII->get(X86::PHI), DestReg)
11845 .addReg(OffsetDestReg).addMBB(offsetMBB)
11846 .addReg(OverflowDestReg).addMBB(overflowMBB);
11849 // Erase the pseudo instruction
11850 MI->eraseFromParent();
11855 MachineBasicBlock *
11856 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11858 MachineBasicBlock *MBB) const {
11859 // Emit code to save XMM registers to the stack. The ABI says that the
11860 // number of registers to save is given in %al, so it's theoretically
11861 // possible to do an indirect jump trick to avoid saving all of them,
11862 // however this code takes a simpler approach and just executes all
11863 // of the stores if %al is non-zero. It's less code, and it's probably
11864 // easier on the hardware branch predictor, and stores aren't all that
11865 // expensive anyway.
11867 // Create the new basic blocks. One block contains all the XMM stores,
11868 // and one block is the final destination regardless of whether any
11869 // stores were performed.
11870 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11871 MachineFunction *F = MBB->getParent();
11872 MachineFunction::iterator MBBIter = MBB;
11874 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11875 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11876 F->insert(MBBIter, XMMSaveMBB);
11877 F->insert(MBBIter, EndMBB);
11879 // Transfer the remainder of MBB and its successor edges to EndMBB.
11880 EndMBB->splice(EndMBB->begin(), MBB,
11881 llvm::next(MachineBasicBlock::iterator(MI)),
11883 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11885 // The original block will now fall through to the XMM save block.
11886 MBB->addSuccessor(XMMSaveMBB);
11887 // The XMMSaveMBB will fall through to the end block.
11888 XMMSaveMBB->addSuccessor(EndMBB);
11890 // Now add the instructions.
11891 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11892 DebugLoc DL = MI->getDebugLoc();
11894 unsigned CountReg = MI->getOperand(0).getReg();
11895 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11896 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11898 if (!Subtarget->isTargetWin64()) {
11899 // If %al is 0, branch around the XMM save block.
11900 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11901 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11902 MBB->addSuccessor(EndMBB);
11905 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11906 // In the XMM save block, save all the XMM argument registers.
11907 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11908 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11909 MachineMemOperand *MMO =
11910 F->getMachineMemOperand(
11911 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11912 MachineMemOperand::MOStore,
11913 /*Size=*/16, /*Align=*/16);
11914 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11915 .addFrameIndex(RegSaveFrameIndex)
11916 .addImm(/*Scale=*/1)
11917 .addReg(/*IndexReg=*/0)
11918 .addImm(/*Disp=*/Offset)
11919 .addReg(/*Segment=*/0)
11920 .addReg(MI->getOperand(i).getReg())
11921 .addMemOperand(MMO);
11924 MI->eraseFromParent(); // The pseudo instruction is gone now.
11929 MachineBasicBlock *
11930 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11931 MachineBasicBlock *BB) const {
11932 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11933 DebugLoc DL = MI->getDebugLoc();
11935 // To "insert" a SELECT_CC instruction, we actually have to insert the
11936 // diamond control-flow pattern. The incoming instruction knows the
11937 // destination vreg to set, the condition code register to branch on, the
11938 // true/false values to select between, and a branch opcode to use.
11939 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11940 MachineFunction::iterator It = BB;
11946 // cmpTY ccX, r1, r2
11948 // fallthrough --> copy0MBB
11949 MachineBasicBlock *thisMBB = BB;
11950 MachineFunction *F = BB->getParent();
11951 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11952 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11953 F->insert(It, copy0MBB);
11954 F->insert(It, sinkMBB);
11956 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11957 // live into the sink and copy blocks.
11958 if (!MI->killsRegister(X86::EFLAGS)) {
11959 copy0MBB->addLiveIn(X86::EFLAGS);
11960 sinkMBB->addLiveIn(X86::EFLAGS);
11963 // Transfer the remainder of BB and its successor edges to sinkMBB.
11964 sinkMBB->splice(sinkMBB->begin(), BB,
11965 llvm::next(MachineBasicBlock::iterator(MI)),
11967 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11969 // Add the true and fallthrough blocks as its successors.
11970 BB->addSuccessor(copy0MBB);
11971 BB->addSuccessor(sinkMBB);
11973 // Create the conditional branch instruction.
11975 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11976 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11979 // %FalseValue = ...
11980 // # fallthrough to sinkMBB
11981 copy0MBB->addSuccessor(sinkMBB);
11984 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11986 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11987 TII->get(X86::PHI), MI->getOperand(0).getReg())
11988 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11989 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11991 MI->eraseFromParent(); // The pseudo instruction is gone now.
11995 MachineBasicBlock *
11996 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
11997 bool Is64Bit) const {
11998 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11999 DebugLoc DL = MI->getDebugLoc();
12000 MachineFunction *MF = BB->getParent();
12001 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12003 assert(getTargetMachine().Options.EnableSegmentedStacks);
12005 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12006 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12009 // ... [Till the alloca]
12010 // If stacklet is not large enough, jump to mallocMBB
12013 // Allocate by subtracting from RSP
12014 // Jump to continueMBB
12017 // Allocate by call to runtime
12021 // [rest of original BB]
12024 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12025 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12026 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12028 MachineRegisterInfo &MRI = MF->getRegInfo();
12029 const TargetRegisterClass *AddrRegClass =
12030 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12032 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12033 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12034 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12035 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12036 sizeVReg = MI->getOperand(1).getReg(),
12037 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12039 MachineFunction::iterator MBBIter = BB;
12042 MF->insert(MBBIter, bumpMBB);
12043 MF->insert(MBBIter, mallocMBB);
12044 MF->insert(MBBIter, continueMBB);
12046 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12047 (MachineBasicBlock::iterator(MI)), BB->end());
12048 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12050 // Add code to the main basic block to check if the stack limit has been hit,
12051 // and if so, jump to mallocMBB otherwise to bumpMBB.
12052 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12053 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12054 .addReg(tmpSPVReg).addReg(sizeVReg);
12055 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12056 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12057 .addReg(SPLimitVReg);
12058 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12060 // bumpMBB simply decreases the stack pointer, since we know the current
12061 // stacklet has enough space.
12062 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12063 .addReg(SPLimitVReg);
12064 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12065 .addReg(SPLimitVReg);
12066 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12068 // Calls into a routine in libgcc to allocate more space from the heap.
12070 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12072 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12073 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
12075 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12077 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12078 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12079 .addExternalSymbol("__morestack_allocate_stack_space");
12083 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12086 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12087 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12088 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12090 // Set up the CFG correctly.
12091 BB->addSuccessor(bumpMBB);
12092 BB->addSuccessor(mallocMBB);
12093 mallocMBB->addSuccessor(continueMBB);
12094 bumpMBB->addSuccessor(continueMBB);
12096 // Take care of the PHI nodes.
12097 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12098 MI->getOperand(0).getReg())
12099 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12100 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12102 // Delete the original pseudo instruction.
12103 MI->eraseFromParent();
12106 return continueMBB;
12109 MachineBasicBlock *
12110 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12111 MachineBasicBlock *BB) const {
12112 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12113 DebugLoc DL = MI->getDebugLoc();
12115 assert(!Subtarget->isTargetEnvMacho());
12117 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12118 // non-trivial part is impdef of ESP.
12120 if (Subtarget->isTargetWin64()) {
12121 if (Subtarget->isTargetCygMing()) {
12122 // ___chkstk(Mingw64):
12123 // Clobbers R10, R11, RAX and EFLAGS.
12125 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12126 .addExternalSymbol("___chkstk")
12127 .addReg(X86::RAX, RegState::Implicit)
12128 .addReg(X86::RSP, RegState::Implicit)
12129 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12130 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12131 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12133 // __chkstk(MSVCRT): does not update stack pointer.
12134 // Clobbers R10, R11 and EFLAGS.
12135 // FIXME: RAX(allocated size) might be reused and not killed.
12136 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12137 .addExternalSymbol("__chkstk")
12138 .addReg(X86::RAX, RegState::Implicit)
12139 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12140 // RAX has the offset to subtracted from RSP.
12141 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12146 const char *StackProbeSymbol =
12147 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12149 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12150 .addExternalSymbol(StackProbeSymbol)
12151 .addReg(X86::EAX, RegState::Implicit)
12152 .addReg(X86::ESP, RegState::Implicit)
12153 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12154 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12155 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12158 MI->eraseFromParent(); // The pseudo instruction is gone now.
12162 MachineBasicBlock *
12163 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12164 MachineBasicBlock *BB) const {
12165 // This is pretty easy. We're taking the value that we received from
12166 // our load from the relocation, sticking it in either RDI (x86-64)
12167 // or EAX and doing an indirect call. The return value will then
12168 // be in the normal return register.
12169 const X86InstrInfo *TII
12170 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12171 DebugLoc DL = MI->getDebugLoc();
12172 MachineFunction *F = BB->getParent();
12174 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12175 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12177 if (Subtarget->is64Bit()) {
12178 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12179 TII->get(X86::MOV64rm), X86::RDI)
12181 .addImm(0).addReg(0)
12182 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12183 MI->getOperand(3).getTargetFlags())
12185 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12186 addDirectMem(MIB, X86::RDI);
12187 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12188 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12189 TII->get(X86::MOV32rm), X86::EAX)
12191 .addImm(0).addReg(0)
12192 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12193 MI->getOperand(3).getTargetFlags())
12195 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12196 addDirectMem(MIB, X86::EAX);
12198 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12199 TII->get(X86::MOV32rm), X86::EAX)
12200 .addReg(TII->getGlobalBaseReg(F))
12201 .addImm(0).addReg(0)
12202 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12203 MI->getOperand(3).getTargetFlags())
12205 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12206 addDirectMem(MIB, X86::EAX);
12209 MI->eraseFromParent(); // The pseudo instruction is gone now.
12213 MachineBasicBlock *
12214 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12215 MachineBasicBlock *BB) const {
12216 switch (MI->getOpcode()) {
12217 default: assert(0 && "Unexpected instr type to insert");
12218 case X86::TAILJMPd64:
12219 case X86::TAILJMPr64:
12220 case X86::TAILJMPm64:
12221 assert(0 && "TAILJMP64 would not be touched here.");
12222 case X86::TCRETURNdi64:
12223 case X86::TCRETURNri64:
12224 case X86::TCRETURNmi64:
12225 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
12226 // On AMD64, additional defs should be added before register allocation.
12227 if (!Subtarget->isTargetWin64()) {
12228 MI->addRegisterDefined(X86::RSI);
12229 MI->addRegisterDefined(X86::RDI);
12230 MI->addRegisterDefined(X86::XMM6);
12231 MI->addRegisterDefined(X86::XMM7);
12232 MI->addRegisterDefined(X86::XMM8);
12233 MI->addRegisterDefined(X86::XMM9);
12234 MI->addRegisterDefined(X86::XMM10);
12235 MI->addRegisterDefined(X86::XMM11);
12236 MI->addRegisterDefined(X86::XMM12);
12237 MI->addRegisterDefined(X86::XMM13);
12238 MI->addRegisterDefined(X86::XMM14);
12239 MI->addRegisterDefined(X86::XMM15);
12242 case X86::WIN_ALLOCA:
12243 return EmitLoweredWinAlloca(MI, BB);
12244 case X86::SEG_ALLOCA_32:
12245 return EmitLoweredSegAlloca(MI, BB, false);
12246 case X86::SEG_ALLOCA_64:
12247 return EmitLoweredSegAlloca(MI, BB, true);
12248 case X86::TLSCall_32:
12249 case X86::TLSCall_64:
12250 return EmitLoweredTLSCall(MI, BB);
12251 case X86::CMOV_GR8:
12252 case X86::CMOV_FR32:
12253 case X86::CMOV_FR64:
12254 case X86::CMOV_V4F32:
12255 case X86::CMOV_V2F64:
12256 case X86::CMOV_V2I64:
12257 case X86::CMOV_V8F32:
12258 case X86::CMOV_V4F64:
12259 case X86::CMOV_V4I64:
12260 case X86::CMOV_GR16:
12261 case X86::CMOV_GR32:
12262 case X86::CMOV_RFP32:
12263 case X86::CMOV_RFP64:
12264 case X86::CMOV_RFP80:
12265 return EmitLoweredSelect(MI, BB);
12267 case X86::FP32_TO_INT16_IN_MEM:
12268 case X86::FP32_TO_INT32_IN_MEM:
12269 case X86::FP32_TO_INT64_IN_MEM:
12270 case X86::FP64_TO_INT16_IN_MEM:
12271 case X86::FP64_TO_INT32_IN_MEM:
12272 case X86::FP64_TO_INT64_IN_MEM:
12273 case X86::FP80_TO_INT16_IN_MEM:
12274 case X86::FP80_TO_INT32_IN_MEM:
12275 case X86::FP80_TO_INT64_IN_MEM: {
12276 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12277 DebugLoc DL = MI->getDebugLoc();
12279 // Change the floating point control register to use "round towards zero"
12280 // mode when truncating to an integer value.
12281 MachineFunction *F = BB->getParent();
12282 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12283 addFrameReference(BuildMI(*BB, MI, DL,
12284 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12286 // Load the old value of the high byte of the control word...
12288 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12289 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12292 // Set the high part to be round to zero...
12293 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12296 // Reload the modified control word now...
12297 addFrameReference(BuildMI(*BB, MI, DL,
12298 TII->get(X86::FLDCW16m)), CWFrameIdx);
12300 // Restore the memory image of control word to original value
12301 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12304 // Get the X86 opcode to use.
12306 switch (MI->getOpcode()) {
12307 default: llvm_unreachable("illegal opcode!");
12308 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12309 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12310 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12311 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12312 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12313 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12314 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12315 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12316 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12320 MachineOperand &Op = MI->getOperand(0);
12322 AM.BaseType = X86AddressMode::RegBase;
12323 AM.Base.Reg = Op.getReg();
12325 AM.BaseType = X86AddressMode::FrameIndexBase;
12326 AM.Base.FrameIndex = Op.getIndex();
12328 Op = MI->getOperand(1);
12330 AM.Scale = Op.getImm();
12331 Op = MI->getOperand(2);
12333 AM.IndexReg = Op.getImm();
12334 Op = MI->getOperand(3);
12335 if (Op.isGlobal()) {
12336 AM.GV = Op.getGlobal();
12338 AM.Disp = Op.getImm();
12340 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12341 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12343 // Reload the original control word now.
12344 addFrameReference(BuildMI(*BB, MI, DL,
12345 TII->get(X86::FLDCW16m)), CWFrameIdx);
12347 MI->eraseFromParent(); // The pseudo instruction is gone now.
12350 // String/text processing lowering.
12351 case X86::PCMPISTRM128REG:
12352 case X86::VPCMPISTRM128REG:
12353 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12354 case X86::PCMPISTRM128MEM:
12355 case X86::VPCMPISTRM128MEM:
12356 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12357 case X86::PCMPESTRM128REG:
12358 case X86::VPCMPESTRM128REG:
12359 return EmitPCMP(MI, BB, 5, false /* in mem */);
12360 case X86::PCMPESTRM128MEM:
12361 case X86::VPCMPESTRM128MEM:
12362 return EmitPCMP(MI, BB, 5, true /* in mem */);
12364 // Thread synchronization.
12366 return EmitMonitor(MI, BB);
12368 return EmitMwait(MI, BB);
12370 // Atomic Lowering.
12371 case X86::ATOMAND32:
12372 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12373 X86::AND32ri, X86::MOV32rm,
12375 X86::NOT32r, X86::EAX,
12376 X86::GR32RegisterClass);
12377 case X86::ATOMOR32:
12378 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12379 X86::OR32ri, X86::MOV32rm,
12381 X86::NOT32r, X86::EAX,
12382 X86::GR32RegisterClass);
12383 case X86::ATOMXOR32:
12384 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12385 X86::XOR32ri, X86::MOV32rm,
12387 X86::NOT32r, X86::EAX,
12388 X86::GR32RegisterClass);
12389 case X86::ATOMNAND32:
12390 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12391 X86::AND32ri, X86::MOV32rm,
12393 X86::NOT32r, X86::EAX,
12394 X86::GR32RegisterClass, true);
12395 case X86::ATOMMIN32:
12396 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12397 case X86::ATOMMAX32:
12398 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12399 case X86::ATOMUMIN32:
12400 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12401 case X86::ATOMUMAX32:
12402 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12404 case X86::ATOMAND16:
12405 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12406 X86::AND16ri, X86::MOV16rm,
12408 X86::NOT16r, X86::AX,
12409 X86::GR16RegisterClass);
12410 case X86::ATOMOR16:
12411 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12412 X86::OR16ri, X86::MOV16rm,
12414 X86::NOT16r, X86::AX,
12415 X86::GR16RegisterClass);
12416 case X86::ATOMXOR16:
12417 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12418 X86::XOR16ri, X86::MOV16rm,
12420 X86::NOT16r, X86::AX,
12421 X86::GR16RegisterClass);
12422 case X86::ATOMNAND16:
12423 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12424 X86::AND16ri, X86::MOV16rm,
12426 X86::NOT16r, X86::AX,
12427 X86::GR16RegisterClass, true);
12428 case X86::ATOMMIN16:
12429 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12430 case X86::ATOMMAX16:
12431 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12432 case X86::ATOMUMIN16:
12433 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12434 case X86::ATOMUMAX16:
12435 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12437 case X86::ATOMAND8:
12438 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12439 X86::AND8ri, X86::MOV8rm,
12441 X86::NOT8r, X86::AL,
12442 X86::GR8RegisterClass);
12444 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12445 X86::OR8ri, X86::MOV8rm,
12447 X86::NOT8r, X86::AL,
12448 X86::GR8RegisterClass);
12449 case X86::ATOMXOR8:
12450 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12451 X86::XOR8ri, X86::MOV8rm,
12453 X86::NOT8r, X86::AL,
12454 X86::GR8RegisterClass);
12455 case X86::ATOMNAND8:
12456 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12457 X86::AND8ri, X86::MOV8rm,
12459 X86::NOT8r, X86::AL,
12460 X86::GR8RegisterClass, true);
12461 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12462 // This group is for 64-bit host.
12463 case X86::ATOMAND64:
12464 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12465 X86::AND64ri32, X86::MOV64rm,
12467 X86::NOT64r, X86::RAX,
12468 X86::GR64RegisterClass);
12469 case X86::ATOMOR64:
12470 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12471 X86::OR64ri32, X86::MOV64rm,
12473 X86::NOT64r, X86::RAX,
12474 X86::GR64RegisterClass);
12475 case X86::ATOMXOR64:
12476 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12477 X86::XOR64ri32, X86::MOV64rm,
12479 X86::NOT64r, X86::RAX,
12480 X86::GR64RegisterClass);
12481 case X86::ATOMNAND64:
12482 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12483 X86::AND64ri32, X86::MOV64rm,
12485 X86::NOT64r, X86::RAX,
12486 X86::GR64RegisterClass, true);
12487 case X86::ATOMMIN64:
12488 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12489 case X86::ATOMMAX64:
12490 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12491 case X86::ATOMUMIN64:
12492 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12493 case X86::ATOMUMAX64:
12494 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12496 // This group does 64-bit operations on a 32-bit host.
12497 case X86::ATOMAND6432:
12498 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12499 X86::AND32rr, X86::AND32rr,
12500 X86::AND32ri, X86::AND32ri,
12502 case X86::ATOMOR6432:
12503 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12504 X86::OR32rr, X86::OR32rr,
12505 X86::OR32ri, X86::OR32ri,
12507 case X86::ATOMXOR6432:
12508 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12509 X86::XOR32rr, X86::XOR32rr,
12510 X86::XOR32ri, X86::XOR32ri,
12512 case X86::ATOMNAND6432:
12513 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12514 X86::AND32rr, X86::AND32rr,
12515 X86::AND32ri, X86::AND32ri,
12517 case X86::ATOMADD6432:
12518 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12519 X86::ADD32rr, X86::ADC32rr,
12520 X86::ADD32ri, X86::ADC32ri,
12522 case X86::ATOMSUB6432:
12523 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12524 X86::SUB32rr, X86::SBB32rr,
12525 X86::SUB32ri, X86::SBB32ri,
12527 case X86::ATOMSWAP6432:
12528 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12529 X86::MOV32rr, X86::MOV32rr,
12530 X86::MOV32ri, X86::MOV32ri,
12532 case X86::VASTART_SAVE_XMM_REGS:
12533 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12535 case X86::VAARG_64:
12536 return EmitVAARG64WithCustomInserter(MI, BB);
12540 //===----------------------------------------------------------------------===//
12541 // X86 Optimization Hooks
12542 //===----------------------------------------------------------------------===//
12544 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12548 const SelectionDAG &DAG,
12549 unsigned Depth) const {
12550 unsigned Opc = Op.getOpcode();
12551 assert((Opc >= ISD::BUILTIN_OP_END ||
12552 Opc == ISD::INTRINSIC_WO_CHAIN ||
12553 Opc == ISD::INTRINSIC_W_CHAIN ||
12554 Opc == ISD::INTRINSIC_VOID) &&
12555 "Should use MaskedValueIsZero if you don't know whether Op"
12556 " is a target node!");
12558 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12572 // These nodes' second result is a boolean.
12573 if (Op.getResNo() == 0)
12576 case X86ISD::SETCC:
12577 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12578 Mask.getBitWidth() - 1);
12580 case ISD::INTRINSIC_WO_CHAIN: {
12581 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12582 unsigned NumLoBits = 0;
12585 case Intrinsic::x86_sse_movmsk_ps:
12586 case Intrinsic::x86_avx_movmsk_ps_256:
12587 case Intrinsic::x86_sse2_movmsk_pd:
12588 case Intrinsic::x86_avx_movmsk_pd_256:
12589 case Intrinsic::x86_mmx_pmovmskb:
12590 case Intrinsic::x86_sse2_pmovmskb_128: {
12591 // High bits of movmskp{s|d}, pmovmskb are known zero.
12593 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12594 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12595 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12596 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12597 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12598 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12600 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12601 Mask.getBitWidth() - NumLoBits);
12610 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12611 unsigned Depth) const {
12612 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12613 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12614 return Op.getValueType().getScalarType().getSizeInBits();
12620 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12621 /// node is a GlobalAddress + offset.
12622 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12623 const GlobalValue* &GA,
12624 int64_t &Offset) const {
12625 if (N->getOpcode() == X86ISD::Wrapper) {
12626 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12627 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12628 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12632 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12635 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12636 /// same as extracting the high 128-bit part of 256-bit vector and then
12637 /// inserting the result into the low part of a new 256-bit vector
12638 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12639 EVT VT = SVOp->getValueType(0);
12640 int NumElems = VT.getVectorNumElements();
12642 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12643 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12644 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12645 SVOp->getMaskElt(j) >= 0)
12651 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12652 /// same as extracting the low 128-bit part of 256-bit vector and then
12653 /// inserting the result into the high part of a new 256-bit vector
12654 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12655 EVT VT = SVOp->getValueType(0);
12656 int NumElems = VT.getVectorNumElements();
12658 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12659 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12660 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12661 SVOp->getMaskElt(j) >= 0)
12667 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12668 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12669 TargetLowering::DAGCombinerInfo &DCI) {
12670 DebugLoc dl = N->getDebugLoc();
12671 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12672 SDValue V1 = SVOp->getOperand(0);
12673 SDValue V2 = SVOp->getOperand(1);
12674 EVT VT = SVOp->getValueType(0);
12675 int NumElems = VT.getVectorNumElements();
12677 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12678 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12682 // V UNDEF BUILD_VECTOR UNDEF
12684 // CONCAT_VECTOR CONCAT_VECTOR
12687 // RESULT: V + zero extended
12689 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12690 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12691 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12694 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12697 // To match the shuffle mask, the first half of the mask should
12698 // be exactly the first vector, and all the rest a splat with the
12699 // first element of the second one.
12700 for (int i = 0; i < NumElems/2; ++i)
12701 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12702 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12705 // Emit a zeroed vector and insert the desired subvector on its
12707 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl);
12708 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12709 DAG.getConstant(0, MVT::i32), DAG, dl);
12710 return DCI.CombineTo(N, InsV);
12713 //===--------------------------------------------------------------------===//
12714 // Combine some shuffles into subvector extracts and inserts:
12717 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12718 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12719 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12721 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12722 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12723 return DCI.CombineTo(N, InsV);
12726 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12727 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12728 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12729 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12730 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12731 return DCI.CombineTo(N, InsV);
12737 /// PerformShuffleCombine - Performs several different shuffle combines.
12738 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12739 TargetLowering::DAGCombinerInfo &DCI,
12740 const X86Subtarget *Subtarget) {
12741 DebugLoc dl = N->getDebugLoc();
12742 EVT VT = N->getValueType(0);
12744 // Don't create instructions with illegal types after legalize types has run.
12745 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12746 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12749 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12750 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12751 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12752 return PerformShuffleCombine256(N, DAG, DCI);
12754 // Only handle 128 wide vector from here on.
12755 if (VT.getSizeInBits() != 128)
12758 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12759 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12760 // consecutive, non-overlapping, and in the right order.
12761 SmallVector<SDValue, 16> Elts;
12762 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12763 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12765 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12768 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12769 /// generation and convert it from being a bunch of shuffles and extracts
12770 /// to a simple store and scalar loads to extract the elements.
12771 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12772 const TargetLowering &TLI) {
12773 SDValue InputVector = N->getOperand(0);
12775 // Only operate on vectors of 4 elements, where the alternative shuffling
12776 // gets to be more expensive.
12777 if (InputVector.getValueType() != MVT::v4i32)
12780 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12781 // single use which is a sign-extend or zero-extend, and all elements are
12783 SmallVector<SDNode *, 4> Uses;
12784 unsigned ExtractedElements = 0;
12785 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12786 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12787 if (UI.getUse().getResNo() != InputVector.getResNo())
12790 SDNode *Extract = *UI;
12791 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12794 if (Extract->getValueType(0) != MVT::i32)
12796 if (!Extract->hasOneUse())
12798 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12799 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12801 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12804 // Record which element was extracted.
12805 ExtractedElements |=
12806 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12808 Uses.push_back(Extract);
12811 // If not all the elements were used, this may not be worthwhile.
12812 if (ExtractedElements != 15)
12815 // Ok, we've now decided to do the transformation.
12816 DebugLoc dl = InputVector.getDebugLoc();
12818 // Store the value to a temporary stack slot.
12819 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12820 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12821 MachinePointerInfo(), false, false, 0);
12823 // Replace each use (extract) with a load of the appropriate element.
12824 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12825 UE = Uses.end(); UI != UE; ++UI) {
12826 SDNode *Extract = *UI;
12828 // cOMpute the element's address.
12829 SDValue Idx = Extract->getOperand(1);
12831 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12832 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12833 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12835 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12836 StackPtr, OffsetVal);
12838 // Load the scalar.
12839 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12840 ScalarAddr, MachinePointerInfo(),
12841 false, false, false, 0);
12843 // Replace the exact with the load.
12844 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12847 // The replacement was made in place; don't return anything.
12851 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
12853 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12854 const X86Subtarget *Subtarget) {
12855 DebugLoc DL = N->getDebugLoc();
12856 SDValue Cond = N->getOperand(0);
12857 // Get the LHS/RHS of the select.
12858 SDValue LHS = N->getOperand(1);
12859 SDValue RHS = N->getOperand(2);
12860 EVT VT = LHS.getValueType();
12862 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12863 // instructions match the semantics of the common C idiom x<y?x:y but not
12864 // x<=y?x:y, because of how they handle negative zero (which can be
12865 // ignored in unsafe-math mode).
12866 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
12867 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
12868 (Subtarget->hasXMMInt() ||
12869 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
12870 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12872 unsigned Opcode = 0;
12873 // Check for x CC y ? x : y.
12874 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12875 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12879 // Converting this to a min would handle NaNs incorrectly, and swapping
12880 // the operands would cause it to handle comparisons between positive
12881 // and negative zero incorrectly.
12882 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12883 if (!DAG.getTarget().Options.UnsafeFPMath &&
12884 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12886 std::swap(LHS, RHS);
12888 Opcode = X86ISD::FMIN;
12891 // Converting this to a min would handle comparisons between positive
12892 // and negative zero incorrectly.
12893 if (!DAG.getTarget().Options.UnsafeFPMath &&
12894 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12896 Opcode = X86ISD::FMIN;
12899 // Converting this to a min would handle both negative zeros and NaNs
12900 // incorrectly, but we can swap the operands to fix both.
12901 std::swap(LHS, RHS);
12905 Opcode = X86ISD::FMIN;
12909 // Converting this to a max would handle comparisons between positive
12910 // and negative zero incorrectly.
12911 if (!DAG.getTarget().Options.UnsafeFPMath &&
12912 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12914 Opcode = X86ISD::FMAX;
12917 // Converting this to a max would handle NaNs incorrectly, and swapping
12918 // the operands would cause it to handle comparisons between positive
12919 // and negative zero incorrectly.
12920 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12921 if (!DAG.getTarget().Options.UnsafeFPMath &&
12922 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12924 std::swap(LHS, RHS);
12926 Opcode = X86ISD::FMAX;
12929 // Converting this to a max would handle both negative zeros and NaNs
12930 // incorrectly, but we can swap the operands to fix both.
12931 std::swap(LHS, RHS);
12935 Opcode = X86ISD::FMAX;
12938 // Check for x CC y ? y : x -- a min/max with reversed arms.
12939 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12940 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12944 // Converting this to a min would handle comparisons between positive
12945 // and negative zero incorrectly, and swapping the operands would
12946 // cause it to handle NaNs incorrectly.
12947 if (!DAG.getTarget().Options.UnsafeFPMath &&
12948 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12949 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12951 std::swap(LHS, RHS);
12953 Opcode = X86ISD::FMIN;
12956 // Converting this to a min would handle NaNs incorrectly.
12957 if (!DAG.getTarget().Options.UnsafeFPMath &&
12958 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12960 Opcode = X86ISD::FMIN;
12963 // Converting this to a min would handle both negative zeros and NaNs
12964 // incorrectly, but we can swap the operands to fix both.
12965 std::swap(LHS, RHS);
12969 Opcode = X86ISD::FMIN;
12973 // Converting this to a max would handle NaNs incorrectly.
12974 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12976 Opcode = X86ISD::FMAX;
12979 // Converting this to a max would handle comparisons between positive
12980 // and negative zero incorrectly, and swapping the operands would
12981 // cause it to handle NaNs incorrectly.
12982 if (!DAG.getTarget().Options.UnsafeFPMath &&
12983 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12984 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12986 std::swap(LHS, RHS);
12988 Opcode = X86ISD::FMAX;
12991 // Converting this to a max would handle both negative zeros and NaNs
12992 // incorrectly, but we can swap the operands to fix both.
12993 std::swap(LHS, RHS);
12997 Opcode = X86ISD::FMAX;
13003 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13006 // If this is a select between two integer constants, try to do some
13008 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13009 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13010 // Don't do this for crazy integer types.
13011 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13012 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13013 // so that TrueC (the true value) is larger than FalseC.
13014 bool NeedsCondInvert = false;
13016 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13017 // Efficiently invertible.
13018 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13019 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13020 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13021 NeedsCondInvert = true;
13022 std::swap(TrueC, FalseC);
13025 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13026 if (FalseC->getAPIntValue() == 0 &&
13027 TrueC->getAPIntValue().isPowerOf2()) {
13028 if (NeedsCondInvert) // Invert the condition if needed.
13029 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13030 DAG.getConstant(1, Cond.getValueType()));
13032 // Zero extend the condition if needed.
13033 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13035 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13036 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13037 DAG.getConstant(ShAmt, MVT::i8));
13040 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13041 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13042 if (NeedsCondInvert) // Invert the condition if needed.
13043 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13044 DAG.getConstant(1, Cond.getValueType()));
13046 // Zero extend the condition if needed.
13047 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13048 FalseC->getValueType(0), Cond);
13049 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13050 SDValue(FalseC, 0));
13053 // Optimize cases that will turn into an LEA instruction. This requires
13054 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13055 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13056 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13057 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13059 bool isFastMultiplier = false;
13061 switch ((unsigned char)Diff) {
13063 case 1: // result = add base, cond
13064 case 2: // result = lea base( , cond*2)
13065 case 3: // result = lea base(cond, cond*2)
13066 case 4: // result = lea base( , cond*4)
13067 case 5: // result = lea base(cond, cond*4)
13068 case 8: // result = lea base( , cond*8)
13069 case 9: // result = lea base(cond, cond*8)
13070 isFastMultiplier = true;
13075 if (isFastMultiplier) {
13076 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13077 if (NeedsCondInvert) // Invert the condition if needed.
13078 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13079 DAG.getConstant(1, Cond.getValueType()));
13081 // Zero extend the condition if needed.
13082 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13084 // Scale the condition by the difference.
13086 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13087 DAG.getConstant(Diff, Cond.getValueType()));
13089 // Add the base if non-zero.
13090 if (FalseC->getAPIntValue() != 0)
13091 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13092 SDValue(FalseC, 0));
13102 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13103 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13104 TargetLowering::DAGCombinerInfo &DCI) {
13105 DebugLoc DL = N->getDebugLoc();
13107 // If the flag operand isn't dead, don't touch this CMOV.
13108 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13111 SDValue FalseOp = N->getOperand(0);
13112 SDValue TrueOp = N->getOperand(1);
13113 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13114 SDValue Cond = N->getOperand(3);
13115 if (CC == X86::COND_E || CC == X86::COND_NE) {
13116 switch (Cond.getOpcode()) {
13120 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13121 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13122 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13126 // If this is a select between two integer constants, try to do some
13127 // optimizations. Note that the operands are ordered the opposite of SELECT
13129 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13130 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13131 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13132 // larger than FalseC (the false value).
13133 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13134 CC = X86::GetOppositeBranchCondition(CC);
13135 std::swap(TrueC, FalseC);
13138 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13139 // This is efficient for any integer data type (including i8/i16) and
13141 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13142 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13143 DAG.getConstant(CC, MVT::i8), Cond);
13145 // Zero extend the condition if needed.
13146 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13148 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13149 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13150 DAG.getConstant(ShAmt, MVT::i8));
13151 if (N->getNumValues() == 2) // Dead flag value?
13152 return DCI.CombineTo(N, Cond, SDValue());
13156 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13157 // for any integer data type, including i8/i16.
13158 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13159 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13160 DAG.getConstant(CC, MVT::i8), Cond);
13162 // Zero extend the condition if needed.
13163 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13164 FalseC->getValueType(0), Cond);
13165 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13166 SDValue(FalseC, 0));
13168 if (N->getNumValues() == 2) // Dead flag value?
13169 return DCI.CombineTo(N, Cond, SDValue());
13173 // Optimize cases that will turn into an LEA instruction. This requires
13174 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13175 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13176 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13177 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13179 bool isFastMultiplier = false;
13181 switch ((unsigned char)Diff) {
13183 case 1: // result = add base, cond
13184 case 2: // result = lea base( , cond*2)
13185 case 3: // result = lea base(cond, cond*2)
13186 case 4: // result = lea base( , cond*4)
13187 case 5: // result = lea base(cond, cond*4)
13188 case 8: // result = lea base( , cond*8)
13189 case 9: // result = lea base(cond, cond*8)
13190 isFastMultiplier = true;
13195 if (isFastMultiplier) {
13196 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13197 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13198 DAG.getConstant(CC, MVT::i8), Cond);
13199 // Zero extend the condition if needed.
13200 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13202 // Scale the condition by the difference.
13204 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13205 DAG.getConstant(Diff, Cond.getValueType()));
13207 // Add the base if non-zero.
13208 if (FalseC->getAPIntValue() != 0)
13209 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13210 SDValue(FalseC, 0));
13211 if (N->getNumValues() == 2) // Dead flag value?
13212 return DCI.CombineTo(N, Cond, SDValue());
13222 /// PerformMulCombine - Optimize a single multiply with constant into two
13223 /// in order to implement it with two cheaper instructions, e.g.
13224 /// LEA + SHL, LEA + LEA.
13225 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13226 TargetLowering::DAGCombinerInfo &DCI) {
13227 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13230 EVT VT = N->getValueType(0);
13231 if (VT != MVT::i64)
13234 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13237 uint64_t MulAmt = C->getZExtValue();
13238 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13241 uint64_t MulAmt1 = 0;
13242 uint64_t MulAmt2 = 0;
13243 if ((MulAmt % 9) == 0) {
13245 MulAmt2 = MulAmt / 9;
13246 } else if ((MulAmt % 5) == 0) {
13248 MulAmt2 = MulAmt / 5;
13249 } else if ((MulAmt % 3) == 0) {
13251 MulAmt2 = MulAmt / 3;
13254 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13255 DebugLoc DL = N->getDebugLoc();
13257 if (isPowerOf2_64(MulAmt2) &&
13258 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13259 // If second multiplifer is pow2, issue it first. We want the multiply by
13260 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13262 std::swap(MulAmt1, MulAmt2);
13265 if (isPowerOf2_64(MulAmt1))
13266 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13267 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13269 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13270 DAG.getConstant(MulAmt1, VT));
13272 if (isPowerOf2_64(MulAmt2))
13273 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13274 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13276 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13277 DAG.getConstant(MulAmt2, VT));
13279 // Do not add new nodes to DAG combiner worklist.
13280 DCI.CombineTo(N, NewMul, false);
13285 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13286 SDValue N0 = N->getOperand(0);
13287 SDValue N1 = N->getOperand(1);
13288 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13289 EVT VT = N0.getValueType();
13291 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13292 // since the result of setcc_c is all zero's or all ones.
13293 if (VT.isInteger() && !VT.isVector() &&
13294 N1C && N0.getOpcode() == ISD::AND &&
13295 N0.getOperand(1).getOpcode() == ISD::Constant) {
13296 SDValue N00 = N0.getOperand(0);
13297 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13298 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13299 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13300 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13301 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13302 APInt ShAmt = N1C->getAPIntValue();
13303 Mask = Mask.shl(ShAmt);
13305 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13306 N00, DAG.getConstant(Mask, VT));
13311 // Hardware support for vector shifts is sparse which makes us scalarize the
13312 // vector operations in many cases. Also, on sandybridge ADD is faster than
13314 // (shl V, 1) -> add V,V
13315 if (isSplatVector(N1.getNode())) {
13316 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13317 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13318 // We shift all of the values by one. In many cases we do not have
13319 // hardware support for this operation. This is better expressed as an ADD
13321 if (N1C && (1 == N1C->getZExtValue())) {
13322 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13329 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13331 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13332 const X86Subtarget *Subtarget) {
13333 EVT VT = N->getValueType(0);
13334 if (N->getOpcode() == ISD::SHL) {
13335 SDValue V = PerformSHLCombine(N, DAG);
13336 if (V.getNode()) return V;
13339 // On X86 with SSE2 support, we can transform this to a vector shift if
13340 // all elements are shifted by the same amount. We can't do this in legalize
13341 // because the a constant vector is typically transformed to a constant pool
13342 // so we have no knowledge of the shift amount.
13343 if (!Subtarget->hasXMMInt())
13346 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13347 (!Subtarget->hasAVX2() ||
13348 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13351 SDValue ShAmtOp = N->getOperand(1);
13352 EVT EltVT = VT.getVectorElementType();
13353 DebugLoc DL = N->getDebugLoc();
13354 SDValue BaseShAmt = SDValue();
13355 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13356 unsigned NumElts = VT.getVectorNumElements();
13358 for (; i != NumElts; ++i) {
13359 SDValue Arg = ShAmtOp.getOperand(i);
13360 if (Arg.getOpcode() == ISD::UNDEF) continue;
13364 for (; i != NumElts; ++i) {
13365 SDValue Arg = ShAmtOp.getOperand(i);
13366 if (Arg.getOpcode() == ISD::UNDEF) continue;
13367 if (Arg != BaseShAmt) {
13371 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13372 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13373 SDValue InVec = ShAmtOp.getOperand(0);
13374 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13375 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13377 for (; i != NumElts; ++i) {
13378 SDValue Arg = InVec.getOperand(i);
13379 if (Arg.getOpcode() == ISD::UNDEF) continue;
13383 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13384 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13385 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13386 if (C->getZExtValue() == SplatIdx)
13387 BaseShAmt = InVec.getOperand(1);
13390 if (BaseShAmt.getNode() == 0)
13391 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13392 DAG.getIntPtrConstant(0));
13396 // The shift amount is an i32.
13397 if (EltVT.bitsGT(MVT::i32))
13398 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13399 else if (EltVT.bitsLT(MVT::i32))
13400 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13402 // The shift amount is identical so we can do a vector shift.
13403 SDValue ValOp = N->getOperand(0);
13404 switch (N->getOpcode()) {
13406 llvm_unreachable("Unknown shift opcode!");
13409 if (VT == MVT::v2i64)
13410 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13411 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
13413 if (VT == MVT::v4i32)
13414 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13415 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
13417 if (VT == MVT::v8i16)
13418 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13419 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
13421 if (VT == MVT::v4i64)
13422 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13423 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
13425 if (VT == MVT::v8i32)
13426 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13427 DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32),
13429 if (VT == MVT::v16i16)
13430 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13431 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
13435 if (VT == MVT::v4i32)
13436 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13437 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
13439 if (VT == MVT::v8i16)
13440 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13441 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
13443 if (VT == MVT::v8i32)
13444 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13445 DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32),
13447 if (VT == MVT::v16i16)
13448 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13449 DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32),
13453 if (VT == MVT::v2i64)
13454 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13455 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
13457 if (VT == MVT::v4i32)
13458 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13459 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
13461 if (VT == MVT::v8i16)
13462 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13463 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
13465 if (VT == MVT::v4i64)
13466 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13467 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
13469 if (VT == MVT::v8i32)
13470 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13471 DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32),
13473 if (VT == MVT::v16i16)
13474 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13475 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
13483 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13484 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13485 // and friends. Likewise for OR -> CMPNEQSS.
13486 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13487 TargetLowering::DAGCombinerInfo &DCI,
13488 const X86Subtarget *Subtarget) {
13491 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13492 // we're requiring SSE2 for both.
13493 if (Subtarget->hasXMMInt() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13494 SDValue N0 = N->getOperand(0);
13495 SDValue N1 = N->getOperand(1);
13496 SDValue CMP0 = N0->getOperand(1);
13497 SDValue CMP1 = N1->getOperand(1);
13498 DebugLoc DL = N->getDebugLoc();
13500 // The SETCCs should both refer to the same CMP.
13501 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13504 SDValue CMP00 = CMP0->getOperand(0);
13505 SDValue CMP01 = CMP0->getOperand(1);
13506 EVT VT = CMP00.getValueType();
13508 if (VT == MVT::f32 || VT == MVT::f64) {
13509 bool ExpectingFlags = false;
13510 // Check for any users that want flags:
13511 for (SDNode::use_iterator UI = N->use_begin(),
13513 !ExpectingFlags && UI != UE; ++UI)
13514 switch (UI->getOpcode()) {
13519 ExpectingFlags = true;
13521 case ISD::CopyToReg:
13522 case ISD::SIGN_EXTEND:
13523 case ISD::ZERO_EXTEND:
13524 case ISD::ANY_EXTEND:
13528 if (!ExpectingFlags) {
13529 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13530 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13532 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13533 X86::CondCode tmp = cc0;
13538 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13539 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13540 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13541 X86ISD::NodeType NTOperator = is64BitFP ?
13542 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13543 // FIXME: need symbolic constants for these magic numbers.
13544 // See X86ATTInstPrinter.cpp:printSSECC().
13545 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13546 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13547 DAG.getConstant(x86cc, MVT::i8));
13548 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13550 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13551 DAG.getConstant(1, MVT::i32));
13552 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13553 return OneBitOfTruth;
13561 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13562 /// so it can be folded inside ANDNP.
13563 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13564 EVT VT = N->getValueType(0);
13566 // Match direct AllOnes for 128 and 256-bit vectors
13567 if (ISD::isBuildVectorAllOnes(N))
13570 // Look through a bit convert.
13571 if (N->getOpcode() == ISD::BITCAST)
13572 N = N->getOperand(0).getNode();
13574 // Sometimes the operand may come from a insert_subvector building a 256-bit
13576 if (VT.getSizeInBits() == 256 &&
13577 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13578 SDValue V1 = N->getOperand(0);
13579 SDValue V2 = N->getOperand(1);
13581 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13582 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13583 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13584 ISD::isBuildVectorAllOnes(V2.getNode()))
13591 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13592 TargetLowering::DAGCombinerInfo &DCI,
13593 const X86Subtarget *Subtarget) {
13594 if (DCI.isBeforeLegalizeOps())
13597 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13601 EVT VT = N->getValueType(0);
13603 // Create ANDN, BLSI, and BLSR instructions
13604 // BLSI is X & (-X)
13605 // BLSR is X & (X-1)
13606 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13607 SDValue N0 = N->getOperand(0);
13608 SDValue N1 = N->getOperand(1);
13609 DebugLoc DL = N->getDebugLoc();
13611 // Check LHS for not
13612 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13613 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13614 // Check RHS for not
13615 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13616 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13618 // Check LHS for neg
13619 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13620 isZero(N0.getOperand(0)))
13621 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13623 // Check RHS for neg
13624 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13625 isZero(N1.getOperand(0)))
13626 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13628 // Check LHS for X-1
13629 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13630 isAllOnes(N0.getOperand(1)))
13631 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13633 // Check RHS for X-1
13634 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13635 isAllOnes(N1.getOperand(1)))
13636 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13641 // Want to form ANDNP nodes:
13642 // 1) In the hopes of then easily combining them with OR and AND nodes
13643 // to form PBLEND/PSIGN.
13644 // 2) To match ANDN packed intrinsics
13645 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13648 SDValue N0 = N->getOperand(0);
13649 SDValue N1 = N->getOperand(1);
13650 DebugLoc DL = N->getDebugLoc();
13652 // Check LHS for vnot
13653 if (N0.getOpcode() == ISD::XOR &&
13654 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13655 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13656 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13658 // Check RHS for vnot
13659 if (N1.getOpcode() == ISD::XOR &&
13660 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13661 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13662 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13667 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13668 TargetLowering::DAGCombinerInfo &DCI,
13669 const X86Subtarget *Subtarget) {
13670 if (DCI.isBeforeLegalizeOps())
13673 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13677 EVT VT = N->getValueType(0);
13679 SDValue N0 = N->getOperand(0);
13680 SDValue N1 = N->getOperand(1);
13682 // look for psign/blend
13683 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13684 if (!Subtarget->hasSSSE3orAVX() ||
13685 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13688 // Canonicalize pandn to RHS
13689 if (N0.getOpcode() == X86ISD::ANDNP)
13691 // or (and (m, x), (pandn m, y))
13692 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13693 SDValue Mask = N1.getOperand(0);
13694 SDValue X = N1.getOperand(1);
13696 if (N0.getOperand(0) == Mask)
13697 Y = N0.getOperand(1);
13698 if (N0.getOperand(1) == Mask)
13699 Y = N0.getOperand(0);
13701 // Check to see if the mask appeared in both the AND and ANDNP and
13705 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13706 if (Mask.getOpcode() != ISD::BITCAST ||
13707 X.getOpcode() != ISD::BITCAST ||
13708 Y.getOpcode() != ISD::BITCAST)
13711 // Look through mask bitcast.
13712 Mask = Mask.getOperand(0);
13713 EVT MaskVT = Mask.getValueType();
13715 // Validate that the Mask operand is a vector sra node. The sra node
13716 // will be an intrinsic.
13717 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13720 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13721 // there is no psrai.b
13722 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13723 case Intrinsic::x86_sse2_psrai_w:
13724 case Intrinsic::x86_sse2_psrai_d:
13725 case Intrinsic::x86_avx2_psrai_w:
13726 case Intrinsic::x86_avx2_psrai_d:
13728 default: return SDValue();
13731 // Check that the SRA is all signbits.
13732 SDValue SraC = Mask.getOperand(2);
13733 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13734 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13735 if ((SraAmt + 1) != EltBits)
13738 DebugLoc DL = N->getDebugLoc();
13740 // Now we know we at least have a plendvb with the mask val. See if
13741 // we can form a psignb/w/d.
13742 // psign = x.type == y.type == mask.type && y = sub(0, x);
13743 X = X.getOperand(0);
13744 Y = Y.getOperand(0);
13745 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13746 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13747 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType() &&
13748 (EltBits == 8 || EltBits == 16 || EltBits == 32)) {
13749 SDValue Sign = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X,
13750 Mask.getOperand(1));
13751 return DAG.getNode(ISD::BITCAST, DL, VT, Sign);
13753 // PBLENDVB only available on SSE 4.1
13754 if (!Subtarget->hasSSE41orAVX())
13757 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
13759 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
13760 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
13761 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
13762 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
13763 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
13767 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
13770 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13771 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13773 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13775 if (!N0.hasOneUse() || !N1.hasOneUse())
13778 SDValue ShAmt0 = N0.getOperand(1);
13779 if (ShAmt0.getValueType() != MVT::i8)
13781 SDValue ShAmt1 = N1.getOperand(1);
13782 if (ShAmt1.getValueType() != MVT::i8)
13784 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13785 ShAmt0 = ShAmt0.getOperand(0);
13786 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13787 ShAmt1 = ShAmt1.getOperand(0);
13789 DebugLoc DL = N->getDebugLoc();
13790 unsigned Opc = X86ISD::SHLD;
13791 SDValue Op0 = N0.getOperand(0);
13792 SDValue Op1 = N1.getOperand(0);
13793 if (ShAmt0.getOpcode() == ISD::SUB) {
13794 Opc = X86ISD::SHRD;
13795 std::swap(Op0, Op1);
13796 std::swap(ShAmt0, ShAmt1);
13799 unsigned Bits = VT.getSizeInBits();
13800 if (ShAmt1.getOpcode() == ISD::SUB) {
13801 SDValue Sum = ShAmt1.getOperand(0);
13802 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13803 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13804 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13805 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13806 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13807 return DAG.getNode(Opc, DL, VT,
13809 DAG.getNode(ISD::TRUNCATE, DL,
13812 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13813 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13815 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13816 return DAG.getNode(Opc, DL, VT,
13817 N0.getOperand(0), N1.getOperand(0),
13818 DAG.getNode(ISD::TRUNCATE, DL,
13825 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
13826 TargetLowering::DAGCombinerInfo &DCI,
13827 const X86Subtarget *Subtarget) {
13828 if (DCI.isBeforeLegalizeOps())
13831 EVT VT = N->getValueType(0);
13833 if (VT != MVT::i32 && VT != MVT::i64)
13836 // Create BLSMSK instructions by finding X ^ (X-1)
13837 SDValue N0 = N->getOperand(0);
13838 SDValue N1 = N->getOperand(1);
13839 DebugLoc DL = N->getDebugLoc();
13841 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13842 isAllOnes(N0.getOperand(1)))
13843 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
13845 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13846 isAllOnes(N1.getOperand(1)))
13847 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
13852 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
13853 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
13854 const X86Subtarget *Subtarget) {
13855 LoadSDNode *Ld = cast<LoadSDNode>(N);
13856 EVT RegVT = Ld->getValueType(0);
13857 EVT MemVT = Ld->getMemoryVT();
13858 DebugLoc dl = Ld->getDebugLoc();
13859 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13861 ISD::LoadExtType Ext = Ld->getExtensionType();
13863 // If this is a vector EXT Load then attempt to optimize it using a
13864 // shuffle. We need SSE4 for the shuffles.
13865 // TODO: It is possible to support ZExt by zeroing the undef values
13866 // during the shuffle phase or after the shuffle.
13867 if (RegVT.isVector() && Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
13868 assert(MemVT != RegVT && "Cannot extend to the same type");
13869 assert(MemVT.isVector() && "Must load a vector from memory");
13871 unsigned NumElems = RegVT.getVectorNumElements();
13872 unsigned RegSz = RegVT.getSizeInBits();
13873 unsigned MemSz = MemVT.getSizeInBits();
13874 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13875 // All sizes must be a power of two
13876 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
13878 // Attempt to load the original value using a single load op.
13879 // Find a scalar type which is equal to the loaded word size.
13880 MVT SclrLoadTy = MVT::i8;
13881 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13882 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13883 MVT Tp = (MVT::SimpleValueType)tp;
13884 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
13890 // Proceed if a load word is found.
13891 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
13893 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
13894 RegSz/SclrLoadTy.getSizeInBits());
13896 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13897 RegSz/MemVT.getScalarType().getSizeInBits());
13898 // Can't shuffle using an illegal type.
13899 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13901 // Perform a single load.
13902 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
13904 Ld->getPointerInfo(), Ld->isVolatile(),
13905 Ld->isNonTemporal(), Ld->isInvariant(),
13906 Ld->getAlignment());
13908 // Insert the word loaded into a vector.
13909 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13910 LoadUnitVecVT, ScalarLoad);
13912 // Bitcast the loaded value to a vector of the original element type, in
13913 // the size of the target vector type.
13914 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, ScalarInVector);
13915 unsigned SizeRatio = RegSz/MemSz;
13917 // Redistribute the loaded elements into the different locations.
13918 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13919 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
13921 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13922 DAG.getUNDEF(SlicedVec.getValueType()),
13923 ShuffleVec.data());
13925 // Bitcast to the requested type.
13926 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13927 // Replace the original load with the new sequence
13928 // and return the new chain.
13929 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
13930 return SDValue(ScalarLoad.getNode(), 1);
13936 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13937 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13938 const X86Subtarget *Subtarget) {
13939 StoreSDNode *St = cast<StoreSDNode>(N);
13940 EVT VT = St->getValue().getValueType();
13941 EVT StVT = St->getMemoryVT();
13942 DebugLoc dl = St->getDebugLoc();
13943 SDValue StoredVal = St->getOperand(1);
13944 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13946 // If we are saving a concatenation of two XMM registers, perform two stores.
13947 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
13948 // 128-bit ones. If in the future the cost becomes only one memory access the
13949 // first version would be better.
13950 if (VT.getSizeInBits() == 256 &&
13951 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
13952 StoredVal.getNumOperands() == 2) {
13954 SDValue Value0 = StoredVal.getOperand(0);
13955 SDValue Value1 = StoredVal.getOperand(1);
13957 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
13958 SDValue Ptr0 = St->getBasePtr();
13959 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
13961 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
13962 St->getPointerInfo(), St->isVolatile(),
13963 St->isNonTemporal(), St->getAlignment());
13964 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
13965 St->getPointerInfo(), St->isVolatile(),
13966 St->isNonTemporal(), St->getAlignment());
13967 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
13970 // Optimize trunc store (of multiple scalars) to shuffle and store.
13971 // First, pack all of the elements in one place. Next, store to memory
13972 // in fewer chunks.
13973 if (St->isTruncatingStore() && VT.isVector()) {
13974 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13975 unsigned NumElems = VT.getVectorNumElements();
13976 assert(StVT != VT && "Cannot truncate to the same type");
13977 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
13978 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
13980 // From, To sizes and ElemCount must be pow of two
13981 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
13982 // We are going to use the original vector elt for storing.
13983 // Accumulated smaller vector elements must be a multiple of the store size.
13984 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
13986 unsigned SizeRatio = FromSz / ToSz;
13988 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
13990 // Create a type on which we perform the shuffle
13991 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
13992 StVT.getScalarType(), NumElems*SizeRatio);
13994 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
13996 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
13997 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13998 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14000 // Can't shuffle using an illegal type
14001 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14003 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14004 DAG.getUNDEF(WideVec.getValueType()),
14005 ShuffleVec.data());
14006 // At this point all of the data is stored at the bottom of the
14007 // register. We now need to save it to mem.
14009 // Find the largest store unit
14010 MVT StoreType = MVT::i8;
14011 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14012 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14013 MVT Tp = (MVT::SimpleValueType)tp;
14014 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14018 // Bitcast the original vector into a vector of store-size units
14019 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14020 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14021 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14022 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14023 SmallVector<SDValue, 8> Chains;
14024 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14025 TLI.getPointerTy());
14026 SDValue Ptr = St->getBasePtr();
14028 // Perform one or more big stores into memory.
14029 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14030 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14031 StoreType, ShuffWide,
14032 DAG.getIntPtrConstant(i));
14033 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14034 St->getPointerInfo(), St->isVolatile(),
14035 St->isNonTemporal(), St->getAlignment());
14036 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14037 Chains.push_back(Ch);
14040 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14045 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14046 // the FP state in cases where an emms may be missing.
14047 // A preferable solution to the general problem is to figure out the right
14048 // places to insert EMMS. This qualifies as a quick hack.
14050 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14051 if (VT.getSizeInBits() != 64)
14054 const Function *F = DAG.getMachineFunction().getFunction();
14055 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14056 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14057 && Subtarget->hasXMMInt();
14058 if ((VT.isVector() ||
14059 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14060 isa<LoadSDNode>(St->getValue()) &&
14061 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14062 St->getChain().hasOneUse() && !St->isVolatile()) {
14063 SDNode* LdVal = St->getValue().getNode();
14064 LoadSDNode *Ld = 0;
14065 int TokenFactorIndex = -1;
14066 SmallVector<SDValue, 8> Ops;
14067 SDNode* ChainVal = St->getChain().getNode();
14068 // Must be a store of a load. We currently handle two cases: the load
14069 // is a direct child, and it's under an intervening TokenFactor. It is
14070 // possible to dig deeper under nested TokenFactors.
14071 if (ChainVal == LdVal)
14072 Ld = cast<LoadSDNode>(St->getChain());
14073 else if (St->getValue().hasOneUse() &&
14074 ChainVal->getOpcode() == ISD::TokenFactor) {
14075 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
14076 if (ChainVal->getOperand(i).getNode() == LdVal) {
14077 TokenFactorIndex = i;
14078 Ld = cast<LoadSDNode>(St->getValue());
14080 Ops.push_back(ChainVal->getOperand(i));
14084 if (!Ld || !ISD::isNormalLoad(Ld))
14087 // If this is not the MMX case, i.e. we are just turning i64 load/store
14088 // into f64 load/store, avoid the transformation if there are multiple
14089 // uses of the loaded value.
14090 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14093 DebugLoc LdDL = Ld->getDebugLoc();
14094 DebugLoc StDL = N->getDebugLoc();
14095 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14096 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14098 if (Subtarget->is64Bit() || F64IsLegal) {
14099 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14100 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14101 Ld->getPointerInfo(), Ld->isVolatile(),
14102 Ld->isNonTemporal(), Ld->isInvariant(),
14103 Ld->getAlignment());
14104 SDValue NewChain = NewLd.getValue(1);
14105 if (TokenFactorIndex != -1) {
14106 Ops.push_back(NewChain);
14107 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14110 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14111 St->getPointerInfo(),
14112 St->isVolatile(), St->isNonTemporal(),
14113 St->getAlignment());
14116 // Otherwise, lower to two pairs of 32-bit loads / stores.
14117 SDValue LoAddr = Ld->getBasePtr();
14118 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14119 DAG.getConstant(4, MVT::i32));
14121 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14122 Ld->getPointerInfo(),
14123 Ld->isVolatile(), Ld->isNonTemporal(),
14124 Ld->isInvariant(), Ld->getAlignment());
14125 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14126 Ld->getPointerInfo().getWithOffset(4),
14127 Ld->isVolatile(), Ld->isNonTemporal(),
14129 MinAlign(Ld->getAlignment(), 4));
14131 SDValue NewChain = LoLd.getValue(1);
14132 if (TokenFactorIndex != -1) {
14133 Ops.push_back(LoLd);
14134 Ops.push_back(HiLd);
14135 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14139 LoAddr = St->getBasePtr();
14140 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14141 DAG.getConstant(4, MVT::i32));
14143 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14144 St->getPointerInfo(),
14145 St->isVolatile(), St->isNonTemporal(),
14146 St->getAlignment());
14147 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14148 St->getPointerInfo().getWithOffset(4),
14150 St->isNonTemporal(),
14151 MinAlign(St->getAlignment(), 4));
14152 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14157 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14158 /// and return the operands for the horizontal operation in LHS and RHS. A
14159 /// horizontal operation performs the binary operation on successive elements
14160 /// of its first operand, then on successive elements of its second operand,
14161 /// returning the resulting values in a vector. For example, if
14162 /// A = < float a0, float a1, float a2, float a3 >
14164 /// B = < float b0, float b1, float b2, float b3 >
14165 /// then the result of doing a horizontal operation on A and B is
14166 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14167 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14168 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14169 /// set to A, RHS to B, and the routine returns 'true'.
14170 /// Note that the binary operation should have the property that if one of the
14171 /// operands is UNDEF then the result is UNDEF.
14172 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14173 // Look for the following pattern: if
14174 // A = < float a0, float a1, float a2, float a3 >
14175 // B = < float b0, float b1, float b2, float b3 >
14177 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14178 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14179 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14180 // which is A horizontal-op B.
14182 // At least one of the operands should be a vector shuffle.
14183 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14184 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14187 EVT VT = LHS.getValueType();
14189 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14190 "Unsupported vector type for horizontal add/sub");
14192 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14193 // operate independently on 128-bit lanes.
14194 unsigned NumElts = VT.getVectorNumElements();
14195 unsigned NumLanes = VT.getSizeInBits()/128;
14196 unsigned NumLaneElts = NumElts / NumLanes;
14197 assert((NumLaneElts % 2 == 0) &&
14198 "Vector type should have an even number of elements in each lane");
14199 unsigned HalfLaneElts = NumLaneElts/2;
14201 // View LHS in the form
14202 // LHS = VECTOR_SHUFFLE A, B, LMask
14203 // If LHS is not a shuffle then pretend it is the shuffle
14204 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14205 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14208 SmallVector<int, 16> LMask(NumElts);
14209 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14210 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14211 A = LHS.getOperand(0);
14212 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14213 B = LHS.getOperand(1);
14214 cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(LMask);
14216 if (LHS.getOpcode() != ISD::UNDEF)
14218 for (unsigned i = 0; i != NumElts; ++i)
14222 // Likewise, view RHS in the form
14223 // RHS = VECTOR_SHUFFLE C, D, RMask
14225 SmallVector<int, 16> RMask(NumElts);
14226 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14227 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14228 C = RHS.getOperand(0);
14229 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14230 D = RHS.getOperand(1);
14231 cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(RMask);
14233 if (RHS.getOpcode() != ISD::UNDEF)
14235 for (unsigned i = 0; i != NumElts; ++i)
14239 // Check that the shuffles are both shuffling the same vectors.
14240 if (!(A == C && B == D) && !(A == D && B == C))
14243 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14244 if (!A.getNode() && !B.getNode())
14247 // If A and B occur in reverse order in RHS, then "swap" them (which means
14248 // rewriting the mask).
14250 CommuteVectorShuffleMask(RMask, NumElts);
14252 // At this point LHS and RHS are equivalent to
14253 // LHS = VECTOR_SHUFFLE A, B, LMask
14254 // RHS = VECTOR_SHUFFLE A, B, RMask
14255 // Check that the masks correspond to performing a horizontal operation.
14256 for (unsigned i = 0; i != NumElts; ++i) {
14257 int LIdx = LMask[i], RIdx = RMask[i];
14259 // Ignore any UNDEF components.
14260 if (LIdx < 0 || RIdx < 0 ||
14261 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14262 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14265 // Check that successive elements are being operated on. If not, this is
14266 // not a horizontal operation.
14267 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14268 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14269 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14270 if (!(LIdx == Index && RIdx == Index + 1) &&
14271 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14275 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14276 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14280 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14281 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14282 const X86Subtarget *Subtarget) {
14283 EVT VT = N->getValueType(0);
14284 SDValue LHS = N->getOperand(0);
14285 SDValue RHS = N->getOperand(1);
14287 // Try to synthesize horizontal adds from adds of shuffles.
14288 if (((Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14289 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14290 isHorizontalBinOp(LHS, RHS, true))
14291 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14295 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14296 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14297 const X86Subtarget *Subtarget) {
14298 EVT VT = N->getValueType(0);
14299 SDValue LHS = N->getOperand(0);
14300 SDValue RHS = N->getOperand(1);
14302 // Try to synthesize horizontal subs from subs of shuffles.
14303 if (((Subtarget->hasSSE3orAVX() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14304 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14305 isHorizontalBinOp(LHS, RHS, false))
14306 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14310 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14311 /// X86ISD::FXOR nodes.
14312 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14313 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14314 // F[X]OR(0.0, x) -> x
14315 // F[X]OR(x, 0.0) -> x
14316 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14317 if (C->getValueAPF().isPosZero())
14318 return N->getOperand(1);
14319 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14320 if (C->getValueAPF().isPosZero())
14321 return N->getOperand(0);
14325 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14326 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14327 // FAND(0.0, x) -> 0.0
14328 // FAND(x, 0.0) -> 0.0
14329 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14330 if (C->getValueAPF().isPosZero())
14331 return N->getOperand(0);
14332 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14333 if (C->getValueAPF().isPosZero())
14334 return N->getOperand(1);
14338 static SDValue PerformBTCombine(SDNode *N,
14340 TargetLowering::DAGCombinerInfo &DCI) {
14341 // BT ignores high bits in the bit index operand.
14342 SDValue Op1 = N->getOperand(1);
14343 if (Op1.hasOneUse()) {
14344 unsigned BitWidth = Op1.getValueSizeInBits();
14345 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14346 APInt KnownZero, KnownOne;
14347 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14348 !DCI.isBeforeLegalizeOps());
14349 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14350 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14351 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14352 DCI.CommitTargetLoweringOpt(TLO);
14357 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14358 SDValue Op = N->getOperand(0);
14359 if (Op.getOpcode() == ISD::BITCAST)
14360 Op = Op.getOperand(0);
14361 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14362 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14363 VT.getVectorElementType().getSizeInBits() ==
14364 OpVT.getVectorElementType().getSizeInBits()) {
14365 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14370 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
14371 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14372 // (and (i32 x86isd::setcc_carry), 1)
14373 // This eliminates the zext. This transformation is necessary because
14374 // ISD::SETCC is always legalized to i8.
14375 DebugLoc dl = N->getDebugLoc();
14376 SDValue N0 = N->getOperand(0);
14377 EVT VT = N->getValueType(0);
14378 if (N0.getOpcode() == ISD::AND &&
14380 N0.getOperand(0).hasOneUse()) {
14381 SDValue N00 = N0.getOperand(0);
14382 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14384 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14385 if (!C || C->getZExtValue() != 1)
14387 return DAG.getNode(ISD::AND, dl, VT,
14388 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14389 N00.getOperand(0), N00.getOperand(1)),
14390 DAG.getConstant(1, VT));
14396 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14397 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14398 unsigned X86CC = N->getConstantOperandVal(0);
14399 SDValue EFLAG = N->getOperand(1);
14400 DebugLoc DL = N->getDebugLoc();
14402 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14403 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14405 if (X86CC == X86::COND_B)
14406 return DAG.getNode(ISD::AND, DL, MVT::i8,
14407 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14408 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14409 DAG.getConstant(1, MVT::i8));
14414 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14415 const X86TargetLowering *XTLI) {
14416 SDValue Op0 = N->getOperand(0);
14417 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14418 // a 32-bit target where SSE doesn't support i64->FP operations.
14419 if (Op0.getOpcode() == ISD::LOAD) {
14420 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14421 EVT VT = Ld->getValueType(0);
14422 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14423 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14424 !XTLI->getSubtarget()->is64Bit() &&
14425 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14426 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14427 Ld->getChain(), Op0, DAG);
14428 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14435 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14436 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14437 X86TargetLowering::DAGCombinerInfo &DCI) {
14438 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14439 // the result is either zero or one (depending on the input carry bit).
14440 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14441 if (X86::isZeroNode(N->getOperand(0)) &&
14442 X86::isZeroNode(N->getOperand(1)) &&
14443 // We don't have a good way to replace an EFLAGS use, so only do this when
14445 SDValue(N, 1).use_empty()) {
14446 DebugLoc DL = N->getDebugLoc();
14447 EVT VT = N->getValueType(0);
14448 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14449 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14450 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14451 DAG.getConstant(X86::COND_B,MVT::i8),
14453 DAG.getConstant(1, VT));
14454 return DCI.CombineTo(N, Res1, CarryOut);
14460 // fold (add Y, (sete X, 0)) -> adc 0, Y
14461 // (add Y, (setne X, 0)) -> sbb -1, Y
14462 // (sub (sete X, 0), Y) -> sbb 0, Y
14463 // (sub (setne X, 0), Y) -> adc -1, Y
14464 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14465 DebugLoc DL = N->getDebugLoc();
14467 // Look through ZExts.
14468 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14469 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14472 SDValue SetCC = Ext.getOperand(0);
14473 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14476 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14477 if (CC != X86::COND_E && CC != X86::COND_NE)
14480 SDValue Cmp = SetCC.getOperand(1);
14481 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14482 !X86::isZeroNode(Cmp.getOperand(1)) ||
14483 !Cmp.getOperand(0).getValueType().isInteger())
14486 SDValue CmpOp0 = Cmp.getOperand(0);
14487 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14488 DAG.getConstant(1, CmpOp0.getValueType()));
14490 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14491 if (CC == X86::COND_NE)
14492 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14493 DL, OtherVal.getValueType(), OtherVal,
14494 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14495 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14496 DL, OtherVal.getValueType(), OtherVal,
14497 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14500 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14501 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14502 const X86Subtarget *Subtarget) {
14503 EVT VT = N->getValueType(0);
14504 SDValue Op0 = N->getOperand(0);
14505 SDValue Op1 = N->getOperand(1);
14507 // Try to synthesize horizontal adds from adds of shuffles.
14508 if (((Subtarget->hasSSSE3orAVX() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14509 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || MVT::v8i32))) &&
14510 isHorizontalBinOp(Op0, Op1, true))
14511 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14513 return OptimizeConditionalInDecrement(N, DAG);
14516 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14517 const X86Subtarget *Subtarget) {
14518 SDValue Op0 = N->getOperand(0);
14519 SDValue Op1 = N->getOperand(1);
14521 // X86 can't encode an immediate LHS of a sub. See if we can push the
14522 // negation into a preceding instruction.
14523 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14524 // If the RHS of the sub is a XOR with one use and a constant, invert the
14525 // immediate. Then add one to the LHS of the sub so we can turn
14526 // X-Y -> X+~Y+1, saving one register.
14527 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14528 isa<ConstantSDNode>(Op1.getOperand(1))) {
14529 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14530 EVT VT = Op0.getValueType();
14531 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14533 DAG.getConstant(~XorC, VT));
14534 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14535 DAG.getConstant(C->getAPIntValue()+1, VT));
14539 // Try to synthesize horizontal adds from adds of shuffles.
14540 EVT VT = N->getValueType(0);
14541 if (((Subtarget->hasSSSE3orAVX() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14542 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14543 isHorizontalBinOp(Op0, Op1, true))
14544 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14546 return OptimizeConditionalInDecrement(N, DAG);
14549 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14550 DAGCombinerInfo &DCI) const {
14551 SelectionDAG &DAG = DCI.DAG;
14552 switch (N->getOpcode()) {
14554 case ISD::EXTRACT_VECTOR_ELT:
14555 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14557 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
14558 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14559 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14560 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14561 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14562 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14565 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
14566 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14567 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14568 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14569 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14570 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14571 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14572 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14573 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14575 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14576 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14577 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14578 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14579 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
14580 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14581 case X86ISD::SHUFPS: // Handle all target specific shuffles
14582 case X86ISD::SHUFPD:
14583 case X86ISD::PALIGN:
14584 case X86ISD::UNPCKH:
14585 case X86ISD::UNPCKL:
14586 case X86ISD::MOVHLPS:
14587 case X86ISD::MOVLHPS:
14588 case X86ISD::PSHUFD:
14589 case X86ISD::PSHUFHW:
14590 case X86ISD::PSHUFLW:
14591 case X86ISD::MOVSS:
14592 case X86ISD::MOVSD:
14593 case X86ISD::VPERMILP:
14594 case X86ISD::VPERM2X128:
14595 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14601 /// isTypeDesirableForOp - Return true if the target has native support for
14602 /// the specified value type and it is 'desirable' to use the type for the
14603 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14604 /// instruction encodings are longer and some i16 instructions are slow.
14605 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14606 if (!isTypeLegal(VT))
14608 if (VT != MVT::i16)
14615 case ISD::SIGN_EXTEND:
14616 case ISD::ZERO_EXTEND:
14617 case ISD::ANY_EXTEND:
14630 /// IsDesirableToPromoteOp - This method query the target whether it is
14631 /// beneficial for dag combiner to promote the specified node. If true, it
14632 /// should return the desired promotion type by reference.
14633 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14634 EVT VT = Op.getValueType();
14635 if (VT != MVT::i16)
14638 bool Promote = false;
14639 bool Commute = false;
14640 switch (Op.getOpcode()) {
14643 LoadSDNode *LD = cast<LoadSDNode>(Op);
14644 // If the non-extending load has a single use and it's not live out, then it
14645 // might be folded.
14646 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14647 Op.hasOneUse()*/) {
14648 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14649 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14650 // The only case where we'd want to promote LOAD (rather then it being
14651 // promoted as an operand is when it's only use is liveout.
14652 if (UI->getOpcode() != ISD::CopyToReg)
14659 case ISD::SIGN_EXTEND:
14660 case ISD::ZERO_EXTEND:
14661 case ISD::ANY_EXTEND:
14666 SDValue N0 = Op.getOperand(0);
14667 // Look out for (store (shl (load), x)).
14668 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
14681 SDValue N0 = Op.getOperand(0);
14682 SDValue N1 = Op.getOperand(1);
14683 if (!Commute && MayFoldLoad(N1))
14685 // Avoid disabling potential load folding opportunities.
14686 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14688 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14698 //===----------------------------------------------------------------------===//
14699 // X86 Inline Assembly Support
14700 //===----------------------------------------------------------------------===//
14702 // Helper to match a string separated by whitespace.
14703 static bool END_WITH_NULL matchAsm(StringRef s, ...) {
14706 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
14708 while (const char *p = va_arg(ap, const char *)) {
14709 StringRef piece(p);
14710 if (!s.startswith(piece)) { // Check if the piece matches.
14715 s = s.substr(piece.size());
14716 StringRef::size_type i = s.find_first_not_of(" \t");
14717 if (i == 0) { // We matched a prefix.
14728 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
14729 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
14731 std::string AsmStr = IA->getAsmString();
14733 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14734 if (!Ty || Ty->getBitWidth() % 16 != 0)
14737 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
14738 SmallVector<StringRef, 4> AsmPieces;
14739 SplitString(AsmStr, AsmPieces, ";\n");
14741 switch (AsmPieces.size()) {
14742 default: return false;
14744 // FIXME: this should verify that we are targeting a 486 or better. If not,
14745 // we will turn this bswap into something that will be lowered to logical
14746 // ops instead of emitting the bswap asm. For now, we don't support 486 or
14747 // lower so don't worry about this.
14749 if (matchAsm(AsmPieces[0], "bswap", "$0", NULL) ||
14750 matchAsm(AsmPieces[0], "bswapl", "$0", NULL) ||
14751 matchAsm(AsmPieces[0], "bswapq", "$0", NULL) ||
14752 matchAsm(AsmPieces[0], "bswap", "${0:q}", NULL) ||
14753 matchAsm(AsmPieces[0], "bswapl", "${0:q}", NULL) ||
14754 matchAsm(AsmPieces[0], "bswapq", "${0:q}", NULL)) {
14755 // No need to check constraints, nothing other than the equivalent of
14756 // "=r,0" would be valid here.
14757 return IntrinsicLowering::LowerToByteSwap(CI);
14760 // rorw $$8, ${0:w} --> llvm.bswap.i16
14761 if (CI->getType()->isIntegerTy(16) &&
14762 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
14763 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}", NULL) ||
14764 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}", NULL))) {
14766 const std::string &ConstraintsStr = IA->getConstraintString();
14767 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14768 std::sort(AsmPieces.begin(), AsmPieces.end());
14769 if (AsmPieces.size() == 4 &&
14770 AsmPieces[0] == "~{cc}" &&
14771 AsmPieces[1] == "~{dirflag}" &&
14772 AsmPieces[2] == "~{flags}" &&
14773 AsmPieces[3] == "~{fpsr}")
14774 return IntrinsicLowering::LowerToByteSwap(CI);
14778 if (CI->getType()->isIntegerTy(32) &&
14779 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
14780 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}", NULL) &&
14781 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0", NULL) &&
14782 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}", NULL)) {
14784 const std::string &ConstraintsStr = IA->getConstraintString();
14785 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14786 std::sort(AsmPieces.begin(), AsmPieces.end());
14787 if (AsmPieces.size() == 4 &&
14788 AsmPieces[0] == "~{cc}" &&
14789 AsmPieces[1] == "~{dirflag}" &&
14790 AsmPieces[2] == "~{flags}" &&
14791 AsmPieces[3] == "~{fpsr}")
14792 return IntrinsicLowering::LowerToByteSwap(CI);
14795 if (CI->getType()->isIntegerTy(64)) {
14796 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
14797 if (Constraints.size() >= 2 &&
14798 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
14799 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
14800 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
14801 if (matchAsm(AsmPieces[0], "bswap", "%eax", NULL) &&
14802 matchAsm(AsmPieces[1], "bswap", "%edx", NULL) &&
14803 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx", NULL))
14804 return IntrinsicLowering::LowerToByteSwap(CI);
14814 /// getConstraintType - Given a constraint letter, return the type of
14815 /// constraint it is for this target.
14816 X86TargetLowering::ConstraintType
14817 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
14818 if (Constraint.size() == 1) {
14819 switch (Constraint[0]) {
14830 return C_RegisterClass;
14854 return TargetLowering::getConstraintType(Constraint);
14857 /// Examine constraint type and operand type and determine a weight value.
14858 /// This object must already have been set up with the operand type
14859 /// and the current alternative constraint selected.
14860 TargetLowering::ConstraintWeight
14861 X86TargetLowering::getSingleConstraintMatchWeight(
14862 AsmOperandInfo &info, const char *constraint) const {
14863 ConstraintWeight weight = CW_Invalid;
14864 Value *CallOperandVal = info.CallOperandVal;
14865 // If we don't have a value, we can't do a match,
14866 // but allow it at the lowest weight.
14867 if (CallOperandVal == NULL)
14869 Type *type = CallOperandVal->getType();
14870 // Look at the constraint type.
14871 switch (*constraint) {
14873 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14884 if (CallOperandVal->getType()->isIntegerTy())
14885 weight = CW_SpecificReg;
14890 if (type->isFloatingPointTy())
14891 weight = CW_SpecificReg;
14894 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14895 weight = CW_SpecificReg;
14899 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
14900 weight = CW_Register;
14903 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
14904 if (C->getZExtValue() <= 31)
14905 weight = CW_Constant;
14909 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14910 if (C->getZExtValue() <= 63)
14911 weight = CW_Constant;
14915 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14916 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
14917 weight = CW_Constant;
14921 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14922 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14923 weight = CW_Constant;
14927 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14928 if (C->getZExtValue() <= 3)
14929 weight = CW_Constant;
14933 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14934 if (C->getZExtValue() <= 0xff)
14935 weight = CW_Constant;
14940 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14941 weight = CW_Constant;
14945 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14946 if ((C->getSExtValue() >= -0x80000000LL) &&
14947 (C->getSExtValue() <= 0x7fffffffLL))
14948 weight = CW_Constant;
14952 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14953 if (C->getZExtValue() <= 0xffffffff)
14954 weight = CW_Constant;
14961 /// LowerXConstraint - try to replace an X constraint, which matches anything,
14962 /// with another that has more specific requirements based on the type of the
14963 /// corresponding operand.
14964 const char *X86TargetLowering::
14965 LowerXConstraint(EVT ConstraintVT) const {
14966 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
14967 // 'f' like normal targets.
14968 if (ConstraintVT.isFloatingPoint()) {
14969 if (Subtarget->hasXMMInt())
14971 if (Subtarget->hasXMM())
14975 return TargetLowering::LowerXConstraint(ConstraintVT);
14978 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
14979 /// vector. If it is invalid, don't add anything to Ops.
14980 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
14981 std::string &Constraint,
14982 std::vector<SDValue>&Ops,
14983 SelectionDAG &DAG) const {
14984 SDValue Result(0, 0);
14986 // Only support length 1 constraints for now.
14987 if (Constraint.length() > 1) return;
14989 char ConstraintLetter = Constraint[0];
14990 switch (ConstraintLetter) {
14993 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14994 if (C->getZExtValue() <= 31) {
14995 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15001 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15002 if (C->getZExtValue() <= 63) {
15003 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15009 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15010 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15011 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15017 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15018 if (C->getZExtValue() <= 255) {
15019 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15025 // 32-bit signed value
15026 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15027 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15028 C->getSExtValue())) {
15029 // Widen to 64 bits here to get it sign extended.
15030 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15033 // FIXME gcc accepts some relocatable values here too, but only in certain
15034 // memory models; it's complicated.
15039 // 32-bit unsigned value
15040 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15041 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15042 C->getZExtValue())) {
15043 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15047 // FIXME gcc accepts some relocatable values here too, but only in certain
15048 // memory models; it's complicated.
15052 // Literal immediates are always ok.
15053 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15054 // Widen to 64 bits here to get it sign extended.
15055 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15059 // In any sort of PIC mode addresses need to be computed at runtime by
15060 // adding in a register or some sort of table lookup. These can't
15061 // be used as immediates.
15062 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15065 // If we are in non-pic codegen mode, we allow the address of a global (with
15066 // an optional displacement) to be used with 'i'.
15067 GlobalAddressSDNode *GA = 0;
15068 int64_t Offset = 0;
15070 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15072 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15073 Offset += GA->getOffset();
15075 } else if (Op.getOpcode() == ISD::ADD) {
15076 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15077 Offset += C->getZExtValue();
15078 Op = Op.getOperand(0);
15081 } else if (Op.getOpcode() == ISD::SUB) {
15082 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15083 Offset += -C->getZExtValue();
15084 Op = Op.getOperand(0);
15089 // Otherwise, this isn't something we can handle, reject it.
15093 const GlobalValue *GV = GA->getGlobal();
15094 // If we require an extra load to get this address, as in PIC mode, we
15095 // can't accept it.
15096 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15097 getTargetMachine())))
15100 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15101 GA->getValueType(0), Offset);
15106 if (Result.getNode()) {
15107 Ops.push_back(Result);
15110 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15113 std::pair<unsigned, const TargetRegisterClass*>
15114 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15116 // First, see if this is a constraint that directly corresponds to an LLVM
15118 if (Constraint.size() == 1) {
15119 // GCC Constraint Letters
15120 switch (Constraint[0]) {
15122 // TODO: Slight differences here in allocation order and leaving
15123 // RIP in the class. Do they matter any more here than they do
15124 // in the normal allocation?
15125 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15126 if (Subtarget->is64Bit()) {
15127 if (VT == MVT::i32 || VT == MVT::f32)
15128 return std::make_pair(0U, X86::GR32RegisterClass);
15129 else if (VT == MVT::i16)
15130 return std::make_pair(0U, X86::GR16RegisterClass);
15131 else if (VT == MVT::i8 || VT == MVT::i1)
15132 return std::make_pair(0U, X86::GR8RegisterClass);
15133 else if (VT == MVT::i64 || VT == MVT::f64)
15134 return std::make_pair(0U, X86::GR64RegisterClass);
15137 // 32-bit fallthrough
15138 case 'Q': // Q_REGS
15139 if (VT == MVT::i32 || VT == MVT::f32)
15140 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15141 else if (VT == MVT::i16)
15142 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15143 else if (VT == MVT::i8 || VT == MVT::i1)
15144 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15145 else if (VT == MVT::i64)
15146 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15148 case 'r': // GENERAL_REGS
15149 case 'l': // INDEX_REGS
15150 if (VT == MVT::i8 || VT == MVT::i1)
15151 return std::make_pair(0U, X86::GR8RegisterClass);
15152 if (VT == MVT::i16)
15153 return std::make_pair(0U, X86::GR16RegisterClass);
15154 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15155 return std::make_pair(0U, X86::GR32RegisterClass);
15156 return std::make_pair(0U, X86::GR64RegisterClass);
15157 case 'R': // LEGACY_REGS
15158 if (VT == MVT::i8 || VT == MVT::i1)
15159 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15160 if (VT == MVT::i16)
15161 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15162 if (VT == MVT::i32 || !Subtarget->is64Bit())
15163 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15164 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15165 case 'f': // FP Stack registers.
15166 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15167 // value to the correct fpstack register class.
15168 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15169 return std::make_pair(0U, X86::RFP32RegisterClass);
15170 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15171 return std::make_pair(0U, X86::RFP64RegisterClass);
15172 return std::make_pair(0U, X86::RFP80RegisterClass);
15173 case 'y': // MMX_REGS if MMX allowed.
15174 if (!Subtarget->hasMMX()) break;
15175 return std::make_pair(0U, X86::VR64RegisterClass);
15176 case 'Y': // SSE_REGS if SSE2 allowed
15177 if (!Subtarget->hasXMMInt()) break;
15179 case 'x': // SSE_REGS if SSE1 allowed
15180 if (!Subtarget->hasXMM()) break;
15182 switch (VT.getSimpleVT().SimpleTy) {
15184 // Scalar SSE types.
15187 return std::make_pair(0U, X86::FR32RegisterClass);
15190 return std::make_pair(0U, X86::FR64RegisterClass);
15198 return std::make_pair(0U, X86::VR128RegisterClass);
15204 // Use the default implementation in TargetLowering to convert the register
15205 // constraint into a member of a register class.
15206 std::pair<unsigned, const TargetRegisterClass*> Res;
15207 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15209 // Not found as a standard register?
15210 if (Res.second == 0) {
15211 // Map st(0) -> st(7) -> ST0
15212 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15213 tolower(Constraint[1]) == 's' &&
15214 tolower(Constraint[2]) == 't' &&
15215 Constraint[3] == '(' &&
15216 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15217 Constraint[5] == ')' &&
15218 Constraint[6] == '}') {
15220 Res.first = X86::ST0+Constraint[4]-'0';
15221 Res.second = X86::RFP80RegisterClass;
15225 // GCC allows "st(0)" to be called just plain "st".
15226 if (StringRef("{st}").equals_lower(Constraint)) {
15227 Res.first = X86::ST0;
15228 Res.second = X86::RFP80RegisterClass;
15233 if (StringRef("{flags}").equals_lower(Constraint)) {
15234 Res.first = X86::EFLAGS;
15235 Res.second = X86::CCRRegisterClass;
15239 // 'A' means EAX + EDX.
15240 if (Constraint == "A") {
15241 Res.first = X86::EAX;
15242 Res.second = X86::GR32_ADRegisterClass;
15248 // Otherwise, check to see if this is a register class of the wrong value
15249 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15250 // turn into {ax},{dx}.
15251 if (Res.second->hasType(VT))
15252 return Res; // Correct type already, nothing to do.
15254 // All of the single-register GCC register classes map their values onto
15255 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15256 // really want an 8-bit or 32-bit register, map to the appropriate register
15257 // class and return the appropriate register.
15258 if (Res.second == X86::GR16RegisterClass) {
15259 if (VT == MVT::i8) {
15260 unsigned DestReg = 0;
15261 switch (Res.first) {
15263 case X86::AX: DestReg = X86::AL; break;
15264 case X86::DX: DestReg = X86::DL; break;
15265 case X86::CX: DestReg = X86::CL; break;
15266 case X86::BX: DestReg = X86::BL; break;
15269 Res.first = DestReg;
15270 Res.second = X86::GR8RegisterClass;
15272 } else if (VT == MVT::i32) {
15273 unsigned DestReg = 0;
15274 switch (Res.first) {
15276 case X86::AX: DestReg = X86::EAX; break;
15277 case X86::DX: DestReg = X86::EDX; break;
15278 case X86::CX: DestReg = X86::ECX; break;
15279 case X86::BX: DestReg = X86::EBX; break;
15280 case X86::SI: DestReg = X86::ESI; break;
15281 case X86::DI: DestReg = X86::EDI; break;
15282 case X86::BP: DestReg = X86::EBP; break;
15283 case X86::SP: DestReg = X86::ESP; break;
15286 Res.first = DestReg;
15287 Res.second = X86::GR32RegisterClass;
15289 } else if (VT == MVT::i64) {
15290 unsigned DestReg = 0;
15291 switch (Res.first) {
15293 case X86::AX: DestReg = X86::RAX; break;
15294 case X86::DX: DestReg = X86::RDX; break;
15295 case X86::CX: DestReg = X86::RCX; break;
15296 case X86::BX: DestReg = X86::RBX; break;
15297 case X86::SI: DestReg = X86::RSI; break;
15298 case X86::DI: DestReg = X86::RDI; break;
15299 case X86::BP: DestReg = X86::RBP; break;
15300 case X86::SP: DestReg = X86::RSP; break;
15303 Res.first = DestReg;
15304 Res.second = X86::GR64RegisterClass;
15307 } else if (Res.second == X86::FR32RegisterClass ||
15308 Res.second == X86::FR64RegisterClass ||
15309 Res.second == X86::VR128RegisterClass) {
15310 // Handle references to XMM physical registers that got mapped into the
15311 // wrong class. This can happen with constraints like {xmm0} where the
15312 // target independent register mapper will just pick the first match it can
15313 // find, ignoring the required type.
15314 if (VT == MVT::f32)
15315 Res.second = X86::FR32RegisterClass;
15316 else if (VT == MVT::f64)
15317 Res.second = X86::FR64RegisterClass;
15318 else if (X86::VR128RegisterClass->hasType(VT))
15319 Res.second = X86::VR128RegisterClass;