1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
66 SelectionDAG &DAG, DebugLoc dl) {
67 EVT VT = Vec.getValueType();
68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
69 EVT ElVT = VT.getVectorElementType();
70 unsigned Factor = VT.getSizeInBits()/128;
71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
72 VT.getVectorNumElements()/Factor);
74 // Extract from UNDEF is UNDEF.
75 if (Vec.getOpcode() == ISD::UNDEF)
76 return DAG.getUNDEF(ResultVT);
78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
79 // we can match to VEXTRACTF128.
80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
82 // This is the index of the first element of the 128-bit chunk
84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
94 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
95 /// sets things up to match to an AVX VINSERTF128 instruction or a
96 /// simple superregister reference. Idx is an index in the 128 bits
97 /// we want. It need not be aligned to a 128-bit bounday. That makes
98 /// lowering INSERT_VECTOR_ELT operations easier.
99 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
100 unsigned IdxVal, SelectionDAG &DAG,
102 EVT VT = Vec.getValueType();
103 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
105 EVT ElVT = VT.getVectorElementType();
106 EVT ResultVT = Result.getValueType();
108 // Insert the relevant 128 bits.
109 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
111 // This is the index of the first element of the 128-bit chunk
113 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
116 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
117 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
122 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
123 /// instructions. This is used because creating CONCAT_VECTOR nodes of
124 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
125 /// large BUILD_VECTORS.
126 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
127 unsigned NumElems, SelectionDAG &DAG,
129 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
130 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
133 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
134 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
135 bool is64Bit = Subtarget->is64Bit();
137 if (Subtarget->isTargetEnvMacho()) {
139 return new X8664_MachoTargetObjectFile();
140 return new TargetLoweringObjectFileMachO();
143 if (Subtarget->isTargetELF())
144 return new TargetLoweringObjectFileELF();
145 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
146 return new TargetLoweringObjectFileCOFF();
147 llvm_unreachable("unknown subtarget type");
150 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
151 : TargetLowering(TM, createTLOF(TM)) {
152 Subtarget = &TM.getSubtarget<X86Subtarget>();
153 X86ScalarSSEf64 = Subtarget->hasSSE2();
154 X86ScalarSSEf32 = Subtarget->hasSSE1();
155 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
157 RegInfo = TM.getRegisterInfo();
158 TD = getTargetData();
160 // Set up the TargetLowering object.
161 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
163 // X86 is weird, it always uses i8 for shift amounts and setcc results.
164 setBooleanContents(ZeroOrOneBooleanContent);
165 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
166 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
168 // For 64-bit since we have so many registers use the ILP scheduler, for
169 // 32-bit code use the register pressure specific scheduling.
170 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
171 if (Subtarget->is64Bit())
172 setSchedulingPreference(Sched::ILP);
173 else if (Subtarget->isAtom())
174 setSchedulingPreference(Sched::Hybrid);
176 setSchedulingPreference(Sched::RegPressure);
177 setStackPointerRegisterToSaveRestore(X86StackPtr);
179 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
180 // Setup Windows compiler runtime calls.
181 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
182 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
183 setLibcallName(RTLIB::SREM_I64, "_allrem");
184 setLibcallName(RTLIB::UREM_I64, "_aullrem");
185 setLibcallName(RTLIB::MUL_I64, "_allmul");
186 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
187 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
188 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
189 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
190 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
192 // The _ftol2 runtime function has an unusual calling conv, which
193 // is modeled by a special pseudo-instruction.
194 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
195 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
196 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
197 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
200 if (Subtarget->isTargetDarwin()) {
201 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
202 setUseUnderscoreSetJmp(false);
203 setUseUnderscoreLongJmp(false);
204 } else if (Subtarget->isTargetMingw()) {
205 // MS runtime is weird: it exports _setjmp, but longjmp!
206 setUseUnderscoreSetJmp(true);
207 setUseUnderscoreLongJmp(false);
209 setUseUnderscoreSetJmp(true);
210 setUseUnderscoreLongJmp(true);
213 // Set up the register classes.
214 addRegisterClass(MVT::i8, &X86::GR8RegClass);
215 addRegisterClass(MVT::i16, &X86::GR16RegClass);
216 addRegisterClass(MVT::i32, &X86::GR32RegClass);
217 if (Subtarget->is64Bit())
218 addRegisterClass(MVT::i64, &X86::GR64RegClass);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
222 // We don't accept any truncstore of integer registers.
223 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
224 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
225 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
226 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
227 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
228 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
230 // SETOEQ and SETUNE require checking two conditions.
231 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
232 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
233 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
234 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
235 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
236 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
238 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
240 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
241 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
242 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
244 if (Subtarget->is64Bit()) {
245 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
247 } else if (!TM.Options.UseSoftFloat) {
248 // We have an algorithm for SSE2->double, and we turn this into a
249 // 64-bit FILD followed by conditional FADD for other targets.
250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
251 // We have an algorithm for SSE2, and we turn this into a 64-bit
252 // FILD for other targets.
253 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
256 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
258 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
259 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
261 if (!TM.Options.UseSoftFloat) {
262 // SSE has no i16 to fp conversion, only i32
263 if (X86ScalarSSEf32) {
264 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
265 // f32 and f64 cases are Legal, f80 case is not
266 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
276 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
277 // are Legal, f80 is custom lowered.
278 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
281 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
283 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
284 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
286 if (X86ScalarSSEf32) {
287 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
288 // f32 and f64 cases are Legal, f80 case is not
289 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
292 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
295 // Handle FP_TO_UINT by promoting the destination to a larger signed
297 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
298 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
299 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
301 if (Subtarget->is64Bit()) {
302 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
304 } else if (!TM.Options.UseSoftFloat) {
305 // Since AVX is a superset of SSE3, only check for SSE here.
306 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
307 // Expand FP_TO_UINT into a select.
308 // FIXME: We would like to use a Custom expander here eventually to do
309 // the optimal thing for SSE vs. the default expansion in the legalizer.
310 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
312 // With SSE3 we can use fisttpll to convert to a signed i64; without
313 // SSE, we're stuck with a fistpll.
314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
317 if (isTargetFTOL()) {
318 // Use the _ftol2 runtime function, which has a pseudo-instruction
319 // to handle its weird calling convention.
320 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
323 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
324 if (!X86ScalarSSEf64) {
325 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
326 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
327 if (Subtarget->is64Bit()) {
328 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
329 // Without SSE, i64->f64 goes through memory.
330 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
334 // Scalar integer divide and remainder are lowered to use operations that
335 // produce two results, to match the available instructions. This exposes
336 // the two-result form to trivial CSE, which is able to combine x/y and x%y
337 // into a single instruction.
339 // Scalar integer multiply-high is also lowered to use two-result
340 // operations, to match the available instructions. However, plain multiply
341 // (low) operations are left as Legal, as there are single-result
342 // instructions for this in x86. Using the two-result multiply instructions
343 // when both high and low results are needed must be arranged by dagcombine.
344 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
346 setOperationAction(ISD::MULHS, VT, Expand);
347 setOperationAction(ISD::MULHU, VT, Expand);
348 setOperationAction(ISD::SDIV, VT, Expand);
349 setOperationAction(ISD::UDIV, VT, Expand);
350 setOperationAction(ISD::SREM, VT, Expand);
351 setOperationAction(ISD::UREM, VT, Expand);
353 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
354 setOperationAction(ISD::ADDC, VT, Custom);
355 setOperationAction(ISD::ADDE, VT, Custom);
356 setOperationAction(ISD::SUBC, VT, Custom);
357 setOperationAction(ISD::SUBE, VT, Custom);
360 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
361 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
362 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
363 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
364 if (Subtarget->is64Bit())
365 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
366 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
369 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
370 setOperationAction(ISD::FREM , MVT::f32 , Expand);
371 setOperationAction(ISD::FREM , MVT::f64 , Expand);
372 setOperationAction(ISD::FREM , MVT::f80 , Expand);
373 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
375 // Promote the i8 variants and force them on up to i32 which has a shorter
377 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
378 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
379 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
380 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
381 if (Subtarget->hasBMI()) {
382 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
384 if (Subtarget->is64Bit())
385 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
387 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
388 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
393 if (Subtarget->hasLZCNT()) {
394 // When promoting the i8 variants, force them to i32 for a shorter
396 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
397 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
398 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
399 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
400 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
401 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
402 if (Subtarget->is64Bit())
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
405 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
406 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
407 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
411 if (Subtarget->is64Bit()) {
412 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
417 if (Subtarget->hasPOPCNT()) {
418 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
420 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
421 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
422 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
423 if (Subtarget->is64Bit())
424 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
427 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
428 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
430 // These should be promoted to a larger select which is supported.
431 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
432 // X86 wants to expand cmov itself.
433 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
434 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
435 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
436 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
437 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
438 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
439 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
440 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
441 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
442 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
443 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
444 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
445 if (Subtarget->is64Bit()) {
446 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
449 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
452 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
455 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
456 if (Subtarget->is64Bit())
457 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
458 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
459 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
460 if (Subtarget->is64Bit()) {
461 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
462 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
463 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
464 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
465 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
467 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
468 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
469 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
470 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
471 if (Subtarget->is64Bit()) {
472 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
473 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
474 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
477 if (Subtarget->hasSSE1())
478 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
480 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
481 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
483 // On X86 and X86-64, atomic operations are lowered to locked instructions.
484 // Locked instructions, in turn, have implicit fence semantics (all memory
485 // operations are flushed before issuing the locked instruction, and they
486 // are not buffered), so we can fold away the common pattern of
487 // fence-atomic-fence.
488 setShouldFoldAtomicFences(true);
490 // Expand certain atomics
491 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
493 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
494 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
495 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
498 if (!Subtarget->is64Bit()) {
499 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
500 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
501 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
502 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
503 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
509 if (Subtarget->hasCmpxchg16b()) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
513 // FIXME - use subtarget debug flags
514 if (!Subtarget->isTargetDarwin() &&
515 !Subtarget->isTargetELF() &&
516 !Subtarget->isTargetCygMing()) {
517 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
520 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
521 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
522 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
523 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
524 if (Subtarget->is64Bit()) {
525 setExceptionPointerRegister(X86::RAX);
526 setExceptionSelectorRegister(X86::RDX);
528 setExceptionPointerRegister(X86::EAX);
529 setExceptionSelectorRegister(X86::EDX);
531 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
532 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
534 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
535 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
537 setOperationAction(ISD::TRAP, MVT::Other, Legal);
539 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
540 setOperationAction(ISD::VASTART , MVT::Other, Custom);
541 setOperationAction(ISD::VAEND , MVT::Other, Expand);
542 if (Subtarget->is64Bit()) {
543 setOperationAction(ISD::VAARG , MVT::Other, Custom);
544 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
546 setOperationAction(ISD::VAARG , MVT::Other, Expand);
547 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
550 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
551 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
553 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
554 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
555 MVT::i64 : MVT::i32, Custom);
556 else if (TM.Options.EnableSegmentedStacks)
557 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
558 MVT::i64 : MVT::i32, Custom);
560 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
561 MVT::i64 : MVT::i32, Expand);
563 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
564 // f32 and f64 use SSE.
565 // Set up the FP register classes.
566 addRegisterClass(MVT::f32, &X86::FR32RegClass);
567 addRegisterClass(MVT::f64, &X86::FR64RegClass);
569 // Use ANDPD to simulate FABS.
570 setOperationAction(ISD::FABS , MVT::f64, Custom);
571 setOperationAction(ISD::FABS , MVT::f32, Custom);
573 // Use XORP to simulate FNEG.
574 setOperationAction(ISD::FNEG , MVT::f64, Custom);
575 setOperationAction(ISD::FNEG , MVT::f32, Custom);
577 // Use ANDPD and ORPD to simulate FCOPYSIGN.
578 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
579 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
581 // Lower this to FGETSIGNx86 plus an AND.
582 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
583 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
585 // We don't support sin/cos/fmod
586 setOperationAction(ISD::FSIN , MVT::f64, Expand);
587 setOperationAction(ISD::FCOS , MVT::f64, Expand);
588 setOperationAction(ISD::FSIN , MVT::f32, Expand);
589 setOperationAction(ISD::FCOS , MVT::f32, Expand);
591 // Expand FP immediates into loads from the stack, except for the special
593 addLegalFPImmediate(APFloat(+0.0)); // xorpd
594 addLegalFPImmediate(APFloat(+0.0f)); // xorps
595 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
596 // Use SSE for f32, x87 for f64.
597 // Set up the FP register classes.
598 addRegisterClass(MVT::f32, &X86::FR32RegClass);
599 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
601 // Use ANDPS to simulate FABS.
602 setOperationAction(ISD::FABS , MVT::f32, Custom);
604 // Use XORP to simulate FNEG.
605 setOperationAction(ISD::FNEG , MVT::f32, Custom);
607 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
609 // Use ANDPS and ORPS to simulate FCOPYSIGN.
610 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
611 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
613 // We don't support sin/cos/fmod
614 setOperationAction(ISD::FSIN , MVT::f32, Expand);
615 setOperationAction(ISD::FCOS , MVT::f32, Expand);
617 // Special cases we handle for FP constants.
618 addLegalFPImmediate(APFloat(+0.0f)); // xorps
619 addLegalFPImmediate(APFloat(+0.0)); // FLD0
620 addLegalFPImmediate(APFloat(+1.0)); // FLD1
621 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
622 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
624 if (!TM.Options.UnsafeFPMath) {
625 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
626 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
628 } else if (!TM.Options.UseSoftFloat) {
629 // f32 and f64 in x87.
630 // Set up the FP register classes.
631 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
632 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
634 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
635 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
636 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
637 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
639 if (!TM.Options.UnsafeFPMath) {
640 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
641 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
643 addLegalFPImmediate(APFloat(+0.0)); // FLD0
644 addLegalFPImmediate(APFloat(+1.0)); // FLD1
645 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
646 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
647 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
648 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
649 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
650 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
653 // We don't support FMA.
654 setOperationAction(ISD::FMA, MVT::f64, Expand);
655 setOperationAction(ISD::FMA, MVT::f32, Expand);
657 // Long double always uses X87.
658 if (!TM.Options.UseSoftFloat) {
659 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
660 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
661 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
663 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
664 addLegalFPImmediate(TmpFlt); // FLD0
666 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
669 APFloat TmpFlt2(+1.0);
670 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
672 addLegalFPImmediate(TmpFlt2); // FLD1
673 TmpFlt2.changeSign();
674 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
677 if (!TM.Options.UnsafeFPMath) {
678 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
679 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
682 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
683 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
684 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
685 setOperationAction(ISD::FRINT, MVT::f80, Expand);
686 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
687 setOperationAction(ISD::FMA, MVT::f80, Expand);
690 // Always use a library call for pow.
691 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
692 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
693 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
695 setOperationAction(ISD::FLOG, MVT::f80, Expand);
696 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
697 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
698 setOperationAction(ISD::FEXP, MVT::f80, Expand);
699 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
701 // First set operation action for all vector types to either promote
702 // (for widening) or expand (for scalarization). Then we will selectively
703 // turn on ones that can be effectively codegen'd.
704 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
705 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) {
706 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
721 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
723 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
724 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
758 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
763 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
764 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
765 setTruncStoreAction((MVT::SimpleValueType)VT,
766 (MVT::SimpleValueType)InnerVT, Expand);
767 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
768 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
769 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
773 // with -msoft-float, disable use of MMX as well.
774 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
775 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
776 // No operations on x86mmx supported, everything uses intrinsics.
779 // MMX-sized vectors (other than x86mmx) are expected to be expanded
780 // into smaller operations.
781 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
782 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
783 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
784 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
785 setOperationAction(ISD::AND, MVT::v8i8, Expand);
786 setOperationAction(ISD::AND, MVT::v4i16, Expand);
787 setOperationAction(ISD::AND, MVT::v2i32, Expand);
788 setOperationAction(ISD::AND, MVT::v1i64, Expand);
789 setOperationAction(ISD::OR, MVT::v8i8, Expand);
790 setOperationAction(ISD::OR, MVT::v4i16, Expand);
791 setOperationAction(ISD::OR, MVT::v2i32, Expand);
792 setOperationAction(ISD::OR, MVT::v1i64, Expand);
793 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
794 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
795 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
796 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
797 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
798 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
799 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
800 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
801 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
802 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
803 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
804 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
805 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
806 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
807 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
808 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
809 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
811 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
812 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
814 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
815 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
816 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
817 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
818 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
819 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
820 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
821 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
822 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
823 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
824 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
825 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
828 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
829 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
831 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
832 // registers cannot be used even for integer operations.
833 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
834 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
835 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
836 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
838 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
839 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
840 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
841 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
842 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
843 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
844 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
845 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
846 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
847 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
848 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
849 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
850 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
851 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
852 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
853 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
855 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
856 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
857 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
858 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
860 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
861 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
862 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
863 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
866 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
867 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
868 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
869 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
872 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
873 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
874 EVT VT = (MVT::SimpleValueType)i;
875 // Do not attempt to custom lower non-power-of-2 vectors
876 if (!isPowerOf2_32(VT.getVectorNumElements()))
878 // Do not attempt to custom lower non-128-bit vectors
879 if (!VT.is128BitVector())
881 setOperationAction(ISD::BUILD_VECTOR,
882 VT.getSimpleVT().SimpleTy, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE,
884 VT.getSimpleVT().SimpleTy, Custom);
885 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
886 VT.getSimpleVT().SimpleTy, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
890 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
892 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
893 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
894 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
896 if (Subtarget->is64Bit()) {
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
901 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
902 for (int i = MVT::v16i8; i != MVT::v2i64; i++) {
903 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
906 // Do not attempt to promote non-128-bit vectors
907 if (!VT.is128BitVector())
910 setOperationAction(ISD::AND, SVT, Promote);
911 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
912 setOperationAction(ISD::OR, SVT, Promote);
913 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
914 setOperationAction(ISD::XOR, SVT, Promote);
915 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
916 setOperationAction(ISD::LOAD, SVT, Promote);
917 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
918 setOperationAction(ISD::SELECT, SVT, Promote);
919 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
922 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
924 // Custom lower v2i64 and v2f64 selects.
925 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
926 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
927 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
928 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
930 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
931 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
934 if (Subtarget->hasSSE41()) {
935 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
936 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
937 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
938 setOperationAction(ISD::FRINT, MVT::f32, Legal);
939 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
940 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
941 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
942 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
943 setOperationAction(ISD::FRINT, MVT::f64, Legal);
944 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
946 // FIXME: Do we need to handle scalar-to-vector here?
947 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
949 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
950 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
951 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
952 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
955 // i8 and i16 vectors are custom , because the source register and source
956 // source memory operand types are not the same width. f32 vectors are
957 // custom since the immediate controlling the insert encodes additional
959 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
960 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
961 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
962 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
964 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
965 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
969 // FIXME: these should be Legal but thats only for the case where
970 // the index is constant. For now custom expand to deal with that.
971 if (Subtarget->is64Bit()) {
972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
973 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
977 if (Subtarget->hasSSE2()) {
978 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
979 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
981 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
982 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
984 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
985 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
987 if (Subtarget->hasAVX2()) {
988 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
989 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
991 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
992 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
994 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
996 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
997 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
999 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1000 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1002 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1006 if (Subtarget->hasSSE42())
1007 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1009 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1010 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1011 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1012 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1013 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1014 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1015 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1017 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1018 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1019 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1021 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1022 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1023 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1024 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1025 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1028 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1029 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1030 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1031 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1032 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1035 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1036 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1037 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1039 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1040 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1041 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1042 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1046 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1047 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1049 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1052 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1053 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1055 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1056 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1058 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1060 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1061 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1062 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1064 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1069 if (Subtarget->hasAVX2()) {
1070 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1071 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1072 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1073 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1075 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1076 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1077 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1078 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1080 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1081 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1082 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1083 // Don't lower v32i8 because there is no 128-bit byte mul
1085 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1087 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1088 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1090 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1091 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1093 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1095 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1096 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1097 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1098 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1100 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1101 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1102 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1103 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1105 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1106 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1107 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1108 // Don't lower v32i8 because there is no 128-bit byte mul
1110 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1111 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1113 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1114 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1116 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1119 // Custom lower several nodes for 256-bit types.
1120 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1121 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1122 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1125 // Extract subvector is special because the value type
1126 // (result) is 128-bit but the source is 256-bit wide.
1127 if (VT.is128BitVector())
1128 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1130 // Do not attempt to custom lower other non-256-bit vectors
1131 if (!VT.is256BitVector())
1134 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1135 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1137 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1138 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1139 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1142 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1143 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1144 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1147 // Do not attempt to promote non-256-bit vectors
1148 if (!VT.is256BitVector())
1151 setOperationAction(ISD::AND, SVT, Promote);
1152 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1153 setOperationAction(ISD::OR, SVT, Promote);
1154 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1155 setOperationAction(ISD::XOR, SVT, Promote);
1156 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1157 setOperationAction(ISD::LOAD, SVT, Promote);
1158 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1159 setOperationAction(ISD::SELECT, SVT, Promote);
1160 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1164 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1165 // of this type with custom code.
1166 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1167 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1168 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1172 // We want to custom lower some of our intrinsics.
1173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1176 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1177 // handle type legalization for these operations here.
1179 // FIXME: We really should do custom legalization for addition and
1180 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1181 // than generic legalization for 64-bit multiplication-with-overflow, though.
1182 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1183 // Add/Sub/Mul with overflow operations are custom lowered.
1185 setOperationAction(ISD::SADDO, VT, Custom);
1186 setOperationAction(ISD::UADDO, VT, Custom);
1187 setOperationAction(ISD::SSUBO, VT, Custom);
1188 setOperationAction(ISD::USUBO, VT, Custom);
1189 setOperationAction(ISD::SMULO, VT, Custom);
1190 setOperationAction(ISD::UMULO, VT, Custom);
1193 // There are no 8-bit 3-address imul/mul instructions
1194 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1195 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1197 if (!Subtarget->is64Bit()) {
1198 // These libcalls are not available in 32-bit.
1199 setLibcallName(RTLIB::SHL_I128, 0);
1200 setLibcallName(RTLIB::SRL_I128, 0);
1201 setLibcallName(RTLIB::SRA_I128, 0);
1204 // We have target-specific dag combine patterns for the following nodes:
1205 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1206 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1207 setTargetDAGCombine(ISD::VSELECT);
1208 setTargetDAGCombine(ISD::SELECT);
1209 setTargetDAGCombine(ISD::SHL);
1210 setTargetDAGCombine(ISD::SRA);
1211 setTargetDAGCombine(ISD::SRL);
1212 setTargetDAGCombine(ISD::OR);
1213 setTargetDAGCombine(ISD::AND);
1214 setTargetDAGCombine(ISD::ADD);
1215 setTargetDAGCombine(ISD::FADD);
1216 setTargetDAGCombine(ISD::FSUB);
1217 setTargetDAGCombine(ISD::SUB);
1218 setTargetDAGCombine(ISD::LOAD);
1219 setTargetDAGCombine(ISD::STORE);
1220 setTargetDAGCombine(ISD::ZERO_EXTEND);
1221 setTargetDAGCombine(ISD::ANY_EXTEND);
1222 setTargetDAGCombine(ISD::SIGN_EXTEND);
1223 setTargetDAGCombine(ISD::TRUNCATE);
1224 setTargetDAGCombine(ISD::UINT_TO_FP);
1225 setTargetDAGCombine(ISD::SINT_TO_FP);
1226 setTargetDAGCombine(ISD::SETCC);
1227 setTargetDAGCombine(ISD::FP_TO_SINT);
1228 if (Subtarget->is64Bit())
1229 setTargetDAGCombine(ISD::MUL);
1230 if (Subtarget->hasBMI())
1231 setTargetDAGCombine(ISD::XOR);
1233 computeRegisterProperties();
1235 // On Darwin, -Os means optimize for size without hurting performance,
1236 // do not reduce the limit.
1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1243 setPrefLoopAlignment(4); // 2^4 bytes.
1244 benefitFromCodePlacementOpt = true;
1246 setPrefFunctionAlignment(4); // 2^4 bytes.
1250 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1251 if (!VT.isVector()) return MVT::i8;
1252 return VT.changeVectorElementTypeToInteger();
1256 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1257 /// the desired ByVal argument alignment.
1258 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1262 if (VTy->getBitWidth() == 128)
1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1265 unsigned EltAlign = 0;
1266 getMaxByValAlign(ATy->getElementType(), EltAlign);
1267 if (EltAlign > MaxAlign)
1268 MaxAlign = EltAlign;
1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1271 unsigned EltAlign = 0;
1272 getMaxByValAlign(STy->getElementType(i), EltAlign);
1273 if (EltAlign > MaxAlign)
1274 MaxAlign = EltAlign;
1281 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1282 /// function arguments in the caller parameter area. For X86, aggregates
1283 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1284 /// are at 4-byte boundaries.
1285 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1286 if (Subtarget->is64Bit()) {
1287 // Max of 8 and alignment of type.
1288 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1295 if (Subtarget->hasSSE1())
1296 getMaxByValAlign(Ty, Align);
1300 /// getOptimalMemOpType - Returns the target specific optimal type for load
1301 /// and store operations as a result of memset, memcpy, and memmove
1302 /// lowering. If DstAlign is zero that means it's safe to destination
1303 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1304 /// means there isn't a need to check it against alignment requirement,
1305 /// probably because the source does not need to be loaded. If
1306 /// 'IsZeroVal' is true, that means it's safe to return a
1307 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1308 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1309 /// constant so it does not need to be loaded.
1310 /// It returns EVT::Other if the type should be determined using generic
1311 /// target-independent logic.
1313 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1314 unsigned DstAlign, unsigned SrcAlign,
1317 MachineFunction &MF) const {
1318 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1319 // linux. This is because the stack realignment code can't handle certain
1320 // cases like PR2962. This should be removed when PR2962 is fixed.
1321 const Function *F = MF.getFunction();
1323 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1325 (Subtarget->isUnalignedMemAccessFast() ||
1326 ((DstAlign == 0 || DstAlign >= 16) &&
1327 (SrcAlign == 0 || SrcAlign >= 16))) &&
1328 Subtarget->getStackAlignment() >= 16) {
1329 if (Subtarget->getStackAlignment() >= 32) {
1330 if (Subtarget->hasAVX2())
1332 if (Subtarget->hasAVX())
1335 if (Subtarget->hasSSE2())
1337 if (Subtarget->hasSSE1())
1339 } else if (!MemcpyStrSrc && Size >= 8 &&
1340 !Subtarget->is64Bit() &&
1341 Subtarget->getStackAlignment() >= 8 &&
1342 Subtarget->hasSSE2()) {
1343 // Do not use f64 to lower memcpy if source is string constant. It's
1344 // better to use i32 to avoid the loads.
1348 if (Subtarget->is64Bit() && Size >= 8)
1353 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1354 /// current function. The returned value is a member of the
1355 /// MachineJumpTableInfo::JTEntryKind enum.
1356 unsigned X86TargetLowering::getJumpTableEncoding() const {
1357 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1359 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1360 Subtarget->isPICStyleGOT())
1361 return MachineJumpTableInfo::EK_Custom32;
1363 // Otherwise, use the normal jump table encoding heuristics.
1364 return TargetLowering::getJumpTableEncoding();
1368 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1369 const MachineBasicBlock *MBB,
1370 unsigned uid,MCContext &Ctx) const{
1371 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1372 Subtarget->isPICStyleGOT());
1373 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1375 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1376 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1379 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1381 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1382 SelectionDAG &DAG) const {
1383 if (!Subtarget->is64Bit())
1384 // This doesn't have DebugLoc associated with it, but is not really the
1385 // same as a Register.
1386 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1390 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1391 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1393 const MCExpr *X86TargetLowering::
1394 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1395 MCContext &Ctx) const {
1396 // X86-64 uses RIP relative addressing based on the jump table label.
1397 if (Subtarget->isPICStyleRIPRel())
1398 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1400 // Otherwise, the reference is relative to the PIC base.
1401 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1404 // FIXME: Why this routine is here? Move to RegInfo!
1405 std::pair<const TargetRegisterClass*, uint8_t>
1406 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1407 const TargetRegisterClass *RRC = 0;
1409 switch (VT.getSimpleVT().SimpleTy) {
1411 return TargetLowering::findRepresentativeClass(VT);
1412 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1413 RRC = Subtarget->is64Bit() ?
1414 (const TargetRegisterClass*)&X86::GR64RegClass :
1415 (const TargetRegisterClass*)&X86::GR32RegClass;
1418 RRC = &X86::VR64RegClass;
1420 case MVT::f32: case MVT::f64:
1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1422 case MVT::v4f32: case MVT::v2f64:
1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1425 RRC = &X86::VR128RegClass;
1428 return std::make_pair(RRC, Cost);
1431 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1432 unsigned &Offset) const {
1433 if (!Subtarget->isTargetLinux())
1436 if (Subtarget->is64Bit()) {
1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1452 //===----------------------------------------------------------------------===//
1453 // Return Value Calling Convention Implementation
1454 //===----------------------------------------------------------------------===//
1456 #include "X86GenCallingConv.inc"
1459 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1460 MachineFunction &MF, bool isVarArg,
1461 const SmallVectorImpl<ISD::OutputArg> &Outs,
1462 LLVMContext &Context) const {
1463 SmallVector<CCValAssign, 16> RVLocs;
1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1466 return CCInfo.CheckReturn(Outs, RetCC_X86);
1470 X86TargetLowering::LowerReturn(SDValue Chain,
1471 CallingConv::ID CallConv, bool isVarArg,
1472 const SmallVectorImpl<ISD::OutputArg> &Outs,
1473 const SmallVectorImpl<SDValue> &OutVals,
1474 DebugLoc dl, SelectionDAG &DAG) const {
1475 MachineFunction &MF = DAG.getMachineFunction();
1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1478 SmallVector<CCValAssign, 16> RVLocs;
1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1480 RVLocs, *DAG.getContext());
1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1483 // Add the regs to the liveout set for the function.
1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1485 for (unsigned i = 0; i != RVLocs.size(); ++i)
1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1487 MRI.addLiveOut(RVLocs[i].getLocReg());
1491 SmallVector<SDValue, 6> RetOps;
1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1493 // Operand #1 = Bytes To Pop
1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1497 // Copy the result values into the output registers.
1498 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1499 CCValAssign &VA = RVLocs[i];
1500 assert(VA.isRegLoc() && "Can only return in registers!");
1501 SDValue ValToCopy = OutVals[i];
1502 EVT ValVT = ValToCopy.getValueType();
1504 // If this is x86-64, and we disabled SSE, we can't return FP values,
1505 // or SSE or MMX vectors.
1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1509 report_fatal_error("SSE register return with SSE disabled");
1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1512 // llvm-gcc has never done it right and no one has noticed, so this
1513 // should be OK for now.
1514 if (ValVT == MVT::f64 &&
1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1516 report_fatal_error("SSE2 register return with SSE2 disabled");
1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1519 // the RET instruction and handled by the FP Stackifier.
1520 if (VA.getLocReg() == X86::ST0 ||
1521 VA.getLocReg() == X86::ST1) {
1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1523 // change the value to the FP stack register class.
1524 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1526 RetOps.push_back(ValToCopy);
1527 // Don't emit a copytoreg.
1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1532 // which is returned in RAX / RDX.
1533 if (Subtarget->is64Bit()) {
1534 if (ValVT == MVT::x86mmx) {
1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1539 // If we don't have SSE2 available, convert to v4f32 so the generated
1540 // register is legal.
1541 if (!Subtarget->hasSSE2())
1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1548 Flag = Chain.getValue(1);
1551 // The x86-64 ABI for returning structs by value requires that we copy
1552 // the sret argument into %rax for the return. We saved the argument into
1553 // a virtual register in the entry block, so now we copy the value out
1555 if (Subtarget->is64Bit() &&
1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1557 MachineFunction &MF = DAG.getMachineFunction();
1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1559 unsigned Reg = FuncInfo->getSRetReturnReg();
1561 "SRetReturnReg should have been set in LowerFormalArguments().");
1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1565 Flag = Chain.getValue(1);
1567 // RAX now acts like a return value.
1568 MRI.addLiveOut(X86::RAX);
1571 RetOps[0] = Chain; // Update chain.
1573 // Add the flag if we have it.
1575 RetOps.push_back(Flag);
1577 return DAG.getNode(X86ISD::RET_FLAG, dl,
1578 MVT::Other, &RetOps[0], RetOps.size());
1581 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1582 if (N->getNumValues() != 1)
1584 if (!N->hasNUsesOfValue(1, 0))
1587 SDValue TCChain = Chain;
1588 SDNode *Copy = *N->use_begin();
1589 if (Copy->getOpcode() == ISD::CopyToReg) {
1590 // If the copy has a glue operand, we conservatively assume it isn't safe to
1591 // perform a tail call.
1592 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1594 TCChain = Copy->getOperand(0);
1595 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1598 bool HasRet = false;
1599 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1601 if (UI->getOpcode() != X86ISD::RET_FLAG)
1614 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1615 ISD::NodeType ExtendKind) const {
1617 // TODO: Is this also valid on 32-bit?
1618 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1619 ReturnMVT = MVT::i8;
1621 ReturnMVT = MVT::i32;
1623 EVT MinVT = getRegisterType(Context, ReturnMVT);
1624 return VT.bitsLT(MinVT) ? MinVT : VT;
1627 /// LowerCallResult - Lower the result values of a call into the
1628 /// appropriate copies out of appropriate physical registers.
1631 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1632 CallingConv::ID CallConv, bool isVarArg,
1633 const SmallVectorImpl<ISD::InputArg> &Ins,
1634 DebugLoc dl, SelectionDAG &DAG,
1635 SmallVectorImpl<SDValue> &InVals) const {
1637 // Assign locations to each value returned by this call.
1638 SmallVector<CCValAssign, 16> RVLocs;
1639 bool Is64Bit = Subtarget->is64Bit();
1640 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1641 getTargetMachine(), RVLocs, *DAG.getContext());
1642 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1644 // Copy all of the result registers out of their specified physreg.
1645 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1646 CCValAssign &VA = RVLocs[i];
1647 EVT CopyVT = VA.getValVT();
1649 // If this is x86-64, and we disabled SSE, we can't return FP values
1650 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1651 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1652 report_fatal_error("SSE register return with SSE disabled");
1657 // If this is a call to a function that returns an fp value on the floating
1658 // point stack, we must guarantee the the value is popped from the stack, so
1659 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1660 // if the return value is not used. We use the FpPOP_RETVAL instruction
1662 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1663 // If we prefer to use the value in xmm registers, copy it out as f80 and
1664 // use a truncate to move it from fp stack reg to xmm reg.
1665 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1666 SDValue Ops[] = { Chain, InFlag };
1667 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1668 MVT::Other, MVT::Glue, Ops, 2), 1);
1669 Val = Chain.getValue(0);
1671 // Round the f80 to the right size, which also moves it to the appropriate
1673 if (CopyVT != VA.getValVT())
1674 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1675 // This truncation won't change the value.
1676 DAG.getIntPtrConstant(1));
1678 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1679 CopyVT, InFlag).getValue(1);
1680 Val = Chain.getValue(0);
1682 InFlag = Chain.getValue(2);
1683 InVals.push_back(Val);
1690 //===----------------------------------------------------------------------===//
1691 // C & StdCall & Fast Calling Convention implementation
1692 //===----------------------------------------------------------------------===//
1693 // StdCall calling convention seems to be standard for many Windows' API
1694 // routines and around. It differs from C calling convention just a little:
1695 // callee should clean up the stack, not caller. Symbols should be also
1696 // decorated in some fancy way :) It doesn't support any vector arguments.
1697 // For info on fast calling convention see Fast Calling Convention (tail call)
1698 // implementation LowerX86_32FastCCCallTo.
1700 /// CallIsStructReturn - Determines whether a call uses struct return
1702 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1706 return Outs[0].Flags.isSRet();
1709 /// ArgsAreStructReturn - Determines whether a function uses struct
1710 /// return semantics.
1712 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1716 return Ins[0].Flags.isSRet();
1719 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1720 /// by "Src" to address "Dst" with size and alignment information specified by
1721 /// the specific parameter attribute. The copy will be passed as a byval
1722 /// function parameter.
1724 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1725 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1727 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1729 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1730 /*isVolatile*/false, /*AlwaysInline=*/true,
1731 MachinePointerInfo(), MachinePointerInfo());
1734 /// IsTailCallConvention - Return true if the calling convention is one that
1735 /// supports tail call optimization.
1736 static bool IsTailCallConvention(CallingConv::ID CC) {
1737 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1740 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1741 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1745 CallingConv::ID CalleeCC = CS.getCallingConv();
1746 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1752 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1753 /// a tailcall target by changing its ABI.
1754 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1755 bool GuaranteedTailCallOpt) {
1756 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1760 X86TargetLowering::LowerMemArgument(SDValue Chain,
1761 CallingConv::ID CallConv,
1762 const SmallVectorImpl<ISD::InputArg> &Ins,
1763 DebugLoc dl, SelectionDAG &DAG,
1764 const CCValAssign &VA,
1765 MachineFrameInfo *MFI,
1767 // Create the nodes corresponding to a load from this parameter slot.
1768 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1769 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1770 getTargetMachine().Options.GuaranteedTailCallOpt);
1771 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1774 // If value is passed by pointer we have address passed instead of the value
1776 if (VA.getLocInfo() == CCValAssign::Indirect)
1777 ValVT = VA.getLocVT();
1779 ValVT = VA.getValVT();
1781 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1782 // changed with more analysis.
1783 // In case of tail call optimization mark all arguments mutable. Since they
1784 // could be overwritten by lowering of arguments in case of a tail call.
1785 if (Flags.isByVal()) {
1786 unsigned Bytes = Flags.getByValSize();
1787 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1788 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1789 return DAG.getFrameIndex(FI, getPointerTy());
1791 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1792 VA.getLocMemOffset(), isImmutable);
1793 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1794 return DAG.getLoad(ValVT, dl, Chain, FIN,
1795 MachinePointerInfo::getFixedStack(FI),
1796 false, false, false, 0);
1801 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1802 CallingConv::ID CallConv,
1804 const SmallVectorImpl<ISD::InputArg> &Ins,
1807 SmallVectorImpl<SDValue> &InVals)
1809 MachineFunction &MF = DAG.getMachineFunction();
1810 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1812 const Function* Fn = MF.getFunction();
1813 if (Fn->hasExternalLinkage() &&
1814 Subtarget->isTargetCygMing() &&
1815 Fn->getName() == "main")
1816 FuncInfo->setForceFramePointer(true);
1818 MachineFrameInfo *MFI = MF.getFrameInfo();
1819 bool Is64Bit = Subtarget->is64Bit();
1820 bool IsWindows = Subtarget->isTargetWindows();
1821 bool IsWin64 = Subtarget->isTargetWin64();
1823 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1824 "Var args not supported with calling convention fastcc or ghc");
1826 // Assign locations to all of the incoming arguments.
1827 SmallVector<CCValAssign, 16> ArgLocs;
1828 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1829 ArgLocs, *DAG.getContext());
1831 // Allocate shadow area for Win64
1833 CCInfo.AllocateStack(32, 8);
1836 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1838 unsigned LastVal = ~0U;
1840 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1841 CCValAssign &VA = ArgLocs[i];
1842 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1844 assert(VA.getValNo() != LastVal &&
1845 "Don't support value assigned to multiple locs yet");
1847 LastVal = VA.getValNo();
1849 if (VA.isRegLoc()) {
1850 EVT RegVT = VA.getLocVT();
1851 const TargetRegisterClass *RC;
1852 if (RegVT == MVT::i32)
1853 RC = &X86::GR32RegClass;
1854 else if (Is64Bit && RegVT == MVT::i64)
1855 RC = &X86::GR64RegClass;
1856 else if (RegVT == MVT::f32)
1857 RC = &X86::FR32RegClass;
1858 else if (RegVT == MVT::f64)
1859 RC = &X86::FR64RegClass;
1860 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1861 RC = &X86::VR256RegClass;
1862 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1863 RC = &X86::VR128RegClass;
1864 else if (RegVT == MVT::x86mmx)
1865 RC = &X86::VR64RegClass;
1867 llvm_unreachable("Unknown argument type!");
1869 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1870 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1872 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1873 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1875 if (VA.getLocInfo() == CCValAssign::SExt)
1876 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1877 DAG.getValueType(VA.getValVT()));
1878 else if (VA.getLocInfo() == CCValAssign::ZExt)
1879 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1880 DAG.getValueType(VA.getValVT()));
1881 else if (VA.getLocInfo() == CCValAssign::BCvt)
1882 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1884 if (VA.isExtInLoc()) {
1885 // Handle MMX values passed in XMM regs.
1886 if (RegVT.isVector()) {
1887 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1890 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1893 assert(VA.isMemLoc());
1894 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1897 // If value is passed via pointer - do a load.
1898 if (VA.getLocInfo() == CCValAssign::Indirect)
1899 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1900 MachinePointerInfo(), false, false, false, 0);
1902 InVals.push_back(ArgValue);
1905 // The x86-64 ABI for returning structs by value requires that we copy
1906 // the sret argument into %rax for the return. Save the argument into
1907 // a virtual register so that we can access it from the return points.
1908 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1909 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1910 unsigned Reg = FuncInfo->getSRetReturnReg();
1912 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1913 FuncInfo->setSRetReturnReg(Reg);
1915 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1916 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1919 unsigned StackSize = CCInfo.getNextStackOffset();
1920 // Align stack specially for tail calls.
1921 if (FuncIsMadeTailCallSafe(CallConv,
1922 MF.getTarget().Options.GuaranteedTailCallOpt))
1923 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1925 // If the function takes variable number of arguments, make a frame index for
1926 // the start of the first vararg value... for expansion of llvm.va_start.
1928 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1929 CallConv != CallingConv::X86_ThisCall)) {
1930 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1933 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1935 // FIXME: We should really autogenerate these arrays
1936 static const uint16_t GPR64ArgRegsWin64[] = {
1937 X86::RCX, X86::RDX, X86::R8, X86::R9
1939 static const uint16_t GPR64ArgRegs64Bit[] = {
1940 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1942 static const uint16_t XMMArgRegs64Bit[] = {
1943 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1944 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1946 const uint16_t *GPR64ArgRegs;
1947 unsigned NumXMMRegs = 0;
1950 // The XMM registers which might contain var arg parameters are shadowed
1951 // in their paired GPR. So we only need to save the GPR to their home
1953 TotalNumIntRegs = 4;
1954 GPR64ArgRegs = GPR64ArgRegsWin64;
1956 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1957 GPR64ArgRegs = GPR64ArgRegs64Bit;
1959 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1962 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1965 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1966 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1967 "SSE register cannot be used when SSE is disabled!");
1968 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1969 NoImplicitFloatOps) &&
1970 "SSE register cannot be used when SSE is disabled!");
1971 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1972 !Subtarget->hasSSE1())
1973 // Kernel mode asks for SSE to be disabled, so don't push them
1975 TotalNumXMMRegs = 0;
1978 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1979 // Get to the caller-allocated home save location. Add 8 to account
1980 // for the return address.
1981 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1982 FuncInfo->setRegSaveFrameIndex(
1983 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1984 // Fixup to set vararg frame on shadow area (4 x i64).
1986 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1988 // For X86-64, if there are vararg parameters that are passed via
1989 // registers, then we must store them to their spots on the stack so
1990 // they may be loaded by deferencing the result of va_next.
1991 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1992 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1993 FuncInfo->setRegSaveFrameIndex(
1994 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1998 // Store the integer parameter registers.
1999 SmallVector<SDValue, 8> MemOps;
2000 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2002 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2003 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2004 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2005 DAG.getIntPtrConstant(Offset));
2006 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2007 &X86::GR64RegClass);
2008 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2010 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2011 MachinePointerInfo::getFixedStack(
2012 FuncInfo->getRegSaveFrameIndex(), Offset),
2014 MemOps.push_back(Store);
2018 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2019 // Now store the XMM (fp + vector) parameter registers.
2020 SmallVector<SDValue, 11> SaveXMMOps;
2021 SaveXMMOps.push_back(Chain);
2023 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2024 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2025 SaveXMMOps.push_back(ALVal);
2027 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2028 FuncInfo->getRegSaveFrameIndex()));
2029 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2030 FuncInfo->getVarArgsFPOffset()));
2032 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2033 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2034 &X86::VR128RegClass);
2035 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2036 SaveXMMOps.push_back(Val);
2038 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2040 &SaveXMMOps[0], SaveXMMOps.size()));
2043 if (!MemOps.empty())
2044 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2045 &MemOps[0], MemOps.size());
2049 // Some CCs need callee pop.
2050 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2051 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2052 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2054 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2055 // If this is an sret function, the return should pop the hidden pointer.
2056 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2057 ArgsAreStructReturn(Ins))
2058 FuncInfo->setBytesToPopOnReturn(4);
2062 // RegSaveFrameIndex is X86-64 only.
2063 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2064 if (CallConv == CallingConv::X86_FastCall ||
2065 CallConv == CallingConv::X86_ThisCall)
2066 // fastcc functions can't have varargs.
2067 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2070 FuncInfo->setArgumentStackSize(StackSize);
2076 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2077 SDValue StackPtr, SDValue Arg,
2078 DebugLoc dl, SelectionDAG &DAG,
2079 const CCValAssign &VA,
2080 ISD::ArgFlagsTy Flags) const {
2081 unsigned LocMemOffset = VA.getLocMemOffset();
2082 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2083 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2084 if (Flags.isByVal())
2085 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2087 return DAG.getStore(Chain, dl, Arg, PtrOff,
2088 MachinePointerInfo::getStack(LocMemOffset),
2092 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2093 /// optimization is performed and it is required.
2095 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2096 SDValue &OutRetAddr, SDValue Chain,
2097 bool IsTailCall, bool Is64Bit,
2098 int FPDiff, DebugLoc dl) const {
2099 // Adjust the Return address stack slot.
2100 EVT VT = getPointerTy();
2101 OutRetAddr = getReturnAddressFrameIndex(DAG);
2103 // Load the "old" Return address.
2104 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2105 false, false, false, 0);
2106 return SDValue(OutRetAddr.getNode(), 1);
2109 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2110 /// optimization is performed and it is required (FPDiff!=0).
2112 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2113 SDValue Chain, SDValue RetAddrFrIdx,
2114 bool Is64Bit, int FPDiff, DebugLoc dl) {
2115 // Store the return address to the appropriate stack slot.
2116 if (!FPDiff) return Chain;
2117 // Calculate the new stack slot for the return address.
2118 int SlotSize = Is64Bit ? 8 : 4;
2119 int NewReturnAddrFI =
2120 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2121 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2122 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2123 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2124 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2130 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2131 CallingConv::ID CallConv, bool isVarArg,
2132 bool doesNotRet, bool &isTailCall,
2133 const SmallVectorImpl<ISD::OutputArg> &Outs,
2134 const SmallVectorImpl<SDValue> &OutVals,
2135 const SmallVectorImpl<ISD::InputArg> &Ins,
2136 DebugLoc dl, SelectionDAG &DAG,
2137 SmallVectorImpl<SDValue> &InVals) const {
2138 MachineFunction &MF = DAG.getMachineFunction();
2139 bool Is64Bit = Subtarget->is64Bit();
2140 bool IsWin64 = Subtarget->isTargetWin64();
2141 bool IsWindows = Subtarget->isTargetWindows();
2142 bool IsStructRet = CallIsStructReturn(Outs);
2143 bool IsSibcall = false;
2145 if (MF.getTarget().Options.DisableTailCalls)
2149 // Check if it's really possible to do a tail call.
2150 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2151 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2152 Outs, OutVals, Ins, DAG);
2154 // Sibcalls are automatically detected tailcalls which do not require
2156 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2163 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2164 "Var args not supported with calling convention fastcc or ghc");
2166 // Analyze operands of the call, assigning locations to each operand.
2167 SmallVector<CCValAssign, 16> ArgLocs;
2168 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2169 ArgLocs, *DAG.getContext());
2171 // Allocate shadow area for Win64
2173 CCInfo.AllocateStack(32, 8);
2176 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2178 // Get a count of how many bytes are to be pushed on the stack.
2179 unsigned NumBytes = CCInfo.getNextStackOffset();
2181 // This is a sibcall. The memory operands are available in caller's
2182 // own caller's stack.
2184 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2185 IsTailCallConvention(CallConv))
2186 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2189 if (isTailCall && !IsSibcall) {
2190 // Lower arguments at fp - stackoffset + fpdiff.
2191 unsigned NumBytesCallerPushed =
2192 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2193 FPDiff = NumBytesCallerPushed - NumBytes;
2195 // Set the delta of movement of the returnaddr stackslot.
2196 // But only set if delta is greater than previous delta.
2197 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2198 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2202 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2204 SDValue RetAddrFrIdx;
2205 // Load return address for tail calls.
2206 if (isTailCall && FPDiff)
2207 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2208 Is64Bit, FPDiff, dl);
2210 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2211 SmallVector<SDValue, 8> MemOpChains;
2214 // Walk the register/memloc assignments, inserting copies/loads. In the case
2215 // of tail call optimization arguments are handle later.
2216 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2217 CCValAssign &VA = ArgLocs[i];
2218 EVT RegVT = VA.getLocVT();
2219 SDValue Arg = OutVals[i];
2220 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2221 bool isByVal = Flags.isByVal();
2223 // Promote the value if needed.
2224 switch (VA.getLocInfo()) {
2225 default: llvm_unreachable("Unknown loc info!");
2226 case CCValAssign::Full: break;
2227 case CCValAssign::SExt:
2228 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2230 case CCValAssign::ZExt:
2231 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2233 case CCValAssign::AExt:
2234 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2235 // Special case: passing MMX values in XMM registers.
2236 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2237 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2238 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2240 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2242 case CCValAssign::BCvt:
2243 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2245 case CCValAssign::Indirect: {
2246 // Store the argument.
2247 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2248 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2249 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2250 MachinePointerInfo::getFixedStack(FI),
2257 if (VA.isRegLoc()) {
2258 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2259 if (isVarArg && IsWin64) {
2260 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2261 // shadow reg if callee is a varargs function.
2262 unsigned ShadowReg = 0;
2263 switch (VA.getLocReg()) {
2264 case X86::XMM0: ShadowReg = X86::RCX; break;
2265 case X86::XMM1: ShadowReg = X86::RDX; break;
2266 case X86::XMM2: ShadowReg = X86::R8; break;
2267 case X86::XMM3: ShadowReg = X86::R9; break;
2270 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2272 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2273 assert(VA.isMemLoc());
2274 if (StackPtr.getNode() == 0)
2275 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2276 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2277 dl, DAG, VA, Flags));
2281 if (!MemOpChains.empty())
2282 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2283 &MemOpChains[0], MemOpChains.size());
2285 // Build a sequence of copy-to-reg nodes chained together with token chain
2286 // and flag operands which copy the outgoing args into registers.
2288 // Tail call byval lowering might overwrite argument registers so in case of
2289 // tail call optimization the copies to registers are lowered later.
2291 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2292 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2293 RegsToPass[i].second, InFlag);
2294 InFlag = Chain.getValue(1);
2297 if (Subtarget->isPICStyleGOT()) {
2298 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2301 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2302 DAG.getNode(X86ISD::GlobalBaseReg,
2303 DebugLoc(), getPointerTy()),
2305 InFlag = Chain.getValue(1);
2307 // If we are tail calling and generating PIC/GOT style code load the
2308 // address of the callee into ECX. The value in ecx is used as target of
2309 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2310 // for tail calls on PIC/GOT architectures. Normally we would just put the
2311 // address of GOT into ebx and then call target@PLT. But for tail calls
2312 // ebx would be restored (since ebx is callee saved) before jumping to the
2315 // Note: The actual moving to ECX is done further down.
2316 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2317 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2318 !G->getGlobal()->hasProtectedVisibility())
2319 Callee = LowerGlobalAddress(Callee, DAG);
2320 else if (isa<ExternalSymbolSDNode>(Callee))
2321 Callee = LowerExternalSymbol(Callee, DAG);
2325 if (Is64Bit && isVarArg && !IsWin64) {
2326 // From AMD64 ABI document:
2327 // For calls that may call functions that use varargs or stdargs
2328 // (prototype-less calls or calls to functions containing ellipsis (...) in
2329 // the declaration) %al is used as hidden argument to specify the number
2330 // of SSE registers used. The contents of %al do not need to match exactly
2331 // the number of registers, but must be an ubound on the number of SSE
2332 // registers used and is in the range 0 - 8 inclusive.
2334 // Count the number of XMM registers allocated.
2335 static const uint16_t XMMArgRegs[] = {
2336 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2337 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2339 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2340 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2341 && "SSE registers cannot be used when SSE is disabled");
2343 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2344 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2345 InFlag = Chain.getValue(1);
2349 // For tail calls lower the arguments to the 'real' stack slot.
2351 // Force all the incoming stack arguments to be loaded from the stack
2352 // before any new outgoing arguments are stored to the stack, because the
2353 // outgoing stack slots may alias the incoming argument stack slots, and
2354 // the alias isn't otherwise explicit. This is slightly more conservative
2355 // than necessary, because it means that each store effectively depends
2356 // on every argument instead of just those arguments it would clobber.
2357 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2359 SmallVector<SDValue, 8> MemOpChains2;
2362 // Do not flag preceding copytoreg stuff together with the following stuff.
2364 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2365 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2366 CCValAssign &VA = ArgLocs[i];
2369 assert(VA.isMemLoc());
2370 SDValue Arg = OutVals[i];
2371 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2372 // Create frame index.
2373 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2374 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2375 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2376 FIN = DAG.getFrameIndex(FI, getPointerTy());
2378 if (Flags.isByVal()) {
2379 // Copy relative to framepointer.
2380 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2381 if (StackPtr.getNode() == 0)
2382 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2384 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2386 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2390 // Store relative to framepointer.
2391 MemOpChains2.push_back(
2392 DAG.getStore(ArgChain, dl, Arg, FIN,
2393 MachinePointerInfo::getFixedStack(FI),
2399 if (!MemOpChains2.empty())
2400 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2401 &MemOpChains2[0], MemOpChains2.size());
2403 // Copy arguments to their registers.
2404 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2405 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2406 RegsToPass[i].second, InFlag);
2407 InFlag = Chain.getValue(1);
2411 // Store the return address to the appropriate stack slot.
2412 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2416 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2417 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2418 // In the 64-bit large code model, we have to make all calls
2419 // through a register, since the call instruction's 32-bit
2420 // pc-relative offset may not be large enough to hold the whole
2422 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2423 // If the callee is a GlobalAddress node (quite common, every direct call
2424 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2427 // We should use extra load for direct calls to dllimported functions in
2429 const GlobalValue *GV = G->getGlobal();
2430 if (!GV->hasDLLImportLinkage()) {
2431 unsigned char OpFlags = 0;
2432 bool ExtraLoad = false;
2433 unsigned WrapperKind = ISD::DELETED_NODE;
2435 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2436 // external symbols most go through the PLT in PIC mode. If the symbol
2437 // has hidden or protected visibility, or if it is static or local, then
2438 // we don't need to use the PLT - we can directly call it.
2439 if (Subtarget->isTargetELF() &&
2440 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2441 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2442 OpFlags = X86II::MO_PLT;
2443 } else if (Subtarget->isPICStyleStubAny() &&
2444 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2445 (!Subtarget->getTargetTriple().isMacOSX() ||
2446 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2447 // PC-relative references to external symbols should go through $stub,
2448 // unless we're building with the leopard linker or later, which
2449 // automatically synthesizes these stubs.
2450 OpFlags = X86II::MO_DARWIN_STUB;
2451 } else if (Subtarget->isPICStyleRIPRel() &&
2452 isa<Function>(GV) &&
2453 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2454 // If the function is marked as non-lazy, generate an indirect call
2455 // which loads from the GOT directly. This avoids runtime overhead
2456 // at the cost of eager binding (and one extra byte of encoding).
2457 OpFlags = X86II::MO_GOTPCREL;
2458 WrapperKind = X86ISD::WrapperRIP;
2462 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2463 G->getOffset(), OpFlags);
2465 // Add a wrapper if needed.
2466 if (WrapperKind != ISD::DELETED_NODE)
2467 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2468 // Add extra indirection if needed.
2470 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2471 MachinePointerInfo::getGOT(),
2472 false, false, false, 0);
2474 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2475 unsigned char OpFlags = 0;
2477 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2478 // external symbols should go through the PLT.
2479 if (Subtarget->isTargetELF() &&
2480 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2481 OpFlags = X86II::MO_PLT;
2482 } else if (Subtarget->isPICStyleStubAny() &&
2483 (!Subtarget->getTargetTriple().isMacOSX() ||
2484 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2485 // PC-relative references to external symbols should go through $stub,
2486 // unless we're building with the leopard linker or later, which
2487 // automatically synthesizes these stubs.
2488 OpFlags = X86II::MO_DARWIN_STUB;
2491 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2495 // Returns a chain & a flag for retval copy to use.
2496 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2497 SmallVector<SDValue, 8> Ops;
2499 if (!IsSibcall && isTailCall) {
2500 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2501 DAG.getIntPtrConstant(0, true), InFlag);
2502 InFlag = Chain.getValue(1);
2505 Ops.push_back(Chain);
2506 Ops.push_back(Callee);
2509 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2511 // Add argument registers to the end of the list so that they are known live
2513 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2514 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2515 RegsToPass[i].second.getValueType()));
2517 // Add an implicit use GOT pointer in EBX.
2518 if (!isTailCall && Subtarget->isPICStyleGOT())
2519 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2521 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2522 if (Is64Bit && isVarArg && !IsWin64)
2523 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2525 // Add a register mask operand representing the call-preserved registers.
2526 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2527 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2528 assert(Mask && "Missing call preserved mask for calling convention");
2529 Ops.push_back(DAG.getRegisterMask(Mask));
2531 if (InFlag.getNode())
2532 Ops.push_back(InFlag);
2536 //// If this is the first return lowered for this function, add the regs
2537 //// to the liveout set for the function.
2538 // This isn't right, although it's probably harmless on x86; liveouts
2539 // should be computed from returns not tail calls. Consider a void
2540 // function making a tail call to a function returning int.
2541 return DAG.getNode(X86ISD::TC_RETURN, dl,
2542 NodeTys, &Ops[0], Ops.size());
2545 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2546 InFlag = Chain.getValue(1);
2548 // Create the CALLSEQ_END node.
2549 unsigned NumBytesForCalleeToPush;
2550 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2551 getTargetMachine().Options.GuaranteedTailCallOpt))
2552 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2553 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2555 // If this is a call to a struct-return function, the callee
2556 // pops the hidden struct pointer, so we have to push it back.
2557 // This is common for Darwin/X86, Linux & Mingw32 targets.
2558 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2559 NumBytesForCalleeToPush = 4;
2561 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2563 // Returns a flag for retval copy to use.
2565 Chain = DAG.getCALLSEQ_END(Chain,
2566 DAG.getIntPtrConstant(NumBytes, true),
2567 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2570 InFlag = Chain.getValue(1);
2573 // Handle result values, copying them out of physregs into vregs that we
2575 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2576 Ins, dl, DAG, InVals);
2580 //===----------------------------------------------------------------------===//
2581 // Fast Calling Convention (tail call) implementation
2582 //===----------------------------------------------------------------------===//
2584 // Like std call, callee cleans arguments, convention except that ECX is
2585 // reserved for storing the tail called function address. Only 2 registers are
2586 // free for argument passing (inreg). Tail call optimization is performed
2588 // * tailcallopt is enabled
2589 // * caller/callee are fastcc
2590 // On X86_64 architecture with GOT-style position independent code only local
2591 // (within module) calls are supported at the moment.
2592 // To keep the stack aligned according to platform abi the function
2593 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2594 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2595 // If a tail called function callee has more arguments than the caller the
2596 // caller needs to make sure that there is room to move the RETADDR to. This is
2597 // achieved by reserving an area the size of the argument delta right after the
2598 // original REtADDR, but before the saved framepointer or the spilled registers
2599 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2611 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2612 /// for a 16 byte align requirement.
2614 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2615 SelectionDAG& DAG) const {
2616 MachineFunction &MF = DAG.getMachineFunction();
2617 const TargetMachine &TM = MF.getTarget();
2618 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2619 unsigned StackAlignment = TFI.getStackAlignment();
2620 uint64_t AlignMask = StackAlignment - 1;
2621 int64_t Offset = StackSize;
2622 uint64_t SlotSize = TD->getPointerSize();
2623 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2624 // Number smaller than 12 so just add the difference.
2625 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2627 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2628 Offset = ((~AlignMask) & Offset) + StackAlignment +
2629 (StackAlignment-SlotSize);
2634 /// MatchingStackOffset - Return true if the given stack call argument is
2635 /// already available in the same position (relatively) of the caller's
2636 /// incoming argument stack.
2638 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2639 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2640 const X86InstrInfo *TII) {
2641 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2643 if (Arg.getOpcode() == ISD::CopyFromReg) {
2644 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2645 if (!TargetRegisterInfo::isVirtualRegister(VR))
2647 MachineInstr *Def = MRI->getVRegDef(VR);
2650 if (!Flags.isByVal()) {
2651 if (!TII->isLoadFromStackSlot(Def, FI))
2654 unsigned Opcode = Def->getOpcode();
2655 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2656 Def->getOperand(1).isFI()) {
2657 FI = Def->getOperand(1).getIndex();
2658 Bytes = Flags.getByValSize();
2662 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2663 if (Flags.isByVal())
2664 // ByVal argument is passed in as a pointer but it's now being
2665 // dereferenced. e.g.
2666 // define @foo(%struct.X* %A) {
2667 // tail call @bar(%struct.X* byval %A)
2670 SDValue Ptr = Ld->getBasePtr();
2671 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2674 FI = FINode->getIndex();
2675 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2676 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2677 FI = FINode->getIndex();
2678 Bytes = Flags.getByValSize();
2682 assert(FI != INT_MAX);
2683 if (!MFI->isFixedObjectIndex(FI))
2685 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2688 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2689 /// for tail call optimization. Targets which want to do tail call
2690 /// optimization should implement this function.
2692 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2693 CallingConv::ID CalleeCC,
2695 bool isCalleeStructRet,
2696 bool isCallerStructRet,
2697 const SmallVectorImpl<ISD::OutputArg> &Outs,
2698 const SmallVectorImpl<SDValue> &OutVals,
2699 const SmallVectorImpl<ISD::InputArg> &Ins,
2700 SelectionDAG& DAG) const {
2701 if (!IsTailCallConvention(CalleeCC) &&
2702 CalleeCC != CallingConv::C)
2705 // If -tailcallopt is specified, make fastcc functions tail-callable.
2706 const MachineFunction &MF = DAG.getMachineFunction();
2707 const Function *CallerF = DAG.getMachineFunction().getFunction();
2708 CallingConv::ID CallerCC = CallerF->getCallingConv();
2709 bool CCMatch = CallerCC == CalleeCC;
2711 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2712 if (IsTailCallConvention(CalleeCC) && CCMatch)
2717 // Look for obvious safe cases to perform tail call optimization that do not
2718 // require ABI changes. This is what gcc calls sibcall.
2720 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2721 // emit a special epilogue.
2722 if (RegInfo->needsStackRealignment(MF))
2725 // Also avoid sibcall optimization if either caller or callee uses struct
2726 // return semantics.
2727 if (isCalleeStructRet || isCallerStructRet)
2730 // An stdcall caller is expected to clean up its arguments; the callee
2731 // isn't going to do that.
2732 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2735 // Do not sibcall optimize vararg calls unless all arguments are passed via
2737 if (isVarArg && !Outs.empty()) {
2739 // Optimizing for varargs on Win64 is unlikely to be safe without
2740 // additional testing.
2741 if (Subtarget->isTargetWin64())
2744 SmallVector<CCValAssign, 16> ArgLocs;
2745 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2746 getTargetMachine(), ArgLocs, *DAG.getContext());
2748 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2749 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2750 if (!ArgLocs[i].isRegLoc())
2754 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2755 // stack. Therefore, if it's not used by the call it is not safe to optimize
2756 // this into a sibcall.
2757 bool Unused = false;
2758 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2765 SmallVector<CCValAssign, 16> RVLocs;
2766 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2767 getTargetMachine(), RVLocs, *DAG.getContext());
2768 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2769 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2770 CCValAssign &VA = RVLocs[i];
2771 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2776 // If the calling conventions do not match, then we'd better make sure the
2777 // results are returned in the same way as what the caller expects.
2779 SmallVector<CCValAssign, 16> RVLocs1;
2780 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2781 getTargetMachine(), RVLocs1, *DAG.getContext());
2782 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2784 SmallVector<CCValAssign, 16> RVLocs2;
2785 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2786 getTargetMachine(), RVLocs2, *DAG.getContext());
2787 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2789 if (RVLocs1.size() != RVLocs2.size())
2791 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2792 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2794 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2796 if (RVLocs1[i].isRegLoc()) {
2797 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2800 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2806 // If the callee takes no arguments then go on to check the results of the
2808 if (!Outs.empty()) {
2809 // Check if stack adjustment is needed. For now, do not do this if any
2810 // argument is passed on the stack.
2811 SmallVector<CCValAssign, 16> ArgLocs;
2812 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2813 getTargetMachine(), ArgLocs, *DAG.getContext());
2815 // Allocate shadow area for Win64
2816 if (Subtarget->isTargetWin64()) {
2817 CCInfo.AllocateStack(32, 8);
2820 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2821 if (CCInfo.getNextStackOffset()) {
2822 MachineFunction &MF = DAG.getMachineFunction();
2823 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2826 // Check if the arguments are already laid out in the right way as
2827 // the caller's fixed stack objects.
2828 MachineFrameInfo *MFI = MF.getFrameInfo();
2829 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2830 const X86InstrInfo *TII =
2831 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2832 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2833 CCValAssign &VA = ArgLocs[i];
2834 SDValue Arg = OutVals[i];
2835 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2836 if (VA.getLocInfo() == CCValAssign::Indirect)
2838 if (!VA.isRegLoc()) {
2839 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2846 // If the tailcall address may be in a register, then make sure it's
2847 // possible to register allocate for it. In 32-bit, the call address can
2848 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2849 // callee-saved registers are restored. These happen to be the same
2850 // registers used to pass 'inreg' arguments so watch out for those.
2851 if (!Subtarget->is64Bit() &&
2852 !isa<GlobalAddressSDNode>(Callee) &&
2853 !isa<ExternalSymbolSDNode>(Callee)) {
2854 unsigned NumInRegs = 0;
2855 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2856 CCValAssign &VA = ArgLocs[i];
2859 unsigned Reg = VA.getLocReg();
2862 case X86::EAX: case X86::EDX: case X86::ECX:
2863 if (++NumInRegs == 3)
2875 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2876 return X86::createFastISel(funcInfo);
2880 //===----------------------------------------------------------------------===//
2881 // Other Lowering Hooks
2882 //===----------------------------------------------------------------------===//
2884 static bool MayFoldLoad(SDValue Op) {
2885 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2888 static bool MayFoldIntoStore(SDValue Op) {
2889 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2892 static bool isTargetShuffle(unsigned Opcode) {
2894 default: return false;
2895 case X86ISD::PSHUFD:
2896 case X86ISD::PSHUFHW:
2897 case X86ISD::PSHUFLW:
2899 case X86ISD::PALIGN:
2900 case X86ISD::MOVLHPS:
2901 case X86ISD::MOVLHPD:
2902 case X86ISD::MOVHLPS:
2903 case X86ISD::MOVLPS:
2904 case X86ISD::MOVLPD:
2905 case X86ISD::MOVSHDUP:
2906 case X86ISD::MOVSLDUP:
2907 case X86ISD::MOVDDUP:
2910 case X86ISD::UNPCKL:
2911 case X86ISD::UNPCKH:
2912 case X86ISD::VPERMILP:
2913 case X86ISD::VPERM2X128:
2918 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2919 SDValue V1, SelectionDAG &DAG) {
2921 default: llvm_unreachable("Unknown x86 shuffle node");
2922 case X86ISD::MOVSHDUP:
2923 case X86ISD::MOVSLDUP:
2924 case X86ISD::MOVDDUP:
2925 return DAG.getNode(Opc, dl, VT, V1);
2929 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2930 SDValue V1, unsigned TargetMask,
2931 SelectionDAG &DAG) {
2933 default: llvm_unreachable("Unknown x86 shuffle node");
2934 case X86ISD::PSHUFD:
2935 case X86ISD::PSHUFHW:
2936 case X86ISD::PSHUFLW:
2937 case X86ISD::VPERMILP:
2938 case X86ISD::VPERMI:
2939 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2943 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2944 SDValue V1, SDValue V2, unsigned TargetMask,
2945 SelectionDAG &DAG) {
2947 default: llvm_unreachable("Unknown x86 shuffle node");
2948 case X86ISD::PALIGN:
2950 case X86ISD::VPERM2X128:
2951 return DAG.getNode(Opc, dl, VT, V1, V2,
2952 DAG.getConstant(TargetMask, MVT::i8));
2956 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2957 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2959 default: llvm_unreachable("Unknown x86 shuffle node");
2960 case X86ISD::MOVLHPS:
2961 case X86ISD::MOVLHPD:
2962 case X86ISD::MOVHLPS:
2963 case X86ISD::MOVLPS:
2964 case X86ISD::MOVLPD:
2967 case X86ISD::UNPCKL:
2968 case X86ISD::UNPCKH:
2969 return DAG.getNode(Opc, dl, VT, V1, V2);
2973 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2974 MachineFunction &MF = DAG.getMachineFunction();
2975 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2976 int ReturnAddrIndex = FuncInfo->getRAIndex();
2978 if (ReturnAddrIndex == 0) {
2979 // Set up a frame object for the return address.
2980 uint64_t SlotSize = TD->getPointerSize();
2981 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2983 FuncInfo->setRAIndex(ReturnAddrIndex);
2986 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2990 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2991 bool hasSymbolicDisplacement) {
2992 // Offset should fit into 32 bit immediate field.
2993 if (!isInt<32>(Offset))
2996 // If we don't have a symbolic displacement - we don't have any extra
2998 if (!hasSymbolicDisplacement)
3001 // FIXME: Some tweaks might be needed for medium code model.
3002 if (M != CodeModel::Small && M != CodeModel::Kernel)
3005 // For small code model we assume that latest object is 16MB before end of 31
3006 // bits boundary. We may also accept pretty large negative constants knowing
3007 // that all objects are in the positive half of address space.
3008 if (M == CodeModel::Small && Offset < 16*1024*1024)
3011 // For kernel code model we know that all object resist in the negative half
3012 // of 32bits address space. We may not accept negative offsets, since they may
3013 // be just off and we may accept pretty large positive ones.
3014 if (M == CodeModel::Kernel && Offset > 0)
3020 /// isCalleePop - Determines whether the callee is required to pop its
3021 /// own arguments. Callee pop is necessary to support tail calls.
3022 bool X86::isCalleePop(CallingConv::ID CallingConv,
3023 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3027 switch (CallingConv) {
3030 case CallingConv::X86_StdCall:
3032 case CallingConv::X86_FastCall:
3034 case CallingConv::X86_ThisCall:
3036 case CallingConv::Fast:
3038 case CallingConv::GHC:
3043 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3044 /// specific condition code, returning the condition code and the LHS/RHS of the
3045 /// comparison to make.
3046 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3047 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3049 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3050 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3051 // X > -1 -> X == 0, jump !sign.
3052 RHS = DAG.getConstant(0, RHS.getValueType());
3053 return X86::COND_NS;
3055 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3056 // X < 0 -> X == 0, jump on sign.
3059 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3061 RHS = DAG.getConstant(0, RHS.getValueType());
3062 return X86::COND_LE;
3066 switch (SetCCOpcode) {
3067 default: llvm_unreachable("Invalid integer condition!");
3068 case ISD::SETEQ: return X86::COND_E;
3069 case ISD::SETGT: return X86::COND_G;
3070 case ISD::SETGE: return X86::COND_GE;
3071 case ISD::SETLT: return X86::COND_L;
3072 case ISD::SETLE: return X86::COND_LE;
3073 case ISD::SETNE: return X86::COND_NE;
3074 case ISD::SETULT: return X86::COND_B;
3075 case ISD::SETUGT: return X86::COND_A;
3076 case ISD::SETULE: return X86::COND_BE;
3077 case ISD::SETUGE: return X86::COND_AE;
3081 // First determine if it is required or is profitable to flip the operands.
3083 // If LHS is a foldable load, but RHS is not, flip the condition.
3084 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3085 !ISD::isNON_EXTLoad(RHS.getNode())) {
3086 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3087 std::swap(LHS, RHS);
3090 switch (SetCCOpcode) {
3096 std::swap(LHS, RHS);
3100 // On a floating point condition, the flags are set as follows:
3102 // 0 | 0 | 0 | X > Y
3103 // 0 | 0 | 1 | X < Y
3104 // 1 | 0 | 0 | X == Y
3105 // 1 | 1 | 1 | unordered
3106 switch (SetCCOpcode) {
3107 default: llvm_unreachable("Condcode should be pre-legalized away");
3109 case ISD::SETEQ: return X86::COND_E;
3110 case ISD::SETOLT: // flipped
3112 case ISD::SETGT: return X86::COND_A;
3113 case ISD::SETOLE: // flipped
3115 case ISD::SETGE: return X86::COND_AE;
3116 case ISD::SETUGT: // flipped
3118 case ISD::SETLT: return X86::COND_B;
3119 case ISD::SETUGE: // flipped
3121 case ISD::SETLE: return X86::COND_BE;
3123 case ISD::SETNE: return X86::COND_NE;
3124 case ISD::SETUO: return X86::COND_P;
3125 case ISD::SETO: return X86::COND_NP;
3127 case ISD::SETUNE: return X86::COND_INVALID;
3131 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3132 /// code. Current x86 isa includes the following FP cmov instructions:
3133 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3134 static bool hasFPCMov(unsigned X86CC) {
3150 /// isFPImmLegal - Returns true if the target can instruction select the
3151 /// specified FP immediate natively. If false, the legalizer will
3152 /// materialize the FP immediate as a load from a constant pool.
3153 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3154 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3155 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3161 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3162 /// the specified range (L, H].
3163 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3164 return (Val < 0) || (Val >= Low && Val < Hi);
3167 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3168 /// specified value.
3169 static bool isUndefOrEqual(int Val, int CmpVal) {
3170 if (Val < 0 || Val == CmpVal)
3175 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3176 /// from position Pos and ending in Pos+Size, falls within the specified
3177 /// sequential range (L, L+Pos]. or is undef.
3178 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3179 int Pos, int Size, int Low) {
3180 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3181 if (!isUndefOrEqual(Mask[i], Low))
3186 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3187 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3188 /// the second operand.
3189 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3190 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3191 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3192 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3193 return (Mask[0] < 2 && Mask[1] < 2);
3197 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3198 /// is suitable for input to PSHUFHW.
3199 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3200 if (VT != MVT::v8i16)
3203 // Lower quadword copied in order or undef.
3204 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3207 // Upper quadword shuffled.
3208 for (unsigned i = 4; i != 8; ++i)
3209 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3215 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3216 /// is suitable for input to PSHUFLW.
3217 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3218 if (VT != MVT::v8i16)
3221 // Upper quadword copied in order.
3222 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3225 // Lower quadword shuffled.
3226 for (unsigned i = 0; i != 4; ++i)
3233 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3234 /// is suitable for input to PALIGNR.
3235 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3236 const X86Subtarget *Subtarget) {
3237 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3238 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3241 unsigned NumElts = VT.getVectorNumElements();
3242 unsigned NumLanes = VT.getSizeInBits()/128;
3243 unsigned NumLaneElts = NumElts/NumLanes;
3245 // Do not handle 64-bit element shuffles with palignr.
3246 if (NumLaneElts == 2)
3249 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3251 for (i = 0; i != NumLaneElts; ++i) {
3256 // Lane is all undef, go to next lane
3257 if (i == NumLaneElts)
3260 int Start = Mask[i+l];
3262 // Make sure its in this lane in one of the sources
3263 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3264 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3267 // If not lane 0, then we must match lane 0
3268 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3271 // Correct second source to be contiguous with first source
3272 if (Start >= (int)NumElts)
3273 Start -= NumElts - NumLaneElts;
3275 // Make sure we're shifting in the right direction.
3276 if (Start <= (int)(i+l))
3281 // Check the rest of the elements to see if they are consecutive.
3282 for (++i; i != NumLaneElts; ++i) {
3283 int Idx = Mask[i+l];
3285 // Make sure its in this lane
3286 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3287 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3290 // If not lane 0, then we must match lane 0
3291 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3294 if (Idx >= (int)NumElts)
3295 Idx -= NumElts - NumLaneElts;
3297 if (!isUndefOrEqual(Idx, Start+i))
3306 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3307 /// the two vector operands have swapped position.
3308 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3309 unsigned NumElems) {
3310 for (unsigned i = 0; i != NumElems; ++i) {
3314 else if (idx < (int)NumElems)
3315 Mask[i] = idx + NumElems;
3317 Mask[i] = idx - NumElems;
3321 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3322 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3323 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3324 /// reverse of what x86 shuffles want.
3325 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3326 bool Commuted = false) {
3327 if (!HasAVX && VT.getSizeInBits() == 256)
3330 unsigned NumElems = VT.getVectorNumElements();
3331 unsigned NumLanes = VT.getSizeInBits()/128;
3332 unsigned NumLaneElems = NumElems/NumLanes;
3334 if (NumLaneElems != 2 && NumLaneElems != 4)
3337 // VSHUFPSY divides the resulting vector into 4 chunks.
3338 // The sources are also splitted into 4 chunks, and each destination
3339 // chunk must come from a different source chunk.
3341 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3342 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3344 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3345 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3347 // VSHUFPDY divides the resulting vector into 4 chunks.
3348 // The sources are also splitted into 4 chunks, and each destination
3349 // chunk must come from a different source chunk.
3351 // SRC1 => X3 X2 X1 X0
3352 // SRC2 => Y3 Y2 Y1 Y0
3354 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3356 unsigned HalfLaneElems = NumLaneElems/2;
3357 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3358 for (unsigned i = 0; i != NumLaneElems; ++i) {
3359 int Idx = Mask[i+l];
3360 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3361 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3363 // For VSHUFPSY, the mask of the second half must be the same as the
3364 // first but with the appropriate offsets. This works in the same way as
3365 // VPERMILPS works with masks.
3366 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3368 if (!isUndefOrEqual(Idx, Mask[i]+l))
3376 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3377 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3378 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3379 unsigned NumElems = VT.getVectorNumElements();
3381 if (VT.getSizeInBits() != 128)
3387 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3388 return isUndefOrEqual(Mask[0], 6) &&
3389 isUndefOrEqual(Mask[1], 7) &&
3390 isUndefOrEqual(Mask[2], 2) &&
3391 isUndefOrEqual(Mask[3], 3);
3394 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3395 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3397 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3398 unsigned NumElems = VT.getVectorNumElements();
3400 if (VT.getSizeInBits() != 128)
3406 return isUndefOrEqual(Mask[0], 2) &&
3407 isUndefOrEqual(Mask[1], 3) &&
3408 isUndefOrEqual(Mask[2], 2) &&
3409 isUndefOrEqual(Mask[3], 3);
3412 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3413 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3414 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3415 if (VT.getSizeInBits() != 128)
3418 unsigned NumElems = VT.getVectorNumElements();
3420 if (NumElems != 2 && NumElems != 4)
3423 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3424 if (!isUndefOrEqual(Mask[i], i + NumElems))
3427 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3428 if (!isUndefOrEqual(Mask[i], i))
3434 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3435 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3436 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3437 unsigned NumElems = VT.getVectorNumElements();
3439 if ((NumElems != 2 && NumElems != 4)
3440 || VT.getSizeInBits() > 128)
3443 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3444 if (!isUndefOrEqual(Mask[i], i))
3447 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3448 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3454 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3455 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3456 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3457 bool HasAVX2, bool V2IsSplat = false) {
3458 unsigned NumElts = VT.getVectorNumElements();
3460 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3461 "Unsupported vector type for unpckh");
3463 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3464 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3467 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3468 // independently on 128-bit lanes.
3469 unsigned NumLanes = VT.getSizeInBits()/128;
3470 unsigned NumLaneElts = NumElts/NumLanes;
3472 for (unsigned l = 0; l != NumLanes; ++l) {
3473 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3474 i != (l+1)*NumLaneElts;
3477 int BitI1 = Mask[i+1];
3478 if (!isUndefOrEqual(BitI, j))
3481 if (!isUndefOrEqual(BitI1, NumElts))
3484 if (!isUndefOrEqual(BitI1, j + NumElts))
3493 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3494 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3495 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3496 bool HasAVX2, bool V2IsSplat = false) {
3497 unsigned NumElts = VT.getVectorNumElements();
3499 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3500 "Unsupported vector type for unpckh");
3502 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3503 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3506 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3507 // independently on 128-bit lanes.
3508 unsigned NumLanes = VT.getSizeInBits()/128;
3509 unsigned NumLaneElts = NumElts/NumLanes;
3511 for (unsigned l = 0; l != NumLanes; ++l) {
3512 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3513 i != (l+1)*NumLaneElts; i += 2, ++j) {
3515 int BitI1 = Mask[i+1];
3516 if (!isUndefOrEqual(BitI, j))
3519 if (isUndefOrEqual(BitI1, NumElts))
3522 if (!isUndefOrEqual(BitI1, j+NumElts))
3530 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3531 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3533 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3535 unsigned NumElts = VT.getVectorNumElements();
3537 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3538 "Unsupported vector type for unpckh");
3540 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3541 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3544 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3545 // FIXME: Need a better way to get rid of this, there's no latency difference
3546 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3547 // the former later. We should also remove the "_undef" special mask.
3548 if (NumElts == 4 && VT.getSizeInBits() == 256)
3551 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3552 // independently on 128-bit lanes.
3553 unsigned NumLanes = VT.getSizeInBits()/128;
3554 unsigned NumLaneElts = NumElts/NumLanes;
3556 for (unsigned l = 0; l != NumLanes; ++l) {
3557 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3558 i != (l+1)*NumLaneElts;
3561 int BitI1 = Mask[i+1];
3563 if (!isUndefOrEqual(BitI, j))
3565 if (!isUndefOrEqual(BitI1, j))
3573 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3574 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3576 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3577 unsigned NumElts = VT.getVectorNumElements();
3579 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3580 "Unsupported vector type for unpckh");
3582 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3583 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3586 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3587 // independently on 128-bit lanes.
3588 unsigned NumLanes = VT.getSizeInBits()/128;
3589 unsigned NumLaneElts = NumElts/NumLanes;
3591 for (unsigned l = 0; l != NumLanes; ++l) {
3592 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3593 i != (l+1)*NumLaneElts; i += 2, ++j) {
3595 int BitI1 = Mask[i+1];
3596 if (!isUndefOrEqual(BitI, j))
3598 if (!isUndefOrEqual(BitI1, j))
3605 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3606 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3607 /// MOVSD, and MOVD, i.e. setting the lowest element.
3608 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3609 if (VT.getVectorElementType().getSizeInBits() < 32)
3611 if (VT.getSizeInBits() == 256)
3614 unsigned NumElts = VT.getVectorNumElements();
3616 if (!isUndefOrEqual(Mask[0], NumElts))
3619 for (unsigned i = 1; i != NumElts; ++i)
3620 if (!isUndefOrEqual(Mask[i], i))
3626 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3627 /// as permutations between 128-bit chunks or halves. As an example: this
3629 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3630 /// The first half comes from the second half of V1 and the second half from the
3631 /// the second half of V2.
3632 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3633 if (!HasAVX || VT.getSizeInBits() != 256)
3636 // The shuffle result is divided into half A and half B. In total the two
3637 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3638 // B must come from C, D, E or F.
3639 unsigned HalfSize = VT.getVectorNumElements()/2;
3640 bool MatchA = false, MatchB = false;
3642 // Check if A comes from one of C, D, E, F.
3643 for (unsigned Half = 0; Half != 4; ++Half) {
3644 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3650 // Check if B comes from one of C, D, E, F.
3651 for (unsigned Half = 0; Half != 4; ++Half) {
3652 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3658 return MatchA && MatchB;
3661 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3662 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3663 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3664 EVT VT = SVOp->getValueType(0);
3666 unsigned HalfSize = VT.getVectorNumElements()/2;
3668 unsigned FstHalf = 0, SndHalf = 0;
3669 for (unsigned i = 0; i < HalfSize; ++i) {
3670 if (SVOp->getMaskElt(i) > 0) {
3671 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3675 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3676 if (SVOp->getMaskElt(i) > 0) {
3677 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3682 return (FstHalf | (SndHalf << 4));
3685 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3686 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3687 /// Note that VPERMIL mask matching is different depending whether theunderlying
3688 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3689 /// to the same elements of the low, but to the higher half of the source.
3690 /// In VPERMILPD the two lanes could be shuffled independently of each other
3691 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3692 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3696 unsigned NumElts = VT.getVectorNumElements();
3697 // Only match 256-bit with 32/64-bit types
3698 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3701 unsigned NumLanes = VT.getSizeInBits()/128;
3702 unsigned LaneSize = NumElts/NumLanes;
3703 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3704 for (unsigned i = 0; i != LaneSize; ++i) {
3705 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3707 if (NumElts != 8 || l == 0)
3709 // VPERMILPS handling
3712 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3720 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3721 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3722 /// element of vector 2 and the other elements to come from vector 1 in order.
3723 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3724 bool V2IsSplat = false, bool V2IsUndef = false) {
3725 unsigned NumOps = VT.getVectorNumElements();
3726 if (VT.getSizeInBits() == 256)
3728 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3731 if (!isUndefOrEqual(Mask[0], 0))
3734 for (unsigned i = 1; i != NumOps; ++i)
3735 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3736 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3737 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3743 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3744 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3745 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3746 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3747 const X86Subtarget *Subtarget) {
3748 if (!Subtarget->hasSSE3())
3751 unsigned NumElems = VT.getVectorNumElements();
3753 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3754 (VT.getSizeInBits() == 256 && NumElems != 8))
3757 // "i+1" is the value the indexed mask element must have
3758 for (unsigned i = 0; i != NumElems; i += 2)
3759 if (!isUndefOrEqual(Mask[i], i+1) ||
3760 !isUndefOrEqual(Mask[i+1], i+1))
3766 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3767 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3768 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3769 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3770 const X86Subtarget *Subtarget) {
3771 if (!Subtarget->hasSSE3())
3774 unsigned NumElems = VT.getVectorNumElements();
3776 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3777 (VT.getSizeInBits() == 256 && NumElems != 8))
3780 // "i" is the value the indexed mask element must have
3781 for (unsigned i = 0; i != NumElems; i += 2)
3782 if (!isUndefOrEqual(Mask[i], i) ||
3783 !isUndefOrEqual(Mask[i+1], i))
3789 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3790 /// specifies a shuffle of elements that is suitable for input to 256-bit
3791 /// version of MOVDDUP.
3792 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3793 unsigned NumElts = VT.getVectorNumElements();
3795 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3798 for (unsigned i = 0; i != NumElts/2; ++i)
3799 if (!isUndefOrEqual(Mask[i], 0))
3801 for (unsigned i = NumElts/2; i != NumElts; ++i)
3802 if (!isUndefOrEqual(Mask[i], NumElts/2))
3807 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3808 /// specifies a shuffle of elements that is suitable for input to 128-bit
3809 /// version of MOVDDUP.
3810 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3811 if (VT.getSizeInBits() != 128)
3814 unsigned e = VT.getVectorNumElements() / 2;
3815 for (unsigned i = 0; i != e; ++i)
3816 if (!isUndefOrEqual(Mask[i], i))
3818 for (unsigned i = 0; i != e; ++i)
3819 if (!isUndefOrEqual(Mask[e+i], i))
3824 /// isVEXTRACTF128Index - Return true if the specified
3825 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3826 /// suitable for input to VEXTRACTF128.
3827 bool X86::isVEXTRACTF128Index(SDNode *N) {
3828 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3831 // The index should be aligned on a 128-bit boundary.
3833 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3835 unsigned VL = N->getValueType(0).getVectorNumElements();
3836 unsigned VBits = N->getValueType(0).getSizeInBits();
3837 unsigned ElSize = VBits / VL;
3838 bool Result = (Index * ElSize) % 128 == 0;
3843 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3844 /// operand specifies a subvector insert that is suitable for input to
3846 bool X86::isVINSERTF128Index(SDNode *N) {
3847 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3850 // The index should be aligned on a 128-bit boundary.
3852 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3854 unsigned VL = N->getValueType(0).getVectorNumElements();
3855 unsigned VBits = N->getValueType(0).getSizeInBits();
3856 unsigned ElSize = VBits / VL;
3857 bool Result = (Index * ElSize) % 128 == 0;
3862 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3863 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3864 /// Handles 128-bit and 256-bit.
3865 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3866 EVT VT = N->getValueType(0);
3868 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3869 "Unsupported vector type for PSHUF/SHUFP");
3871 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3872 // independently on 128-bit lanes.
3873 unsigned NumElts = VT.getVectorNumElements();
3874 unsigned NumLanes = VT.getSizeInBits()/128;
3875 unsigned NumLaneElts = NumElts/NumLanes;
3877 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3878 "Only supports 2 or 4 elements per lane");
3880 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3882 for (unsigned i = 0; i != NumElts; ++i) {
3883 int Elt = N->getMaskElt(i);
3884 if (Elt < 0) continue;
3886 unsigned ShAmt = i << Shift;
3887 if (ShAmt >= 8) ShAmt -= 8;
3888 Mask |= Elt << ShAmt;
3894 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3895 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3896 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3898 // 8 nodes, but we only care about the last 4.
3899 for (unsigned i = 7; i >= 4; --i) {
3900 int Val = N->getMaskElt(i);
3909 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3910 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3911 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3913 // 8 nodes, but we only care about the first 4.
3914 for (int i = 3; i >= 0; --i) {
3915 int Val = N->getMaskElt(i);
3924 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3925 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3926 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3927 EVT VT = SVOp->getValueType(0);
3928 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3930 unsigned NumElts = VT.getVectorNumElements();
3931 unsigned NumLanes = VT.getSizeInBits()/128;
3932 unsigned NumLaneElts = NumElts/NumLanes;
3936 for (i = 0; i != NumElts; ++i) {
3937 Val = SVOp->getMaskElt(i);
3941 if (Val >= (int)NumElts)
3942 Val -= NumElts - NumLaneElts;
3944 assert(Val - i > 0 && "PALIGNR imm should be positive");
3945 return (Val - i) * EltSize;
3948 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3949 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3951 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3952 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3953 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3956 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3958 EVT VecVT = N->getOperand(0).getValueType();
3959 EVT ElVT = VecVT.getVectorElementType();
3961 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3962 return Index / NumElemsPerChunk;
3965 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3966 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3968 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3969 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3970 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3973 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3975 EVT VecVT = N->getValueType(0);
3976 EVT ElVT = VecVT.getVectorElementType();
3978 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3979 return Index / NumElemsPerChunk;
3982 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
3983 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
3984 /// Handles 256-bit.
3985 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
3986 EVT VT = N->getValueType(0);
3988 unsigned NumElts = VT.getVectorNumElements();
3990 assert((VT.is256BitVector() && NumElts == 4) &&
3991 "Unsupported vector type for VPERMQ/VPERMPD");
3994 for (unsigned i = 0; i != NumElts; ++i) {
3995 int Elt = N->getMaskElt(i);
3998 Mask |= Elt << (i*2);
4003 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4005 bool X86::isZeroNode(SDValue Elt) {
4006 return ((isa<ConstantSDNode>(Elt) &&
4007 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4008 (isa<ConstantFPSDNode>(Elt) &&
4009 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4012 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4013 /// their permute mask.
4014 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4015 SelectionDAG &DAG) {
4016 EVT VT = SVOp->getValueType(0);
4017 unsigned NumElems = VT.getVectorNumElements();
4018 SmallVector<int, 8> MaskVec;
4020 for (unsigned i = 0; i != NumElems; ++i) {
4021 int idx = SVOp->getMaskElt(i);
4023 MaskVec.push_back(idx);
4024 else if (idx < (int)NumElems)
4025 MaskVec.push_back(idx + NumElems);
4027 MaskVec.push_back(idx - NumElems);
4029 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4030 SVOp->getOperand(0), &MaskVec[0]);
4033 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4034 /// match movhlps. The lower half elements should come from upper half of
4035 /// V1 (and in order), and the upper half elements should come from the upper
4036 /// half of V2 (and in order).
4037 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4038 if (VT.getSizeInBits() != 128)
4040 if (VT.getVectorNumElements() != 4)
4042 for (unsigned i = 0, e = 2; i != e; ++i)
4043 if (!isUndefOrEqual(Mask[i], i+2))
4045 for (unsigned i = 2; i != 4; ++i)
4046 if (!isUndefOrEqual(Mask[i], i+4))
4051 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4052 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4054 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4055 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4057 N = N->getOperand(0).getNode();
4058 if (!ISD::isNON_EXTLoad(N))
4061 *LD = cast<LoadSDNode>(N);
4065 // Test whether the given value is a vector value which will be legalized
4067 static bool WillBeConstantPoolLoad(SDNode *N) {
4068 if (N->getOpcode() != ISD::BUILD_VECTOR)
4071 // Check for any non-constant elements.
4072 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4073 switch (N->getOperand(i).getNode()->getOpcode()) {
4075 case ISD::ConstantFP:
4082 // Vectors of all-zeros and all-ones are materialized with special
4083 // instructions rather than being loaded.
4084 return !ISD::isBuildVectorAllZeros(N) &&
4085 !ISD::isBuildVectorAllOnes(N);
4088 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4089 /// match movlp{s|d}. The lower half elements should come from lower half of
4090 /// V1 (and in order), and the upper half elements should come from the upper
4091 /// half of V2 (and in order). And since V1 will become the source of the
4092 /// MOVLP, it must be either a vector load or a scalar load to vector.
4093 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4094 ArrayRef<int> Mask, EVT VT) {
4095 if (VT.getSizeInBits() != 128)
4098 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4100 // Is V2 is a vector load, don't do this transformation. We will try to use
4101 // load folding shufps op.
4102 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4105 unsigned NumElems = VT.getVectorNumElements();
4107 if (NumElems != 2 && NumElems != 4)
4109 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4110 if (!isUndefOrEqual(Mask[i], i))
4112 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4113 if (!isUndefOrEqual(Mask[i], i+NumElems))
4118 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4120 static bool isSplatVector(SDNode *N) {
4121 if (N->getOpcode() != ISD::BUILD_VECTOR)
4124 SDValue SplatValue = N->getOperand(0);
4125 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4126 if (N->getOperand(i) != SplatValue)
4131 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4132 /// to an zero vector.
4133 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4134 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4135 SDValue V1 = N->getOperand(0);
4136 SDValue V2 = N->getOperand(1);
4137 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4138 for (unsigned i = 0; i != NumElems; ++i) {
4139 int Idx = N->getMaskElt(i);
4140 if (Idx >= (int)NumElems) {
4141 unsigned Opc = V2.getOpcode();
4142 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4144 if (Opc != ISD::BUILD_VECTOR ||
4145 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4147 } else if (Idx >= 0) {
4148 unsigned Opc = V1.getOpcode();
4149 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4151 if (Opc != ISD::BUILD_VECTOR ||
4152 !X86::isZeroNode(V1.getOperand(Idx)))
4159 /// getZeroVector - Returns a vector of specified type with all zero elements.
4161 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4162 SelectionDAG &DAG, DebugLoc dl) {
4163 assert(VT.isVector() && "Expected a vector type");
4164 unsigned Size = VT.getSizeInBits();
4166 // Always build SSE zero vectors as <4 x i32> bitcasted
4167 // to their dest type. This ensures they get CSE'd.
4169 if (Size == 128) { // SSE
4170 if (Subtarget->hasSSE2()) { // SSE2
4171 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4172 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4174 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4175 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4177 } else if (Size == 256) { // AVX
4178 if (Subtarget->hasAVX2()) { // AVX2
4179 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4180 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4181 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4183 // 256-bit logic and arithmetic instructions in AVX are all
4184 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4185 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4186 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4187 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4190 llvm_unreachable("Unexpected vector type");
4192 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4195 /// getOnesVector - Returns a vector of specified type with all bits set.
4196 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4197 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4198 /// Then bitcast to their original type, ensuring they get CSE'd.
4199 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4201 assert(VT.isVector() && "Expected a vector type");
4202 unsigned Size = VT.getSizeInBits();
4204 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4207 if (HasAVX2) { // AVX2
4208 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4209 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4211 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4212 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4214 } else if (Size == 128) {
4215 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4217 llvm_unreachable("Unexpected vector type");
4219 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4222 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4223 /// that point to V2 points to its first element.
4224 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4225 for (unsigned i = 0; i != NumElems; ++i) {
4226 if (Mask[i] > (int)NumElems) {
4232 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4233 /// operation of specified width.
4234 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4236 unsigned NumElems = VT.getVectorNumElements();
4237 SmallVector<int, 8> Mask;
4238 Mask.push_back(NumElems);
4239 for (unsigned i = 1; i != NumElems; ++i)
4241 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4244 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4245 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4247 unsigned NumElems = VT.getVectorNumElements();
4248 SmallVector<int, 8> Mask;
4249 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4251 Mask.push_back(i + NumElems);
4253 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4256 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4257 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4259 unsigned NumElems = VT.getVectorNumElements();
4260 SmallVector<int, 8> Mask;
4261 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4262 Mask.push_back(i + Half);
4263 Mask.push_back(i + NumElems + Half);
4265 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4268 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4269 // a generic shuffle instruction because the target has no such instructions.
4270 // Generate shuffles which repeat i16 and i8 several times until they can be
4271 // represented by v4f32 and then be manipulated by target suported shuffles.
4272 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4273 EVT VT = V.getValueType();
4274 int NumElems = VT.getVectorNumElements();
4275 DebugLoc dl = V.getDebugLoc();
4277 while (NumElems > 4) {
4278 if (EltNo < NumElems/2) {
4279 V = getUnpackl(DAG, dl, VT, V, V);
4281 V = getUnpackh(DAG, dl, VT, V, V);
4282 EltNo -= NumElems/2;
4289 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4290 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4291 EVT VT = V.getValueType();
4292 DebugLoc dl = V.getDebugLoc();
4293 unsigned Size = VT.getSizeInBits();
4296 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4297 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4298 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4300 } else if (Size == 256) {
4301 // To use VPERMILPS to splat scalars, the second half of indicies must
4302 // refer to the higher part, which is a duplication of the lower one,
4303 // because VPERMILPS can only handle in-lane permutations.
4304 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4305 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4307 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4308 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4311 llvm_unreachable("Vector size not supported");
4313 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4316 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4317 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4318 EVT SrcVT = SV->getValueType(0);
4319 SDValue V1 = SV->getOperand(0);
4320 DebugLoc dl = SV->getDebugLoc();
4322 int EltNo = SV->getSplatIndex();
4323 int NumElems = SrcVT.getVectorNumElements();
4324 unsigned Size = SrcVT.getSizeInBits();
4326 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4327 "Unknown how to promote splat for type");
4329 // Extract the 128-bit part containing the splat element and update
4330 // the splat element index when it refers to the higher register.
4332 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4333 if (EltNo >= NumElems/2)
4334 EltNo -= NumElems/2;
4337 // All i16 and i8 vector types can't be used directly by a generic shuffle
4338 // instruction because the target has no such instruction. Generate shuffles
4339 // which repeat i16 and i8 several times until they fit in i32, and then can
4340 // be manipulated by target suported shuffles.
4341 EVT EltVT = SrcVT.getVectorElementType();
4342 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4343 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4345 // Recreate the 256-bit vector and place the same 128-bit vector
4346 // into the low and high part. This is necessary because we want
4347 // to use VPERM* to shuffle the vectors
4349 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4352 return getLegalSplat(DAG, V1, EltNo);
4355 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4356 /// vector of zero or undef vector. This produces a shuffle where the low
4357 /// element of V2 is swizzled into the zero/undef vector, landing at element
4358 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4359 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4361 const X86Subtarget *Subtarget,
4362 SelectionDAG &DAG) {
4363 EVT VT = V2.getValueType();
4365 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4366 unsigned NumElems = VT.getVectorNumElements();
4367 SmallVector<int, 16> MaskVec;
4368 for (unsigned i = 0; i != NumElems; ++i)
4369 // If this is the insertion idx, put the low elt of V2 here.
4370 MaskVec.push_back(i == Idx ? NumElems : i);
4371 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4374 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4375 /// target specific opcode. Returns true if the Mask could be calculated.
4376 /// Sets IsUnary to true if only uses one source.
4377 static bool getTargetShuffleMask(SDNode *N, EVT VT,
4378 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4379 unsigned NumElems = VT.getVectorNumElements();
4383 switch(N->getOpcode()) {
4385 ImmN = N->getOperand(N->getNumOperands()-1);
4386 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4388 case X86ISD::UNPCKH:
4389 DecodeUNPCKHMask(VT, Mask);
4391 case X86ISD::UNPCKL:
4392 DecodeUNPCKLMask(VT, Mask);
4394 case X86ISD::MOVHLPS:
4395 DecodeMOVHLPSMask(NumElems, Mask);
4397 case X86ISD::MOVLHPS:
4398 DecodeMOVLHPSMask(NumElems, Mask);
4400 case X86ISD::PSHUFD:
4401 case X86ISD::VPERMILP:
4402 ImmN = N->getOperand(N->getNumOperands()-1);
4403 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4406 case X86ISD::PSHUFHW:
4407 ImmN = N->getOperand(N->getNumOperands()-1);
4408 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4411 case X86ISD::PSHUFLW:
4412 ImmN = N->getOperand(N->getNumOperands()-1);
4413 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4417 case X86ISD::MOVSD: {
4418 // The index 0 always comes from the first element of the second source,
4419 // this is why MOVSS and MOVSD are used in the first place. The other
4420 // elements come from the other positions of the first source vector
4421 Mask.push_back(NumElems);
4422 for (unsigned i = 1; i != NumElems; ++i) {
4427 case X86ISD::VPERM2X128:
4428 ImmN = N->getOperand(N->getNumOperands()-1);
4429 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4430 if (Mask.empty()) return false;
4432 case X86ISD::MOVDDUP:
4433 case X86ISD::MOVLHPD:
4434 case X86ISD::MOVLPD:
4435 case X86ISD::MOVLPS:
4436 case X86ISD::MOVSHDUP:
4437 case X86ISD::MOVSLDUP:
4438 case X86ISD::PALIGN:
4439 // Not yet implemented
4441 default: llvm_unreachable("unknown target shuffle node");
4447 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4448 /// element of the result of the vector shuffle.
4449 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4452 return SDValue(); // Limit search depth.
4454 SDValue V = SDValue(N, 0);
4455 EVT VT = V.getValueType();
4456 unsigned Opcode = V.getOpcode();
4458 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4459 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4460 int Elt = SV->getMaskElt(Index);
4463 return DAG.getUNDEF(VT.getVectorElementType());
4465 unsigned NumElems = VT.getVectorNumElements();
4466 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4467 : SV->getOperand(1);
4468 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4471 // Recurse into target specific vector shuffles to find scalars.
4472 if (isTargetShuffle(Opcode)) {
4473 unsigned NumElems = VT.getVectorNumElements();
4474 SmallVector<int, 16> ShuffleMask;
4478 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary))
4481 int Elt = ShuffleMask[Index];
4483 return DAG.getUNDEF(VT.getVectorElementType());
4485 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4487 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4491 // Actual nodes that may contain scalar elements
4492 if (Opcode == ISD::BITCAST) {
4493 V = V.getOperand(0);
4494 EVT SrcVT = V.getValueType();
4495 unsigned NumElems = VT.getVectorNumElements();
4497 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4501 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4502 return (Index == 0) ? V.getOperand(0)
4503 : DAG.getUNDEF(VT.getVectorElementType());
4505 if (V.getOpcode() == ISD::BUILD_VECTOR)
4506 return V.getOperand(Index);
4511 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4512 /// shuffle operation which come from a consecutively from a zero. The
4513 /// search can start in two different directions, from left or right.
4515 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4516 bool ZerosFromLeft, SelectionDAG &DAG) {
4518 for (i = 0; i != NumElems; ++i) {
4519 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4520 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4521 if (!(Elt.getNode() &&
4522 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4529 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4530 /// correspond consecutively to elements from one of the vector operands,
4531 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4533 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4534 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4535 unsigned NumElems, unsigned &OpNum) {
4536 bool SeenV1 = false;
4537 bool SeenV2 = false;
4539 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4540 int Idx = SVOp->getMaskElt(i);
4541 // Ignore undef indicies
4545 if (Idx < (int)NumElems)
4550 // Only accept consecutive elements from the same vector
4551 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4555 OpNum = SeenV1 ? 0 : 1;
4559 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4560 /// logical left shift of a vector.
4561 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4562 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4563 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4564 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4565 false /* check zeros from right */, DAG);
4571 // Considering the elements in the mask that are not consecutive zeros,
4572 // check if they consecutively come from only one of the source vectors.
4574 // V1 = {X, A, B, C} 0
4576 // vector_shuffle V1, V2 <1, 2, 3, X>
4578 if (!isShuffleMaskConsecutive(SVOp,
4579 0, // Mask Start Index
4580 NumElems-NumZeros, // Mask End Index(exclusive)
4581 NumZeros, // Where to start looking in the src vector
4582 NumElems, // Number of elements in vector
4583 OpSrc)) // Which source operand ?
4588 ShVal = SVOp->getOperand(OpSrc);
4592 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4593 /// logical left shift of a vector.
4594 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4595 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4596 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4597 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4598 true /* check zeros from left */, DAG);
4604 // Considering the elements in the mask that are not consecutive zeros,
4605 // check if they consecutively come from only one of the source vectors.
4607 // 0 { A, B, X, X } = V2
4609 // vector_shuffle V1, V2 <X, X, 4, 5>
4611 if (!isShuffleMaskConsecutive(SVOp,
4612 NumZeros, // Mask Start Index
4613 NumElems, // Mask End Index(exclusive)
4614 0, // Where to start looking in the src vector
4615 NumElems, // Number of elements in vector
4616 OpSrc)) // Which source operand ?
4621 ShVal = SVOp->getOperand(OpSrc);
4625 /// isVectorShift - Returns true if the shuffle can be implemented as a
4626 /// logical left or right shift of a vector.
4627 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4628 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4629 // Although the logic below support any bitwidth size, there are no
4630 // shift instructions which handle more than 128-bit vectors.
4631 if (SVOp->getValueType(0).getSizeInBits() > 128)
4634 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4635 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4641 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4643 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4644 unsigned NumNonZero, unsigned NumZero,
4646 const X86Subtarget* Subtarget,
4647 const TargetLowering &TLI) {
4651 DebugLoc dl = Op.getDebugLoc();
4654 for (unsigned i = 0; i < 16; ++i) {
4655 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4656 if (ThisIsNonZero && First) {
4658 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4660 V = DAG.getUNDEF(MVT::v8i16);
4665 SDValue ThisElt(0, 0), LastElt(0, 0);
4666 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4667 if (LastIsNonZero) {
4668 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4669 MVT::i16, Op.getOperand(i-1));
4671 if (ThisIsNonZero) {
4672 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4673 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4674 ThisElt, DAG.getConstant(8, MVT::i8));
4676 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4680 if (ThisElt.getNode())
4681 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4682 DAG.getIntPtrConstant(i/2));
4686 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4689 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4691 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4692 unsigned NumNonZero, unsigned NumZero,
4694 const X86Subtarget* Subtarget,
4695 const TargetLowering &TLI) {
4699 DebugLoc dl = Op.getDebugLoc();
4702 for (unsigned i = 0; i < 8; ++i) {
4703 bool isNonZero = (NonZeros & (1 << i)) != 0;
4707 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4709 V = DAG.getUNDEF(MVT::v8i16);
4712 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4713 MVT::v8i16, V, Op.getOperand(i),
4714 DAG.getIntPtrConstant(i));
4721 /// getVShift - Return a vector logical shift node.
4723 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4724 unsigned NumBits, SelectionDAG &DAG,
4725 const TargetLowering &TLI, DebugLoc dl) {
4726 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4727 EVT ShVT = MVT::v2i64;
4728 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4729 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4730 return DAG.getNode(ISD::BITCAST, dl, VT,
4731 DAG.getNode(Opc, dl, ShVT, SrcOp,
4732 DAG.getConstant(NumBits,
4733 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4737 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4738 SelectionDAG &DAG) const {
4740 // Check if the scalar load can be widened into a vector load. And if
4741 // the address is "base + cst" see if the cst can be "absorbed" into
4742 // the shuffle mask.
4743 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4744 SDValue Ptr = LD->getBasePtr();
4745 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4747 EVT PVT = LD->getValueType(0);
4748 if (PVT != MVT::i32 && PVT != MVT::f32)
4753 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4754 FI = FINode->getIndex();
4756 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4757 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4758 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4759 Offset = Ptr.getConstantOperandVal(1);
4760 Ptr = Ptr.getOperand(0);
4765 // FIXME: 256-bit vector instructions don't require a strict alignment,
4766 // improve this code to support it better.
4767 unsigned RequiredAlign = VT.getSizeInBits()/8;
4768 SDValue Chain = LD->getChain();
4769 // Make sure the stack object alignment is at least 16 or 32.
4770 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4771 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4772 if (MFI->isFixedObjectIndex(FI)) {
4773 // Can't change the alignment. FIXME: It's possible to compute
4774 // the exact stack offset and reference FI + adjust offset instead.
4775 // If someone *really* cares about this. That's the way to implement it.
4778 MFI->setObjectAlignment(FI, RequiredAlign);
4782 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4783 // Ptr + (Offset & ~15).
4786 if ((Offset % RequiredAlign) & 3)
4788 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4790 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4791 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4793 int EltNo = (Offset - StartOffset) >> 2;
4794 unsigned NumElems = VT.getVectorNumElements();
4796 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4797 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4798 LD->getPointerInfo().getWithOffset(StartOffset),
4799 false, false, false, 0);
4801 SmallVector<int, 8> Mask;
4802 for (unsigned i = 0; i != NumElems; ++i)
4803 Mask.push_back(EltNo);
4805 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4811 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4812 /// vector of type 'VT', see if the elements can be replaced by a single large
4813 /// load which has the same value as a build_vector whose operands are 'elts'.
4815 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4817 /// FIXME: we'd also like to handle the case where the last elements are zero
4818 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4819 /// There's even a handy isZeroNode for that purpose.
4820 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4821 DebugLoc &DL, SelectionDAG &DAG) {
4822 EVT EltVT = VT.getVectorElementType();
4823 unsigned NumElems = Elts.size();
4825 LoadSDNode *LDBase = NULL;
4826 unsigned LastLoadedElt = -1U;
4828 // For each element in the initializer, see if we've found a load or an undef.
4829 // If we don't find an initial load element, or later load elements are
4830 // non-consecutive, bail out.
4831 for (unsigned i = 0; i < NumElems; ++i) {
4832 SDValue Elt = Elts[i];
4834 if (!Elt.getNode() ||
4835 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4838 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4840 LDBase = cast<LoadSDNode>(Elt.getNode());
4844 if (Elt.getOpcode() == ISD::UNDEF)
4847 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4848 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4853 // If we have found an entire vector of loads and undefs, then return a large
4854 // load of the entire vector width starting at the base pointer. If we found
4855 // consecutive loads for the low half, generate a vzext_load node.
4856 if (LastLoadedElt == NumElems - 1) {
4857 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4858 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4859 LDBase->getPointerInfo(),
4860 LDBase->isVolatile(), LDBase->isNonTemporal(),
4861 LDBase->isInvariant(), 0);
4862 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4863 LDBase->getPointerInfo(),
4864 LDBase->isVolatile(), LDBase->isNonTemporal(),
4865 LDBase->isInvariant(), LDBase->getAlignment());
4867 if (NumElems == 4 && LastLoadedElt == 1 &&
4868 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4869 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4870 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4872 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4873 LDBase->getPointerInfo(),
4874 LDBase->getAlignment(),
4875 false/*isVolatile*/, true/*ReadMem*/,
4877 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4882 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4883 /// to generate a splat value for the following cases:
4884 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4885 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4886 /// a scalar load, or a constant.
4887 /// The VBROADCAST node is returned when a pattern is found,
4888 /// or SDValue() otherwise.
4890 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4891 if (!Subtarget->hasAVX())
4894 EVT VT = Op.getValueType();
4895 DebugLoc dl = Op.getDebugLoc();
4900 switch (Op.getOpcode()) {
4902 // Unknown pattern found.
4905 case ISD::BUILD_VECTOR: {
4906 // The BUILD_VECTOR node must be a splat.
4907 if (!isSplatVector(Op.getNode()))
4910 Ld = Op.getOperand(0);
4911 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4912 Ld.getOpcode() == ISD::ConstantFP);
4914 // The suspected load node has several users. Make sure that all
4915 // of its users are from the BUILD_VECTOR node.
4916 // Constants may have multiple users.
4917 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4922 case ISD::VECTOR_SHUFFLE: {
4923 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4925 // Shuffles must have a splat mask where the first element is
4927 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4930 SDValue Sc = Op.getOperand(0);
4931 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4934 Ld = Sc.getOperand(0);
4935 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4936 Ld.getOpcode() == ISD::ConstantFP);
4938 // The scalar_to_vector node and the suspected
4939 // load node must have exactly one user.
4940 // Constants may have multiple users.
4941 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
4947 bool Is256 = VT.getSizeInBits() == 256;
4948 bool Is128 = VT.getSizeInBits() == 128;
4950 // Handle the broadcasting a single constant scalar from the constant pool
4951 // into a vector. On Sandybridge it is still better to load a constant vector
4952 // from the constant pool and not to broadcast it from a scalar.
4953 if (ConstSplatVal && Subtarget->hasAVX2()) {
4954 EVT CVT = Ld.getValueType();
4955 assert(!CVT.isVector() && "Must not broadcast a vector type");
4956 unsigned ScalarSize = CVT.getSizeInBits();
4958 if ((Is256 && (ScalarSize == 32 || ScalarSize == 64)) ||
4959 (Is128 && (ScalarSize == 32))) {
4961 const Constant *C = 0;
4962 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4963 C = CI->getConstantIntValue();
4964 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
4965 C = CF->getConstantFPValue();
4967 assert(C && "Invalid constant type");
4969 SDValue CP = DAG.getConstantPool(C, getPointerTy());
4970 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
4971 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
4972 MachinePointerInfo::getConstantPool(),
4973 false, false, false, Alignment);
4975 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4979 // The scalar source must be a normal load.
4980 if (!ISD::isNormalLoad(Ld.getNode()))
4983 // Reject loads that have uses of the chain result
4984 if (Ld->hasAnyUseOfValue(1))
4987 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4989 // VBroadcast to YMM
4990 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
4991 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4993 // VBroadcast to XMM
4994 if (Is128 && (ScalarSize == 32))
4995 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4997 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
4998 // double since there is vbroadcastsd xmm
4999 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5000 // VBroadcast to YMM
5001 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
5002 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5004 // VBroadcast to XMM
5005 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
5006 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5009 // Unsupported broadcast.
5014 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5015 DebugLoc dl = Op.getDebugLoc();
5017 EVT VT = Op.getValueType();
5018 EVT ExtVT = VT.getVectorElementType();
5019 unsigned NumElems = Op.getNumOperands();
5021 // Vectors containing all zeros can be matched by pxor and xorps later
5022 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5023 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5024 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5025 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5028 return getZeroVector(VT, Subtarget, DAG, dl);
5031 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5032 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5033 // vpcmpeqd on 256-bit vectors.
5034 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5035 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5038 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5041 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5042 if (Broadcast.getNode())
5045 unsigned EVTBits = ExtVT.getSizeInBits();
5047 unsigned NumZero = 0;
5048 unsigned NumNonZero = 0;
5049 unsigned NonZeros = 0;
5050 bool IsAllConstants = true;
5051 SmallSet<SDValue, 8> Values;
5052 for (unsigned i = 0; i < NumElems; ++i) {
5053 SDValue Elt = Op.getOperand(i);
5054 if (Elt.getOpcode() == ISD::UNDEF)
5057 if (Elt.getOpcode() != ISD::Constant &&
5058 Elt.getOpcode() != ISD::ConstantFP)
5059 IsAllConstants = false;
5060 if (X86::isZeroNode(Elt))
5063 NonZeros |= (1 << i);
5068 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5069 if (NumNonZero == 0)
5070 return DAG.getUNDEF(VT);
5072 // Special case for single non-zero, non-undef, element.
5073 if (NumNonZero == 1) {
5074 unsigned Idx = CountTrailingZeros_32(NonZeros);
5075 SDValue Item = Op.getOperand(Idx);
5077 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5078 // the value are obviously zero, truncate the value to i32 and do the
5079 // insertion that way. Only do this if the value is non-constant or if the
5080 // value is a constant being inserted into element 0. It is cheaper to do
5081 // a constant pool load than it is to do a movd + shuffle.
5082 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5083 (!IsAllConstants || Idx == 0)) {
5084 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5086 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5087 EVT VecVT = MVT::v4i32;
5088 unsigned VecElts = 4;
5090 // Truncate the value (which may itself be a constant) to i32, and
5091 // convert it to a vector with movd (S2V+shuffle to zero extend).
5092 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5093 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5094 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5096 // Now we have our 32-bit value zero extended in the low element of
5097 // a vector. If Idx != 0, swizzle it into place.
5099 SmallVector<int, 4> Mask;
5100 Mask.push_back(Idx);
5101 for (unsigned i = 1; i != VecElts; ++i)
5103 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5106 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5110 // If we have a constant or non-constant insertion into the low element of
5111 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5112 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5113 // depending on what the source datatype is.
5116 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5118 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5119 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5120 if (VT.getSizeInBits() == 256) {
5121 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5122 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5123 Item, DAG.getIntPtrConstant(0));
5125 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5126 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5127 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5128 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5131 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5132 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5133 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5134 if (VT.getSizeInBits() == 256) {
5135 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5136 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5138 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5139 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5141 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5145 // Is it a vector logical left shift?
5146 if (NumElems == 2 && Idx == 1 &&
5147 X86::isZeroNode(Op.getOperand(0)) &&
5148 !X86::isZeroNode(Op.getOperand(1))) {
5149 unsigned NumBits = VT.getSizeInBits();
5150 return getVShift(true, VT,
5151 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5152 VT, Op.getOperand(1)),
5153 NumBits/2, DAG, *this, dl);
5156 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5159 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5160 // is a non-constant being inserted into an element other than the low one,
5161 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5162 // movd/movss) to move this into the low element, then shuffle it into
5164 if (EVTBits == 32) {
5165 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5167 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5168 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5169 SmallVector<int, 8> MaskVec;
5170 for (unsigned i = 0; i < NumElems; i++)
5171 MaskVec.push_back(i == Idx ? 0 : 1);
5172 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5176 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5177 if (Values.size() == 1) {
5178 if (EVTBits == 32) {
5179 // Instead of a shuffle like this:
5180 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5181 // Check if it's possible to issue this instead.
5182 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5183 unsigned Idx = CountTrailingZeros_32(NonZeros);
5184 SDValue Item = Op.getOperand(Idx);
5185 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5186 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5191 // A vector full of immediates; various special cases are already
5192 // handled, so this is best done with a single constant-pool load.
5196 // For AVX-length vectors, build the individual 128-bit pieces and use
5197 // shuffles to put them in place.
5198 if (VT.getSizeInBits() == 256) {
5199 SmallVector<SDValue, 32> V;
5200 for (unsigned i = 0; i != NumElems; ++i)
5201 V.push_back(Op.getOperand(i));
5203 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5205 // Build both the lower and upper subvector.
5206 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5207 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5210 // Recreate the wider vector with the lower and upper part.
5211 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5214 // Let legalizer expand 2-wide build_vectors.
5215 if (EVTBits == 64) {
5216 if (NumNonZero == 1) {
5217 // One half is zero or undef.
5218 unsigned Idx = CountTrailingZeros_32(NonZeros);
5219 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5220 Op.getOperand(Idx));
5221 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5226 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5227 if (EVTBits == 8 && NumElems == 16) {
5228 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5230 if (V.getNode()) return V;
5233 if (EVTBits == 16 && NumElems == 8) {
5234 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5236 if (V.getNode()) return V;
5239 // If element VT is == 32 bits, turn it into a number of shuffles.
5240 SmallVector<SDValue, 8> V(NumElems);
5241 if (NumElems == 4 && NumZero > 0) {
5242 for (unsigned i = 0; i < 4; ++i) {
5243 bool isZero = !(NonZeros & (1 << i));
5245 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5247 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5250 for (unsigned i = 0; i < 2; ++i) {
5251 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5254 V[i] = V[i*2]; // Must be a zero vector.
5257 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5260 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5263 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5268 bool Reverse1 = (NonZeros & 0x3) == 2;
5269 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5273 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5274 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5276 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5279 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5280 // Check for a build vector of consecutive loads.
5281 for (unsigned i = 0; i < NumElems; ++i)
5282 V[i] = Op.getOperand(i);
5284 // Check for elements which are consecutive loads.
5285 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5289 // For SSE 4.1, use insertps to put the high elements into the low element.
5290 if (getSubtarget()->hasSSE41()) {
5292 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5293 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5295 Result = DAG.getUNDEF(VT);
5297 for (unsigned i = 1; i < NumElems; ++i) {
5298 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5299 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5300 Op.getOperand(i), DAG.getIntPtrConstant(i));
5305 // Otherwise, expand into a number of unpckl*, start by extending each of
5306 // our (non-undef) elements to the full vector width with the element in the
5307 // bottom slot of the vector (which generates no code for SSE).
5308 for (unsigned i = 0; i < NumElems; ++i) {
5309 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5310 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5312 V[i] = DAG.getUNDEF(VT);
5315 // Next, we iteratively mix elements, e.g. for v4f32:
5316 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5317 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5318 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5319 unsigned EltStride = NumElems >> 1;
5320 while (EltStride != 0) {
5321 for (unsigned i = 0; i < EltStride; ++i) {
5322 // If V[i+EltStride] is undef and this is the first round of mixing,
5323 // then it is safe to just drop this shuffle: V[i] is already in the
5324 // right place, the one element (since it's the first round) being
5325 // inserted as undef can be dropped. This isn't safe for successive
5326 // rounds because they will permute elements within both vectors.
5327 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5328 EltStride == NumElems/2)
5331 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5340 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5341 // them in a MMX register. This is better than doing a stack convert.
5342 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5343 DebugLoc dl = Op.getDebugLoc();
5344 EVT ResVT = Op.getValueType();
5346 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5347 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5349 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5350 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5351 InVec = Op.getOperand(1);
5352 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5353 unsigned NumElts = ResVT.getVectorNumElements();
5354 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5355 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5356 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5358 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5359 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5360 Mask[0] = 0; Mask[1] = 2;
5361 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5363 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5366 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5367 // to create 256-bit vectors from two other 128-bit ones.
5368 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5369 DebugLoc dl = Op.getDebugLoc();
5370 EVT ResVT = Op.getValueType();
5372 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5374 SDValue V1 = Op.getOperand(0);
5375 SDValue V2 = Op.getOperand(1);
5376 unsigned NumElems = ResVT.getVectorNumElements();
5378 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5382 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5383 EVT ResVT = Op.getValueType();
5385 assert(Op.getNumOperands() == 2);
5386 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5387 "Unsupported CONCAT_VECTORS for value type");
5389 // We support concatenate two MMX registers and place them in a MMX register.
5390 // This is better than doing a stack convert.
5391 if (ResVT.is128BitVector())
5392 return LowerMMXCONCAT_VECTORS(Op, DAG);
5394 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5395 // from two other 128-bit ones.
5396 return LowerAVXCONCAT_VECTORS(Op, DAG);
5399 // Try to lower a shuffle node into a simple blend instruction.
5400 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5401 const X86Subtarget *Subtarget,
5402 SelectionDAG &DAG) {
5403 SDValue V1 = SVOp->getOperand(0);
5404 SDValue V2 = SVOp->getOperand(1);
5405 DebugLoc dl = SVOp->getDebugLoc();
5406 MVT VT = SVOp->getValueType(0).getSimpleVT();
5407 unsigned NumElems = VT.getVectorNumElements();
5409 if (!Subtarget->hasSSE41())
5415 switch (VT.SimpleTy) {
5416 default: return SDValue();
5418 ISDNo = X86ISD::BLENDPW;
5423 ISDNo = X86ISD::BLENDPS;
5428 ISDNo = X86ISD::BLENDPD;
5433 if (!Subtarget->hasAVX())
5435 ISDNo = X86ISD::BLENDPS;
5440 if (!Subtarget->hasAVX())
5442 ISDNo = X86ISD::BLENDPD;
5446 assert(ISDNo && "Invalid Op Number");
5448 unsigned MaskVals = 0;
5450 for (unsigned i = 0; i != NumElems; ++i) {
5451 int EltIdx = SVOp->getMaskElt(i);
5452 if (EltIdx == (int)i || EltIdx < 0)
5454 else if (EltIdx == (int)(i + NumElems))
5455 continue; // Bit is set to zero;
5460 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5461 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5462 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5463 DAG.getConstant(MaskVals, MVT::i32));
5464 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5467 // v8i16 shuffles - Prefer shuffles in the following order:
5468 // 1. [all] pshuflw, pshufhw, optional move
5469 // 2. [ssse3] 1 x pshufb
5470 // 3. [ssse3] 2 x pshufb + 1 x por
5471 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5473 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5474 SelectionDAG &DAG) const {
5475 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5476 SDValue V1 = SVOp->getOperand(0);
5477 SDValue V2 = SVOp->getOperand(1);
5478 DebugLoc dl = SVOp->getDebugLoc();
5479 SmallVector<int, 8> MaskVals;
5481 // Determine if more than 1 of the words in each of the low and high quadwords
5482 // of the result come from the same quadword of one of the two inputs. Undef
5483 // mask values count as coming from any quadword, for better codegen.
5484 unsigned LoQuad[] = { 0, 0, 0, 0 };
5485 unsigned HiQuad[] = { 0, 0, 0, 0 };
5486 std::bitset<4> InputQuads;
5487 for (unsigned i = 0; i < 8; ++i) {
5488 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5489 int EltIdx = SVOp->getMaskElt(i);
5490 MaskVals.push_back(EltIdx);
5499 InputQuads.set(EltIdx / 4);
5502 int BestLoQuad = -1;
5503 unsigned MaxQuad = 1;
5504 for (unsigned i = 0; i < 4; ++i) {
5505 if (LoQuad[i] > MaxQuad) {
5507 MaxQuad = LoQuad[i];
5511 int BestHiQuad = -1;
5513 for (unsigned i = 0; i < 4; ++i) {
5514 if (HiQuad[i] > MaxQuad) {
5516 MaxQuad = HiQuad[i];
5520 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5521 // of the two input vectors, shuffle them into one input vector so only a
5522 // single pshufb instruction is necessary. If There are more than 2 input
5523 // quads, disable the next transformation since it does not help SSSE3.
5524 bool V1Used = InputQuads[0] || InputQuads[1];
5525 bool V2Used = InputQuads[2] || InputQuads[3];
5526 if (Subtarget->hasSSSE3()) {
5527 if (InputQuads.count() == 2 && V1Used && V2Used) {
5528 BestLoQuad = InputQuads[0] ? 0 : 1;
5529 BestHiQuad = InputQuads[2] ? 2 : 3;
5531 if (InputQuads.count() > 2) {
5537 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5538 // the shuffle mask. If a quad is scored as -1, that means that it contains
5539 // words from all 4 input quadwords.
5541 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5543 BestLoQuad < 0 ? 0 : BestLoQuad,
5544 BestHiQuad < 0 ? 1 : BestHiQuad
5546 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5547 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5548 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5549 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5551 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5552 // source words for the shuffle, to aid later transformations.
5553 bool AllWordsInNewV = true;
5554 bool InOrder[2] = { true, true };
5555 for (unsigned i = 0; i != 8; ++i) {
5556 int idx = MaskVals[i];
5558 InOrder[i/4] = false;
5559 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5561 AllWordsInNewV = false;
5565 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5566 if (AllWordsInNewV) {
5567 for (int i = 0; i != 8; ++i) {
5568 int idx = MaskVals[i];
5571 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5572 if ((idx != i) && idx < 4)
5574 if ((idx != i) && idx > 3)
5583 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5584 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5585 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5586 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5587 unsigned TargetMask = 0;
5588 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5589 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5590 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5591 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5592 getShufflePSHUFLWImmediate(SVOp);
5593 V1 = NewV.getOperand(0);
5594 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5598 // If we have SSSE3, and all words of the result are from 1 input vector,
5599 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5600 // is present, fall back to case 4.
5601 if (Subtarget->hasSSSE3()) {
5602 SmallVector<SDValue,16> pshufbMask;
5604 // If we have elements from both input vectors, set the high bit of the
5605 // shuffle mask element to zero out elements that come from V2 in the V1
5606 // mask, and elements that come from V1 in the V2 mask, so that the two
5607 // results can be OR'd together.
5608 bool TwoInputs = V1Used && V2Used;
5609 for (unsigned i = 0; i != 8; ++i) {
5610 int EltIdx = MaskVals[i] * 2;
5611 if (TwoInputs && (EltIdx >= 16)) {
5612 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5613 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5616 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5617 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5619 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5620 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5621 DAG.getNode(ISD::BUILD_VECTOR, dl,
5622 MVT::v16i8, &pshufbMask[0], 16));
5624 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5626 // Calculate the shuffle mask for the second input, shuffle it, and
5627 // OR it with the first shuffled input.
5629 for (unsigned i = 0; i != 8; ++i) {
5630 int EltIdx = MaskVals[i] * 2;
5632 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5633 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5636 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5637 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5639 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5640 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5641 DAG.getNode(ISD::BUILD_VECTOR, dl,
5642 MVT::v16i8, &pshufbMask[0], 16));
5643 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5644 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5647 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5648 // and update MaskVals with new element order.
5649 std::bitset<8> InOrder;
5650 if (BestLoQuad >= 0) {
5651 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5652 for (int i = 0; i != 4; ++i) {
5653 int idx = MaskVals[i];
5656 } else if ((idx / 4) == BestLoQuad) {
5661 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5664 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5665 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5666 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5668 getShufflePSHUFLWImmediate(SVOp), DAG);
5672 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5673 // and update MaskVals with the new element order.
5674 if (BestHiQuad >= 0) {
5675 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5676 for (unsigned i = 4; i != 8; ++i) {
5677 int idx = MaskVals[i];
5680 } else if ((idx / 4) == BestHiQuad) {
5681 MaskV[i] = (idx & 3) + 4;
5685 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5688 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5689 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5690 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5692 getShufflePSHUFHWImmediate(SVOp), DAG);
5696 // In case BestHi & BestLo were both -1, which means each quadword has a word
5697 // from each of the four input quadwords, calculate the InOrder bitvector now
5698 // before falling through to the insert/extract cleanup.
5699 if (BestLoQuad == -1 && BestHiQuad == -1) {
5701 for (int i = 0; i != 8; ++i)
5702 if (MaskVals[i] < 0 || MaskVals[i] == i)
5706 // The other elements are put in the right place using pextrw and pinsrw.
5707 for (unsigned i = 0; i != 8; ++i) {
5710 int EltIdx = MaskVals[i];
5713 SDValue ExtOp = (EltIdx < 8)
5714 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5715 DAG.getIntPtrConstant(EltIdx))
5716 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5717 DAG.getIntPtrConstant(EltIdx - 8));
5718 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5719 DAG.getIntPtrConstant(i));
5724 // v16i8 shuffles - Prefer shuffles in the following order:
5725 // 1. [ssse3] 1 x pshufb
5726 // 2. [ssse3] 2 x pshufb + 1 x por
5727 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5729 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5731 const X86TargetLowering &TLI) {
5732 SDValue V1 = SVOp->getOperand(0);
5733 SDValue V2 = SVOp->getOperand(1);
5734 DebugLoc dl = SVOp->getDebugLoc();
5735 ArrayRef<int> MaskVals = SVOp->getMask();
5737 // If we have SSSE3, case 1 is generated when all result bytes come from
5738 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5739 // present, fall back to case 3.
5740 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5743 for (unsigned i = 0; i < 16; ++i) {
5744 int EltIdx = MaskVals[i];
5753 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5754 if (TLI.getSubtarget()->hasSSSE3()) {
5755 SmallVector<SDValue,16> pshufbMask;
5757 // If all result elements are from one input vector, then only translate
5758 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5760 // Otherwise, we have elements from both input vectors, and must zero out
5761 // elements that come from V2 in the first mask, and V1 in the second mask
5762 // so that we can OR them together.
5763 bool TwoInputs = !(V1Only || V2Only);
5764 for (unsigned i = 0; i != 16; ++i) {
5765 int EltIdx = MaskVals[i];
5766 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5767 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5770 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5772 // If all the elements are from V2, assign it to V1 and return after
5773 // building the first pshufb.
5776 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5777 DAG.getNode(ISD::BUILD_VECTOR, dl,
5778 MVT::v16i8, &pshufbMask[0], 16));
5782 // Calculate the shuffle mask for the second input, shuffle it, and
5783 // OR it with the first shuffled input.
5785 for (unsigned i = 0; i != 16; ++i) {
5786 int EltIdx = MaskVals[i];
5788 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5791 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5793 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5794 DAG.getNode(ISD::BUILD_VECTOR, dl,
5795 MVT::v16i8, &pshufbMask[0], 16));
5796 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5799 // No SSSE3 - Calculate in place words and then fix all out of place words
5800 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5801 // the 16 different words that comprise the two doublequadword input vectors.
5802 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5803 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5804 SDValue NewV = V2Only ? V2 : V1;
5805 for (int i = 0; i != 8; ++i) {
5806 int Elt0 = MaskVals[i*2];
5807 int Elt1 = MaskVals[i*2+1];
5809 // This word of the result is all undef, skip it.
5810 if (Elt0 < 0 && Elt1 < 0)
5813 // This word of the result is already in the correct place, skip it.
5814 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5816 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5819 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5820 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5823 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5824 // using a single extract together, load it and store it.
5825 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5826 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5827 DAG.getIntPtrConstant(Elt1 / 2));
5828 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5829 DAG.getIntPtrConstant(i));
5833 // If Elt1 is defined, extract it from the appropriate source. If the
5834 // source byte is not also odd, shift the extracted word left 8 bits
5835 // otherwise clear the bottom 8 bits if we need to do an or.
5837 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5838 DAG.getIntPtrConstant(Elt1 / 2));
5839 if ((Elt1 & 1) == 0)
5840 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5842 TLI.getShiftAmountTy(InsElt.getValueType())));
5844 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5845 DAG.getConstant(0xFF00, MVT::i16));
5847 // If Elt0 is defined, extract it from the appropriate source. If the
5848 // source byte is not also even, shift the extracted word right 8 bits. If
5849 // Elt1 was also defined, OR the extracted values together before
5850 // inserting them in the result.
5852 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5853 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5854 if ((Elt0 & 1) != 0)
5855 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5857 TLI.getShiftAmountTy(InsElt0.getValueType())));
5859 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5860 DAG.getConstant(0x00FF, MVT::i16));
5861 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5864 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5865 DAG.getIntPtrConstant(i));
5867 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5870 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5871 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5872 /// done when every pair / quad of shuffle mask elements point to elements in
5873 /// the right sequence. e.g.
5874 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5876 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5877 SelectionDAG &DAG, DebugLoc dl) {
5878 EVT VT = SVOp->getValueType(0);
5879 SDValue V1 = SVOp->getOperand(0);
5880 SDValue V2 = SVOp->getOperand(1);
5881 unsigned NumElems = VT.getVectorNumElements();
5882 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5884 switch (VT.getSimpleVT().SimpleTy) {
5885 default: llvm_unreachable("Unexpected!");
5886 case MVT::v4f32: NewVT = MVT::v2f64; break;
5887 case MVT::v4i32: NewVT = MVT::v2i64; break;
5888 case MVT::v8i16: NewVT = MVT::v4i32; break;
5889 case MVT::v16i8: NewVT = MVT::v4i32; break;
5892 int Scale = NumElems / NewWidth;
5893 SmallVector<int, 8> MaskVec;
5894 for (unsigned i = 0; i < NumElems; i += Scale) {
5896 for (int j = 0; j < Scale; ++j) {
5897 int EltIdx = SVOp->getMaskElt(i+j);
5901 StartIdx = EltIdx - (EltIdx % Scale);
5902 if (EltIdx != StartIdx + j)
5906 MaskVec.push_back(-1);
5908 MaskVec.push_back(StartIdx / Scale);
5911 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5912 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5913 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5916 /// getVZextMovL - Return a zero-extending vector move low node.
5918 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5919 SDValue SrcOp, SelectionDAG &DAG,
5920 const X86Subtarget *Subtarget, DebugLoc dl) {
5921 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5922 LoadSDNode *LD = NULL;
5923 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5924 LD = dyn_cast<LoadSDNode>(SrcOp);
5926 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5928 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5929 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5930 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5931 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5932 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5934 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5935 return DAG.getNode(ISD::BITCAST, dl, VT,
5936 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5937 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5945 return DAG.getNode(ISD::BITCAST, dl, VT,
5946 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5947 DAG.getNode(ISD::BITCAST, dl,
5951 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5952 /// which could not be matched by any known target speficic shuffle
5954 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5955 EVT VT = SVOp->getValueType(0);
5957 unsigned NumElems = VT.getVectorNumElements();
5958 unsigned NumLaneElems = NumElems / 2;
5960 DebugLoc dl = SVOp->getDebugLoc();
5961 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5962 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
5965 SmallVector<int, 16> Mask;
5966 for (unsigned l = 0; l < 2; ++l) {
5967 // Build a shuffle mask for the output, discovering on the fly which
5968 // input vectors to use as shuffle operands (recorded in InputUsed).
5969 // If building a suitable shuffle vector proves too hard, then bail
5970 // out with useBuildVector set.
5971 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
5972 unsigned LaneStart = l * NumLaneElems;
5973 for (unsigned i = 0; i != NumLaneElems; ++i) {
5974 // The mask element. This indexes into the input.
5975 int Idx = SVOp->getMaskElt(i+LaneStart);
5977 // the mask element does not index into any input vector.
5982 // The input vector this mask element indexes into.
5983 int Input = Idx / NumLaneElems;
5985 // Turn the index into an offset from the start of the input vector.
5986 Idx -= Input * NumLaneElems;
5988 // Find or create a shuffle vector operand to hold this input.
5990 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
5991 if (InputUsed[OpNo] == Input)
5992 // This input vector is already an operand.
5994 if (InputUsed[OpNo] < 0) {
5995 // Create a new operand for this input vector.
5996 InputUsed[OpNo] = Input;
6001 if (OpNo >= array_lengthof(InputUsed)) {
6002 // More than two input vectors used! Give up.
6006 // Add the mask index for the new shuffle vector.
6007 Mask.push_back(Idx + OpNo * NumLaneElems);
6010 if (InputUsed[0] < 0) {
6011 // No input vectors were used! The result is undefined.
6012 Shufs[l] = DAG.getUNDEF(NVT);
6014 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6015 (InputUsed[0] % 2) * NumLaneElems,
6017 // If only one input was used, use an undefined vector for the other.
6018 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6019 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6020 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6021 // At least one input vector was used. Create a new shuffle vector.
6022 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6028 // Concatenate the result back
6029 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Shufs[0], Shufs[1]);
6032 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6033 /// 4 elements, and match them with several different shuffle types.
6035 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6036 SDValue V1 = SVOp->getOperand(0);
6037 SDValue V2 = SVOp->getOperand(1);
6038 DebugLoc dl = SVOp->getDebugLoc();
6039 EVT VT = SVOp->getValueType(0);
6041 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6043 std::pair<int, int> Locs[4];
6044 int Mask1[] = { -1, -1, -1, -1 };
6045 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6049 for (unsigned i = 0; i != 4; ++i) {
6050 int Idx = PermMask[i];
6052 Locs[i] = std::make_pair(-1, -1);
6054 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6056 Locs[i] = std::make_pair(0, NumLo);
6060 Locs[i] = std::make_pair(1, NumHi);
6062 Mask1[2+NumHi] = Idx;
6068 if (NumLo <= 2 && NumHi <= 2) {
6069 // If no more than two elements come from either vector. This can be
6070 // implemented with two shuffles. First shuffle gather the elements.
6071 // The second shuffle, which takes the first shuffle as both of its
6072 // vector operands, put the elements into the right order.
6073 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6075 int Mask2[] = { -1, -1, -1, -1 };
6077 for (unsigned i = 0; i != 4; ++i)
6078 if (Locs[i].first != -1) {
6079 unsigned Idx = (i < 2) ? 0 : 4;
6080 Idx += Locs[i].first * 2 + Locs[i].second;
6084 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6087 if (NumLo == 3 || NumHi == 3) {
6088 // Otherwise, we must have three elements from one vector, call it X, and
6089 // one element from the other, call it Y. First, use a shufps to build an
6090 // intermediate vector with the one element from Y and the element from X
6091 // that will be in the same half in the final destination (the indexes don't
6092 // matter). Then, use a shufps to build the final vector, taking the half
6093 // containing the element from Y from the intermediate, and the other half
6096 // Normalize it so the 3 elements come from V1.
6097 CommuteVectorShuffleMask(PermMask, 4);
6101 // Find the element from V2.
6103 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6104 int Val = PermMask[HiIndex];
6111 Mask1[0] = PermMask[HiIndex];
6113 Mask1[2] = PermMask[HiIndex^1];
6115 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6118 Mask1[0] = PermMask[0];
6119 Mask1[1] = PermMask[1];
6120 Mask1[2] = HiIndex & 1 ? 6 : 4;
6121 Mask1[3] = HiIndex & 1 ? 4 : 6;
6122 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6125 Mask1[0] = HiIndex & 1 ? 2 : 0;
6126 Mask1[1] = HiIndex & 1 ? 0 : 2;
6127 Mask1[2] = PermMask[2];
6128 Mask1[3] = PermMask[3];
6133 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6136 // Break it into (shuffle shuffle_hi, shuffle_lo).
6137 int LoMask[] = { -1, -1, -1, -1 };
6138 int HiMask[] = { -1, -1, -1, -1 };
6140 int *MaskPtr = LoMask;
6141 unsigned MaskIdx = 0;
6144 for (unsigned i = 0; i != 4; ++i) {
6151 int Idx = PermMask[i];
6153 Locs[i] = std::make_pair(-1, -1);
6154 } else if (Idx < 4) {
6155 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6156 MaskPtr[LoIdx] = Idx;
6159 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6160 MaskPtr[HiIdx] = Idx;
6165 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6166 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6167 int MaskOps[] = { -1, -1, -1, -1 };
6168 for (unsigned i = 0; i != 4; ++i)
6169 if (Locs[i].first != -1)
6170 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6171 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6174 static bool MayFoldVectorLoad(SDValue V) {
6175 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6176 V = V.getOperand(0);
6177 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6178 V = V.getOperand(0);
6179 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6180 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6181 // BUILD_VECTOR (load), undef
6182 V = V.getOperand(0);
6188 // FIXME: the version above should always be used. Since there's
6189 // a bug where several vector shuffles can't be folded because the
6190 // DAG is not updated during lowering and a node claims to have two
6191 // uses while it only has one, use this version, and let isel match
6192 // another instruction if the load really happens to have more than
6193 // one use. Remove this version after this bug get fixed.
6194 // rdar://8434668, PR8156
6195 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6196 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6197 V = V.getOperand(0);
6198 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6199 V = V.getOperand(0);
6200 if (ISD::isNormalLoad(V.getNode()))
6206 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6207 EVT VT = Op.getValueType();
6209 // Canonizalize to v2f64.
6210 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6211 return DAG.getNode(ISD::BITCAST, dl, VT,
6212 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6217 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6219 SDValue V1 = Op.getOperand(0);
6220 SDValue V2 = Op.getOperand(1);
6221 EVT VT = Op.getValueType();
6223 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6225 if (HasSSE2 && VT == MVT::v2f64)
6226 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6228 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6229 return DAG.getNode(ISD::BITCAST, dl, VT,
6230 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6231 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6232 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6236 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6237 SDValue V1 = Op.getOperand(0);
6238 SDValue V2 = Op.getOperand(1);
6239 EVT VT = Op.getValueType();
6241 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6242 "unsupported shuffle type");
6244 if (V2.getOpcode() == ISD::UNDEF)
6248 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6252 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6253 SDValue V1 = Op.getOperand(0);
6254 SDValue V2 = Op.getOperand(1);
6255 EVT VT = Op.getValueType();
6256 unsigned NumElems = VT.getVectorNumElements();
6258 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6259 // operand of these instructions is only memory, so check if there's a
6260 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6262 bool CanFoldLoad = false;
6264 // Trivial case, when V2 comes from a load.
6265 if (MayFoldVectorLoad(V2))
6268 // When V1 is a load, it can be folded later into a store in isel, example:
6269 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6271 // (MOVLPSmr addr:$src1, VR128:$src2)
6272 // So, recognize this potential and also use MOVLPS or MOVLPD
6273 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6276 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6278 if (HasSSE2 && NumElems == 2)
6279 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6282 // If we don't care about the second element, procede to use movss.
6283 if (SVOp->getMaskElt(1) != -1)
6284 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6287 // movl and movlp will both match v2i64, but v2i64 is never matched by
6288 // movl earlier because we make it strict to avoid messing with the movlp load
6289 // folding logic (see the code above getMOVLP call). Match it here then,
6290 // this is horrible, but will stay like this until we move all shuffle
6291 // matching to x86 specific nodes. Note that for the 1st condition all
6292 // types are matched with movsd.
6294 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6295 // as to remove this logic from here, as much as possible
6296 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6297 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6298 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6301 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6303 // Invert the operand order and use SHUFPS to match it.
6304 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6305 getShuffleSHUFImmediate(SVOp), DAG);
6309 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6310 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6311 EVT VT = Op.getValueType();
6312 DebugLoc dl = Op.getDebugLoc();
6313 SDValue V1 = Op.getOperand(0);
6314 SDValue V2 = Op.getOperand(1);
6316 if (isZeroShuffle(SVOp))
6317 return getZeroVector(VT, Subtarget, DAG, dl);
6319 // Handle splat operations
6320 if (SVOp->isSplat()) {
6321 unsigned NumElem = VT.getVectorNumElements();
6322 int Size = VT.getSizeInBits();
6324 // Use vbroadcast whenever the splat comes from a foldable load
6325 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6326 if (Broadcast.getNode())
6329 // Handle splats by matching through known shuffle masks
6330 if ((Size == 128 && NumElem <= 4) ||
6331 (Size == 256 && NumElem < 8))
6334 // All remaning splats are promoted to target supported vector shuffles.
6335 return PromoteSplat(SVOp, DAG);
6338 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6340 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6341 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6342 if (NewOp.getNode())
6343 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6344 } else if ((VT == MVT::v4i32 ||
6345 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6346 // FIXME: Figure out a cleaner way to do this.
6347 // Try to make use of movq to zero out the top part.
6348 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6349 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6350 if (NewOp.getNode()) {
6351 EVT NewVT = NewOp.getValueType();
6352 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6353 NewVT, true, false))
6354 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6355 DAG, Subtarget, dl);
6357 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6358 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6359 if (NewOp.getNode()) {
6360 EVT NewVT = NewOp.getValueType();
6361 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6362 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6363 DAG, Subtarget, dl);
6371 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6372 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6373 SDValue V1 = Op.getOperand(0);
6374 SDValue V2 = Op.getOperand(1);
6375 EVT VT = Op.getValueType();
6376 DebugLoc dl = Op.getDebugLoc();
6377 unsigned NumElems = VT.getVectorNumElements();
6378 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6379 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6380 bool V1IsSplat = false;
6381 bool V2IsSplat = false;
6382 bool HasSSE2 = Subtarget->hasSSE2();
6383 bool HasAVX = Subtarget->hasAVX();
6384 bool HasAVX2 = Subtarget->hasAVX2();
6385 MachineFunction &MF = DAG.getMachineFunction();
6386 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6388 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6390 if (V1IsUndef && V2IsUndef)
6391 return DAG.getUNDEF(VT);
6393 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6395 // Vector shuffle lowering takes 3 steps:
6397 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6398 // narrowing and commutation of operands should be handled.
6399 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6401 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6402 // so the shuffle can be broken into other shuffles and the legalizer can
6403 // try the lowering again.
6405 // The general idea is that no vector_shuffle operation should be left to
6406 // be matched during isel, all of them must be converted to a target specific
6409 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6410 // narrowing and commutation of operands should be handled. The actual code
6411 // doesn't include all of those, work in progress...
6412 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6413 if (NewOp.getNode())
6416 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6418 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6419 // unpckh_undef). Only use pshufd if speed is more important than size.
6420 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6421 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6422 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6423 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6425 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6426 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6427 return getMOVDDup(Op, dl, V1, DAG);
6429 if (isMOVHLPS_v_undef_Mask(M, VT))
6430 return getMOVHighToLow(Op, dl, DAG);
6432 // Use to match splats
6433 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6434 (VT == MVT::v2f64 || VT == MVT::v2i64))
6435 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6437 if (isPSHUFDMask(M, VT)) {
6438 // The actual implementation will match the mask in the if above and then
6439 // during isel it can match several different instructions, not only pshufd
6440 // as its name says, sad but true, emulate the behavior for now...
6441 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6442 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6444 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6446 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6447 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6449 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6450 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6452 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6456 // Check if this can be converted into a logical shift.
6457 bool isLeft = false;
6460 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6461 if (isShift && ShVal.hasOneUse()) {
6462 // If the shifted value has multiple uses, it may be cheaper to use
6463 // v_set0 + movlhps or movhlps, etc.
6464 EVT EltVT = VT.getVectorElementType();
6465 ShAmt *= EltVT.getSizeInBits();
6466 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6469 if (isMOVLMask(M, VT)) {
6470 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6471 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6472 if (!isMOVLPMask(M, VT)) {
6473 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6474 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6476 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6477 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6481 // FIXME: fold these into legal mask.
6482 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6483 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6485 if (isMOVHLPSMask(M, VT))
6486 return getMOVHighToLow(Op, dl, DAG);
6488 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6489 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6491 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6492 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6494 if (isMOVLPMask(M, VT))
6495 return getMOVLP(Op, dl, DAG, HasSSE2);
6497 if (ShouldXformToMOVHLPS(M, VT) ||
6498 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6499 return CommuteVectorShuffle(SVOp, DAG);
6502 // No better options. Use a vshldq / vsrldq.
6503 EVT EltVT = VT.getVectorElementType();
6504 ShAmt *= EltVT.getSizeInBits();
6505 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6508 bool Commuted = false;
6509 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6510 // 1,1,1,1 -> v8i16 though.
6511 V1IsSplat = isSplatVector(V1.getNode());
6512 V2IsSplat = isSplatVector(V2.getNode());
6514 // Canonicalize the splat or undef, if present, to be on the RHS.
6515 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6516 CommuteVectorShuffleMask(M, NumElems);
6518 std::swap(V1IsSplat, V2IsSplat);
6522 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6523 // Shuffling low element of v1 into undef, just return v1.
6526 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6527 // the instruction selector will not match, so get a canonical MOVL with
6528 // swapped operands to undo the commute.
6529 return getMOVL(DAG, dl, VT, V2, V1);
6532 if (isUNPCKLMask(M, VT, HasAVX2))
6533 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6535 if (isUNPCKHMask(M, VT, HasAVX2))
6536 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6539 // Normalize mask so all entries that point to V2 points to its first
6540 // element then try to match unpck{h|l} again. If match, return a
6541 // new vector_shuffle with the corrected mask.p
6542 SmallVector<int, 8> NewMask(M.begin(), M.end());
6543 NormalizeMask(NewMask, NumElems);
6544 if (isUNPCKLMask(NewMask, VT, HasAVX2, true))
6545 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6546 if (isUNPCKHMask(NewMask, VT, HasAVX2, true))
6547 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6551 // Commute is back and try unpck* again.
6552 // FIXME: this seems wrong.
6553 CommuteVectorShuffleMask(M, NumElems);
6555 std::swap(V1IsSplat, V2IsSplat);
6558 if (isUNPCKLMask(M, VT, HasAVX2))
6559 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6561 if (isUNPCKHMask(M, VT, HasAVX2))
6562 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6565 // Normalize the node to match x86 shuffle ops if needed
6566 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6567 return CommuteVectorShuffle(SVOp, DAG);
6569 // The checks below are all present in isShuffleMaskLegal, but they are
6570 // inlined here right now to enable us to directly emit target specific
6571 // nodes, and remove one by one until they don't return Op anymore.
6573 if (isPALIGNRMask(M, VT, Subtarget))
6574 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6575 getShufflePALIGNRImmediate(SVOp),
6578 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6579 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6580 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6581 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6584 if (isPSHUFHWMask(M, VT))
6585 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6586 getShufflePSHUFHWImmediate(SVOp),
6589 if (isPSHUFLWMask(M, VT))
6590 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6591 getShufflePSHUFLWImmediate(SVOp),
6594 if (isSHUFPMask(M, VT, HasAVX))
6595 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6596 getShuffleSHUFImmediate(SVOp), DAG);
6598 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6599 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6600 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6601 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6603 //===--------------------------------------------------------------------===//
6604 // Generate target specific nodes for 128 or 256-bit shuffles only
6605 // supported in the AVX instruction set.
6608 // Handle VMOVDDUPY permutations
6609 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6610 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6612 // Handle VPERMILPS/D* permutations
6613 if (isVPERMILPMask(M, VT, HasAVX)) {
6614 if (HasAVX2 && VT == MVT::v8i32)
6615 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6616 getShuffleSHUFImmediate(SVOp), DAG);
6617 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6618 getShuffleSHUFImmediate(SVOp), DAG);
6621 // Handle VPERM2F128/VPERM2I128 permutations
6622 if (isVPERM2X128Mask(M, VT, HasAVX))
6623 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6624 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6626 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6627 if (BlendOp.getNode())
6630 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6631 SmallVector<SDValue, 8> permclMask;
6632 for (unsigned i = 0; i != 8; ++i) {
6633 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6635 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6637 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6638 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6639 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6642 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6643 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6644 getShuffleCLImmediate(SVOp), DAG);
6647 //===--------------------------------------------------------------------===//
6648 // Since no target specific shuffle was selected for this generic one,
6649 // lower it into other known shuffles. FIXME: this isn't true yet, but
6650 // this is the plan.
6653 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6654 if (VT == MVT::v8i16) {
6655 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6656 if (NewOp.getNode())
6660 if (VT == MVT::v16i8) {
6661 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6662 if (NewOp.getNode())
6666 // Handle all 128-bit wide vectors with 4 elements, and match them with
6667 // several different shuffle types.
6668 if (NumElems == 4 && VT.getSizeInBits() == 128)
6669 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6671 // Handle general 256-bit shuffles
6672 if (VT.is256BitVector())
6673 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6679 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6680 SelectionDAG &DAG) const {
6681 EVT VT = Op.getValueType();
6682 DebugLoc dl = Op.getDebugLoc();
6684 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6687 if (VT.getSizeInBits() == 8) {
6688 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6689 Op.getOperand(0), Op.getOperand(1));
6690 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6691 DAG.getValueType(VT));
6692 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6695 if (VT.getSizeInBits() == 16) {
6696 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6697 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6699 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6700 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6701 DAG.getNode(ISD::BITCAST, dl,
6705 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6706 Op.getOperand(0), Op.getOperand(1));
6707 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6708 DAG.getValueType(VT));
6709 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6712 if (VT == MVT::f32) {
6713 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6714 // the result back to FR32 register. It's only worth matching if the
6715 // result has a single use which is a store or a bitcast to i32. And in
6716 // the case of a store, it's not worth it if the index is a constant 0,
6717 // because a MOVSSmr can be used instead, which is smaller and faster.
6718 if (!Op.hasOneUse())
6720 SDNode *User = *Op.getNode()->use_begin();
6721 if ((User->getOpcode() != ISD::STORE ||
6722 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6723 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6724 (User->getOpcode() != ISD::BITCAST ||
6725 User->getValueType(0) != MVT::i32))
6727 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6728 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6731 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6734 if (VT == MVT::i32 || VT == MVT::i64) {
6735 // ExtractPS/pextrq works with constant index.
6736 if (isa<ConstantSDNode>(Op.getOperand(1)))
6744 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6745 SelectionDAG &DAG) const {
6746 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6749 SDValue Vec = Op.getOperand(0);
6750 EVT VecVT = Vec.getValueType();
6752 // If this is a 256-bit vector result, first extract the 128-bit vector and
6753 // then extract the element from the 128-bit vector.
6754 if (VecVT.getSizeInBits() == 256) {
6755 DebugLoc dl = Op.getNode()->getDebugLoc();
6756 unsigned NumElems = VecVT.getVectorNumElements();
6757 SDValue Idx = Op.getOperand(1);
6758 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6760 // Get the 128-bit vector.
6761 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
6763 if (IdxVal >= NumElems/2)
6764 IdxVal -= NumElems/2;
6765 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6766 DAG.getConstant(IdxVal, MVT::i32));
6769 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6771 if (Subtarget->hasSSE41()) {
6772 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6777 EVT VT = Op.getValueType();
6778 DebugLoc dl = Op.getDebugLoc();
6779 // TODO: handle v16i8.
6780 if (VT.getSizeInBits() == 16) {
6781 SDValue Vec = Op.getOperand(0);
6782 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6784 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6785 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6786 DAG.getNode(ISD::BITCAST, dl,
6789 // Transform it so it match pextrw which produces a 32-bit result.
6790 EVT EltVT = MVT::i32;
6791 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6792 Op.getOperand(0), Op.getOperand(1));
6793 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6794 DAG.getValueType(VT));
6795 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6798 if (VT.getSizeInBits() == 32) {
6799 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6803 // SHUFPS the element to the lowest double word, then movss.
6804 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6805 EVT VVT = Op.getOperand(0).getValueType();
6806 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6807 DAG.getUNDEF(VVT), Mask);
6808 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6809 DAG.getIntPtrConstant(0));
6812 if (VT.getSizeInBits() == 64) {
6813 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6814 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6815 // to match extract_elt for f64.
6816 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6820 // UNPCKHPD the element to the lowest double word, then movsd.
6821 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6822 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6823 int Mask[2] = { 1, -1 };
6824 EVT VVT = Op.getOperand(0).getValueType();
6825 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6826 DAG.getUNDEF(VVT), Mask);
6827 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6828 DAG.getIntPtrConstant(0));
6835 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6836 SelectionDAG &DAG) const {
6837 EVT VT = Op.getValueType();
6838 EVT EltVT = VT.getVectorElementType();
6839 DebugLoc dl = Op.getDebugLoc();
6841 SDValue N0 = Op.getOperand(0);
6842 SDValue N1 = Op.getOperand(1);
6843 SDValue N2 = Op.getOperand(2);
6845 if (VT.getSizeInBits() == 256)
6848 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6849 isa<ConstantSDNode>(N2)) {
6851 if (VT == MVT::v8i16)
6852 Opc = X86ISD::PINSRW;
6853 else if (VT == MVT::v16i8)
6854 Opc = X86ISD::PINSRB;
6856 Opc = X86ISD::PINSRB;
6858 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6860 if (N1.getValueType() != MVT::i32)
6861 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6862 if (N2.getValueType() != MVT::i32)
6863 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6864 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6867 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6868 // Bits [7:6] of the constant are the source select. This will always be
6869 // zero here. The DAG Combiner may combine an extract_elt index into these
6870 // bits. For example (insert (extract, 3), 2) could be matched by putting
6871 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6872 // Bits [5:4] of the constant are the destination select. This is the
6873 // value of the incoming immediate.
6874 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6875 // combine either bitwise AND or insert of float 0.0 to set these bits.
6876 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6877 // Create this as a scalar to vector..
6878 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6879 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6882 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
6883 // PINSR* works with constant index.
6890 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6891 EVT VT = Op.getValueType();
6892 EVT EltVT = VT.getVectorElementType();
6894 DebugLoc dl = Op.getDebugLoc();
6895 SDValue N0 = Op.getOperand(0);
6896 SDValue N1 = Op.getOperand(1);
6897 SDValue N2 = Op.getOperand(2);
6899 // If this is a 256-bit vector result, first extract the 128-bit vector,
6900 // insert the element into the extracted half and then place it back.
6901 if (VT.getSizeInBits() == 256) {
6902 if (!isa<ConstantSDNode>(N2))
6905 // Get the desired 128-bit vector half.
6906 unsigned NumElems = VT.getVectorNumElements();
6907 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6908 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
6910 // Insert the element into the desired half.
6911 bool Upper = IdxVal >= NumElems/2;
6912 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
6913 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
6915 // Insert the changed part back to the 256-bit vector
6916 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
6919 if (Subtarget->hasSSE41())
6920 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6922 if (EltVT == MVT::i8)
6925 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6926 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6927 // as its second argument.
6928 if (N1.getValueType() != MVT::i32)
6929 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6930 if (N2.getValueType() != MVT::i32)
6931 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6932 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6938 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6939 LLVMContext *Context = DAG.getContext();
6940 DebugLoc dl = Op.getDebugLoc();
6941 EVT OpVT = Op.getValueType();
6943 // If this is a 256-bit vector result, first insert into a 128-bit
6944 // vector and then insert into the 256-bit vector.
6945 if (OpVT.getSizeInBits() > 128) {
6946 // Insert into a 128-bit vector.
6947 EVT VT128 = EVT::getVectorVT(*Context,
6948 OpVT.getVectorElementType(),
6949 OpVT.getVectorNumElements() / 2);
6951 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6953 // Insert the 128-bit vector.
6954 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
6957 if (OpVT == MVT::v1i64 &&
6958 Op.getOperand(0).getValueType() == MVT::i64)
6959 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6961 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6962 assert(OpVT.getSizeInBits() == 128 && "Expected an SSE type!");
6963 return DAG.getNode(ISD::BITCAST, dl, OpVT,
6964 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6967 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6968 // a simple subregister reference or explicit instructions to grab
6969 // upper bits of a vector.
6971 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6972 if (Subtarget->hasAVX()) {
6973 DebugLoc dl = Op.getNode()->getDebugLoc();
6974 SDValue Vec = Op.getNode()->getOperand(0);
6975 SDValue Idx = Op.getNode()->getOperand(1);
6977 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 &&
6978 Vec.getNode()->getValueType(0).getSizeInBits() == 256 &&
6979 isa<ConstantSDNode>(Idx)) {
6980 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6981 return Extract128BitVector(Vec, IdxVal, DAG, dl);
6987 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6988 // simple superregister reference or explicit instructions to insert
6989 // the upper bits of a vector.
6991 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6992 if (Subtarget->hasAVX()) {
6993 DebugLoc dl = Op.getNode()->getDebugLoc();
6994 SDValue Vec = Op.getNode()->getOperand(0);
6995 SDValue SubVec = Op.getNode()->getOperand(1);
6996 SDValue Idx = Op.getNode()->getOperand(2);
6998 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 &&
6999 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 &&
7000 isa<ConstantSDNode>(Idx)) {
7001 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7002 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7008 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7009 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7010 // one of the above mentioned nodes. It has to be wrapped because otherwise
7011 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7012 // be used to form addressing mode. These wrapped nodes will be selected
7015 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7016 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7018 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7020 unsigned char OpFlag = 0;
7021 unsigned WrapperKind = X86ISD::Wrapper;
7022 CodeModel::Model M = getTargetMachine().getCodeModel();
7024 if (Subtarget->isPICStyleRIPRel() &&
7025 (M == CodeModel::Small || M == CodeModel::Kernel))
7026 WrapperKind = X86ISD::WrapperRIP;
7027 else if (Subtarget->isPICStyleGOT())
7028 OpFlag = X86II::MO_GOTOFF;
7029 else if (Subtarget->isPICStyleStubPIC())
7030 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7032 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7034 CP->getOffset(), OpFlag);
7035 DebugLoc DL = CP->getDebugLoc();
7036 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7037 // With PIC, the address is actually $g + Offset.
7039 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7040 DAG.getNode(X86ISD::GlobalBaseReg,
7041 DebugLoc(), getPointerTy()),
7048 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7049 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7051 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7053 unsigned char OpFlag = 0;
7054 unsigned WrapperKind = X86ISD::Wrapper;
7055 CodeModel::Model M = getTargetMachine().getCodeModel();
7057 if (Subtarget->isPICStyleRIPRel() &&
7058 (M == CodeModel::Small || M == CodeModel::Kernel))
7059 WrapperKind = X86ISD::WrapperRIP;
7060 else if (Subtarget->isPICStyleGOT())
7061 OpFlag = X86II::MO_GOTOFF;
7062 else if (Subtarget->isPICStyleStubPIC())
7063 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7065 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7067 DebugLoc DL = JT->getDebugLoc();
7068 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7070 // With PIC, the address is actually $g + Offset.
7072 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7073 DAG.getNode(X86ISD::GlobalBaseReg,
7074 DebugLoc(), getPointerTy()),
7081 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7082 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7084 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7086 unsigned char OpFlag = 0;
7087 unsigned WrapperKind = X86ISD::Wrapper;
7088 CodeModel::Model M = getTargetMachine().getCodeModel();
7090 if (Subtarget->isPICStyleRIPRel() &&
7091 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7092 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7093 OpFlag = X86II::MO_GOTPCREL;
7094 WrapperKind = X86ISD::WrapperRIP;
7095 } else if (Subtarget->isPICStyleGOT()) {
7096 OpFlag = X86II::MO_GOT;
7097 } else if (Subtarget->isPICStyleStubPIC()) {
7098 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7099 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7100 OpFlag = X86II::MO_DARWIN_NONLAZY;
7103 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7105 DebugLoc DL = Op.getDebugLoc();
7106 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7109 // With PIC, the address is actually $g + Offset.
7110 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7111 !Subtarget->is64Bit()) {
7112 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7113 DAG.getNode(X86ISD::GlobalBaseReg,
7114 DebugLoc(), getPointerTy()),
7118 // For symbols that require a load from a stub to get the address, emit the
7120 if (isGlobalStubReference(OpFlag))
7121 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7122 MachinePointerInfo::getGOT(), false, false, false, 0);
7128 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7129 // Create the TargetBlockAddressAddress node.
7130 unsigned char OpFlags =
7131 Subtarget->ClassifyBlockAddressReference();
7132 CodeModel::Model M = getTargetMachine().getCodeModel();
7133 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7134 DebugLoc dl = Op.getDebugLoc();
7135 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7136 /*isTarget=*/true, OpFlags);
7138 if (Subtarget->isPICStyleRIPRel() &&
7139 (M == CodeModel::Small || M == CodeModel::Kernel))
7140 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7142 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7144 // With PIC, the address is actually $g + Offset.
7145 if (isGlobalRelativeToPICBase(OpFlags)) {
7146 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7147 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7155 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7157 SelectionDAG &DAG) const {
7158 // Create the TargetGlobalAddress node, folding in the constant
7159 // offset if it is legal.
7160 unsigned char OpFlags =
7161 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7162 CodeModel::Model M = getTargetMachine().getCodeModel();
7164 if (OpFlags == X86II::MO_NO_FLAG &&
7165 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7166 // A direct static reference to a global.
7167 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7170 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7173 if (Subtarget->isPICStyleRIPRel() &&
7174 (M == CodeModel::Small || M == CodeModel::Kernel))
7175 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7177 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7179 // With PIC, the address is actually $g + Offset.
7180 if (isGlobalRelativeToPICBase(OpFlags)) {
7181 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7182 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7186 // For globals that require a load from a stub to get the address, emit the
7188 if (isGlobalStubReference(OpFlags))
7189 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7190 MachinePointerInfo::getGOT(), false, false, false, 0);
7192 // If there was a non-zero offset that we didn't fold, create an explicit
7195 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7196 DAG.getConstant(Offset, getPointerTy()));
7202 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7203 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7204 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7205 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7209 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7210 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7211 unsigned char OperandFlags) {
7212 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7213 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7214 DebugLoc dl = GA->getDebugLoc();
7215 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7216 GA->getValueType(0),
7220 SDValue Ops[] = { Chain, TGA, *InFlag };
7221 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7223 SDValue Ops[] = { Chain, TGA };
7224 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7227 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7228 MFI->setAdjustsStack(true);
7230 SDValue Flag = Chain.getValue(1);
7231 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7234 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7236 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7239 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7240 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7241 DAG.getNode(X86ISD::GlobalBaseReg,
7242 DebugLoc(), PtrVT), InFlag);
7243 InFlag = Chain.getValue(1);
7245 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7248 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7250 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7252 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7253 X86::RAX, X86II::MO_TLSGD);
7256 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7257 // "local exec" model.
7258 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7259 const EVT PtrVT, TLSModel::Model model,
7261 DebugLoc dl = GA->getDebugLoc();
7263 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7264 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7265 is64Bit ? 257 : 256));
7267 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7268 DAG.getIntPtrConstant(0),
7269 MachinePointerInfo(Ptr),
7270 false, false, false, 0);
7272 unsigned char OperandFlags = 0;
7273 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7275 unsigned WrapperKind = X86ISD::Wrapper;
7276 if (model == TLSModel::LocalExec) {
7277 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7278 } else if (is64Bit) {
7279 assert(model == TLSModel::InitialExec);
7280 OperandFlags = X86II::MO_GOTTPOFF;
7281 WrapperKind = X86ISD::WrapperRIP;
7283 assert(model == TLSModel::InitialExec);
7284 OperandFlags = X86II::MO_INDNTPOFF;
7287 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7289 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7290 GA->getValueType(0),
7291 GA->getOffset(), OperandFlags);
7292 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7294 if (model == TLSModel::InitialExec)
7295 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7296 MachinePointerInfo::getGOT(), false, false, false, 0);
7298 // The address of the thread local variable is the add of the thread
7299 // pointer with the offset of the variable.
7300 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7304 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7306 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7307 const GlobalValue *GV = GA->getGlobal();
7309 if (Subtarget->isTargetELF()) {
7310 // TODO: implement the "local dynamic" model
7311 // TODO: implement the "initial exec"model for pic executables
7313 // If GV is an alias then use the aliasee for determining
7314 // thread-localness.
7315 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7316 GV = GA->resolveAliasedGlobal(false);
7318 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7321 case TLSModel::GeneralDynamic:
7322 case TLSModel::LocalDynamic: // not implemented
7323 if (Subtarget->is64Bit())
7324 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7325 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7327 case TLSModel::InitialExec:
7328 case TLSModel::LocalExec:
7329 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7330 Subtarget->is64Bit());
7332 llvm_unreachable("Unknown TLS model.");
7335 if (Subtarget->isTargetDarwin()) {
7336 // Darwin only has one model of TLS. Lower to that.
7337 unsigned char OpFlag = 0;
7338 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7339 X86ISD::WrapperRIP : X86ISD::Wrapper;
7341 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7343 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7344 !Subtarget->is64Bit();
7346 OpFlag = X86II::MO_TLVP_PIC_BASE;
7348 OpFlag = X86II::MO_TLVP;
7349 DebugLoc DL = Op.getDebugLoc();
7350 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7351 GA->getValueType(0),
7352 GA->getOffset(), OpFlag);
7353 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7355 // With PIC32, the address is actually $g + Offset.
7357 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7358 DAG.getNode(X86ISD::GlobalBaseReg,
7359 DebugLoc(), getPointerTy()),
7362 // Lowering the machine isd will make sure everything is in the right
7364 SDValue Chain = DAG.getEntryNode();
7365 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7366 SDValue Args[] = { Chain, Offset };
7367 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7369 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7370 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7371 MFI->setAdjustsStack(true);
7373 // And our return value (tls address) is in the standard call return value
7375 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7376 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7380 if (Subtarget->isTargetWindows()) {
7381 // Just use the implicit TLS architecture
7382 // Need to generate someting similar to:
7383 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7385 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7386 // mov rcx, qword [rdx+rcx*8]
7387 // mov eax, .tls$:tlsvar
7388 // [rax+rcx] contains the address
7389 // Windows 64bit: gs:0x58
7390 // Windows 32bit: fs:__tls_array
7392 // If GV is an alias then use the aliasee for determining
7393 // thread-localness.
7394 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7395 GV = GA->resolveAliasedGlobal(false);
7396 DebugLoc dl = GA->getDebugLoc();
7397 SDValue Chain = DAG.getEntryNode();
7399 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7400 // %gs:0x58 (64-bit).
7401 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7402 ? Type::getInt8PtrTy(*DAG.getContext(),
7404 : Type::getInt32PtrTy(*DAG.getContext(),
7407 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7408 Subtarget->is64Bit()
7409 ? DAG.getIntPtrConstant(0x58)
7410 : DAG.getExternalSymbol("_tls_array",
7412 MachinePointerInfo(Ptr),
7413 false, false, false, 0);
7415 // Load the _tls_index variable
7416 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7417 if (Subtarget->is64Bit())
7418 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7419 IDX, MachinePointerInfo(), MVT::i32,
7422 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7423 false, false, false, 0);
7425 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7427 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7429 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7430 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7431 false, false, false, 0);
7433 // Get the offset of start of .tls section
7434 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7435 GA->getValueType(0),
7436 GA->getOffset(), X86II::MO_SECREL);
7437 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7439 // The address of the thread local variable is the add of the thread
7440 // pointer with the offset of the variable.
7441 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7444 llvm_unreachable("TLS not implemented for this target.");
7448 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7449 /// and take a 2 x i32 value to shift plus a shift amount.
7450 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7451 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7452 EVT VT = Op.getValueType();
7453 unsigned VTBits = VT.getSizeInBits();
7454 DebugLoc dl = Op.getDebugLoc();
7455 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7456 SDValue ShOpLo = Op.getOperand(0);
7457 SDValue ShOpHi = Op.getOperand(1);
7458 SDValue ShAmt = Op.getOperand(2);
7459 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7460 DAG.getConstant(VTBits - 1, MVT::i8))
7461 : DAG.getConstant(0, VT);
7464 if (Op.getOpcode() == ISD::SHL_PARTS) {
7465 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7466 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7468 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7469 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7472 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7473 DAG.getConstant(VTBits, MVT::i8));
7474 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7475 AndNode, DAG.getConstant(0, MVT::i8));
7478 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7479 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7480 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7482 if (Op.getOpcode() == ISD::SHL_PARTS) {
7483 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7484 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7486 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7487 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7490 SDValue Ops[2] = { Lo, Hi };
7491 return DAG.getMergeValues(Ops, 2, dl);
7494 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7495 SelectionDAG &DAG) const {
7496 EVT SrcVT = Op.getOperand(0).getValueType();
7498 if (SrcVT.isVector())
7501 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7502 "Unknown SINT_TO_FP to lower!");
7504 // These are really Legal; return the operand so the caller accepts it as
7506 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7508 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7509 Subtarget->is64Bit()) {
7513 DebugLoc dl = Op.getDebugLoc();
7514 unsigned Size = SrcVT.getSizeInBits()/8;
7515 MachineFunction &MF = DAG.getMachineFunction();
7516 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7517 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7518 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7520 MachinePointerInfo::getFixedStack(SSFI),
7522 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7525 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7527 SelectionDAG &DAG) const {
7529 DebugLoc DL = Op.getDebugLoc();
7531 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7533 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7535 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7537 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7539 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7540 MachineMemOperand *MMO;
7542 int SSFI = FI->getIndex();
7544 DAG.getMachineFunction()
7545 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7546 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7548 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7549 StackSlot = StackSlot.getOperand(1);
7551 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7552 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7554 Tys, Ops, array_lengthof(Ops),
7558 Chain = Result.getValue(1);
7559 SDValue InFlag = Result.getValue(2);
7561 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7562 // shouldn't be necessary except that RFP cannot be live across
7563 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7564 MachineFunction &MF = DAG.getMachineFunction();
7565 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7566 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7567 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7568 Tys = DAG.getVTList(MVT::Other);
7570 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7572 MachineMemOperand *MMO =
7573 DAG.getMachineFunction()
7574 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7575 MachineMemOperand::MOStore, SSFISize, SSFISize);
7577 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7578 Ops, array_lengthof(Ops),
7579 Op.getValueType(), MMO);
7580 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7581 MachinePointerInfo::getFixedStack(SSFI),
7582 false, false, false, 0);
7588 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7589 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7590 SelectionDAG &DAG) const {
7591 // This algorithm is not obvious. Here it is what we're trying to output:
7594 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7595 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7599 pshufd $0x4e, %xmm0, %xmm1
7604 DebugLoc dl = Op.getDebugLoc();
7605 LLVMContext *Context = DAG.getContext();
7607 // Build some magic constants.
7608 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7609 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7610 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7612 SmallVector<Constant*,2> CV1;
7614 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7616 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7617 Constant *C1 = ConstantVector::get(CV1);
7618 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7620 // Load the 64-bit value into an XMM register.
7621 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7623 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7624 MachinePointerInfo::getConstantPool(),
7625 false, false, false, 16);
7626 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7627 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7630 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7631 MachinePointerInfo::getConstantPool(),
7632 false, false, false, 16);
7633 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7634 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7637 if (Subtarget->hasSSE3()) {
7638 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7639 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7641 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7642 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7644 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7645 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7649 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7650 DAG.getIntPtrConstant(0));
7653 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7654 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7655 SelectionDAG &DAG) const {
7656 DebugLoc dl = Op.getDebugLoc();
7657 // FP constant to bias correct the final result.
7658 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7661 // Load the 32-bit value into an XMM register.
7662 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7665 // Zero out the upper parts of the register.
7666 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7668 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7669 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7670 DAG.getIntPtrConstant(0));
7672 // Or the load with the bias.
7673 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7674 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7675 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7677 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7678 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7679 MVT::v2f64, Bias)));
7680 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7681 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7682 DAG.getIntPtrConstant(0));
7684 // Subtract the bias.
7685 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7687 // Handle final rounding.
7688 EVT DestVT = Op.getValueType();
7690 if (DestVT.bitsLT(MVT::f64))
7691 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7692 DAG.getIntPtrConstant(0));
7693 if (DestVT.bitsGT(MVT::f64))
7694 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7696 // Handle final rounding.
7700 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7701 SelectionDAG &DAG) const {
7702 SDValue N0 = Op.getOperand(0);
7703 DebugLoc dl = Op.getDebugLoc();
7705 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7706 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7707 // the optimization here.
7708 if (DAG.SignBitIsZero(N0))
7709 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7711 EVT SrcVT = N0.getValueType();
7712 EVT DstVT = Op.getValueType();
7713 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7714 return LowerUINT_TO_FP_i64(Op, DAG);
7715 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7716 return LowerUINT_TO_FP_i32(Op, DAG);
7717 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
7720 // Make a 64-bit buffer, and use it to build an FILD.
7721 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7722 if (SrcVT == MVT::i32) {
7723 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7724 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7725 getPointerTy(), StackSlot, WordOff);
7726 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7727 StackSlot, MachinePointerInfo(),
7729 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7730 OffsetSlot, MachinePointerInfo(),
7732 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7736 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7737 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7738 StackSlot, MachinePointerInfo(),
7740 // For i64 source, we need to add the appropriate power of 2 if the input
7741 // was negative. This is the same as the optimization in
7742 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7743 // we must be careful to do the computation in x87 extended precision, not
7744 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7745 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7746 MachineMemOperand *MMO =
7747 DAG.getMachineFunction()
7748 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7749 MachineMemOperand::MOLoad, 8, 8);
7751 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7752 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7753 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7756 APInt FF(32, 0x5F800000ULL);
7758 // Check whether the sign bit is set.
7759 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7760 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7763 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7764 SDValue FudgePtr = DAG.getConstantPool(
7765 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7768 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7769 SDValue Zero = DAG.getIntPtrConstant(0);
7770 SDValue Four = DAG.getIntPtrConstant(4);
7771 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7773 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7775 // Load the value out, extending it from f32 to f80.
7776 // FIXME: Avoid the extend by constructing the right constant pool?
7777 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7778 FudgePtr, MachinePointerInfo::getConstantPool(),
7779 MVT::f32, false, false, 4);
7780 // Extend everything to 80 bits to force it to be done on x87.
7781 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7782 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7785 std::pair<SDValue,SDValue> X86TargetLowering::
7786 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7787 DebugLoc DL = Op.getDebugLoc();
7789 EVT DstTy = Op.getValueType();
7791 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7792 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7796 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7797 DstTy.getSimpleVT() >= MVT::i16 &&
7798 "Unknown FP_TO_INT to lower!");
7800 // These are really Legal.
7801 if (DstTy == MVT::i32 &&
7802 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7803 return std::make_pair(SDValue(), SDValue());
7804 if (Subtarget->is64Bit() &&
7805 DstTy == MVT::i64 &&
7806 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7807 return std::make_pair(SDValue(), SDValue());
7809 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7810 // stack slot, or into the FTOL runtime function.
7811 MachineFunction &MF = DAG.getMachineFunction();
7812 unsigned MemSize = DstTy.getSizeInBits()/8;
7813 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7814 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7817 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7818 Opc = X86ISD::WIN_FTOL;
7820 switch (DstTy.getSimpleVT().SimpleTy) {
7821 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7822 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7823 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7824 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7827 SDValue Chain = DAG.getEntryNode();
7828 SDValue Value = Op.getOperand(0);
7829 EVT TheVT = Op.getOperand(0).getValueType();
7830 // FIXME This causes a redundant load/store if the SSE-class value is already
7831 // in memory, such as if it is on the callstack.
7832 if (isScalarFPTypeInSSEReg(TheVT)) {
7833 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7834 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7835 MachinePointerInfo::getFixedStack(SSFI),
7837 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7839 Chain, StackSlot, DAG.getValueType(TheVT)
7842 MachineMemOperand *MMO =
7843 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7844 MachineMemOperand::MOLoad, MemSize, MemSize);
7845 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7847 Chain = Value.getValue(1);
7848 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7849 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7852 MachineMemOperand *MMO =
7853 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7854 MachineMemOperand::MOStore, MemSize, MemSize);
7856 if (Opc != X86ISD::WIN_FTOL) {
7857 // Build the FP_TO_INT*_IN_MEM
7858 SDValue Ops[] = { Chain, Value, StackSlot };
7859 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7860 Ops, 3, DstTy, MMO);
7861 return std::make_pair(FIST, StackSlot);
7863 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7864 DAG.getVTList(MVT::Other, MVT::Glue),
7866 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7867 MVT::i32, ftol.getValue(1));
7868 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7869 MVT::i32, eax.getValue(2));
7870 SDValue Ops[] = { eax, edx };
7871 SDValue pair = IsReplace
7872 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7873 : DAG.getMergeValues(Ops, 2, DL);
7874 return std::make_pair(pair, SDValue());
7878 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7879 SelectionDAG &DAG) const {
7880 if (Op.getValueType().isVector())
7883 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7884 /*IsSigned=*/ true, /*IsReplace=*/ false);
7885 SDValue FIST = Vals.first, StackSlot = Vals.second;
7886 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7887 if (FIST.getNode() == 0) return Op;
7889 if (StackSlot.getNode())
7891 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7892 FIST, StackSlot, MachinePointerInfo(),
7893 false, false, false, 0);
7895 // The node is the result.
7899 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7900 SelectionDAG &DAG) const {
7901 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7902 /*IsSigned=*/ false, /*IsReplace=*/ false);
7903 SDValue FIST = Vals.first, StackSlot = Vals.second;
7904 assert(FIST.getNode() && "Unexpected failure");
7906 if (StackSlot.getNode())
7908 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7909 FIST, StackSlot, MachinePointerInfo(),
7910 false, false, false, 0);
7912 // The node is the result.
7916 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7917 SelectionDAG &DAG) const {
7918 LLVMContext *Context = DAG.getContext();
7919 DebugLoc dl = Op.getDebugLoc();
7920 EVT VT = Op.getValueType();
7923 EltVT = VT.getVectorElementType();
7925 if (EltVT == MVT::f64) {
7926 C = ConstantVector::getSplat(2,
7927 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7929 C = ConstantVector::getSplat(4,
7930 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7932 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7933 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7934 MachinePointerInfo::getConstantPool(),
7935 false, false, false, 16);
7936 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7939 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7940 LLVMContext *Context = DAG.getContext();
7941 DebugLoc dl = Op.getDebugLoc();
7942 EVT VT = Op.getValueType();
7944 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7945 if (VT.isVector()) {
7946 EltVT = VT.getVectorElementType();
7947 NumElts = VT.getVectorNumElements();
7950 if (EltVT == MVT::f64)
7951 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7953 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7954 C = ConstantVector::getSplat(NumElts, C);
7955 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7956 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7957 MachinePointerInfo::getConstantPool(),
7958 false, false, false, 16);
7959 if (VT.isVector()) {
7960 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7961 return DAG.getNode(ISD::BITCAST, dl, VT,
7962 DAG.getNode(ISD::XOR, dl, XORVT,
7963 DAG.getNode(ISD::BITCAST, dl, XORVT,
7965 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7968 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7971 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7972 LLVMContext *Context = DAG.getContext();
7973 SDValue Op0 = Op.getOperand(0);
7974 SDValue Op1 = Op.getOperand(1);
7975 DebugLoc dl = Op.getDebugLoc();
7976 EVT VT = Op.getValueType();
7977 EVT SrcVT = Op1.getValueType();
7979 // If second operand is smaller, extend it first.
7980 if (SrcVT.bitsLT(VT)) {
7981 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7984 // And if it is bigger, shrink it first.
7985 if (SrcVT.bitsGT(VT)) {
7986 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7990 // At this point the operands and the result should have the same
7991 // type, and that won't be f80 since that is not custom lowered.
7993 // First get the sign bit of second operand.
7994 SmallVector<Constant*,4> CV;
7995 if (SrcVT == MVT::f64) {
7996 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7997 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7999 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8000 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8001 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8002 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8004 Constant *C = ConstantVector::get(CV);
8005 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8006 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8007 MachinePointerInfo::getConstantPool(),
8008 false, false, false, 16);
8009 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8011 // Shift sign bit right or left if the two operands have different types.
8012 if (SrcVT.bitsGT(VT)) {
8013 // Op0 is MVT::f32, Op1 is MVT::f64.
8014 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8015 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8016 DAG.getConstant(32, MVT::i32));
8017 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8018 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8019 DAG.getIntPtrConstant(0));
8022 // Clear first operand sign bit.
8024 if (VT == MVT::f64) {
8025 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8026 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8028 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8029 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8030 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8031 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8033 C = ConstantVector::get(CV);
8034 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8035 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8036 MachinePointerInfo::getConstantPool(),
8037 false, false, false, 16);
8038 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8040 // Or the value with the sign bit.
8041 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8044 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8045 SDValue N0 = Op.getOperand(0);
8046 DebugLoc dl = Op.getDebugLoc();
8047 EVT VT = Op.getValueType();
8049 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8050 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8051 DAG.getConstant(1, VT));
8052 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8055 /// Emit nodes that will be selected as "test Op0,Op0", or something
8057 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8058 SelectionDAG &DAG) const {
8059 DebugLoc dl = Op.getDebugLoc();
8061 // CF and OF aren't always set the way we want. Determine which
8062 // of these we need.
8063 bool NeedCF = false;
8064 bool NeedOF = false;
8067 case X86::COND_A: case X86::COND_AE:
8068 case X86::COND_B: case X86::COND_BE:
8071 case X86::COND_G: case X86::COND_GE:
8072 case X86::COND_L: case X86::COND_LE:
8073 case X86::COND_O: case X86::COND_NO:
8078 // See if we can use the EFLAGS value from the operand instead of
8079 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8080 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8081 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8082 // Emit a CMP with 0, which is the TEST pattern.
8083 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8084 DAG.getConstant(0, Op.getValueType()));
8086 unsigned Opcode = 0;
8087 unsigned NumOperands = 0;
8088 switch (Op.getNode()->getOpcode()) {
8090 // Due to an isel shortcoming, be conservative if this add is likely to be
8091 // selected as part of a load-modify-store instruction. When the root node
8092 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8093 // uses of other nodes in the match, such as the ADD in this case. This
8094 // leads to the ADD being left around and reselected, with the result being
8095 // two adds in the output. Alas, even if none our users are stores, that
8096 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8097 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8098 // climbing the DAG back to the root, and it doesn't seem to be worth the
8100 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8101 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8102 if (UI->getOpcode() != ISD::CopyToReg &&
8103 UI->getOpcode() != ISD::SETCC &&
8104 UI->getOpcode() != ISD::STORE)
8107 if (ConstantSDNode *C =
8108 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8109 // An add of one will be selected as an INC.
8110 if (C->getAPIntValue() == 1) {
8111 Opcode = X86ISD::INC;
8116 // An add of negative one (subtract of one) will be selected as a DEC.
8117 if (C->getAPIntValue().isAllOnesValue()) {
8118 Opcode = X86ISD::DEC;
8124 // Otherwise use a regular EFLAGS-setting add.
8125 Opcode = X86ISD::ADD;
8129 // If the primary and result isn't used, don't bother using X86ISD::AND,
8130 // because a TEST instruction will be better.
8131 bool NonFlagUse = false;
8132 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8133 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8135 unsigned UOpNo = UI.getOperandNo();
8136 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8137 // Look pass truncate.
8138 UOpNo = User->use_begin().getOperandNo();
8139 User = *User->use_begin();
8142 if (User->getOpcode() != ISD::BRCOND &&
8143 User->getOpcode() != ISD::SETCC &&
8144 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8157 // Due to the ISEL shortcoming noted above, be conservative if this op is
8158 // likely to be selected as part of a load-modify-store instruction.
8159 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8160 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8161 if (UI->getOpcode() == ISD::STORE)
8164 // Otherwise use a regular EFLAGS-setting instruction.
8165 switch (Op.getNode()->getOpcode()) {
8166 default: llvm_unreachable("unexpected operator!");
8167 case ISD::SUB: Opcode = X86ISD::SUB; break;
8168 case ISD::OR: Opcode = X86ISD::OR; break;
8169 case ISD::XOR: Opcode = X86ISD::XOR; break;
8170 case ISD::AND: Opcode = X86ISD::AND; break;
8182 return SDValue(Op.getNode(), 1);
8189 // Emit a CMP with 0, which is the TEST pattern.
8190 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8191 DAG.getConstant(0, Op.getValueType()));
8193 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8194 SmallVector<SDValue, 4> Ops;
8195 for (unsigned i = 0; i != NumOperands; ++i)
8196 Ops.push_back(Op.getOperand(i));
8198 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8199 DAG.ReplaceAllUsesWith(Op, New);
8200 return SDValue(New.getNode(), 1);
8203 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8205 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8206 SelectionDAG &DAG) const {
8207 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8208 if (C->getAPIntValue() == 0)
8209 return EmitTest(Op0, X86CC, DAG);
8211 DebugLoc dl = Op0.getDebugLoc();
8212 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8215 /// Convert a comparison if required by the subtarget.
8216 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
8217 SelectionDAG &DAG) const {
8218 // If the subtarget does not support the FUCOMI instruction, floating-point
8219 // comparisons have to be converted.
8220 if (Subtarget->hasCMov() ||
8221 Cmp.getOpcode() != X86ISD::CMP ||
8222 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
8223 !Cmp.getOperand(1).getValueType().isFloatingPoint())
8226 // The instruction selector will select an FUCOM instruction instead of
8227 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8228 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8229 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
8230 DebugLoc dl = Cmp.getDebugLoc();
8231 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
8232 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
8233 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
8234 DAG.getConstant(8, MVT::i8));
8235 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
8236 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
8239 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8240 /// if it's possible.
8241 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8242 DebugLoc dl, SelectionDAG &DAG) const {
8243 SDValue Op0 = And.getOperand(0);
8244 SDValue Op1 = And.getOperand(1);
8245 if (Op0.getOpcode() == ISD::TRUNCATE)
8246 Op0 = Op0.getOperand(0);
8247 if (Op1.getOpcode() == ISD::TRUNCATE)
8248 Op1 = Op1.getOperand(0);
8251 if (Op1.getOpcode() == ISD::SHL)
8252 std::swap(Op0, Op1);
8253 if (Op0.getOpcode() == ISD::SHL) {
8254 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8255 if (And00C->getZExtValue() == 1) {
8256 // If we looked past a truncate, check that it's only truncating away
8258 unsigned BitWidth = Op0.getValueSizeInBits();
8259 unsigned AndBitWidth = And.getValueSizeInBits();
8260 if (BitWidth > AndBitWidth) {
8262 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8263 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8267 RHS = Op0.getOperand(1);
8269 } else if (Op1.getOpcode() == ISD::Constant) {
8270 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8271 uint64_t AndRHSVal = AndRHS->getZExtValue();
8272 SDValue AndLHS = Op0;
8274 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8275 LHS = AndLHS.getOperand(0);
8276 RHS = AndLHS.getOperand(1);
8279 // Use BT if the immediate can't be encoded in a TEST instruction.
8280 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8282 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8286 if (LHS.getNode()) {
8287 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8288 // instruction. Since the shift amount is in-range-or-undefined, we know
8289 // that doing a bittest on the i32 value is ok. We extend to i32 because
8290 // the encoding for the i16 version is larger than the i32 version.
8291 // Also promote i16 to i32 for performance / code size reason.
8292 if (LHS.getValueType() == MVT::i8 ||
8293 LHS.getValueType() == MVT::i16)
8294 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8296 // If the operand types disagree, extend the shift amount to match. Since
8297 // BT ignores high bits (like shifts) we can use anyextend.
8298 if (LHS.getValueType() != RHS.getValueType())
8299 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8301 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8302 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8303 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8304 DAG.getConstant(Cond, MVT::i8), BT);
8310 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8312 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8314 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8315 SDValue Op0 = Op.getOperand(0);
8316 SDValue Op1 = Op.getOperand(1);
8317 DebugLoc dl = Op.getDebugLoc();
8318 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8320 // Optimize to BT if possible.
8321 // Lower (X & (1 << N)) == 0 to BT(X, N).
8322 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8323 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8324 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8325 Op1.getOpcode() == ISD::Constant &&
8326 cast<ConstantSDNode>(Op1)->isNullValue() &&
8327 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8328 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8329 if (NewSetCC.getNode())
8333 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8335 if (Op1.getOpcode() == ISD::Constant &&
8336 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8337 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8338 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8340 // If the input is a setcc, then reuse the input setcc or use a new one with
8341 // the inverted condition.
8342 if (Op0.getOpcode() == X86ISD::SETCC) {
8343 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8344 bool Invert = (CC == ISD::SETNE) ^
8345 cast<ConstantSDNode>(Op1)->isNullValue();
8346 if (!Invert) return Op0;
8348 CCode = X86::GetOppositeBranchCondition(CCode);
8349 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8350 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8354 bool isFP = Op1.getValueType().isFloatingPoint();
8355 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8356 if (X86CC == X86::COND_INVALID)
8359 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8360 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
8361 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8362 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8365 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8366 // ones, and then concatenate the result back.
8367 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8368 EVT VT = Op.getValueType();
8370 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8371 "Unsupported value type for operation");
8373 unsigned NumElems = VT.getVectorNumElements();
8374 DebugLoc dl = Op.getDebugLoc();
8375 SDValue CC = Op.getOperand(2);
8377 // Extract the LHS vectors
8378 SDValue LHS = Op.getOperand(0);
8379 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8380 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8382 // Extract the RHS vectors
8383 SDValue RHS = Op.getOperand(1);
8384 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8385 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8387 // Issue the operation on the smaller types and concatenate the result back
8388 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8389 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8390 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8391 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8392 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8396 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8398 SDValue Op0 = Op.getOperand(0);
8399 SDValue Op1 = Op.getOperand(1);
8400 SDValue CC = Op.getOperand(2);
8401 EVT VT = Op.getValueType();
8402 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8403 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8404 DebugLoc dl = Op.getDebugLoc();
8408 EVT EltVT = Op0.getValueType().getVectorElementType();
8409 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8413 // SSE Condition code mapping:
8422 switch (SetCCOpcode) {
8425 case ISD::SETEQ: SSECC = 0; break;
8427 case ISD::SETGT: Swap = true; // Fallthrough
8429 case ISD::SETOLT: SSECC = 1; break;
8431 case ISD::SETGE: Swap = true; // Fallthrough
8433 case ISD::SETOLE: SSECC = 2; break;
8434 case ISD::SETUO: SSECC = 3; break;
8436 case ISD::SETNE: SSECC = 4; break;
8437 case ISD::SETULE: Swap = true;
8438 case ISD::SETUGE: SSECC = 5; break;
8439 case ISD::SETULT: Swap = true;
8440 case ISD::SETUGT: SSECC = 6; break;
8441 case ISD::SETO: SSECC = 7; break;
8444 std::swap(Op0, Op1);
8446 // In the two special cases we can't handle, emit two comparisons.
8448 if (SetCCOpcode == ISD::SETUEQ) {
8450 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8451 DAG.getConstant(3, MVT::i8));
8452 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8453 DAG.getConstant(0, MVT::i8));
8454 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8456 if (SetCCOpcode == ISD::SETONE) {
8458 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8459 DAG.getConstant(7, MVT::i8));
8460 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8461 DAG.getConstant(4, MVT::i8));
8462 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8464 llvm_unreachable("Illegal FP comparison");
8466 // Handle all other FP comparisons here.
8467 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8468 DAG.getConstant(SSECC, MVT::i8));
8471 // Break 256-bit integer vector compare into smaller ones.
8472 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8473 return Lower256IntVSETCC(Op, DAG);
8475 // We are handling one of the integer comparisons here. Since SSE only has
8476 // GT and EQ comparisons for integer, swapping operands and multiple
8477 // operations may be required for some comparisons.
8479 bool Swap = false, Invert = false, FlipSigns = false;
8481 switch (SetCCOpcode) {
8483 case ISD::SETNE: Invert = true;
8484 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8485 case ISD::SETLT: Swap = true;
8486 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8487 case ISD::SETGE: Swap = true;
8488 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8489 case ISD::SETULT: Swap = true;
8490 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8491 case ISD::SETUGE: Swap = true;
8492 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8495 std::swap(Op0, Op1);
8497 // Check that the operation in question is available (most are plain SSE2,
8498 // but PCMPGTQ and PCMPEQQ have different requirements).
8499 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8501 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8504 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8505 // bits of the inputs before performing those operations.
8507 EVT EltVT = VT.getVectorElementType();
8508 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8510 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8511 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8513 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8514 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8517 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8519 // If the logical-not of the result is required, perform that now.
8521 Result = DAG.getNOT(dl, Result, VT);
8526 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8527 static bool isX86LogicalCmp(SDValue Op) {
8528 unsigned Opc = Op.getNode()->getOpcode();
8529 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
8530 Opc == X86ISD::SAHF)
8532 if (Op.getResNo() == 1 &&
8533 (Opc == X86ISD::ADD ||
8534 Opc == X86ISD::SUB ||
8535 Opc == X86ISD::ADC ||
8536 Opc == X86ISD::SBB ||
8537 Opc == X86ISD::SMUL ||
8538 Opc == X86ISD::UMUL ||
8539 Opc == X86ISD::INC ||
8540 Opc == X86ISD::DEC ||
8541 Opc == X86ISD::OR ||
8542 Opc == X86ISD::XOR ||
8543 Opc == X86ISD::AND))
8546 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8552 static bool isZero(SDValue V) {
8553 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8554 return C && C->isNullValue();
8557 static bool isAllOnes(SDValue V) {
8558 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8559 return C && C->isAllOnesValue();
8562 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8563 bool addTest = true;
8564 SDValue Cond = Op.getOperand(0);
8565 SDValue Op1 = Op.getOperand(1);
8566 SDValue Op2 = Op.getOperand(2);
8567 DebugLoc DL = Op.getDebugLoc();
8570 if (Cond.getOpcode() == ISD::SETCC) {
8571 SDValue NewCond = LowerSETCC(Cond, DAG);
8572 if (NewCond.getNode())
8576 // Handle the following cases related to max and min:
8577 // (a > b) ? (a-b) : 0
8578 // (a >= b) ? (a-b) : 0
8579 // (b < a) ? (a-b) : 0
8580 // (b <= a) ? (a-b) : 0
8581 // Comparison is removed to use EFLAGS from SUB.
8582 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2))
8583 if (Cond.getOpcode() == X86ISD::SETCC &&
8584 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8585 (Op1.getOpcode() == ISD::SUB || Op1.getOpcode() == X86ISD::SUB) &&
8586 C->getAPIntValue() == 0) {
8587 SDValue Cmp = Cond.getOperand(1);
8588 unsigned CC = cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8589 if ((DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(0)) &&
8590 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(1)) &&
8591 (CC == X86::COND_G || CC == X86::COND_GE ||
8592 CC == X86::COND_A || CC == X86::COND_AE)) ||
8593 (DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(1)) &&
8594 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(0)) &&
8595 (CC == X86::COND_L || CC == X86::COND_LE ||
8596 CC == X86::COND_B || CC == X86::COND_BE))) {
8598 if (Op1.getOpcode() == ISD::SUB) {
8599 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i32);
8600 SDValue New = DAG.getNode(X86ISD::SUB, DL, VTs,
8601 Op1.getOperand(0), Op1.getOperand(1));
8602 DAG.ReplaceAllUsesWith(Op1, New);
8606 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8607 unsigned NewCC = (CC == X86::COND_G || CC == X86::COND_GE ||
8608 CC == X86::COND_L ||
8609 CC == X86::COND_LE) ? X86::COND_GE : X86::COND_AE;
8610 SDValue Ops[] = { Op2, Op1, DAG.getConstant(NewCC, MVT::i8),
8611 SDValue(Op1.getNode(), 1) };
8612 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8616 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8617 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8618 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8619 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8620 if (Cond.getOpcode() == X86ISD::SETCC &&
8621 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8622 isZero(Cond.getOperand(1).getOperand(1))) {
8623 SDValue Cmp = Cond.getOperand(1);
8625 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8627 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8628 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8629 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8631 SDValue CmpOp0 = Cmp.getOperand(0);
8632 // further optimization for special cases
8633 // (select (x != 0), -1, 0) -> neg & sbb
8634 // (select (x == 0), 0, -1) -> neg & sbb
8635 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
8636 if (YC->isNullValue() &&
8637 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
8638 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
8639 SDValue Neg = DAG.getNode(ISD::SUB, DL, VTs,
8640 DAG.getConstant(0, CmpOp0.getValueType()),
8642 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8643 DAG.getConstant(X86::COND_B, MVT::i8),
8644 SDValue(Neg.getNode(), 1));
8648 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8649 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8650 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8652 SDValue Res = // Res = 0 or -1.
8653 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8654 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8656 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8657 Res = DAG.getNOT(DL, Res, Res.getValueType());
8659 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8660 if (N2C == 0 || !N2C->isNullValue())
8661 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8666 // Look past (and (setcc_carry (cmp ...)), 1).
8667 if (Cond.getOpcode() == ISD::AND &&
8668 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8669 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8670 if (C && C->getAPIntValue() == 1)
8671 Cond = Cond.getOperand(0);
8674 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8675 // setting operand in place of the X86ISD::SETCC.
8676 unsigned CondOpcode = Cond.getOpcode();
8677 if (CondOpcode == X86ISD::SETCC ||
8678 CondOpcode == X86ISD::SETCC_CARRY) {
8679 CC = Cond.getOperand(0);
8681 SDValue Cmp = Cond.getOperand(1);
8682 unsigned Opc = Cmp.getOpcode();
8683 EVT VT = Op.getValueType();
8685 bool IllegalFPCMov = false;
8686 if (VT.isFloatingPoint() && !VT.isVector() &&
8687 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8688 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8690 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8691 Opc == X86ISD::BT) { // FIXME
8695 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8696 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8697 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8698 Cond.getOperand(0).getValueType() != MVT::i8)) {
8699 SDValue LHS = Cond.getOperand(0);
8700 SDValue RHS = Cond.getOperand(1);
8704 switch (CondOpcode) {
8705 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8706 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8707 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8708 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8709 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8710 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8711 default: llvm_unreachable("unexpected overflowing operator");
8713 if (CondOpcode == ISD::UMULO)
8714 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8717 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8719 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8721 if (CondOpcode == ISD::UMULO)
8722 Cond = X86Op.getValue(2);
8724 Cond = X86Op.getValue(1);
8726 CC = DAG.getConstant(X86Cond, MVT::i8);
8731 // Look pass the truncate.
8732 if (Cond.getOpcode() == ISD::TRUNCATE)
8733 Cond = Cond.getOperand(0);
8735 // We know the result of AND is compared against zero. Try to match
8737 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8738 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8739 if (NewSetCC.getNode()) {
8740 CC = NewSetCC.getOperand(0);
8741 Cond = NewSetCC.getOperand(1);
8748 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8749 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8752 // a < b ? -1 : 0 -> RES = ~setcc_carry
8753 // a < b ? 0 : -1 -> RES = setcc_carry
8754 // a >= b ? -1 : 0 -> RES = setcc_carry
8755 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8756 if (Cond.getOpcode() == X86ISD::CMP) {
8757 Cond = ConvertCmpIfNecessary(Cond, DAG);
8758 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8760 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8761 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8762 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8763 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8764 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8765 return DAG.getNOT(DL, Res, Res.getValueType());
8770 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8771 // condition is true.
8772 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8773 SDValue Ops[] = { Op2, Op1, CC, Cond };
8774 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8777 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8778 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8779 // from the AND / OR.
8780 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8781 Opc = Op.getOpcode();
8782 if (Opc != ISD::OR && Opc != ISD::AND)
8784 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8785 Op.getOperand(0).hasOneUse() &&
8786 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8787 Op.getOperand(1).hasOneUse());
8790 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8791 // 1 and that the SETCC node has a single use.
8792 static bool isXor1OfSetCC(SDValue Op) {
8793 if (Op.getOpcode() != ISD::XOR)
8795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8796 if (N1C && N1C->getAPIntValue() == 1) {
8797 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8798 Op.getOperand(0).hasOneUse();
8803 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8804 bool addTest = true;
8805 SDValue Chain = Op.getOperand(0);
8806 SDValue Cond = Op.getOperand(1);
8807 SDValue Dest = Op.getOperand(2);
8808 DebugLoc dl = Op.getDebugLoc();
8810 bool Inverted = false;
8812 if (Cond.getOpcode() == ISD::SETCC) {
8813 // Check for setcc([su]{add,sub,mul}o == 0).
8814 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8815 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8816 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8817 Cond.getOperand(0).getResNo() == 1 &&
8818 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8819 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8820 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8821 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8822 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8823 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8825 Cond = Cond.getOperand(0);
8827 SDValue NewCond = LowerSETCC(Cond, DAG);
8828 if (NewCond.getNode())
8833 // FIXME: LowerXALUO doesn't handle these!!
8834 else if (Cond.getOpcode() == X86ISD::ADD ||
8835 Cond.getOpcode() == X86ISD::SUB ||
8836 Cond.getOpcode() == X86ISD::SMUL ||
8837 Cond.getOpcode() == X86ISD::UMUL)
8838 Cond = LowerXALUO(Cond, DAG);
8841 // Look pass (and (setcc_carry (cmp ...)), 1).
8842 if (Cond.getOpcode() == ISD::AND &&
8843 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8844 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8845 if (C && C->getAPIntValue() == 1)
8846 Cond = Cond.getOperand(0);
8849 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8850 // setting operand in place of the X86ISD::SETCC.
8851 unsigned CondOpcode = Cond.getOpcode();
8852 if (CondOpcode == X86ISD::SETCC ||
8853 CondOpcode == X86ISD::SETCC_CARRY) {
8854 CC = Cond.getOperand(0);
8856 SDValue Cmp = Cond.getOperand(1);
8857 unsigned Opc = Cmp.getOpcode();
8858 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8859 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8863 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8867 // These can only come from an arithmetic instruction with overflow,
8868 // e.g. SADDO, UADDO.
8869 Cond = Cond.getNode()->getOperand(1);
8875 CondOpcode = Cond.getOpcode();
8876 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8877 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8878 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8879 Cond.getOperand(0).getValueType() != MVT::i8)) {
8880 SDValue LHS = Cond.getOperand(0);
8881 SDValue RHS = Cond.getOperand(1);
8885 switch (CondOpcode) {
8886 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8887 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8888 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8889 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8890 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8891 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8892 default: llvm_unreachable("unexpected overflowing operator");
8895 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8896 if (CondOpcode == ISD::UMULO)
8897 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8900 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8902 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8904 if (CondOpcode == ISD::UMULO)
8905 Cond = X86Op.getValue(2);
8907 Cond = X86Op.getValue(1);
8909 CC = DAG.getConstant(X86Cond, MVT::i8);
8913 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8914 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8915 if (CondOpc == ISD::OR) {
8916 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8917 // two branches instead of an explicit OR instruction with a
8919 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8920 isX86LogicalCmp(Cmp)) {
8921 CC = Cond.getOperand(0).getOperand(0);
8922 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8923 Chain, Dest, CC, Cmp);
8924 CC = Cond.getOperand(1).getOperand(0);
8928 } else { // ISD::AND
8929 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8930 // two branches instead of an explicit AND instruction with a
8931 // separate test. However, we only do this if this block doesn't
8932 // have a fall-through edge, because this requires an explicit
8933 // jmp when the condition is false.
8934 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8935 isX86LogicalCmp(Cmp) &&
8936 Op.getNode()->hasOneUse()) {
8937 X86::CondCode CCode =
8938 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8939 CCode = X86::GetOppositeBranchCondition(CCode);
8940 CC = DAG.getConstant(CCode, MVT::i8);
8941 SDNode *User = *Op.getNode()->use_begin();
8942 // Look for an unconditional branch following this conditional branch.
8943 // We need this because we need to reverse the successors in order
8944 // to implement FCMP_OEQ.
8945 if (User->getOpcode() == ISD::BR) {
8946 SDValue FalseBB = User->getOperand(1);
8948 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8949 assert(NewBR == User);
8953 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8954 Chain, Dest, CC, Cmp);
8955 X86::CondCode CCode =
8956 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8957 CCode = X86::GetOppositeBranchCondition(CCode);
8958 CC = DAG.getConstant(CCode, MVT::i8);
8964 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8965 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8966 // It should be transformed during dag combiner except when the condition
8967 // is set by a arithmetics with overflow node.
8968 X86::CondCode CCode =
8969 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8970 CCode = X86::GetOppositeBranchCondition(CCode);
8971 CC = DAG.getConstant(CCode, MVT::i8);
8972 Cond = Cond.getOperand(0).getOperand(1);
8974 } else if (Cond.getOpcode() == ISD::SETCC &&
8975 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8976 // For FCMP_OEQ, we can emit
8977 // two branches instead of an explicit AND instruction with a
8978 // separate test. However, we only do this if this block doesn't
8979 // have a fall-through edge, because this requires an explicit
8980 // jmp when the condition is false.
8981 if (Op.getNode()->hasOneUse()) {
8982 SDNode *User = *Op.getNode()->use_begin();
8983 // Look for an unconditional branch following this conditional branch.
8984 // We need this because we need to reverse the successors in order
8985 // to implement FCMP_OEQ.
8986 if (User->getOpcode() == ISD::BR) {
8987 SDValue FalseBB = User->getOperand(1);
8989 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8990 assert(NewBR == User);
8994 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8995 Cond.getOperand(0), Cond.getOperand(1));
8996 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8997 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8998 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8999 Chain, Dest, CC, Cmp);
9000 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9005 } else if (Cond.getOpcode() == ISD::SETCC &&
9006 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9007 // For FCMP_UNE, we can emit
9008 // two branches instead of an explicit AND instruction with a
9009 // separate test. However, we only do this if this block doesn't
9010 // have a fall-through edge, because this requires an explicit
9011 // jmp when the condition is false.
9012 if (Op.getNode()->hasOneUse()) {
9013 SDNode *User = *Op.getNode()->use_begin();
9014 // Look for an unconditional branch following this conditional branch.
9015 // We need this because we need to reverse the successors in order
9016 // to implement FCMP_UNE.
9017 if (User->getOpcode() == ISD::BR) {
9018 SDValue FalseBB = User->getOperand(1);
9020 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9021 assert(NewBR == User);
9024 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9025 Cond.getOperand(0), Cond.getOperand(1));
9026 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9027 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9028 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9029 Chain, Dest, CC, Cmp);
9030 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9040 // Look pass the truncate.
9041 if (Cond.getOpcode() == ISD::TRUNCATE)
9042 Cond = Cond.getOperand(0);
9044 // We know the result of AND is compared against zero. Try to match
9046 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9047 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9048 if (NewSetCC.getNode()) {
9049 CC = NewSetCC.getOperand(0);
9050 Cond = NewSetCC.getOperand(1);
9057 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9058 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9060 Cond = ConvertCmpIfNecessary(Cond, DAG);
9061 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9062 Chain, Dest, CC, Cond);
9066 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9067 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9068 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9069 // that the guard pages used by the OS virtual memory manager are allocated in
9070 // correct sequence.
9072 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9073 SelectionDAG &DAG) const {
9074 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9075 getTargetMachine().Options.EnableSegmentedStacks) &&
9076 "This should be used only on Windows targets or when segmented stacks "
9078 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9079 DebugLoc dl = Op.getDebugLoc();
9082 SDValue Chain = Op.getOperand(0);
9083 SDValue Size = Op.getOperand(1);
9084 // FIXME: Ensure alignment here
9086 bool Is64Bit = Subtarget->is64Bit();
9087 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9089 if (getTargetMachine().Options.EnableSegmentedStacks) {
9090 MachineFunction &MF = DAG.getMachineFunction();
9091 MachineRegisterInfo &MRI = MF.getRegInfo();
9094 // The 64 bit implementation of segmented stacks needs to clobber both r10
9095 // r11. This makes it impossible to use it along with nested parameters.
9096 const Function *F = MF.getFunction();
9098 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9100 if (I->hasNestAttr())
9101 report_fatal_error("Cannot use segmented stacks with functions that "
9102 "have nested arguments.");
9105 const TargetRegisterClass *AddrRegClass =
9106 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9107 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9108 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9109 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9110 DAG.getRegister(Vreg, SPTy));
9111 SDValue Ops1[2] = { Value, Chain };
9112 return DAG.getMergeValues(Ops1, 2, dl);
9115 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9117 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9118 Flag = Chain.getValue(1);
9119 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9121 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9122 Flag = Chain.getValue(1);
9124 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9126 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9127 return DAG.getMergeValues(Ops1, 2, dl);
9131 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9132 MachineFunction &MF = DAG.getMachineFunction();
9133 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9135 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9136 DebugLoc DL = Op.getDebugLoc();
9138 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9139 // vastart just stores the address of the VarArgsFrameIndex slot into the
9140 // memory location argument.
9141 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9143 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9144 MachinePointerInfo(SV), false, false, 0);
9148 // gp_offset (0 - 6 * 8)
9149 // fp_offset (48 - 48 + 8 * 16)
9150 // overflow_arg_area (point to parameters coming in memory).
9152 SmallVector<SDValue, 8> MemOps;
9153 SDValue FIN = Op.getOperand(1);
9155 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9156 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9158 FIN, MachinePointerInfo(SV), false, false, 0);
9159 MemOps.push_back(Store);
9162 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9163 FIN, DAG.getIntPtrConstant(4));
9164 Store = DAG.getStore(Op.getOperand(0), DL,
9165 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9167 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9168 MemOps.push_back(Store);
9170 // Store ptr to overflow_arg_area
9171 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9172 FIN, DAG.getIntPtrConstant(4));
9173 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9175 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9176 MachinePointerInfo(SV, 8),
9178 MemOps.push_back(Store);
9180 // Store ptr to reg_save_area.
9181 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9182 FIN, DAG.getIntPtrConstant(8));
9183 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9185 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9186 MachinePointerInfo(SV, 16), false, false, 0);
9187 MemOps.push_back(Store);
9188 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9189 &MemOps[0], MemOps.size());
9192 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9193 assert(Subtarget->is64Bit() &&
9194 "LowerVAARG only handles 64-bit va_arg!");
9195 assert((Subtarget->isTargetLinux() ||
9196 Subtarget->isTargetDarwin()) &&
9197 "Unhandled target in LowerVAARG");
9198 assert(Op.getNode()->getNumOperands() == 4);
9199 SDValue Chain = Op.getOperand(0);
9200 SDValue SrcPtr = Op.getOperand(1);
9201 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9202 unsigned Align = Op.getConstantOperandVal(3);
9203 DebugLoc dl = Op.getDebugLoc();
9205 EVT ArgVT = Op.getNode()->getValueType(0);
9206 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9207 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9210 // Decide which area this value should be read from.
9211 // TODO: Implement the AMD64 ABI in its entirety. This simple
9212 // selection mechanism works only for the basic types.
9213 if (ArgVT == MVT::f80) {
9214 llvm_unreachable("va_arg for f80 not yet implemented");
9215 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9216 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9217 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9218 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9220 llvm_unreachable("Unhandled argument type in LowerVAARG");
9224 // Sanity Check: Make sure using fp_offset makes sense.
9225 assert(!getTargetMachine().Options.UseSoftFloat &&
9226 !(DAG.getMachineFunction()
9227 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9228 Subtarget->hasSSE1());
9231 // Insert VAARG_64 node into the DAG
9232 // VAARG_64 returns two values: Variable Argument Address, Chain
9233 SmallVector<SDValue, 11> InstOps;
9234 InstOps.push_back(Chain);
9235 InstOps.push_back(SrcPtr);
9236 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9237 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9238 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9239 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9240 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9241 VTs, &InstOps[0], InstOps.size(),
9243 MachinePointerInfo(SV),
9248 Chain = VAARG.getValue(1);
9250 // Load the next argument and return it
9251 return DAG.getLoad(ArgVT, dl,
9254 MachinePointerInfo(),
9255 false, false, false, 0);
9258 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9259 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9260 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9261 SDValue Chain = Op.getOperand(0);
9262 SDValue DstPtr = Op.getOperand(1);
9263 SDValue SrcPtr = Op.getOperand(2);
9264 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9265 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9266 DebugLoc DL = Op.getDebugLoc();
9268 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9269 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9271 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9274 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9275 // may or may not be a constant. Takes immediate version of shift as input.
9276 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9277 SDValue SrcOp, SDValue ShAmt,
9278 SelectionDAG &DAG) {
9279 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9281 if (isa<ConstantSDNode>(ShAmt)) {
9283 default: llvm_unreachable("Unknown target vector shift node");
9287 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9291 // Change opcode to non-immediate version
9293 default: llvm_unreachable("Unknown target vector shift node");
9294 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9295 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9296 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9299 // Need to build a vector containing shift amount
9300 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9303 ShOps[1] = DAG.getConstant(0, MVT::i32);
9304 ShOps[2] = DAG.getUNDEF(MVT::i32);
9305 ShOps[3] = DAG.getUNDEF(MVT::i32);
9306 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9307 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9308 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9312 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9313 DebugLoc dl = Op.getDebugLoc();
9314 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9316 default: return SDValue(); // Don't custom lower most intrinsics.
9317 // Comparison intrinsics.
9318 case Intrinsic::x86_sse_comieq_ss:
9319 case Intrinsic::x86_sse_comilt_ss:
9320 case Intrinsic::x86_sse_comile_ss:
9321 case Intrinsic::x86_sse_comigt_ss:
9322 case Intrinsic::x86_sse_comige_ss:
9323 case Intrinsic::x86_sse_comineq_ss:
9324 case Intrinsic::x86_sse_ucomieq_ss:
9325 case Intrinsic::x86_sse_ucomilt_ss:
9326 case Intrinsic::x86_sse_ucomile_ss:
9327 case Intrinsic::x86_sse_ucomigt_ss:
9328 case Intrinsic::x86_sse_ucomige_ss:
9329 case Intrinsic::x86_sse_ucomineq_ss:
9330 case Intrinsic::x86_sse2_comieq_sd:
9331 case Intrinsic::x86_sse2_comilt_sd:
9332 case Intrinsic::x86_sse2_comile_sd:
9333 case Intrinsic::x86_sse2_comigt_sd:
9334 case Intrinsic::x86_sse2_comige_sd:
9335 case Intrinsic::x86_sse2_comineq_sd:
9336 case Intrinsic::x86_sse2_ucomieq_sd:
9337 case Intrinsic::x86_sse2_ucomilt_sd:
9338 case Intrinsic::x86_sse2_ucomile_sd:
9339 case Intrinsic::x86_sse2_ucomigt_sd:
9340 case Intrinsic::x86_sse2_ucomige_sd:
9341 case Intrinsic::x86_sse2_ucomineq_sd: {
9343 ISD::CondCode CC = ISD::SETCC_INVALID;
9345 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9346 case Intrinsic::x86_sse_comieq_ss:
9347 case Intrinsic::x86_sse2_comieq_sd:
9351 case Intrinsic::x86_sse_comilt_ss:
9352 case Intrinsic::x86_sse2_comilt_sd:
9356 case Intrinsic::x86_sse_comile_ss:
9357 case Intrinsic::x86_sse2_comile_sd:
9361 case Intrinsic::x86_sse_comigt_ss:
9362 case Intrinsic::x86_sse2_comigt_sd:
9366 case Intrinsic::x86_sse_comige_ss:
9367 case Intrinsic::x86_sse2_comige_sd:
9371 case Intrinsic::x86_sse_comineq_ss:
9372 case Intrinsic::x86_sse2_comineq_sd:
9376 case Intrinsic::x86_sse_ucomieq_ss:
9377 case Intrinsic::x86_sse2_ucomieq_sd:
9378 Opc = X86ISD::UCOMI;
9381 case Intrinsic::x86_sse_ucomilt_ss:
9382 case Intrinsic::x86_sse2_ucomilt_sd:
9383 Opc = X86ISD::UCOMI;
9386 case Intrinsic::x86_sse_ucomile_ss:
9387 case Intrinsic::x86_sse2_ucomile_sd:
9388 Opc = X86ISD::UCOMI;
9391 case Intrinsic::x86_sse_ucomigt_ss:
9392 case Intrinsic::x86_sse2_ucomigt_sd:
9393 Opc = X86ISD::UCOMI;
9396 case Intrinsic::x86_sse_ucomige_ss:
9397 case Intrinsic::x86_sse2_ucomige_sd:
9398 Opc = X86ISD::UCOMI;
9401 case Intrinsic::x86_sse_ucomineq_ss:
9402 case Intrinsic::x86_sse2_ucomineq_sd:
9403 Opc = X86ISD::UCOMI;
9408 SDValue LHS = Op.getOperand(1);
9409 SDValue RHS = Op.getOperand(2);
9410 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9411 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9412 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9413 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9414 DAG.getConstant(X86CC, MVT::i8), Cond);
9415 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9417 // XOP comparison intrinsics
9418 case Intrinsic::x86_xop_vpcomltb:
9419 case Intrinsic::x86_xop_vpcomltw:
9420 case Intrinsic::x86_xop_vpcomltd:
9421 case Intrinsic::x86_xop_vpcomltq:
9422 case Intrinsic::x86_xop_vpcomltub:
9423 case Intrinsic::x86_xop_vpcomltuw:
9424 case Intrinsic::x86_xop_vpcomltud:
9425 case Intrinsic::x86_xop_vpcomltuq:
9426 case Intrinsic::x86_xop_vpcomleb:
9427 case Intrinsic::x86_xop_vpcomlew:
9428 case Intrinsic::x86_xop_vpcomled:
9429 case Intrinsic::x86_xop_vpcomleq:
9430 case Intrinsic::x86_xop_vpcomleub:
9431 case Intrinsic::x86_xop_vpcomleuw:
9432 case Intrinsic::x86_xop_vpcomleud:
9433 case Intrinsic::x86_xop_vpcomleuq:
9434 case Intrinsic::x86_xop_vpcomgtb:
9435 case Intrinsic::x86_xop_vpcomgtw:
9436 case Intrinsic::x86_xop_vpcomgtd:
9437 case Intrinsic::x86_xop_vpcomgtq:
9438 case Intrinsic::x86_xop_vpcomgtub:
9439 case Intrinsic::x86_xop_vpcomgtuw:
9440 case Intrinsic::x86_xop_vpcomgtud:
9441 case Intrinsic::x86_xop_vpcomgtuq:
9442 case Intrinsic::x86_xop_vpcomgeb:
9443 case Intrinsic::x86_xop_vpcomgew:
9444 case Intrinsic::x86_xop_vpcomged:
9445 case Intrinsic::x86_xop_vpcomgeq:
9446 case Intrinsic::x86_xop_vpcomgeub:
9447 case Intrinsic::x86_xop_vpcomgeuw:
9448 case Intrinsic::x86_xop_vpcomgeud:
9449 case Intrinsic::x86_xop_vpcomgeuq:
9450 case Intrinsic::x86_xop_vpcomeqb:
9451 case Intrinsic::x86_xop_vpcomeqw:
9452 case Intrinsic::x86_xop_vpcomeqd:
9453 case Intrinsic::x86_xop_vpcomeqq:
9454 case Intrinsic::x86_xop_vpcomequb:
9455 case Intrinsic::x86_xop_vpcomequw:
9456 case Intrinsic::x86_xop_vpcomequd:
9457 case Intrinsic::x86_xop_vpcomequq:
9458 case Intrinsic::x86_xop_vpcomneb:
9459 case Intrinsic::x86_xop_vpcomnew:
9460 case Intrinsic::x86_xop_vpcomned:
9461 case Intrinsic::x86_xop_vpcomneq:
9462 case Intrinsic::x86_xop_vpcomneub:
9463 case Intrinsic::x86_xop_vpcomneuw:
9464 case Intrinsic::x86_xop_vpcomneud:
9465 case Intrinsic::x86_xop_vpcomneuq:
9466 case Intrinsic::x86_xop_vpcomfalseb:
9467 case Intrinsic::x86_xop_vpcomfalsew:
9468 case Intrinsic::x86_xop_vpcomfalsed:
9469 case Intrinsic::x86_xop_vpcomfalseq:
9470 case Intrinsic::x86_xop_vpcomfalseub:
9471 case Intrinsic::x86_xop_vpcomfalseuw:
9472 case Intrinsic::x86_xop_vpcomfalseud:
9473 case Intrinsic::x86_xop_vpcomfalseuq:
9474 case Intrinsic::x86_xop_vpcomtrueb:
9475 case Intrinsic::x86_xop_vpcomtruew:
9476 case Intrinsic::x86_xop_vpcomtrued:
9477 case Intrinsic::x86_xop_vpcomtrueq:
9478 case Intrinsic::x86_xop_vpcomtrueub:
9479 case Intrinsic::x86_xop_vpcomtrueuw:
9480 case Intrinsic::x86_xop_vpcomtrueud:
9481 case Intrinsic::x86_xop_vpcomtrueuq: {
9486 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9487 case Intrinsic::x86_xop_vpcomltb:
9488 case Intrinsic::x86_xop_vpcomltw:
9489 case Intrinsic::x86_xop_vpcomltd:
9490 case Intrinsic::x86_xop_vpcomltq:
9492 Opc = X86ISD::VPCOM;
9494 case Intrinsic::x86_xop_vpcomltub:
9495 case Intrinsic::x86_xop_vpcomltuw:
9496 case Intrinsic::x86_xop_vpcomltud:
9497 case Intrinsic::x86_xop_vpcomltuq:
9499 Opc = X86ISD::VPCOMU;
9501 case Intrinsic::x86_xop_vpcomleb:
9502 case Intrinsic::x86_xop_vpcomlew:
9503 case Intrinsic::x86_xop_vpcomled:
9504 case Intrinsic::x86_xop_vpcomleq:
9506 Opc = X86ISD::VPCOM;
9508 case Intrinsic::x86_xop_vpcomleub:
9509 case Intrinsic::x86_xop_vpcomleuw:
9510 case Intrinsic::x86_xop_vpcomleud:
9511 case Intrinsic::x86_xop_vpcomleuq:
9513 Opc = X86ISD::VPCOMU;
9515 case Intrinsic::x86_xop_vpcomgtb:
9516 case Intrinsic::x86_xop_vpcomgtw:
9517 case Intrinsic::x86_xop_vpcomgtd:
9518 case Intrinsic::x86_xop_vpcomgtq:
9520 Opc = X86ISD::VPCOM;
9522 case Intrinsic::x86_xop_vpcomgtub:
9523 case Intrinsic::x86_xop_vpcomgtuw:
9524 case Intrinsic::x86_xop_vpcomgtud:
9525 case Intrinsic::x86_xop_vpcomgtuq:
9527 Opc = X86ISD::VPCOMU;
9529 case Intrinsic::x86_xop_vpcomgeb:
9530 case Intrinsic::x86_xop_vpcomgew:
9531 case Intrinsic::x86_xop_vpcomged:
9532 case Intrinsic::x86_xop_vpcomgeq:
9534 Opc = X86ISD::VPCOM;
9536 case Intrinsic::x86_xop_vpcomgeub:
9537 case Intrinsic::x86_xop_vpcomgeuw:
9538 case Intrinsic::x86_xop_vpcomgeud:
9539 case Intrinsic::x86_xop_vpcomgeuq:
9541 Opc = X86ISD::VPCOMU;
9543 case Intrinsic::x86_xop_vpcomeqb:
9544 case Intrinsic::x86_xop_vpcomeqw:
9545 case Intrinsic::x86_xop_vpcomeqd:
9546 case Intrinsic::x86_xop_vpcomeqq:
9548 Opc = X86ISD::VPCOM;
9550 case Intrinsic::x86_xop_vpcomequb:
9551 case Intrinsic::x86_xop_vpcomequw:
9552 case Intrinsic::x86_xop_vpcomequd:
9553 case Intrinsic::x86_xop_vpcomequq:
9555 Opc = X86ISD::VPCOMU;
9557 case Intrinsic::x86_xop_vpcomneb:
9558 case Intrinsic::x86_xop_vpcomnew:
9559 case Intrinsic::x86_xop_vpcomned:
9560 case Intrinsic::x86_xop_vpcomneq:
9562 Opc = X86ISD::VPCOM;
9564 case Intrinsic::x86_xop_vpcomneub:
9565 case Intrinsic::x86_xop_vpcomneuw:
9566 case Intrinsic::x86_xop_vpcomneud:
9567 case Intrinsic::x86_xop_vpcomneuq:
9569 Opc = X86ISD::VPCOMU;
9571 case Intrinsic::x86_xop_vpcomfalseb:
9572 case Intrinsic::x86_xop_vpcomfalsew:
9573 case Intrinsic::x86_xop_vpcomfalsed:
9574 case Intrinsic::x86_xop_vpcomfalseq:
9576 Opc = X86ISD::VPCOM;
9578 case Intrinsic::x86_xop_vpcomfalseub:
9579 case Intrinsic::x86_xop_vpcomfalseuw:
9580 case Intrinsic::x86_xop_vpcomfalseud:
9581 case Intrinsic::x86_xop_vpcomfalseuq:
9583 Opc = X86ISD::VPCOMU;
9585 case Intrinsic::x86_xop_vpcomtrueb:
9586 case Intrinsic::x86_xop_vpcomtruew:
9587 case Intrinsic::x86_xop_vpcomtrued:
9588 case Intrinsic::x86_xop_vpcomtrueq:
9590 Opc = X86ISD::VPCOM;
9592 case Intrinsic::x86_xop_vpcomtrueub:
9593 case Intrinsic::x86_xop_vpcomtrueuw:
9594 case Intrinsic::x86_xop_vpcomtrueud:
9595 case Intrinsic::x86_xop_vpcomtrueuq:
9597 Opc = X86ISD::VPCOMU;
9601 SDValue LHS = Op.getOperand(1);
9602 SDValue RHS = Op.getOperand(2);
9603 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9604 DAG.getConstant(CC, MVT::i8));
9607 // Arithmetic intrinsics.
9608 case Intrinsic::x86_sse2_pmulu_dq:
9609 case Intrinsic::x86_avx2_pmulu_dq:
9610 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9611 Op.getOperand(1), Op.getOperand(2));
9612 case Intrinsic::x86_sse3_hadd_ps:
9613 case Intrinsic::x86_sse3_hadd_pd:
9614 case Intrinsic::x86_avx_hadd_ps_256:
9615 case Intrinsic::x86_avx_hadd_pd_256:
9616 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9617 Op.getOperand(1), Op.getOperand(2));
9618 case Intrinsic::x86_sse3_hsub_ps:
9619 case Intrinsic::x86_sse3_hsub_pd:
9620 case Intrinsic::x86_avx_hsub_ps_256:
9621 case Intrinsic::x86_avx_hsub_pd_256:
9622 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9623 Op.getOperand(1), Op.getOperand(2));
9624 case Intrinsic::x86_ssse3_phadd_w_128:
9625 case Intrinsic::x86_ssse3_phadd_d_128:
9626 case Intrinsic::x86_avx2_phadd_w:
9627 case Intrinsic::x86_avx2_phadd_d:
9628 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9629 Op.getOperand(1), Op.getOperand(2));
9630 case Intrinsic::x86_ssse3_phsub_w_128:
9631 case Intrinsic::x86_ssse3_phsub_d_128:
9632 case Intrinsic::x86_avx2_phsub_w:
9633 case Intrinsic::x86_avx2_phsub_d:
9634 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9635 Op.getOperand(1), Op.getOperand(2));
9636 case Intrinsic::x86_avx2_psllv_d:
9637 case Intrinsic::x86_avx2_psllv_q:
9638 case Intrinsic::x86_avx2_psllv_d_256:
9639 case Intrinsic::x86_avx2_psllv_q_256:
9640 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9641 Op.getOperand(1), Op.getOperand(2));
9642 case Intrinsic::x86_avx2_psrlv_d:
9643 case Intrinsic::x86_avx2_psrlv_q:
9644 case Intrinsic::x86_avx2_psrlv_d_256:
9645 case Intrinsic::x86_avx2_psrlv_q_256:
9646 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9647 Op.getOperand(1), Op.getOperand(2));
9648 case Intrinsic::x86_avx2_psrav_d:
9649 case Intrinsic::x86_avx2_psrav_d_256:
9650 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9651 Op.getOperand(1), Op.getOperand(2));
9652 case Intrinsic::x86_ssse3_pshuf_b_128:
9653 case Intrinsic::x86_avx2_pshuf_b:
9654 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9655 Op.getOperand(1), Op.getOperand(2));
9656 case Intrinsic::x86_ssse3_psign_b_128:
9657 case Intrinsic::x86_ssse3_psign_w_128:
9658 case Intrinsic::x86_ssse3_psign_d_128:
9659 case Intrinsic::x86_avx2_psign_b:
9660 case Intrinsic::x86_avx2_psign_w:
9661 case Intrinsic::x86_avx2_psign_d:
9662 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9663 Op.getOperand(1), Op.getOperand(2));
9664 case Intrinsic::x86_sse41_insertps:
9665 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9666 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9667 case Intrinsic::x86_avx_vperm2f128_ps_256:
9668 case Intrinsic::x86_avx_vperm2f128_pd_256:
9669 case Intrinsic::x86_avx_vperm2f128_si_256:
9670 case Intrinsic::x86_avx2_vperm2i128:
9671 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9672 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9673 case Intrinsic::x86_avx2_permd:
9674 case Intrinsic::x86_avx2_permps:
9675 // Operands intentionally swapped. Mask is last operand to intrinsic,
9676 // but second operand for node/intruction.
9677 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9678 Op.getOperand(2), Op.getOperand(1));
9680 // ptest and testp intrinsics. The intrinsic these come from are designed to
9681 // return an integer value, not just an instruction so lower it to the ptest
9682 // or testp pattern and a setcc for the result.
9683 case Intrinsic::x86_sse41_ptestz:
9684 case Intrinsic::x86_sse41_ptestc:
9685 case Intrinsic::x86_sse41_ptestnzc:
9686 case Intrinsic::x86_avx_ptestz_256:
9687 case Intrinsic::x86_avx_ptestc_256:
9688 case Intrinsic::x86_avx_ptestnzc_256:
9689 case Intrinsic::x86_avx_vtestz_ps:
9690 case Intrinsic::x86_avx_vtestc_ps:
9691 case Intrinsic::x86_avx_vtestnzc_ps:
9692 case Intrinsic::x86_avx_vtestz_pd:
9693 case Intrinsic::x86_avx_vtestc_pd:
9694 case Intrinsic::x86_avx_vtestnzc_pd:
9695 case Intrinsic::x86_avx_vtestz_ps_256:
9696 case Intrinsic::x86_avx_vtestc_ps_256:
9697 case Intrinsic::x86_avx_vtestnzc_ps_256:
9698 case Intrinsic::x86_avx_vtestz_pd_256:
9699 case Intrinsic::x86_avx_vtestc_pd_256:
9700 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9701 bool IsTestPacked = false;
9704 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9705 case Intrinsic::x86_avx_vtestz_ps:
9706 case Intrinsic::x86_avx_vtestz_pd:
9707 case Intrinsic::x86_avx_vtestz_ps_256:
9708 case Intrinsic::x86_avx_vtestz_pd_256:
9709 IsTestPacked = true; // Fallthrough
9710 case Intrinsic::x86_sse41_ptestz:
9711 case Intrinsic::x86_avx_ptestz_256:
9713 X86CC = X86::COND_E;
9715 case Intrinsic::x86_avx_vtestc_ps:
9716 case Intrinsic::x86_avx_vtestc_pd:
9717 case Intrinsic::x86_avx_vtestc_ps_256:
9718 case Intrinsic::x86_avx_vtestc_pd_256:
9719 IsTestPacked = true; // Fallthrough
9720 case Intrinsic::x86_sse41_ptestc:
9721 case Intrinsic::x86_avx_ptestc_256:
9723 X86CC = X86::COND_B;
9725 case Intrinsic::x86_avx_vtestnzc_ps:
9726 case Intrinsic::x86_avx_vtestnzc_pd:
9727 case Intrinsic::x86_avx_vtestnzc_ps_256:
9728 case Intrinsic::x86_avx_vtestnzc_pd_256:
9729 IsTestPacked = true; // Fallthrough
9730 case Intrinsic::x86_sse41_ptestnzc:
9731 case Intrinsic::x86_avx_ptestnzc_256:
9733 X86CC = X86::COND_A;
9737 SDValue LHS = Op.getOperand(1);
9738 SDValue RHS = Op.getOperand(2);
9739 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9740 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9741 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9742 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9743 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9746 // SSE/AVX shift intrinsics
9747 case Intrinsic::x86_sse2_psll_w:
9748 case Intrinsic::x86_sse2_psll_d:
9749 case Intrinsic::x86_sse2_psll_q:
9750 case Intrinsic::x86_avx2_psll_w:
9751 case Intrinsic::x86_avx2_psll_d:
9752 case Intrinsic::x86_avx2_psll_q:
9753 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9754 Op.getOperand(1), Op.getOperand(2));
9755 case Intrinsic::x86_sse2_psrl_w:
9756 case Intrinsic::x86_sse2_psrl_d:
9757 case Intrinsic::x86_sse2_psrl_q:
9758 case Intrinsic::x86_avx2_psrl_w:
9759 case Intrinsic::x86_avx2_psrl_d:
9760 case Intrinsic::x86_avx2_psrl_q:
9761 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9762 Op.getOperand(1), Op.getOperand(2));
9763 case Intrinsic::x86_sse2_psra_w:
9764 case Intrinsic::x86_sse2_psra_d:
9765 case Intrinsic::x86_avx2_psra_w:
9766 case Intrinsic::x86_avx2_psra_d:
9767 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9768 Op.getOperand(1), Op.getOperand(2));
9769 case Intrinsic::x86_sse2_pslli_w:
9770 case Intrinsic::x86_sse2_pslli_d:
9771 case Intrinsic::x86_sse2_pslli_q:
9772 case Intrinsic::x86_avx2_pslli_w:
9773 case Intrinsic::x86_avx2_pslli_d:
9774 case Intrinsic::x86_avx2_pslli_q:
9775 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9776 Op.getOperand(1), Op.getOperand(2), DAG);
9777 case Intrinsic::x86_sse2_psrli_w:
9778 case Intrinsic::x86_sse2_psrli_d:
9779 case Intrinsic::x86_sse2_psrli_q:
9780 case Intrinsic::x86_avx2_psrli_w:
9781 case Intrinsic::x86_avx2_psrli_d:
9782 case Intrinsic::x86_avx2_psrli_q:
9783 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9784 Op.getOperand(1), Op.getOperand(2), DAG);
9785 case Intrinsic::x86_sse2_psrai_w:
9786 case Intrinsic::x86_sse2_psrai_d:
9787 case Intrinsic::x86_avx2_psrai_w:
9788 case Intrinsic::x86_avx2_psrai_d:
9789 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9790 Op.getOperand(1), Op.getOperand(2), DAG);
9791 // Fix vector shift instructions where the last operand is a non-immediate
9793 case Intrinsic::x86_mmx_pslli_w:
9794 case Intrinsic::x86_mmx_pslli_d:
9795 case Intrinsic::x86_mmx_pslli_q:
9796 case Intrinsic::x86_mmx_psrli_w:
9797 case Intrinsic::x86_mmx_psrli_d:
9798 case Intrinsic::x86_mmx_psrli_q:
9799 case Intrinsic::x86_mmx_psrai_w:
9800 case Intrinsic::x86_mmx_psrai_d: {
9801 SDValue ShAmt = Op.getOperand(2);
9802 if (isa<ConstantSDNode>(ShAmt))
9805 unsigned NewIntNo = 0;
9807 case Intrinsic::x86_mmx_pslli_w:
9808 NewIntNo = Intrinsic::x86_mmx_psll_w;
9810 case Intrinsic::x86_mmx_pslli_d:
9811 NewIntNo = Intrinsic::x86_mmx_psll_d;
9813 case Intrinsic::x86_mmx_pslli_q:
9814 NewIntNo = Intrinsic::x86_mmx_psll_q;
9816 case Intrinsic::x86_mmx_psrli_w:
9817 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9819 case Intrinsic::x86_mmx_psrli_d:
9820 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9822 case Intrinsic::x86_mmx_psrli_q:
9823 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9825 case Intrinsic::x86_mmx_psrai_w:
9826 NewIntNo = Intrinsic::x86_mmx_psra_w;
9828 case Intrinsic::x86_mmx_psrai_d:
9829 NewIntNo = Intrinsic::x86_mmx_psra_d;
9831 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9834 // The vector shift intrinsics with scalars uses 32b shift amounts but
9835 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9837 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9838 DAG.getConstant(0, MVT::i32));
9839 // FIXME this must be lowered to get rid of the invalid type.
9841 EVT VT = Op.getValueType();
9842 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9843 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9844 DAG.getConstant(NewIntNo, MVT::i32),
9845 Op.getOperand(1), ShAmt);
9850 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9851 SelectionDAG &DAG) const {
9852 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9853 MFI->setReturnAddressIsTaken(true);
9855 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9856 DebugLoc dl = Op.getDebugLoc();
9859 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9861 DAG.getConstant(TD->getPointerSize(),
9862 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9863 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9864 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9866 MachinePointerInfo(), false, false, false, 0);
9869 // Just load the return address.
9870 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9871 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9872 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9875 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9876 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9877 MFI->setFrameAddressIsTaken(true);
9879 EVT VT = Op.getValueType();
9880 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9881 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9882 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9883 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9885 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9886 MachinePointerInfo(),
9887 false, false, false, 0);
9891 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9892 SelectionDAG &DAG) const {
9893 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9896 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9897 MachineFunction &MF = DAG.getMachineFunction();
9898 SDValue Chain = Op.getOperand(0);
9899 SDValue Offset = Op.getOperand(1);
9900 SDValue Handler = Op.getOperand(2);
9901 DebugLoc dl = Op.getDebugLoc();
9903 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9904 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9906 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9908 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9909 DAG.getIntPtrConstant(TD->getPointerSize()));
9910 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9911 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9913 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9914 MF.getRegInfo().addLiveOut(StoreAddrReg);
9916 return DAG.getNode(X86ISD::EH_RETURN, dl,
9918 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9921 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9922 SelectionDAG &DAG) const {
9923 return Op.getOperand(0);
9926 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9927 SelectionDAG &DAG) const {
9928 SDValue Root = Op.getOperand(0);
9929 SDValue Trmp = Op.getOperand(1); // trampoline
9930 SDValue FPtr = Op.getOperand(2); // nested function
9931 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9932 DebugLoc dl = Op.getDebugLoc();
9934 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9936 if (Subtarget->is64Bit()) {
9937 SDValue OutChains[6];
9939 // Large code-model.
9940 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9941 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9943 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9944 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9946 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9948 // Load the pointer to the nested function into R11.
9949 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9950 SDValue Addr = Trmp;
9951 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9952 Addr, MachinePointerInfo(TrmpAddr),
9955 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9956 DAG.getConstant(2, MVT::i64));
9957 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9958 MachinePointerInfo(TrmpAddr, 2),
9961 // Load the 'nest' parameter value into R10.
9962 // R10 is specified in X86CallingConv.td
9963 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9964 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9965 DAG.getConstant(10, MVT::i64));
9966 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9967 Addr, MachinePointerInfo(TrmpAddr, 10),
9970 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9971 DAG.getConstant(12, MVT::i64));
9972 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9973 MachinePointerInfo(TrmpAddr, 12),
9976 // Jump to the nested function.
9977 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9978 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9979 DAG.getConstant(20, MVT::i64));
9980 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9981 Addr, MachinePointerInfo(TrmpAddr, 20),
9984 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9985 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9986 DAG.getConstant(22, MVT::i64));
9987 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9988 MachinePointerInfo(TrmpAddr, 22),
9991 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9993 const Function *Func =
9994 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9995 CallingConv::ID CC = Func->getCallingConv();
10000 llvm_unreachable("Unsupported calling convention");
10001 case CallingConv::C:
10002 case CallingConv::X86_StdCall: {
10003 // Pass 'nest' parameter in ECX.
10004 // Must be kept in sync with X86CallingConv.td
10005 NestReg = X86::ECX;
10007 // Check that ECX wasn't needed by an 'inreg' parameter.
10008 FunctionType *FTy = Func->getFunctionType();
10009 const AttrListPtr &Attrs = Func->getAttributes();
10011 if (!Attrs.isEmpty() && !Func->isVarArg()) {
10012 unsigned InRegCount = 0;
10015 for (FunctionType::param_iterator I = FTy->param_begin(),
10016 E = FTy->param_end(); I != E; ++I, ++Idx)
10017 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
10018 // FIXME: should only count parameters that are lowered to integers.
10019 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
10021 if (InRegCount > 2) {
10022 report_fatal_error("Nest register in use - reduce number of inreg"
10028 case CallingConv::X86_FastCall:
10029 case CallingConv::X86_ThisCall:
10030 case CallingConv::Fast:
10031 // Pass 'nest' parameter in EAX.
10032 // Must be kept in sync with X86CallingConv.td
10033 NestReg = X86::EAX;
10037 SDValue OutChains[4];
10038 SDValue Addr, Disp;
10040 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10041 DAG.getConstant(10, MVT::i32));
10042 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
10044 // This is storing the opcode for MOV32ri.
10045 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
10046 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
10047 OutChains[0] = DAG.getStore(Root, dl,
10048 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
10049 Trmp, MachinePointerInfo(TrmpAddr),
10052 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10053 DAG.getConstant(1, MVT::i32));
10054 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
10055 MachinePointerInfo(TrmpAddr, 1),
10058 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
10059 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10060 DAG.getConstant(5, MVT::i32));
10061 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
10062 MachinePointerInfo(TrmpAddr, 5),
10065 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10066 DAG.getConstant(6, MVT::i32));
10067 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
10068 MachinePointerInfo(TrmpAddr, 6),
10071 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10075 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10076 SelectionDAG &DAG) const {
10078 The rounding mode is in bits 11:10 of FPSR, and has the following
10080 00 Round to nearest
10085 FLT_ROUNDS, on the other hand, expects the following:
10092 To perform the conversion, we do:
10093 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10096 MachineFunction &MF = DAG.getMachineFunction();
10097 const TargetMachine &TM = MF.getTarget();
10098 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10099 unsigned StackAlignment = TFI.getStackAlignment();
10100 EVT VT = Op.getValueType();
10101 DebugLoc DL = Op.getDebugLoc();
10103 // Save FP Control Word to stack slot
10104 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10105 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10108 MachineMemOperand *MMO =
10109 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10110 MachineMemOperand::MOStore, 2, 2);
10112 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10113 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10114 DAG.getVTList(MVT::Other),
10115 Ops, 2, MVT::i16, MMO);
10117 // Load FP Control Word from stack slot
10118 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10119 MachinePointerInfo(), false, false, false, 0);
10121 // Transform as necessary
10123 DAG.getNode(ISD::SRL, DL, MVT::i16,
10124 DAG.getNode(ISD::AND, DL, MVT::i16,
10125 CWD, DAG.getConstant(0x800, MVT::i16)),
10126 DAG.getConstant(11, MVT::i8));
10128 DAG.getNode(ISD::SRL, DL, MVT::i16,
10129 DAG.getNode(ISD::AND, DL, MVT::i16,
10130 CWD, DAG.getConstant(0x400, MVT::i16)),
10131 DAG.getConstant(9, MVT::i8));
10134 DAG.getNode(ISD::AND, DL, MVT::i16,
10135 DAG.getNode(ISD::ADD, DL, MVT::i16,
10136 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10137 DAG.getConstant(1, MVT::i16)),
10138 DAG.getConstant(3, MVT::i16));
10141 return DAG.getNode((VT.getSizeInBits() < 16 ?
10142 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10145 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10146 EVT VT = Op.getValueType();
10148 unsigned NumBits = VT.getSizeInBits();
10149 DebugLoc dl = Op.getDebugLoc();
10151 Op = Op.getOperand(0);
10152 if (VT == MVT::i8) {
10153 // Zero extend to i32 since there is not an i8 bsr.
10155 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10158 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10159 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10160 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10162 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10165 DAG.getConstant(NumBits+NumBits-1, OpVT),
10166 DAG.getConstant(X86::COND_E, MVT::i8),
10169 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10171 // Finally xor with NumBits-1.
10172 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10175 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10179 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10180 SelectionDAG &DAG) const {
10181 EVT VT = Op.getValueType();
10183 unsigned NumBits = VT.getSizeInBits();
10184 DebugLoc dl = Op.getDebugLoc();
10186 Op = Op.getOperand(0);
10187 if (VT == MVT::i8) {
10188 // Zero extend to i32 since there is not an i8 bsr.
10190 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10193 // Issue a bsr (scan bits in reverse).
10194 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10195 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10197 // And xor with NumBits-1.
10198 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10201 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10205 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10206 EVT VT = Op.getValueType();
10207 unsigned NumBits = VT.getSizeInBits();
10208 DebugLoc dl = Op.getDebugLoc();
10209 Op = Op.getOperand(0);
10211 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10212 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10213 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10215 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10218 DAG.getConstant(NumBits, VT),
10219 DAG.getConstant(X86::COND_E, MVT::i8),
10222 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10225 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10226 // ones, and then concatenate the result back.
10227 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10228 EVT VT = Op.getValueType();
10230 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10231 "Unsupported value type for operation");
10233 unsigned NumElems = VT.getVectorNumElements();
10234 DebugLoc dl = Op.getDebugLoc();
10236 // Extract the LHS vectors
10237 SDValue LHS = Op.getOperand(0);
10238 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10239 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10241 // Extract the RHS vectors
10242 SDValue RHS = Op.getOperand(1);
10243 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10244 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10246 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10247 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10249 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10250 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10251 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10254 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10255 assert(Op.getValueType().getSizeInBits() == 256 &&
10256 Op.getValueType().isInteger() &&
10257 "Only handle AVX 256-bit vector integer operation");
10258 return Lower256IntArith(Op, DAG);
10261 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10262 assert(Op.getValueType().getSizeInBits() == 256 &&
10263 Op.getValueType().isInteger() &&
10264 "Only handle AVX 256-bit vector integer operation");
10265 return Lower256IntArith(Op, DAG);
10268 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10269 EVT VT = Op.getValueType();
10271 // Decompose 256-bit ops into smaller 128-bit ops.
10272 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10273 return Lower256IntArith(Op, DAG);
10275 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10276 "Only know how to lower V2I64/V4I64 multiply");
10278 DebugLoc dl = Op.getDebugLoc();
10280 // Ahi = psrlqi(a, 32);
10281 // Bhi = psrlqi(b, 32);
10283 // AloBlo = pmuludq(a, b);
10284 // AloBhi = pmuludq(a, Bhi);
10285 // AhiBlo = pmuludq(Ahi, b);
10287 // AloBhi = psllqi(AloBhi, 32);
10288 // AhiBlo = psllqi(AhiBlo, 32);
10289 // return AloBlo + AloBhi + AhiBlo;
10291 SDValue A = Op.getOperand(0);
10292 SDValue B = Op.getOperand(1);
10294 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10296 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10297 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10299 // Bit cast to 32-bit vectors for MULUDQ
10300 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10301 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10302 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10303 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10304 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10306 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10307 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10308 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10310 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10311 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10313 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10314 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10317 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10319 EVT VT = Op.getValueType();
10320 DebugLoc dl = Op.getDebugLoc();
10321 SDValue R = Op.getOperand(0);
10322 SDValue Amt = Op.getOperand(1);
10323 LLVMContext *Context = DAG.getContext();
10325 if (!Subtarget->hasSSE2())
10328 // Optimize shl/srl/sra with constant shift amount.
10329 if (isSplatVector(Amt.getNode())) {
10330 SDValue SclrAmt = Amt->getOperand(0);
10331 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10332 uint64_t ShiftAmt = C->getZExtValue();
10334 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10335 (Subtarget->hasAVX2() &&
10336 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10337 if (Op.getOpcode() == ISD::SHL)
10338 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10339 DAG.getConstant(ShiftAmt, MVT::i32));
10340 if (Op.getOpcode() == ISD::SRL)
10341 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10342 DAG.getConstant(ShiftAmt, MVT::i32));
10343 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10344 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10345 DAG.getConstant(ShiftAmt, MVT::i32));
10348 if (VT == MVT::v16i8) {
10349 if (Op.getOpcode() == ISD::SHL) {
10350 // Make a large shift.
10351 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10352 DAG.getConstant(ShiftAmt, MVT::i32));
10353 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10354 // Zero out the rightmost bits.
10355 SmallVector<SDValue, 16> V(16,
10356 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10358 return DAG.getNode(ISD::AND, dl, VT, SHL,
10359 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10361 if (Op.getOpcode() == ISD::SRL) {
10362 // Make a large shift.
10363 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10364 DAG.getConstant(ShiftAmt, MVT::i32));
10365 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10366 // Zero out the leftmost bits.
10367 SmallVector<SDValue, 16> V(16,
10368 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10370 return DAG.getNode(ISD::AND, dl, VT, SRL,
10371 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10373 if (Op.getOpcode() == ISD::SRA) {
10374 if (ShiftAmt == 7) {
10375 // R s>> 7 === R s< 0
10376 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10377 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10380 // R s>> a === ((R u>> a) ^ m) - m
10381 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10382 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10384 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10385 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10386 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10389 llvm_unreachable("Unknown shift opcode.");
10392 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10393 if (Op.getOpcode() == ISD::SHL) {
10394 // Make a large shift.
10395 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10396 DAG.getConstant(ShiftAmt, MVT::i32));
10397 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10398 // Zero out the rightmost bits.
10399 SmallVector<SDValue, 32> V(32,
10400 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10402 return DAG.getNode(ISD::AND, dl, VT, SHL,
10403 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10405 if (Op.getOpcode() == ISD::SRL) {
10406 // Make a large shift.
10407 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10408 DAG.getConstant(ShiftAmt, MVT::i32));
10409 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10410 // Zero out the leftmost bits.
10411 SmallVector<SDValue, 32> V(32,
10412 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10414 return DAG.getNode(ISD::AND, dl, VT, SRL,
10415 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10417 if (Op.getOpcode() == ISD::SRA) {
10418 if (ShiftAmt == 7) {
10419 // R s>> 7 === R s< 0
10420 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10421 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10424 // R s>> a === ((R u>> a) ^ m) - m
10425 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10426 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10428 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10429 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10430 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10433 llvm_unreachable("Unknown shift opcode.");
10438 // Lower SHL with variable shift amount.
10439 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10440 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10441 DAG.getConstant(23, MVT::i32));
10443 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10444 Constant *C = ConstantDataVector::get(*Context, CV);
10445 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10446 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10447 MachinePointerInfo::getConstantPool(),
10448 false, false, false, 16);
10450 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10451 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10452 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10453 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10455 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10456 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10459 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10460 DAG.getConstant(5, MVT::i32));
10461 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10463 // Turn 'a' into a mask suitable for VSELECT
10464 SDValue VSelM = DAG.getConstant(0x80, VT);
10465 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10466 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10468 SDValue CM1 = DAG.getConstant(0x0f, VT);
10469 SDValue CM2 = DAG.getConstant(0x3f, VT);
10471 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10472 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10473 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10474 DAG.getConstant(4, MVT::i32), DAG);
10475 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10476 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10479 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10480 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10481 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10483 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10484 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10485 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10486 DAG.getConstant(2, MVT::i32), DAG);
10487 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10488 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10491 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10492 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10493 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10495 // return VSELECT(r, r+r, a);
10496 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10497 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10501 // Decompose 256-bit shifts into smaller 128-bit shifts.
10502 if (VT.getSizeInBits() == 256) {
10503 unsigned NumElems = VT.getVectorNumElements();
10504 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10505 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10507 // Extract the two vectors
10508 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10509 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10511 // Recreate the shift amount vectors
10512 SDValue Amt1, Amt2;
10513 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10514 // Constant shift amount
10515 SmallVector<SDValue, 4> Amt1Csts;
10516 SmallVector<SDValue, 4> Amt2Csts;
10517 for (unsigned i = 0; i != NumElems/2; ++i)
10518 Amt1Csts.push_back(Amt->getOperand(i));
10519 for (unsigned i = NumElems/2; i != NumElems; ++i)
10520 Amt2Csts.push_back(Amt->getOperand(i));
10522 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10523 &Amt1Csts[0], NumElems/2);
10524 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10525 &Amt2Csts[0], NumElems/2);
10527 // Variable shift amount
10528 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10529 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10532 // Issue new vector shifts for the smaller types
10533 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10534 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10536 // Concatenate the result back
10537 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10543 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10544 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10545 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10546 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10547 // has only one use.
10548 SDNode *N = Op.getNode();
10549 SDValue LHS = N->getOperand(0);
10550 SDValue RHS = N->getOperand(1);
10551 unsigned BaseOp = 0;
10553 DebugLoc DL = Op.getDebugLoc();
10554 switch (Op.getOpcode()) {
10555 default: llvm_unreachable("Unknown ovf instruction!");
10557 // A subtract of one will be selected as a INC. Note that INC doesn't
10558 // set CF, so we can't do this for UADDO.
10559 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10561 BaseOp = X86ISD::INC;
10562 Cond = X86::COND_O;
10565 BaseOp = X86ISD::ADD;
10566 Cond = X86::COND_O;
10569 BaseOp = X86ISD::ADD;
10570 Cond = X86::COND_B;
10573 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10574 // set CF, so we can't do this for USUBO.
10575 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10577 BaseOp = X86ISD::DEC;
10578 Cond = X86::COND_O;
10581 BaseOp = X86ISD::SUB;
10582 Cond = X86::COND_O;
10585 BaseOp = X86ISD::SUB;
10586 Cond = X86::COND_B;
10589 BaseOp = X86ISD::SMUL;
10590 Cond = X86::COND_O;
10592 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10593 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10595 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10598 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10599 DAG.getConstant(X86::COND_O, MVT::i32),
10600 SDValue(Sum.getNode(), 2));
10602 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10606 // Also sets EFLAGS.
10607 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10608 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10611 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10612 DAG.getConstant(Cond, MVT::i32),
10613 SDValue(Sum.getNode(), 1));
10615 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10618 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10619 SelectionDAG &DAG) const {
10620 DebugLoc dl = Op.getDebugLoc();
10621 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10622 EVT VT = Op.getValueType();
10624 if (!Subtarget->hasSSE2() || !VT.isVector())
10627 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10628 ExtraVT.getScalarType().getSizeInBits();
10629 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10631 switch (VT.getSimpleVT().SimpleTy) {
10632 default: return SDValue();
10635 if (!Subtarget->hasAVX())
10637 if (!Subtarget->hasAVX2()) {
10638 // needs to be split
10639 unsigned NumElems = VT.getVectorNumElements();
10641 // Extract the LHS vectors
10642 SDValue LHS = Op.getOperand(0);
10643 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10644 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10646 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10647 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10649 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10650 int ExtraNumElems = ExtraVT.getVectorNumElements();
10651 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10653 SDValue Extra = DAG.getValueType(ExtraVT);
10655 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10656 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10658 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10663 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10664 Op.getOperand(0), ShAmt, DAG);
10665 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10671 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10672 DebugLoc dl = Op.getDebugLoc();
10674 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10675 // There isn't any reason to disable it if the target processor supports it.
10676 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10677 SDValue Chain = Op.getOperand(0);
10678 SDValue Zero = DAG.getConstant(0, MVT::i32);
10680 DAG.getRegister(X86::ESP, MVT::i32), // Base
10681 DAG.getTargetConstant(1, MVT::i8), // Scale
10682 DAG.getRegister(0, MVT::i32), // Index
10683 DAG.getTargetConstant(0, MVT::i32), // Disp
10684 DAG.getRegister(0, MVT::i32), // Segment.
10689 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10690 array_lengthof(Ops));
10691 return SDValue(Res, 0);
10694 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10696 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10698 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10699 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10700 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10701 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10703 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10704 if (!Op1 && !Op2 && !Op3 && Op4)
10705 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10707 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10708 if (Op1 && !Op2 && !Op3 && !Op4)
10709 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10711 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10713 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10716 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10717 SelectionDAG &DAG) const {
10718 DebugLoc dl = Op.getDebugLoc();
10719 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10720 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10721 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10722 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10724 // The only fence that needs an instruction is a sequentially-consistent
10725 // cross-thread fence.
10726 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10727 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10728 // no-sse2). There isn't any reason to disable it if the target processor
10730 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10731 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10733 SDValue Chain = Op.getOperand(0);
10734 SDValue Zero = DAG.getConstant(0, MVT::i32);
10736 DAG.getRegister(X86::ESP, MVT::i32), // Base
10737 DAG.getTargetConstant(1, MVT::i8), // Scale
10738 DAG.getRegister(0, MVT::i32), // Index
10739 DAG.getTargetConstant(0, MVT::i32), // Disp
10740 DAG.getRegister(0, MVT::i32), // Segment.
10745 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10746 array_lengthof(Ops));
10747 return SDValue(Res, 0);
10750 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10751 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10755 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10756 EVT T = Op.getValueType();
10757 DebugLoc DL = Op.getDebugLoc();
10760 switch(T.getSimpleVT().SimpleTy) {
10761 default: llvm_unreachable("Invalid value type!");
10762 case MVT::i8: Reg = X86::AL; size = 1; break;
10763 case MVT::i16: Reg = X86::AX; size = 2; break;
10764 case MVT::i32: Reg = X86::EAX; size = 4; break;
10766 assert(Subtarget->is64Bit() && "Node not type legal!");
10767 Reg = X86::RAX; size = 8;
10770 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10771 Op.getOperand(2), SDValue());
10772 SDValue Ops[] = { cpIn.getValue(0),
10775 DAG.getTargetConstant(size, MVT::i8),
10776 cpIn.getValue(1) };
10777 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10778 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10779 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10782 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10786 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10787 SelectionDAG &DAG) const {
10788 assert(Subtarget->is64Bit() && "Result not type legalized?");
10789 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10790 SDValue TheChain = Op.getOperand(0);
10791 DebugLoc dl = Op.getDebugLoc();
10792 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10793 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10794 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10796 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10797 DAG.getConstant(32, MVT::i8));
10799 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10802 return DAG.getMergeValues(Ops, 2, dl);
10805 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10806 SelectionDAG &DAG) const {
10807 EVT SrcVT = Op.getOperand(0).getValueType();
10808 EVT DstVT = Op.getValueType();
10809 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10810 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10811 assert((DstVT == MVT::i64 ||
10812 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10813 "Unexpected custom BITCAST");
10814 // i64 <=> MMX conversions are Legal.
10815 if (SrcVT==MVT::i64 && DstVT.isVector())
10817 if (DstVT==MVT::i64 && SrcVT.isVector())
10819 // MMX <=> MMX conversions are Legal.
10820 if (SrcVT.isVector() && DstVT.isVector())
10822 // All other conversions need to be expanded.
10826 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10827 SDNode *Node = Op.getNode();
10828 DebugLoc dl = Node->getDebugLoc();
10829 EVT T = Node->getValueType(0);
10830 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10831 DAG.getConstant(0, T), Node->getOperand(2));
10832 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10833 cast<AtomicSDNode>(Node)->getMemoryVT(),
10834 Node->getOperand(0),
10835 Node->getOperand(1), negOp,
10836 cast<AtomicSDNode>(Node)->getSrcValue(),
10837 cast<AtomicSDNode>(Node)->getAlignment(),
10838 cast<AtomicSDNode>(Node)->getOrdering(),
10839 cast<AtomicSDNode>(Node)->getSynchScope());
10842 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10843 SDNode *Node = Op.getNode();
10844 DebugLoc dl = Node->getDebugLoc();
10845 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10847 // Convert seq_cst store -> xchg
10848 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10849 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10850 // (The only way to get a 16-byte store is cmpxchg16b)
10851 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10852 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10853 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10854 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10855 cast<AtomicSDNode>(Node)->getMemoryVT(),
10856 Node->getOperand(0),
10857 Node->getOperand(1), Node->getOperand(2),
10858 cast<AtomicSDNode>(Node)->getMemOperand(),
10859 cast<AtomicSDNode>(Node)->getOrdering(),
10860 cast<AtomicSDNode>(Node)->getSynchScope());
10861 return Swap.getValue(1);
10863 // Other atomic stores have a simple pattern.
10867 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10868 EVT VT = Op.getNode()->getValueType(0);
10870 // Let legalize expand this if it isn't a legal type yet.
10871 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10874 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10877 bool ExtraOp = false;
10878 switch (Op.getOpcode()) {
10879 default: llvm_unreachable("Invalid code");
10880 case ISD::ADDC: Opc = X86ISD::ADD; break;
10881 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10882 case ISD::SUBC: Opc = X86ISD::SUB; break;
10883 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10887 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10889 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10890 Op.getOperand(1), Op.getOperand(2));
10893 /// LowerOperation - Provide custom lowering hooks for some operations.
10895 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10896 switch (Op.getOpcode()) {
10897 default: llvm_unreachable("Should not custom lower this!");
10898 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10899 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10900 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10901 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10902 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10903 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10904 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10905 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10906 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10907 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10908 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10909 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10910 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10911 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10912 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10913 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10914 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10915 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10916 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10917 case ISD::SHL_PARTS:
10918 case ISD::SRA_PARTS:
10919 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10920 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10921 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10922 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10923 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10924 case ISD::FABS: return LowerFABS(Op, DAG);
10925 case ISD::FNEG: return LowerFNEG(Op, DAG);
10926 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10927 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10928 case ISD::SETCC: return LowerSETCC(Op, DAG);
10929 case ISD::SELECT: return LowerSELECT(Op, DAG);
10930 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10931 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10932 case ISD::VASTART: return LowerVASTART(Op, DAG);
10933 case ISD::VAARG: return LowerVAARG(Op, DAG);
10934 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10935 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10936 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10937 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10938 case ISD::FRAME_TO_ARGS_OFFSET:
10939 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10940 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10941 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10942 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10943 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10944 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10945 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10946 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10947 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10948 case ISD::MUL: return LowerMUL(Op, DAG);
10951 case ISD::SHL: return LowerShift(Op, DAG);
10957 case ISD::UMULO: return LowerXALUO(Op, DAG);
10958 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10959 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10963 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10964 case ISD::ADD: return LowerADD(Op, DAG);
10965 case ISD::SUB: return LowerSUB(Op, DAG);
10969 static void ReplaceATOMIC_LOAD(SDNode *Node,
10970 SmallVectorImpl<SDValue> &Results,
10971 SelectionDAG &DAG) {
10972 DebugLoc dl = Node->getDebugLoc();
10973 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10975 // Convert wide load -> cmpxchg8b/cmpxchg16b
10976 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10977 // (The only way to get a 16-byte load is cmpxchg16b)
10978 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10979 SDValue Zero = DAG.getConstant(0, VT);
10980 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10981 Node->getOperand(0),
10982 Node->getOperand(1), Zero, Zero,
10983 cast<AtomicSDNode>(Node)->getMemOperand(),
10984 cast<AtomicSDNode>(Node)->getOrdering(),
10985 cast<AtomicSDNode>(Node)->getSynchScope());
10986 Results.push_back(Swap.getValue(0));
10987 Results.push_back(Swap.getValue(1));
10990 void X86TargetLowering::
10991 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10992 SelectionDAG &DAG, unsigned NewOp) const {
10993 DebugLoc dl = Node->getDebugLoc();
10994 assert (Node->getValueType(0) == MVT::i64 &&
10995 "Only know how to expand i64 atomics");
10997 SDValue Chain = Node->getOperand(0);
10998 SDValue In1 = Node->getOperand(1);
10999 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11000 Node->getOperand(2), DAG.getIntPtrConstant(0));
11001 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11002 Node->getOperand(2), DAG.getIntPtrConstant(1));
11003 SDValue Ops[] = { Chain, In1, In2L, In2H };
11004 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
11006 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
11007 cast<MemSDNode>(Node)->getMemOperand());
11008 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
11009 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
11010 Results.push_back(Result.getValue(2));
11013 /// ReplaceNodeResults - Replace a node with an illegal result type
11014 /// with a new node built out of custom code.
11015 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
11016 SmallVectorImpl<SDValue>&Results,
11017 SelectionDAG &DAG) const {
11018 DebugLoc dl = N->getDebugLoc();
11019 switch (N->getOpcode()) {
11021 llvm_unreachable("Do not know how to custom type legalize this operation!");
11022 case ISD::SIGN_EXTEND_INREG:
11027 // We don't want to expand or promote these.
11029 case ISD::FP_TO_SINT:
11030 case ISD::FP_TO_UINT: {
11031 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
11033 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
11036 std::pair<SDValue,SDValue> Vals =
11037 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
11038 SDValue FIST = Vals.first, StackSlot = Vals.second;
11039 if (FIST.getNode() != 0) {
11040 EVT VT = N->getValueType(0);
11041 // Return a load from the stack slot.
11042 if (StackSlot.getNode() != 0)
11043 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
11044 MachinePointerInfo(),
11045 false, false, false, 0));
11047 Results.push_back(FIST);
11051 case ISD::READCYCLECOUNTER: {
11052 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11053 SDValue TheChain = N->getOperand(0);
11054 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11055 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
11057 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
11059 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
11060 SDValue Ops[] = { eax, edx };
11061 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
11062 Results.push_back(edx.getValue(1));
11065 case ISD::ATOMIC_CMP_SWAP: {
11066 EVT T = N->getValueType(0);
11067 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
11068 bool Regs64bit = T == MVT::i128;
11069 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
11070 SDValue cpInL, cpInH;
11071 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11072 DAG.getConstant(0, HalfT));
11073 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11074 DAG.getConstant(1, HalfT));
11075 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11076 Regs64bit ? X86::RAX : X86::EAX,
11078 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11079 Regs64bit ? X86::RDX : X86::EDX,
11080 cpInH, cpInL.getValue(1));
11081 SDValue swapInL, swapInH;
11082 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11083 DAG.getConstant(0, HalfT));
11084 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11085 DAG.getConstant(1, HalfT));
11086 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11087 Regs64bit ? X86::RBX : X86::EBX,
11088 swapInL, cpInH.getValue(1));
11089 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11090 Regs64bit ? X86::RCX : X86::ECX,
11091 swapInH, swapInL.getValue(1));
11092 SDValue Ops[] = { swapInH.getValue(0),
11094 swapInH.getValue(1) };
11095 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11096 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11097 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11098 X86ISD::LCMPXCHG8_DAG;
11099 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11101 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11102 Regs64bit ? X86::RAX : X86::EAX,
11103 HalfT, Result.getValue(1));
11104 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11105 Regs64bit ? X86::RDX : X86::EDX,
11106 HalfT, cpOutL.getValue(2));
11107 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11108 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11109 Results.push_back(cpOutH.getValue(1));
11112 case ISD::ATOMIC_LOAD_ADD:
11113 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11115 case ISD::ATOMIC_LOAD_AND:
11116 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11118 case ISD::ATOMIC_LOAD_NAND:
11119 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11121 case ISD::ATOMIC_LOAD_OR:
11122 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11124 case ISD::ATOMIC_LOAD_SUB:
11125 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11127 case ISD::ATOMIC_LOAD_XOR:
11128 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11130 case ISD::ATOMIC_SWAP:
11131 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11133 case ISD::ATOMIC_LOAD:
11134 ReplaceATOMIC_LOAD(N, Results, DAG);
11138 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11140 default: return NULL;
11141 case X86ISD::BSF: return "X86ISD::BSF";
11142 case X86ISD::BSR: return "X86ISD::BSR";
11143 case X86ISD::SHLD: return "X86ISD::SHLD";
11144 case X86ISD::SHRD: return "X86ISD::SHRD";
11145 case X86ISD::FAND: return "X86ISD::FAND";
11146 case X86ISD::FOR: return "X86ISD::FOR";
11147 case X86ISD::FXOR: return "X86ISD::FXOR";
11148 case X86ISD::FSRL: return "X86ISD::FSRL";
11149 case X86ISD::FILD: return "X86ISD::FILD";
11150 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11151 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11152 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11153 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11154 case X86ISD::FLD: return "X86ISD::FLD";
11155 case X86ISD::FST: return "X86ISD::FST";
11156 case X86ISD::CALL: return "X86ISD::CALL";
11157 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11158 case X86ISD::BT: return "X86ISD::BT";
11159 case X86ISD::CMP: return "X86ISD::CMP";
11160 case X86ISD::COMI: return "X86ISD::COMI";
11161 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11162 case X86ISD::SETCC: return "X86ISD::SETCC";
11163 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11164 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11165 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11166 case X86ISD::CMOV: return "X86ISD::CMOV";
11167 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11168 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11169 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11170 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11171 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11172 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11173 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11174 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11175 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11176 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11177 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11178 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11179 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11180 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11181 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11182 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11183 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11184 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11185 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11186 case X86ISD::HADD: return "X86ISD::HADD";
11187 case X86ISD::HSUB: return "X86ISD::HSUB";
11188 case X86ISD::FHADD: return "X86ISD::FHADD";
11189 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11190 case X86ISD::FMAX: return "X86ISD::FMAX";
11191 case X86ISD::FMIN: return "X86ISD::FMIN";
11192 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11193 case X86ISD::FRCP: return "X86ISD::FRCP";
11194 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11195 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11196 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11197 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11198 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11199 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
11200 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11201 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11202 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11203 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11204 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11205 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11206 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11207 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11208 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11209 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11210 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11211 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11212 case X86ISD::VSHL: return "X86ISD::VSHL";
11213 case X86ISD::VSRL: return "X86ISD::VSRL";
11214 case X86ISD::VSRA: return "X86ISD::VSRA";
11215 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11216 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11217 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11218 case X86ISD::CMPP: return "X86ISD::CMPP";
11219 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11220 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11221 case X86ISD::ADD: return "X86ISD::ADD";
11222 case X86ISD::SUB: return "X86ISD::SUB";
11223 case X86ISD::ADC: return "X86ISD::ADC";
11224 case X86ISD::SBB: return "X86ISD::SBB";
11225 case X86ISD::SMUL: return "X86ISD::SMUL";
11226 case X86ISD::UMUL: return "X86ISD::UMUL";
11227 case X86ISD::INC: return "X86ISD::INC";
11228 case X86ISD::DEC: return "X86ISD::DEC";
11229 case X86ISD::OR: return "X86ISD::OR";
11230 case X86ISD::XOR: return "X86ISD::XOR";
11231 case X86ISD::AND: return "X86ISD::AND";
11232 case X86ISD::ANDN: return "X86ISD::ANDN";
11233 case X86ISD::BLSI: return "X86ISD::BLSI";
11234 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11235 case X86ISD::BLSR: return "X86ISD::BLSR";
11236 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11237 case X86ISD::PTEST: return "X86ISD::PTEST";
11238 case X86ISD::TESTP: return "X86ISD::TESTP";
11239 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11240 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11241 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11242 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11243 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11244 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11245 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11246 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11247 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11248 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11249 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11250 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11251 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11252 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11253 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11254 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11255 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11256 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11257 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11258 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11259 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11260 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11261 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11262 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11263 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11264 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11265 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11266 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11267 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11268 case X86ISD::SAHF: return "X86ISD::SAHF";
11272 // isLegalAddressingMode - Return true if the addressing mode represented
11273 // by AM is legal for this target, for a load/store of the specified type.
11274 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11276 // X86 supports extremely general addressing modes.
11277 CodeModel::Model M = getTargetMachine().getCodeModel();
11278 Reloc::Model R = getTargetMachine().getRelocationModel();
11280 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11281 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11286 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11288 // If a reference to this global requires an extra load, we can't fold it.
11289 if (isGlobalStubReference(GVFlags))
11292 // If BaseGV requires a register for the PIC base, we cannot also have a
11293 // BaseReg specified.
11294 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11297 // If lower 4G is not available, then we must use rip-relative addressing.
11298 if ((M != CodeModel::Small || R != Reloc::Static) &&
11299 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11303 switch (AM.Scale) {
11309 // These scales always work.
11314 // These scales are formed with basereg+scalereg. Only accept if there is
11319 default: // Other stuff never works.
11327 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11328 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11330 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11331 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11332 if (NumBits1 <= NumBits2)
11337 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11338 if (!VT1.isInteger() || !VT2.isInteger())
11340 unsigned NumBits1 = VT1.getSizeInBits();
11341 unsigned NumBits2 = VT2.getSizeInBits();
11342 if (NumBits1 <= NumBits2)
11347 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11348 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11349 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11352 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11353 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11354 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11357 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11358 // i16 instructions are longer (0x66 prefix) and potentially slower.
11359 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11362 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11363 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11364 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11365 /// are assumed to be legal.
11367 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11369 // Very little shuffling can be done for 64-bit vectors right now.
11370 if (VT.getSizeInBits() == 64)
11373 // FIXME: pshufb, blends, shifts.
11374 return (VT.getVectorNumElements() == 2 ||
11375 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11376 isMOVLMask(M, VT) ||
11377 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11378 isPSHUFDMask(M, VT) ||
11379 isPSHUFHWMask(M, VT) ||
11380 isPSHUFLWMask(M, VT) ||
11381 isPALIGNRMask(M, VT, Subtarget) ||
11382 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11383 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11384 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11385 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11389 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11391 unsigned NumElts = VT.getVectorNumElements();
11392 // FIXME: This collection of masks seems suspect.
11395 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11396 return (isMOVLMask(Mask, VT) ||
11397 isCommutedMOVLMask(Mask, VT, true) ||
11398 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11399 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11404 //===----------------------------------------------------------------------===//
11405 // X86 Scheduler Hooks
11406 //===----------------------------------------------------------------------===//
11408 // private utility function
11409 MachineBasicBlock *
11410 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11411 MachineBasicBlock *MBB,
11418 const TargetRegisterClass *RC,
11419 bool Invert) const {
11420 // For the atomic bitwise operator, we generate
11423 // ld t1 = [bitinstr.addr]
11424 // op t2 = t1, [bitinstr.val]
11425 // not t3 = t2 (if Invert)
11427 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11429 // fallthrough -->nextMBB
11430 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11431 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11432 MachineFunction::iterator MBBIter = MBB;
11435 /// First build the CFG
11436 MachineFunction *F = MBB->getParent();
11437 MachineBasicBlock *thisMBB = MBB;
11438 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11439 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11440 F->insert(MBBIter, newMBB);
11441 F->insert(MBBIter, nextMBB);
11443 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11444 nextMBB->splice(nextMBB->begin(), thisMBB,
11445 llvm::next(MachineBasicBlock::iterator(bInstr)),
11447 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11449 // Update thisMBB to fall through to newMBB
11450 thisMBB->addSuccessor(newMBB);
11452 // newMBB jumps to itself and fall through to nextMBB
11453 newMBB->addSuccessor(nextMBB);
11454 newMBB->addSuccessor(newMBB);
11456 // Insert instructions into newMBB based on incoming instruction
11457 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11458 "unexpected number of operands");
11459 DebugLoc dl = bInstr->getDebugLoc();
11460 MachineOperand& destOper = bInstr->getOperand(0);
11461 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11462 int numArgs = bInstr->getNumOperands() - 1;
11463 for (int i=0; i < numArgs; ++i)
11464 argOpers[i] = &bInstr->getOperand(i+1);
11466 // x86 address has 4 operands: base, index, scale, and displacement
11467 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11468 int valArgIndx = lastAddrIndx + 1;
11470 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11471 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11472 for (int i=0; i <= lastAddrIndx; ++i)
11473 (*MIB).addOperand(*argOpers[i]);
11475 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11476 assert((argOpers[valArgIndx]->isReg() ||
11477 argOpers[valArgIndx]->isImm()) &&
11478 "invalid operand");
11479 if (argOpers[valArgIndx]->isReg())
11480 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11482 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11484 (*MIB).addOperand(*argOpers[valArgIndx]);
11486 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11488 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11493 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11496 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11497 for (int i=0; i <= lastAddrIndx; ++i)
11498 (*MIB).addOperand(*argOpers[i]);
11500 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11501 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11502 bInstr->memoperands_end());
11504 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11505 MIB.addReg(EAXreg);
11508 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11510 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11514 // private utility function: 64 bit atomics on 32 bit host.
11515 MachineBasicBlock *
11516 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11517 MachineBasicBlock *MBB,
11522 bool Invert) const {
11523 // For the atomic bitwise operator, we generate
11524 // thisMBB (instructions are in pairs, except cmpxchg8b)
11525 // ld t1,t2 = [bitinstr.addr]
11527 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11528 // op t5, t6 <- out1, out2, [bitinstr.val]
11529 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11530 // neg t7, t8 < t5, t6 (if Invert)
11531 // mov ECX, EBX <- t5, t6
11532 // mov EAX, EDX <- t1, t2
11533 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11534 // mov t3, t4 <- EAX, EDX
11536 // result in out1, out2
11537 // fallthrough -->nextMBB
11539 const TargetRegisterClass *RC = &X86::GR32RegClass;
11540 const unsigned LoadOpc = X86::MOV32rm;
11541 const unsigned NotOpc = X86::NOT32r;
11542 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11543 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11544 MachineFunction::iterator MBBIter = MBB;
11547 /// First build the CFG
11548 MachineFunction *F = MBB->getParent();
11549 MachineBasicBlock *thisMBB = MBB;
11550 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11551 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11552 F->insert(MBBIter, newMBB);
11553 F->insert(MBBIter, nextMBB);
11555 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11556 nextMBB->splice(nextMBB->begin(), thisMBB,
11557 llvm::next(MachineBasicBlock::iterator(bInstr)),
11559 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11561 // Update thisMBB to fall through to newMBB
11562 thisMBB->addSuccessor(newMBB);
11564 // newMBB jumps to itself and fall through to nextMBB
11565 newMBB->addSuccessor(nextMBB);
11566 newMBB->addSuccessor(newMBB);
11568 DebugLoc dl = bInstr->getDebugLoc();
11569 // Insert instructions into newMBB based on incoming instruction
11570 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11571 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11572 "unexpected number of operands");
11573 MachineOperand& dest1Oper = bInstr->getOperand(0);
11574 MachineOperand& dest2Oper = bInstr->getOperand(1);
11575 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11576 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11577 argOpers[i] = &bInstr->getOperand(i+2);
11579 // We use some of the operands multiple times, so conservatively just
11580 // clear any kill flags that might be present.
11581 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11582 argOpers[i]->setIsKill(false);
11585 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11586 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11588 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11589 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11590 for (int i=0; i <= lastAddrIndx; ++i)
11591 (*MIB).addOperand(*argOpers[i]);
11592 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11593 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11594 // add 4 to displacement.
11595 for (int i=0; i <= lastAddrIndx-2; ++i)
11596 (*MIB).addOperand(*argOpers[i]);
11597 MachineOperand newOp3 = *(argOpers[3]);
11598 if (newOp3.isImm())
11599 newOp3.setImm(newOp3.getImm()+4);
11601 newOp3.setOffset(newOp3.getOffset()+4);
11602 (*MIB).addOperand(newOp3);
11603 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11605 // t3/4 are defined later, at the bottom of the loop
11606 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11607 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11608 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11609 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11610 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11611 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11613 // The subsequent operations should be using the destination registers of
11614 // the PHI instructions.
11615 t1 = dest1Oper.getReg();
11616 t2 = dest2Oper.getReg();
11618 int valArgIndx = lastAddrIndx + 1;
11619 assert((argOpers[valArgIndx]->isReg() ||
11620 argOpers[valArgIndx]->isImm()) &&
11621 "invalid operand");
11622 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11623 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11624 if (argOpers[valArgIndx]->isReg())
11625 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11627 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11628 if (regOpcL != X86::MOV32rr)
11630 (*MIB).addOperand(*argOpers[valArgIndx]);
11631 assert(argOpers[valArgIndx + 1]->isReg() ==
11632 argOpers[valArgIndx]->isReg());
11633 assert(argOpers[valArgIndx + 1]->isImm() ==
11634 argOpers[valArgIndx]->isImm());
11635 if (argOpers[valArgIndx + 1]->isReg())
11636 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11638 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11639 if (regOpcH != X86::MOV32rr)
11641 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11645 t7 = F->getRegInfo().createVirtualRegister(RC);
11646 t8 = F->getRegInfo().createVirtualRegister(RC);
11647 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11648 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11654 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11656 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11659 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11661 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11664 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11665 for (int i=0; i <= lastAddrIndx; ++i)
11666 (*MIB).addOperand(*argOpers[i]);
11668 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11669 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11670 bInstr->memoperands_end());
11672 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11673 MIB.addReg(X86::EAX);
11674 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11675 MIB.addReg(X86::EDX);
11678 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11680 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11684 // private utility function
11685 MachineBasicBlock *
11686 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11687 MachineBasicBlock *MBB,
11688 unsigned cmovOpc) const {
11689 // For the atomic min/max operator, we generate
11692 // ld t1 = [min/max.addr]
11693 // mov t2 = [min/max.val]
11695 // cmov[cond] t2 = t1
11697 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11699 // fallthrough -->nextMBB
11701 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11702 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11703 MachineFunction::iterator MBBIter = MBB;
11706 /// First build the CFG
11707 MachineFunction *F = MBB->getParent();
11708 MachineBasicBlock *thisMBB = MBB;
11709 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11710 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11711 F->insert(MBBIter, newMBB);
11712 F->insert(MBBIter, nextMBB);
11714 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11715 nextMBB->splice(nextMBB->begin(), thisMBB,
11716 llvm::next(MachineBasicBlock::iterator(mInstr)),
11718 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11720 // Update thisMBB to fall through to newMBB
11721 thisMBB->addSuccessor(newMBB);
11723 // newMBB jumps to newMBB and fall through to nextMBB
11724 newMBB->addSuccessor(nextMBB);
11725 newMBB->addSuccessor(newMBB);
11727 DebugLoc dl = mInstr->getDebugLoc();
11728 // Insert instructions into newMBB based on incoming instruction
11729 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11730 "unexpected number of operands");
11731 MachineOperand& destOper = mInstr->getOperand(0);
11732 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11733 int numArgs = mInstr->getNumOperands() - 1;
11734 for (int i=0; i < numArgs; ++i)
11735 argOpers[i] = &mInstr->getOperand(i+1);
11737 // x86 address has 4 operands: base, index, scale, and displacement
11738 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11739 int valArgIndx = lastAddrIndx + 1;
11741 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11742 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11743 for (int i=0; i <= lastAddrIndx; ++i)
11744 (*MIB).addOperand(*argOpers[i]);
11746 // We only support register and immediate values
11747 assert((argOpers[valArgIndx]->isReg() ||
11748 argOpers[valArgIndx]->isImm()) &&
11749 "invalid operand");
11751 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11752 if (argOpers[valArgIndx]->isReg())
11753 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11755 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11756 (*MIB).addOperand(*argOpers[valArgIndx]);
11758 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11761 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11766 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11767 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11771 // Cmp and exchange if none has modified the memory location
11772 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11773 for (int i=0; i <= lastAddrIndx; ++i)
11774 (*MIB).addOperand(*argOpers[i]);
11776 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11777 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11778 mInstr->memoperands_end());
11780 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11781 MIB.addReg(X86::EAX);
11784 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11786 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11790 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11791 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11792 // in the .td file.
11793 MachineBasicBlock *
11794 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11795 unsigned numArgs, bool memArg) const {
11796 assert(Subtarget->hasSSE42() &&
11797 "Target must have SSE4.2 or AVX features enabled");
11799 DebugLoc dl = MI->getDebugLoc();
11800 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11802 if (!Subtarget->hasAVX()) {
11804 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11806 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11809 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11811 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11814 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11815 for (unsigned i = 0; i < numArgs; ++i) {
11816 MachineOperand &Op = MI->getOperand(i+1);
11817 if (!(Op.isReg() && Op.isImplicit()))
11818 MIB.addOperand(Op);
11820 BuildMI(*BB, MI, dl,
11821 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11822 MI->getOperand(0).getReg())
11823 .addReg(X86::XMM0);
11825 MI->eraseFromParent();
11829 MachineBasicBlock *
11830 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11831 DebugLoc dl = MI->getDebugLoc();
11832 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11834 // Address into RAX/EAX, other two args into ECX, EDX.
11835 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11836 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11837 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11838 for (int i = 0; i < X86::AddrNumOperands; ++i)
11839 MIB.addOperand(MI->getOperand(i));
11841 unsigned ValOps = X86::AddrNumOperands;
11842 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11843 .addReg(MI->getOperand(ValOps).getReg());
11844 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11845 .addReg(MI->getOperand(ValOps+1).getReg());
11847 // The instruction doesn't actually take any operands though.
11848 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11850 MI->eraseFromParent(); // The pseudo is gone now.
11854 MachineBasicBlock *
11855 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11856 DebugLoc dl = MI->getDebugLoc();
11857 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11859 // First arg in ECX, the second in EAX.
11860 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11861 .addReg(MI->getOperand(0).getReg());
11862 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11863 .addReg(MI->getOperand(1).getReg());
11865 // The instruction doesn't actually take any operands though.
11866 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11868 MI->eraseFromParent(); // The pseudo is gone now.
11872 MachineBasicBlock *
11873 X86TargetLowering::EmitVAARG64WithCustomInserter(
11875 MachineBasicBlock *MBB) const {
11876 // Emit va_arg instruction on X86-64.
11878 // Operands to this pseudo-instruction:
11879 // 0 ) Output : destination address (reg)
11880 // 1-5) Input : va_list address (addr, i64mem)
11881 // 6 ) ArgSize : Size (in bytes) of vararg type
11882 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11883 // 8 ) Align : Alignment of type
11884 // 9 ) EFLAGS (implicit-def)
11886 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11887 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11889 unsigned DestReg = MI->getOperand(0).getReg();
11890 MachineOperand &Base = MI->getOperand(1);
11891 MachineOperand &Scale = MI->getOperand(2);
11892 MachineOperand &Index = MI->getOperand(3);
11893 MachineOperand &Disp = MI->getOperand(4);
11894 MachineOperand &Segment = MI->getOperand(5);
11895 unsigned ArgSize = MI->getOperand(6).getImm();
11896 unsigned ArgMode = MI->getOperand(7).getImm();
11897 unsigned Align = MI->getOperand(8).getImm();
11899 // Memory Reference
11900 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11901 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11902 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11904 // Machine Information
11905 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11906 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11907 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11908 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11909 DebugLoc DL = MI->getDebugLoc();
11911 // struct va_list {
11914 // i64 overflow_area (address)
11915 // i64 reg_save_area (address)
11917 // sizeof(va_list) = 24
11918 // alignment(va_list) = 8
11920 unsigned TotalNumIntRegs = 6;
11921 unsigned TotalNumXMMRegs = 8;
11922 bool UseGPOffset = (ArgMode == 1);
11923 bool UseFPOffset = (ArgMode == 2);
11924 unsigned MaxOffset = TotalNumIntRegs * 8 +
11925 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11927 /* Align ArgSize to a multiple of 8 */
11928 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11929 bool NeedsAlign = (Align > 8);
11931 MachineBasicBlock *thisMBB = MBB;
11932 MachineBasicBlock *overflowMBB;
11933 MachineBasicBlock *offsetMBB;
11934 MachineBasicBlock *endMBB;
11936 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11937 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11938 unsigned OffsetReg = 0;
11940 if (!UseGPOffset && !UseFPOffset) {
11941 // If we only pull from the overflow region, we don't create a branch.
11942 // We don't need to alter control flow.
11943 OffsetDestReg = 0; // unused
11944 OverflowDestReg = DestReg;
11947 overflowMBB = thisMBB;
11950 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11951 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11952 // If not, pull from overflow_area. (branch to overflowMBB)
11957 // offsetMBB overflowMBB
11962 // Registers for the PHI in endMBB
11963 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11964 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11966 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11967 MachineFunction *MF = MBB->getParent();
11968 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11969 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11970 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11972 MachineFunction::iterator MBBIter = MBB;
11975 // Insert the new basic blocks
11976 MF->insert(MBBIter, offsetMBB);
11977 MF->insert(MBBIter, overflowMBB);
11978 MF->insert(MBBIter, endMBB);
11980 // Transfer the remainder of MBB and its successor edges to endMBB.
11981 endMBB->splice(endMBB->begin(), thisMBB,
11982 llvm::next(MachineBasicBlock::iterator(MI)),
11984 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11986 // Make offsetMBB and overflowMBB successors of thisMBB
11987 thisMBB->addSuccessor(offsetMBB);
11988 thisMBB->addSuccessor(overflowMBB);
11990 // endMBB is a successor of both offsetMBB and overflowMBB
11991 offsetMBB->addSuccessor(endMBB);
11992 overflowMBB->addSuccessor(endMBB);
11994 // Load the offset value into a register
11995 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11996 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
12000 .addDisp(Disp, UseFPOffset ? 4 : 0)
12001 .addOperand(Segment)
12002 .setMemRefs(MMOBegin, MMOEnd);
12004 // Check if there is enough room left to pull this argument.
12005 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
12007 .addImm(MaxOffset + 8 - ArgSizeA8);
12009 // Branch to "overflowMBB" if offset >= max
12010 // Fall through to "offsetMBB" otherwise
12011 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
12012 .addMBB(overflowMBB);
12015 // In offsetMBB, emit code to use the reg_save_area.
12017 assert(OffsetReg != 0);
12019 // Read the reg_save_area address.
12020 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
12021 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
12026 .addOperand(Segment)
12027 .setMemRefs(MMOBegin, MMOEnd);
12029 // Zero-extend the offset
12030 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
12031 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
12034 .addImm(X86::sub_32bit);
12036 // Add the offset to the reg_save_area to get the final address.
12037 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
12038 .addReg(OffsetReg64)
12039 .addReg(RegSaveReg);
12041 // Compute the offset for the next argument
12042 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12043 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
12045 .addImm(UseFPOffset ? 16 : 8);
12047 // Store it back into the va_list.
12048 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
12052 .addDisp(Disp, UseFPOffset ? 4 : 0)
12053 .addOperand(Segment)
12054 .addReg(NextOffsetReg)
12055 .setMemRefs(MMOBegin, MMOEnd);
12058 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
12063 // Emit code to use overflow area
12066 // Load the overflow_area address into a register.
12067 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
12068 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
12073 .addOperand(Segment)
12074 .setMemRefs(MMOBegin, MMOEnd);
12076 // If we need to align it, do so. Otherwise, just copy the address
12077 // to OverflowDestReg.
12079 // Align the overflow address
12080 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12081 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12083 // aligned_addr = (addr + (align-1)) & ~(align-1)
12084 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12085 .addReg(OverflowAddrReg)
12088 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12090 .addImm(~(uint64_t)(Align-1));
12092 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12093 .addReg(OverflowAddrReg);
12096 // Compute the next overflow address after this argument.
12097 // (the overflow address should be kept 8-byte aligned)
12098 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12099 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12100 .addReg(OverflowDestReg)
12101 .addImm(ArgSizeA8);
12103 // Store the new overflow address.
12104 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12109 .addOperand(Segment)
12110 .addReg(NextAddrReg)
12111 .setMemRefs(MMOBegin, MMOEnd);
12113 // If we branched, emit the PHI to the front of endMBB.
12115 BuildMI(*endMBB, endMBB->begin(), DL,
12116 TII->get(X86::PHI), DestReg)
12117 .addReg(OffsetDestReg).addMBB(offsetMBB)
12118 .addReg(OverflowDestReg).addMBB(overflowMBB);
12121 // Erase the pseudo instruction
12122 MI->eraseFromParent();
12127 MachineBasicBlock *
12128 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12130 MachineBasicBlock *MBB) const {
12131 // Emit code to save XMM registers to the stack. The ABI says that the
12132 // number of registers to save is given in %al, so it's theoretically
12133 // possible to do an indirect jump trick to avoid saving all of them,
12134 // however this code takes a simpler approach and just executes all
12135 // of the stores if %al is non-zero. It's less code, and it's probably
12136 // easier on the hardware branch predictor, and stores aren't all that
12137 // expensive anyway.
12139 // Create the new basic blocks. One block contains all the XMM stores,
12140 // and one block is the final destination regardless of whether any
12141 // stores were performed.
12142 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12143 MachineFunction *F = MBB->getParent();
12144 MachineFunction::iterator MBBIter = MBB;
12146 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12147 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12148 F->insert(MBBIter, XMMSaveMBB);
12149 F->insert(MBBIter, EndMBB);
12151 // Transfer the remainder of MBB and its successor edges to EndMBB.
12152 EndMBB->splice(EndMBB->begin(), MBB,
12153 llvm::next(MachineBasicBlock::iterator(MI)),
12155 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12157 // The original block will now fall through to the XMM save block.
12158 MBB->addSuccessor(XMMSaveMBB);
12159 // The XMMSaveMBB will fall through to the end block.
12160 XMMSaveMBB->addSuccessor(EndMBB);
12162 // Now add the instructions.
12163 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12164 DebugLoc DL = MI->getDebugLoc();
12166 unsigned CountReg = MI->getOperand(0).getReg();
12167 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12168 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12170 if (!Subtarget->isTargetWin64()) {
12171 // If %al is 0, branch around the XMM save block.
12172 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12173 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12174 MBB->addSuccessor(EndMBB);
12177 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12178 // In the XMM save block, save all the XMM argument registers.
12179 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12180 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12181 MachineMemOperand *MMO =
12182 F->getMachineMemOperand(
12183 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12184 MachineMemOperand::MOStore,
12185 /*Size=*/16, /*Align=*/16);
12186 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12187 .addFrameIndex(RegSaveFrameIndex)
12188 .addImm(/*Scale=*/1)
12189 .addReg(/*IndexReg=*/0)
12190 .addImm(/*Disp=*/Offset)
12191 .addReg(/*Segment=*/0)
12192 .addReg(MI->getOperand(i).getReg())
12193 .addMemOperand(MMO);
12196 MI->eraseFromParent(); // The pseudo instruction is gone now.
12201 // The EFLAGS operand of SelectItr might be missing a kill marker
12202 // because there were multiple uses of EFLAGS, and ISel didn't know
12203 // which to mark. Figure out whether SelectItr should have had a
12204 // kill marker, and set it if it should. Returns the correct kill
12206 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12207 MachineBasicBlock* BB,
12208 const TargetRegisterInfo* TRI) {
12209 // Scan forward through BB for a use/def of EFLAGS.
12210 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12211 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12212 const MachineInstr& mi = *miI;
12213 if (mi.readsRegister(X86::EFLAGS))
12215 if (mi.definesRegister(X86::EFLAGS))
12216 break; // Should have kill-flag - update below.
12219 // If we hit the end of the block, check whether EFLAGS is live into a
12221 if (miI == BB->end()) {
12222 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12223 sEnd = BB->succ_end();
12224 sItr != sEnd; ++sItr) {
12225 MachineBasicBlock* succ = *sItr;
12226 if (succ->isLiveIn(X86::EFLAGS))
12231 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12232 // out. SelectMI should have a kill flag on EFLAGS.
12233 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12237 MachineBasicBlock *
12238 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12239 MachineBasicBlock *BB) const {
12240 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12241 DebugLoc DL = MI->getDebugLoc();
12243 // To "insert" a SELECT_CC instruction, we actually have to insert the
12244 // diamond control-flow pattern. The incoming instruction knows the
12245 // destination vreg to set, the condition code register to branch on, the
12246 // true/false values to select between, and a branch opcode to use.
12247 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12248 MachineFunction::iterator It = BB;
12254 // cmpTY ccX, r1, r2
12256 // fallthrough --> copy0MBB
12257 MachineBasicBlock *thisMBB = BB;
12258 MachineFunction *F = BB->getParent();
12259 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12260 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12261 F->insert(It, copy0MBB);
12262 F->insert(It, sinkMBB);
12264 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12265 // live into the sink and copy blocks.
12266 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12267 if (!MI->killsRegister(X86::EFLAGS) &&
12268 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12269 copy0MBB->addLiveIn(X86::EFLAGS);
12270 sinkMBB->addLiveIn(X86::EFLAGS);
12273 // Transfer the remainder of BB and its successor edges to sinkMBB.
12274 sinkMBB->splice(sinkMBB->begin(), BB,
12275 llvm::next(MachineBasicBlock::iterator(MI)),
12277 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12279 // Add the true and fallthrough blocks as its successors.
12280 BB->addSuccessor(copy0MBB);
12281 BB->addSuccessor(sinkMBB);
12283 // Create the conditional branch instruction.
12285 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12286 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12289 // %FalseValue = ...
12290 // # fallthrough to sinkMBB
12291 copy0MBB->addSuccessor(sinkMBB);
12294 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12296 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12297 TII->get(X86::PHI), MI->getOperand(0).getReg())
12298 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12299 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12301 MI->eraseFromParent(); // The pseudo instruction is gone now.
12305 MachineBasicBlock *
12306 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12307 bool Is64Bit) const {
12308 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12309 DebugLoc DL = MI->getDebugLoc();
12310 MachineFunction *MF = BB->getParent();
12311 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12313 assert(getTargetMachine().Options.EnableSegmentedStacks);
12315 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12316 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12319 // ... [Till the alloca]
12320 // If stacklet is not large enough, jump to mallocMBB
12323 // Allocate by subtracting from RSP
12324 // Jump to continueMBB
12327 // Allocate by call to runtime
12331 // [rest of original BB]
12334 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12335 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12336 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12338 MachineRegisterInfo &MRI = MF->getRegInfo();
12339 const TargetRegisterClass *AddrRegClass =
12340 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12342 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12343 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12344 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12345 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12346 sizeVReg = MI->getOperand(1).getReg(),
12347 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12349 MachineFunction::iterator MBBIter = BB;
12352 MF->insert(MBBIter, bumpMBB);
12353 MF->insert(MBBIter, mallocMBB);
12354 MF->insert(MBBIter, continueMBB);
12356 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12357 (MachineBasicBlock::iterator(MI)), BB->end());
12358 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12360 // Add code to the main basic block to check if the stack limit has been hit,
12361 // and if so, jump to mallocMBB otherwise to bumpMBB.
12362 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12363 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12364 .addReg(tmpSPVReg).addReg(sizeVReg);
12365 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12366 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12367 .addReg(SPLimitVReg);
12368 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12370 // bumpMBB simply decreases the stack pointer, since we know the current
12371 // stacklet has enough space.
12372 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12373 .addReg(SPLimitVReg);
12374 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12375 .addReg(SPLimitVReg);
12376 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12378 // Calls into a routine in libgcc to allocate more space from the heap.
12379 const uint32_t *RegMask =
12380 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12382 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12384 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12385 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12386 .addRegMask(RegMask)
12387 .addReg(X86::RAX, RegState::ImplicitDefine);
12389 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12391 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12392 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12393 .addExternalSymbol("__morestack_allocate_stack_space")
12394 .addRegMask(RegMask)
12395 .addReg(X86::EAX, RegState::ImplicitDefine);
12399 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12402 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12403 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12404 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12406 // Set up the CFG correctly.
12407 BB->addSuccessor(bumpMBB);
12408 BB->addSuccessor(mallocMBB);
12409 mallocMBB->addSuccessor(continueMBB);
12410 bumpMBB->addSuccessor(continueMBB);
12412 // Take care of the PHI nodes.
12413 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12414 MI->getOperand(0).getReg())
12415 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12416 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12418 // Delete the original pseudo instruction.
12419 MI->eraseFromParent();
12422 return continueMBB;
12425 MachineBasicBlock *
12426 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12427 MachineBasicBlock *BB) const {
12428 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12429 DebugLoc DL = MI->getDebugLoc();
12431 assert(!Subtarget->isTargetEnvMacho());
12433 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12434 // non-trivial part is impdef of ESP.
12436 if (Subtarget->isTargetWin64()) {
12437 if (Subtarget->isTargetCygMing()) {
12438 // ___chkstk(Mingw64):
12439 // Clobbers R10, R11, RAX and EFLAGS.
12441 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12442 .addExternalSymbol("___chkstk")
12443 .addReg(X86::RAX, RegState::Implicit)
12444 .addReg(X86::RSP, RegState::Implicit)
12445 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12446 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12447 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12449 // __chkstk(MSVCRT): does not update stack pointer.
12450 // Clobbers R10, R11 and EFLAGS.
12451 // FIXME: RAX(allocated size) might be reused and not killed.
12452 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12453 .addExternalSymbol("__chkstk")
12454 .addReg(X86::RAX, RegState::Implicit)
12455 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12456 // RAX has the offset to subtracted from RSP.
12457 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12462 const char *StackProbeSymbol =
12463 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12465 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12466 .addExternalSymbol(StackProbeSymbol)
12467 .addReg(X86::EAX, RegState::Implicit)
12468 .addReg(X86::ESP, RegState::Implicit)
12469 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12470 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12471 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12474 MI->eraseFromParent(); // The pseudo instruction is gone now.
12478 MachineBasicBlock *
12479 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12480 MachineBasicBlock *BB) const {
12481 // This is pretty easy. We're taking the value that we received from
12482 // our load from the relocation, sticking it in either RDI (x86-64)
12483 // or EAX and doing an indirect call. The return value will then
12484 // be in the normal return register.
12485 const X86InstrInfo *TII
12486 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12487 DebugLoc DL = MI->getDebugLoc();
12488 MachineFunction *F = BB->getParent();
12490 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12491 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12493 // Get a register mask for the lowered call.
12494 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12495 // proper register mask.
12496 const uint32_t *RegMask =
12497 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12498 if (Subtarget->is64Bit()) {
12499 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12500 TII->get(X86::MOV64rm), X86::RDI)
12502 .addImm(0).addReg(0)
12503 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12504 MI->getOperand(3).getTargetFlags())
12506 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12507 addDirectMem(MIB, X86::RDI);
12508 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12509 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12510 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12511 TII->get(X86::MOV32rm), X86::EAX)
12513 .addImm(0).addReg(0)
12514 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12515 MI->getOperand(3).getTargetFlags())
12517 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12518 addDirectMem(MIB, X86::EAX);
12519 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12521 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12522 TII->get(X86::MOV32rm), X86::EAX)
12523 .addReg(TII->getGlobalBaseReg(F))
12524 .addImm(0).addReg(0)
12525 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12526 MI->getOperand(3).getTargetFlags())
12528 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12529 addDirectMem(MIB, X86::EAX);
12530 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12533 MI->eraseFromParent(); // The pseudo instruction is gone now.
12537 MachineBasicBlock *
12538 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12539 MachineBasicBlock *BB) const {
12540 switch (MI->getOpcode()) {
12541 default: llvm_unreachable("Unexpected instr type to insert");
12542 case X86::TAILJMPd64:
12543 case X86::TAILJMPr64:
12544 case X86::TAILJMPm64:
12545 llvm_unreachable("TAILJMP64 would not be touched here.");
12546 case X86::TCRETURNdi64:
12547 case X86::TCRETURNri64:
12548 case X86::TCRETURNmi64:
12550 case X86::WIN_ALLOCA:
12551 return EmitLoweredWinAlloca(MI, BB);
12552 case X86::SEG_ALLOCA_32:
12553 return EmitLoweredSegAlloca(MI, BB, false);
12554 case X86::SEG_ALLOCA_64:
12555 return EmitLoweredSegAlloca(MI, BB, true);
12556 case X86::TLSCall_32:
12557 case X86::TLSCall_64:
12558 return EmitLoweredTLSCall(MI, BB);
12559 case X86::CMOV_GR8:
12560 case X86::CMOV_FR32:
12561 case X86::CMOV_FR64:
12562 case X86::CMOV_V4F32:
12563 case X86::CMOV_V2F64:
12564 case X86::CMOV_V2I64:
12565 case X86::CMOV_V8F32:
12566 case X86::CMOV_V4F64:
12567 case X86::CMOV_V4I64:
12568 case X86::CMOV_GR16:
12569 case X86::CMOV_GR32:
12570 case X86::CMOV_RFP32:
12571 case X86::CMOV_RFP64:
12572 case X86::CMOV_RFP80:
12573 return EmitLoweredSelect(MI, BB);
12575 case X86::FP32_TO_INT16_IN_MEM:
12576 case X86::FP32_TO_INT32_IN_MEM:
12577 case X86::FP32_TO_INT64_IN_MEM:
12578 case X86::FP64_TO_INT16_IN_MEM:
12579 case X86::FP64_TO_INT32_IN_MEM:
12580 case X86::FP64_TO_INT64_IN_MEM:
12581 case X86::FP80_TO_INT16_IN_MEM:
12582 case X86::FP80_TO_INT32_IN_MEM:
12583 case X86::FP80_TO_INT64_IN_MEM: {
12584 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12585 DebugLoc DL = MI->getDebugLoc();
12587 // Change the floating point control register to use "round towards zero"
12588 // mode when truncating to an integer value.
12589 MachineFunction *F = BB->getParent();
12590 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12591 addFrameReference(BuildMI(*BB, MI, DL,
12592 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12594 // Load the old value of the high byte of the control word...
12596 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12597 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12600 // Set the high part to be round to zero...
12601 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12604 // Reload the modified control word now...
12605 addFrameReference(BuildMI(*BB, MI, DL,
12606 TII->get(X86::FLDCW16m)), CWFrameIdx);
12608 // Restore the memory image of control word to original value
12609 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12612 // Get the X86 opcode to use.
12614 switch (MI->getOpcode()) {
12615 default: llvm_unreachable("illegal opcode!");
12616 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12617 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12618 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12619 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12620 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12621 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12622 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12623 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12624 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12628 MachineOperand &Op = MI->getOperand(0);
12630 AM.BaseType = X86AddressMode::RegBase;
12631 AM.Base.Reg = Op.getReg();
12633 AM.BaseType = X86AddressMode::FrameIndexBase;
12634 AM.Base.FrameIndex = Op.getIndex();
12636 Op = MI->getOperand(1);
12638 AM.Scale = Op.getImm();
12639 Op = MI->getOperand(2);
12641 AM.IndexReg = Op.getImm();
12642 Op = MI->getOperand(3);
12643 if (Op.isGlobal()) {
12644 AM.GV = Op.getGlobal();
12646 AM.Disp = Op.getImm();
12648 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12649 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12651 // Reload the original control word now.
12652 addFrameReference(BuildMI(*BB, MI, DL,
12653 TII->get(X86::FLDCW16m)), CWFrameIdx);
12655 MI->eraseFromParent(); // The pseudo instruction is gone now.
12658 // String/text processing lowering.
12659 case X86::PCMPISTRM128REG:
12660 case X86::VPCMPISTRM128REG:
12661 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12662 case X86::PCMPISTRM128MEM:
12663 case X86::VPCMPISTRM128MEM:
12664 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12665 case X86::PCMPESTRM128REG:
12666 case X86::VPCMPESTRM128REG:
12667 return EmitPCMP(MI, BB, 5, false /* in mem */);
12668 case X86::PCMPESTRM128MEM:
12669 case X86::VPCMPESTRM128MEM:
12670 return EmitPCMP(MI, BB, 5, true /* in mem */);
12672 // Thread synchronization.
12674 return EmitMonitor(MI, BB);
12676 return EmitMwait(MI, BB);
12678 // Atomic Lowering.
12679 case X86::ATOMAND32:
12680 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12681 X86::AND32ri, X86::MOV32rm,
12683 X86::NOT32r, X86::EAX,
12684 &X86::GR32RegClass);
12685 case X86::ATOMOR32:
12686 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12687 X86::OR32ri, X86::MOV32rm,
12689 X86::NOT32r, X86::EAX,
12690 &X86::GR32RegClass);
12691 case X86::ATOMXOR32:
12692 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12693 X86::XOR32ri, X86::MOV32rm,
12695 X86::NOT32r, X86::EAX,
12696 &X86::GR32RegClass);
12697 case X86::ATOMNAND32:
12698 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12699 X86::AND32ri, X86::MOV32rm,
12701 X86::NOT32r, X86::EAX,
12702 &X86::GR32RegClass, true);
12703 case X86::ATOMMIN32:
12704 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12705 case X86::ATOMMAX32:
12706 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12707 case X86::ATOMUMIN32:
12708 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12709 case X86::ATOMUMAX32:
12710 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12712 case X86::ATOMAND16:
12713 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12714 X86::AND16ri, X86::MOV16rm,
12716 X86::NOT16r, X86::AX,
12717 &X86::GR16RegClass);
12718 case X86::ATOMOR16:
12719 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12720 X86::OR16ri, X86::MOV16rm,
12722 X86::NOT16r, X86::AX,
12723 &X86::GR16RegClass);
12724 case X86::ATOMXOR16:
12725 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12726 X86::XOR16ri, X86::MOV16rm,
12728 X86::NOT16r, X86::AX,
12729 &X86::GR16RegClass);
12730 case X86::ATOMNAND16:
12731 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12732 X86::AND16ri, X86::MOV16rm,
12734 X86::NOT16r, X86::AX,
12735 &X86::GR16RegClass, true);
12736 case X86::ATOMMIN16:
12737 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12738 case X86::ATOMMAX16:
12739 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12740 case X86::ATOMUMIN16:
12741 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12742 case X86::ATOMUMAX16:
12743 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12745 case X86::ATOMAND8:
12746 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12747 X86::AND8ri, X86::MOV8rm,
12749 X86::NOT8r, X86::AL,
12750 &X86::GR8RegClass);
12752 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12753 X86::OR8ri, X86::MOV8rm,
12755 X86::NOT8r, X86::AL,
12756 &X86::GR8RegClass);
12757 case X86::ATOMXOR8:
12758 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12759 X86::XOR8ri, X86::MOV8rm,
12761 X86::NOT8r, X86::AL,
12762 &X86::GR8RegClass);
12763 case X86::ATOMNAND8:
12764 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12765 X86::AND8ri, X86::MOV8rm,
12767 X86::NOT8r, X86::AL,
12768 &X86::GR8RegClass, true);
12769 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12770 // This group is for 64-bit host.
12771 case X86::ATOMAND64:
12772 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12773 X86::AND64ri32, X86::MOV64rm,
12775 X86::NOT64r, X86::RAX,
12776 &X86::GR64RegClass);
12777 case X86::ATOMOR64:
12778 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12779 X86::OR64ri32, X86::MOV64rm,
12781 X86::NOT64r, X86::RAX,
12782 &X86::GR64RegClass);
12783 case X86::ATOMXOR64:
12784 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12785 X86::XOR64ri32, X86::MOV64rm,
12787 X86::NOT64r, X86::RAX,
12788 &X86::GR64RegClass);
12789 case X86::ATOMNAND64:
12790 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12791 X86::AND64ri32, X86::MOV64rm,
12793 X86::NOT64r, X86::RAX,
12794 &X86::GR64RegClass, true);
12795 case X86::ATOMMIN64:
12796 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12797 case X86::ATOMMAX64:
12798 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12799 case X86::ATOMUMIN64:
12800 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12801 case X86::ATOMUMAX64:
12802 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12804 // This group does 64-bit operations on a 32-bit host.
12805 case X86::ATOMAND6432:
12806 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12807 X86::AND32rr, X86::AND32rr,
12808 X86::AND32ri, X86::AND32ri,
12810 case X86::ATOMOR6432:
12811 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12812 X86::OR32rr, X86::OR32rr,
12813 X86::OR32ri, X86::OR32ri,
12815 case X86::ATOMXOR6432:
12816 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12817 X86::XOR32rr, X86::XOR32rr,
12818 X86::XOR32ri, X86::XOR32ri,
12820 case X86::ATOMNAND6432:
12821 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12822 X86::AND32rr, X86::AND32rr,
12823 X86::AND32ri, X86::AND32ri,
12825 case X86::ATOMADD6432:
12826 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12827 X86::ADD32rr, X86::ADC32rr,
12828 X86::ADD32ri, X86::ADC32ri,
12830 case X86::ATOMSUB6432:
12831 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12832 X86::SUB32rr, X86::SBB32rr,
12833 X86::SUB32ri, X86::SBB32ri,
12835 case X86::ATOMSWAP6432:
12836 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12837 X86::MOV32rr, X86::MOV32rr,
12838 X86::MOV32ri, X86::MOV32ri,
12840 case X86::VASTART_SAVE_XMM_REGS:
12841 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12843 case X86::VAARG_64:
12844 return EmitVAARG64WithCustomInserter(MI, BB);
12848 //===----------------------------------------------------------------------===//
12849 // X86 Optimization Hooks
12850 //===----------------------------------------------------------------------===//
12852 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12855 const SelectionDAG &DAG,
12856 unsigned Depth) const {
12857 unsigned BitWidth = KnownZero.getBitWidth();
12858 unsigned Opc = Op.getOpcode();
12859 assert((Opc >= ISD::BUILTIN_OP_END ||
12860 Opc == ISD::INTRINSIC_WO_CHAIN ||
12861 Opc == ISD::INTRINSIC_W_CHAIN ||
12862 Opc == ISD::INTRINSIC_VOID) &&
12863 "Should use MaskedValueIsZero if you don't know whether Op"
12864 " is a target node!");
12866 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12880 // These nodes' second result is a boolean.
12881 if (Op.getResNo() == 0)
12884 case X86ISD::SETCC:
12885 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12887 case ISD::INTRINSIC_WO_CHAIN: {
12888 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12889 unsigned NumLoBits = 0;
12892 case Intrinsic::x86_sse_movmsk_ps:
12893 case Intrinsic::x86_avx_movmsk_ps_256:
12894 case Intrinsic::x86_sse2_movmsk_pd:
12895 case Intrinsic::x86_avx_movmsk_pd_256:
12896 case Intrinsic::x86_mmx_pmovmskb:
12897 case Intrinsic::x86_sse2_pmovmskb_128:
12898 case Intrinsic::x86_avx2_pmovmskb: {
12899 // High bits of movmskp{s|d}, pmovmskb are known zero.
12901 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12902 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12903 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12904 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12905 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12906 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12907 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12908 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12910 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12919 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12920 unsigned Depth) const {
12921 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12922 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12923 return Op.getValueType().getScalarType().getSizeInBits();
12929 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12930 /// node is a GlobalAddress + offset.
12931 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12932 const GlobalValue* &GA,
12933 int64_t &Offset) const {
12934 if (N->getOpcode() == X86ISD::Wrapper) {
12935 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12936 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12937 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12941 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12944 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12945 /// same as extracting the high 128-bit part of 256-bit vector and then
12946 /// inserting the result into the low part of a new 256-bit vector
12947 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12948 EVT VT = SVOp->getValueType(0);
12949 unsigned NumElems = VT.getVectorNumElements();
12951 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12952 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
12953 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12954 SVOp->getMaskElt(j) >= 0)
12960 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12961 /// same as extracting the low 128-bit part of 256-bit vector and then
12962 /// inserting the result into the high part of a new 256-bit vector
12963 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12964 EVT VT = SVOp->getValueType(0);
12965 unsigned NumElems = VT.getVectorNumElements();
12967 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12968 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
12969 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12970 SVOp->getMaskElt(j) >= 0)
12976 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12977 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12978 TargetLowering::DAGCombinerInfo &DCI,
12979 const X86Subtarget* Subtarget) {
12980 DebugLoc dl = N->getDebugLoc();
12981 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12982 SDValue V1 = SVOp->getOperand(0);
12983 SDValue V2 = SVOp->getOperand(1);
12984 EVT VT = SVOp->getValueType(0);
12985 unsigned NumElems = VT.getVectorNumElements();
12987 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12988 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12992 // V UNDEF BUILD_VECTOR UNDEF
12994 // CONCAT_VECTOR CONCAT_VECTOR
12997 // RESULT: V + zero extended
12999 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
13000 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
13001 V1.getOperand(1).getOpcode() != ISD::UNDEF)
13004 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
13007 // To match the shuffle mask, the first half of the mask should
13008 // be exactly the first vector, and all the rest a splat with the
13009 // first element of the second one.
13010 for (unsigned i = 0; i != NumElems/2; ++i)
13011 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
13012 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
13015 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
13016 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
13017 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
13018 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
13020 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
13022 Ld->getPointerInfo(),
13023 Ld->getAlignment(),
13024 false/*isVolatile*/, true/*ReadMem*/,
13025 false/*WriteMem*/);
13026 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
13029 // Emit a zeroed vector and insert the desired subvector on its
13031 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13032 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
13033 return DCI.CombineTo(N, InsV);
13036 //===--------------------------------------------------------------------===//
13037 // Combine some shuffles into subvector extracts and inserts:
13040 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13041 if (isShuffleHigh128VectorInsertLow(SVOp)) {
13042 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
13043 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
13044 return DCI.CombineTo(N, InsV);
13047 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13048 if (isShuffleLow128VectorInsertHigh(SVOp)) {
13049 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
13050 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
13051 return DCI.CombineTo(N, InsV);
13057 /// PerformShuffleCombine - Performs several different shuffle combines.
13058 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
13059 TargetLowering::DAGCombinerInfo &DCI,
13060 const X86Subtarget *Subtarget) {
13061 DebugLoc dl = N->getDebugLoc();
13062 EVT VT = N->getValueType(0);
13064 // Don't create instructions with illegal types after legalize types has run.
13065 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13066 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
13069 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
13070 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
13071 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13072 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13074 // Only handle 128 wide vector from here on.
13075 if (VT.getSizeInBits() != 128)
13078 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13079 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
13080 // consecutive, non-overlapping, and in the right order.
13081 SmallVector<SDValue, 16> Elts;
13082 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13083 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13085 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13089 /// DCI, PerformTruncateCombine - Converts truncate operation to
13090 /// a sequence of vector shuffle operations.
13091 /// It is possible when we truncate 256-bit vector to 128-bit vector
13093 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13094 DAGCombinerInfo &DCI) const {
13095 if (!DCI.isBeforeLegalizeOps())
13098 if (!Subtarget->hasAVX())
13101 EVT VT = N->getValueType(0);
13102 SDValue Op = N->getOperand(0);
13103 EVT OpVT = Op.getValueType();
13104 DebugLoc dl = N->getDebugLoc();
13106 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13108 if (Subtarget->hasAVX2()) {
13109 // AVX2: v4i64 -> v4i32
13112 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13114 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13115 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13118 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13119 DAG.getIntPtrConstant(0));
13122 // AVX: v4i64 -> v4i32
13123 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13124 DAG.getIntPtrConstant(0));
13126 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13127 DAG.getIntPtrConstant(2));
13129 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13130 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13133 static const int ShufMask1[] = {0, 2, 0, 0};
13135 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
13136 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
13139 static const int ShufMask2[] = {0, 1, 4, 5};
13141 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13144 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13146 if (Subtarget->hasAVX2()) {
13147 // AVX2: v8i32 -> v8i16
13149 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13152 SmallVector<SDValue,32> pshufbMask;
13153 for (unsigned i = 0; i < 2; ++i) {
13154 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13155 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13156 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13157 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13158 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13159 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13160 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13161 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13162 for (unsigned j = 0; j < 8; ++j)
13163 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13165 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13166 &pshufbMask[0], 32);
13167 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13169 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13171 static const int ShufMask[] = {0, 2, -1, -1};
13172 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13175 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13176 DAG.getIntPtrConstant(0));
13178 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13181 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13182 DAG.getIntPtrConstant(0));
13184 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13185 DAG.getIntPtrConstant(4));
13187 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13188 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13191 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13192 -1, -1, -1, -1, -1, -1, -1, -1};
13194 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
13196 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
13199 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13200 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13203 static const int ShufMask2[] = {0, 1, 4, 5};
13205 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13206 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13212 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13213 /// specific shuffle of a load can be folded into a single element load.
13214 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13215 /// shuffles have been customed lowered so we need to handle those here.
13216 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13217 TargetLowering::DAGCombinerInfo &DCI) {
13218 if (DCI.isBeforeLegalizeOps())
13221 SDValue InVec = N->getOperand(0);
13222 SDValue EltNo = N->getOperand(1);
13224 if (!isa<ConstantSDNode>(EltNo))
13227 EVT VT = InVec.getValueType();
13229 bool HasShuffleIntoBitcast = false;
13230 if (InVec.getOpcode() == ISD::BITCAST) {
13231 // Don't duplicate a load with other uses.
13232 if (!InVec.hasOneUse())
13234 EVT BCVT = InVec.getOperand(0).getValueType();
13235 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13237 InVec = InVec.getOperand(0);
13238 HasShuffleIntoBitcast = true;
13241 if (!isTargetShuffle(InVec.getOpcode()))
13244 // Don't duplicate a load with other uses.
13245 if (!InVec.hasOneUse())
13248 SmallVector<int, 16> ShuffleMask;
13250 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle))
13253 // Select the input vector, guarding against out of range extract vector.
13254 unsigned NumElems = VT.getVectorNumElements();
13255 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13256 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13257 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13258 : InVec.getOperand(1);
13260 // If inputs to shuffle are the same for both ops, then allow 2 uses
13261 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13263 if (LdNode.getOpcode() == ISD::BITCAST) {
13264 // Don't duplicate a load with other uses.
13265 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13268 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13269 LdNode = LdNode.getOperand(0);
13272 if (!ISD::isNormalLoad(LdNode.getNode()))
13275 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13277 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13280 if (HasShuffleIntoBitcast) {
13281 // If there's a bitcast before the shuffle, check if the load type and
13282 // alignment is valid.
13283 unsigned Align = LN0->getAlignment();
13284 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13285 unsigned NewAlign = TLI.getTargetData()->
13286 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13288 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13292 // All checks match so transform back to vector_shuffle so that DAG combiner
13293 // can finish the job
13294 DebugLoc dl = N->getDebugLoc();
13296 // Create shuffle node taking into account the case that its a unary shuffle
13297 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13298 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13299 InVec.getOperand(0), Shuffle,
13301 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13302 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13306 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13307 /// generation and convert it from being a bunch of shuffles and extracts
13308 /// to a simple store and scalar loads to extract the elements.
13309 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13310 TargetLowering::DAGCombinerInfo &DCI) {
13311 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13312 if (NewOp.getNode())
13315 SDValue InputVector = N->getOperand(0);
13317 // Only operate on vectors of 4 elements, where the alternative shuffling
13318 // gets to be more expensive.
13319 if (InputVector.getValueType() != MVT::v4i32)
13322 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13323 // single use which is a sign-extend or zero-extend, and all elements are
13325 SmallVector<SDNode *, 4> Uses;
13326 unsigned ExtractedElements = 0;
13327 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13328 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13329 if (UI.getUse().getResNo() != InputVector.getResNo())
13332 SDNode *Extract = *UI;
13333 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13336 if (Extract->getValueType(0) != MVT::i32)
13338 if (!Extract->hasOneUse())
13340 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13341 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13343 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13346 // Record which element was extracted.
13347 ExtractedElements |=
13348 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13350 Uses.push_back(Extract);
13353 // If not all the elements were used, this may not be worthwhile.
13354 if (ExtractedElements != 15)
13357 // Ok, we've now decided to do the transformation.
13358 DebugLoc dl = InputVector.getDebugLoc();
13360 // Store the value to a temporary stack slot.
13361 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13362 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13363 MachinePointerInfo(), false, false, 0);
13365 // Replace each use (extract) with a load of the appropriate element.
13366 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13367 UE = Uses.end(); UI != UE; ++UI) {
13368 SDNode *Extract = *UI;
13370 // cOMpute the element's address.
13371 SDValue Idx = Extract->getOperand(1);
13373 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13374 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13375 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13376 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13378 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13379 StackPtr, OffsetVal);
13381 // Load the scalar.
13382 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13383 ScalarAddr, MachinePointerInfo(),
13384 false, false, false, 0);
13386 // Replace the exact with the load.
13387 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13390 // The replacement was made in place; don't return anything.
13394 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13396 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13397 TargetLowering::DAGCombinerInfo &DCI,
13398 const X86Subtarget *Subtarget) {
13401 DebugLoc DL = N->getDebugLoc();
13402 SDValue Cond = N->getOperand(0);
13403 // Get the LHS/RHS of the select.
13404 SDValue LHS = N->getOperand(1);
13405 SDValue RHS = N->getOperand(2);
13406 EVT VT = LHS.getValueType();
13408 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13409 // instructions match the semantics of the common C idiom x<y?x:y but not
13410 // x<=y?x:y, because of how they handle negative zero (which can be
13411 // ignored in unsafe-math mode).
13412 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13413 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13414 (Subtarget->hasSSE2() ||
13415 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13416 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13418 unsigned Opcode = 0;
13419 // Check for x CC y ? x : y.
13420 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13421 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13425 // Converting this to a min would handle NaNs incorrectly, and swapping
13426 // the operands would cause it to handle comparisons between positive
13427 // and negative zero incorrectly.
13428 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13429 if (!DAG.getTarget().Options.UnsafeFPMath &&
13430 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13432 std::swap(LHS, RHS);
13434 Opcode = X86ISD::FMIN;
13437 // Converting this to a min would handle comparisons between positive
13438 // and negative zero incorrectly.
13439 if (!DAG.getTarget().Options.UnsafeFPMath &&
13440 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13442 Opcode = X86ISD::FMIN;
13445 // Converting this to a min would handle both negative zeros and NaNs
13446 // incorrectly, but we can swap the operands to fix both.
13447 std::swap(LHS, RHS);
13451 Opcode = X86ISD::FMIN;
13455 // Converting this to a max would handle comparisons between positive
13456 // and negative zero incorrectly.
13457 if (!DAG.getTarget().Options.UnsafeFPMath &&
13458 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13460 Opcode = X86ISD::FMAX;
13463 // Converting this to a max would handle NaNs incorrectly, and swapping
13464 // the operands would cause it to handle comparisons between positive
13465 // and negative zero incorrectly.
13466 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13467 if (!DAG.getTarget().Options.UnsafeFPMath &&
13468 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13470 std::swap(LHS, RHS);
13472 Opcode = X86ISD::FMAX;
13475 // Converting this to a max would handle both negative zeros and NaNs
13476 // incorrectly, but we can swap the operands to fix both.
13477 std::swap(LHS, RHS);
13481 Opcode = X86ISD::FMAX;
13484 // Check for x CC y ? y : x -- a min/max with reversed arms.
13485 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13486 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13490 // Converting this to a min would handle comparisons between positive
13491 // and negative zero incorrectly, and swapping the operands would
13492 // cause it to handle NaNs incorrectly.
13493 if (!DAG.getTarget().Options.UnsafeFPMath &&
13494 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13495 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13497 std::swap(LHS, RHS);
13499 Opcode = X86ISD::FMIN;
13502 // Converting this to a min would handle NaNs incorrectly.
13503 if (!DAG.getTarget().Options.UnsafeFPMath &&
13504 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13506 Opcode = X86ISD::FMIN;
13509 // Converting this to a min would handle both negative zeros and NaNs
13510 // incorrectly, but we can swap the operands to fix both.
13511 std::swap(LHS, RHS);
13515 Opcode = X86ISD::FMIN;
13519 // Converting this to a max would handle NaNs incorrectly.
13520 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13522 Opcode = X86ISD::FMAX;
13525 // Converting this to a max would handle comparisons between positive
13526 // and negative zero incorrectly, and swapping the operands would
13527 // cause it to handle NaNs incorrectly.
13528 if (!DAG.getTarget().Options.UnsafeFPMath &&
13529 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13530 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13532 std::swap(LHS, RHS);
13534 Opcode = X86ISD::FMAX;
13537 // Converting this to a max would handle both negative zeros and NaNs
13538 // incorrectly, but we can swap the operands to fix both.
13539 std::swap(LHS, RHS);
13543 Opcode = X86ISD::FMAX;
13549 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13552 // If this is a select between two integer constants, try to do some
13554 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13555 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13556 // Don't do this for crazy integer types.
13557 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13558 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13559 // so that TrueC (the true value) is larger than FalseC.
13560 bool NeedsCondInvert = false;
13562 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13563 // Efficiently invertible.
13564 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13565 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13566 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13567 NeedsCondInvert = true;
13568 std::swap(TrueC, FalseC);
13571 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13572 if (FalseC->getAPIntValue() == 0 &&
13573 TrueC->getAPIntValue().isPowerOf2()) {
13574 if (NeedsCondInvert) // Invert the condition if needed.
13575 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13576 DAG.getConstant(1, Cond.getValueType()));
13578 // Zero extend the condition if needed.
13579 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13581 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13582 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13583 DAG.getConstant(ShAmt, MVT::i8));
13586 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13587 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13588 if (NeedsCondInvert) // Invert the condition if needed.
13589 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13590 DAG.getConstant(1, Cond.getValueType()));
13592 // Zero extend the condition if needed.
13593 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13594 FalseC->getValueType(0), Cond);
13595 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13596 SDValue(FalseC, 0));
13599 // Optimize cases that will turn into an LEA instruction. This requires
13600 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13601 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13602 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13603 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13605 bool isFastMultiplier = false;
13607 switch ((unsigned char)Diff) {
13609 case 1: // result = add base, cond
13610 case 2: // result = lea base( , cond*2)
13611 case 3: // result = lea base(cond, cond*2)
13612 case 4: // result = lea base( , cond*4)
13613 case 5: // result = lea base(cond, cond*4)
13614 case 8: // result = lea base( , cond*8)
13615 case 9: // result = lea base(cond, cond*8)
13616 isFastMultiplier = true;
13621 if (isFastMultiplier) {
13622 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13623 if (NeedsCondInvert) // Invert the condition if needed.
13624 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13625 DAG.getConstant(1, Cond.getValueType()));
13627 // Zero extend the condition if needed.
13628 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13630 // Scale the condition by the difference.
13632 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13633 DAG.getConstant(Diff, Cond.getValueType()));
13635 // Add the base if non-zero.
13636 if (FalseC->getAPIntValue() != 0)
13637 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13638 SDValue(FalseC, 0));
13645 // Canonicalize max and min:
13646 // (x > y) ? x : y -> (x >= y) ? x : y
13647 // (x < y) ? x : y -> (x <= y) ? x : y
13648 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13649 // the need for an extra compare
13650 // against zero. e.g.
13651 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13653 // testl %edi, %edi
13655 // cmovgl %edi, %eax
13659 // cmovsl %eax, %edi
13660 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13661 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13662 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13663 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13668 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13669 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13670 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13671 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13676 // If we know that this node is legal then we know that it is going to be
13677 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13678 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13679 // to simplify previous instructions.
13680 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13681 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13682 !DCI.isBeforeLegalize() &&
13683 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13684 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13685 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13686 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13688 APInt KnownZero, KnownOne;
13689 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13690 DCI.isBeforeLegalizeOps());
13691 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13692 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13693 DCI.CommitTargetLoweringOpt(TLO);
13699 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13700 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13701 TargetLowering::DAGCombinerInfo &DCI) {
13702 DebugLoc DL = N->getDebugLoc();
13704 // If the flag operand isn't dead, don't touch this CMOV.
13705 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13708 SDValue FalseOp = N->getOperand(0);
13709 SDValue TrueOp = N->getOperand(1);
13710 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13711 SDValue Cond = N->getOperand(3);
13712 if (CC == X86::COND_E || CC == X86::COND_NE) {
13713 switch (Cond.getOpcode()) {
13717 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13718 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13719 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13723 // If this is a select between two integer constants, try to do some
13724 // optimizations. Note that the operands are ordered the opposite of SELECT
13726 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13727 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13728 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13729 // larger than FalseC (the false value).
13730 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13731 CC = X86::GetOppositeBranchCondition(CC);
13732 std::swap(TrueC, FalseC);
13735 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13736 // This is efficient for any integer data type (including i8/i16) and
13738 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13739 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13740 DAG.getConstant(CC, MVT::i8), Cond);
13742 // Zero extend the condition if needed.
13743 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13745 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13746 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13747 DAG.getConstant(ShAmt, MVT::i8));
13748 if (N->getNumValues() == 2) // Dead flag value?
13749 return DCI.CombineTo(N, Cond, SDValue());
13753 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13754 // for any integer data type, including i8/i16.
13755 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13756 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13757 DAG.getConstant(CC, MVT::i8), Cond);
13759 // Zero extend the condition if needed.
13760 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13761 FalseC->getValueType(0), Cond);
13762 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13763 SDValue(FalseC, 0));
13765 if (N->getNumValues() == 2) // Dead flag value?
13766 return DCI.CombineTo(N, Cond, SDValue());
13770 // Optimize cases that will turn into an LEA instruction. This requires
13771 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13772 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13773 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13774 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13776 bool isFastMultiplier = false;
13778 switch ((unsigned char)Diff) {
13780 case 1: // result = add base, cond
13781 case 2: // result = lea base( , cond*2)
13782 case 3: // result = lea base(cond, cond*2)
13783 case 4: // result = lea base( , cond*4)
13784 case 5: // result = lea base(cond, cond*4)
13785 case 8: // result = lea base( , cond*8)
13786 case 9: // result = lea base(cond, cond*8)
13787 isFastMultiplier = true;
13792 if (isFastMultiplier) {
13793 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13794 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13795 DAG.getConstant(CC, MVT::i8), Cond);
13796 // Zero extend the condition if needed.
13797 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13799 // Scale the condition by the difference.
13801 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13802 DAG.getConstant(Diff, Cond.getValueType()));
13804 // Add the base if non-zero.
13805 if (FalseC->getAPIntValue() != 0)
13806 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13807 SDValue(FalseC, 0));
13808 if (N->getNumValues() == 2) // Dead flag value?
13809 return DCI.CombineTo(N, Cond, SDValue());
13819 /// PerformMulCombine - Optimize a single multiply with constant into two
13820 /// in order to implement it with two cheaper instructions, e.g.
13821 /// LEA + SHL, LEA + LEA.
13822 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13823 TargetLowering::DAGCombinerInfo &DCI) {
13824 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13827 EVT VT = N->getValueType(0);
13828 if (VT != MVT::i64)
13831 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13834 uint64_t MulAmt = C->getZExtValue();
13835 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13838 uint64_t MulAmt1 = 0;
13839 uint64_t MulAmt2 = 0;
13840 if ((MulAmt % 9) == 0) {
13842 MulAmt2 = MulAmt / 9;
13843 } else if ((MulAmt % 5) == 0) {
13845 MulAmt2 = MulAmt / 5;
13846 } else if ((MulAmt % 3) == 0) {
13848 MulAmt2 = MulAmt / 3;
13851 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13852 DebugLoc DL = N->getDebugLoc();
13854 if (isPowerOf2_64(MulAmt2) &&
13855 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13856 // If second multiplifer is pow2, issue it first. We want the multiply by
13857 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13859 std::swap(MulAmt1, MulAmt2);
13862 if (isPowerOf2_64(MulAmt1))
13863 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13864 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13866 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13867 DAG.getConstant(MulAmt1, VT));
13869 if (isPowerOf2_64(MulAmt2))
13870 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13871 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13873 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13874 DAG.getConstant(MulAmt2, VT));
13876 // Do not add new nodes to DAG combiner worklist.
13877 DCI.CombineTo(N, NewMul, false);
13882 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13883 SDValue N0 = N->getOperand(0);
13884 SDValue N1 = N->getOperand(1);
13885 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13886 EVT VT = N0.getValueType();
13888 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13889 // since the result of setcc_c is all zero's or all ones.
13890 if (VT.isInteger() && !VT.isVector() &&
13891 N1C && N0.getOpcode() == ISD::AND &&
13892 N0.getOperand(1).getOpcode() == ISD::Constant) {
13893 SDValue N00 = N0.getOperand(0);
13894 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13895 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13896 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13897 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13898 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13899 APInt ShAmt = N1C->getAPIntValue();
13900 Mask = Mask.shl(ShAmt);
13902 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13903 N00, DAG.getConstant(Mask, VT));
13908 // Hardware support for vector shifts is sparse which makes us scalarize the
13909 // vector operations in many cases. Also, on sandybridge ADD is faster than
13911 // (shl V, 1) -> add V,V
13912 if (isSplatVector(N1.getNode())) {
13913 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13914 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13915 // We shift all of the values by one. In many cases we do not have
13916 // hardware support for this operation. This is better expressed as an ADD
13918 if (N1C && (1 == N1C->getZExtValue())) {
13919 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13926 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13928 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13929 TargetLowering::DAGCombinerInfo &DCI,
13930 const X86Subtarget *Subtarget) {
13931 EVT VT = N->getValueType(0);
13932 if (N->getOpcode() == ISD::SHL) {
13933 SDValue V = PerformSHLCombine(N, DAG);
13934 if (V.getNode()) return V;
13937 // On X86 with SSE2 support, we can transform this to a vector shift if
13938 // all elements are shifted by the same amount. We can't do this in legalize
13939 // because the a constant vector is typically transformed to a constant pool
13940 // so we have no knowledge of the shift amount.
13941 if (!Subtarget->hasSSE2())
13944 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13945 (!Subtarget->hasAVX2() ||
13946 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13949 SDValue ShAmtOp = N->getOperand(1);
13950 EVT EltVT = VT.getVectorElementType();
13951 DebugLoc DL = N->getDebugLoc();
13952 SDValue BaseShAmt = SDValue();
13953 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13954 unsigned NumElts = VT.getVectorNumElements();
13956 for (; i != NumElts; ++i) {
13957 SDValue Arg = ShAmtOp.getOperand(i);
13958 if (Arg.getOpcode() == ISD::UNDEF) continue;
13962 // Handle the case where the build_vector is all undef
13963 // FIXME: Should DAG allow this?
13967 for (; i != NumElts; ++i) {
13968 SDValue Arg = ShAmtOp.getOperand(i);
13969 if (Arg.getOpcode() == ISD::UNDEF) continue;
13970 if (Arg != BaseShAmt) {
13974 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13975 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13976 SDValue InVec = ShAmtOp.getOperand(0);
13977 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13978 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13980 for (; i != NumElts; ++i) {
13981 SDValue Arg = InVec.getOperand(i);
13982 if (Arg.getOpcode() == ISD::UNDEF) continue;
13986 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13987 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13988 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13989 if (C->getZExtValue() == SplatIdx)
13990 BaseShAmt = InVec.getOperand(1);
13993 if (BaseShAmt.getNode() == 0) {
13994 // Don't create instructions with illegal types after legalize
13996 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13997 !DCI.isBeforeLegalize())
14000 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
14001 DAG.getIntPtrConstant(0));
14006 // The shift amount is an i32.
14007 if (EltVT.bitsGT(MVT::i32))
14008 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
14009 else if (EltVT.bitsLT(MVT::i32))
14010 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
14012 // The shift amount is identical so we can do a vector shift.
14013 SDValue ValOp = N->getOperand(0);
14014 switch (N->getOpcode()) {
14016 llvm_unreachable("Unknown shift opcode!");
14018 switch (VT.getSimpleVT().SimpleTy) {
14019 default: return SDValue();
14026 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
14029 switch (VT.getSimpleVT().SimpleTy) {
14030 default: return SDValue();
14035 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
14038 switch (VT.getSimpleVT().SimpleTy) {
14039 default: return SDValue();
14046 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
14052 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
14053 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
14054 // and friends. Likewise for OR -> CMPNEQSS.
14055 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
14056 TargetLowering::DAGCombinerInfo &DCI,
14057 const X86Subtarget *Subtarget) {
14060 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
14061 // we're requiring SSE2 for both.
14062 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
14063 SDValue N0 = N->getOperand(0);
14064 SDValue N1 = N->getOperand(1);
14065 SDValue CMP0 = N0->getOperand(1);
14066 SDValue CMP1 = N1->getOperand(1);
14067 DebugLoc DL = N->getDebugLoc();
14069 // The SETCCs should both refer to the same CMP.
14070 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
14073 SDValue CMP00 = CMP0->getOperand(0);
14074 SDValue CMP01 = CMP0->getOperand(1);
14075 EVT VT = CMP00.getValueType();
14077 if (VT == MVT::f32 || VT == MVT::f64) {
14078 bool ExpectingFlags = false;
14079 // Check for any users that want flags:
14080 for (SDNode::use_iterator UI = N->use_begin(),
14082 !ExpectingFlags && UI != UE; ++UI)
14083 switch (UI->getOpcode()) {
14088 ExpectingFlags = true;
14090 case ISD::CopyToReg:
14091 case ISD::SIGN_EXTEND:
14092 case ISD::ZERO_EXTEND:
14093 case ISD::ANY_EXTEND:
14097 if (!ExpectingFlags) {
14098 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14099 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14101 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14102 X86::CondCode tmp = cc0;
14107 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14108 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14109 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14110 X86ISD::NodeType NTOperator = is64BitFP ?
14111 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14112 // FIXME: need symbolic constants for these magic numbers.
14113 // See X86ATTInstPrinter.cpp:printSSECC().
14114 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14115 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14116 DAG.getConstant(x86cc, MVT::i8));
14117 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14119 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14120 DAG.getConstant(1, MVT::i32));
14121 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14122 return OneBitOfTruth;
14130 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14131 /// so it can be folded inside ANDNP.
14132 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14133 EVT VT = N->getValueType(0);
14135 // Match direct AllOnes for 128 and 256-bit vectors
14136 if (ISD::isBuildVectorAllOnes(N))
14139 // Look through a bit convert.
14140 if (N->getOpcode() == ISD::BITCAST)
14141 N = N->getOperand(0).getNode();
14143 // Sometimes the operand may come from a insert_subvector building a 256-bit
14145 if (VT.getSizeInBits() == 256 &&
14146 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14147 SDValue V1 = N->getOperand(0);
14148 SDValue V2 = N->getOperand(1);
14150 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14151 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14152 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14153 ISD::isBuildVectorAllOnes(V2.getNode()))
14160 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14161 TargetLowering::DAGCombinerInfo &DCI,
14162 const X86Subtarget *Subtarget) {
14163 if (DCI.isBeforeLegalizeOps())
14166 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14170 EVT VT = N->getValueType(0);
14172 // Create ANDN, BLSI, and BLSR instructions
14173 // BLSI is X & (-X)
14174 // BLSR is X & (X-1)
14175 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14176 SDValue N0 = N->getOperand(0);
14177 SDValue N1 = N->getOperand(1);
14178 DebugLoc DL = N->getDebugLoc();
14180 // Check LHS for not
14181 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14182 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14183 // Check RHS for not
14184 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14185 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14187 // Check LHS for neg
14188 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14189 isZero(N0.getOperand(0)))
14190 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14192 // Check RHS for neg
14193 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14194 isZero(N1.getOperand(0)))
14195 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14197 // Check LHS for X-1
14198 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14199 isAllOnes(N0.getOperand(1)))
14200 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14202 // Check RHS for X-1
14203 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14204 isAllOnes(N1.getOperand(1)))
14205 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14210 // Want to form ANDNP nodes:
14211 // 1) In the hopes of then easily combining them with OR and AND nodes
14212 // to form PBLEND/PSIGN.
14213 // 2) To match ANDN packed intrinsics
14214 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14217 SDValue N0 = N->getOperand(0);
14218 SDValue N1 = N->getOperand(1);
14219 DebugLoc DL = N->getDebugLoc();
14221 // Check LHS for vnot
14222 if (N0.getOpcode() == ISD::XOR &&
14223 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14224 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14225 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14227 // Check RHS for vnot
14228 if (N1.getOpcode() == ISD::XOR &&
14229 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14230 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14231 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14236 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14237 TargetLowering::DAGCombinerInfo &DCI,
14238 const X86Subtarget *Subtarget) {
14239 if (DCI.isBeforeLegalizeOps())
14242 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14246 EVT VT = N->getValueType(0);
14248 SDValue N0 = N->getOperand(0);
14249 SDValue N1 = N->getOperand(1);
14251 // look for psign/blend
14252 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14253 if (!Subtarget->hasSSSE3() ||
14254 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14257 // Canonicalize pandn to RHS
14258 if (N0.getOpcode() == X86ISD::ANDNP)
14260 // or (and (m, y), (pandn m, x))
14261 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14262 SDValue Mask = N1.getOperand(0);
14263 SDValue X = N1.getOperand(1);
14265 if (N0.getOperand(0) == Mask)
14266 Y = N0.getOperand(1);
14267 if (N0.getOperand(1) == Mask)
14268 Y = N0.getOperand(0);
14270 // Check to see if the mask appeared in both the AND and ANDNP and
14274 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14275 // Look through mask bitcast.
14276 if (Mask.getOpcode() == ISD::BITCAST)
14277 Mask = Mask.getOperand(0);
14278 if (X.getOpcode() == ISD::BITCAST)
14279 X = X.getOperand(0);
14280 if (Y.getOpcode() == ISD::BITCAST)
14281 Y = Y.getOperand(0);
14283 EVT MaskVT = Mask.getValueType();
14285 // Validate that the Mask operand is a vector sra node.
14286 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14287 // there is no psrai.b
14288 if (Mask.getOpcode() != X86ISD::VSRAI)
14291 // Check that the SRA is all signbits.
14292 SDValue SraC = Mask.getOperand(1);
14293 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14294 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14295 if ((SraAmt + 1) != EltBits)
14298 DebugLoc DL = N->getDebugLoc();
14300 // Now we know we at least have a plendvb with the mask val. See if
14301 // we can form a psignb/w/d.
14302 // psign = x.type == y.type == mask.type && y = sub(0, x);
14303 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14304 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14305 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14306 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14307 "Unsupported VT for PSIGN");
14308 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14309 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14311 // PBLENDVB only available on SSE 4.1
14312 if (!Subtarget->hasSSE41())
14315 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14317 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14318 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14319 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14320 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14321 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14325 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14328 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14329 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14331 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14333 if (!N0.hasOneUse() || !N1.hasOneUse())
14336 SDValue ShAmt0 = N0.getOperand(1);
14337 if (ShAmt0.getValueType() != MVT::i8)
14339 SDValue ShAmt1 = N1.getOperand(1);
14340 if (ShAmt1.getValueType() != MVT::i8)
14342 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14343 ShAmt0 = ShAmt0.getOperand(0);
14344 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14345 ShAmt1 = ShAmt1.getOperand(0);
14347 DebugLoc DL = N->getDebugLoc();
14348 unsigned Opc = X86ISD::SHLD;
14349 SDValue Op0 = N0.getOperand(0);
14350 SDValue Op1 = N1.getOperand(0);
14351 if (ShAmt0.getOpcode() == ISD::SUB) {
14352 Opc = X86ISD::SHRD;
14353 std::swap(Op0, Op1);
14354 std::swap(ShAmt0, ShAmt1);
14357 unsigned Bits = VT.getSizeInBits();
14358 if (ShAmt1.getOpcode() == ISD::SUB) {
14359 SDValue Sum = ShAmt1.getOperand(0);
14360 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14361 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14362 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14363 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14364 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14365 return DAG.getNode(Opc, DL, VT,
14367 DAG.getNode(ISD::TRUNCATE, DL,
14370 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14371 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14373 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14374 return DAG.getNode(Opc, DL, VT,
14375 N0.getOperand(0), N1.getOperand(0),
14376 DAG.getNode(ISD::TRUNCATE, DL,
14383 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14384 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14385 TargetLowering::DAGCombinerInfo &DCI,
14386 const X86Subtarget *Subtarget) {
14387 if (DCI.isBeforeLegalizeOps())
14390 EVT VT = N->getValueType(0);
14392 if (VT != MVT::i32 && VT != MVT::i64)
14395 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14397 // Create BLSMSK instructions by finding X ^ (X-1)
14398 SDValue N0 = N->getOperand(0);
14399 SDValue N1 = N->getOperand(1);
14400 DebugLoc DL = N->getDebugLoc();
14402 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14403 isAllOnes(N0.getOperand(1)))
14404 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14406 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14407 isAllOnes(N1.getOperand(1)))
14408 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14413 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14414 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14415 const X86Subtarget *Subtarget) {
14416 LoadSDNode *Ld = cast<LoadSDNode>(N);
14417 EVT RegVT = Ld->getValueType(0);
14418 EVT MemVT = Ld->getMemoryVT();
14419 DebugLoc dl = Ld->getDebugLoc();
14420 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14422 ISD::LoadExtType Ext = Ld->getExtensionType();
14424 // If this is a vector EXT Load then attempt to optimize it using a
14425 // shuffle. We need SSE4 for the shuffles.
14426 // TODO: It is possible to support ZExt by zeroing the undef values
14427 // during the shuffle phase or after the shuffle.
14428 if (RegVT.isVector() && RegVT.isInteger() &&
14429 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14430 assert(MemVT != RegVT && "Cannot extend to the same type");
14431 assert(MemVT.isVector() && "Must load a vector from memory");
14433 unsigned NumElems = RegVT.getVectorNumElements();
14434 unsigned RegSz = RegVT.getSizeInBits();
14435 unsigned MemSz = MemVT.getSizeInBits();
14436 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14437 // All sizes must be a power of two
14438 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14440 // Attempt to load the original value using a single load op.
14441 // Find a scalar type which is equal to the loaded word size.
14442 MVT SclrLoadTy = MVT::i8;
14443 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14444 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14445 MVT Tp = (MVT::SimpleValueType)tp;
14446 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14452 // Proceed if a load word is found.
14453 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14455 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14456 RegSz/SclrLoadTy.getSizeInBits());
14458 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14459 RegSz/MemVT.getScalarType().getSizeInBits());
14460 // Can't shuffle using an illegal type.
14461 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14463 // Perform a single load.
14464 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14466 Ld->getPointerInfo(), Ld->isVolatile(),
14467 Ld->isNonTemporal(), Ld->isInvariant(),
14468 Ld->getAlignment());
14470 // Insert the word loaded into a vector.
14471 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14472 LoadUnitVecVT, ScalarLoad);
14474 // Bitcast the loaded value to a vector of the original element type, in
14475 // the size of the target vector type.
14476 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14478 unsigned SizeRatio = RegSz/MemSz;
14480 // Redistribute the loaded elements into the different locations.
14481 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14482 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14484 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14485 DAG.getUNDEF(WideVecVT),
14488 // Bitcast to the requested type.
14489 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14490 // Replace the original load with the new sequence
14491 // and return the new chain.
14492 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14493 return SDValue(ScalarLoad.getNode(), 1);
14499 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14500 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14501 const X86Subtarget *Subtarget) {
14502 StoreSDNode *St = cast<StoreSDNode>(N);
14503 EVT VT = St->getValue().getValueType();
14504 EVT StVT = St->getMemoryVT();
14505 DebugLoc dl = St->getDebugLoc();
14506 SDValue StoredVal = St->getOperand(1);
14507 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14509 // If we are saving a concatenation of two XMM registers, perform two stores.
14510 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14511 // 128-bit ones. If in the future the cost becomes only one memory access the
14512 // first version would be better.
14513 if (VT.getSizeInBits() == 256 &&
14514 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14515 StoredVal.getNumOperands() == 2) {
14517 SDValue Value0 = StoredVal.getOperand(0);
14518 SDValue Value1 = StoredVal.getOperand(1);
14520 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14521 SDValue Ptr0 = St->getBasePtr();
14522 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14524 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14525 St->getPointerInfo(), St->isVolatile(),
14526 St->isNonTemporal(), St->getAlignment());
14527 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14528 St->getPointerInfo(), St->isVolatile(),
14529 St->isNonTemporal(), St->getAlignment());
14530 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14533 // Optimize trunc store (of multiple scalars) to shuffle and store.
14534 // First, pack all of the elements in one place. Next, store to memory
14535 // in fewer chunks.
14536 if (St->isTruncatingStore() && VT.isVector()) {
14537 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14538 unsigned NumElems = VT.getVectorNumElements();
14539 assert(StVT != VT && "Cannot truncate to the same type");
14540 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14541 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14543 // From, To sizes and ElemCount must be pow of two
14544 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14545 // We are going to use the original vector elt for storing.
14546 // Accumulated smaller vector elements must be a multiple of the store size.
14547 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14549 unsigned SizeRatio = FromSz / ToSz;
14551 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14553 // Create a type on which we perform the shuffle
14554 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14555 StVT.getScalarType(), NumElems*SizeRatio);
14557 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14559 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14560 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14561 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14563 // Can't shuffle using an illegal type
14564 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14566 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14567 DAG.getUNDEF(WideVecVT),
14569 // At this point all of the data is stored at the bottom of the
14570 // register. We now need to save it to mem.
14572 // Find the largest store unit
14573 MVT StoreType = MVT::i8;
14574 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14575 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14576 MVT Tp = (MVT::SimpleValueType)tp;
14577 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14581 // Bitcast the original vector into a vector of store-size units
14582 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14583 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14584 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14585 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14586 SmallVector<SDValue, 8> Chains;
14587 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14588 TLI.getPointerTy());
14589 SDValue Ptr = St->getBasePtr();
14591 // Perform one or more big stores into memory.
14592 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14593 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14594 StoreType, ShuffWide,
14595 DAG.getIntPtrConstant(i));
14596 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14597 St->getPointerInfo(), St->isVolatile(),
14598 St->isNonTemporal(), St->getAlignment());
14599 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14600 Chains.push_back(Ch);
14603 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14608 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14609 // the FP state in cases where an emms may be missing.
14610 // A preferable solution to the general problem is to figure out the right
14611 // places to insert EMMS. This qualifies as a quick hack.
14613 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14614 if (VT.getSizeInBits() != 64)
14617 const Function *F = DAG.getMachineFunction().getFunction();
14618 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14619 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14620 && Subtarget->hasSSE2();
14621 if ((VT.isVector() ||
14622 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14623 isa<LoadSDNode>(St->getValue()) &&
14624 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14625 St->getChain().hasOneUse() && !St->isVolatile()) {
14626 SDNode* LdVal = St->getValue().getNode();
14627 LoadSDNode *Ld = 0;
14628 int TokenFactorIndex = -1;
14629 SmallVector<SDValue, 8> Ops;
14630 SDNode* ChainVal = St->getChain().getNode();
14631 // Must be a store of a load. We currently handle two cases: the load
14632 // is a direct child, and it's under an intervening TokenFactor. It is
14633 // possible to dig deeper under nested TokenFactors.
14634 if (ChainVal == LdVal)
14635 Ld = cast<LoadSDNode>(St->getChain());
14636 else if (St->getValue().hasOneUse() &&
14637 ChainVal->getOpcode() == ISD::TokenFactor) {
14638 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14639 if (ChainVal->getOperand(i).getNode() == LdVal) {
14640 TokenFactorIndex = i;
14641 Ld = cast<LoadSDNode>(St->getValue());
14643 Ops.push_back(ChainVal->getOperand(i));
14647 if (!Ld || !ISD::isNormalLoad(Ld))
14650 // If this is not the MMX case, i.e. we are just turning i64 load/store
14651 // into f64 load/store, avoid the transformation if there are multiple
14652 // uses of the loaded value.
14653 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14656 DebugLoc LdDL = Ld->getDebugLoc();
14657 DebugLoc StDL = N->getDebugLoc();
14658 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14659 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14661 if (Subtarget->is64Bit() || F64IsLegal) {
14662 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14663 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14664 Ld->getPointerInfo(), Ld->isVolatile(),
14665 Ld->isNonTemporal(), Ld->isInvariant(),
14666 Ld->getAlignment());
14667 SDValue NewChain = NewLd.getValue(1);
14668 if (TokenFactorIndex != -1) {
14669 Ops.push_back(NewChain);
14670 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14673 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14674 St->getPointerInfo(),
14675 St->isVolatile(), St->isNonTemporal(),
14676 St->getAlignment());
14679 // Otherwise, lower to two pairs of 32-bit loads / stores.
14680 SDValue LoAddr = Ld->getBasePtr();
14681 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14682 DAG.getConstant(4, MVT::i32));
14684 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14685 Ld->getPointerInfo(),
14686 Ld->isVolatile(), Ld->isNonTemporal(),
14687 Ld->isInvariant(), Ld->getAlignment());
14688 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14689 Ld->getPointerInfo().getWithOffset(4),
14690 Ld->isVolatile(), Ld->isNonTemporal(),
14692 MinAlign(Ld->getAlignment(), 4));
14694 SDValue NewChain = LoLd.getValue(1);
14695 if (TokenFactorIndex != -1) {
14696 Ops.push_back(LoLd);
14697 Ops.push_back(HiLd);
14698 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14702 LoAddr = St->getBasePtr();
14703 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14704 DAG.getConstant(4, MVT::i32));
14706 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14707 St->getPointerInfo(),
14708 St->isVolatile(), St->isNonTemporal(),
14709 St->getAlignment());
14710 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14711 St->getPointerInfo().getWithOffset(4),
14713 St->isNonTemporal(),
14714 MinAlign(St->getAlignment(), 4));
14715 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14720 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14721 /// and return the operands for the horizontal operation in LHS and RHS. A
14722 /// horizontal operation performs the binary operation on successive elements
14723 /// of its first operand, then on successive elements of its second operand,
14724 /// returning the resulting values in a vector. For example, if
14725 /// A = < float a0, float a1, float a2, float a3 >
14727 /// B = < float b0, float b1, float b2, float b3 >
14728 /// then the result of doing a horizontal operation on A and B is
14729 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14730 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14731 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14732 /// set to A, RHS to B, and the routine returns 'true'.
14733 /// Note that the binary operation should have the property that if one of the
14734 /// operands is UNDEF then the result is UNDEF.
14735 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14736 // Look for the following pattern: if
14737 // A = < float a0, float a1, float a2, float a3 >
14738 // B = < float b0, float b1, float b2, float b3 >
14740 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14741 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14742 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14743 // which is A horizontal-op B.
14745 // At least one of the operands should be a vector shuffle.
14746 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14747 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14750 EVT VT = LHS.getValueType();
14752 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14753 "Unsupported vector type for horizontal add/sub");
14755 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14756 // operate independently on 128-bit lanes.
14757 unsigned NumElts = VT.getVectorNumElements();
14758 unsigned NumLanes = VT.getSizeInBits()/128;
14759 unsigned NumLaneElts = NumElts / NumLanes;
14760 assert((NumLaneElts % 2 == 0) &&
14761 "Vector type should have an even number of elements in each lane");
14762 unsigned HalfLaneElts = NumLaneElts/2;
14764 // View LHS in the form
14765 // LHS = VECTOR_SHUFFLE A, B, LMask
14766 // If LHS is not a shuffle then pretend it is the shuffle
14767 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14768 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14771 SmallVector<int, 16> LMask(NumElts);
14772 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14773 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14774 A = LHS.getOperand(0);
14775 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14776 B = LHS.getOperand(1);
14777 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14778 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14780 if (LHS.getOpcode() != ISD::UNDEF)
14782 for (unsigned i = 0; i != NumElts; ++i)
14786 // Likewise, view RHS in the form
14787 // RHS = VECTOR_SHUFFLE C, D, RMask
14789 SmallVector<int, 16> RMask(NumElts);
14790 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14791 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14792 C = RHS.getOperand(0);
14793 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14794 D = RHS.getOperand(1);
14795 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14796 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14798 if (RHS.getOpcode() != ISD::UNDEF)
14800 for (unsigned i = 0; i != NumElts; ++i)
14804 // Check that the shuffles are both shuffling the same vectors.
14805 if (!(A == C && B == D) && !(A == D && B == C))
14808 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14809 if (!A.getNode() && !B.getNode())
14812 // If A and B occur in reverse order in RHS, then "swap" them (which means
14813 // rewriting the mask).
14815 CommuteVectorShuffleMask(RMask, NumElts);
14817 // At this point LHS and RHS are equivalent to
14818 // LHS = VECTOR_SHUFFLE A, B, LMask
14819 // RHS = VECTOR_SHUFFLE A, B, RMask
14820 // Check that the masks correspond to performing a horizontal operation.
14821 for (unsigned i = 0; i != NumElts; ++i) {
14822 int LIdx = LMask[i], RIdx = RMask[i];
14824 // Ignore any UNDEF components.
14825 if (LIdx < 0 || RIdx < 0 ||
14826 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14827 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14830 // Check that successive elements are being operated on. If not, this is
14831 // not a horizontal operation.
14832 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14833 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14834 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14835 if (!(LIdx == Index && RIdx == Index + 1) &&
14836 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14840 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14841 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14845 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14846 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14847 const X86Subtarget *Subtarget) {
14848 EVT VT = N->getValueType(0);
14849 SDValue LHS = N->getOperand(0);
14850 SDValue RHS = N->getOperand(1);
14852 // Try to synthesize horizontal adds from adds of shuffles.
14853 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14854 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14855 isHorizontalBinOp(LHS, RHS, true))
14856 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14860 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14861 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14862 const X86Subtarget *Subtarget) {
14863 EVT VT = N->getValueType(0);
14864 SDValue LHS = N->getOperand(0);
14865 SDValue RHS = N->getOperand(1);
14867 // Try to synthesize horizontal subs from subs of shuffles.
14868 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14869 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14870 isHorizontalBinOp(LHS, RHS, false))
14871 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14875 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14876 /// X86ISD::FXOR nodes.
14877 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14878 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14879 // F[X]OR(0.0, x) -> x
14880 // F[X]OR(x, 0.0) -> x
14881 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14882 if (C->getValueAPF().isPosZero())
14883 return N->getOperand(1);
14884 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14885 if (C->getValueAPF().isPosZero())
14886 return N->getOperand(0);
14890 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14891 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14892 // FAND(0.0, x) -> 0.0
14893 // FAND(x, 0.0) -> 0.0
14894 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14895 if (C->getValueAPF().isPosZero())
14896 return N->getOperand(0);
14897 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14898 if (C->getValueAPF().isPosZero())
14899 return N->getOperand(1);
14903 static SDValue PerformBTCombine(SDNode *N,
14905 TargetLowering::DAGCombinerInfo &DCI) {
14906 // BT ignores high bits in the bit index operand.
14907 SDValue Op1 = N->getOperand(1);
14908 if (Op1.hasOneUse()) {
14909 unsigned BitWidth = Op1.getValueSizeInBits();
14910 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14911 APInt KnownZero, KnownOne;
14912 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14913 !DCI.isBeforeLegalizeOps());
14914 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14915 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14916 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14917 DCI.CommitTargetLoweringOpt(TLO);
14922 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14923 SDValue Op = N->getOperand(0);
14924 if (Op.getOpcode() == ISD::BITCAST)
14925 Op = Op.getOperand(0);
14926 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14927 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14928 VT.getVectorElementType().getSizeInBits() ==
14929 OpVT.getVectorElementType().getSizeInBits()) {
14930 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14935 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14936 TargetLowering::DAGCombinerInfo &DCI,
14937 const X86Subtarget *Subtarget) {
14938 if (!DCI.isBeforeLegalizeOps())
14941 if (!Subtarget->hasAVX())
14944 EVT VT = N->getValueType(0);
14945 SDValue Op = N->getOperand(0);
14946 EVT OpVT = Op.getValueType();
14947 DebugLoc dl = N->getDebugLoc();
14949 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14950 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14952 if (Subtarget->hasAVX2())
14953 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
14955 // Optimize vectors in AVX mode
14956 // Sign extend v8i16 to v8i32 and
14959 // Divide input vector into two parts
14960 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14961 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14962 // concat the vectors to original VT
14964 unsigned NumElems = OpVT.getVectorNumElements();
14965 SmallVector<int,8> ShufMask1(NumElems, -1);
14966 for (unsigned i = 0; i != NumElems/2; ++i)
14969 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14972 SmallVector<int,8> ShufMask2(NumElems, -1);
14973 for (unsigned i = 0; i != NumElems/2; ++i)
14974 ShufMask2[i] = i + NumElems/2;
14976 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14979 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14980 VT.getVectorNumElements()/2);
14982 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14983 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14985 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14990 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14991 TargetLowering::DAGCombinerInfo &DCI,
14992 const X86Subtarget *Subtarget) {
14993 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14994 // (and (i32 x86isd::setcc_carry), 1)
14995 // This eliminates the zext. This transformation is necessary because
14996 // ISD::SETCC is always legalized to i8.
14997 DebugLoc dl = N->getDebugLoc();
14998 SDValue N0 = N->getOperand(0);
14999 EVT VT = N->getValueType(0);
15000 EVT OpVT = N0.getValueType();
15002 if (N0.getOpcode() == ISD::AND &&
15004 N0.getOperand(0).hasOneUse()) {
15005 SDValue N00 = N0.getOperand(0);
15006 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
15008 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
15009 if (!C || C->getZExtValue() != 1)
15011 return DAG.getNode(ISD::AND, dl, VT,
15012 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
15013 N00.getOperand(0), N00.getOperand(1)),
15014 DAG.getConstant(1, VT));
15017 // Optimize vectors in AVX mode:
15020 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
15021 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
15022 // Concat upper and lower parts.
15025 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
15026 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
15027 // Concat upper and lower parts.
15029 if (!DCI.isBeforeLegalizeOps())
15032 if (!Subtarget->hasAVX())
15035 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
15036 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
15038 if (Subtarget->hasAVX2())
15039 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
15041 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
15042 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec);
15043 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec);
15045 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
15046 VT.getVectorNumElements()/2);
15048 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
15049 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
15051 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15057 // Optimize x == -y --> x+y == 0
15058 // x != -y --> x+y != 0
15059 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15060 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
15061 SDValue LHS = N->getOperand(0);
15062 SDValue RHS = N->getOperand(1);
15064 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
15065 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
15066 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
15067 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15068 LHS.getValueType(), RHS, LHS.getOperand(1));
15069 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15070 addV, DAG.getConstant(0, addV.getValueType()), CC);
15072 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
15073 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
15074 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
15075 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15076 RHS.getValueType(), LHS, RHS.getOperand(1));
15077 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15078 addV, DAG.getConstant(0, addV.getValueType()), CC);
15083 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
15084 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15085 unsigned X86CC = N->getConstantOperandVal(0);
15086 SDValue EFLAG = N->getOperand(1);
15087 DebugLoc DL = N->getDebugLoc();
15089 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
15090 // a zext and produces an all-ones bit which is more useful than 0/1 in some
15092 if (X86CC == X86::COND_B)
15093 return DAG.getNode(ISD::AND, DL, MVT::i8,
15094 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
15095 DAG.getConstant(X86CC, MVT::i8), EFLAG),
15096 DAG.getConstant(1, MVT::i8));
15101 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) {
15102 SDValue Op0 = N->getOperand(0);
15103 EVT InVT = Op0->getValueType(0);
15105 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
15106 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15107 DebugLoc dl = N->getDebugLoc();
15108 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15109 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
15110 // Notice that we use SINT_TO_FP because we know that the high bits
15111 // are zero and SINT_TO_FP is better supported by the hardware.
15112 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15118 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15119 const X86TargetLowering *XTLI) {
15120 SDValue Op0 = N->getOperand(0);
15121 EVT InVT = Op0->getValueType(0);
15123 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
15124 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15125 DebugLoc dl = N->getDebugLoc();
15126 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15127 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
15128 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15131 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15132 // a 32-bit target where SSE doesn't support i64->FP operations.
15133 if (Op0.getOpcode() == ISD::LOAD) {
15134 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15135 EVT VT = Ld->getValueType(0);
15136 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15137 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15138 !XTLI->getSubtarget()->is64Bit() &&
15139 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15140 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15141 Ld->getChain(), Op0, DAG);
15142 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15149 static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) {
15150 EVT VT = N->getValueType(0);
15152 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
15153 if (VT == MVT::v8i8 || VT == MVT::v4i8) {
15154 DebugLoc dl = N->getDebugLoc();
15155 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15156 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
15157 return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
15163 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15164 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15165 X86TargetLowering::DAGCombinerInfo &DCI) {
15166 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15167 // the result is either zero or one (depending on the input carry bit).
15168 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15169 if (X86::isZeroNode(N->getOperand(0)) &&
15170 X86::isZeroNode(N->getOperand(1)) &&
15171 // We don't have a good way to replace an EFLAGS use, so only do this when
15173 SDValue(N, 1).use_empty()) {
15174 DebugLoc DL = N->getDebugLoc();
15175 EVT VT = N->getValueType(0);
15176 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15177 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15178 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15179 DAG.getConstant(X86::COND_B,MVT::i8),
15181 DAG.getConstant(1, VT));
15182 return DCI.CombineTo(N, Res1, CarryOut);
15188 // fold (add Y, (sete X, 0)) -> adc 0, Y
15189 // (add Y, (setne X, 0)) -> sbb -1, Y
15190 // (sub (sete X, 0), Y) -> sbb 0, Y
15191 // (sub (setne X, 0), Y) -> adc -1, Y
15192 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15193 DebugLoc DL = N->getDebugLoc();
15195 // Look through ZExts.
15196 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15197 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15200 SDValue SetCC = Ext.getOperand(0);
15201 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15204 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15205 if (CC != X86::COND_E && CC != X86::COND_NE)
15208 SDValue Cmp = SetCC.getOperand(1);
15209 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15210 !X86::isZeroNode(Cmp.getOperand(1)) ||
15211 !Cmp.getOperand(0).getValueType().isInteger())
15214 SDValue CmpOp0 = Cmp.getOperand(0);
15215 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15216 DAG.getConstant(1, CmpOp0.getValueType()));
15218 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15219 if (CC == X86::COND_NE)
15220 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15221 DL, OtherVal.getValueType(), OtherVal,
15222 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15223 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15224 DL, OtherVal.getValueType(), OtherVal,
15225 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15228 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15229 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15230 const X86Subtarget *Subtarget) {
15231 EVT VT = N->getValueType(0);
15232 SDValue Op0 = N->getOperand(0);
15233 SDValue Op1 = N->getOperand(1);
15235 // Try to synthesize horizontal adds from adds of shuffles.
15236 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15237 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15238 isHorizontalBinOp(Op0, Op1, true))
15239 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15241 return OptimizeConditionalInDecrement(N, DAG);
15244 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15245 const X86Subtarget *Subtarget) {
15246 SDValue Op0 = N->getOperand(0);
15247 SDValue Op1 = N->getOperand(1);
15249 // X86 can't encode an immediate LHS of a sub. See if we can push the
15250 // negation into a preceding instruction.
15251 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15252 // If the RHS of the sub is a XOR with one use and a constant, invert the
15253 // immediate. Then add one to the LHS of the sub so we can turn
15254 // X-Y -> X+~Y+1, saving one register.
15255 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15256 isa<ConstantSDNode>(Op1.getOperand(1))) {
15257 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15258 EVT VT = Op0.getValueType();
15259 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15261 DAG.getConstant(~XorC, VT));
15262 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15263 DAG.getConstant(C->getAPIntValue()+1, VT));
15267 // Try to synthesize horizontal adds from adds of shuffles.
15268 EVT VT = N->getValueType(0);
15269 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15270 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15271 isHorizontalBinOp(Op0, Op1, true))
15272 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15274 return OptimizeConditionalInDecrement(N, DAG);
15277 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15278 DAGCombinerInfo &DCI) const {
15279 SelectionDAG &DAG = DCI.DAG;
15280 switch (N->getOpcode()) {
15282 case ISD::EXTRACT_VECTOR_ELT:
15283 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15285 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15286 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15287 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15288 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15289 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15290 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15293 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15294 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15295 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15296 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15297 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
15298 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15299 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG);
15300 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15301 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG);
15302 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15303 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15305 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15306 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15307 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15308 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15309 case ISD::ANY_EXTEND:
15310 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
15311 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15312 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15313 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
15314 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15315 case X86ISD::SHUFP: // Handle all target specific shuffles
15316 case X86ISD::PALIGN:
15317 case X86ISD::UNPCKH:
15318 case X86ISD::UNPCKL:
15319 case X86ISD::MOVHLPS:
15320 case X86ISD::MOVLHPS:
15321 case X86ISD::PSHUFD:
15322 case X86ISD::PSHUFHW:
15323 case X86ISD::PSHUFLW:
15324 case X86ISD::MOVSS:
15325 case X86ISD::MOVSD:
15326 case X86ISD::VPERMILP:
15327 case X86ISD::VPERM2X128:
15328 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15334 /// isTypeDesirableForOp - Return true if the target has native support for
15335 /// the specified value type and it is 'desirable' to use the type for the
15336 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15337 /// instruction encodings are longer and some i16 instructions are slow.
15338 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15339 if (!isTypeLegal(VT))
15341 if (VT != MVT::i16)
15348 case ISD::SIGN_EXTEND:
15349 case ISD::ZERO_EXTEND:
15350 case ISD::ANY_EXTEND:
15363 /// IsDesirableToPromoteOp - This method query the target whether it is
15364 /// beneficial for dag combiner to promote the specified node. If true, it
15365 /// should return the desired promotion type by reference.
15366 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15367 EVT VT = Op.getValueType();
15368 if (VT != MVT::i16)
15371 bool Promote = false;
15372 bool Commute = false;
15373 switch (Op.getOpcode()) {
15376 LoadSDNode *LD = cast<LoadSDNode>(Op);
15377 // If the non-extending load has a single use and it's not live out, then it
15378 // might be folded.
15379 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15380 Op.hasOneUse()*/) {
15381 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15382 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15383 // The only case where we'd want to promote LOAD (rather then it being
15384 // promoted as an operand is when it's only use is liveout.
15385 if (UI->getOpcode() != ISD::CopyToReg)
15392 case ISD::SIGN_EXTEND:
15393 case ISD::ZERO_EXTEND:
15394 case ISD::ANY_EXTEND:
15399 SDValue N0 = Op.getOperand(0);
15400 // Look out for (store (shl (load), x)).
15401 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15414 SDValue N0 = Op.getOperand(0);
15415 SDValue N1 = Op.getOperand(1);
15416 if (!Commute && MayFoldLoad(N1))
15418 // Avoid disabling potential load folding opportunities.
15419 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15421 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15431 //===----------------------------------------------------------------------===//
15432 // X86 Inline Assembly Support
15433 //===----------------------------------------------------------------------===//
15436 // Helper to match a string separated by whitespace.
15437 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15438 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15440 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15441 StringRef piece(*args[i]);
15442 if (!s.startswith(piece)) // Check if the piece matches.
15445 s = s.substr(piece.size());
15446 StringRef::size_type pos = s.find_first_not_of(" \t");
15447 if (pos == 0) // We matched a prefix.
15455 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15458 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15459 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15461 std::string AsmStr = IA->getAsmString();
15463 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15464 if (!Ty || Ty->getBitWidth() % 16 != 0)
15467 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15468 SmallVector<StringRef, 4> AsmPieces;
15469 SplitString(AsmStr, AsmPieces, ";\n");
15471 switch (AsmPieces.size()) {
15472 default: return false;
15474 // FIXME: this should verify that we are targeting a 486 or better. If not,
15475 // we will turn this bswap into something that will be lowered to logical
15476 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15477 // lower so don't worry about this.
15479 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15480 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15481 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15482 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15483 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15484 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15485 // No need to check constraints, nothing other than the equivalent of
15486 // "=r,0" would be valid here.
15487 return IntrinsicLowering::LowerToByteSwap(CI);
15490 // rorw $$8, ${0:w} --> llvm.bswap.i16
15491 if (CI->getType()->isIntegerTy(16) &&
15492 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15493 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15494 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15496 const std::string &ConstraintsStr = IA->getConstraintString();
15497 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15498 std::sort(AsmPieces.begin(), AsmPieces.end());
15499 if (AsmPieces.size() == 4 &&
15500 AsmPieces[0] == "~{cc}" &&
15501 AsmPieces[1] == "~{dirflag}" &&
15502 AsmPieces[2] == "~{flags}" &&
15503 AsmPieces[3] == "~{fpsr}")
15504 return IntrinsicLowering::LowerToByteSwap(CI);
15508 if (CI->getType()->isIntegerTy(32) &&
15509 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15510 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15511 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15512 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15514 const std::string &ConstraintsStr = IA->getConstraintString();
15515 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15516 std::sort(AsmPieces.begin(), AsmPieces.end());
15517 if (AsmPieces.size() == 4 &&
15518 AsmPieces[0] == "~{cc}" &&
15519 AsmPieces[1] == "~{dirflag}" &&
15520 AsmPieces[2] == "~{flags}" &&
15521 AsmPieces[3] == "~{fpsr}")
15522 return IntrinsicLowering::LowerToByteSwap(CI);
15525 if (CI->getType()->isIntegerTy(64)) {
15526 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15527 if (Constraints.size() >= 2 &&
15528 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15529 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15530 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15531 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15532 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15533 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15534 return IntrinsicLowering::LowerToByteSwap(CI);
15544 /// getConstraintType - Given a constraint letter, return the type of
15545 /// constraint it is for this target.
15546 X86TargetLowering::ConstraintType
15547 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15548 if (Constraint.size() == 1) {
15549 switch (Constraint[0]) {
15560 return C_RegisterClass;
15584 return TargetLowering::getConstraintType(Constraint);
15587 /// Examine constraint type and operand type and determine a weight value.
15588 /// This object must already have been set up with the operand type
15589 /// and the current alternative constraint selected.
15590 TargetLowering::ConstraintWeight
15591 X86TargetLowering::getSingleConstraintMatchWeight(
15592 AsmOperandInfo &info, const char *constraint) const {
15593 ConstraintWeight weight = CW_Invalid;
15594 Value *CallOperandVal = info.CallOperandVal;
15595 // If we don't have a value, we can't do a match,
15596 // but allow it at the lowest weight.
15597 if (CallOperandVal == NULL)
15599 Type *type = CallOperandVal->getType();
15600 // Look at the constraint type.
15601 switch (*constraint) {
15603 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15614 if (CallOperandVal->getType()->isIntegerTy())
15615 weight = CW_SpecificReg;
15620 if (type->isFloatingPointTy())
15621 weight = CW_SpecificReg;
15624 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15625 weight = CW_SpecificReg;
15629 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15630 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15631 weight = CW_Register;
15634 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15635 if (C->getZExtValue() <= 31)
15636 weight = CW_Constant;
15640 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15641 if (C->getZExtValue() <= 63)
15642 weight = CW_Constant;
15646 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15647 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15648 weight = CW_Constant;
15652 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15653 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15654 weight = CW_Constant;
15658 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15659 if (C->getZExtValue() <= 3)
15660 weight = CW_Constant;
15664 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15665 if (C->getZExtValue() <= 0xff)
15666 weight = CW_Constant;
15671 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15672 weight = CW_Constant;
15676 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15677 if ((C->getSExtValue() >= -0x80000000LL) &&
15678 (C->getSExtValue() <= 0x7fffffffLL))
15679 weight = CW_Constant;
15683 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15684 if (C->getZExtValue() <= 0xffffffff)
15685 weight = CW_Constant;
15692 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15693 /// with another that has more specific requirements based on the type of the
15694 /// corresponding operand.
15695 const char *X86TargetLowering::
15696 LowerXConstraint(EVT ConstraintVT) const {
15697 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15698 // 'f' like normal targets.
15699 if (ConstraintVT.isFloatingPoint()) {
15700 if (Subtarget->hasSSE2())
15702 if (Subtarget->hasSSE1())
15706 return TargetLowering::LowerXConstraint(ConstraintVT);
15709 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15710 /// vector. If it is invalid, don't add anything to Ops.
15711 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15712 std::string &Constraint,
15713 std::vector<SDValue>&Ops,
15714 SelectionDAG &DAG) const {
15715 SDValue Result(0, 0);
15717 // Only support length 1 constraints for now.
15718 if (Constraint.length() > 1) return;
15720 char ConstraintLetter = Constraint[0];
15721 switch (ConstraintLetter) {
15724 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15725 if (C->getZExtValue() <= 31) {
15726 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15732 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15733 if (C->getZExtValue() <= 63) {
15734 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15740 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15741 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15742 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15748 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15749 if (C->getZExtValue() <= 255) {
15750 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15756 // 32-bit signed value
15757 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15758 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15759 C->getSExtValue())) {
15760 // Widen to 64 bits here to get it sign extended.
15761 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15764 // FIXME gcc accepts some relocatable values here too, but only in certain
15765 // memory models; it's complicated.
15770 // 32-bit unsigned value
15771 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15772 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15773 C->getZExtValue())) {
15774 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15778 // FIXME gcc accepts some relocatable values here too, but only in certain
15779 // memory models; it's complicated.
15783 // Literal immediates are always ok.
15784 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15785 // Widen to 64 bits here to get it sign extended.
15786 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15790 // In any sort of PIC mode addresses need to be computed at runtime by
15791 // adding in a register or some sort of table lookup. These can't
15792 // be used as immediates.
15793 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15796 // If we are in non-pic codegen mode, we allow the address of a global (with
15797 // an optional displacement) to be used with 'i'.
15798 GlobalAddressSDNode *GA = 0;
15799 int64_t Offset = 0;
15801 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15803 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15804 Offset += GA->getOffset();
15806 } else if (Op.getOpcode() == ISD::ADD) {
15807 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15808 Offset += C->getZExtValue();
15809 Op = Op.getOperand(0);
15812 } else if (Op.getOpcode() == ISD::SUB) {
15813 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15814 Offset += -C->getZExtValue();
15815 Op = Op.getOperand(0);
15820 // Otherwise, this isn't something we can handle, reject it.
15824 const GlobalValue *GV = GA->getGlobal();
15825 // If we require an extra load to get this address, as in PIC mode, we
15826 // can't accept it.
15827 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15828 getTargetMachine())))
15831 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15832 GA->getValueType(0), Offset);
15837 if (Result.getNode()) {
15838 Ops.push_back(Result);
15841 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15844 std::pair<unsigned, const TargetRegisterClass*>
15845 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15847 // First, see if this is a constraint that directly corresponds to an LLVM
15849 if (Constraint.size() == 1) {
15850 // GCC Constraint Letters
15851 switch (Constraint[0]) {
15853 // TODO: Slight differences here in allocation order and leaving
15854 // RIP in the class. Do they matter any more here than they do
15855 // in the normal allocation?
15856 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15857 if (Subtarget->is64Bit()) {
15858 if (VT == MVT::i32 || VT == MVT::f32)
15859 return std::make_pair(0U, &X86::GR32RegClass);
15860 if (VT == MVT::i16)
15861 return std::make_pair(0U, &X86::GR16RegClass);
15862 if (VT == MVT::i8 || VT == MVT::i1)
15863 return std::make_pair(0U, &X86::GR8RegClass);
15864 if (VT == MVT::i64 || VT == MVT::f64)
15865 return std::make_pair(0U, &X86::GR64RegClass);
15868 // 32-bit fallthrough
15869 case 'Q': // Q_REGS
15870 if (VT == MVT::i32 || VT == MVT::f32)
15871 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
15872 if (VT == MVT::i16)
15873 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
15874 if (VT == MVT::i8 || VT == MVT::i1)
15875 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
15876 if (VT == MVT::i64)
15877 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
15879 case 'r': // GENERAL_REGS
15880 case 'l': // INDEX_REGS
15881 if (VT == MVT::i8 || VT == MVT::i1)
15882 return std::make_pair(0U, &X86::GR8RegClass);
15883 if (VT == MVT::i16)
15884 return std::make_pair(0U, &X86::GR16RegClass);
15885 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15886 return std::make_pair(0U, &X86::GR32RegClass);
15887 return std::make_pair(0U, &X86::GR64RegClass);
15888 case 'R': // LEGACY_REGS
15889 if (VT == MVT::i8 || VT == MVT::i1)
15890 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
15891 if (VT == MVT::i16)
15892 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
15893 if (VT == MVT::i32 || !Subtarget->is64Bit())
15894 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
15895 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
15896 case 'f': // FP Stack registers.
15897 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15898 // value to the correct fpstack register class.
15899 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15900 return std::make_pair(0U, &X86::RFP32RegClass);
15901 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15902 return std::make_pair(0U, &X86::RFP64RegClass);
15903 return std::make_pair(0U, &X86::RFP80RegClass);
15904 case 'y': // MMX_REGS if MMX allowed.
15905 if (!Subtarget->hasMMX()) break;
15906 return std::make_pair(0U, &X86::VR64RegClass);
15907 case 'Y': // SSE_REGS if SSE2 allowed
15908 if (!Subtarget->hasSSE2()) break;
15910 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15911 if (!Subtarget->hasSSE1()) break;
15913 switch (VT.getSimpleVT().SimpleTy) {
15915 // Scalar SSE types.
15918 return std::make_pair(0U, &X86::FR32RegClass);
15921 return std::make_pair(0U, &X86::FR64RegClass);
15929 return std::make_pair(0U, &X86::VR128RegClass);
15937 return std::make_pair(0U, &X86::VR256RegClass);
15943 // Use the default implementation in TargetLowering to convert the register
15944 // constraint into a member of a register class.
15945 std::pair<unsigned, const TargetRegisterClass*> Res;
15946 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15948 // Not found as a standard register?
15949 if (Res.second == 0) {
15950 // Map st(0) -> st(7) -> ST0
15951 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15952 tolower(Constraint[1]) == 's' &&
15953 tolower(Constraint[2]) == 't' &&
15954 Constraint[3] == '(' &&
15955 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15956 Constraint[5] == ')' &&
15957 Constraint[6] == '}') {
15959 Res.first = X86::ST0+Constraint[4]-'0';
15960 Res.second = &X86::RFP80RegClass;
15964 // GCC allows "st(0)" to be called just plain "st".
15965 if (StringRef("{st}").equals_lower(Constraint)) {
15966 Res.first = X86::ST0;
15967 Res.second = &X86::RFP80RegClass;
15972 if (StringRef("{flags}").equals_lower(Constraint)) {
15973 Res.first = X86::EFLAGS;
15974 Res.second = &X86::CCRRegClass;
15978 // 'A' means EAX + EDX.
15979 if (Constraint == "A") {
15980 Res.first = X86::EAX;
15981 Res.second = &X86::GR32_ADRegClass;
15987 // Otherwise, check to see if this is a register class of the wrong value
15988 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15989 // turn into {ax},{dx}.
15990 if (Res.second->hasType(VT))
15991 return Res; // Correct type already, nothing to do.
15993 // All of the single-register GCC register classes map their values onto
15994 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15995 // really want an 8-bit or 32-bit register, map to the appropriate register
15996 // class and return the appropriate register.
15997 if (Res.second == &X86::GR16RegClass) {
15998 if (VT == MVT::i8) {
15999 unsigned DestReg = 0;
16000 switch (Res.first) {
16002 case X86::AX: DestReg = X86::AL; break;
16003 case X86::DX: DestReg = X86::DL; break;
16004 case X86::CX: DestReg = X86::CL; break;
16005 case X86::BX: DestReg = X86::BL; break;
16008 Res.first = DestReg;
16009 Res.second = &X86::GR8RegClass;
16011 } else if (VT == MVT::i32) {
16012 unsigned DestReg = 0;
16013 switch (Res.first) {
16015 case X86::AX: DestReg = X86::EAX; break;
16016 case X86::DX: DestReg = X86::EDX; break;
16017 case X86::CX: DestReg = X86::ECX; break;
16018 case X86::BX: DestReg = X86::EBX; break;
16019 case X86::SI: DestReg = X86::ESI; break;
16020 case X86::DI: DestReg = X86::EDI; break;
16021 case X86::BP: DestReg = X86::EBP; break;
16022 case X86::SP: DestReg = X86::ESP; break;
16025 Res.first = DestReg;
16026 Res.second = &X86::GR32RegClass;
16028 } else if (VT == MVT::i64) {
16029 unsigned DestReg = 0;
16030 switch (Res.first) {
16032 case X86::AX: DestReg = X86::RAX; break;
16033 case X86::DX: DestReg = X86::RDX; break;
16034 case X86::CX: DestReg = X86::RCX; break;
16035 case X86::BX: DestReg = X86::RBX; break;
16036 case X86::SI: DestReg = X86::RSI; break;
16037 case X86::DI: DestReg = X86::RDI; break;
16038 case X86::BP: DestReg = X86::RBP; break;
16039 case X86::SP: DestReg = X86::RSP; break;
16042 Res.first = DestReg;
16043 Res.second = &X86::GR64RegClass;
16046 } else if (Res.second == &X86::FR32RegClass ||
16047 Res.second == &X86::FR64RegClass ||
16048 Res.second == &X86::VR128RegClass) {
16049 // Handle references to XMM physical registers that got mapped into the
16050 // wrong class. This can happen with constraints like {xmm0} where the
16051 // target independent register mapper will just pick the first match it can
16052 // find, ignoring the required type.
16053 if (VT == MVT::f32)
16054 Res.second = &X86::FR32RegClass;
16055 else if (VT == MVT::f64)
16056 Res.second = &X86::FR64RegClass;
16057 else if (X86::VR128RegClass.hasType(VT))
16058 Res.second = &X86::VR128RegClass;