1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VariadicFunction.h"
47 #include "llvm/Support/CallSite.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetOptions.h"
56 using namespace dwarf;
58 STATISTIC(NumTailCalls, "Number of tail calls");
60 static cl::opt<bool> UseRegMask("x86-use-regmask",
61 cl::desc("Use register masks for x86 calls"));
63 // Forward declarations.
64 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
67 static SDValue Insert128BitVector(SDValue Result,
73 static SDValue Extract128BitVector(SDValue Vec,
78 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
79 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
80 /// simple subregister reference. Idx is an index in the 128 bits we
81 /// want. It need not be aligned to a 128-bit bounday. That makes
82 /// lowering EXTRACT_VECTOR_ELT operations easier.
83 static SDValue Extract128BitVector(SDValue Vec,
87 EVT VT = Vec.getValueType();
88 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
89 EVT ElVT = VT.getVectorElementType();
90 int Factor = VT.getSizeInBits()/128;
91 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
92 VT.getVectorNumElements()/Factor);
94 // Extract from UNDEF is UNDEF.
95 if (Vec.getOpcode() == ISD::UNDEF)
96 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
98 if (isa<ConstantSDNode>(Idx)) {
99 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
101 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
102 // we can match to VEXTRACTF128.
103 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
105 // This is the index of the first element of the 128-bit chunk
107 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
110 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
111 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
121 /// sets things up to match to an AVX VINSERTF128 instruction or a
122 /// simple superregister reference. Idx is an index in the 128 bits
123 /// we want. It need not be aligned to a 128-bit bounday. That makes
124 /// lowering INSERT_VECTOR_ELT operations easier.
125 static SDValue Insert128BitVector(SDValue Result,
130 if (isa<ConstantSDNode>(Idx)) {
131 EVT VT = Vec.getValueType();
132 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
134 EVT ElVT = VT.getVectorElementType();
135 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
136 EVT ResultVT = Result.getValueType();
138 // Insert the relevant 128 bits.
139 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
141 // This is the index of the first element of the 128-bit chunk
143 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
146 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
147 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
155 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
156 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
157 bool is64Bit = Subtarget->is64Bit();
159 if (Subtarget->isTargetEnvMacho()) {
161 return new X8664_MachoTargetObjectFile();
162 return new TargetLoweringObjectFileMachO();
165 if (Subtarget->isTargetELF())
166 return new TargetLoweringObjectFileELF();
167 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
168 return new TargetLoweringObjectFileCOFF();
169 llvm_unreachable("unknown subtarget type");
172 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
173 : TargetLowering(TM, createTLOF(TM)) {
174 Subtarget = &TM.getSubtarget<X86Subtarget>();
175 X86ScalarSSEf64 = Subtarget->hasSSE2();
176 X86ScalarSSEf32 = Subtarget->hasSSE1();
177 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
179 RegInfo = TM.getRegisterInfo();
180 TD = getTargetData();
182 // Set up the TargetLowering object.
183 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
185 // X86 is weird, it always uses i8 for shift amounts and setcc results.
186 setBooleanContents(ZeroOrOneBooleanContent);
187 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
188 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
190 // For 64-bit since we have so many registers use the ILP scheduler, for
191 // 32-bit code use the register pressure specific scheduling.
192 if (Subtarget->is64Bit())
193 setSchedulingPreference(Sched::ILP);
195 setSchedulingPreference(Sched::RegPressure);
196 setStackPointerRegisterToSaveRestore(X86StackPtr);
198 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
199 // Setup Windows compiler runtime calls.
200 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
201 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
202 setLibcallName(RTLIB::SREM_I64, "_allrem");
203 setLibcallName(RTLIB::UREM_I64, "_aullrem");
204 setLibcallName(RTLIB::MUL_I64, "_allmul");
205 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
206 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
207 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
208 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
209 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
210 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
211 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
212 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
213 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
216 if (Subtarget->isTargetDarwin()) {
217 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
218 setUseUnderscoreSetJmp(false);
219 setUseUnderscoreLongJmp(false);
220 } else if (Subtarget->isTargetMingw()) {
221 // MS runtime is weird: it exports _setjmp, but longjmp!
222 setUseUnderscoreSetJmp(true);
223 setUseUnderscoreLongJmp(false);
225 setUseUnderscoreSetJmp(true);
226 setUseUnderscoreLongJmp(true);
229 // Set up the register classes.
230 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
231 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
232 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
233 if (Subtarget->is64Bit())
234 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
236 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
238 // We don't accept any truncstore of integer registers.
239 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
240 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
241 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
242 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
243 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
244 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
246 // SETOEQ and SETUNE require checking two conditions.
247 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
248 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
249 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
250 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
251 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
252 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
254 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
256 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
257 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
258 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
260 if (Subtarget->is64Bit()) {
261 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
262 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
263 } else if (!TM.Options.UseSoftFloat) {
264 // We have an algorithm for SSE2->double, and we turn this into a
265 // 64-bit FILD followed by conditional FADD for other targets.
266 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
267 // We have an algorithm for SSE2, and we turn this into a 64-bit
268 // FILD for other targets.
269 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
272 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
274 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
275 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
277 if (!TM.Options.UseSoftFloat) {
278 // SSE has no i16 to fp conversion, only i32
279 if (X86ScalarSSEf32) {
280 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
281 // f32 and f64 cases are Legal, f80 case is not
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
284 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
288 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
289 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
292 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
293 // are Legal, f80 is custom lowered.
294 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
295 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
297 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
299 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
300 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
302 if (X86ScalarSSEf32) {
303 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
304 // f32 and f64 cases are Legal, f80 case is not
305 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
307 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
308 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
311 // Handle FP_TO_UINT by promoting the destination to a larger signed
313 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
314 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
315 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
320 } else if (!TM.Options.UseSoftFloat) {
321 // Since AVX is a superset of SSE3, only check for SSE here.
322 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
323 // Expand FP_TO_UINT into a select.
324 // FIXME: We would like to use a Custom expander here eventually to do
325 // the optimal thing for SSE vs. the default expansion in the legalizer.
326 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
328 // With SSE3 we can use fisttpll to convert to a signed i64; without
329 // SSE, we're stuck with a fistpll.
330 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
333 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
334 if (!X86ScalarSSEf64) {
335 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
336 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
339 // Without SSE, i64->f64 goes through memory.
340 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
344 // Scalar integer divide and remainder are lowered to use operations that
345 // produce two results, to match the available instructions. This exposes
346 // the two-result form to trivial CSE, which is able to combine x/y and x%y
347 // into a single instruction.
349 // Scalar integer multiply-high is also lowered to use two-result
350 // operations, to match the available instructions. However, plain multiply
351 // (low) operations are left as Legal, as there are single-result
352 // instructions for this in x86. Using the two-result multiply instructions
353 // when both high and low results are needed must be arranged by dagcombine.
354 for (unsigned i = 0, e = 4; i != e; ++i) {
356 setOperationAction(ISD::MULHS, VT, Expand);
357 setOperationAction(ISD::MULHU, VT, Expand);
358 setOperationAction(ISD::SDIV, VT, Expand);
359 setOperationAction(ISD::UDIV, VT, Expand);
360 setOperationAction(ISD::SREM, VT, Expand);
361 setOperationAction(ISD::UREM, VT, Expand);
363 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
364 setOperationAction(ISD::ADDC, VT, Custom);
365 setOperationAction(ISD::ADDE, VT, Custom);
366 setOperationAction(ISD::SUBC, VT, Custom);
367 setOperationAction(ISD::SUBE, VT, Custom);
370 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
371 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
372 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
373 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
374 if (Subtarget->is64Bit())
375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
376 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
377 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
378 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
379 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
380 setOperationAction(ISD::FREM , MVT::f32 , Expand);
381 setOperationAction(ISD::FREM , MVT::f64 , Expand);
382 setOperationAction(ISD::FREM , MVT::f80 , Expand);
383 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
385 // Promote the i8 variants and force them on up to i32 which has a shorter
387 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
388 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
389 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
390 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
391 if (Subtarget->hasBMI()) {
392 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
393 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
394 if (Subtarget->is64Bit())
395 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
397 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
398 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
399 if (Subtarget->is64Bit())
400 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
403 if (Subtarget->hasLZCNT()) {
404 // When promoting the i8 variants, force them to i32 for a shorter
406 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
407 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
409 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
411 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
412 if (Subtarget->is64Bit())
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
415 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
416 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
417 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
420 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
421 if (Subtarget->is64Bit()) {
422 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
423 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
427 if (Subtarget->hasPOPCNT()) {
428 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
430 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
431 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
432 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
433 if (Subtarget->is64Bit())
434 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
437 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
438 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
440 // These should be promoted to a larger select which is supported.
441 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
442 // X86 wants to expand cmov itself.
443 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
444 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
445 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
446 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
447 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
448 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
449 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
450 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
451 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
452 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
453 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
454 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
455 if (Subtarget->is64Bit()) {
456 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
457 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
459 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
462 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
463 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
464 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
465 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
466 if (Subtarget->is64Bit())
467 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
468 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
469 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
470 if (Subtarget->is64Bit()) {
471 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
472 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
473 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
474 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
475 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
477 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
478 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
479 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
480 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
481 if (Subtarget->is64Bit()) {
482 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
483 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
484 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
487 if (Subtarget->hasSSE1())
488 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
490 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
491 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
493 // On X86 and X86-64, atomic operations are lowered to locked instructions.
494 // Locked instructions, in turn, have implicit fence semantics (all memory
495 // operations are flushed before issuing the locked instruction, and they
496 // are not buffered), so we can fold away the common pattern of
497 // fence-atomic-fence.
498 setShouldFoldAtomicFences(true);
500 // Expand certain atomics
501 for (unsigned i = 0, e = 4; i != e; ++i) {
503 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
505 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
508 if (!Subtarget->is64Bit()) {
509 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
512 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
513 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
514 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
515 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
516 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
519 if (Subtarget->hasCmpxchg16b()) {
520 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
523 // FIXME - use subtarget debug flags
524 if (!Subtarget->isTargetDarwin() &&
525 !Subtarget->isTargetELF() &&
526 !Subtarget->isTargetCygMing()) {
527 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
530 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
531 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
532 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
533 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
534 if (Subtarget->is64Bit()) {
535 setExceptionPointerRegister(X86::RAX);
536 setExceptionSelectorRegister(X86::RDX);
538 setExceptionPointerRegister(X86::EAX);
539 setExceptionSelectorRegister(X86::EDX);
541 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
542 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
544 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
545 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
547 setOperationAction(ISD::TRAP, MVT::Other, Legal);
549 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
550 setOperationAction(ISD::VASTART , MVT::Other, Custom);
551 setOperationAction(ISD::VAEND , MVT::Other, Expand);
552 if (Subtarget->is64Bit()) {
553 setOperationAction(ISD::VAARG , MVT::Other, Custom);
554 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
556 setOperationAction(ISD::VAARG , MVT::Other, Expand);
557 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
560 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
561 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
563 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
564 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
565 MVT::i64 : MVT::i32, Custom);
566 else if (TM.Options.EnableSegmentedStacks)
567 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
568 MVT::i64 : MVT::i32, Custom);
570 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
571 MVT::i64 : MVT::i32, Expand);
573 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
574 // f32 and f64 use SSE.
575 // Set up the FP register classes.
576 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
577 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
579 // Use ANDPD to simulate FABS.
580 setOperationAction(ISD::FABS , MVT::f64, Custom);
581 setOperationAction(ISD::FABS , MVT::f32, Custom);
583 // Use XORP to simulate FNEG.
584 setOperationAction(ISD::FNEG , MVT::f64, Custom);
585 setOperationAction(ISD::FNEG , MVT::f32, Custom);
587 // Use ANDPD and ORPD to simulate FCOPYSIGN.
588 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
589 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
591 // Lower this to FGETSIGNx86 plus an AND.
592 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
593 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
595 // We don't support sin/cos/fmod
596 setOperationAction(ISD::FSIN , MVT::f64, Expand);
597 setOperationAction(ISD::FCOS , MVT::f64, Expand);
598 setOperationAction(ISD::FSIN , MVT::f32, Expand);
599 setOperationAction(ISD::FCOS , MVT::f32, Expand);
601 // Expand FP immediates into loads from the stack, except for the special
603 addLegalFPImmediate(APFloat(+0.0)); // xorpd
604 addLegalFPImmediate(APFloat(+0.0f)); // xorps
605 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
606 // Use SSE for f32, x87 for f64.
607 // Set up the FP register classes.
608 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
609 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
611 // Use ANDPS to simulate FABS.
612 setOperationAction(ISD::FABS , MVT::f32, Custom);
614 // Use XORP to simulate FNEG.
615 setOperationAction(ISD::FNEG , MVT::f32, Custom);
617 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
619 // Use ANDPS and ORPS to simulate FCOPYSIGN.
620 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
621 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
623 // We don't support sin/cos/fmod
624 setOperationAction(ISD::FSIN , MVT::f32, Expand);
625 setOperationAction(ISD::FCOS , MVT::f32, Expand);
627 // Special cases we handle for FP constants.
628 addLegalFPImmediate(APFloat(+0.0f)); // xorps
629 addLegalFPImmediate(APFloat(+0.0)); // FLD0
630 addLegalFPImmediate(APFloat(+1.0)); // FLD1
631 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
632 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
634 if (!TM.Options.UnsafeFPMath) {
635 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
636 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
638 } else if (!TM.Options.UseSoftFloat) {
639 // f32 and f64 in x87.
640 // Set up the FP register classes.
641 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
642 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
644 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
645 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
646 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
647 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
649 if (!TM.Options.UnsafeFPMath) {
650 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
651 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
653 addLegalFPImmediate(APFloat(+0.0)); // FLD0
654 addLegalFPImmediate(APFloat(+1.0)); // FLD1
655 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
656 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
657 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
658 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
659 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
660 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
663 // We don't support FMA.
664 setOperationAction(ISD::FMA, MVT::f64, Expand);
665 setOperationAction(ISD::FMA, MVT::f32, Expand);
667 // Long double always uses X87.
668 if (!TM.Options.UseSoftFloat) {
669 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
670 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
671 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
673 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
674 addLegalFPImmediate(TmpFlt); // FLD0
676 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
679 APFloat TmpFlt2(+1.0);
680 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
682 addLegalFPImmediate(TmpFlt2); // FLD1
683 TmpFlt2.changeSign();
684 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
687 if (!TM.Options.UnsafeFPMath) {
688 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
689 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
692 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
693 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
694 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
695 setOperationAction(ISD::FRINT, MVT::f80, Expand);
696 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
697 setOperationAction(ISD::FMA, MVT::f80, Expand);
700 // Always use a library call for pow.
701 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
702 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
703 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
705 setOperationAction(ISD::FLOG, MVT::f80, Expand);
706 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
707 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
708 setOperationAction(ISD::FEXP, MVT::f80, Expand);
709 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
711 // First set operation action for all vector types to either promote
712 // (for widening) or expand (for scalarization). Then we will selectively
713 // turn on ones that can be effectively codegen'd.
714 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
715 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
716 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
731 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
733 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
734 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
768 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
769 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
770 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
771 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
772 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
773 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
774 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
775 setTruncStoreAction((MVT::SimpleValueType)VT,
776 (MVT::SimpleValueType)InnerVT, Expand);
777 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
778 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
779 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
782 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
783 // with -msoft-float, disable use of MMX as well.
784 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
785 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
786 // No operations on x86mmx supported, everything uses intrinsics.
789 // MMX-sized vectors (other than x86mmx) are expected to be expanded
790 // into smaller operations.
791 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
792 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
793 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
794 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
795 setOperationAction(ISD::AND, MVT::v8i8, Expand);
796 setOperationAction(ISD::AND, MVT::v4i16, Expand);
797 setOperationAction(ISD::AND, MVT::v2i32, Expand);
798 setOperationAction(ISD::AND, MVT::v1i64, Expand);
799 setOperationAction(ISD::OR, MVT::v8i8, Expand);
800 setOperationAction(ISD::OR, MVT::v4i16, Expand);
801 setOperationAction(ISD::OR, MVT::v2i32, Expand);
802 setOperationAction(ISD::OR, MVT::v1i64, Expand);
803 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
804 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
805 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
806 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
807 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
808 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
809 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
810 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
811 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
812 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
813 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
814 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
815 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
816 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
817 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
818 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
819 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
821 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
822 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
824 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
825 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
826 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
827 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
828 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
829 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
830 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
831 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
832 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
833 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
834 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
835 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
838 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
839 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
841 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
842 // registers cannot be used even for integer operations.
843 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
844 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
845 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
846 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
848 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
849 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
850 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
851 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
852 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
853 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
854 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
855 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
856 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
857 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
858 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
859 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
860 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
861 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
862 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
863 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
865 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
866 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
867 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
868 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
870 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
871 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
872 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
873 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
874 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
876 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
877 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
878 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
879 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
880 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
882 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
883 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
884 EVT VT = (MVT::SimpleValueType)i;
885 // Do not attempt to custom lower non-power-of-2 vectors
886 if (!isPowerOf2_32(VT.getVectorNumElements()))
888 // Do not attempt to custom lower non-128-bit vectors
889 if (!VT.is128BitVector())
891 setOperationAction(ISD::BUILD_VECTOR,
892 VT.getSimpleVT().SimpleTy, Custom);
893 setOperationAction(ISD::VECTOR_SHUFFLE,
894 VT.getSimpleVT().SimpleTy, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
896 VT.getSimpleVT().SimpleTy, Custom);
899 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
900 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
901 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
902 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
903 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
904 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
906 if (Subtarget->is64Bit()) {
907 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
908 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
911 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
912 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
913 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
916 // Do not attempt to promote non-128-bit vectors
917 if (!VT.is128BitVector())
920 setOperationAction(ISD::AND, SVT, Promote);
921 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
922 setOperationAction(ISD::OR, SVT, Promote);
923 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
924 setOperationAction(ISD::XOR, SVT, Promote);
925 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
926 setOperationAction(ISD::LOAD, SVT, Promote);
927 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
928 setOperationAction(ISD::SELECT, SVT, Promote);
929 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
932 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
934 // Custom lower v2i64 and v2f64 selects.
935 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
936 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
937 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
938 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
940 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
941 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
944 if (Subtarget->hasSSE41()) {
945 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
946 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
947 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
948 setOperationAction(ISD::FRINT, MVT::f32, Legal);
949 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
950 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
951 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
952 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
953 setOperationAction(ISD::FRINT, MVT::f64, Legal);
954 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
956 // FIXME: Do we need to handle scalar-to-vector here?
957 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
959 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
960 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
961 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
962 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
963 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
965 // i8 and i16 vectors are custom , because the source register and source
966 // source memory operand types are not the same width. f32 vectors are
967 // custom since the immediate controlling the insert encodes additional
969 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
970 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
971 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
972 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
974 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
975 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
976 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
977 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
979 // FIXME: these should be Legal but thats only for the case where
980 // the index is constant. For now custom expand to deal with that.
981 if (Subtarget->is64Bit()) {
982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
983 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
987 if (Subtarget->hasSSE2()) {
988 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
989 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
991 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
992 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
994 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
995 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
997 if (Subtarget->hasAVX2()) {
998 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
999 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
1001 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1002 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
1004 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1006 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1007 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1009 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1010 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1012 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1016 if (Subtarget->hasSSE42())
1017 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1019 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1020 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1021 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1022 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1023 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1024 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1025 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1027 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1028 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1029 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1031 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1032 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1033 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1034 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1035 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1036 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1038 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1039 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1040 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1041 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1042 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1043 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1045 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1046 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1047 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1049 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1050 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1051 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1052 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1053 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1054 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1056 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1059 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1060 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1062 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1063 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1065 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1066 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1067 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1068 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1070 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1071 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1072 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1074 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1075 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1076 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1077 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1079 if (Subtarget->hasAVX2()) {
1080 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1081 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1082 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1083 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1085 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1086 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1087 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1088 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1090 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1091 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1092 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1093 // Don't lower v32i8 because there is no 128-bit byte mul
1095 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1097 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1098 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1100 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1101 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1103 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1105 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1106 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1107 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1108 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1110 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1111 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1112 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1113 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1115 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1116 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1117 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1118 // Don't lower v32i8 because there is no 128-bit byte mul
1120 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1123 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1124 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1126 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1129 // Custom lower several nodes for 256-bit types.
1130 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1131 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1132 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1135 // Extract subvector is special because the value type
1136 // (result) is 128-bit but the source is 256-bit wide.
1137 if (VT.is128BitVector())
1138 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1140 // Do not attempt to custom lower other non-256-bit vectors
1141 if (!VT.is256BitVector())
1144 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1145 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1146 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1147 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1148 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1149 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1152 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1153 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1154 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1157 // Do not attempt to promote non-256-bit vectors
1158 if (!VT.is256BitVector())
1161 setOperationAction(ISD::AND, SVT, Promote);
1162 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1163 setOperationAction(ISD::OR, SVT, Promote);
1164 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1165 setOperationAction(ISD::XOR, SVT, Promote);
1166 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1167 setOperationAction(ISD::LOAD, SVT, Promote);
1168 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1169 setOperationAction(ISD::SELECT, SVT, Promote);
1170 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1174 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1175 // of this type with custom code.
1176 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1177 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1178 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1182 // We want to custom lower some of our intrinsics.
1183 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1186 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1187 // handle type legalization for these operations here.
1189 // FIXME: We really should do custom legalization for addition and
1190 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1191 // than generic legalization for 64-bit multiplication-with-overflow, though.
1192 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1193 // Add/Sub/Mul with overflow operations are custom lowered.
1195 setOperationAction(ISD::SADDO, VT, Custom);
1196 setOperationAction(ISD::UADDO, VT, Custom);
1197 setOperationAction(ISD::SSUBO, VT, Custom);
1198 setOperationAction(ISD::USUBO, VT, Custom);
1199 setOperationAction(ISD::SMULO, VT, Custom);
1200 setOperationAction(ISD::UMULO, VT, Custom);
1203 // There are no 8-bit 3-address imul/mul instructions
1204 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1205 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1207 if (!Subtarget->is64Bit()) {
1208 // These libcalls are not available in 32-bit.
1209 setLibcallName(RTLIB::SHL_I128, 0);
1210 setLibcallName(RTLIB::SRL_I128, 0);
1211 setLibcallName(RTLIB::SRA_I128, 0);
1214 // We have target-specific dag combine patterns for the following nodes:
1215 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1216 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1217 setTargetDAGCombine(ISD::VSELECT);
1218 setTargetDAGCombine(ISD::SELECT);
1219 setTargetDAGCombine(ISD::SHL);
1220 setTargetDAGCombine(ISD::SRA);
1221 setTargetDAGCombine(ISD::SRL);
1222 setTargetDAGCombine(ISD::OR);
1223 setTargetDAGCombine(ISD::AND);
1224 setTargetDAGCombine(ISD::ADD);
1225 setTargetDAGCombine(ISD::FADD);
1226 setTargetDAGCombine(ISD::FSUB);
1227 setTargetDAGCombine(ISD::SUB);
1228 setTargetDAGCombine(ISD::LOAD);
1229 setTargetDAGCombine(ISD::STORE);
1230 setTargetDAGCombine(ISD::ZERO_EXTEND);
1231 setTargetDAGCombine(ISD::SINT_TO_FP);
1232 if (Subtarget->is64Bit())
1233 setTargetDAGCombine(ISD::MUL);
1234 if (Subtarget->hasBMI())
1235 setTargetDAGCombine(ISD::XOR);
1237 computeRegisterProperties();
1239 // On Darwin, -Os means optimize for size without hurting performance,
1240 // do not reduce the limit.
1241 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1242 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1243 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1244 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1245 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1246 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1247 setPrefLoopAlignment(4); // 2^4 bytes.
1248 benefitFromCodePlacementOpt = true;
1250 setPrefFunctionAlignment(4); // 2^4 bytes.
1254 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1255 if (!VT.isVector()) return MVT::i8;
1256 return VT.changeVectorElementTypeToInteger();
1260 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1261 /// the desired ByVal argument alignment.
1262 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1265 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1266 if (VTy->getBitWidth() == 128)
1268 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1269 unsigned EltAlign = 0;
1270 getMaxByValAlign(ATy->getElementType(), EltAlign);
1271 if (EltAlign > MaxAlign)
1272 MaxAlign = EltAlign;
1273 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1274 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1275 unsigned EltAlign = 0;
1276 getMaxByValAlign(STy->getElementType(i), EltAlign);
1277 if (EltAlign > MaxAlign)
1278 MaxAlign = EltAlign;
1286 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1287 /// function arguments in the caller parameter area. For X86, aggregates
1288 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1289 /// are at 4-byte boundaries.
1290 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1291 if (Subtarget->is64Bit()) {
1292 // Max of 8 and alignment of type.
1293 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1300 if (Subtarget->hasSSE1())
1301 getMaxByValAlign(Ty, Align);
1305 /// getOptimalMemOpType - Returns the target specific optimal type for load
1306 /// and store operations as a result of memset, memcpy, and memmove
1307 /// lowering. If DstAlign is zero that means it's safe to destination
1308 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1309 /// means there isn't a need to check it against alignment requirement,
1310 /// probably because the source does not need to be loaded. If
1311 /// 'IsZeroVal' is true, that means it's safe to return a
1312 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1313 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1314 /// constant so it does not need to be loaded.
1315 /// It returns EVT::Other if the type should be determined using generic
1316 /// target-independent logic.
1318 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1319 unsigned DstAlign, unsigned SrcAlign,
1322 MachineFunction &MF) const {
1323 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1324 // linux. This is because the stack realignment code can't handle certain
1325 // cases like PR2962. This should be removed when PR2962 is fixed.
1326 const Function *F = MF.getFunction();
1328 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1330 (Subtarget->isUnalignedMemAccessFast() ||
1331 ((DstAlign == 0 || DstAlign >= 16) &&
1332 (SrcAlign == 0 || SrcAlign >= 16))) &&
1333 Subtarget->getStackAlignment() >= 16) {
1334 if (Subtarget->getStackAlignment() >= 32) {
1335 if (Subtarget->hasAVX2())
1337 if (Subtarget->hasAVX())
1340 if (Subtarget->hasSSE2())
1342 if (Subtarget->hasSSE1())
1344 } else if (!MemcpyStrSrc && Size >= 8 &&
1345 !Subtarget->is64Bit() &&
1346 Subtarget->getStackAlignment() >= 8 &&
1347 Subtarget->hasSSE2()) {
1348 // Do not use f64 to lower memcpy if source is string constant. It's
1349 // better to use i32 to avoid the loads.
1353 if (Subtarget->is64Bit() && Size >= 8)
1358 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1359 /// current function. The returned value is a member of the
1360 /// MachineJumpTableInfo::JTEntryKind enum.
1361 unsigned X86TargetLowering::getJumpTableEncoding() const {
1362 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1364 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1365 Subtarget->isPICStyleGOT())
1366 return MachineJumpTableInfo::EK_Custom32;
1368 // Otherwise, use the normal jump table encoding heuristics.
1369 return TargetLowering::getJumpTableEncoding();
1373 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1374 const MachineBasicBlock *MBB,
1375 unsigned uid,MCContext &Ctx) const{
1376 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1377 Subtarget->isPICStyleGOT());
1378 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1380 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1381 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1384 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1386 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1387 SelectionDAG &DAG) const {
1388 if (!Subtarget->is64Bit())
1389 // This doesn't have DebugLoc associated with it, but is not really the
1390 // same as a Register.
1391 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1395 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1396 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1398 const MCExpr *X86TargetLowering::
1399 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1400 MCContext &Ctx) const {
1401 // X86-64 uses RIP relative addressing based on the jump table label.
1402 if (Subtarget->isPICStyleRIPRel())
1403 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1405 // Otherwise, the reference is relative to the PIC base.
1406 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1409 // FIXME: Why this routine is here? Move to RegInfo!
1410 std::pair<const TargetRegisterClass*, uint8_t>
1411 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1412 const TargetRegisterClass *RRC = 0;
1414 switch (VT.getSimpleVT().SimpleTy) {
1416 return TargetLowering::findRepresentativeClass(VT);
1417 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1418 RRC = (Subtarget->is64Bit()
1419 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1422 RRC = X86::VR64RegisterClass;
1424 case MVT::f32: case MVT::f64:
1425 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1426 case MVT::v4f32: case MVT::v2f64:
1427 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1429 RRC = X86::VR128RegisterClass;
1432 return std::make_pair(RRC, Cost);
1435 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1436 unsigned &Offset) const {
1437 if (!Subtarget->isTargetLinux())
1440 if (Subtarget->is64Bit()) {
1441 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1443 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1456 //===----------------------------------------------------------------------===//
1457 // Return Value Calling Convention Implementation
1458 //===----------------------------------------------------------------------===//
1460 #include "X86GenCallingConv.inc"
1463 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1464 MachineFunction &MF, bool isVarArg,
1465 const SmallVectorImpl<ISD::OutputArg> &Outs,
1466 LLVMContext &Context) const {
1467 SmallVector<CCValAssign, 16> RVLocs;
1468 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1470 return CCInfo.CheckReturn(Outs, RetCC_X86);
1474 X86TargetLowering::LowerReturn(SDValue Chain,
1475 CallingConv::ID CallConv, bool isVarArg,
1476 const SmallVectorImpl<ISD::OutputArg> &Outs,
1477 const SmallVectorImpl<SDValue> &OutVals,
1478 DebugLoc dl, SelectionDAG &DAG) const {
1479 MachineFunction &MF = DAG.getMachineFunction();
1480 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1482 SmallVector<CCValAssign, 16> RVLocs;
1483 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1484 RVLocs, *DAG.getContext());
1485 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1487 // Add the regs to the liveout set for the function.
1488 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1489 for (unsigned i = 0; i != RVLocs.size(); ++i)
1490 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1491 MRI.addLiveOut(RVLocs[i].getLocReg());
1495 SmallVector<SDValue, 6> RetOps;
1496 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1497 // Operand #1 = Bytes To Pop
1498 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1501 // Copy the result values into the output registers.
1502 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1503 CCValAssign &VA = RVLocs[i];
1504 assert(VA.isRegLoc() && "Can only return in registers!");
1505 SDValue ValToCopy = OutVals[i];
1506 EVT ValVT = ValToCopy.getValueType();
1508 // If this is x86-64, and we disabled SSE, we can't return FP values,
1509 // or SSE or MMX vectors.
1510 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1511 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1512 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1513 report_fatal_error("SSE register return with SSE disabled");
1515 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1516 // llvm-gcc has never done it right and no one has noticed, so this
1517 // should be OK for now.
1518 if (ValVT == MVT::f64 &&
1519 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1520 report_fatal_error("SSE2 register return with SSE2 disabled");
1522 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1523 // the RET instruction and handled by the FP Stackifier.
1524 if (VA.getLocReg() == X86::ST0 ||
1525 VA.getLocReg() == X86::ST1) {
1526 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1527 // change the value to the FP stack register class.
1528 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1529 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1530 RetOps.push_back(ValToCopy);
1531 // Don't emit a copytoreg.
1535 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1536 // which is returned in RAX / RDX.
1537 if (Subtarget->is64Bit()) {
1538 if (ValVT == MVT::x86mmx) {
1539 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1540 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1541 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1543 // If we don't have SSE2 available, convert to v4f32 so the generated
1544 // register is legal.
1545 if (!Subtarget->hasSSE2())
1546 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1551 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1552 Flag = Chain.getValue(1);
1555 // The x86-64 ABI for returning structs by value requires that we copy
1556 // the sret argument into %rax for the return. We saved the argument into
1557 // a virtual register in the entry block, so now we copy the value out
1559 if (Subtarget->is64Bit() &&
1560 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1561 MachineFunction &MF = DAG.getMachineFunction();
1562 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1563 unsigned Reg = FuncInfo->getSRetReturnReg();
1565 "SRetReturnReg should have been set in LowerFormalArguments().");
1566 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1568 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1569 Flag = Chain.getValue(1);
1571 // RAX now acts like a return value.
1572 MRI.addLiveOut(X86::RAX);
1575 RetOps[0] = Chain; // Update chain.
1577 // Add the flag if we have it.
1579 RetOps.push_back(Flag);
1581 return DAG.getNode(X86ISD::RET_FLAG, dl,
1582 MVT::Other, &RetOps[0], RetOps.size());
1585 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1586 if (N->getNumValues() != 1)
1588 if (!N->hasNUsesOfValue(1, 0))
1591 SDNode *Copy = *N->use_begin();
1592 if (Copy->getOpcode() != ISD::CopyToReg &&
1593 Copy->getOpcode() != ISD::FP_EXTEND)
1596 bool HasRet = false;
1597 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1599 if (UI->getOpcode() != X86ISD::RET_FLAG)
1608 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1609 ISD::NodeType ExtendKind) const {
1611 // TODO: Is this also valid on 32-bit?
1612 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1613 ReturnMVT = MVT::i8;
1615 ReturnMVT = MVT::i32;
1617 EVT MinVT = getRegisterType(Context, ReturnMVT);
1618 return VT.bitsLT(MinVT) ? MinVT : VT;
1621 /// LowerCallResult - Lower the result values of a call into the
1622 /// appropriate copies out of appropriate physical registers.
1625 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1626 CallingConv::ID CallConv, bool isVarArg,
1627 const SmallVectorImpl<ISD::InputArg> &Ins,
1628 DebugLoc dl, SelectionDAG &DAG,
1629 SmallVectorImpl<SDValue> &InVals) const {
1631 // Assign locations to each value returned by this call.
1632 SmallVector<CCValAssign, 16> RVLocs;
1633 bool Is64Bit = Subtarget->is64Bit();
1634 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1635 getTargetMachine(), RVLocs, *DAG.getContext());
1636 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1638 // Copy all of the result registers out of their specified physreg.
1639 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1640 CCValAssign &VA = RVLocs[i];
1641 EVT CopyVT = VA.getValVT();
1643 // If this is x86-64, and we disabled SSE, we can't return FP values
1644 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1645 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1646 report_fatal_error("SSE register return with SSE disabled");
1651 // If this is a call to a function that returns an fp value on the floating
1652 // point stack, we must guarantee the the value is popped from the stack, so
1653 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1654 // if the return value is not used. We use the FpPOP_RETVAL instruction
1656 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1657 // If we prefer to use the value in xmm registers, copy it out as f80 and
1658 // use a truncate to move it from fp stack reg to xmm reg.
1659 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1660 SDValue Ops[] = { Chain, InFlag };
1661 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1662 MVT::Other, MVT::Glue, Ops, 2), 1);
1663 Val = Chain.getValue(0);
1665 // Round the f80 to the right size, which also moves it to the appropriate
1667 if (CopyVT != VA.getValVT())
1668 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1669 // This truncation won't change the value.
1670 DAG.getIntPtrConstant(1));
1672 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1673 CopyVT, InFlag).getValue(1);
1674 Val = Chain.getValue(0);
1676 InFlag = Chain.getValue(2);
1677 InVals.push_back(Val);
1684 //===----------------------------------------------------------------------===//
1685 // C & StdCall & Fast Calling Convention implementation
1686 //===----------------------------------------------------------------------===//
1687 // StdCall calling convention seems to be standard for many Windows' API
1688 // routines and around. It differs from C calling convention just a little:
1689 // callee should clean up the stack, not caller. Symbols should be also
1690 // decorated in some fancy way :) It doesn't support any vector arguments.
1691 // For info on fast calling convention see Fast Calling Convention (tail call)
1692 // implementation LowerX86_32FastCCCallTo.
1694 /// CallIsStructReturn - Determines whether a call uses struct return
1696 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1700 return Outs[0].Flags.isSRet();
1703 /// ArgsAreStructReturn - Determines whether a function uses struct
1704 /// return semantics.
1706 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1710 return Ins[0].Flags.isSRet();
1713 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1714 /// by "Src" to address "Dst" with size and alignment information specified by
1715 /// the specific parameter attribute. The copy will be passed as a byval
1716 /// function parameter.
1718 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1719 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1721 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1723 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1724 /*isVolatile*/false, /*AlwaysInline=*/true,
1725 MachinePointerInfo(), MachinePointerInfo());
1728 /// IsTailCallConvention - Return true if the calling convention is one that
1729 /// supports tail call optimization.
1730 static bool IsTailCallConvention(CallingConv::ID CC) {
1731 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1734 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1735 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1739 CallingConv::ID CalleeCC = CS.getCallingConv();
1740 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1746 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1747 /// a tailcall target by changing its ABI.
1748 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1749 bool GuaranteedTailCallOpt) {
1750 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1754 X86TargetLowering::LowerMemArgument(SDValue Chain,
1755 CallingConv::ID CallConv,
1756 const SmallVectorImpl<ISD::InputArg> &Ins,
1757 DebugLoc dl, SelectionDAG &DAG,
1758 const CCValAssign &VA,
1759 MachineFrameInfo *MFI,
1761 // Create the nodes corresponding to a load from this parameter slot.
1762 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1763 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1764 getTargetMachine().Options.GuaranteedTailCallOpt);
1765 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1768 // If value is passed by pointer we have address passed instead of the value
1770 if (VA.getLocInfo() == CCValAssign::Indirect)
1771 ValVT = VA.getLocVT();
1773 ValVT = VA.getValVT();
1775 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1776 // changed with more analysis.
1777 // In case of tail call optimization mark all arguments mutable. Since they
1778 // could be overwritten by lowering of arguments in case of a tail call.
1779 if (Flags.isByVal()) {
1780 unsigned Bytes = Flags.getByValSize();
1781 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1782 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1783 return DAG.getFrameIndex(FI, getPointerTy());
1785 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1786 VA.getLocMemOffset(), isImmutable);
1787 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1788 return DAG.getLoad(ValVT, dl, Chain, FIN,
1789 MachinePointerInfo::getFixedStack(FI),
1790 false, false, false, 0);
1795 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1796 CallingConv::ID CallConv,
1798 const SmallVectorImpl<ISD::InputArg> &Ins,
1801 SmallVectorImpl<SDValue> &InVals)
1803 MachineFunction &MF = DAG.getMachineFunction();
1804 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1806 const Function* Fn = MF.getFunction();
1807 if (Fn->hasExternalLinkage() &&
1808 Subtarget->isTargetCygMing() &&
1809 Fn->getName() == "main")
1810 FuncInfo->setForceFramePointer(true);
1812 MachineFrameInfo *MFI = MF.getFrameInfo();
1813 bool Is64Bit = Subtarget->is64Bit();
1814 bool IsWindows = Subtarget->isTargetWindows();
1815 bool IsWin64 = Subtarget->isTargetWin64();
1817 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1818 "Var args not supported with calling convention fastcc or ghc");
1820 // Assign locations to all of the incoming arguments.
1821 SmallVector<CCValAssign, 16> ArgLocs;
1822 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1823 ArgLocs, *DAG.getContext());
1825 // Allocate shadow area for Win64
1827 CCInfo.AllocateStack(32, 8);
1830 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1832 unsigned LastVal = ~0U;
1834 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1835 CCValAssign &VA = ArgLocs[i];
1836 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1838 assert(VA.getValNo() != LastVal &&
1839 "Don't support value assigned to multiple locs yet");
1841 LastVal = VA.getValNo();
1843 if (VA.isRegLoc()) {
1844 EVT RegVT = VA.getLocVT();
1845 TargetRegisterClass *RC = NULL;
1846 if (RegVT == MVT::i32)
1847 RC = X86::GR32RegisterClass;
1848 else if (Is64Bit && RegVT == MVT::i64)
1849 RC = X86::GR64RegisterClass;
1850 else if (RegVT == MVT::f32)
1851 RC = X86::FR32RegisterClass;
1852 else if (RegVT == MVT::f64)
1853 RC = X86::FR64RegisterClass;
1854 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1855 RC = X86::VR256RegisterClass;
1856 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1857 RC = X86::VR128RegisterClass;
1858 else if (RegVT == MVT::x86mmx)
1859 RC = X86::VR64RegisterClass;
1861 llvm_unreachable("Unknown argument type!");
1863 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1864 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1866 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1867 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1869 if (VA.getLocInfo() == CCValAssign::SExt)
1870 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1871 DAG.getValueType(VA.getValVT()));
1872 else if (VA.getLocInfo() == CCValAssign::ZExt)
1873 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1874 DAG.getValueType(VA.getValVT()));
1875 else if (VA.getLocInfo() == CCValAssign::BCvt)
1876 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1878 if (VA.isExtInLoc()) {
1879 // Handle MMX values passed in XMM regs.
1880 if (RegVT.isVector()) {
1881 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1884 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1887 assert(VA.isMemLoc());
1888 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1891 // If value is passed via pointer - do a load.
1892 if (VA.getLocInfo() == CCValAssign::Indirect)
1893 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1894 MachinePointerInfo(), false, false, false, 0);
1896 InVals.push_back(ArgValue);
1899 // The x86-64 ABI for returning structs by value requires that we copy
1900 // the sret argument into %rax for the return. Save the argument into
1901 // a virtual register so that we can access it from the return points.
1902 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1903 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1904 unsigned Reg = FuncInfo->getSRetReturnReg();
1906 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1907 FuncInfo->setSRetReturnReg(Reg);
1909 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1910 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1913 unsigned StackSize = CCInfo.getNextStackOffset();
1914 // Align stack specially for tail calls.
1915 if (FuncIsMadeTailCallSafe(CallConv,
1916 MF.getTarget().Options.GuaranteedTailCallOpt))
1917 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1919 // If the function takes variable number of arguments, make a frame index for
1920 // the start of the first vararg value... for expansion of llvm.va_start.
1922 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1923 CallConv != CallingConv::X86_ThisCall)) {
1924 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1927 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1929 // FIXME: We should really autogenerate these arrays
1930 static const unsigned GPR64ArgRegsWin64[] = {
1931 X86::RCX, X86::RDX, X86::R8, X86::R9
1933 static const unsigned GPR64ArgRegs64Bit[] = {
1934 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1936 static const unsigned XMMArgRegs64Bit[] = {
1937 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1938 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1940 const unsigned *GPR64ArgRegs;
1941 unsigned NumXMMRegs = 0;
1944 // The XMM registers which might contain var arg parameters are shadowed
1945 // in their paired GPR. So we only need to save the GPR to their home
1947 TotalNumIntRegs = 4;
1948 GPR64ArgRegs = GPR64ArgRegsWin64;
1950 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1951 GPR64ArgRegs = GPR64ArgRegs64Bit;
1953 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1956 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1959 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1960 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1961 "SSE register cannot be used when SSE is disabled!");
1962 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1963 NoImplicitFloatOps) &&
1964 "SSE register cannot be used when SSE is disabled!");
1965 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1966 !Subtarget->hasSSE1())
1967 // Kernel mode asks for SSE to be disabled, so don't push them
1969 TotalNumXMMRegs = 0;
1972 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1973 // Get to the caller-allocated home save location. Add 8 to account
1974 // for the return address.
1975 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1976 FuncInfo->setRegSaveFrameIndex(
1977 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1978 // Fixup to set vararg frame on shadow area (4 x i64).
1980 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1982 // For X86-64, if there are vararg parameters that are passed via
1983 // registers, then we must store them to their spots on the stack so
1984 // they may be loaded by deferencing the result of va_next.
1985 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1986 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1987 FuncInfo->setRegSaveFrameIndex(
1988 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1992 // Store the integer parameter registers.
1993 SmallVector<SDValue, 8> MemOps;
1994 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1996 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1997 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1998 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1999 DAG.getIntPtrConstant(Offset));
2000 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2001 X86::GR64RegisterClass);
2002 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2004 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2005 MachinePointerInfo::getFixedStack(
2006 FuncInfo->getRegSaveFrameIndex(), Offset),
2008 MemOps.push_back(Store);
2012 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2013 // Now store the XMM (fp + vector) parameter registers.
2014 SmallVector<SDValue, 11> SaveXMMOps;
2015 SaveXMMOps.push_back(Chain);
2017 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
2018 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2019 SaveXMMOps.push_back(ALVal);
2021 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2022 FuncInfo->getRegSaveFrameIndex()));
2023 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2024 FuncInfo->getVarArgsFPOffset()));
2026 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2027 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2028 X86::VR128RegisterClass);
2029 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2030 SaveXMMOps.push_back(Val);
2032 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2034 &SaveXMMOps[0], SaveXMMOps.size()));
2037 if (!MemOps.empty())
2038 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2039 &MemOps[0], MemOps.size());
2043 // Some CCs need callee pop.
2044 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2045 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2046 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2048 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2049 // If this is an sret function, the return should pop the hidden pointer.
2050 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2051 ArgsAreStructReturn(Ins))
2052 FuncInfo->setBytesToPopOnReturn(4);
2056 // RegSaveFrameIndex is X86-64 only.
2057 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2058 if (CallConv == CallingConv::X86_FastCall ||
2059 CallConv == CallingConv::X86_ThisCall)
2060 // fastcc functions can't have varargs.
2061 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2064 FuncInfo->setArgumentStackSize(StackSize);
2070 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2071 SDValue StackPtr, SDValue Arg,
2072 DebugLoc dl, SelectionDAG &DAG,
2073 const CCValAssign &VA,
2074 ISD::ArgFlagsTy Flags) const {
2075 unsigned LocMemOffset = VA.getLocMemOffset();
2076 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2077 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2078 if (Flags.isByVal())
2079 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2081 return DAG.getStore(Chain, dl, Arg, PtrOff,
2082 MachinePointerInfo::getStack(LocMemOffset),
2086 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2087 /// optimization is performed and it is required.
2089 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2090 SDValue &OutRetAddr, SDValue Chain,
2091 bool IsTailCall, bool Is64Bit,
2092 int FPDiff, DebugLoc dl) const {
2093 // Adjust the Return address stack slot.
2094 EVT VT = getPointerTy();
2095 OutRetAddr = getReturnAddressFrameIndex(DAG);
2097 // Load the "old" Return address.
2098 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2099 false, false, false, 0);
2100 return SDValue(OutRetAddr.getNode(), 1);
2103 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2104 /// optimization is performed and it is required (FPDiff!=0).
2106 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2107 SDValue Chain, SDValue RetAddrFrIdx,
2108 bool Is64Bit, int FPDiff, DebugLoc dl) {
2109 // Store the return address to the appropriate stack slot.
2110 if (!FPDiff) return Chain;
2111 // Calculate the new stack slot for the return address.
2112 int SlotSize = Is64Bit ? 8 : 4;
2113 int NewReturnAddrFI =
2114 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2115 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2116 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2117 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2118 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2124 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2125 CallingConv::ID CallConv, bool isVarArg,
2127 const SmallVectorImpl<ISD::OutputArg> &Outs,
2128 const SmallVectorImpl<SDValue> &OutVals,
2129 const SmallVectorImpl<ISD::InputArg> &Ins,
2130 DebugLoc dl, SelectionDAG &DAG,
2131 SmallVectorImpl<SDValue> &InVals) const {
2132 MachineFunction &MF = DAG.getMachineFunction();
2133 bool Is64Bit = Subtarget->is64Bit();
2134 bool IsWin64 = Subtarget->isTargetWin64();
2135 bool IsWindows = Subtarget->isTargetWindows();
2136 bool IsStructRet = CallIsStructReturn(Outs);
2137 bool IsSibcall = false;
2139 if (MF.getTarget().Options.DisableTailCalls)
2143 // Check if it's really possible to do a tail call.
2144 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2145 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2146 Outs, OutVals, Ins, DAG);
2148 // Sibcalls are automatically detected tailcalls which do not require
2150 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2157 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2158 "Var args not supported with calling convention fastcc or ghc");
2160 // Analyze operands of the call, assigning locations to each operand.
2161 SmallVector<CCValAssign, 16> ArgLocs;
2162 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2163 ArgLocs, *DAG.getContext());
2165 // Allocate shadow area for Win64
2167 CCInfo.AllocateStack(32, 8);
2170 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2172 // Get a count of how many bytes are to be pushed on the stack.
2173 unsigned NumBytes = CCInfo.getNextStackOffset();
2175 // This is a sibcall. The memory operands are available in caller's
2176 // own caller's stack.
2178 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2179 IsTailCallConvention(CallConv))
2180 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2183 if (isTailCall && !IsSibcall) {
2184 // Lower arguments at fp - stackoffset + fpdiff.
2185 unsigned NumBytesCallerPushed =
2186 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2187 FPDiff = NumBytesCallerPushed - NumBytes;
2189 // Set the delta of movement of the returnaddr stackslot.
2190 // But only set if delta is greater than previous delta.
2191 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2192 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2196 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2198 SDValue RetAddrFrIdx;
2199 // Load return address for tail calls.
2200 if (isTailCall && FPDiff)
2201 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2202 Is64Bit, FPDiff, dl);
2204 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2205 SmallVector<SDValue, 8> MemOpChains;
2208 // Walk the register/memloc assignments, inserting copies/loads. In the case
2209 // of tail call optimization arguments are handle later.
2210 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2211 CCValAssign &VA = ArgLocs[i];
2212 EVT RegVT = VA.getLocVT();
2213 SDValue Arg = OutVals[i];
2214 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2215 bool isByVal = Flags.isByVal();
2217 // Promote the value if needed.
2218 switch (VA.getLocInfo()) {
2219 default: llvm_unreachable("Unknown loc info!");
2220 case CCValAssign::Full: break;
2221 case CCValAssign::SExt:
2222 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2224 case CCValAssign::ZExt:
2225 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2227 case CCValAssign::AExt:
2228 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2229 // Special case: passing MMX values in XMM registers.
2230 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2231 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2232 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2234 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2236 case CCValAssign::BCvt:
2237 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2239 case CCValAssign::Indirect: {
2240 // Store the argument.
2241 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2242 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2243 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2244 MachinePointerInfo::getFixedStack(FI),
2251 if (VA.isRegLoc()) {
2252 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2253 if (isVarArg && IsWin64) {
2254 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2255 // shadow reg if callee is a varargs function.
2256 unsigned ShadowReg = 0;
2257 switch (VA.getLocReg()) {
2258 case X86::XMM0: ShadowReg = X86::RCX; break;
2259 case X86::XMM1: ShadowReg = X86::RDX; break;
2260 case X86::XMM2: ShadowReg = X86::R8; break;
2261 case X86::XMM3: ShadowReg = X86::R9; break;
2264 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2266 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2267 assert(VA.isMemLoc());
2268 if (StackPtr.getNode() == 0)
2269 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2270 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2271 dl, DAG, VA, Flags));
2275 if (!MemOpChains.empty())
2276 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2277 &MemOpChains[0], MemOpChains.size());
2279 // Build a sequence of copy-to-reg nodes chained together with token chain
2280 // and flag operands which copy the outgoing args into registers.
2282 // Tail call byval lowering might overwrite argument registers so in case of
2283 // tail call optimization the copies to registers are lowered later.
2285 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2286 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2287 RegsToPass[i].second, InFlag);
2288 InFlag = Chain.getValue(1);
2291 if (Subtarget->isPICStyleGOT()) {
2292 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2295 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2296 DAG.getNode(X86ISD::GlobalBaseReg,
2297 DebugLoc(), getPointerTy()),
2299 InFlag = Chain.getValue(1);
2301 // If we are tail calling and generating PIC/GOT style code load the
2302 // address of the callee into ECX. The value in ecx is used as target of
2303 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2304 // for tail calls on PIC/GOT architectures. Normally we would just put the
2305 // address of GOT into ebx and then call target@PLT. But for tail calls
2306 // ebx would be restored (since ebx is callee saved) before jumping to the
2309 // Note: The actual moving to ECX is done further down.
2310 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2311 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2312 !G->getGlobal()->hasProtectedVisibility())
2313 Callee = LowerGlobalAddress(Callee, DAG);
2314 else if (isa<ExternalSymbolSDNode>(Callee))
2315 Callee = LowerExternalSymbol(Callee, DAG);
2319 if (Is64Bit && isVarArg && !IsWin64) {
2320 // From AMD64 ABI document:
2321 // For calls that may call functions that use varargs or stdargs
2322 // (prototype-less calls or calls to functions containing ellipsis (...) in
2323 // the declaration) %al is used as hidden argument to specify the number
2324 // of SSE registers used. The contents of %al do not need to match exactly
2325 // the number of registers, but must be an ubound on the number of SSE
2326 // registers used and is in the range 0 - 8 inclusive.
2328 // Count the number of XMM registers allocated.
2329 static const unsigned XMMArgRegs[] = {
2330 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2331 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2333 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2334 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2335 && "SSE registers cannot be used when SSE is disabled");
2337 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2338 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2339 InFlag = Chain.getValue(1);
2343 // For tail calls lower the arguments to the 'real' stack slot.
2345 // Force all the incoming stack arguments to be loaded from the stack
2346 // before any new outgoing arguments are stored to the stack, because the
2347 // outgoing stack slots may alias the incoming argument stack slots, and
2348 // the alias isn't otherwise explicit. This is slightly more conservative
2349 // than necessary, because it means that each store effectively depends
2350 // on every argument instead of just those arguments it would clobber.
2351 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2353 SmallVector<SDValue, 8> MemOpChains2;
2356 // Do not flag preceding copytoreg stuff together with the following stuff.
2358 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2359 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2360 CCValAssign &VA = ArgLocs[i];
2363 assert(VA.isMemLoc());
2364 SDValue Arg = OutVals[i];
2365 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2366 // Create frame index.
2367 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2368 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2369 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2370 FIN = DAG.getFrameIndex(FI, getPointerTy());
2372 if (Flags.isByVal()) {
2373 // Copy relative to framepointer.
2374 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2375 if (StackPtr.getNode() == 0)
2376 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2378 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2380 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2384 // Store relative to framepointer.
2385 MemOpChains2.push_back(
2386 DAG.getStore(ArgChain, dl, Arg, FIN,
2387 MachinePointerInfo::getFixedStack(FI),
2393 if (!MemOpChains2.empty())
2394 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2395 &MemOpChains2[0], MemOpChains2.size());
2397 // Copy arguments to their registers.
2398 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2399 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2400 RegsToPass[i].second, InFlag);
2401 InFlag = Chain.getValue(1);
2405 // Store the return address to the appropriate stack slot.
2406 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2410 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2411 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2412 // In the 64-bit large code model, we have to make all calls
2413 // through a register, since the call instruction's 32-bit
2414 // pc-relative offset may not be large enough to hold the whole
2416 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2417 // If the callee is a GlobalAddress node (quite common, every direct call
2418 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2421 // We should use extra load for direct calls to dllimported functions in
2423 const GlobalValue *GV = G->getGlobal();
2424 if (!GV->hasDLLImportLinkage()) {
2425 unsigned char OpFlags = 0;
2426 bool ExtraLoad = false;
2427 unsigned WrapperKind = ISD::DELETED_NODE;
2429 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2430 // external symbols most go through the PLT in PIC mode. If the symbol
2431 // has hidden or protected visibility, or if it is static or local, then
2432 // we don't need to use the PLT - we can directly call it.
2433 if (Subtarget->isTargetELF() &&
2434 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2435 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2436 OpFlags = X86II::MO_PLT;
2437 } else if (Subtarget->isPICStyleStubAny() &&
2438 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2439 (!Subtarget->getTargetTriple().isMacOSX() ||
2440 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2441 // PC-relative references to external symbols should go through $stub,
2442 // unless we're building with the leopard linker or later, which
2443 // automatically synthesizes these stubs.
2444 OpFlags = X86II::MO_DARWIN_STUB;
2445 } else if (Subtarget->isPICStyleRIPRel() &&
2446 isa<Function>(GV) &&
2447 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2448 // If the function is marked as non-lazy, generate an indirect call
2449 // which loads from the GOT directly. This avoids runtime overhead
2450 // at the cost of eager binding (and one extra byte of encoding).
2451 OpFlags = X86II::MO_GOTPCREL;
2452 WrapperKind = X86ISD::WrapperRIP;
2456 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2457 G->getOffset(), OpFlags);
2459 // Add a wrapper if needed.
2460 if (WrapperKind != ISD::DELETED_NODE)
2461 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2462 // Add extra indirection if needed.
2464 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2465 MachinePointerInfo::getGOT(),
2466 false, false, false, 0);
2468 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2469 unsigned char OpFlags = 0;
2471 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2472 // external symbols should go through the PLT.
2473 if (Subtarget->isTargetELF() &&
2474 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2475 OpFlags = X86II::MO_PLT;
2476 } else if (Subtarget->isPICStyleStubAny() &&
2477 (!Subtarget->getTargetTriple().isMacOSX() ||
2478 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2479 // PC-relative references to external symbols should go through $stub,
2480 // unless we're building with the leopard linker or later, which
2481 // automatically synthesizes these stubs.
2482 OpFlags = X86II::MO_DARWIN_STUB;
2485 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2489 // Returns a chain & a flag for retval copy to use.
2490 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2491 SmallVector<SDValue, 8> Ops;
2493 if (!IsSibcall && isTailCall) {
2494 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2495 DAG.getIntPtrConstant(0, true), InFlag);
2496 InFlag = Chain.getValue(1);
2499 Ops.push_back(Chain);
2500 Ops.push_back(Callee);
2503 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2505 // Add argument registers to the end of the list so that they are known live
2507 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2508 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2509 RegsToPass[i].second.getValueType()));
2511 // Add an implicit use GOT pointer in EBX.
2512 if (!isTailCall && Subtarget->isPICStyleGOT())
2513 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2515 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2516 if (Is64Bit && isVarArg && !IsWin64)
2517 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2519 // Experimental: Add a register mask operand representing the call-preserved
2522 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2523 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2524 Ops.push_back(DAG.getRegisterMask(Mask));
2527 if (InFlag.getNode())
2528 Ops.push_back(InFlag);
2532 //// If this is the first return lowered for this function, add the regs
2533 //// to the liveout set for the function.
2534 // This isn't right, although it's probably harmless on x86; liveouts
2535 // should be computed from returns not tail calls. Consider a void
2536 // function making a tail call to a function returning int.
2537 return DAG.getNode(X86ISD::TC_RETURN, dl,
2538 NodeTys, &Ops[0], Ops.size());
2541 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2542 InFlag = Chain.getValue(1);
2544 // Create the CALLSEQ_END node.
2545 unsigned NumBytesForCalleeToPush;
2546 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2547 getTargetMachine().Options.GuaranteedTailCallOpt))
2548 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2549 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2551 // If this is a call to a struct-return function, the callee
2552 // pops the hidden struct pointer, so we have to push it back.
2553 // This is common for Darwin/X86, Linux & Mingw32 targets.
2554 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2555 NumBytesForCalleeToPush = 4;
2557 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2559 // Returns a flag for retval copy to use.
2561 Chain = DAG.getCALLSEQ_END(Chain,
2562 DAG.getIntPtrConstant(NumBytes, true),
2563 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2566 InFlag = Chain.getValue(1);
2569 // Handle result values, copying them out of physregs into vregs that we
2571 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2572 Ins, dl, DAG, InVals);
2576 //===----------------------------------------------------------------------===//
2577 // Fast Calling Convention (tail call) implementation
2578 //===----------------------------------------------------------------------===//
2580 // Like std call, callee cleans arguments, convention except that ECX is
2581 // reserved for storing the tail called function address. Only 2 registers are
2582 // free for argument passing (inreg). Tail call optimization is performed
2584 // * tailcallopt is enabled
2585 // * caller/callee are fastcc
2586 // On X86_64 architecture with GOT-style position independent code only local
2587 // (within module) calls are supported at the moment.
2588 // To keep the stack aligned according to platform abi the function
2589 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2590 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2591 // If a tail called function callee has more arguments than the caller the
2592 // caller needs to make sure that there is room to move the RETADDR to. This is
2593 // achieved by reserving an area the size of the argument delta right after the
2594 // original REtADDR, but before the saved framepointer or the spilled registers
2595 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2607 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2608 /// for a 16 byte align requirement.
2610 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2611 SelectionDAG& DAG) const {
2612 MachineFunction &MF = DAG.getMachineFunction();
2613 const TargetMachine &TM = MF.getTarget();
2614 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2615 unsigned StackAlignment = TFI.getStackAlignment();
2616 uint64_t AlignMask = StackAlignment - 1;
2617 int64_t Offset = StackSize;
2618 uint64_t SlotSize = TD->getPointerSize();
2619 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2620 // Number smaller than 12 so just add the difference.
2621 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2623 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2624 Offset = ((~AlignMask) & Offset) + StackAlignment +
2625 (StackAlignment-SlotSize);
2630 /// MatchingStackOffset - Return true if the given stack call argument is
2631 /// already available in the same position (relatively) of the caller's
2632 /// incoming argument stack.
2634 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2635 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2636 const X86InstrInfo *TII) {
2637 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2639 if (Arg.getOpcode() == ISD::CopyFromReg) {
2640 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2641 if (!TargetRegisterInfo::isVirtualRegister(VR))
2643 MachineInstr *Def = MRI->getVRegDef(VR);
2646 if (!Flags.isByVal()) {
2647 if (!TII->isLoadFromStackSlot(Def, FI))
2650 unsigned Opcode = Def->getOpcode();
2651 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2652 Def->getOperand(1).isFI()) {
2653 FI = Def->getOperand(1).getIndex();
2654 Bytes = Flags.getByValSize();
2658 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2659 if (Flags.isByVal())
2660 // ByVal argument is passed in as a pointer but it's now being
2661 // dereferenced. e.g.
2662 // define @foo(%struct.X* %A) {
2663 // tail call @bar(%struct.X* byval %A)
2666 SDValue Ptr = Ld->getBasePtr();
2667 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2670 FI = FINode->getIndex();
2671 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2672 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2673 FI = FINode->getIndex();
2674 Bytes = Flags.getByValSize();
2678 assert(FI != INT_MAX);
2679 if (!MFI->isFixedObjectIndex(FI))
2681 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2684 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2685 /// for tail call optimization. Targets which want to do tail call
2686 /// optimization should implement this function.
2688 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2689 CallingConv::ID CalleeCC,
2691 bool isCalleeStructRet,
2692 bool isCallerStructRet,
2693 const SmallVectorImpl<ISD::OutputArg> &Outs,
2694 const SmallVectorImpl<SDValue> &OutVals,
2695 const SmallVectorImpl<ISD::InputArg> &Ins,
2696 SelectionDAG& DAG) const {
2697 if (!IsTailCallConvention(CalleeCC) &&
2698 CalleeCC != CallingConv::C)
2701 // If -tailcallopt is specified, make fastcc functions tail-callable.
2702 const MachineFunction &MF = DAG.getMachineFunction();
2703 const Function *CallerF = DAG.getMachineFunction().getFunction();
2704 CallingConv::ID CallerCC = CallerF->getCallingConv();
2705 bool CCMatch = CallerCC == CalleeCC;
2707 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2708 if (IsTailCallConvention(CalleeCC) && CCMatch)
2713 // Look for obvious safe cases to perform tail call optimization that do not
2714 // require ABI changes. This is what gcc calls sibcall.
2716 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2717 // emit a special epilogue.
2718 if (RegInfo->needsStackRealignment(MF))
2721 // Also avoid sibcall optimization if either caller or callee uses struct
2722 // return semantics.
2723 if (isCalleeStructRet || isCallerStructRet)
2726 // An stdcall caller is expected to clean up its arguments; the callee
2727 // isn't going to do that.
2728 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2731 // Do not sibcall optimize vararg calls unless all arguments are passed via
2733 if (isVarArg && !Outs.empty()) {
2735 // Optimizing for varargs on Win64 is unlikely to be safe without
2736 // additional testing.
2737 if (Subtarget->isTargetWin64())
2740 SmallVector<CCValAssign, 16> ArgLocs;
2741 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2742 getTargetMachine(), ArgLocs, *DAG.getContext());
2744 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2745 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2746 if (!ArgLocs[i].isRegLoc())
2750 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2751 // stack. Therefore, if it's not used by the call it is not safe to optimize
2752 // this into a sibcall.
2753 bool Unused = false;
2754 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2761 SmallVector<CCValAssign, 16> RVLocs;
2762 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2763 getTargetMachine(), RVLocs, *DAG.getContext());
2764 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2765 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2766 CCValAssign &VA = RVLocs[i];
2767 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2772 // If the calling conventions do not match, then we'd better make sure the
2773 // results are returned in the same way as what the caller expects.
2775 SmallVector<CCValAssign, 16> RVLocs1;
2776 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2777 getTargetMachine(), RVLocs1, *DAG.getContext());
2778 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2780 SmallVector<CCValAssign, 16> RVLocs2;
2781 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2782 getTargetMachine(), RVLocs2, *DAG.getContext());
2783 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2785 if (RVLocs1.size() != RVLocs2.size())
2787 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2788 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2790 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2792 if (RVLocs1[i].isRegLoc()) {
2793 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2796 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2802 // If the callee takes no arguments then go on to check the results of the
2804 if (!Outs.empty()) {
2805 // Check if stack adjustment is needed. For now, do not do this if any
2806 // argument is passed on the stack.
2807 SmallVector<CCValAssign, 16> ArgLocs;
2808 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2809 getTargetMachine(), ArgLocs, *DAG.getContext());
2811 // Allocate shadow area for Win64
2812 if (Subtarget->isTargetWin64()) {
2813 CCInfo.AllocateStack(32, 8);
2816 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2817 if (CCInfo.getNextStackOffset()) {
2818 MachineFunction &MF = DAG.getMachineFunction();
2819 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2822 // Check if the arguments are already laid out in the right way as
2823 // the caller's fixed stack objects.
2824 MachineFrameInfo *MFI = MF.getFrameInfo();
2825 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2826 const X86InstrInfo *TII =
2827 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2828 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2829 CCValAssign &VA = ArgLocs[i];
2830 SDValue Arg = OutVals[i];
2831 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2832 if (VA.getLocInfo() == CCValAssign::Indirect)
2834 if (!VA.isRegLoc()) {
2835 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2842 // If the tailcall address may be in a register, then make sure it's
2843 // possible to register allocate for it. In 32-bit, the call address can
2844 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2845 // callee-saved registers are restored. These happen to be the same
2846 // registers used to pass 'inreg' arguments so watch out for those.
2847 if (!Subtarget->is64Bit() &&
2848 !isa<GlobalAddressSDNode>(Callee) &&
2849 !isa<ExternalSymbolSDNode>(Callee)) {
2850 unsigned NumInRegs = 0;
2851 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2852 CCValAssign &VA = ArgLocs[i];
2855 unsigned Reg = VA.getLocReg();
2858 case X86::EAX: case X86::EDX: case X86::ECX:
2859 if (++NumInRegs == 3)
2871 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2872 return X86::createFastISel(funcInfo);
2876 //===----------------------------------------------------------------------===//
2877 // Other Lowering Hooks
2878 //===----------------------------------------------------------------------===//
2880 static bool MayFoldLoad(SDValue Op) {
2881 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2884 static bool MayFoldIntoStore(SDValue Op) {
2885 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2888 static bool isTargetShuffle(unsigned Opcode) {
2890 default: return false;
2891 case X86ISD::PSHUFD:
2892 case X86ISD::PSHUFHW:
2893 case X86ISD::PSHUFLW:
2895 case X86ISD::PALIGN:
2896 case X86ISD::MOVLHPS:
2897 case X86ISD::MOVLHPD:
2898 case X86ISD::MOVHLPS:
2899 case X86ISD::MOVLPS:
2900 case X86ISD::MOVLPD:
2901 case X86ISD::MOVSHDUP:
2902 case X86ISD::MOVSLDUP:
2903 case X86ISD::MOVDDUP:
2906 case X86ISD::UNPCKL:
2907 case X86ISD::UNPCKH:
2908 case X86ISD::VPERMILP:
2909 case X86ISD::VPERM2X128:
2915 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2916 SDValue V1, SelectionDAG &DAG) {
2918 default: llvm_unreachable("Unknown x86 shuffle node");
2919 case X86ISD::MOVSHDUP:
2920 case X86ISD::MOVSLDUP:
2921 case X86ISD::MOVDDUP:
2922 return DAG.getNode(Opc, dl, VT, V1);
2928 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2929 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2931 default: llvm_unreachable("Unknown x86 shuffle node");
2932 case X86ISD::PSHUFD:
2933 case X86ISD::PSHUFHW:
2934 case X86ISD::PSHUFLW:
2935 case X86ISD::VPERMILP:
2936 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2942 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2943 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2945 default: llvm_unreachable("Unknown x86 shuffle node");
2946 case X86ISD::PALIGN:
2948 case X86ISD::VPERM2X128:
2949 return DAG.getNode(Opc, dl, VT, V1, V2,
2950 DAG.getConstant(TargetMask, MVT::i8));
2955 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2956 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2958 default: llvm_unreachable("Unknown x86 shuffle node");
2959 case X86ISD::MOVLHPS:
2960 case X86ISD::MOVLHPD:
2961 case X86ISD::MOVHLPS:
2962 case X86ISD::MOVLPS:
2963 case X86ISD::MOVLPD:
2966 case X86ISD::UNPCKL:
2967 case X86ISD::UNPCKH:
2968 return DAG.getNode(Opc, dl, VT, V1, V2);
2973 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2974 MachineFunction &MF = DAG.getMachineFunction();
2975 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2976 int ReturnAddrIndex = FuncInfo->getRAIndex();
2978 if (ReturnAddrIndex == 0) {
2979 // Set up a frame object for the return address.
2980 uint64_t SlotSize = TD->getPointerSize();
2981 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2983 FuncInfo->setRAIndex(ReturnAddrIndex);
2986 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2990 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2991 bool hasSymbolicDisplacement) {
2992 // Offset should fit into 32 bit immediate field.
2993 if (!isInt<32>(Offset))
2996 // If we don't have a symbolic displacement - we don't have any extra
2998 if (!hasSymbolicDisplacement)
3001 // FIXME: Some tweaks might be needed for medium code model.
3002 if (M != CodeModel::Small && M != CodeModel::Kernel)
3005 // For small code model we assume that latest object is 16MB before end of 31
3006 // bits boundary. We may also accept pretty large negative constants knowing
3007 // that all objects are in the positive half of address space.
3008 if (M == CodeModel::Small && Offset < 16*1024*1024)
3011 // For kernel code model we know that all object resist in the negative half
3012 // of 32bits address space. We may not accept negative offsets, since they may
3013 // be just off and we may accept pretty large positive ones.
3014 if (M == CodeModel::Kernel && Offset > 0)
3020 /// isCalleePop - Determines whether the callee is required to pop its
3021 /// own arguments. Callee pop is necessary to support tail calls.
3022 bool X86::isCalleePop(CallingConv::ID CallingConv,
3023 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3027 switch (CallingConv) {
3030 case CallingConv::X86_StdCall:
3032 case CallingConv::X86_FastCall:
3034 case CallingConv::X86_ThisCall:
3036 case CallingConv::Fast:
3038 case CallingConv::GHC:
3043 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3044 /// specific condition code, returning the condition code and the LHS/RHS of the
3045 /// comparison to make.
3046 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3047 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3049 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3050 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3051 // X > -1 -> X == 0, jump !sign.
3052 RHS = DAG.getConstant(0, RHS.getValueType());
3053 return X86::COND_NS;
3054 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3055 // X < 0 -> X == 0, jump on sign.
3057 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3059 RHS = DAG.getConstant(0, RHS.getValueType());
3060 return X86::COND_LE;
3064 switch (SetCCOpcode) {
3065 default: llvm_unreachable("Invalid integer condition!");
3066 case ISD::SETEQ: return X86::COND_E;
3067 case ISD::SETGT: return X86::COND_G;
3068 case ISD::SETGE: return X86::COND_GE;
3069 case ISD::SETLT: return X86::COND_L;
3070 case ISD::SETLE: return X86::COND_LE;
3071 case ISD::SETNE: return X86::COND_NE;
3072 case ISD::SETULT: return X86::COND_B;
3073 case ISD::SETUGT: return X86::COND_A;
3074 case ISD::SETULE: return X86::COND_BE;
3075 case ISD::SETUGE: return X86::COND_AE;
3079 // First determine if it is required or is profitable to flip the operands.
3081 // If LHS is a foldable load, but RHS is not, flip the condition.
3082 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3083 !ISD::isNON_EXTLoad(RHS.getNode())) {
3084 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3085 std::swap(LHS, RHS);
3088 switch (SetCCOpcode) {
3094 std::swap(LHS, RHS);
3098 // On a floating point condition, the flags are set as follows:
3100 // 0 | 0 | 0 | X > Y
3101 // 0 | 0 | 1 | X < Y
3102 // 1 | 0 | 0 | X == Y
3103 // 1 | 1 | 1 | unordered
3104 switch (SetCCOpcode) {
3105 default: llvm_unreachable("Condcode should be pre-legalized away");
3107 case ISD::SETEQ: return X86::COND_E;
3108 case ISD::SETOLT: // flipped
3110 case ISD::SETGT: return X86::COND_A;
3111 case ISD::SETOLE: // flipped
3113 case ISD::SETGE: return X86::COND_AE;
3114 case ISD::SETUGT: // flipped
3116 case ISD::SETLT: return X86::COND_B;
3117 case ISD::SETUGE: // flipped
3119 case ISD::SETLE: return X86::COND_BE;
3121 case ISD::SETNE: return X86::COND_NE;
3122 case ISD::SETUO: return X86::COND_P;
3123 case ISD::SETO: return X86::COND_NP;
3125 case ISD::SETUNE: return X86::COND_INVALID;
3129 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3130 /// code. Current x86 isa includes the following FP cmov instructions:
3131 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3132 static bool hasFPCMov(unsigned X86CC) {
3148 /// isFPImmLegal - Returns true if the target can instruction select the
3149 /// specified FP immediate natively. If false, the legalizer will
3150 /// materialize the FP immediate as a load from a constant pool.
3151 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3152 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3153 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3159 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3160 /// the specified range (L, H].
3161 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3162 return (Val < 0) || (Val >= Low && Val < Hi);
3165 /// isUndefOrInRange - Return true if every element in Mask, begining
3166 /// from position Pos and ending in Pos+Size, falls within the specified
3167 /// range (L, L+Pos]. or is undef.
3168 static bool isUndefOrInRange(ArrayRef<int> Mask,
3169 int Pos, int Size, int Low, int Hi) {
3170 for (int i = Pos, e = Pos+Size; i != e; ++i)
3171 if (!isUndefOrInRange(Mask[i], Low, Hi))
3176 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3177 /// specified value.
3178 static bool isUndefOrEqual(int Val, int CmpVal) {
3179 if (Val < 0 || Val == CmpVal)
3184 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3185 /// from position Pos and ending in Pos+Size, falls within the specified
3186 /// sequential range (L, L+Pos]. or is undef.
3187 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3188 int Pos, int Size, int Low) {
3189 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3190 if (!isUndefOrEqual(Mask[i], Low))
3195 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3196 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3197 /// the second operand.
3198 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3199 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3200 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3201 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3202 return (Mask[0] < 2 && Mask[1] < 2);
3206 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3207 return ::isPSHUFDMask(N->getMask(), N->getValueType(0));
3210 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3211 /// is suitable for input to PSHUFHW.
3212 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3213 if (VT != MVT::v8i16)
3216 // Lower quadword copied in order or undef.
3217 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3220 // Upper quadword shuffled.
3221 for (unsigned i = 4; i != 8; ++i)
3222 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3228 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3229 return ::isPSHUFHWMask(N->getMask(), N->getValueType(0));
3232 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3233 /// is suitable for input to PSHUFLW.
3234 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3235 if (VT != MVT::v8i16)
3238 // Upper quadword copied in order.
3239 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3242 // Lower quadword shuffled.
3243 for (unsigned i = 0; i != 4; ++i)
3250 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3251 return ::isPSHUFLWMask(N->getMask(), N->getValueType(0));
3254 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3255 /// is suitable for input to PALIGNR.
3256 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, bool hasSSSE3) {
3257 int i, e = VT.getVectorNumElements();
3258 if (VT.getSizeInBits() != 128)
3261 // Do not handle v2i64 / v2f64 shuffles with palignr.
3262 if (e < 4 || !hasSSSE3)
3265 for (i = 0; i != e; ++i)
3269 // All undef, not a palignr.
3273 // Make sure we're shifting in the right direction.
3277 int s = Mask[i] - i;
3279 // Check the rest of the elements to see if they are consecutive.
3280 for (++i; i != e; ++i) {
3282 if (m >= 0 && m != s+i)
3288 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3289 /// the two vector operands have swapped position.
3290 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3291 unsigned NumElems) {
3292 for (unsigned i = 0; i != NumElems; ++i) {
3296 else if (idx < (int)NumElems)
3297 Mask[i] = idx + NumElems;
3299 Mask[i] = idx - NumElems;
3303 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3304 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3305 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3306 /// reverse of what x86 shuffles want.
3307 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3308 bool Commuted = false) {
3309 if (!HasAVX && VT.getSizeInBits() == 256)
3312 unsigned NumElems = VT.getVectorNumElements();
3313 unsigned NumLanes = VT.getSizeInBits()/128;
3314 unsigned NumLaneElems = NumElems/NumLanes;
3316 if (NumLaneElems != 2 && NumLaneElems != 4)
3319 // VSHUFPSY divides the resulting vector into 4 chunks.
3320 // The sources are also splitted into 4 chunks, and each destination
3321 // chunk must come from a different source chunk.
3323 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3324 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3326 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3327 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3329 // VSHUFPDY divides the resulting vector into 4 chunks.
3330 // The sources are also splitted into 4 chunks, and each destination
3331 // chunk must come from a different source chunk.
3333 // SRC1 => X3 X2 X1 X0
3334 // SRC2 => Y3 Y2 Y1 Y0
3336 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3338 unsigned HalfLaneElems = NumLaneElems/2;
3339 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3340 for (unsigned i = 0; i != NumLaneElems; ++i) {
3341 int Idx = Mask[i+l];
3342 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3343 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3345 // For VSHUFPSY, the mask of the second half must be the same as the
3346 // first but with the appropriate offsets. This works in the same way as
3347 // VPERMILPS works with masks.
3348 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3350 if (!isUndefOrEqual(Idx, Mask[i]+l))
3358 bool X86::isSHUFPMask(ShuffleVectorSDNode *N, bool HasAVX) {
3359 return ::isSHUFPMask(N->getMask(), N->getValueType(0), HasAVX);
3362 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3363 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3364 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3365 EVT VT = N->getValueType(0);
3366 unsigned NumElems = VT.getVectorNumElements();
3368 if (VT.getSizeInBits() != 128)
3374 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3375 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3376 isUndefOrEqual(N->getMaskElt(1), 7) &&
3377 isUndefOrEqual(N->getMaskElt(2), 2) &&
3378 isUndefOrEqual(N->getMaskElt(3), 3);
3381 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3382 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3384 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3385 EVT VT = N->getValueType(0);
3386 unsigned NumElems = VT.getVectorNumElements();
3388 if (VT.getSizeInBits() != 128)
3394 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3395 isUndefOrEqual(N->getMaskElt(1), 3) &&
3396 isUndefOrEqual(N->getMaskElt(2), 2) &&
3397 isUndefOrEqual(N->getMaskElt(3), 3);
3400 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3401 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3402 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3403 EVT VT = N->getValueType(0);
3405 if (VT.getSizeInBits() != 128)
3408 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3410 if (NumElems != 2 && NumElems != 4)
3413 for (unsigned i = 0; i < NumElems/2; ++i)
3414 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3417 for (unsigned i = NumElems/2; i < NumElems; ++i)
3418 if (!isUndefOrEqual(N->getMaskElt(i), i))
3424 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3425 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3426 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3427 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3429 if ((NumElems != 2 && NumElems != 4)
3430 || N->getValueType(0).getSizeInBits() > 128)
3433 for (unsigned i = 0; i < NumElems/2; ++i)
3434 if (!isUndefOrEqual(N->getMaskElt(i), i))
3437 for (unsigned i = 0; i < NumElems/2; ++i)
3438 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3444 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3445 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3446 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3447 bool HasAVX2, bool V2IsSplat = false) {
3448 unsigned NumElts = VT.getVectorNumElements();
3450 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3451 "Unsupported vector type for unpckh");
3453 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3454 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3457 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3458 // independently on 128-bit lanes.
3459 unsigned NumLanes = VT.getSizeInBits()/128;
3460 unsigned NumLaneElts = NumElts/NumLanes;
3462 for (unsigned l = 0; l != NumLanes; ++l) {
3463 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3464 i != (l+1)*NumLaneElts;
3467 int BitI1 = Mask[i+1];
3468 if (!isUndefOrEqual(BitI, j))
3471 if (!isUndefOrEqual(BitI1, NumElts))
3474 if (!isUndefOrEqual(BitI1, j + NumElts))
3483 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3484 return ::isUNPCKLMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat);
3487 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3488 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3489 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3490 bool HasAVX2, bool V2IsSplat = false) {
3491 unsigned NumElts = VT.getVectorNumElements();
3493 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3494 "Unsupported vector type for unpckh");
3496 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3497 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3500 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3501 // independently on 128-bit lanes.
3502 unsigned NumLanes = VT.getSizeInBits()/128;
3503 unsigned NumLaneElts = NumElts/NumLanes;
3505 for (unsigned l = 0; l != NumLanes; ++l) {
3506 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3507 i != (l+1)*NumLaneElts; i += 2, ++j) {
3509 int BitI1 = Mask[i+1];
3510 if (!isUndefOrEqual(BitI, j))
3513 if (isUndefOrEqual(BitI1, NumElts))
3516 if (!isUndefOrEqual(BitI1, j+NumElts))
3524 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool HasAVX2, bool V2IsSplat) {
3525 return ::isUNPCKHMask(N->getMask(), N->getValueType(0), HasAVX2, V2IsSplat);
3528 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3529 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3531 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3533 unsigned NumElts = VT.getVectorNumElements();
3535 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3536 "Unsupported vector type for unpckh");
3538 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3539 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3542 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3543 // FIXME: Need a better way to get rid of this, there's no latency difference
3544 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3545 // the former later. We should also remove the "_undef" special mask.
3546 if (NumElts == 4 && VT.getSizeInBits() == 256)
3549 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3550 // independently on 128-bit lanes.
3551 unsigned NumLanes = VT.getSizeInBits()/128;
3552 unsigned NumLaneElts = NumElts/NumLanes;
3554 for (unsigned l = 0; l != NumLanes; ++l) {
3555 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3556 i != (l+1)*NumLaneElts;
3559 int BitI1 = Mask[i+1];
3561 if (!isUndefOrEqual(BitI, j))
3563 if (!isUndefOrEqual(BitI1, j))
3571 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3572 return ::isUNPCKL_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2);
3575 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3576 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3578 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3579 unsigned NumElts = VT.getVectorNumElements();
3581 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3582 "Unsupported vector type for unpckh");
3584 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3585 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3588 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3589 // independently on 128-bit lanes.
3590 unsigned NumLanes = VT.getSizeInBits()/128;
3591 unsigned NumLaneElts = NumElts/NumLanes;
3593 for (unsigned l = 0; l != NumLanes; ++l) {
3594 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3595 i != (l+1)*NumLaneElts; i += 2, ++j) {
3597 int BitI1 = Mask[i+1];
3598 if (!isUndefOrEqual(BitI, j))
3600 if (!isUndefOrEqual(BitI1, j))
3607 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N, bool HasAVX2) {
3608 return ::isUNPCKH_v_undef_Mask(N->getMask(), N->getValueType(0), HasAVX2);
3611 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3612 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3613 /// MOVSD, and MOVD, i.e. setting the lowest element.
3614 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3615 if (VT.getVectorElementType().getSizeInBits() < 32)
3617 if (VT.getSizeInBits() == 256)
3620 unsigned NumElts = VT.getVectorNumElements();
3622 if (!isUndefOrEqual(Mask[0], NumElts))
3625 for (unsigned i = 1; i != NumElts; ++i)
3626 if (!isUndefOrEqual(Mask[i], i))
3632 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3633 return ::isMOVLMask(N->getMask(), N->getValueType(0));
3636 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3637 /// as permutations between 128-bit chunks or halves. As an example: this
3639 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3640 /// The first half comes from the second half of V1 and the second half from the
3641 /// the second half of V2.
3642 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3643 if (!HasAVX || VT.getSizeInBits() != 256)
3646 // The shuffle result is divided into half A and half B. In total the two
3647 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3648 // B must come from C, D, E or F.
3649 unsigned HalfSize = VT.getVectorNumElements()/2;
3650 bool MatchA = false, MatchB = false;
3652 // Check if A comes from one of C, D, E, F.
3653 for (unsigned Half = 0; Half != 4; ++Half) {
3654 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3660 // Check if B comes from one of C, D, E, F.
3661 for (unsigned Half = 0; Half != 4; ++Half) {
3662 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3668 return MatchA && MatchB;
3671 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3672 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3673 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3674 EVT VT = SVOp->getValueType(0);
3676 unsigned HalfSize = VT.getVectorNumElements()/2;
3678 unsigned FstHalf = 0, SndHalf = 0;
3679 for (unsigned i = 0; i < HalfSize; ++i) {
3680 if (SVOp->getMaskElt(i) > 0) {
3681 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3685 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3686 if (SVOp->getMaskElt(i) > 0) {
3687 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3692 return (FstHalf | (SndHalf << 4));
3695 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3696 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3697 /// Note that VPERMIL mask matching is different depending whether theunderlying
3698 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3699 /// to the same elements of the low, but to the higher half of the source.
3700 /// In VPERMILPD the two lanes could be shuffled independently of each other
3701 /// with the same restriction that lanes can't be crossed.
3702 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3706 unsigned NumElts = VT.getVectorNumElements();
3707 // Only match 256-bit with 32/64-bit types
3708 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3711 unsigned NumLanes = VT.getSizeInBits()/128;
3712 unsigned LaneSize = NumElts/NumLanes;
3713 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3714 for (unsigned i = 0; i != LaneSize; ++i) {
3715 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3717 if (NumElts != 8 || l == 0)
3719 // VPERMILPS handling
3722 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3730 /// getShuffleVPERMILPImmediate - Return the appropriate immediate to shuffle
3731 /// the specified VECTOR_MASK mask with VPERMILPS/D* instructions.
3732 static unsigned getShuffleVPERMILPImmediate(ShuffleVectorSDNode *SVOp) {
3733 EVT VT = SVOp->getValueType(0);
3735 unsigned NumElts = VT.getVectorNumElements();
3736 unsigned NumLanes = VT.getSizeInBits()/128;
3737 unsigned LaneSize = NumElts/NumLanes;
3739 // Although the mask is equal for both lanes do it twice to get the cases
3740 // where a mask will match because the same mask element is undef on the
3741 // first half but valid on the second. This would get pathological cases
3742 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3743 unsigned Shift = (LaneSize == 4) ? 2 : 1;
3745 for (unsigned i = 0; i != NumElts; ++i) {
3746 int MaskElt = SVOp->getMaskElt(i);
3749 MaskElt %= LaneSize;
3751 // VPERMILPSY, the mask of the first half must be equal to the second one
3752 if (NumElts == 8) Shamt %= LaneSize;
3753 Mask |= MaskElt << (Shamt*Shift);
3759 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3760 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3761 /// element of vector 2 and the other elements to come from vector 1 in order.
3762 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3763 bool V2IsSplat = false, bool V2IsUndef = false) {
3764 unsigned NumOps = VT.getVectorNumElements();
3765 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3768 if (!isUndefOrEqual(Mask[0], 0))
3771 for (unsigned i = 1; i != NumOps; ++i)
3772 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3773 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3774 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3780 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3781 bool V2IsUndef = false) {
3782 return isCommutedMOVLMask(N->getMask(), N->getValueType(0),
3783 V2IsSplat, V2IsUndef);
3786 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3787 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3788 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3789 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3790 const X86Subtarget *Subtarget) {
3791 if (!Subtarget->hasSSE3())
3794 // The second vector must be undef
3795 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3798 EVT VT = N->getValueType(0);
3799 unsigned NumElems = VT.getVectorNumElements();
3801 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3802 (VT.getSizeInBits() == 256 && NumElems != 8))
3805 // "i+1" is the value the indexed mask element must have
3806 for (unsigned i = 0; i < NumElems; i += 2)
3807 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3808 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3814 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3815 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3816 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3817 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3818 const X86Subtarget *Subtarget) {
3819 if (!Subtarget->hasSSE3())
3822 // The second vector must be undef
3823 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3826 EVT VT = N->getValueType(0);
3827 unsigned NumElems = VT.getVectorNumElements();
3829 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3830 (VT.getSizeInBits() == 256 && NumElems != 8))
3833 // "i" is the value the indexed mask element must have
3834 for (unsigned i = 0; i != NumElems; i += 2)
3835 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3836 !isUndefOrEqual(N->getMaskElt(i+1), i))
3842 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3843 /// specifies a shuffle of elements that is suitable for input to 256-bit
3844 /// version of MOVDDUP.
3845 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3846 unsigned NumElts = VT.getVectorNumElements();
3848 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3851 for (unsigned i = 0; i != NumElts/2; ++i)
3852 if (!isUndefOrEqual(Mask[i], 0))
3854 for (unsigned i = NumElts/2; i != NumElts; ++i)
3855 if (!isUndefOrEqual(Mask[i], NumElts/2))
3860 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3861 /// specifies a shuffle of elements that is suitable for input to 128-bit
3862 /// version of MOVDDUP.
3863 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3864 EVT VT = N->getValueType(0);
3866 if (VT.getSizeInBits() != 128)
3869 unsigned e = VT.getVectorNumElements() / 2;
3870 for (unsigned i = 0; i != e; ++i)
3871 if (!isUndefOrEqual(N->getMaskElt(i), i))
3873 for (unsigned i = 0; i != e; ++i)
3874 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3879 /// isVEXTRACTF128Index - Return true if the specified
3880 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3881 /// suitable for input to VEXTRACTF128.
3882 bool X86::isVEXTRACTF128Index(SDNode *N) {
3883 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3886 // The index should be aligned on a 128-bit boundary.
3888 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3890 unsigned VL = N->getValueType(0).getVectorNumElements();
3891 unsigned VBits = N->getValueType(0).getSizeInBits();
3892 unsigned ElSize = VBits / VL;
3893 bool Result = (Index * ElSize) % 128 == 0;
3898 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3899 /// operand specifies a subvector insert that is suitable for input to
3901 bool X86::isVINSERTF128Index(SDNode *N) {
3902 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3905 // The index should be aligned on a 128-bit boundary.
3907 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3909 unsigned VL = N->getValueType(0).getVectorNumElements();
3910 unsigned VBits = N->getValueType(0).getSizeInBits();
3911 unsigned ElSize = VBits / VL;
3912 bool Result = (Index * ElSize) % 128 == 0;
3917 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3918 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3919 /// Handles 128-bit and 256-bit.
3920 unsigned X86::getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3921 EVT VT = N->getValueType(0);
3923 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3924 "Unsupported vector type for PSHUF/SHUFP");
3926 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3927 // independently on 128-bit lanes.
3928 unsigned NumElts = VT.getVectorNumElements();
3929 unsigned NumLanes = VT.getSizeInBits()/128;
3930 unsigned NumLaneElts = NumElts/NumLanes;
3932 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3933 "Only supports 2 or 4 elements per lane");
3935 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3937 for (unsigned i = 0; i != NumElts; ++i) {
3938 int Elt = N->getMaskElt(i);
3939 if (Elt < 0) continue;
3941 unsigned ShAmt = i << Shift;
3942 if (ShAmt >= 8) ShAmt -= 8;
3943 Mask |= Elt << ShAmt;
3949 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3950 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3951 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3952 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3954 // 8 nodes, but we only care about the last 4.
3955 for (unsigned i = 7; i >= 4; --i) {
3956 int Val = SVOp->getMaskElt(i);
3965 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3966 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3967 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3968 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3970 // 8 nodes, but we only care about the first 4.
3971 for (int i = 3; i >= 0; --i) {
3972 int Val = SVOp->getMaskElt(i);
3981 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3982 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3983 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3984 EVT VT = SVOp->getValueType(0);
3985 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3989 for (i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
3990 Val = SVOp->getMaskElt(i);
3994 assert(Val - i > 0 && "PALIGNR imm should be positive");
3995 return (Val - i) * EltSize;
3998 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3999 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4001 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4002 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4003 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4006 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4008 EVT VecVT = N->getOperand(0).getValueType();
4009 EVT ElVT = VecVT.getVectorElementType();
4011 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4012 return Index / NumElemsPerChunk;
4015 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4016 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4018 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4019 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4020 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4023 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4025 EVT VecVT = N->getValueType(0);
4026 EVT ElVT = VecVT.getVectorElementType();
4028 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4029 return Index / NumElemsPerChunk;
4032 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4034 bool X86::isZeroNode(SDValue Elt) {
4035 return ((isa<ConstantSDNode>(Elt) &&
4036 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4037 (isa<ConstantFPSDNode>(Elt) &&
4038 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4041 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4042 /// their permute mask.
4043 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4044 SelectionDAG &DAG) {
4045 EVT VT = SVOp->getValueType(0);
4046 unsigned NumElems = VT.getVectorNumElements();
4047 SmallVector<int, 8> MaskVec;
4049 for (unsigned i = 0; i != NumElems; ++i) {
4050 int idx = SVOp->getMaskElt(i);
4052 MaskVec.push_back(idx);
4053 else if (idx < (int)NumElems)
4054 MaskVec.push_back(idx + NumElems);
4056 MaskVec.push_back(idx - NumElems);
4058 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4059 SVOp->getOperand(0), &MaskVec[0]);
4062 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4063 /// match movhlps. The lower half elements should come from upper half of
4064 /// V1 (and in order), and the upper half elements should come from the upper
4065 /// half of V2 (and in order).
4066 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4067 EVT VT = Op->getValueType(0);
4068 if (VT.getSizeInBits() != 128)
4070 if (VT.getVectorNumElements() != 4)
4072 for (unsigned i = 0, e = 2; i != e; ++i)
4073 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4075 for (unsigned i = 2; i != 4; ++i)
4076 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4081 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4082 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4084 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4085 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4087 N = N->getOperand(0).getNode();
4088 if (!ISD::isNON_EXTLoad(N))
4091 *LD = cast<LoadSDNode>(N);
4095 // Test whether the given value is a vector value which will be legalized
4097 static bool WillBeConstantPoolLoad(SDNode *N) {
4098 if (N->getOpcode() != ISD::BUILD_VECTOR)
4101 // Check for any non-constant elements.
4102 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4103 switch (N->getOperand(i).getNode()->getOpcode()) {
4105 case ISD::ConstantFP:
4112 // Vectors of all-zeros and all-ones are materialized with special
4113 // instructions rather than being loaded.
4114 return !ISD::isBuildVectorAllZeros(N) &&
4115 !ISD::isBuildVectorAllOnes(N);
4118 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4119 /// match movlp{s|d}. The lower half elements should come from lower half of
4120 /// V1 (and in order), and the upper half elements should come from the upper
4121 /// half of V2 (and in order). And since V1 will become the source of the
4122 /// MOVLP, it must be either a vector load or a scalar load to vector.
4123 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4124 ShuffleVectorSDNode *Op) {
4125 EVT VT = Op->getValueType(0);
4126 if (VT.getSizeInBits() != 128)
4129 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4131 // Is V2 is a vector load, don't do this transformation. We will try to use
4132 // load folding shufps op.
4133 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4136 unsigned NumElems = VT.getVectorNumElements();
4138 if (NumElems != 2 && NumElems != 4)
4140 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4141 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4143 for (unsigned i = NumElems/2; i != NumElems; ++i)
4144 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4149 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4151 static bool isSplatVector(SDNode *N) {
4152 if (N->getOpcode() != ISD::BUILD_VECTOR)
4155 SDValue SplatValue = N->getOperand(0);
4156 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4157 if (N->getOperand(i) != SplatValue)
4162 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4163 /// to an zero vector.
4164 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4165 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4166 SDValue V1 = N->getOperand(0);
4167 SDValue V2 = N->getOperand(1);
4168 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4169 for (unsigned i = 0; i != NumElems; ++i) {
4170 int Idx = N->getMaskElt(i);
4171 if (Idx >= (int)NumElems) {
4172 unsigned Opc = V2.getOpcode();
4173 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4175 if (Opc != ISD::BUILD_VECTOR ||
4176 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4178 } else if (Idx >= 0) {
4179 unsigned Opc = V1.getOpcode();
4180 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4182 if (Opc != ISD::BUILD_VECTOR ||
4183 !X86::isZeroNode(V1.getOperand(Idx)))
4190 /// getZeroVector - Returns a vector of specified type with all zero elements.
4192 static SDValue getZeroVector(EVT VT, bool HasSSE2, bool HasAVX2,
4193 SelectionDAG &DAG, DebugLoc dl) {
4194 assert(VT.isVector() && "Expected a vector type");
4196 // Always build SSE zero vectors as <4 x i32> bitcasted
4197 // to their dest type. This ensures they get CSE'd.
4199 if (VT.getSizeInBits() == 128) { // SSE
4200 if (HasSSE2) { // SSE2
4201 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4202 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4204 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4205 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4207 } else if (VT.getSizeInBits() == 256) { // AVX
4208 if (HasAVX2) { // AVX2
4209 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4210 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4211 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4213 // 256-bit logic and arithmetic instructions in AVX are all
4214 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4215 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4216 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4217 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4220 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4223 /// getOnesVector - Returns a vector of specified type with all bits set.
4224 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4225 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4226 /// Then bitcast to their original type, ensuring they get CSE'd.
4227 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4229 assert(VT.isVector() && "Expected a vector type");
4230 assert((VT.is128BitVector() || VT.is256BitVector())
4231 && "Expected a 128-bit or 256-bit vector type");
4233 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4235 if (VT.getSizeInBits() == 256) {
4236 if (HasAVX2) { // AVX2
4237 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4238 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4240 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4241 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4242 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4243 Vec = Insert128BitVector(InsV, Vec,
4244 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4247 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4250 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4253 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4254 /// that point to V2 points to its first element.
4255 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4256 EVT VT = SVOp->getValueType(0);
4257 unsigned NumElems = VT.getVectorNumElements();
4259 bool Changed = false;
4260 SmallVector<int, 8> MaskVec(SVOp->getMask().begin(), SVOp->getMask().end());
4262 for (unsigned i = 0; i != NumElems; ++i) {
4263 if (MaskVec[i] > (int)NumElems) {
4264 MaskVec[i] = NumElems;
4269 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4270 SVOp->getOperand(1), &MaskVec[0]);
4271 return SDValue(SVOp, 0);
4274 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4275 /// operation of specified width.
4276 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4278 unsigned NumElems = VT.getVectorNumElements();
4279 SmallVector<int, 8> Mask;
4280 Mask.push_back(NumElems);
4281 for (unsigned i = 1; i != NumElems; ++i)
4283 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4286 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4287 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4289 unsigned NumElems = VT.getVectorNumElements();
4290 SmallVector<int, 8> Mask;
4291 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4293 Mask.push_back(i + NumElems);
4295 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4298 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4299 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4301 unsigned NumElems = VT.getVectorNumElements();
4302 unsigned Half = NumElems/2;
4303 SmallVector<int, 8> Mask;
4304 for (unsigned i = 0; i != Half; ++i) {
4305 Mask.push_back(i + Half);
4306 Mask.push_back(i + NumElems + Half);
4308 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4311 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4312 // a generic shuffle instruction because the target has no such instructions.
4313 // Generate shuffles which repeat i16 and i8 several times until they can be
4314 // represented by v4f32 and then be manipulated by target suported shuffles.
4315 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4316 EVT VT = V.getValueType();
4317 int NumElems = VT.getVectorNumElements();
4318 DebugLoc dl = V.getDebugLoc();
4320 while (NumElems > 4) {
4321 if (EltNo < NumElems/2) {
4322 V = getUnpackl(DAG, dl, VT, V, V);
4324 V = getUnpackh(DAG, dl, VT, V, V);
4325 EltNo -= NumElems/2;
4332 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4333 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4334 EVT VT = V.getValueType();
4335 DebugLoc dl = V.getDebugLoc();
4336 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4337 && "Vector size not supported");
4339 if (VT.getSizeInBits() == 128) {
4340 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4341 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4342 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4345 // To use VPERMILPS to splat scalars, the second half of indicies must
4346 // refer to the higher part, which is a duplication of the lower one,
4347 // because VPERMILPS can only handle in-lane permutations.
4348 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4349 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4351 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4352 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4356 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4359 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4360 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4361 EVT SrcVT = SV->getValueType(0);
4362 SDValue V1 = SV->getOperand(0);
4363 DebugLoc dl = SV->getDebugLoc();
4365 int EltNo = SV->getSplatIndex();
4366 int NumElems = SrcVT.getVectorNumElements();
4367 unsigned Size = SrcVT.getSizeInBits();
4369 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4370 "Unknown how to promote splat for type");
4372 // Extract the 128-bit part containing the splat element and update
4373 // the splat element index when it refers to the higher register.
4375 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4376 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4378 EltNo -= NumElems/2;
4381 // All i16 and i8 vector types can't be used directly by a generic shuffle
4382 // instruction because the target has no such instruction. Generate shuffles
4383 // which repeat i16 and i8 several times until they fit in i32, and then can
4384 // be manipulated by target suported shuffles.
4385 EVT EltVT = SrcVT.getVectorElementType();
4386 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4387 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4389 // Recreate the 256-bit vector and place the same 128-bit vector
4390 // into the low and high part. This is necessary because we want
4391 // to use VPERM* to shuffle the vectors
4393 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4394 DAG.getConstant(0, MVT::i32), DAG, dl);
4395 V1 = Insert128BitVector(InsV, V1,
4396 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4399 return getLegalSplat(DAG, V1, EltNo);
4402 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4403 /// vector of zero or undef vector. This produces a shuffle where the low
4404 /// element of V2 is swizzled into the zero/undef vector, landing at element
4405 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4406 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4408 const X86Subtarget *Subtarget,
4409 SelectionDAG &DAG) {
4410 EVT VT = V2.getValueType();
4412 ? getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(), DAG,
4413 V2.getDebugLoc()) : DAG.getUNDEF(VT);
4414 unsigned NumElems = VT.getVectorNumElements();
4415 SmallVector<int, 16> MaskVec;
4416 for (unsigned i = 0; i != NumElems; ++i)
4417 // If this is the insertion idx, put the low elt of V2 here.
4418 MaskVec.push_back(i == Idx ? NumElems : i);
4419 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4422 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4423 /// element of the result of the vector shuffle.
4424 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4427 return SDValue(); // Limit search depth.
4429 SDValue V = SDValue(N, 0);
4430 EVT VT = V.getValueType();
4431 unsigned Opcode = V.getOpcode();
4433 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4434 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4435 Index = SV->getMaskElt(Index);
4438 return DAG.getUNDEF(VT.getVectorElementType());
4440 int NumElems = VT.getVectorNumElements();
4441 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4442 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4445 // Recurse into target specific vector shuffles to find scalars.
4446 if (isTargetShuffle(Opcode)) {
4447 int NumElems = VT.getVectorNumElements();
4448 SmallVector<unsigned, 16> ShuffleMask;
4453 ImmN = N->getOperand(N->getNumOperands()-1);
4454 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4457 case X86ISD::UNPCKH:
4458 DecodeUNPCKHMask(VT, ShuffleMask);
4460 case X86ISD::UNPCKL:
4461 DecodeUNPCKLMask(VT, ShuffleMask);
4463 case X86ISD::MOVHLPS:
4464 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4466 case X86ISD::MOVLHPS:
4467 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4469 case X86ISD::PSHUFD:
4470 ImmN = N->getOperand(N->getNumOperands()-1);
4471 DecodePSHUFMask(NumElems,
4472 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4475 case X86ISD::PSHUFHW:
4476 ImmN = N->getOperand(N->getNumOperands()-1);
4477 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4480 case X86ISD::PSHUFLW:
4481 ImmN = N->getOperand(N->getNumOperands()-1);
4482 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4486 case X86ISD::MOVSD: {
4487 // The index 0 always comes from the first element of the second source,
4488 // this is why MOVSS and MOVSD are used in the first place. The other
4489 // elements come from the other positions of the first source vector.
4490 unsigned OpNum = (Index == 0) ? 1 : 0;
4491 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4494 case X86ISD::VPERMILP:
4495 ImmN = N->getOperand(N->getNumOperands()-1);
4496 DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4499 case X86ISD::VPERM2X128:
4500 ImmN = N->getOperand(N->getNumOperands()-1);
4501 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4504 case X86ISD::MOVDDUP:
4505 case X86ISD::MOVLHPD:
4506 case X86ISD::MOVLPD:
4507 case X86ISD::MOVLPS:
4508 case X86ISD::MOVSHDUP:
4509 case X86ISD::MOVSLDUP:
4510 case X86ISD::PALIGN:
4511 return SDValue(); // Not yet implemented.
4513 assert(0 && "unknown target shuffle node");
4517 Index = ShuffleMask[Index];
4519 return DAG.getUNDEF(VT.getVectorElementType());
4521 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4522 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4526 // Actual nodes that may contain scalar elements
4527 if (Opcode == ISD::BITCAST) {
4528 V = V.getOperand(0);
4529 EVT SrcVT = V.getValueType();
4530 unsigned NumElems = VT.getVectorNumElements();
4532 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4536 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4537 return (Index == 0) ? V.getOperand(0)
4538 : DAG.getUNDEF(VT.getVectorElementType());
4540 if (V.getOpcode() == ISD::BUILD_VECTOR)
4541 return V.getOperand(Index);
4546 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4547 /// shuffle operation which come from a consecutively from a zero. The
4548 /// search can start in two different directions, from left or right.
4550 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4551 bool ZerosFromLeft, SelectionDAG &DAG) {
4554 while (i < NumElems) {
4555 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4556 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4557 if (!(Elt.getNode() &&
4558 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4566 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4567 /// MaskE correspond consecutively to elements from one of the vector operands,
4568 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4570 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4571 int OpIdx, int NumElems, unsigned &OpNum) {
4572 bool SeenV1 = false;
4573 bool SeenV2 = false;
4575 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4576 int Idx = SVOp->getMaskElt(i);
4577 // Ignore undef indicies
4586 // Only accept consecutive elements from the same vector
4587 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4591 OpNum = SeenV1 ? 0 : 1;
4595 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4596 /// logical left shift of a vector.
4597 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4598 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4599 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4600 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4601 false /* check zeros from right */, DAG);
4607 // Considering the elements in the mask that are not consecutive zeros,
4608 // check if they consecutively come from only one of the source vectors.
4610 // V1 = {X, A, B, C} 0
4612 // vector_shuffle V1, V2 <1, 2, 3, X>
4614 if (!isShuffleMaskConsecutive(SVOp,
4615 0, // Mask Start Index
4616 NumElems-NumZeros-1, // Mask End Index
4617 NumZeros, // Where to start looking in the src vector
4618 NumElems, // Number of elements in vector
4619 OpSrc)) // Which source operand ?
4624 ShVal = SVOp->getOperand(OpSrc);
4628 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4629 /// logical left shift of a vector.
4630 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4631 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4632 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4633 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4634 true /* check zeros from left */, DAG);
4640 // Considering the elements in the mask that are not consecutive zeros,
4641 // check if they consecutively come from only one of the source vectors.
4643 // 0 { A, B, X, X } = V2
4645 // vector_shuffle V1, V2 <X, X, 4, 5>
4647 if (!isShuffleMaskConsecutive(SVOp,
4648 NumZeros, // Mask Start Index
4649 NumElems-1, // Mask End Index
4650 0, // Where to start looking in the src vector
4651 NumElems, // Number of elements in vector
4652 OpSrc)) // Which source operand ?
4657 ShVal = SVOp->getOperand(OpSrc);
4661 /// isVectorShift - Returns true if the shuffle can be implemented as a
4662 /// logical left or right shift of a vector.
4663 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4664 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4665 // Although the logic below support any bitwidth size, there are no
4666 // shift instructions which handle more than 128-bit vectors.
4667 if (SVOp->getValueType(0).getSizeInBits() > 128)
4670 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4671 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4677 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4679 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4680 unsigned NumNonZero, unsigned NumZero,
4682 const TargetLowering &TLI) {
4686 DebugLoc dl = Op.getDebugLoc();
4689 for (unsigned i = 0; i < 16; ++i) {
4690 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4691 if (ThisIsNonZero && First) {
4693 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false,
4696 V = DAG.getUNDEF(MVT::v8i16);
4701 SDValue ThisElt(0, 0), LastElt(0, 0);
4702 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4703 if (LastIsNonZero) {
4704 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4705 MVT::i16, Op.getOperand(i-1));
4707 if (ThisIsNonZero) {
4708 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4709 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4710 ThisElt, DAG.getConstant(8, MVT::i8));
4712 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4716 if (ThisElt.getNode())
4717 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4718 DAG.getIntPtrConstant(i/2));
4722 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4725 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4727 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4728 unsigned NumNonZero, unsigned NumZero,
4730 const TargetLowering &TLI) {
4734 DebugLoc dl = Op.getDebugLoc();
4737 for (unsigned i = 0; i < 8; ++i) {
4738 bool isNonZero = (NonZeros & (1 << i)) != 0;
4742 V = getZeroVector(MVT::v8i16, /*HasSSE2*/ true, /*HasAVX2*/ false,
4745 V = DAG.getUNDEF(MVT::v8i16);
4748 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4749 MVT::v8i16, V, Op.getOperand(i),
4750 DAG.getIntPtrConstant(i));
4757 /// getVShift - Return a vector logical shift node.
4759 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4760 unsigned NumBits, SelectionDAG &DAG,
4761 const TargetLowering &TLI, DebugLoc dl) {
4762 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4763 EVT ShVT = MVT::v2i64;
4764 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4765 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4766 return DAG.getNode(ISD::BITCAST, dl, VT,
4767 DAG.getNode(Opc, dl, ShVT, SrcOp,
4768 DAG.getConstant(NumBits,
4769 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4773 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4774 SelectionDAG &DAG) const {
4776 // Check if the scalar load can be widened into a vector load. And if
4777 // the address is "base + cst" see if the cst can be "absorbed" into
4778 // the shuffle mask.
4779 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4780 SDValue Ptr = LD->getBasePtr();
4781 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4783 EVT PVT = LD->getValueType(0);
4784 if (PVT != MVT::i32 && PVT != MVT::f32)
4789 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4790 FI = FINode->getIndex();
4792 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4793 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4794 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4795 Offset = Ptr.getConstantOperandVal(1);
4796 Ptr = Ptr.getOperand(0);
4801 // FIXME: 256-bit vector instructions don't require a strict alignment,
4802 // improve this code to support it better.
4803 unsigned RequiredAlign = VT.getSizeInBits()/8;
4804 SDValue Chain = LD->getChain();
4805 // Make sure the stack object alignment is at least 16 or 32.
4806 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4807 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4808 if (MFI->isFixedObjectIndex(FI)) {
4809 // Can't change the alignment. FIXME: It's possible to compute
4810 // the exact stack offset and reference FI + adjust offset instead.
4811 // If someone *really* cares about this. That's the way to implement it.
4814 MFI->setObjectAlignment(FI, RequiredAlign);
4818 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4819 // Ptr + (Offset & ~15).
4822 if ((Offset % RequiredAlign) & 3)
4824 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4826 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4827 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4829 int EltNo = (Offset - StartOffset) >> 2;
4830 int NumElems = VT.getVectorNumElements();
4832 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4833 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4834 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4835 LD->getPointerInfo().getWithOffset(StartOffset),
4836 false, false, false, 0);
4838 // Canonicalize it to a v4i32 or v8i32 shuffle.
4839 SmallVector<int, 8> Mask;
4840 for (int i = 0; i < NumElems; ++i)
4841 Mask.push_back(EltNo);
4843 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4844 return DAG.getNode(ISD::BITCAST, dl, NVT,
4845 DAG.getVectorShuffle(CanonVT, dl, V1,
4846 DAG.getUNDEF(CanonVT),&Mask[0]));
4852 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4853 /// vector of type 'VT', see if the elements can be replaced by a single large
4854 /// load which has the same value as a build_vector whose operands are 'elts'.
4856 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4858 /// FIXME: we'd also like to handle the case where the last elements are zero
4859 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4860 /// There's even a handy isZeroNode for that purpose.
4861 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4862 DebugLoc &DL, SelectionDAG &DAG) {
4863 EVT EltVT = VT.getVectorElementType();
4864 unsigned NumElems = Elts.size();
4866 LoadSDNode *LDBase = NULL;
4867 unsigned LastLoadedElt = -1U;
4869 // For each element in the initializer, see if we've found a load or an undef.
4870 // If we don't find an initial load element, or later load elements are
4871 // non-consecutive, bail out.
4872 for (unsigned i = 0; i < NumElems; ++i) {
4873 SDValue Elt = Elts[i];
4875 if (!Elt.getNode() ||
4876 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4879 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4881 LDBase = cast<LoadSDNode>(Elt.getNode());
4885 if (Elt.getOpcode() == ISD::UNDEF)
4888 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4889 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4894 // If we have found an entire vector of loads and undefs, then return a large
4895 // load of the entire vector width starting at the base pointer. If we found
4896 // consecutive loads for the low half, generate a vzext_load node.
4897 if (LastLoadedElt == NumElems - 1) {
4898 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4899 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4900 LDBase->getPointerInfo(),
4901 LDBase->isVolatile(), LDBase->isNonTemporal(),
4902 LDBase->isInvariant(), 0);
4903 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4904 LDBase->getPointerInfo(),
4905 LDBase->isVolatile(), LDBase->isNonTemporal(),
4906 LDBase->isInvariant(), LDBase->getAlignment());
4907 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4908 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4909 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4910 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4912 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4913 LDBase->getPointerInfo(),
4914 LDBase->getAlignment(),
4915 false/*isVolatile*/, true/*ReadMem*/,
4917 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4922 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4923 /// a vbroadcast node. We support two patterns:
4924 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4925 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4927 /// The scalar load node is returned when a pattern is found,
4928 /// or SDValue() otherwise.
4929 static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) {
4930 if (!Subtarget->hasAVX())
4933 EVT VT = Op.getValueType();
4936 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4937 V = V.getOperand(0);
4939 //A suspected load to be broadcasted.
4942 switch (V.getOpcode()) {
4944 // Unknown pattern found.
4947 case ISD::BUILD_VECTOR: {
4948 // The BUILD_VECTOR node must be a splat.
4949 if (!isSplatVector(V.getNode()))
4952 Ld = V.getOperand(0);
4954 // The suspected load node has several users. Make sure that all
4955 // of its users are from the BUILD_VECTOR node.
4956 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4961 case ISD::VECTOR_SHUFFLE: {
4962 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4964 // Shuffles must have a splat mask where the first element is
4966 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4969 SDValue Sc = Op.getOperand(0);
4970 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4973 Ld = Sc.getOperand(0);
4975 // The scalar_to_vector node and the suspected
4976 // load node must have exactly one user.
4977 if (!Sc.hasOneUse() || !Ld.hasOneUse())
4983 // The scalar source must be a normal load.
4984 if (!ISD::isNormalLoad(Ld.getNode()))
4987 bool Is256 = VT.getSizeInBits() == 256;
4988 bool Is128 = VT.getSizeInBits() == 128;
4989 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4991 // VBroadcast to YMM
4992 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
4995 // VBroadcast to XMM
4996 if (Is128 && (ScalarSize == 32))
4999 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5000 // double since there is vbroadcastsd xmm
5001 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5002 // VBroadcast to YMM
5003 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
5006 // VBroadcast to XMM
5007 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
5011 // Unsupported broadcast.
5016 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5017 DebugLoc dl = Op.getDebugLoc();
5019 EVT VT = Op.getValueType();
5020 EVT ExtVT = VT.getVectorElementType();
5021 unsigned NumElems = Op.getNumOperands();
5023 // Vectors containing all zeros can be matched by pxor and xorps later
5024 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5025 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5026 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5027 if (Op.getValueType() == MVT::v4i32 ||
5028 Op.getValueType() == MVT::v8i32)
5031 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(),
5032 Subtarget->hasAVX2(), DAG, dl);
5035 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5036 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5037 // vpcmpeqd on 256-bit vectors.
5038 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5039 if (Op.getValueType() == MVT::v4i32 ||
5040 (Op.getValueType() == MVT::v8i32 && Subtarget->hasAVX2()))
5043 return getOnesVector(Op.getValueType(), Subtarget->hasAVX2(), DAG, dl);
5046 SDValue LD = isVectorBroadcast(Op, Subtarget);
5048 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
5050 unsigned EVTBits = ExtVT.getSizeInBits();
5052 unsigned NumZero = 0;
5053 unsigned NumNonZero = 0;
5054 unsigned NonZeros = 0;
5055 bool IsAllConstants = true;
5056 SmallSet<SDValue, 8> Values;
5057 for (unsigned i = 0; i < NumElems; ++i) {
5058 SDValue Elt = Op.getOperand(i);
5059 if (Elt.getOpcode() == ISD::UNDEF)
5062 if (Elt.getOpcode() != ISD::Constant &&
5063 Elt.getOpcode() != ISD::ConstantFP)
5064 IsAllConstants = false;
5065 if (X86::isZeroNode(Elt))
5068 NonZeros |= (1 << i);
5073 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5074 if (NumNonZero == 0)
5075 return DAG.getUNDEF(VT);
5077 // Special case for single non-zero, non-undef, element.
5078 if (NumNonZero == 1) {
5079 unsigned Idx = CountTrailingZeros_32(NonZeros);
5080 SDValue Item = Op.getOperand(Idx);
5082 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5083 // the value are obviously zero, truncate the value to i32 and do the
5084 // insertion that way. Only do this if the value is non-constant or if the
5085 // value is a constant being inserted into element 0. It is cheaper to do
5086 // a constant pool load than it is to do a movd + shuffle.
5087 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5088 (!IsAllConstants || Idx == 0)) {
5089 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5091 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5092 EVT VecVT = MVT::v4i32;
5093 unsigned VecElts = 4;
5095 // Truncate the value (which may itself be a constant) to i32, and
5096 // convert it to a vector with movd (S2V+shuffle to zero extend).
5097 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5098 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5099 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5101 // Now we have our 32-bit value zero extended in the low element of
5102 // a vector. If Idx != 0, swizzle it into place.
5104 SmallVector<int, 4> Mask;
5105 Mask.push_back(Idx);
5106 for (unsigned i = 1; i != VecElts; ++i)
5108 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5109 DAG.getUNDEF(Item.getValueType()),
5112 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5116 // If we have a constant or non-constant insertion into the low element of
5117 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5118 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5119 // depending on what the source datatype is.
5122 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5124 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5125 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5126 if (VT.getSizeInBits() == 256) {
5127 SDValue ZeroVec = getZeroVector(VT, Subtarget->hasSSE2(),
5128 Subtarget->hasAVX2(), DAG, dl);
5129 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5130 Item, DAG.getIntPtrConstant(0));
5132 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5133 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5134 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5135 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5138 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5139 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5140 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5141 if (VT.getSizeInBits() == 256) {
5142 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget->hasSSE2(),
5143 Subtarget->hasAVX2(), DAG, dl);
5144 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5147 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5148 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5150 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5154 // Is it a vector logical left shift?
5155 if (NumElems == 2 && Idx == 1 &&
5156 X86::isZeroNode(Op.getOperand(0)) &&
5157 !X86::isZeroNode(Op.getOperand(1))) {
5158 unsigned NumBits = VT.getSizeInBits();
5159 return getVShift(true, VT,
5160 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5161 VT, Op.getOperand(1)),
5162 NumBits/2, DAG, *this, dl);
5165 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5168 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5169 // is a non-constant being inserted into an element other than the low one,
5170 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5171 // movd/movss) to move this into the low element, then shuffle it into
5173 if (EVTBits == 32) {
5174 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5176 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5177 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5178 SmallVector<int, 8> MaskVec;
5179 for (unsigned i = 0; i < NumElems; i++)
5180 MaskVec.push_back(i == Idx ? 0 : 1);
5181 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5185 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5186 if (Values.size() == 1) {
5187 if (EVTBits == 32) {
5188 // Instead of a shuffle like this:
5189 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5190 // Check if it's possible to issue this instead.
5191 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5192 unsigned Idx = CountTrailingZeros_32(NonZeros);
5193 SDValue Item = Op.getOperand(Idx);
5194 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5195 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5200 // A vector full of immediates; various special cases are already
5201 // handled, so this is best done with a single constant-pool load.
5205 // For AVX-length vectors, build the individual 128-bit pieces and use
5206 // shuffles to put them in place.
5207 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5208 SmallVector<SDValue, 32> V;
5209 for (unsigned i = 0; i < NumElems; ++i)
5210 V.push_back(Op.getOperand(i));
5212 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5214 // Build both the lower and upper subvector.
5215 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5216 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5219 // Recreate the wider vector with the lower and upper part.
5220 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5221 DAG.getConstant(0, MVT::i32), DAG, dl);
5222 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5226 // Let legalizer expand 2-wide build_vectors.
5227 if (EVTBits == 64) {
5228 if (NumNonZero == 1) {
5229 // One half is zero or undef.
5230 unsigned Idx = CountTrailingZeros_32(NonZeros);
5231 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5232 Op.getOperand(Idx));
5233 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5238 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5239 if (EVTBits == 8 && NumElems == 16) {
5240 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5242 if (V.getNode()) return V;
5245 if (EVTBits == 16 && NumElems == 8) {
5246 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5248 if (V.getNode()) return V;
5251 // If element VT is == 32 bits, turn it into a number of shuffles.
5252 SmallVector<SDValue, 8> V;
5254 if (NumElems == 4 && NumZero > 0) {
5255 for (unsigned i = 0; i < 4; ++i) {
5256 bool isZero = !(NonZeros & (1 << i));
5258 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
5261 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5264 for (unsigned i = 0; i < 2; ++i) {
5265 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5268 V[i] = V[i*2]; // Must be a zero vector.
5271 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5274 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5277 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5282 SmallVector<int, 8> MaskVec;
5283 bool Reverse = (NonZeros & 0x3) == 2;
5284 for (unsigned i = 0; i < 2; ++i)
5285 MaskVec.push_back(Reverse ? 1-i : i);
5286 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5287 for (unsigned i = 0; i < 2; ++i)
5288 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5289 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5292 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5293 // Check for a build vector of consecutive loads.
5294 for (unsigned i = 0; i < NumElems; ++i)
5295 V[i] = Op.getOperand(i);
5297 // Check for elements which are consecutive loads.
5298 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5302 // For SSE 4.1, use insertps to put the high elements into the low element.
5303 if (getSubtarget()->hasSSE41()) {
5305 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5306 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5308 Result = DAG.getUNDEF(VT);
5310 for (unsigned i = 1; i < NumElems; ++i) {
5311 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5312 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5313 Op.getOperand(i), DAG.getIntPtrConstant(i));
5318 // Otherwise, expand into a number of unpckl*, start by extending each of
5319 // our (non-undef) elements to the full vector width with the element in the
5320 // bottom slot of the vector (which generates no code for SSE).
5321 for (unsigned i = 0; i < NumElems; ++i) {
5322 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5323 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5325 V[i] = DAG.getUNDEF(VT);
5328 // Next, we iteratively mix elements, e.g. for v4f32:
5329 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5330 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5331 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5332 unsigned EltStride = NumElems >> 1;
5333 while (EltStride != 0) {
5334 for (unsigned i = 0; i < EltStride; ++i) {
5335 // If V[i+EltStride] is undef and this is the first round of mixing,
5336 // then it is safe to just drop this shuffle: V[i] is already in the
5337 // right place, the one element (since it's the first round) being
5338 // inserted as undef can be dropped. This isn't safe for successive
5339 // rounds because they will permute elements within both vectors.
5340 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5341 EltStride == NumElems/2)
5344 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5353 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5354 // them in a MMX register. This is better than doing a stack convert.
5355 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5356 DebugLoc dl = Op.getDebugLoc();
5357 EVT ResVT = Op.getValueType();
5359 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5360 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5362 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5363 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5364 InVec = Op.getOperand(1);
5365 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5366 unsigned NumElts = ResVT.getVectorNumElements();
5367 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5368 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5369 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5371 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5372 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5373 Mask[0] = 0; Mask[1] = 2;
5374 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5376 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5379 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5380 // to create 256-bit vectors from two other 128-bit ones.
5381 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5382 DebugLoc dl = Op.getDebugLoc();
5383 EVT ResVT = Op.getValueType();
5385 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5387 SDValue V1 = Op.getOperand(0);
5388 SDValue V2 = Op.getOperand(1);
5389 unsigned NumElems = ResVT.getVectorNumElements();
5391 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5392 DAG.getConstant(0, MVT::i32), DAG, dl);
5393 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5398 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5399 EVT ResVT = Op.getValueType();
5401 assert(Op.getNumOperands() == 2);
5402 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5403 "Unsupported CONCAT_VECTORS for value type");
5405 // We support concatenate two MMX registers and place them in a MMX register.
5406 // This is better than doing a stack convert.
5407 if (ResVT.is128BitVector())
5408 return LowerMMXCONCAT_VECTORS(Op, DAG);
5410 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5411 // from two other 128-bit ones.
5412 return LowerAVXCONCAT_VECTORS(Op, DAG);
5415 // v8i16 shuffles - Prefer shuffles in the following order:
5416 // 1. [all] pshuflw, pshufhw, optional move
5417 // 2. [ssse3] 1 x pshufb
5418 // 3. [ssse3] 2 x pshufb + 1 x por
5419 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5421 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5422 SelectionDAG &DAG) const {
5423 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5424 SDValue V1 = SVOp->getOperand(0);
5425 SDValue V2 = SVOp->getOperand(1);
5426 DebugLoc dl = SVOp->getDebugLoc();
5427 SmallVector<int, 8> MaskVals;
5429 // Determine if more than 1 of the words in each of the low and high quadwords
5430 // of the result come from the same quadword of one of the two inputs. Undef
5431 // mask values count as coming from any quadword, for better codegen.
5432 unsigned LoQuad[] = { 0, 0, 0, 0 };
5433 unsigned HiQuad[] = { 0, 0, 0, 0 };
5434 BitVector InputQuads(4);
5435 for (unsigned i = 0; i < 8; ++i) {
5436 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5437 int EltIdx = SVOp->getMaskElt(i);
5438 MaskVals.push_back(EltIdx);
5447 InputQuads.set(EltIdx / 4);
5450 int BestLoQuad = -1;
5451 unsigned MaxQuad = 1;
5452 for (unsigned i = 0; i < 4; ++i) {
5453 if (LoQuad[i] > MaxQuad) {
5455 MaxQuad = LoQuad[i];
5459 int BestHiQuad = -1;
5461 for (unsigned i = 0; i < 4; ++i) {
5462 if (HiQuad[i] > MaxQuad) {
5464 MaxQuad = HiQuad[i];
5468 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5469 // of the two input vectors, shuffle them into one input vector so only a
5470 // single pshufb instruction is necessary. If There are more than 2 input
5471 // quads, disable the next transformation since it does not help SSSE3.
5472 bool V1Used = InputQuads[0] || InputQuads[1];
5473 bool V2Used = InputQuads[2] || InputQuads[3];
5474 if (Subtarget->hasSSSE3()) {
5475 if (InputQuads.count() == 2 && V1Used && V2Used) {
5476 BestLoQuad = InputQuads.find_first();
5477 BestHiQuad = InputQuads.find_next(BestLoQuad);
5479 if (InputQuads.count() > 2) {
5485 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5486 // the shuffle mask. If a quad is scored as -1, that means that it contains
5487 // words from all 4 input quadwords.
5489 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5490 SmallVector<int, 8> MaskV;
5491 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5492 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5493 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5494 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5495 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5496 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5498 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5499 // source words for the shuffle, to aid later transformations.
5500 bool AllWordsInNewV = true;
5501 bool InOrder[2] = { true, true };
5502 for (unsigned i = 0; i != 8; ++i) {
5503 int idx = MaskVals[i];
5505 InOrder[i/4] = false;
5506 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5508 AllWordsInNewV = false;
5512 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5513 if (AllWordsInNewV) {
5514 for (int i = 0; i != 8; ++i) {
5515 int idx = MaskVals[i];
5518 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5519 if ((idx != i) && idx < 4)
5521 if ((idx != i) && idx > 3)
5530 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5531 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5532 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5533 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5534 unsigned TargetMask = 0;
5535 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5536 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5537 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5538 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5539 V1 = NewV.getOperand(0);
5540 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5544 // If we have SSSE3, and all words of the result are from 1 input vector,
5545 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5546 // is present, fall back to case 4.
5547 if (Subtarget->hasSSSE3()) {
5548 SmallVector<SDValue,16> pshufbMask;
5550 // If we have elements from both input vectors, set the high bit of the
5551 // shuffle mask element to zero out elements that come from V2 in the V1
5552 // mask, and elements that come from V1 in the V2 mask, so that the two
5553 // results can be OR'd together.
5554 bool TwoInputs = V1Used && V2Used;
5555 for (unsigned i = 0; i != 8; ++i) {
5556 int EltIdx = MaskVals[i] * 2;
5557 if (TwoInputs && (EltIdx >= 16)) {
5558 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5559 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5562 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5563 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5565 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5566 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5567 DAG.getNode(ISD::BUILD_VECTOR, dl,
5568 MVT::v16i8, &pshufbMask[0], 16));
5570 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5572 // Calculate the shuffle mask for the second input, shuffle it, and
5573 // OR it with the first shuffled input.
5575 for (unsigned i = 0; i != 8; ++i) {
5576 int EltIdx = MaskVals[i] * 2;
5578 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5579 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5582 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5583 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5585 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5586 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5587 DAG.getNode(ISD::BUILD_VECTOR, dl,
5588 MVT::v16i8, &pshufbMask[0], 16));
5589 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5590 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5593 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5594 // and update MaskVals with new element order.
5595 BitVector InOrder(8);
5596 if (BestLoQuad >= 0) {
5597 SmallVector<int, 8> MaskV;
5598 for (int i = 0; i != 4; ++i) {
5599 int idx = MaskVals[i];
5601 MaskV.push_back(-1);
5603 } else if ((idx / 4) == BestLoQuad) {
5604 MaskV.push_back(idx & 3);
5607 MaskV.push_back(-1);
5610 for (unsigned i = 4; i != 8; ++i)
5612 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5615 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5616 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5618 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5622 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5623 // and update MaskVals with the new element order.
5624 if (BestHiQuad >= 0) {
5625 SmallVector<int, 8> MaskV;
5626 for (unsigned i = 0; i != 4; ++i)
5628 for (unsigned i = 4; i != 8; ++i) {
5629 int idx = MaskVals[i];
5631 MaskV.push_back(-1);
5633 } else if ((idx / 4) == BestHiQuad) {
5634 MaskV.push_back((idx & 3) + 4);
5637 MaskV.push_back(-1);
5640 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5643 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5644 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5646 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5650 // In case BestHi & BestLo were both -1, which means each quadword has a word
5651 // from each of the four input quadwords, calculate the InOrder bitvector now
5652 // before falling through to the insert/extract cleanup.
5653 if (BestLoQuad == -1 && BestHiQuad == -1) {
5655 for (int i = 0; i != 8; ++i)
5656 if (MaskVals[i] < 0 || MaskVals[i] == i)
5660 // The other elements are put in the right place using pextrw and pinsrw.
5661 for (unsigned i = 0; i != 8; ++i) {
5664 int EltIdx = MaskVals[i];
5667 SDValue ExtOp = (EltIdx < 8)
5668 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5669 DAG.getIntPtrConstant(EltIdx))
5670 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5671 DAG.getIntPtrConstant(EltIdx - 8));
5672 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5673 DAG.getIntPtrConstant(i));
5678 // v16i8 shuffles - Prefer shuffles in the following order:
5679 // 1. [ssse3] 1 x pshufb
5680 // 2. [ssse3] 2 x pshufb + 1 x por
5681 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5683 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5685 const X86TargetLowering &TLI) {
5686 SDValue V1 = SVOp->getOperand(0);
5687 SDValue V2 = SVOp->getOperand(1);
5688 DebugLoc dl = SVOp->getDebugLoc();
5689 ArrayRef<int> MaskVals = SVOp->getMask();
5691 // If we have SSSE3, case 1 is generated when all result bytes come from
5692 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5693 // present, fall back to case 3.
5694 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5697 for (unsigned i = 0; i < 16; ++i) {
5698 int EltIdx = MaskVals[i];
5707 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5708 if (TLI.getSubtarget()->hasSSSE3()) {
5709 SmallVector<SDValue,16> pshufbMask;
5711 // If all result elements are from one input vector, then only translate
5712 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5714 // Otherwise, we have elements from both input vectors, and must zero out
5715 // elements that come from V2 in the first mask, and V1 in the second mask
5716 // so that we can OR them together.
5717 bool TwoInputs = !(V1Only || V2Only);
5718 for (unsigned i = 0; i != 16; ++i) {
5719 int EltIdx = MaskVals[i];
5720 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5721 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5724 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5726 // If all the elements are from V2, assign it to V1 and return after
5727 // building the first pshufb.
5730 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5731 DAG.getNode(ISD::BUILD_VECTOR, dl,
5732 MVT::v16i8, &pshufbMask[0], 16));
5736 // Calculate the shuffle mask for the second input, shuffle it, and
5737 // OR it with the first shuffled input.
5739 for (unsigned i = 0; i != 16; ++i) {
5740 int EltIdx = MaskVals[i];
5742 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5745 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5747 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5748 DAG.getNode(ISD::BUILD_VECTOR, dl,
5749 MVT::v16i8, &pshufbMask[0], 16));
5750 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5753 // No SSSE3 - Calculate in place words and then fix all out of place words
5754 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5755 // the 16 different words that comprise the two doublequadword input vectors.
5756 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5757 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5758 SDValue NewV = V2Only ? V2 : V1;
5759 for (int i = 0; i != 8; ++i) {
5760 int Elt0 = MaskVals[i*2];
5761 int Elt1 = MaskVals[i*2+1];
5763 // This word of the result is all undef, skip it.
5764 if (Elt0 < 0 && Elt1 < 0)
5767 // This word of the result is already in the correct place, skip it.
5768 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5770 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5773 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5774 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5777 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5778 // using a single extract together, load it and store it.
5779 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5780 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5781 DAG.getIntPtrConstant(Elt1 / 2));
5782 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5783 DAG.getIntPtrConstant(i));
5787 // If Elt1 is defined, extract it from the appropriate source. If the
5788 // source byte is not also odd, shift the extracted word left 8 bits
5789 // otherwise clear the bottom 8 bits if we need to do an or.
5791 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5792 DAG.getIntPtrConstant(Elt1 / 2));
5793 if ((Elt1 & 1) == 0)
5794 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5796 TLI.getShiftAmountTy(InsElt.getValueType())));
5798 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5799 DAG.getConstant(0xFF00, MVT::i16));
5801 // If Elt0 is defined, extract it from the appropriate source. If the
5802 // source byte is not also even, shift the extracted word right 8 bits. If
5803 // Elt1 was also defined, OR the extracted values together before
5804 // inserting them in the result.
5806 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5807 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5808 if ((Elt0 & 1) != 0)
5809 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5811 TLI.getShiftAmountTy(InsElt0.getValueType())));
5813 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5814 DAG.getConstant(0x00FF, MVT::i16));
5815 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5818 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5819 DAG.getIntPtrConstant(i));
5821 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5824 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5825 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5826 /// done when every pair / quad of shuffle mask elements point to elements in
5827 /// the right sequence. e.g.
5828 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5830 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5831 SelectionDAG &DAG, DebugLoc dl) {
5832 EVT VT = SVOp->getValueType(0);
5833 SDValue V1 = SVOp->getOperand(0);
5834 SDValue V2 = SVOp->getOperand(1);
5835 unsigned NumElems = VT.getVectorNumElements();
5836 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5838 switch (VT.getSimpleVT().SimpleTy) {
5839 default: assert(false && "Unexpected!");
5840 case MVT::v4f32: NewVT = MVT::v2f64; break;
5841 case MVT::v4i32: NewVT = MVT::v2i64; break;
5842 case MVT::v8i16: NewVT = MVT::v4i32; break;
5843 case MVT::v16i8: NewVT = MVT::v4i32; break;
5846 int Scale = NumElems / NewWidth;
5847 SmallVector<int, 8> MaskVec;
5848 for (unsigned i = 0; i < NumElems; i += Scale) {
5850 for (int j = 0; j < Scale; ++j) {
5851 int EltIdx = SVOp->getMaskElt(i+j);
5855 StartIdx = EltIdx - (EltIdx % Scale);
5856 if (EltIdx != StartIdx + j)
5860 MaskVec.push_back(-1);
5862 MaskVec.push_back(StartIdx / Scale);
5865 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5866 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5867 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5870 /// getVZextMovL - Return a zero-extending vector move low node.
5872 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5873 SDValue SrcOp, SelectionDAG &DAG,
5874 const X86Subtarget *Subtarget, DebugLoc dl) {
5875 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5876 LoadSDNode *LD = NULL;
5877 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5878 LD = dyn_cast<LoadSDNode>(SrcOp);
5880 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5882 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5883 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5884 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5885 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5886 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5888 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5889 return DAG.getNode(ISD::BITCAST, dl, VT,
5890 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5891 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5899 return DAG.getNode(ISD::BITCAST, dl, VT,
5900 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5901 DAG.getNode(ISD::BITCAST, dl,
5905 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5906 /// shuffle node referes to only one lane in the sources.
5907 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5908 EVT VT = SVOp->getValueType(0);
5909 int NumElems = VT.getVectorNumElements();
5910 int HalfSize = NumElems/2;
5911 ArrayRef<int> M = SVOp->getMask();
5912 bool MatchA = false, MatchB = false;
5914 for (int l = 0; l < NumElems*2; l += HalfSize) {
5915 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5921 for (int l = 0; l < NumElems*2; l += HalfSize) {
5922 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5928 return MatchA && MatchB;
5931 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5932 /// which could not be matched by any known target speficic shuffle
5934 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5935 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5936 // If each half of a vector shuffle node referes to only one lane in the
5937 // source vectors, extract each used 128-bit lane and shuffle them using
5938 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5939 // the work to the legalizer.
5940 DebugLoc dl = SVOp->getDebugLoc();
5941 EVT VT = SVOp->getValueType(0);
5942 int NumElems = VT.getVectorNumElements();
5943 int HalfSize = NumElems/2;
5945 // Extract the reference for each half
5946 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5947 int FstVecOpNum = 0, SndVecOpNum = 0;
5948 for (int i = 0; i < HalfSize; ++i) {
5949 int Elt = SVOp->getMaskElt(i);
5950 if (SVOp->getMaskElt(i) < 0)
5952 FstVecOpNum = Elt/NumElems;
5953 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5956 for (int i = HalfSize; i < NumElems; ++i) {
5957 int Elt = SVOp->getMaskElt(i);
5958 if (SVOp->getMaskElt(i) < 0)
5960 SndVecOpNum = Elt/NumElems;
5961 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5965 // Extract the subvectors
5966 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5967 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5968 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5969 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5971 // Generate 128-bit shuffles
5972 SmallVector<int, 16> MaskV1, MaskV2;
5973 for (int i = 0; i < HalfSize; ++i) {
5974 int Elt = SVOp->getMaskElt(i);
5975 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5977 for (int i = HalfSize; i < NumElems; ++i) {
5978 int Elt = SVOp->getMaskElt(i);
5979 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5982 EVT NVT = V1.getValueType();
5983 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5984 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
5986 // Concatenate the result back
5987 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
5988 DAG.getConstant(0, MVT::i32), DAG, dl);
5989 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5996 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5997 /// 4 elements, and match them with several different shuffle types.
5999 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6000 SDValue V1 = SVOp->getOperand(0);
6001 SDValue V2 = SVOp->getOperand(1);
6002 DebugLoc dl = SVOp->getDebugLoc();
6003 EVT VT = SVOp->getValueType(0);
6005 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6007 SmallVector<std::pair<int, int>, 8> Locs;
6009 SmallVector<int, 8> Mask1(4U, -1);
6010 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6014 for (unsigned i = 0; i != 4; ++i) {
6015 int Idx = PermMask[i];
6017 Locs[i] = std::make_pair(-1, -1);
6019 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6021 Locs[i] = std::make_pair(0, NumLo);
6025 Locs[i] = std::make_pair(1, NumHi);
6027 Mask1[2+NumHi] = Idx;
6033 if (NumLo <= 2 && NumHi <= 2) {
6034 // If no more than two elements come from either vector. This can be
6035 // implemented with two shuffles. First shuffle gather the elements.
6036 // The second shuffle, which takes the first shuffle as both of its
6037 // vector operands, put the elements into the right order.
6038 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6040 SmallVector<int, 8> Mask2(4U, -1);
6042 for (unsigned i = 0; i != 4; ++i) {
6043 if (Locs[i].first == -1)
6046 unsigned Idx = (i < 2) ? 0 : 4;
6047 Idx += Locs[i].first * 2 + Locs[i].second;
6052 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6053 } else if (NumLo == 3 || NumHi == 3) {
6054 // Otherwise, we must have three elements from one vector, call it X, and
6055 // one element from the other, call it Y. First, use a shufps to build an
6056 // intermediate vector with the one element from Y and the element from X
6057 // that will be in the same half in the final destination (the indexes don't
6058 // matter). Then, use a shufps to build the final vector, taking the half
6059 // containing the element from Y from the intermediate, and the other half
6062 // Normalize it so the 3 elements come from V1.
6063 CommuteVectorShuffleMask(PermMask, 4);
6067 // Find the element from V2.
6069 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6070 int Val = PermMask[HiIndex];
6077 Mask1[0] = PermMask[HiIndex];
6079 Mask1[2] = PermMask[HiIndex^1];
6081 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6084 Mask1[0] = PermMask[0];
6085 Mask1[1] = PermMask[1];
6086 Mask1[2] = HiIndex & 1 ? 6 : 4;
6087 Mask1[3] = HiIndex & 1 ? 4 : 6;
6088 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6090 Mask1[0] = HiIndex & 1 ? 2 : 0;
6091 Mask1[1] = HiIndex & 1 ? 0 : 2;
6092 Mask1[2] = PermMask[2];
6093 Mask1[3] = PermMask[3];
6098 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6102 // Break it into (shuffle shuffle_hi, shuffle_lo).
6105 SmallVector<int,8> LoMask(4U, -1);
6106 SmallVector<int,8> HiMask(4U, -1);
6108 SmallVector<int,8> *MaskPtr = &LoMask;
6109 unsigned MaskIdx = 0;
6112 for (unsigned i = 0; i != 4; ++i) {
6119 int Idx = PermMask[i];
6121 Locs[i] = std::make_pair(-1, -1);
6122 } else if (Idx < 4) {
6123 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6124 (*MaskPtr)[LoIdx] = Idx;
6127 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6128 (*MaskPtr)[HiIdx] = Idx;
6133 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6134 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6135 SmallVector<int, 8> MaskOps;
6136 for (unsigned i = 0; i != 4; ++i) {
6137 if (Locs[i].first == -1) {
6138 MaskOps.push_back(-1);
6140 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6141 MaskOps.push_back(Idx);
6144 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6147 static bool MayFoldVectorLoad(SDValue V) {
6148 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6149 V = V.getOperand(0);
6150 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6151 V = V.getOperand(0);
6152 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6153 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6154 // BUILD_VECTOR (load), undef
6155 V = V.getOperand(0);
6161 // FIXME: the version above should always be used. Since there's
6162 // a bug where several vector shuffles can't be folded because the
6163 // DAG is not updated during lowering and a node claims to have two
6164 // uses while it only has one, use this version, and let isel match
6165 // another instruction if the load really happens to have more than
6166 // one use. Remove this version after this bug get fixed.
6167 // rdar://8434668, PR8156
6168 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6169 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6170 V = V.getOperand(0);
6171 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6172 V = V.getOperand(0);
6173 if (ISD::isNormalLoad(V.getNode()))
6178 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6179 /// a vector extract, and if both can be later optimized into a single load.
6180 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6181 /// here because otherwise a target specific shuffle node is going to be
6182 /// emitted for this shuffle, and the optimization not done.
6183 /// FIXME: This is probably not the best approach, but fix the problem
6184 /// until the right path is decided.
6186 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6187 const TargetLowering &TLI) {
6188 EVT VT = V.getValueType();
6189 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6191 // Be sure that the vector shuffle is present in a pattern like this:
6192 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6196 SDNode *N = *V.getNode()->use_begin();
6197 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6200 SDValue EltNo = N->getOperand(1);
6201 if (!isa<ConstantSDNode>(EltNo))
6204 // If the bit convert changed the number of elements, it is unsafe
6205 // to examine the mask.
6206 bool HasShuffleIntoBitcast = false;
6207 if (V.getOpcode() == ISD::BITCAST) {
6208 EVT SrcVT = V.getOperand(0).getValueType();
6209 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6211 V = V.getOperand(0);
6212 HasShuffleIntoBitcast = true;
6215 // Select the input vector, guarding against out of range extract vector.
6216 unsigned NumElems = VT.getVectorNumElements();
6217 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6218 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6219 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6221 // If we are accessing the upper part of a YMM register
6222 // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of
6223 // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point
6224 // because the legalization of N did not happen yet.
6225 if (Idx >= (int)NumElems/2 && VT.getSizeInBits() == 256)
6228 // Skip one more bit_convert if necessary
6229 if (V.getOpcode() == ISD::BITCAST)
6230 V = V.getOperand(0);
6232 if (!ISD::isNormalLoad(V.getNode()))
6235 // Is the original load suitable?
6236 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6238 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6241 if (!HasShuffleIntoBitcast)
6244 // If there's a bitcast before the shuffle, check if the load type and
6245 // alignment is valid.
6246 unsigned Align = LN0->getAlignment();
6248 TLI.getTargetData()->getABITypeAlignment(
6249 VT.getTypeForEVT(*DAG.getContext()));
6251 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6258 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6259 EVT VT = Op.getValueType();
6261 // Canonizalize to v2f64.
6262 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6263 return DAG.getNode(ISD::BITCAST, dl, VT,
6264 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6269 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6271 SDValue V1 = Op.getOperand(0);
6272 SDValue V2 = Op.getOperand(1);
6273 EVT VT = Op.getValueType();
6275 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6277 if (HasSSE2 && VT == MVT::v2f64)
6278 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6280 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6281 return DAG.getNode(ISD::BITCAST, dl, VT,
6282 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6283 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6284 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6288 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6289 SDValue V1 = Op.getOperand(0);
6290 SDValue V2 = Op.getOperand(1);
6291 EVT VT = Op.getValueType();
6293 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6294 "unsupported shuffle type");
6296 if (V2.getOpcode() == ISD::UNDEF)
6300 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6304 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6305 SDValue V1 = Op.getOperand(0);
6306 SDValue V2 = Op.getOperand(1);
6307 EVT VT = Op.getValueType();
6308 unsigned NumElems = VT.getVectorNumElements();
6310 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6311 // operand of these instructions is only memory, so check if there's a
6312 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6314 bool CanFoldLoad = false;
6316 // Trivial case, when V2 comes from a load.
6317 if (MayFoldVectorLoad(V2))
6320 // When V1 is a load, it can be folded later into a store in isel, example:
6321 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6323 // (MOVLPSmr addr:$src1, VR128:$src2)
6324 // So, recognize this potential and also use MOVLPS or MOVLPD
6325 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6328 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6330 if (HasSSE2 && NumElems == 2)
6331 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6334 // If we don't care about the second element, procede to use movss.
6335 if (SVOp->getMaskElt(1) != -1)
6336 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6339 // movl and movlp will both match v2i64, but v2i64 is never matched by
6340 // movl earlier because we make it strict to avoid messing with the movlp load
6341 // folding logic (see the code above getMOVLP call). Match it here then,
6342 // this is horrible, but will stay like this until we move all shuffle
6343 // matching to x86 specific nodes. Note that for the 1st condition all
6344 // types are matched with movsd.
6346 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6347 // as to remove this logic from here, as much as possible
6348 if (NumElems == 2 || !X86::isMOVLMask(SVOp))
6349 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6350 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6353 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6355 // Invert the operand order and use SHUFPS to match it.
6356 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6357 X86::getShuffleSHUFImmediate(SVOp), DAG);
6361 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6362 const TargetLowering &TLI,
6363 const X86Subtarget *Subtarget) {
6364 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6365 EVT VT = Op.getValueType();
6366 DebugLoc dl = Op.getDebugLoc();
6367 SDValue V1 = Op.getOperand(0);
6368 SDValue V2 = Op.getOperand(1);
6370 if (isZeroShuffle(SVOp))
6371 return getZeroVector(VT, Subtarget->hasSSE2(), Subtarget->hasAVX2(),
6374 // Handle splat operations
6375 if (SVOp->isSplat()) {
6376 unsigned NumElem = VT.getVectorNumElements();
6377 int Size = VT.getSizeInBits();
6378 // Special case, this is the only place now where it's allowed to return
6379 // a vector_shuffle operation without using a target specific node, because
6380 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6381 // this be moved to DAGCombine instead?
6382 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6385 // Use vbroadcast whenever the splat comes from a foldable load
6386 SDValue LD = isVectorBroadcast(Op, Subtarget);
6388 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6390 // Handle splats by matching through known shuffle masks
6391 if ((Size == 128 && NumElem <= 4) ||
6392 (Size == 256 && NumElem < 8))
6395 // All remaning splats are promoted to target supported vector shuffles.
6396 return PromoteSplat(SVOp, DAG);
6399 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6401 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6402 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6403 if (NewOp.getNode())
6404 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6405 } else if ((VT == MVT::v4i32 ||
6406 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6407 // FIXME: Figure out a cleaner way to do this.
6408 // Try to make use of movq to zero out the top part.
6409 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6410 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6411 if (NewOp.getNode()) {
6412 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6413 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6414 DAG, Subtarget, dl);
6416 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6417 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6418 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6419 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6420 DAG, Subtarget, dl);
6427 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6428 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6429 SDValue V1 = Op.getOperand(0);
6430 SDValue V2 = Op.getOperand(1);
6431 EVT VT = Op.getValueType();
6432 DebugLoc dl = Op.getDebugLoc();
6433 unsigned NumElems = VT.getVectorNumElements();
6434 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6435 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6436 bool V1IsSplat = false;
6437 bool V2IsSplat = false;
6438 bool HasSSE2 = Subtarget->hasSSE2();
6439 bool HasAVX = Subtarget->hasAVX();
6440 bool HasAVX2 = Subtarget->hasAVX2();
6441 MachineFunction &MF = DAG.getMachineFunction();
6442 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6444 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6446 if (V1IsUndef && V2IsUndef)
6447 return DAG.getUNDEF(VT);
6449 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6451 // Vector shuffle lowering takes 3 steps:
6453 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6454 // narrowing and commutation of operands should be handled.
6455 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6457 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6458 // so the shuffle can be broken into other shuffles and the legalizer can
6459 // try the lowering again.
6461 // The general idea is that no vector_shuffle operation should be left to
6462 // be matched during isel, all of them must be converted to a target specific
6465 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6466 // narrowing and commutation of operands should be handled. The actual code
6467 // doesn't include all of those, work in progress...
6468 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6469 if (NewOp.getNode())
6472 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6473 // unpckh_undef). Only use pshufd if speed is more important than size.
6474 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp, HasAVX2))
6475 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6476 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp, HasAVX2))
6477 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6479 if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3() &&
6480 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6481 return getMOVDDup(Op, dl, V1, DAG);
6483 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6484 return getMOVHighToLow(Op, dl, DAG);
6486 // Use to match splats
6487 if (HasSSE2 && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef &&
6488 (VT == MVT::v2f64 || VT == MVT::v2i64))
6489 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6491 if (X86::isPSHUFDMask(SVOp)) {
6492 // The actual implementation will match the mask in the if above and then
6493 // during isel it can match several different instructions, not only pshufd
6494 // as its name says, sad but true, emulate the behavior for now...
6495 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6496 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6498 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6500 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6501 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6503 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6507 // Check if this can be converted into a logical shift.
6508 bool isLeft = false;
6511 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6512 if (isShift && ShVal.hasOneUse()) {
6513 // If the shifted value has multiple uses, it may be cheaper to use
6514 // v_set0 + movlhps or movhlps, etc.
6515 EVT EltVT = VT.getVectorElementType();
6516 ShAmt *= EltVT.getSizeInBits();
6517 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6520 if (X86::isMOVLMask(SVOp)) {
6521 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6522 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6523 if (!X86::isMOVLPMask(SVOp)) {
6524 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6525 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6527 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6528 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6532 // FIXME: fold these into legal mask.
6533 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp, HasAVX2))
6534 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6536 if (X86::isMOVHLPSMask(SVOp))
6537 return getMOVHighToLow(Op, dl, DAG);
6539 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6540 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6542 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6543 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6545 if (X86::isMOVLPMask(SVOp))
6546 return getMOVLP(Op, dl, DAG, HasSSE2);
6548 if (ShouldXformToMOVHLPS(SVOp) ||
6549 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6550 return CommuteVectorShuffle(SVOp, DAG);
6553 // No better options. Use a vshl / vsrl.
6554 EVT EltVT = VT.getVectorElementType();
6555 ShAmt *= EltVT.getSizeInBits();
6556 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6559 bool Commuted = false;
6560 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6561 // 1,1,1,1 -> v8i16 though.
6562 V1IsSplat = isSplatVector(V1.getNode());
6563 V2IsSplat = isSplatVector(V2.getNode());
6565 // Canonicalize the splat or undef, if present, to be on the RHS.
6566 if (V1IsSplat && !V2IsSplat) {
6567 Op = CommuteVectorShuffle(SVOp, DAG);
6568 SVOp = cast<ShuffleVectorSDNode>(Op);
6569 V1 = SVOp->getOperand(0);
6570 V2 = SVOp->getOperand(1);
6571 std::swap(V1IsSplat, V2IsSplat);
6575 ArrayRef<int> M = SVOp->getMask();
6577 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6578 // Shuffling low element of v1 into undef, just return v1.
6581 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6582 // the instruction selector will not match, so get a canonical MOVL with
6583 // swapped operands to undo the commute.
6584 return getMOVL(DAG, dl, VT, V2, V1);
6587 if (isUNPCKLMask(M, VT, HasAVX2))
6588 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6590 if (isUNPCKHMask(M, VT, HasAVX2))
6591 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6594 // Normalize mask so all entries that point to V2 points to its first
6595 // element then try to match unpck{h|l} again. If match, return a
6596 // new vector_shuffle with the corrected mask.
6597 SDValue NewMask = NormalizeMask(SVOp, DAG);
6598 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6599 if (NSVOp != SVOp) {
6600 if (X86::isUNPCKLMask(NSVOp, HasAVX2, true)) {
6602 } else if (X86::isUNPCKHMask(NSVOp, HasAVX2, true)) {
6609 // Commute is back and try unpck* again.
6610 // FIXME: this seems wrong.
6611 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6612 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6614 if (X86::isUNPCKLMask(NewSVOp, HasAVX2))
6615 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG);
6617 if (X86::isUNPCKHMask(NewSVOp, HasAVX2))
6618 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG);
6621 // Normalize the node to match x86 shuffle ops if needed
6622 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6623 return CommuteVectorShuffle(SVOp, DAG);
6625 // The checks below are all present in isShuffleMaskLegal, but they are
6626 // inlined here right now to enable us to directly emit target specific
6627 // nodes, and remove one by one until they don't return Op anymore.
6629 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3()))
6630 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6631 getShufflePALIGNRImmediate(SVOp),
6634 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6635 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6636 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6637 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6640 if (isPSHUFHWMask(M, VT))
6641 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6642 X86::getShufflePSHUFHWImmediate(SVOp),
6645 if (isPSHUFLWMask(M, VT))
6646 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6647 X86::getShufflePSHUFLWImmediate(SVOp),
6650 if (isSHUFPMask(M, VT, HasAVX))
6651 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6652 X86::getShuffleSHUFImmediate(SVOp), DAG);
6654 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6655 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6656 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6657 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6659 //===--------------------------------------------------------------------===//
6660 // Generate target specific nodes for 128 or 256-bit shuffles only
6661 // supported in the AVX instruction set.
6664 // Handle VMOVDDUPY permutations
6665 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6666 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6668 // Handle VPERMILPS/D* permutations
6669 if (isVPERMILPMask(M, VT, HasAVX))
6670 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6671 getShuffleVPERMILPImmediate(SVOp), DAG);
6673 // Handle VPERM2F128/VPERM2I128 permutations
6674 if (isVPERM2X128Mask(M, VT, HasAVX))
6675 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6676 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6678 //===--------------------------------------------------------------------===//
6679 // Since no target specific shuffle was selected for this generic one,
6680 // lower it into other known shuffles. FIXME: this isn't true yet, but
6681 // this is the plan.
6684 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6685 if (VT == MVT::v8i16) {
6686 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6687 if (NewOp.getNode())
6691 if (VT == MVT::v16i8) {
6692 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6693 if (NewOp.getNode())
6697 // Handle all 128-bit wide vectors with 4 elements, and match them with
6698 // several different shuffle types.
6699 if (NumElems == 4 && VT.getSizeInBits() == 128)
6700 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6702 // Handle general 256-bit shuffles
6703 if (VT.is256BitVector())
6704 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6710 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6711 SelectionDAG &DAG) const {
6712 EVT VT = Op.getValueType();
6713 DebugLoc dl = Op.getDebugLoc();
6715 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6718 if (VT.getSizeInBits() == 8) {
6719 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6720 Op.getOperand(0), Op.getOperand(1));
6721 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6722 DAG.getValueType(VT));
6723 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6724 } else if (VT.getSizeInBits() == 16) {
6725 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6726 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6728 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6729 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6730 DAG.getNode(ISD::BITCAST, dl,
6734 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6735 Op.getOperand(0), Op.getOperand(1));
6736 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6737 DAG.getValueType(VT));
6738 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6739 } else if (VT == MVT::f32) {
6740 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6741 // the result back to FR32 register. It's only worth matching if the
6742 // result has a single use which is a store or a bitcast to i32. And in
6743 // the case of a store, it's not worth it if the index is a constant 0,
6744 // because a MOVSSmr can be used instead, which is smaller and faster.
6745 if (!Op.hasOneUse())
6747 SDNode *User = *Op.getNode()->use_begin();
6748 if ((User->getOpcode() != ISD::STORE ||
6749 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6750 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6751 (User->getOpcode() != ISD::BITCAST ||
6752 User->getValueType(0) != MVT::i32))
6754 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6755 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6758 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6759 } else if (VT == MVT::i32 || VT == MVT::i64) {
6760 // ExtractPS/pextrq works with constant index.
6761 if (isa<ConstantSDNode>(Op.getOperand(1)))
6769 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6770 SelectionDAG &DAG) const {
6771 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6774 SDValue Vec = Op.getOperand(0);
6775 EVT VecVT = Vec.getValueType();
6777 // If this is a 256-bit vector result, first extract the 128-bit vector and
6778 // then extract the element from the 128-bit vector.
6779 if (VecVT.getSizeInBits() == 256) {
6780 DebugLoc dl = Op.getNode()->getDebugLoc();
6781 unsigned NumElems = VecVT.getVectorNumElements();
6782 SDValue Idx = Op.getOperand(1);
6783 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6785 // Get the 128-bit vector.
6786 bool Upper = IdxVal >= NumElems/2;
6787 Vec = Extract128BitVector(Vec,
6788 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6790 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6791 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6794 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6796 if (Subtarget->hasSSE41()) {
6797 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6802 EVT VT = Op.getValueType();
6803 DebugLoc dl = Op.getDebugLoc();
6804 // TODO: handle v16i8.
6805 if (VT.getSizeInBits() == 16) {
6806 SDValue Vec = Op.getOperand(0);
6807 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6809 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6810 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6811 DAG.getNode(ISD::BITCAST, dl,
6814 // Transform it so it match pextrw which produces a 32-bit result.
6815 EVT EltVT = MVT::i32;
6816 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6817 Op.getOperand(0), Op.getOperand(1));
6818 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6819 DAG.getValueType(VT));
6820 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6821 } else if (VT.getSizeInBits() == 32) {
6822 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6826 // SHUFPS the element to the lowest double word, then movss.
6827 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6828 EVT VVT = Op.getOperand(0).getValueType();
6829 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6830 DAG.getUNDEF(VVT), Mask);
6831 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6832 DAG.getIntPtrConstant(0));
6833 } else if (VT.getSizeInBits() == 64) {
6834 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6835 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6836 // to match extract_elt for f64.
6837 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6841 // UNPCKHPD the element to the lowest double word, then movsd.
6842 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6843 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6844 int Mask[2] = { 1, -1 };
6845 EVT VVT = Op.getOperand(0).getValueType();
6846 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6847 DAG.getUNDEF(VVT), Mask);
6848 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6849 DAG.getIntPtrConstant(0));
6856 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6857 SelectionDAG &DAG) const {
6858 EVT VT = Op.getValueType();
6859 EVT EltVT = VT.getVectorElementType();
6860 DebugLoc dl = Op.getDebugLoc();
6862 SDValue N0 = Op.getOperand(0);
6863 SDValue N1 = Op.getOperand(1);
6864 SDValue N2 = Op.getOperand(2);
6866 if (VT.getSizeInBits() == 256)
6869 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6870 isa<ConstantSDNode>(N2)) {
6872 if (VT == MVT::v8i16)
6873 Opc = X86ISD::PINSRW;
6874 else if (VT == MVT::v16i8)
6875 Opc = X86ISD::PINSRB;
6877 Opc = X86ISD::PINSRB;
6879 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6881 if (N1.getValueType() != MVT::i32)
6882 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6883 if (N2.getValueType() != MVT::i32)
6884 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6885 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6886 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6887 // Bits [7:6] of the constant are the source select. This will always be
6888 // zero here. The DAG Combiner may combine an extract_elt index into these
6889 // bits. For example (insert (extract, 3), 2) could be matched by putting
6890 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6891 // Bits [5:4] of the constant are the destination select. This is the
6892 // value of the incoming immediate.
6893 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6894 // combine either bitwise AND or insert of float 0.0 to set these bits.
6895 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6896 // Create this as a scalar to vector..
6897 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6898 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6899 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6900 isa<ConstantSDNode>(N2)) {
6901 // PINSR* works with constant index.
6908 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6909 EVT VT = Op.getValueType();
6910 EVT EltVT = VT.getVectorElementType();
6912 DebugLoc dl = Op.getDebugLoc();
6913 SDValue N0 = Op.getOperand(0);
6914 SDValue N1 = Op.getOperand(1);
6915 SDValue N2 = Op.getOperand(2);
6917 // If this is a 256-bit vector result, first extract the 128-bit vector,
6918 // insert the element into the extracted half and then place it back.
6919 if (VT.getSizeInBits() == 256) {
6920 if (!isa<ConstantSDNode>(N2))
6923 // Get the desired 128-bit vector half.
6924 unsigned NumElems = VT.getVectorNumElements();
6925 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6926 bool Upper = IdxVal >= NumElems/2;
6927 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6928 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6930 // Insert the element into the desired half.
6931 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6932 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6934 // Insert the changed part back to the 256-bit vector
6935 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6938 if (Subtarget->hasSSE41())
6939 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6941 if (EltVT == MVT::i8)
6944 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6945 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6946 // as its second argument.
6947 if (N1.getValueType() != MVT::i32)
6948 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6949 if (N2.getValueType() != MVT::i32)
6950 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6951 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6957 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6958 LLVMContext *Context = DAG.getContext();
6959 DebugLoc dl = Op.getDebugLoc();
6960 EVT OpVT = Op.getValueType();
6962 // If this is a 256-bit vector result, first insert into a 128-bit
6963 // vector and then insert into the 256-bit vector.
6964 if (OpVT.getSizeInBits() > 128) {
6965 // Insert into a 128-bit vector.
6966 EVT VT128 = EVT::getVectorVT(*Context,
6967 OpVT.getVectorElementType(),
6968 OpVT.getVectorNumElements() / 2);
6970 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6972 // Insert the 128-bit vector.
6973 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6974 DAG.getConstant(0, MVT::i32),
6978 if (Op.getValueType() == MVT::v1i64 &&
6979 Op.getOperand(0).getValueType() == MVT::i64)
6980 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6982 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6983 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6984 "Expected an SSE type!");
6985 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6986 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6989 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6990 // a simple subregister reference or explicit instructions to grab
6991 // upper bits of a vector.
6993 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6994 if (Subtarget->hasAVX()) {
6995 DebugLoc dl = Op.getNode()->getDebugLoc();
6996 SDValue Vec = Op.getNode()->getOperand(0);
6997 SDValue Idx = Op.getNode()->getOperand(1);
6999 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7000 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7001 return Extract128BitVector(Vec, Idx, DAG, dl);
7007 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7008 // simple superregister reference or explicit instructions to insert
7009 // the upper bits of a vector.
7011 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7012 if (Subtarget->hasAVX()) {
7013 DebugLoc dl = Op.getNode()->getDebugLoc();
7014 SDValue Vec = Op.getNode()->getOperand(0);
7015 SDValue SubVec = Op.getNode()->getOperand(1);
7016 SDValue Idx = Op.getNode()->getOperand(2);
7018 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7019 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7020 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7026 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7027 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7028 // one of the above mentioned nodes. It has to be wrapped because otherwise
7029 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7030 // be used to form addressing mode. These wrapped nodes will be selected
7033 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7034 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7036 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7038 unsigned char OpFlag = 0;
7039 unsigned WrapperKind = X86ISD::Wrapper;
7040 CodeModel::Model M = getTargetMachine().getCodeModel();
7042 if (Subtarget->isPICStyleRIPRel() &&
7043 (M == CodeModel::Small || M == CodeModel::Kernel))
7044 WrapperKind = X86ISD::WrapperRIP;
7045 else if (Subtarget->isPICStyleGOT())
7046 OpFlag = X86II::MO_GOTOFF;
7047 else if (Subtarget->isPICStyleStubPIC())
7048 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7050 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7052 CP->getOffset(), OpFlag);
7053 DebugLoc DL = CP->getDebugLoc();
7054 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7055 // With PIC, the address is actually $g + Offset.
7057 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7058 DAG.getNode(X86ISD::GlobalBaseReg,
7059 DebugLoc(), getPointerTy()),
7066 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7067 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7069 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7071 unsigned char OpFlag = 0;
7072 unsigned WrapperKind = X86ISD::Wrapper;
7073 CodeModel::Model M = getTargetMachine().getCodeModel();
7075 if (Subtarget->isPICStyleRIPRel() &&
7076 (M == CodeModel::Small || M == CodeModel::Kernel))
7077 WrapperKind = X86ISD::WrapperRIP;
7078 else if (Subtarget->isPICStyleGOT())
7079 OpFlag = X86II::MO_GOTOFF;
7080 else if (Subtarget->isPICStyleStubPIC())
7081 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7083 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7085 DebugLoc DL = JT->getDebugLoc();
7086 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7088 // With PIC, the address is actually $g + Offset.
7090 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7091 DAG.getNode(X86ISD::GlobalBaseReg,
7092 DebugLoc(), getPointerTy()),
7099 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7100 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7102 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7104 unsigned char OpFlag = 0;
7105 unsigned WrapperKind = X86ISD::Wrapper;
7106 CodeModel::Model M = getTargetMachine().getCodeModel();
7108 if (Subtarget->isPICStyleRIPRel() &&
7109 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7110 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7111 OpFlag = X86II::MO_GOTPCREL;
7112 WrapperKind = X86ISD::WrapperRIP;
7113 } else if (Subtarget->isPICStyleGOT()) {
7114 OpFlag = X86II::MO_GOT;
7115 } else if (Subtarget->isPICStyleStubPIC()) {
7116 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7117 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7118 OpFlag = X86II::MO_DARWIN_NONLAZY;
7121 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7123 DebugLoc DL = Op.getDebugLoc();
7124 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7127 // With PIC, the address is actually $g + Offset.
7128 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7129 !Subtarget->is64Bit()) {
7130 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7131 DAG.getNode(X86ISD::GlobalBaseReg,
7132 DebugLoc(), getPointerTy()),
7136 // For symbols that require a load from a stub to get the address, emit the
7138 if (isGlobalStubReference(OpFlag))
7139 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7140 MachinePointerInfo::getGOT(), false, false, false, 0);
7146 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7147 // Create the TargetBlockAddressAddress node.
7148 unsigned char OpFlags =
7149 Subtarget->ClassifyBlockAddressReference();
7150 CodeModel::Model M = getTargetMachine().getCodeModel();
7151 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7152 DebugLoc dl = Op.getDebugLoc();
7153 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7154 /*isTarget=*/true, OpFlags);
7156 if (Subtarget->isPICStyleRIPRel() &&
7157 (M == CodeModel::Small || M == CodeModel::Kernel))
7158 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7160 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7162 // With PIC, the address is actually $g + Offset.
7163 if (isGlobalRelativeToPICBase(OpFlags)) {
7164 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7165 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7173 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7175 SelectionDAG &DAG) const {
7176 // Create the TargetGlobalAddress node, folding in the constant
7177 // offset if it is legal.
7178 unsigned char OpFlags =
7179 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7180 CodeModel::Model M = getTargetMachine().getCodeModel();
7182 if (OpFlags == X86II::MO_NO_FLAG &&
7183 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7184 // A direct static reference to a global.
7185 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7188 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7191 if (Subtarget->isPICStyleRIPRel() &&
7192 (M == CodeModel::Small || M == CodeModel::Kernel))
7193 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7195 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7197 // With PIC, the address is actually $g + Offset.
7198 if (isGlobalRelativeToPICBase(OpFlags)) {
7199 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7200 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7204 // For globals that require a load from a stub to get the address, emit the
7206 if (isGlobalStubReference(OpFlags))
7207 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7208 MachinePointerInfo::getGOT(), false, false, false, 0);
7210 // If there was a non-zero offset that we didn't fold, create an explicit
7213 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7214 DAG.getConstant(Offset, getPointerTy()));
7220 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7221 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7222 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7223 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7227 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7228 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7229 unsigned char OperandFlags) {
7230 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7231 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7232 DebugLoc dl = GA->getDebugLoc();
7233 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7234 GA->getValueType(0),
7238 SDValue Ops[] = { Chain, TGA, *InFlag };
7239 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7241 SDValue Ops[] = { Chain, TGA };
7242 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7245 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7246 MFI->setAdjustsStack(true);
7248 SDValue Flag = Chain.getValue(1);
7249 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7252 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7254 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7257 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7258 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7259 DAG.getNode(X86ISD::GlobalBaseReg,
7260 DebugLoc(), PtrVT), InFlag);
7261 InFlag = Chain.getValue(1);
7263 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7266 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7268 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7270 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7271 X86::RAX, X86II::MO_TLSGD);
7274 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7275 // "local exec" model.
7276 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7277 const EVT PtrVT, TLSModel::Model model,
7279 DebugLoc dl = GA->getDebugLoc();
7281 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7282 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7283 is64Bit ? 257 : 256));
7285 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7286 DAG.getIntPtrConstant(0),
7287 MachinePointerInfo(Ptr),
7288 false, false, false, 0);
7290 unsigned char OperandFlags = 0;
7291 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7293 unsigned WrapperKind = X86ISD::Wrapper;
7294 if (model == TLSModel::LocalExec) {
7295 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7296 } else if (is64Bit) {
7297 assert(model == TLSModel::InitialExec);
7298 OperandFlags = X86II::MO_GOTTPOFF;
7299 WrapperKind = X86ISD::WrapperRIP;
7301 assert(model == TLSModel::InitialExec);
7302 OperandFlags = X86II::MO_INDNTPOFF;
7305 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7307 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7308 GA->getValueType(0),
7309 GA->getOffset(), OperandFlags);
7310 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7312 if (model == TLSModel::InitialExec)
7313 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7314 MachinePointerInfo::getGOT(), false, false, false, 0);
7316 // The address of the thread local variable is the add of the thread
7317 // pointer with the offset of the variable.
7318 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7322 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7324 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7325 const GlobalValue *GV = GA->getGlobal();
7327 if (Subtarget->isTargetELF()) {
7328 // TODO: implement the "local dynamic" model
7329 // TODO: implement the "initial exec"model for pic executables
7331 // If GV is an alias then use the aliasee for determining
7332 // thread-localness.
7333 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7334 GV = GA->resolveAliasedGlobal(false);
7336 TLSModel::Model model
7337 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7340 case TLSModel::GeneralDynamic:
7341 case TLSModel::LocalDynamic: // not implemented
7342 if (Subtarget->is64Bit())
7343 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7344 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7346 case TLSModel::InitialExec:
7347 case TLSModel::LocalExec:
7348 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7349 Subtarget->is64Bit());
7351 } else if (Subtarget->isTargetDarwin()) {
7352 // Darwin only has one model of TLS. Lower to that.
7353 unsigned char OpFlag = 0;
7354 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7355 X86ISD::WrapperRIP : X86ISD::Wrapper;
7357 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7359 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7360 !Subtarget->is64Bit();
7362 OpFlag = X86II::MO_TLVP_PIC_BASE;
7364 OpFlag = X86II::MO_TLVP;
7365 DebugLoc DL = Op.getDebugLoc();
7366 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7367 GA->getValueType(0),
7368 GA->getOffset(), OpFlag);
7369 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7371 // With PIC32, the address is actually $g + Offset.
7373 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7374 DAG.getNode(X86ISD::GlobalBaseReg,
7375 DebugLoc(), getPointerTy()),
7378 // Lowering the machine isd will make sure everything is in the right
7380 SDValue Chain = DAG.getEntryNode();
7381 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7382 SDValue Args[] = { Chain, Offset };
7383 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7385 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7386 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7387 MFI->setAdjustsStack(true);
7389 // And our return value (tls address) is in the standard call return value
7391 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7392 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7397 "TLS not implemented for this target.");
7399 llvm_unreachable("Unreachable");
7404 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7405 /// and take a 2 x i32 value to shift plus a shift amount.
7406 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7407 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7408 EVT VT = Op.getValueType();
7409 unsigned VTBits = VT.getSizeInBits();
7410 DebugLoc dl = Op.getDebugLoc();
7411 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7412 SDValue ShOpLo = Op.getOperand(0);
7413 SDValue ShOpHi = Op.getOperand(1);
7414 SDValue ShAmt = Op.getOperand(2);
7415 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7416 DAG.getConstant(VTBits - 1, MVT::i8))
7417 : DAG.getConstant(0, VT);
7420 if (Op.getOpcode() == ISD::SHL_PARTS) {
7421 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7422 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7424 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7425 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7428 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7429 DAG.getConstant(VTBits, MVT::i8));
7430 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7431 AndNode, DAG.getConstant(0, MVT::i8));
7434 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7435 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7436 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7438 if (Op.getOpcode() == ISD::SHL_PARTS) {
7439 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7440 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7442 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7443 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7446 SDValue Ops[2] = { Lo, Hi };
7447 return DAG.getMergeValues(Ops, 2, dl);
7450 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7451 SelectionDAG &DAG) const {
7452 EVT SrcVT = Op.getOperand(0).getValueType();
7454 if (SrcVT.isVector())
7457 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7458 "Unknown SINT_TO_FP to lower!");
7460 // These are really Legal; return the operand so the caller accepts it as
7462 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7464 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7465 Subtarget->is64Bit()) {
7469 DebugLoc dl = Op.getDebugLoc();
7470 unsigned Size = SrcVT.getSizeInBits()/8;
7471 MachineFunction &MF = DAG.getMachineFunction();
7472 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7473 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7474 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7476 MachinePointerInfo::getFixedStack(SSFI),
7478 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7481 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7483 SelectionDAG &DAG) const {
7485 DebugLoc DL = Op.getDebugLoc();
7487 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7489 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7491 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7493 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7495 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7496 MachineMemOperand *MMO;
7498 int SSFI = FI->getIndex();
7500 DAG.getMachineFunction()
7501 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7502 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7504 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7505 StackSlot = StackSlot.getOperand(1);
7507 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7508 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7510 Tys, Ops, array_lengthof(Ops),
7514 Chain = Result.getValue(1);
7515 SDValue InFlag = Result.getValue(2);
7517 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7518 // shouldn't be necessary except that RFP cannot be live across
7519 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7520 MachineFunction &MF = DAG.getMachineFunction();
7521 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7522 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7523 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7524 Tys = DAG.getVTList(MVT::Other);
7526 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7528 MachineMemOperand *MMO =
7529 DAG.getMachineFunction()
7530 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7531 MachineMemOperand::MOStore, SSFISize, SSFISize);
7533 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7534 Ops, array_lengthof(Ops),
7535 Op.getValueType(), MMO);
7536 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7537 MachinePointerInfo::getFixedStack(SSFI),
7538 false, false, false, 0);
7544 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7545 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7546 SelectionDAG &DAG) const {
7547 // This algorithm is not obvious. Here it is what we're trying to output:
7550 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7551 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7555 pshufd $0x4e, %xmm0, %xmm1
7560 DebugLoc dl = Op.getDebugLoc();
7561 LLVMContext *Context = DAG.getContext();
7563 // Build some magic constants.
7564 SmallVector<Constant*,4> CV0;
7565 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7566 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7567 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7568 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7569 Constant *C0 = ConstantVector::get(CV0);
7570 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7572 SmallVector<Constant*,2> CV1;
7574 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7576 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7577 Constant *C1 = ConstantVector::get(CV1);
7578 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7580 // Load the 64-bit value into an XMM register.
7581 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7583 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7584 MachinePointerInfo::getConstantPool(),
7585 false, false, false, 16);
7586 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7587 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7590 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7591 MachinePointerInfo::getConstantPool(),
7592 false, false, false, 16);
7593 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7594 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7597 if (Subtarget->hasSSE3()) {
7598 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7599 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7601 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7602 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7604 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7605 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7609 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7610 DAG.getIntPtrConstant(0));
7613 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7614 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7615 SelectionDAG &DAG) const {
7616 DebugLoc dl = Op.getDebugLoc();
7617 // FP constant to bias correct the final result.
7618 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7621 // Load the 32-bit value into an XMM register.
7622 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7625 // Zero out the upper parts of the register.
7626 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7628 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7629 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7630 DAG.getIntPtrConstant(0));
7632 // Or the load with the bias.
7633 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7634 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7635 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7637 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7638 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7639 MVT::v2f64, Bias)));
7640 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7641 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7642 DAG.getIntPtrConstant(0));
7644 // Subtract the bias.
7645 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7647 // Handle final rounding.
7648 EVT DestVT = Op.getValueType();
7650 if (DestVT.bitsLT(MVT::f64)) {
7651 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7652 DAG.getIntPtrConstant(0));
7653 } else if (DestVT.bitsGT(MVT::f64)) {
7654 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7657 // Handle final rounding.
7661 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7662 SelectionDAG &DAG) const {
7663 SDValue N0 = Op.getOperand(0);
7664 DebugLoc dl = Op.getDebugLoc();
7666 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7667 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7668 // the optimization here.
7669 if (DAG.SignBitIsZero(N0))
7670 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7672 EVT SrcVT = N0.getValueType();
7673 EVT DstVT = Op.getValueType();
7674 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7675 return LowerUINT_TO_FP_i64(Op, DAG);
7676 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7677 return LowerUINT_TO_FP_i32(Op, DAG);
7678 else if (Subtarget->is64Bit() &&
7679 SrcVT == MVT::i64 && DstVT == MVT::f32)
7682 // Make a 64-bit buffer, and use it to build an FILD.
7683 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7684 if (SrcVT == MVT::i32) {
7685 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7686 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7687 getPointerTy(), StackSlot, WordOff);
7688 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7689 StackSlot, MachinePointerInfo(),
7691 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7692 OffsetSlot, MachinePointerInfo(),
7694 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7698 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7699 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7700 StackSlot, MachinePointerInfo(),
7702 // For i64 source, we need to add the appropriate power of 2 if the input
7703 // was negative. This is the same as the optimization in
7704 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7705 // we must be careful to do the computation in x87 extended precision, not
7706 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7707 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7708 MachineMemOperand *MMO =
7709 DAG.getMachineFunction()
7710 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7711 MachineMemOperand::MOLoad, 8, 8);
7713 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7714 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7715 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7718 APInt FF(32, 0x5F800000ULL);
7720 // Check whether the sign bit is set.
7721 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7722 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7725 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7726 SDValue FudgePtr = DAG.getConstantPool(
7727 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7730 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7731 SDValue Zero = DAG.getIntPtrConstant(0);
7732 SDValue Four = DAG.getIntPtrConstant(4);
7733 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7735 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7737 // Load the value out, extending it from f32 to f80.
7738 // FIXME: Avoid the extend by constructing the right constant pool?
7739 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7740 FudgePtr, MachinePointerInfo::getConstantPool(),
7741 MVT::f32, false, false, 4);
7742 // Extend everything to 80 bits to force it to be done on x87.
7743 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7744 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7747 std::pair<SDValue,SDValue> X86TargetLowering::
7748 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7749 DebugLoc DL = Op.getDebugLoc();
7751 EVT DstTy = Op.getValueType();
7754 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7758 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7759 DstTy.getSimpleVT() >= MVT::i16 &&
7760 "Unknown FP_TO_SINT to lower!");
7762 // These are really Legal.
7763 if (DstTy == MVT::i32 &&
7764 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7765 return std::make_pair(SDValue(), SDValue());
7766 if (Subtarget->is64Bit() &&
7767 DstTy == MVT::i64 &&
7768 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7769 return std::make_pair(SDValue(), SDValue());
7771 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7773 MachineFunction &MF = DAG.getMachineFunction();
7774 unsigned MemSize = DstTy.getSizeInBits()/8;
7775 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7776 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7781 switch (DstTy.getSimpleVT().SimpleTy) {
7782 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7783 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7784 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7785 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7788 SDValue Chain = DAG.getEntryNode();
7789 SDValue Value = Op.getOperand(0);
7790 EVT TheVT = Op.getOperand(0).getValueType();
7791 if (isScalarFPTypeInSSEReg(TheVT)) {
7792 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7793 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7794 MachinePointerInfo::getFixedStack(SSFI),
7796 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7798 Chain, StackSlot, DAG.getValueType(TheVT)
7801 MachineMemOperand *MMO =
7802 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7803 MachineMemOperand::MOLoad, MemSize, MemSize);
7804 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7806 Chain = Value.getValue(1);
7807 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7808 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7811 MachineMemOperand *MMO =
7812 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7813 MachineMemOperand::MOStore, MemSize, MemSize);
7815 // Build the FP_TO_INT*_IN_MEM
7816 SDValue Ops[] = { Chain, Value, StackSlot };
7817 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7818 Ops, 3, DstTy, MMO);
7820 return std::make_pair(FIST, StackSlot);
7823 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7824 SelectionDAG &DAG) const {
7825 if (Op.getValueType().isVector())
7828 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7829 SDValue FIST = Vals.first, StackSlot = Vals.second;
7830 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7831 if (FIST.getNode() == 0) return Op;
7834 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7835 FIST, StackSlot, MachinePointerInfo(),
7836 false, false, false, 0);
7839 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7840 SelectionDAG &DAG) const {
7841 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7842 SDValue FIST = Vals.first, StackSlot = Vals.second;
7843 assert(FIST.getNode() && "Unexpected failure");
7846 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7847 FIST, StackSlot, MachinePointerInfo(),
7848 false, false, false, 0);
7851 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7852 SelectionDAG &DAG) const {
7853 LLVMContext *Context = DAG.getContext();
7854 DebugLoc dl = Op.getDebugLoc();
7855 EVT VT = Op.getValueType();
7858 EltVT = VT.getVectorElementType();
7859 SmallVector<Constant*,4> CV;
7860 if (EltVT == MVT::f64) {
7861 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7864 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7867 Constant *C = ConstantVector::get(CV);
7868 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7869 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7870 MachinePointerInfo::getConstantPool(),
7871 false, false, false, 16);
7872 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7875 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7876 LLVMContext *Context = DAG.getContext();
7877 DebugLoc dl = Op.getDebugLoc();
7878 EVT VT = Op.getValueType();
7880 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7881 if (VT.isVector()) {
7882 EltVT = VT.getVectorElementType();
7883 NumElts = VT.getVectorNumElements();
7885 SmallVector<Constant*,8> CV;
7886 if (EltVT == MVT::f64) {
7887 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7888 CV.assign(NumElts, C);
7890 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7891 CV.assign(NumElts, C);
7893 Constant *C = ConstantVector::get(CV);
7894 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7895 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7896 MachinePointerInfo::getConstantPool(),
7897 false, false, false, 16);
7898 if (VT.isVector()) {
7899 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7900 return DAG.getNode(ISD::BITCAST, dl, VT,
7901 DAG.getNode(ISD::XOR, dl, XORVT,
7902 DAG.getNode(ISD::BITCAST, dl, XORVT,
7904 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7906 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7910 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7911 LLVMContext *Context = DAG.getContext();
7912 SDValue Op0 = Op.getOperand(0);
7913 SDValue Op1 = Op.getOperand(1);
7914 DebugLoc dl = Op.getDebugLoc();
7915 EVT VT = Op.getValueType();
7916 EVT SrcVT = Op1.getValueType();
7918 // If second operand is smaller, extend it first.
7919 if (SrcVT.bitsLT(VT)) {
7920 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7923 // And if it is bigger, shrink it first.
7924 if (SrcVT.bitsGT(VT)) {
7925 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7929 // At this point the operands and the result should have the same
7930 // type, and that won't be f80 since that is not custom lowered.
7932 // First get the sign bit of second operand.
7933 SmallVector<Constant*,4> CV;
7934 if (SrcVT == MVT::f64) {
7935 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7936 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7938 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7939 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7940 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7941 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7943 Constant *C = ConstantVector::get(CV);
7944 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7945 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7946 MachinePointerInfo::getConstantPool(),
7947 false, false, false, 16);
7948 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7950 // Shift sign bit right or left if the two operands have different types.
7951 if (SrcVT.bitsGT(VT)) {
7952 // Op0 is MVT::f32, Op1 is MVT::f64.
7953 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7954 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7955 DAG.getConstant(32, MVT::i32));
7956 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7957 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7958 DAG.getIntPtrConstant(0));
7961 // Clear first operand sign bit.
7963 if (VT == MVT::f64) {
7964 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7965 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7967 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7968 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7969 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7970 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7972 C = ConstantVector::get(CV);
7973 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7974 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7975 MachinePointerInfo::getConstantPool(),
7976 false, false, false, 16);
7977 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7979 // Or the value with the sign bit.
7980 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
7983 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
7984 SDValue N0 = Op.getOperand(0);
7985 DebugLoc dl = Op.getDebugLoc();
7986 EVT VT = Op.getValueType();
7988 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
7989 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
7990 DAG.getConstant(1, VT));
7991 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
7994 /// Emit nodes that will be selected as "test Op0,Op0", or something
7996 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
7997 SelectionDAG &DAG) const {
7998 DebugLoc dl = Op.getDebugLoc();
8000 // CF and OF aren't always set the way we want. Determine which
8001 // of these we need.
8002 bool NeedCF = false;
8003 bool NeedOF = false;
8006 case X86::COND_A: case X86::COND_AE:
8007 case X86::COND_B: case X86::COND_BE:
8010 case X86::COND_G: case X86::COND_GE:
8011 case X86::COND_L: case X86::COND_LE:
8012 case X86::COND_O: case X86::COND_NO:
8017 // See if we can use the EFLAGS value from the operand instead of
8018 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8019 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8020 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8021 // Emit a CMP with 0, which is the TEST pattern.
8022 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8023 DAG.getConstant(0, Op.getValueType()));
8025 unsigned Opcode = 0;
8026 unsigned NumOperands = 0;
8027 switch (Op.getNode()->getOpcode()) {
8029 // Due to an isel shortcoming, be conservative if this add is likely to be
8030 // selected as part of a load-modify-store instruction. When the root node
8031 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8032 // uses of other nodes in the match, such as the ADD in this case. This
8033 // leads to the ADD being left around and reselected, with the result being
8034 // two adds in the output. Alas, even if none our users are stores, that
8035 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8036 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8037 // climbing the DAG back to the root, and it doesn't seem to be worth the
8039 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8040 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8041 if (UI->getOpcode() != ISD::CopyToReg &&
8042 UI->getOpcode() != ISD::SETCC &&
8043 UI->getOpcode() != ISD::STORE)
8046 if (ConstantSDNode *C =
8047 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8048 // An add of one will be selected as an INC.
8049 if (C->getAPIntValue() == 1) {
8050 Opcode = X86ISD::INC;
8055 // An add of negative one (subtract of one) will be selected as a DEC.
8056 if (C->getAPIntValue().isAllOnesValue()) {
8057 Opcode = X86ISD::DEC;
8063 // Otherwise use a regular EFLAGS-setting add.
8064 Opcode = X86ISD::ADD;
8068 // If the primary and result isn't used, don't bother using X86ISD::AND,
8069 // because a TEST instruction will be better.
8070 bool NonFlagUse = false;
8071 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8072 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8074 unsigned UOpNo = UI.getOperandNo();
8075 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8076 // Look pass truncate.
8077 UOpNo = User->use_begin().getOperandNo();
8078 User = *User->use_begin();
8081 if (User->getOpcode() != ISD::BRCOND &&
8082 User->getOpcode() != ISD::SETCC &&
8083 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8096 // Due to the ISEL shortcoming noted above, be conservative if this op is
8097 // likely to be selected as part of a load-modify-store instruction.
8098 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8099 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8100 if (UI->getOpcode() == ISD::STORE)
8103 // Otherwise use a regular EFLAGS-setting instruction.
8104 switch (Op.getNode()->getOpcode()) {
8105 default: llvm_unreachable("unexpected operator!");
8106 case ISD::SUB: Opcode = X86ISD::SUB; break;
8107 case ISD::OR: Opcode = X86ISD::OR; break;
8108 case ISD::XOR: Opcode = X86ISD::XOR; break;
8109 case ISD::AND: Opcode = X86ISD::AND; break;
8121 return SDValue(Op.getNode(), 1);
8128 // Emit a CMP with 0, which is the TEST pattern.
8129 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8130 DAG.getConstant(0, Op.getValueType()));
8132 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8133 SmallVector<SDValue, 4> Ops;
8134 for (unsigned i = 0; i != NumOperands; ++i)
8135 Ops.push_back(Op.getOperand(i));
8137 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8138 DAG.ReplaceAllUsesWith(Op, New);
8139 return SDValue(New.getNode(), 1);
8142 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8144 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8145 SelectionDAG &DAG) const {
8146 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8147 if (C->getAPIntValue() == 0)
8148 return EmitTest(Op0, X86CC, DAG);
8150 DebugLoc dl = Op0.getDebugLoc();
8151 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8154 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8155 /// if it's possible.
8156 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8157 DebugLoc dl, SelectionDAG &DAG) const {
8158 SDValue Op0 = And.getOperand(0);
8159 SDValue Op1 = And.getOperand(1);
8160 if (Op0.getOpcode() == ISD::TRUNCATE)
8161 Op0 = Op0.getOperand(0);
8162 if (Op1.getOpcode() == ISD::TRUNCATE)
8163 Op1 = Op1.getOperand(0);
8166 if (Op1.getOpcode() == ISD::SHL)
8167 std::swap(Op0, Op1);
8168 if (Op0.getOpcode() == ISD::SHL) {
8169 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8170 if (And00C->getZExtValue() == 1) {
8171 // If we looked past a truncate, check that it's only truncating away
8173 unsigned BitWidth = Op0.getValueSizeInBits();
8174 unsigned AndBitWidth = And.getValueSizeInBits();
8175 if (BitWidth > AndBitWidth) {
8176 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8177 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8178 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8182 RHS = Op0.getOperand(1);
8184 } else if (Op1.getOpcode() == ISD::Constant) {
8185 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8186 uint64_t AndRHSVal = AndRHS->getZExtValue();
8187 SDValue AndLHS = Op0;
8189 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8190 LHS = AndLHS.getOperand(0);
8191 RHS = AndLHS.getOperand(1);
8194 // Use BT if the immediate can't be encoded in a TEST instruction.
8195 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8197 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8201 if (LHS.getNode()) {
8202 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8203 // instruction. Since the shift amount is in-range-or-undefined, we know
8204 // that doing a bittest on the i32 value is ok. We extend to i32 because
8205 // the encoding for the i16 version is larger than the i32 version.
8206 // Also promote i16 to i32 for performance / code size reason.
8207 if (LHS.getValueType() == MVT::i8 ||
8208 LHS.getValueType() == MVT::i16)
8209 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8211 // If the operand types disagree, extend the shift amount to match. Since
8212 // BT ignores high bits (like shifts) we can use anyextend.
8213 if (LHS.getValueType() != RHS.getValueType())
8214 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8216 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8217 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8218 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8219 DAG.getConstant(Cond, MVT::i8), BT);
8225 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8227 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8229 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8230 SDValue Op0 = Op.getOperand(0);
8231 SDValue Op1 = Op.getOperand(1);
8232 DebugLoc dl = Op.getDebugLoc();
8233 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8235 // Optimize to BT if possible.
8236 // Lower (X & (1 << N)) == 0 to BT(X, N).
8237 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8238 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8239 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8240 Op1.getOpcode() == ISD::Constant &&
8241 cast<ConstantSDNode>(Op1)->isNullValue() &&
8242 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8243 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8244 if (NewSetCC.getNode())
8248 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8250 if (Op1.getOpcode() == ISD::Constant &&
8251 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8252 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8253 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8255 // If the input is a setcc, then reuse the input setcc or use a new one with
8256 // the inverted condition.
8257 if (Op0.getOpcode() == X86ISD::SETCC) {
8258 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8259 bool Invert = (CC == ISD::SETNE) ^
8260 cast<ConstantSDNode>(Op1)->isNullValue();
8261 if (!Invert) return Op0;
8263 CCode = X86::GetOppositeBranchCondition(CCode);
8264 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8265 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8269 bool isFP = Op1.getValueType().isFloatingPoint();
8270 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8271 if (X86CC == X86::COND_INVALID)
8274 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8275 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8276 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8279 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8280 // ones, and then concatenate the result back.
8281 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8282 EVT VT = Op.getValueType();
8284 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8285 "Unsupported value type for operation");
8287 int NumElems = VT.getVectorNumElements();
8288 DebugLoc dl = Op.getDebugLoc();
8289 SDValue CC = Op.getOperand(2);
8290 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8291 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8293 // Extract the LHS vectors
8294 SDValue LHS = Op.getOperand(0);
8295 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8296 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8298 // Extract the RHS vectors
8299 SDValue RHS = Op.getOperand(1);
8300 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8301 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8303 // Issue the operation on the smaller types and concatenate the result back
8304 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8305 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8306 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8307 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8308 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8312 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8314 SDValue Op0 = Op.getOperand(0);
8315 SDValue Op1 = Op.getOperand(1);
8316 SDValue CC = Op.getOperand(2);
8317 EVT VT = Op.getValueType();
8318 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8319 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8320 DebugLoc dl = Op.getDebugLoc();
8324 EVT EltVT = Op0.getValueType().getVectorElementType();
8325 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8327 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8330 // SSE Condition code mapping:
8339 switch (SetCCOpcode) {
8342 case ISD::SETEQ: SSECC = 0; break;
8344 case ISD::SETGT: Swap = true; // Fallthrough
8346 case ISD::SETOLT: SSECC = 1; break;
8348 case ISD::SETGE: Swap = true; // Fallthrough
8350 case ISD::SETOLE: SSECC = 2; break;
8351 case ISD::SETUO: SSECC = 3; break;
8353 case ISD::SETNE: SSECC = 4; break;
8354 case ISD::SETULE: Swap = true;
8355 case ISD::SETUGE: SSECC = 5; break;
8356 case ISD::SETULT: Swap = true;
8357 case ISD::SETUGT: SSECC = 6; break;
8358 case ISD::SETO: SSECC = 7; break;
8361 std::swap(Op0, Op1);
8363 // In the two special cases we can't handle, emit two comparisons.
8365 if (SetCCOpcode == ISD::SETUEQ) {
8367 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8368 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8369 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8370 } else if (SetCCOpcode == ISD::SETONE) {
8372 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8373 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8374 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8376 llvm_unreachable("Illegal FP comparison");
8378 // Handle all other FP comparisons here.
8379 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8382 // Break 256-bit integer vector compare into smaller ones.
8383 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8384 return Lower256IntVSETCC(Op, DAG);
8386 // We are handling one of the integer comparisons here. Since SSE only has
8387 // GT and EQ comparisons for integer, swapping operands and multiple
8388 // operations may be required for some comparisons.
8389 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8390 bool Swap = false, Invert = false, FlipSigns = false;
8392 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
8394 case MVT::i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8395 case MVT::i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8396 case MVT::i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8397 case MVT::i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8400 switch (SetCCOpcode) {
8402 case ISD::SETNE: Invert = true;
8403 case ISD::SETEQ: Opc = EQOpc; break;
8404 case ISD::SETLT: Swap = true;
8405 case ISD::SETGT: Opc = GTOpc; break;
8406 case ISD::SETGE: Swap = true;
8407 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8408 case ISD::SETULT: Swap = true;
8409 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8410 case ISD::SETUGE: Swap = true;
8411 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8414 std::swap(Op0, Op1);
8416 // Check that the operation in question is available (most are plain SSE2,
8417 // but PCMPGTQ and PCMPEQQ have different requirements).
8418 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42())
8420 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41())
8423 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8424 // bits of the inputs before performing those operations.
8426 EVT EltVT = VT.getVectorElementType();
8427 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8429 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8430 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8432 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8433 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8436 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8438 // If the logical-not of the result is required, perform that now.
8440 Result = DAG.getNOT(dl, Result, VT);
8445 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8446 static bool isX86LogicalCmp(SDValue Op) {
8447 unsigned Opc = Op.getNode()->getOpcode();
8448 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8450 if (Op.getResNo() == 1 &&
8451 (Opc == X86ISD::ADD ||
8452 Opc == X86ISD::SUB ||
8453 Opc == X86ISD::ADC ||
8454 Opc == X86ISD::SBB ||
8455 Opc == X86ISD::SMUL ||
8456 Opc == X86ISD::UMUL ||
8457 Opc == X86ISD::INC ||
8458 Opc == X86ISD::DEC ||
8459 Opc == X86ISD::OR ||
8460 Opc == X86ISD::XOR ||
8461 Opc == X86ISD::AND))
8464 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8470 static bool isZero(SDValue V) {
8471 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8472 return C && C->isNullValue();
8475 static bool isAllOnes(SDValue V) {
8476 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8477 return C && C->isAllOnesValue();
8480 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8481 bool addTest = true;
8482 SDValue Cond = Op.getOperand(0);
8483 SDValue Op1 = Op.getOperand(1);
8484 SDValue Op2 = Op.getOperand(2);
8485 DebugLoc DL = Op.getDebugLoc();
8488 if (Cond.getOpcode() == ISD::SETCC) {
8489 SDValue NewCond = LowerSETCC(Cond, DAG);
8490 if (NewCond.getNode())
8494 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8495 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8496 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8497 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8498 if (Cond.getOpcode() == X86ISD::SETCC &&
8499 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8500 isZero(Cond.getOperand(1).getOperand(1))) {
8501 SDValue Cmp = Cond.getOperand(1);
8503 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8505 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8506 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8507 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8509 SDValue CmpOp0 = Cmp.getOperand(0);
8510 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8511 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8513 SDValue Res = // Res = 0 or -1.
8514 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8515 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8517 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8518 Res = DAG.getNOT(DL, Res, Res.getValueType());
8520 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8521 if (N2C == 0 || !N2C->isNullValue())
8522 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8527 // Look past (and (setcc_carry (cmp ...)), 1).
8528 if (Cond.getOpcode() == ISD::AND &&
8529 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8530 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8531 if (C && C->getAPIntValue() == 1)
8532 Cond = Cond.getOperand(0);
8535 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8536 // setting operand in place of the X86ISD::SETCC.
8537 unsigned CondOpcode = Cond.getOpcode();
8538 if (CondOpcode == X86ISD::SETCC ||
8539 CondOpcode == X86ISD::SETCC_CARRY) {
8540 CC = Cond.getOperand(0);
8542 SDValue Cmp = Cond.getOperand(1);
8543 unsigned Opc = Cmp.getOpcode();
8544 EVT VT = Op.getValueType();
8546 bool IllegalFPCMov = false;
8547 if (VT.isFloatingPoint() && !VT.isVector() &&
8548 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8549 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8551 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8552 Opc == X86ISD::BT) { // FIXME
8556 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8557 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8558 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8559 Cond.getOperand(0).getValueType() != MVT::i8)) {
8560 SDValue LHS = Cond.getOperand(0);
8561 SDValue RHS = Cond.getOperand(1);
8565 switch (CondOpcode) {
8566 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8567 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8568 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8569 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8570 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8571 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8572 default: llvm_unreachable("unexpected overflowing operator");
8574 if (CondOpcode == ISD::UMULO)
8575 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8578 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8580 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8582 if (CondOpcode == ISD::UMULO)
8583 Cond = X86Op.getValue(2);
8585 Cond = X86Op.getValue(1);
8587 CC = DAG.getConstant(X86Cond, MVT::i8);
8592 // Look pass the truncate.
8593 if (Cond.getOpcode() == ISD::TRUNCATE)
8594 Cond = Cond.getOperand(0);
8596 // We know the result of AND is compared against zero. Try to match
8598 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8599 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8600 if (NewSetCC.getNode()) {
8601 CC = NewSetCC.getOperand(0);
8602 Cond = NewSetCC.getOperand(1);
8609 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8610 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8613 // a < b ? -1 : 0 -> RES = ~setcc_carry
8614 // a < b ? 0 : -1 -> RES = setcc_carry
8615 // a >= b ? -1 : 0 -> RES = setcc_carry
8616 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8617 if (Cond.getOpcode() == X86ISD::CMP) {
8618 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8620 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8621 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8622 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8623 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8624 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8625 return DAG.getNOT(DL, Res, Res.getValueType());
8630 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8631 // condition is true.
8632 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8633 SDValue Ops[] = { Op2, Op1, CC, Cond };
8634 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8637 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8638 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8639 // from the AND / OR.
8640 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8641 Opc = Op.getOpcode();
8642 if (Opc != ISD::OR && Opc != ISD::AND)
8644 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8645 Op.getOperand(0).hasOneUse() &&
8646 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8647 Op.getOperand(1).hasOneUse());
8650 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8651 // 1 and that the SETCC node has a single use.
8652 static bool isXor1OfSetCC(SDValue Op) {
8653 if (Op.getOpcode() != ISD::XOR)
8655 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8656 if (N1C && N1C->getAPIntValue() == 1) {
8657 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8658 Op.getOperand(0).hasOneUse();
8663 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8664 bool addTest = true;
8665 SDValue Chain = Op.getOperand(0);
8666 SDValue Cond = Op.getOperand(1);
8667 SDValue Dest = Op.getOperand(2);
8668 DebugLoc dl = Op.getDebugLoc();
8670 bool Inverted = false;
8672 if (Cond.getOpcode() == ISD::SETCC) {
8673 // Check for setcc([su]{add,sub,mul}o == 0).
8674 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8675 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8676 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8677 Cond.getOperand(0).getResNo() == 1 &&
8678 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8679 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8680 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8681 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8682 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8683 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8685 Cond = Cond.getOperand(0);
8687 SDValue NewCond = LowerSETCC(Cond, DAG);
8688 if (NewCond.getNode())
8693 // FIXME: LowerXALUO doesn't handle these!!
8694 else if (Cond.getOpcode() == X86ISD::ADD ||
8695 Cond.getOpcode() == X86ISD::SUB ||
8696 Cond.getOpcode() == X86ISD::SMUL ||
8697 Cond.getOpcode() == X86ISD::UMUL)
8698 Cond = LowerXALUO(Cond, DAG);
8701 // Look pass (and (setcc_carry (cmp ...)), 1).
8702 if (Cond.getOpcode() == ISD::AND &&
8703 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8704 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8705 if (C && C->getAPIntValue() == 1)
8706 Cond = Cond.getOperand(0);
8709 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8710 // setting operand in place of the X86ISD::SETCC.
8711 unsigned CondOpcode = Cond.getOpcode();
8712 if (CondOpcode == X86ISD::SETCC ||
8713 CondOpcode == X86ISD::SETCC_CARRY) {
8714 CC = Cond.getOperand(0);
8716 SDValue Cmp = Cond.getOperand(1);
8717 unsigned Opc = Cmp.getOpcode();
8718 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8719 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8723 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8727 // These can only come from an arithmetic instruction with overflow,
8728 // e.g. SADDO, UADDO.
8729 Cond = Cond.getNode()->getOperand(1);
8735 CondOpcode = Cond.getOpcode();
8736 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8737 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8738 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8739 Cond.getOperand(0).getValueType() != MVT::i8)) {
8740 SDValue LHS = Cond.getOperand(0);
8741 SDValue RHS = Cond.getOperand(1);
8745 switch (CondOpcode) {
8746 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8747 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8748 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8749 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8750 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8751 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8752 default: llvm_unreachable("unexpected overflowing operator");
8755 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8756 if (CondOpcode == ISD::UMULO)
8757 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8760 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8762 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8764 if (CondOpcode == ISD::UMULO)
8765 Cond = X86Op.getValue(2);
8767 Cond = X86Op.getValue(1);
8769 CC = DAG.getConstant(X86Cond, MVT::i8);
8773 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8774 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8775 if (CondOpc == ISD::OR) {
8776 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8777 // two branches instead of an explicit OR instruction with a
8779 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8780 isX86LogicalCmp(Cmp)) {
8781 CC = Cond.getOperand(0).getOperand(0);
8782 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8783 Chain, Dest, CC, Cmp);
8784 CC = Cond.getOperand(1).getOperand(0);
8788 } else { // ISD::AND
8789 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8790 // two branches instead of an explicit AND instruction with a
8791 // separate test. However, we only do this if this block doesn't
8792 // have a fall-through edge, because this requires an explicit
8793 // jmp when the condition is false.
8794 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8795 isX86LogicalCmp(Cmp) &&
8796 Op.getNode()->hasOneUse()) {
8797 X86::CondCode CCode =
8798 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8799 CCode = X86::GetOppositeBranchCondition(CCode);
8800 CC = DAG.getConstant(CCode, MVT::i8);
8801 SDNode *User = *Op.getNode()->use_begin();
8802 // Look for an unconditional branch following this conditional branch.
8803 // We need this because we need to reverse the successors in order
8804 // to implement FCMP_OEQ.
8805 if (User->getOpcode() == ISD::BR) {
8806 SDValue FalseBB = User->getOperand(1);
8808 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8809 assert(NewBR == User);
8813 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8814 Chain, Dest, CC, Cmp);
8815 X86::CondCode CCode =
8816 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8817 CCode = X86::GetOppositeBranchCondition(CCode);
8818 CC = DAG.getConstant(CCode, MVT::i8);
8824 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8825 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8826 // It should be transformed during dag combiner except when the condition
8827 // is set by a arithmetics with overflow node.
8828 X86::CondCode CCode =
8829 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8830 CCode = X86::GetOppositeBranchCondition(CCode);
8831 CC = DAG.getConstant(CCode, MVT::i8);
8832 Cond = Cond.getOperand(0).getOperand(1);
8834 } else if (Cond.getOpcode() == ISD::SETCC &&
8835 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8836 // For FCMP_OEQ, we can emit
8837 // two branches instead of an explicit AND instruction with a
8838 // separate test. However, we only do this if this block doesn't
8839 // have a fall-through edge, because this requires an explicit
8840 // jmp when the condition is false.
8841 if (Op.getNode()->hasOneUse()) {
8842 SDNode *User = *Op.getNode()->use_begin();
8843 // Look for an unconditional branch following this conditional branch.
8844 // We need this because we need to reverse the successors in order
8845 // to implement FCMP_OEQ.
8846 if (User->getOpcode() == ISD::BR) {
8847 SDValue FalseBB = User->getOperand(1);
8849 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8850 assert(NewBR == User);
8854 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8855 Cond.getOperand(0), Cond.getOperand(1));
8856 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8857 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8858 Chain, Dest, CC, Cmp);
8859 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8864 } else if (Cond.getOpcode() == ISD::SETCC &&
8865 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8866 // For FCMP_UNE, we can emit
8867 // two branches instead of an explicit AND instruction with a
8868 // separate test. However, we only do this if this block doesn't
8869 // have a fall-through edge, because this requires an explicit
8870 // jmp when the condition is false.
8871 if (Op.getNode()->hasOneUse()) {
8872 SDNode *User = *Op.getNode()->use_begin();
8873 // Look for an unconditional branch following this conditional branch.
8874 // We need this because we need to reverse the successors in order
8875 // to implement FCMP_UNE.
8876 if (User->getOpcode() == ISD::BR) {
8877 SDValue FalseBB = User->getOperand(1);
8879 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8880 assert(NewBR == User);
8883 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8884 Cond.getOperand(0), Cond.getOperand(1));
8885 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8886 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8887 Chain, Dest, CC, Cmp);
8888 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8898 // Look pass the truncate.
8899 if (Cond.getOpcode() == ISD::TRUNCATE)
8900 Cond = Cond.getOperand(0);
8902 // We know the result of AND is compared against zero. Try to match
8904 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8905 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8906 if (NewSetCC.getNode()) {
8907 CC = NewSetCC.getOperand(0);
8908 Cond = NewSetCC.getOperand(1);
8915 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8916 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8918 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8919 Chain, Dest, CC, Cond);
8923 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8924 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8925 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8926 // that the guard pages used by the OS virtual memory manager are allocated in
8927 // correct sequence.
8929 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8930 SelectionDAG &DAG) const {
8931 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8932 getTargetMachine().Options.EnableSegmentedStacks) &&
8933 "This should be used only on Windows targets or when segmented stacks "
8935 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8936 DebugLoc dl = Op.getDebugLoc();
8939 SDValue Chain = Op.getOperand(0);
8940 SDValue Size = Op.getOperand(1);
8941 // FIXME: Ensure alignment here
8943 bool Is64Bit = Subtarget->is64Bit();
8944 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8946 if (getTargetMachine().Options.EnableSegmentedStacks) {
8947 MachineFunction &MF = DAG.getMachineFunction();
8948 MachineRegisterInfo &MRI = MF.getRegInfo();
8951 // The 64 bit implementation of segmented stacks needs to clobber both r10
8952 // r11. This makes it impossible to use it along with nested parameters.
8953 const Function *F = MF.getFunction();
8955 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8957 if (I->hasNestAttr())
8958 report_fatal_error("Cannot use segmented stacks with functions that "
8959 "have nested arguments.");
8962 const TargetRegisterClass *AddrRegClass =
8963 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8964 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8965 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8966 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8967 DAG.getRegister(Vreg, SPTy));
8968 SDValue Ops1[2] = { Value, Chain };
8969 return DAG.getMergeValues(Ops1, 2, dl);
8972 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8974 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8975 Flag = Chain.getValue(1);
8976 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8978 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8979 Flag = Chain.getValue(1);
8981 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8983 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8984 return DAG.getMergeValues(Ops1, 2, dl);
8988 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8989 MachineFunction &MF = DAG.getMachineFunction();
8990 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8992 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8993 DebugLoc DL = Op.getDebugLoc();
8995 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8996 // vastart just stores the address of the VarArgsFrameIndex slot into the
8997 // memory location argument.
8998 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9000 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9001 MachinePointerInfo(SV), false, false, 0);
9005 // gp_offset (0 - 6 * 8)
9006 // fp_offset (48 - 48 + 8 * 16)
9007 // overflow_arg_area (point to parameters coming in memory).
9009 SmallVector<SDValue, 8> MemOps;
9010 SDValue FIN = Op.getOperand(1);
9012 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9013 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9015 FIN, MachinePointerInfo(SV), false, false, 0);
9016 MemOps.push_back(Store);
9019 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9020 FIN, DAG.getIntPtrConstant(4));
9021 Store = DAG.getStore(Op.getOperand(0), DL,
9022 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9024 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9025 MemOps.push_back(Store);
9027 // Store ptr to overflow_arg_area
9028 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9029 FIN, DAG.getIntPtrConstant(4));
9030 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9032 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9033 MachinePointerInfo(SV, 8),
9035 MemOps.push_back(Store);
9037 // Store ptr to reg_save_area.
9038 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9039 FIN, DAG.getIntPtrConstant(8));
9040 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9042 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9043 MachinePointerInfo(SV, 16), false, false, 0);
9044 MemOps.push_back(Store);
9045 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9046 &MemOps[0], MemOps.size());
9049 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9050 assert(Subtarget->is64Bit() &&
9051 "LowerVAARG only handles 64-bit va_arg!");
9052 assert((Subtarget->isTargetLinux() ||
9053 Subtarget->isTargetDarwin()) &&
9054 "Unhandled target in LowerVAARG");
9055 assert(Op.getNode()->getNumOperands() == 4);
9056 SDValue Chain = Op.getOperand(0);
9057 SDValue SrcPtr = Op.getOperand(1);
9058 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9059 unsigned Align = Op.getConstantOperandVal(3);
9060 DebugLoc dl = Op.getDebugLoc();
9062 EVT ArgVT = Op.getNode()->getValueType(0);
9063 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9064 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9067 // Decide which area this value should be read from.
9068 // TODO: Implement the AMD64 ABI in its entirety. This simple
9069 // selection mechanism works only for the basic types.
9070 if (ArgVT == MVT::f80) {
9071 llvm_unreachable("va_arg for f80 not yet implemented");
9072 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9073 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9074 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9075 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9077 llvm_unreachable("Unhandled argument type in LowerVAARG");
9081 // Sanity Check: Make sure using fp_offset makes sense.
9082 assert(!getTargetMachine().Options.UseSoftFloat &&
9083 !(DAG.getMachineFunction()
9084 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9085 Subtarget->hasSSE1());
9088 // Insert VAARG_64 node into the DAG
9089 // VAARG_64 returns two values: Variable Argument Address, Chain
9090 SmallVector<SDValue, 11> InstOps;
9091 InstOps.push_back(Chain);
9092 InstOps.push_back(SrcPtr);
9093 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9094 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9095 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9096 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9097 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9098 VTs, &InstOps[0], InstOps.size(),
9100 MachinePointerInfo(SV),
9105 Chain = VAARG.getValue(1);
9107 // Load the next argument and return it
9108 return DAG.getLoad(ArgVT, dl,
9111 MachinePointerInfo(),
9112 false, false, false, 0);
9115 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9116 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9117 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9118 SDValue Chain = Op.getOperand(0);
9119 SDValue DstPtr = Op.getOperand(1);
9120 SDValue SrcPtr = Op.getOperand(2);
9121 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9122 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9123 DebugLoc DL = Op.getDebugLoc();
9125 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9126 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9128 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9132 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9133 DebugLoc dl = Op.getDebugLoc();
9134 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9136 default: return SDValue(); // Don't custom lower most intrinsics.
9137 // Comparison intrinsics.
9138 case Intrinsic::x86_sse_comieq_ss:
9139 case Intrinsic::x86_sse_comilt_ss:
9140 case Intrinsic::x86_sse_comile_ss:
9141 case Intrinsic::x86_sse_comigt_ss:
9142 case Intrinsic::x86_sse_comige_ss:
9143 case Intrinsic::x86_sse_comineq_ss:
9144 case Intrinsic::x86_sse_ucomieq_ss:
9145 case Intrinsic::x86_sse_ucomilt_ss:
9146 case Intrinsic::x86_sse_ucomile_ss:
9147 case Intrinsic::x86_sse_ucomigt_ss:
9148 case Intrinsic::x86_sse_ucomige_ss:
9149 case Intrinsic::x86_sse_ucomineq_ss:
9150 case Intrinsic::x86_sse2_comieq_sd:
9151 case Intrinsic::x86_sse2_comilt_sd:
9152 case Intrinsic::x86_sse2_comile_sd:
9153 case Intrinsic::x86_sse2_comigt_sd:
9154 case Intrinsic::x86_sse2_comige_sd:
9155 case Intrinsic::x86_sse2_comineq_sd:
9156 case Intrinsic::x86_sse2_ucomieq_sd:
9157 case Intrinsic::x86_sse2_ucomilt_sd:
9158 case Intrinsic::x86_sse2_ucomile_sd:
9159 case Intrinsic::x86_sse2_ucomigt_sd:
9160 case Intrinsic::x86_sse2_ucomige_sd:
9161 case Intrinsic::x86_sse2_ucomineq_sd: {
9163 ISD::CondCode CC = ISD::SETCC_INVALID;
9166 case Intrinsic::x86_sse_comieq_ss:
9167 case Intrinsic::x86_sse2_comieq_sd:
9171 case Intrinsic::x86_sse_comilt_ss:
9172 case Intrinsic::x86_sse2_comilt_sd:
9176 case Intrinsic::x86_sse_comile_ss:
9177 case Intrinsic::x86_sse2_comile_sd:
9181 case Intrinsic::x86_sse_comigt_ss:
9182 case Intrinsic::x86_sse2_comigt_sd:
9186 case Intrinsic::x86_sse_comige_ss:
9187 case Intrinsic::x86_sse2_comige_sd:
9191 case Intrinsic::x86_sse_comineq_ss:
9192 case Intrinsic::x86_sse2_comineq_sd:
9196 case Intrinsic::x86_sse_ucomieq_ss:
9197 case Intrinsic::x86_sse2_ucomieq_sd:
9198 Opc = X86ISD::UCOMI;
9201 case Intrinsic::x86_sse_ucomilt_ss:
9202 case Intrinsic::x86_sse2_ucomilt_sd:
9203 Opc = X86ISD::UCOMI;
9206 case Intrinsic::x86_sse_ucomile_ss:
9207 case Intrinsic::x86_sse2_ucomile_sd:
9208 Opc = X86ISD::UCOMI;
9211 case Intrinsic::x86_sse_ucomigt_ss:
9212 case Intrinsic::x86_sse2_ucomigt_sd:
9213 Opc = X86ISD::UCOMI;
9216 case Intrinsic::x86_sse_ucomige_ss:
9217 case Intrinsic::x86_sse2_ucomige_sd:
9218 Opc = X86ISD::UCOMI;
9221 case Intrinsic::x86_sse_ucomineq_ss:
9222 case Intrinsic::x86_sse2_ucomineq_sd:
9223 Opc = X86ISD::UCOMI;
9228 SDValue LHS = Op.getOperand(1);
9229 SDValue RHS = Op.getOperand(2);
9230 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9231 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9232 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9233 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9234 DAG.getConstant(X86CC, MVT::i8), Cond);
9235 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9237 // Arithmetic intrinsics.
9238 case Intrinsic::x86_sse3_hadd_ps:
9239 case Intrinsic::x86_sse3_hadd_pd:
9240 case Intrinsic::x86_avx_hadd_ps_256:
9241 case Intrinsic::x86_avx_hadd_pd_256:
9242 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9243 Op.getOperand(1), Op.getOperand(2));
9244 case Intrinsic::x86_sse3_hsub_ps:
9245 case Intrinsic::x86_sse3_hsub_pd:
9246 case Intrinsic::x86_avx_hsub_ps_256:
9247 case Intrinsic::x86_avx_hsub_pd_256:
9248 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9249 Op.getOperand(1), Op.getOperand(2));
9250 case Intrinsic::x86_avx2_psllv_d:
9251 case Intrinsic::x86_avx2_psllv_q:
9252 case Intrinsic::x86_avx2_psllv_d_256:
9253 case Intrinsic::x86_avx2_psllv_q_256:
9254 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9255 Op.getOperand(1), Op.getOperand(2));
9256 case Intrinsic::x86_avx2_psrlv_d:
9257 case Intrinsic::x86_avx2_psrlv_q:
9258 case Intrinsic::x86_avx2_psrlv_d_256:
9259 case Intrinsic::x86_avx2_psrlv_q_256:
9260 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9261 Op.getOperand(1), Op.getOperand(2));
9262 case Intrinsic::x86_avx2_psrav_d:
9263 case Intrinsic::x86_avx2_psrav_d_256:
9264 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9265 Op.getOperand(1), Op.getOperand(2));
9267 // ptest and testp intrinsics. The intrinsic these come from are designed to
9268 // return an integer value, not just an instruction so lower it to the ptest
9269 // or testp pattern and a setcc for the result.
9270 case Intrinsic::x86_sse41_ptestz:
9271 case Intrinsic::x86_sse41_ptestc:
9272 case Intrinsic::x86_sse41_ptestnzc:
9273 case Intrinsic::x86_avx_ptestz_256:
9274 case Intrinsic::x86_avx_ptestc_256:
9275 case Intrinsic::x86_avx_ptestnzc_256:
9276 case Intrinsic::x86_avx_vtestz_ps:
9277 case Intrinsic::x86_avx_vtestc_ps:
9278 case Intrinsic::x86_avx_vtestnzc_ps:
9279 case Intrinsic::x86_avx_vtestz_pd:
9280 case Intrinsic::x86_avx_vtestc_pd:
9281 case Intrinsic::x86_avx_vtestnzc_pd:
9282 case Intrinsic::x86_avx_vtestz_ps_256:
9283 case Intrinsic::x86_avx_vtestc_ps_256:
9284 case Intrinsic::x86_avx_vtestnzc_ps_256:
9285 case Intrinsic::x86_avx_vtestz_pd_256:
9286 case Intrinsic::x86_avx_vtestc_pd_256:
9287 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9288 bool IsTestPacked = false;
9291 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9292 case Intrinsic::x86_avx_vtestz_ps:
9293 case Intrinsic::x86_avx_vtestz_pd:
9294 case Intrinsic::x86_avx_vtestz_ps_256:
9295 case Intrinsic::x86_avx_vtestz_pd_256:
9296 IsTestPacked = true; // Fallthrough
9297 case Intrinsic::x86_sse41_ptestz:
9298 case Intrinsic::x86_avx_ptestz_256:
9300 X86CC = X86::COND_E;
9302 case Intrinsic::x86_avx_vtestc_ps:
9303 case Intrinsic::x86_avx_vtestc_pd:
9304 case Intrinsic::x86_avx_vtestc_ps_256:
9305 case Intrinsic::x86_avx_vtestc_pd_256:
9306 IsTestPacked = true; // Fallthrough
9307 case Intrinsic::x86_sse41_ptestc:
9308 case Intrinsic::x86_avx_ptestc_256:
9310 X86CC = X86::COND_B;
9312 case Intrinsic::x86_avx_vtestnzc_ps:
9313 case Intrinsic::x86_avx_vtestnzc_pd:
9314 case Intrinsic::x86_avx_vtestnzc_ps_256:
9315 case Intrinsic::x86_avx_vtestnzc_pd_256:
9316 IsTestPacked = true; // Fallthrough
9317 case Intrinsic::x86_sse41_ptestnzc:
9318 case Intrinsic::x86_avx_ptestnzc_256:
9320 X86CC = X86::COND_A;
9324 SDValue LHS = Op.getOperand(1);
9325 SDValue RHS = Op.getOperand(2);
9326 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9327 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9328 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9329 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9330 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9333 // Fix vector shift instructions where the last operand is a non-immediate
9335 case Intrinsic::x86_avx2_pslli_w:
9336 case Intrinsic::x86_avx2_pslli_d:
9337 case Intrinsic::x86_avx2_pslli_q:
9338 case Intrinsic::x86_avx2_psrli_w:
9339 case Intrinsic::x86_avx2_psrli_d:
9340 case Intrinsic::x86_avx2_psrli_q:
9341 case Intrinsic::x86_avx2_psrai_w:
9342 case Intrinsic::x86_avx2_psrai_d:
9343 case Intrinsic::x86_sse2_pslli_w:
9344 case Intrinsic::x86_sse2_pslli_d:
9345 case Intrinsic::x86_sse2_pslli_q:
9346 case Intrinsic::x86_sse2_psrli_w:
9347 case Intrinsic::x86_sse2_psrli_d:
9348 case Intrinsic::x86_sse2_psrli_q:
9349 case Intrinsic::x86_sse2_psrai_w:
9350 case Intrinsic::x86_sse2_psrai_d:
9351 case Intrinsic::x86_mmx_pslli_w:
9352 case Intrinsic::x86_mmx_pslli_d:
9353 case Intrinsic::x86_mmx_pslli_q:
9354 case Intrinsic::x86_mmx_psrli_w:
9355 case Intrinsic::x86_mmx_psrli_d:
9356 case Intrinsic::x86_mmx_psrli_q:
9357 case Intrinsic::x86_mmx_psrai_w:
9358 case Intrinsic::x86_mmx_psrai_d: {
9359 SDValue ShAmt = Op.getOperand(2);
9360 if (isa<ConstantSDNode>(ShAmt))
9363 unsigned NewIntNo = 0;
9364 EVT ShAmtVT = MVT::v4i32;
9366 case Intrinsic::x86_sse2_pslli_w:
9367 NewIntNo = Intrinsic::x86_sse2_psll_w;
9369 case Intrinsic::x86_sse2_pslli_d:
9370 NewIntNo = Intrinsic::x86_sse2_psll_d;
9372 case Intrinsic::x86_sse2_pslli_q:
9373 NewIntNo = Intrinsic::x86_sse2_psll_q;
9375 case Intrinsic::x86_sse2_psrli_w:
9376 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9378 case Intrinsic::x86_sse2_psrli_d:
9379 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9381 case Intrinsic::x86_sse2_psrli_q:
9382 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9384 case Intrinsic::x86_sse2_psrai_w:
9385 NewIntNo = Intrinsic::x86_sse2_psra_w;
9387 case Intrinsic::x86_sse2_psrai_d:
9388 NewIntNo = Intrinsic::x86_sse2_psra_d;
9390 case Intrinsic::x86_avx2_pslli_w:
9391 NewIntNo = Intrinsic::x86_avx2_psll_w;
9393 case Intrinsic::x86_avx2_pslli_d:
9394 NewIntNo = Intrinsic::x86_avx2_psll_d;
9396 case Intrinsic::x86_avx2_pslli_q:
9397 NewIntNo = Intrinsic::x86_avx2_psll_q;
9399 case Intrinsic::x86_avx2_psrli_w:
9400 NewIntNo = Intrinsic::x86_avx2_psrl_w;
9402 case Intrinsic::x86_avx2_psrli_d:
9403 NewIntNo = Intrinsic::x86_avx2_psrl_d;
9405 case Intrinsic::x86_avx2_psrli_q:
9406 NewIntNo = Intrinsic::x86_avx2_psrl_q;
9408 case Intrinsic::x86_avx2_psrai_w:
9409 NewIntNo = Intrinsic::x86_avx2_psra_w;
9411 case Intrinsic::x86_avx2_psrai_d:
9412 NewIntNo = Intrinsic::x86_avx2_psra_d;
9415 ShAmtVT = MVT::v2i32;
9417 case Intrinsic::x86_mmx_pslli_w:
9418 NewIntNo = Intrinsic::x86_mmx_psll_w;
9420 case Intrinsic::x86_mmx_pslli_d:
9421 NewIntNo = Intrinsic::x86_mmx_psll_d;
9423 case Intrinsic::x86_mmx_pslli_q:
9424 NewIntNo = Intrinsic::x86_mmx_psll_q;
9426 case Intrinsic::x86_mmx_psrli_w:
9427 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9429 case Intrinsic::x86_mmx_psrli_d:
9430 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9432 case Intrinsic::x86_mmx_psrli_q:
9433 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9435 case Intrinsic::x86_mmx_psrai_w:
9436 NewIntNo = Intrinsic::x86_mmx_psra_w;
9438 case Intrinsic::x86_mmx_psrai_d:
9439 NewIntNo = Intrinsic::x86_mmx_psra_d;
9441 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9447 // The vector shift intrinsics with scalars uses 32b shift amounts but
9448 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9452 ShOps[1] = DAG.getConstant(0, MVT::i32);
9453 if (ShAmtVT == MVT::v4i32) {
9454 ShOps[2] = DAG.getUNDEF(MVT::i32);
9455 ShOps[3] = DAG.getUNDEF(MVT::i32);
9456 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9458 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9459 // FIXME this must be lowered to get rid of the invalid type.
9462 EVT VT = Op.getValueType();
9463 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9464 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9465 DAG.getConstant(NewIntNo, MVT::i32),
9466 Op.getOperand(1), ShAmt);
9471 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9472 SelectionDAG &DAG) const {
9473 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9474 MFI->setReturnAddressIsTaken(true);
9476 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9477 DebugLoc dl = Op.getDebugLoc();
9480 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9482 DAG.getConstant(TD->getPointerSize(),
9483 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9484 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9485 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9487 MachinePointerInfo(), false, false, false, 0);
9490 // Just load the return address.
9491 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9492 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9493 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9496 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9497 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9498 MFI->setFrameAddressIsTaken(true);
9500 EVT VT = Op.getValueType();
9501 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9502 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9503 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9504 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9506 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9507 MachinePointerInfo(),
9508 false, false, false, 0);
9512 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9513 SelectionDAG &DAG) const {
9514 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9517 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9518 MachineFunction &MF = DAG.getMachineFunction();
9519 SDValue Chain = Op.getOperand(0);
9520 SDValue Offset = Op.getOperand(1);
9521 SDValue Handler = Op.getOperand(2);
9522 DebugLoc dl = Op.getDebugLoc();
9524 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9525 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9527 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9529 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9530 DAG.getIntPtrConstant(TD->getPointerSize()));
9531 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9532 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9534 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9535 MF.getRegInfo().addLiveOut(StoreAddrReg);
9537 return DAG.getNode(X86ISD::EH_RETURN, dl,
9539 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9542 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9543 SelectionDAG &DAG) const {
9544 return Op.getOperand(0);
9547 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9548 SelectionDAG &DAG) const {
9549 SDValue Root = Op.getOperand(0);
9550 SDValue Trmp = Op.getOperand(1); // trampoline
9551 SDValue FPtr = Op.getOperand(2); // nested function
9552 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9553 DebugLoc dl = Op.getDebugLoc();
9555 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9557 if (Subtarget->is64Bit()) {
9558 SDValue OutChains[6];
9560 // Large code-model.
9561 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9562 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9564 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9565 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9567 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9569 // Load the pointer to the nested function into R11.
9570 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9571 SDValue Addr = Trmp;
9572 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9573 Addr, MachinePointerInfo(TrmpAddr),
9576 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9577 DAG.getConstant(2, MVT::i64));
9578 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9579 MachinePointerInfo(TrmpAddr, 2),
9582 // Load the 'nest' parameter value into R10.
9583 // R10 is specified in X86CallingConv.td
9584 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9585 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9586 DAG.getConstant(10, MVT::i64));
9587 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9588 Addr, MachinePointerInfo(TrmpAddr, 10),
9591 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9592 DAG.getConstant(12, MVT::i64));
9593 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9594 MachinePointerInfo(TrmpAddr, 12),
9597 // Jump to the nested function.
9598 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9599 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9600 DAG.getConstant(20, MVT::i64));
9601 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9602 Addr, MachinePointerInfo(TrmpAddr, 20),
9605 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9606 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9607 DAG.getConstant(22, MVT::i64));
9608 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9609 MachinePointerInfo(TrmpAddr, 22),
9612 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9614 const Function *Func =
9615 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9616 CallingConv::ID CC = Func->getCallingConv();
9621 llvm_unreachable("Unsupported calling convention");
9622 case CallingConv::C:
9623 case CallingConv::X86_StdCall: {
9624 // Pass 'nest' parameter in ECX.
9625 // Must be kept in sync with X86CallingConv.td
9628 // Check that ECX wasn't needed by an 'inreg' parameter.
9629 FunctionType *FTy = Func->getFunctionType();
9630 const AttrListPtr &Attrs = Func->getAttributes();
9632 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9633 unsigned InRegCount = 0;
9636 for (FunctionType::param_iterator I = FTy->param_begin(),
9637 E = FTy->param_end(); I != E; ++I, ++Idx)
9638 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9639 // FIXME: should only count parameters that are lowered to integers.
9640 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9642 if (InRegCount > 2) {
9643 report_fatal_error("Nest register in use - reduce number of inreg"
9649 case CallingConv::X86_FastCall:
9650 case CallingConv::X86_ThisCall:
9651 case CallingConv::Fast:
9652 // Pass 'nest' parameter in EAX.
9653 // Must be kept in sync with X86CallingConv.td
9658 SDValue OutChains[4];
9661 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9662 DAG.getConstant(10, MVT::i32));
9663 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9665 // This is storing the opcode for MOV32ri.
9666 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9667 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9668 OutChains[0] = DAG.getStore(Root, dl,
9669 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9670 Trmp, MachinePointerInfo(TrmpAddr),
9673 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9674 DAG.getConstant(1, MVT::i32));
9675 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9676 MachinePointerInfo(TrmpAddr, 1),
9679 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9680 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9681 DAG.getConstant(5, MVT::i32));
9682 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9683 MachinePointerInfo(TrmpAddr, 5),
9686 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9687 DAG.getConstant(6, MVT::i32));
9688 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9689 MachinePointerInfo(TrmpAddr, 6),
9692 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9696 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9697 SelectionDAG &DAG) const {
9699 The rounding mode is in bits 11:10 of FPSR, and has the following
9706 FLT_ROUNDS, on the other hand, expects the following:
9713 To perform the conversion, we do:
9714 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9717 MachineFunction &MF = DAG.getMachineFunction();
9718 const TargetMachine &TM = MF.getTarget();
9719 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9720 unsigned StackAlignment = TFI.getStackAlignment();
9721 EVT VT = Op.getValueType();
9722 DebugLoc DL = Op.getDebugLoc();
9724 // Save FP Control Word to stack slot
9725 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9726 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9729 MachineMemOperand *MMO =
9730 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9731 MachineMemOperand::MOStore, 2, 2);
9733 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9734 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9735 DAG.getVTList(MVT::Other),
9736 Ops, 2, MVT::i16, MMO);
9738 // Load FP Control Word from stack slot
9739 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9740 MachinePointerInfo(), false, false, false, 0);
9742 // Transform as necessary
9744 DAG.getNode(ISD::SRL, DL, MVT::i16,
9745 DAG.getNode(ISD::AND, DL, MVT::i16,
9746 CWD, DAG.getConstant(0x800, MVT::i16)),
9747 DAG.getConstant(11, MVT::i8));
9749 DAG.getNode(ISD::SRL, DL, MVT::i16,
9750 DAG.getNode(ISD::AND, DL, MVT::i16,
9751 CWD, DAG.getConstant(0x400, MVT::i16)),
9752 DAG.getConstant(9, MVT::i8));
9755 DAG.getNode(ISD::AND, DL, MVT::i16,
9756 DAG.getNode(ISD::ADD, DL, MVT::i16,
9757 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9758 DAG.getConstant(1, MVT::i16)),
9759 DAG.getConstant(3, MVT::i16));
9762 return DAG.getNode((VT.getSizeInBits() < 16 ?
9763 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9766 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9767 EVT VT = Op.getValueType();
9769 unsigned NumBits = VT.getSizeInBits();
9770 DebugLoc dl = Op.getDebugLoc();
9772 Op = Op.getOperand(0);
9773 if (VT == MVT::i8) {
9774 // Zero extend to i32 since there is not an i8 bsr.
9776 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9779 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9780 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9781 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9783 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9786 DAG.getConstant(NumBits+NumBits-1, OpVT),
9787 DAG.getConstant(X86::COND_E, MVT::i8),
9790 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9792 // Finally xor with NumBits-1.
9793 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9796 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9800 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
9801 SelectionDAG &DAG) const {
9802 EVT VT = Op.getValueType();
9804 unsigned NumBits = VT.getSizeInBits();
9805 DebugLoc dl = Op.getDebugLoc();
9807 Op = Op.getOperand(0);
9808 if (VT == MVT::i8) {
9809 // Zero extend to i32 since there is not an i8 bsr.
9811 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9814 // Issue a bsr (scan bits in reverse).
9815 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9816 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9818 // And xor with NumBits-1.
9819 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9822 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9826 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9827 EVT VT = Op.getValueType();
9828 unsigned NumBits = VT.getSizeInBits();
9829 DebugLoc dl = Op.getDebugLoc();
9830 Op = Op.getOperand(0);
9832 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9833 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
9834 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9836 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9839 DAG.getConstant(NumBits, VT),
9840 DAG.getConstant(X86::COND_E, MVT::i8),
9843 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
9846 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9847 // ones, and then concatenate the result back.
9848 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9849 EVT VT = Op.getValueType();
9851 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9852 "Unsupported value type for operation");
9854 int NumElems = VT.getVectorNumElements();
9855 DebugLoc dl = Op.getDebugLoc();
9856 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9857 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9859 // Extract the LHS vectors
9860 SDValue LHS = Op.getOperand(0);
9861 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9862 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9864 // Extract the RHS vectors
9865 SDValue RHS = Op.getOperand(1);
9866 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9867 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9869 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9870 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9872 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9873 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9874 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9877 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9878 assert(Op.getValueType().getSizeInBits() == 256 &&
9879 Op.getValueType().isInteger() &&
9880 "Only handle AVX 256-bit vector integer operation");
9881 return Lower256IntArith(Op, DAG);
9884 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9885 assert(Op.getValueType().getSizeInBits() == 256 &&
9886 Op.getValueType().isInteger() &&
9887 "Only handle AVX 256-bit vector integer operation");
9888 return Lower256IntArith(Op, DAG);
9891 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9892 EVT VT = Op.getValueType();
9894 // Decompose 256-bit ops into smaller 128-bit ops.
9895 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
9896 return Lower256IntArith(Op, DAG);
9898 DebugLoc dl = Op.getDebugLoc();
9900 SDValue A = Op.getOperand(0);
9901 SDValue B = Op.getOperand(1);
9903 if (VT == MVT::v4i64) {
9904 assert(Subtarget->hasAVX2() && "Lowering v4i64 multiply requires AVX2");
9906 // ulong2 Ahi = __builtin_ia32_psrlqi256( a, 32);
9907 // ulong2 Bhi = __builtin_ia32_psrlqi256( b, 32);
9908 // ulong2 AloBlo = __builtin_ia32_pmuludq256( a, b );
9909 // ulong2 AloBhi = __builtin_ia32_pmuludq256( a, Bhi );
9910 // ulong2 AhiBlo = __builtin_ia32_pmuludq256( Ahi, b );
9912 // AloBhi = __builtin_ia32_psllqi256( AloBhi, 32 );
9913 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 );
9914 // return AloBlo + AloBhi + AhiBlo;
9916 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9917 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9918 A, DAG.getConstant(32, MVT::i32));
9919 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9920 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9921 B, DAG.getConstant(32, MVT::i32));
9922 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9923 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9925 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9926 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9928 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9929 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
9931 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9932 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9933 AloBhi, DAG.getConstant(32, MVT::i32));
9934 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9935 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9936 AhiBlo, DAG.getConstant(32, MVT::i32));
9937 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9938 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9942 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9944 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9945 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9946 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9947 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9948 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9950 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9951 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9952 // return AloBlo + AloBhi + AhiBlo;
9954 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9955 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9956 A, DAG.getConstant(32, MVT::i32));
9957 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9958 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9959 B, DAG.getConstant(32, MVT::i32));
9960 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9961 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9963 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9964 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9966 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9967 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9969 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9970 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9971 AloBhi, DAG.getConstant(32, MVT::i32));
9972 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9973 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9974 AhiBlo, DAG.getConstant(32, MVT::i32));
9975 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9976 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9980 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9982 EVT VT = Op.getValueType();
9983 DebugLoc dl = Op.getDebugLoc();
9984 SDValue R = Op.getOperand(0);
9985 SDValue Amt = Op.getOperand(1);
9986 LLVMContext *Context = DAG.getContext();
9988 if (!Subtarget->hasSSE2())
9991 // Optimize shl/srl/sra with constant shift amount.
9992 if (isSplatVector(Amt.getNode())) {
9993 SDValue SclrAmt = Amt->getOperand(0);
9994 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
9995 uint64_t ShiftAmt = C->getZExtValue();
9997 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SHL) {
9998 // Make a large shift.
10000 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10001 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10002 R, DAG.getConstant(ShiftAmt, MVT::i32));
10003 // Zero out the rightmost bits.
10004 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U << ShiftAmt),
10006 return DAG.getNode(ISD::AND, dl, VT, SHL,
10007 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10010 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
10011 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10012 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10013 R, DAG.getConstant(ShiftAmt, MVT::i32));
10015 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
10016 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10017 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10018 R, DAG.getConstant(ShiftAmt, MVT::i32));
10020 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
10021 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10022 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10023 R, DAG.getConstant(ShiftAmt, MVT::i32));
10025 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRL) {
10026 // Make a large shift.
10028 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10029 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10030 R, DAG.getConstant(ShiftAmt, MVT::i32));
10031 // Zero out the leftmost bits.
10032 SmallVector<SDValue, 16> V(16, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10034 return DAG.getNode(ISD::AND, dl, VT, SRL,
10035 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10038 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
10039 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10040 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10041 R, DAG.getConstant(ShiftAmt, MVT::i32));
10043 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
10044 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10045 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
10046 R, DAG.getConstant(ShiftAmt, MVT::i32));
10048 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
10049 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10050 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10051 R, DAG.getConstant(ShiftAmt, MVT::i32));
10053 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
10054 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10055 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
10056 R, DAG.getConstant(ShiftAmt, MVT::i32));
10058 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
10059 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10060 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
10061 R, DAG.getConstant(ShiftAmt, MVT::i32));
10063 if (VT == MVT::v16i8 && Op.getOpcode() == ISD::SRA) {
10064 if (ShiftAmt == 7) {
10065 // R s>> 7 === R s< 0
10066 SDValue Zeros = getZeroVector(VT, /* HasSSE2 */true,
10067 /* HasAVX2 */false, DAG, dl);
10068 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
10071 // R s>> a === ((R u>> a) ^ m) - m
10072 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10073 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10075 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10076 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10077 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10081 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10082 if (Op.getOpcode() == ISD::SHL) {
10083 // Make a large shift.
10085 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10086 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
10087 R, DAG.getConstant(ShiftAmt, MVT::i32));
10088 // Zero out the rightmost bits.
10089 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U << ShiftAmt),
10091 return DAG.getNode(ISD::AND, dl, VT, SHL,
10092 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10094 if (Op.getOpcode() == ISD::SRL) {
10095 // Make a large shift.
10097 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10098 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
10099 R, DAG.getConstant(ShiftAmt, MVT::i32));
10100 // Zero out the leftmost bits.
10101 SmallVector<SDValue, 32> V(32, DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10103 return DAG.getNode(ISD::AND, dl, VT, SRL,
10104 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10106 if (Op.getOpcode() == ISD::SRA) {
10107 if (ShiftAmt == 7) {
10108 // R s>> 7 === R s< 0
10109 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */,
10110 true /* HasAVX2 */, DAG, dl);
10111 return DAG.getNode(X86ISD::PCMPGTB, dl, VT, Zeros, R);
10114 // R s>> a === ((R u>> a) ^ m) - m
10115 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10116 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10118 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10119 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10120 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10127 // Lower SHL with variable shift amount.
10128 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10129 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10130 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10131 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
10133 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
10135 std::vector<Constant*> CV(4, CI);
10136 Constant *C = ConstantVector::get(CV);
10137 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10138 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10139 MachinePointerInfo::getConstantPool(),
10140 false, false, false, 16);
10142 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10143 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10144 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10145 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10147 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10148 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10151 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10152 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10153 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
10155 // Turn 'a' into a mask suitable for VSELECT
10156 SDValue VSelM = DAG.getConstant(0x80, VT);
10157 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10158 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10159 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10162 SDValue CM1 = DAG.getConstant(0x0f, VT);
10163 SDValue CM2 = DAG.getConstant(0x3f, VT);
10165 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10166 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10167 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10168 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10169 DAG.getConstant(4, MVT::i32));
10170 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10173 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10174 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10175 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10176 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10179 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10180 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10181 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10182 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
10183 DAG.getConstant(2, MVT::i32));
10184 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10187 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10188 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10189 OpVSel = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10190 DAG.getConstant(Intrinsic::x86_sse2_pcmpeq_b, MVT::i32),
10193 // return VSELECT(r, r+r, a);
10194 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10195 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10199 // Decompose 256-bit shifts into smaller 128-bit shifts.
10200 if (VT.getSizeInBits() == 256) {
10201 int NumElems = VT.getVectorNumElements();
10202 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10203 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10205 // Extract the two vectors
10206 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10207 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10210 // Recreate the shift amount vectors
10211 SDValue Amt1, Amt2;
10212 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10213 // Constant shift amount
10214 SmallVector<SDValue, 4> Amt1Csts;
10215 SmallVector<SDValue, 4> Amt2Csts;
10216 for (int i = 0; i < NumElems/2; ++i)
10217 Amt1Csts.push_back(Amt->getOperand(i));
10218 for (int i = NumElems/2; i < NumElems; ++i)
10219 Amt2Csts.push_back(Amt->getOperand(i));
10221 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10222 &Amt1Csts[0], NumElems/2);
10223 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10224 &Amt2Csts[0], NumElems/2);
10226 // Variable shift amount
10227 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10228 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10232 // Issue new vector shifts for the smaller types
10233 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10234 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10236 // Concatenate the result back
10237 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10243 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10244 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10245 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10246 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10247 // has only one use.
10248 SDNode *N = Op.getNode();
10249 SDValue LHS = N->getOperand(0);
10250 SDValue RHS = N->getOperand(1);
10251 unsigned BaseOp = 0;
10253 DebugLoc DL = Op.getDebugLoc();
10254 switch (Op.getOpcode()) {
10255 default: llvm_unreachable("Unknown ovf instruction!");
10257 // A subtract of one will be selected as a INC. Note that INC doesn't
10258 // set CF, so we can't do this for UADDO.
10259 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10261 BaseOp = X86ISD::INC;
10262 Cond = X86::COND_O;
10265 BaseOp = X86ISD::ADD;
10266 Cond = X86::COND_O;
10269 BaseOp = X86ISD::ADD;
10270 Cond = X86::COND_B;
10273 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10274 // set CF, so we can't do this for USUBO.
10275 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10277 BaseOp = X86ISD::DEC;
10278 Cond = X86::COND_O;
10281 BaseOp = X86ISD::SUB;
10282 Cond = X86::COND_O;
10285 BaseOp = X86ISD::SUB;
10286 Cond = X86::COND_B;
10289 BaseOp = X86ISD::SMUL;
10290 Cond = X86::COND_O;
10292 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10293 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10295 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10298 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10299 DAG.getConstant(X86::COND_O, MVT::i32),
10300 SDValue(Sum.getNode(), 2));
10302 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10306 // Also sets EFLAGS.
10307 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10308 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10311 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10312 DAG.getConstant(Cond, MVT::i32),
10313 SDValue(Sum.getNode(), 1));
10315 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10318 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10319 SelectionDAG &DAG) const {
10320 DebugLoc dl = Op.getDebugLoc();
10321 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10322 EVT VT = Op.getValueType();
10324 if (Subtarget->hasSSE2() && VT.isVector()) {
10325 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10326 ExtraVT.getScalarType().getSizeInBits();
10327 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10329 unsigned SHLIntrinsicsID = 0;
10330 unsigned SRAIntrinsicsID = 0;
10331 switch (VT.getSimpleVT().SimpleTy) {
10335 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
10336 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
10339 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
10340 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
10344 if (!Subtarget->hasAVX())
10346 if (!Subtarget->hasAVX2()) {
10347 // needs to be split
10348 int NumElems = VT.getVectorNumElements();
10349 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10350 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10352 // Extract the LHS vectors
10353 SDValue LHS = Op.getOperand(0);
10354 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10355 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10357 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10358 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10360 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10361 int ExtraNumElems = ExtraVT.getVectorNumElements();
10362 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10364 SDValue Extra = DAG.getValueType(ExtraVT);
10366 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10367 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10369 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10371 if (VT == MVT::v8i32) {
10372 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_d;
10373 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_d;
10375 SHLIntrinsicsID = Intrinsic::x86_avx2_pslli_w;
10376 SRAIntrinsicsID = Intrinsic::x86_avx2_psrai_w;
10380 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10381 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
10382 Op.getOperand(0), ShAmt);
10384 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10385 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
10393 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10394 DebugLoc dl = Op.getDebugLoc();
10396 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10397 // There isn't any reason to disable it if the target processor supports it.
10398 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10399 SDValue Chain = Op.getOperand(0);
10400 SDValue Zero = DAG.getConstant(0, MVT::i32);
10402 DAG.getRegister(X86::ESP, MVT::i32), // Base
10403 DAG.getTargetConstant(1, MVT::i8), // Scale
10404 DAG.getRegister(0, MVT::i32), // Index
10405 DAG.getTargetConstant(0, MVT::i32), // Disp
10406 DAG.getRegister(0, MVT::i32), // Segment.
10411 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10412 array_lengthof(Ops));
10413 return SDValue(Res, 0);
10416 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10418 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10420 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10421 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10422 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10423 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10425 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10426 if (!Op1 && !Op2 && !Op3 && Op4)
10427 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10429 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10430 if (Op1 && !Op2 && !Op3 && !Op4)
10431 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10433 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10435 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10438 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10439 SelectionDAG &DAG) const {
10440 DebugLoc dl = Op.getDebugLoc();
10441 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10442 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10443 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10444 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10446 // The only fence that needs an instruction is a sequentially-consistent
10447 // cross-thread fence.
10448 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10449 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10450 // no-sse2). There isn't any reason to disable it if the target processor
10452 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10453 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10455 SDValue Chain = Op.getOperand(0);
10456 SDValue Zero = DAG.getConstant(0, MVT::i32);
10458 DAG.getRegister(X86::ESP, MVT::i32), // Base
10459 DAG.getTargetConstant(1, MVT::i8), // Scale
10460 DAG.getRegister(0, MVT::i32), // Index
10461 DAG.getTargetConstant(0, MVT::i32), // Disp
10462 DAG.getRegister(0, MVT::i32), // Segment.
10467 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10468 array_lengthof(Ops));
10469 return SDValue(Res, 0);
10472 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10473 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10477 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10478 EVT T = Op.getValueType();
10479 DebugLoc DL = Op.getDebugLoc();
10482 switch(T.getSimpleVT().SimpleTy) {
10484 assert(false && "Invalid value type!");
10485 case MVT::i8: Reg = X86::AL; size = 1; break;
10486 case MVT::i16: Reg = X86::AX; size = 2; break;
10487 case MVT::i32: Reg = X86::EAX; size = 4; break;
10489 assert(Subtarget->is64Bit() && "Node not type legal!");
10490 Reg = X86::RAX; size = 8;
10493 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10494 Op.getOperand(2), SDValue());
10495 SDValue Ops[] = { cpIn.getValue(0),
10498 DAG.getTargetConstant(size, MVT::i8),
10499 cpIn.getValue(1) };
10500 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10501 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10502 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10505 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10509 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10510 SelectionDAG &DAG) const {
10511 assert(Subtarget->is64Bit() && "Result not type legalized?");
10512 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10513 SDValue TheChain = Op.getOperand(0);
10514 DebugLoc dl = Op.getDebugLoc();
10515 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10516 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10517 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10519 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10520 DAG.getConstant(32, MVT::i8));
10522 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10525 return DAG.getMergeValues(Ops, 2, dl);
10528 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10529 SelectionDAG &DAG) const {
10530 EVT SrcVT = Op.getOperand(0).getValueType();
10531 EVT DstVT = Op.getValueType();
10532 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10533 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10534 assert((DstVT == MVT::i64 ||
10535 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10536 "Unexpected custom BITCAST");
10537 // i64 <=> MMX conversions are Legal.
10538 if (SrcVT==MVT::i64 && DstVT.isVector())
10540 if (DstVT==MVT::i64 && SrcVT.isVector())
10542 // MMX <=> MMX conversions are Legal.
10543 if (SrcVT.isVector() && DstVT.isVector())
10545 // All other conversions need to be expanded.
10549 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10550 SDNode *Node = Op.getNode();
10551 DebugLoc dl = Node->getDebugLoc();
10552 EVT T = Node->getValueType(0);
10553 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10554 DAG.getConstant(0, T), Node->getOperand(2));
10555 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10556 cast<AtomicSDNode>(Node)->getMemoryVT(),
10557 Node->getOperand(0),
10558 Node->getOperand(1), negOp,
10559 cast<AtomicSDNode>(Node)->getSrcValue(),
10560 cast<AtomicSDNode>(Node)->getAlignment(),
10561 cast<AtomicSDNode>(Node)->getOrdering(),
10562 cast<AtomicSDNode>(Node)->getSynchScope());
10565 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10566 SDNode *Node = Op.getNode();
10567 DebugLoc dl = Node->getDebugLoc();
10568 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10570 // Convert seq_cst store -> xchg
10571 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10572 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10573 // (The only way to get a 16-byte store is cmpxchg16b)
10574 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10575 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10576 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10577 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10578 cast<AtomicSDNode>(Node)->getMemoryVT(),
10579 Node->getOperand(0),
10580 Node->getOperand(1), Node->getOperand(2),
10581 cast<AtomicSDNode>(Node)->getMemOperand(),
10582 cast<AtomicSDNode>(Node)->getOrdering(),
10583 cast<AtomicSDNode>(Node)->getSynchScope());
10584 return Swap.getValue(1);
10586 // Other atomic stores have a simple pattern.
10590 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10591 EVT VT = Op.getNode()->getValueType(0);
10593 // Let legalize expand this if it isn't a legal type yet.
10594 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10597 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10600 bool ExtraOp = false;
10601 switch (Op.getOpcode()) {
10602 default: assert(0 && "Invalid code");
10603 case ISD::ADDC: Opc = X86ISD::ADD; break;
10604 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10605 case ISD::SUBC: Opc = X86ISD::SUB; break;
10606 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10610 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10612 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10613 Op.getOperand(1), Op.getOperand(2));
10616 /// LowerOperation - Provide custom lowering hooks for some operations.
10618 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10619 switch (Op.getOpcode()) {
10620 default: llvm_unreachable("Should not custom lower this!");
10621 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10622 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10623 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10624 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10625 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10626 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10627 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10628 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10629 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10630 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10631 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10632 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10633 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10634 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10635 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10636 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10637 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10638 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10639 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10640 case ISD::SHL_PARTS:
10641 case ISD::SRA_PARTS:
10642 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10643 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10644 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10645 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10646 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10647 case ISD::FABS: return LowerFABS(Op, DAG);
10648 case ISD::FNEG: return LowerFNEG(Op, DAG);
10649 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10650 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10651 case ISD::SETCC: return LowerSETCC(Op, DAG);
10652 case ISD::SELECT: return LowerSELECT(Op, DAG);
10653 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10654 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10655 case ISD::VASTART: return LowerVASTART(Op, DAG);
10656 case ISD::VAARG: return LowerVAARG(Op, DAG);
10657 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10658 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10659 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10660 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10661 case ISD::FRAME_TO_ARGS_OFFSET:
10662 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10663 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10664 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10665 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10666 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10667 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10668 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10669 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10670 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10671 case ISD::MUL: return LowerMUL(Op, DAG);
10674 case ISD::SHL: return LowerShift(Op, DAG);
10680 case ISD::UMULO: return LowerXALUO(Op, DAG);
10681 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10682 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10686 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10687 case ISD::ADD: return LowerADD(Op, DAG);
10688 case ISD::SUB: return LowerSUB(Op, DAG);
10692 static void ReplaceATOMIC_LOAD(SDNode *Node,
10693 SmallVectorImpl<SDValue> &Results,
10694 SelectionDAG &DAG) {
10695 DebugLoc dl = Node->getDebugLoc();
10696 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10698 // Convert wide load -> cmpxchg8b/cmpxchg16b
10699 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10700 // (The only way to get a 16-byte load is cmpxchg16b)
10701 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10702 SDValue Zero = DAG.getConstant(0, VT);
10703 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10704 Node->getOperand(0),
10705 Node->getOperand(1), Zero, Zero,
10706 cast<AtomicSDNode>(Node)->getMemOperand(),
10707 cast<AtomicSDNode>(Node)->getOrdering(),
10708 cast<AtomicSDNode>(Node)->getSynchScope());
10709 Results.push_back(Swap.getValue(0));
10710 Results.push_back(Swap.getValue(1));
10713 void X86TargetLowering::
10714 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10715 SelectionDAG &DAG, unsigned NewOp) const {
10716 DebugLoc dl = Node->getDebugLoc();
10717 assert (Node->getValueType(0) == MVT::i64 &&
10718 "Only know how to expand i64 atomics");
10720 SDValue Chain = Node->getOperand(0);
10721 SDValue In1 = Node->getOperand(1);
10722 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10723 Node->getOperand(2), DAG.getIntPtrConstant(0));
10724 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10725 Node->getOperand(2), DAG.getIntPtrConstant(1));
10726 SDValue Ops[] = { Chain, In1, In2L, In2H };
10727 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10729 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10730 cast<MemSDNode>(Node)->getMemOperand());
10731 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10732 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10733 Results.push_back(Result.getValue(2));
10736 /// ReplaceNodeResults - Replace a node with an illegal result type
10737 /// with a new node built out of custom code.
10738 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10739 SmallVectorImpl<SDValue>&Results,
10740 SelectionDAG &DAG) const {
10741 DebugLoc dl = N->getDebugLoc();
10742 switch (N->getOpcode()) {
10744 assert(false && "Do not know how to custom type legalize this operation!");
10746 case ISD::SIGN_EXTEND_INREG:
10751 // We don't want to expand or promote these.
10753 case ISD::FP_TO_SINT: {
10754 std::pair<SDValue,SDValue> Vals =
10755 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10756 SDValue FIST = Vals.first, StackSlot = Vals.second;
10757 if (FIST.getNode() != 0) {
10758 EVT VT = N->getValueType(0);
10759 // Return a load from the stack slot.
10760 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10761 MachinePointerInfo(),
10762 false, false, false, 0));
10766 case ISD::READCYCLECOUNTER: {
10767 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10768 SDValue TheChain = N->getOperand(0);
10769 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10770 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10772 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10774 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10775 SDValue Ops[] = { eax, edx };
10776 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10777 Results.push_back(edx.getValue(1));
10780 case ISD::ATOMIC_CMP_SWAP: {
10781 EVT T = N->getValueType(0);
10782 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10783 bool Regs64bit = T == MVT::i128;
10784 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10785 SDValue cpInL, cpInH;
10786 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10787 DAG.getConstant(0, HalfT));
10788 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10789 DAG.getConstant(1, HalfT));
10790 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10791 Regs64bit ? X86::RAX : X86::EAX,
10793 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10794 Regs64bit ? X86::RDX : X86::EDX,
10795 cpInH, cpInL.getValue(1));
10796 SDValue swapInL, swapInH;
10797 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10798 DAG.getConstant(0, HalfT));
10799 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10800 DAG.getConstant(1, HalfT));
10801 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10802 Regs64bit ? X86::RBX : X86::EBX,
10803 swapInL, cpInH.getValue(1));
10804 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10805 Regs64bit ? X86::RCX : X86::ECX,
10806 swapInH, swapInL.getValue(1));
10807 SDValue Ops[] = { swapInH.getValue(0),
10809 swapInH.getValue(1) };
10810 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10811 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10812 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10813 X86ISD::LCMPXCHG8_DAG;
10814 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10816 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10817 Regs64bit ? X86::RAX : X86::EAX,
10818 HalfT, Result.getValue(1));
10819 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10820 Regs64bit ? X86::RDX : X86::EDX,
10821 HalfT, cpOutL.getValue(2));
10822 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10823 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10824 Results.push_back(cpOutH.getValue(1));
10827 case ISD::ATOMIC_LOAD_ADD:
10828 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10830 case ISD::ATOMIC_LOAD_AND:
10831 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10833 case ISD::ATOMIC_LOAD_NAND:
10834 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10836 case ISD::ATOMIC_LOAD_OR:
10837 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10839 case ISD::ATOMIC_LOAD_SUB:
10840 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10842 case ISD::ATOMIC_LOAD_XOR:
10843 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10845 case ISD::ATOMIC_SWAP:
10846 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10848 case ISD::ATOMIC_LOAD:
10849 ReplaceATOMIC_LOAD(N, Results, DAG);
10853 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10855 default: return NULL;
10856 case X86ISD::BSF: return "X86ISD::BSF";
10857 case X86ISD::BSR: return "X86ISD::BSR";
10858 case X86ISD::SHLD: return "X86ISD::SHLD";
10859 case X86ISD::SHRD: return "X86ISD::SHRD";
10860 case X86ISD::FAND: return "X86ISD::FAND";
10861 case X86ISD::FOR: return "X86ISD::FOR";
10862 case X86ISD::FXOR: return "X86ISD::FXOR";
10863 case X86ISD::FSRL: return "X86ISD::FSRL";
10864 case X86ISD::FILD: return "X86ISD::FILD";
10865 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10866 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10867 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10868 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10869 case X86ISD::FLD: return "X86ISD::FLD";
10870 case X86ISD::FST: return "X86ISD::FST";
10871 case X86ISD::CALL: return "X86ISD::CALL";
10872 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10873 case X86ISD::BT: return "X86ISD::BT";
10874 case X86ISD::CMP: return "X86ISD::CMP";
10875 case X86ISD::COMI: return "X86ISD::COMI";
10876 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10877 case X86ISD::SETCC: return "X86ISD::SETCC";
10878 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10879 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10880 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10881 case X86ISD::CMOV: return "X86ISD::CMOV";
10882 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10883 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10884 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10885 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10886 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10887 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10888 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10889 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10890 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10891 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10892 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10893 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10894 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10895 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10896 case X86ISD::PSIGN: return "X86ISD::PSIGN";
10897 case X86ISD::BLENDV: return "X86ISD::BLENDV";
10898 case X86ISD::HADD: return "X86ISD::HADD";
10899 case X86ISD::HSUB: return "X86ISD::HSUB";
10900 case X86ISD::FHADD: return "X86ISD::FHADD";
10901 case X86ISD::FHSUB: return "X86ISD::FHSUB";
10902 case X86ISD::FMAX: return "X86ISD::FMAX";
10903 case X86ISD::FMIN: return "X86ISD::FMIN";
10904 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10905 case X86ISD::FRCP: return "X86ISD::FRCP";
10906 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10907 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10908 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10909 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10910 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10911 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10912 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10913 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10914 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10915 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10916 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10917 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10918 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10919 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10920 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10921 case X86ISD::VSHL: return "X86ISD::VSHL";
10922 case X86ISD::VSRL: return "X86ISD::VSRL";
10923 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10924 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10925 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10926 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10927 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10928 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10929 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10930 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10931 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10932 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10933 case X86ISD::ADD: return "X86ISD::ADD";
10934 case X86ISD::SUB: return "X86ISD::SUB";
10935 case X86ISD::ADC: return "X86ISD::ADC";
10936 case X86ISD::SBB: return "X86ISD::SBB";
10937 case X86ISD::SMUL: return "X86ISD::SMUL";
10938 case X86ISD::UMUL: return "X86ISD::UMUL";
10939 case X86ISD::INC: return "X86ISD::INC";
10940 case X86ISD::DEC: return "X86ISD::DEC";
10941 case X86ISD::OR: return "X86ISD::OR";
10942 case X86ISD::XOR: return "X86ISD::XOR";
10943 case X86ISD::AND: return "X86ISD::AND";
10944 case X86ISD::ANDN: return "X86ISD::ANDN";
10945 case X86ISD::BLSI: return "X86ISD::BLSI";
10946 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
10947 case X86ISD::BLSR: return "X86ISD::BLSR";
10948 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10949 case X86ISD::PTEST: return "X86ISD::PTEST";
10950 case X86ISD::TESTP: return "X86ISD::TESTP";
10951 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10952 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10953 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10954 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10955 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10956 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10957 case X86ISD::SHUFP: return "X86ISD::SHUFP";
10958 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10959 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10960 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10961 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10962 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10963 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10964 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10965 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10966 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10967 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10968 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10969 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10970 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
10971 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
10972 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10973 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
10974 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
10975 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10976 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10977 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10978 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10979 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
10983 // isLegalAddressingMode - Return true if the addressing mode represented
10984 // by AM is legal for this target, for a load/store of the specified type.
10985 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10987 // X86 supports extremely general addressing modes.
10988 CodeModel::Model M = getTargetMachine().getCodeModel();
10989 Reloc::Model R = getTargetMachine().getRelocationModel();
10991 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10992 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10997 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
10999 // If a reference to this global requires an extra load, we can't fold it.
11000 if (isGlobalStubReference(GVFlags))
11003 // If BaseGV requires a register for the PIC base, we cannot also have a
11004 // BaseReg specified.
11005 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11008 // If lower 4G is not available, then we must use rip-relative addressing.
11009 if ((M != CodeModel::Small || R != Reloc::Static) &&
11010 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11014 switch (AM.Scale) {
11020 // These scales always work.
11025 // These scales are formed with basereg+scalereg. Only accept if there is
11030 default: // Other stuff never works.
11038 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11039 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11041 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11042 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11043 if (NumBits1 <= NumBits2)
11048 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11049 if (!VT1.isInteger() || !VT2.isInteger())
11051 unsigned NumBits1 = VT1.getSizeInBits();
11052 unsigned NumBits2 = VT2.getSizeInBits();
11053 if (NumBits1 <= NumBits2)
11058 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11059 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11060 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11063 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11064 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11065 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11068 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11069 // i16 instructions are longer (0x66 prefix) and potentially slower.
11070 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11073 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11074 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11075 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11076 /// are assumed to be legal.
11078 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11080 // Very little shuffling can be done for 64-bit vectors right now.
11081 if (VT.getSizeInBits() == 64)
11084 // FIXME: pshufb, blends, shifts.
11085 return (VT.getVectorNumElements() == 2 ||
11086 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11087 isMOVLMask(M, VT) ||
11088 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11089 isPSHUFDMask(M, VT) ||
11090 isPSHUFHWMask(M, VT) ||
11091 isPSHUFLWMask(M, VT) ||
11092 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
11093 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11094 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11095 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11096 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11100 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11102 unsigned NumElts = VT.getVectorNumElements();
11103 // FIXME: This collection of masks seems suspect.
11106 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11107 return (isMOVLMask(Mask, VT) ||
11108 isCommutedMOVLMask(Mask, VT, true) ||
11109 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11110 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11115 //===----------------------------------------------------------------------===//
11116 // X86 Scheduler Hooks
11117 //===----------------------------------------------------------------------===//
11119 // private utility function
11120 MachineBasicBlock *
11121 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11122 MachineBasicBlock *MBB,
11129 TargetRegisterClass *RC,
11130 bool invSrc) const {
11131 // For the atomic bitwise operator, we generate
11134 // ld t1 = [bitinstr.addr]
11135 // op t2 = t1, [bitinstr.val]
11137 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11139 // fallthrough -->nextMBB
11140 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11141 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11142 MachineFunction::iterator MBBIter = MBB;
11145 /// First build the CFG
11146 MachineFunction *F = MBB->getParent();
11147 MachineBasicBlock *thisMBB = MBB;
11148 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11149 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11150 F->insert(MBBIter, newMBB);
11151 F->insert(MBBIter, nextMBB);
11153 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11154 nextMBB->splice(nextMBB->begin(), thisMBB,
11155 llvm::next(MachineBasicBlock::iterator(bInstr)),
11157 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11159 // Update thisMBB to fall through to newMBB
11160 thisMBB->addSuccessor(newMBB);
11162 // newMBB jumps to itself and fall through to nextMBB
11163 newMBB->addSuccessor(nextMBB);
11164 newMBB->addSuccessor(newMBB);
11166 // Insert instructions into newMBB based on incoming instruction
11167 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11168 "unexpected number of operands");
11169 DebugLoc dl = bInstr->getDebugLoc();
11170 MachineOperand& destOper = bInstr->getOperand(0);
11171 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11172 int numArgs = bInstr->getNumOperands() - 1;
11173 for (int i=0; i < numArgs; ++i)
11174 argOpers[i] = &bInstr->getOperand(i+1);
11176 // x86 address has 4 operands: base, index, scale, and displacement
11177 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11178 int valArgIndx = lastAddrIndx + 1;
11180 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11181 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11182 for (int i=0; i <= lastAddrIndx; ++i)
11183 (*MIB).addOperand(*argOpers[i]);
11185 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11187 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11192 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11193 assert((argOpers[valArgIndx]->isReg() ||
11194 argOpers[valArgIndx]->isImm()) &&
11195 "invalid operand");
11196 if (argOpers[valArgIndx]->isReg())
11197 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11199 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11201 (*MIB).addOperand(*argOpers[valArgIndx]);
11203 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11206 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11207 for (int i=0; i <= lastAddrIndx; ++i)
11208 (*MIB).addOperand(*argOpers[i]);
11210 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11211 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11212 bInstr->memoperands_end());
11214 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11215 MIB.addReg(EAXreg);
11218 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11220 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11224 // private utility function: 64 bit atomics on 32 bit host.
11225 MachineBasicBlock *
11226 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11227 MachineBasicBlock *MBB,
11232 bool invSrc) const {
11233 // For the atomic bitwise operator, we generate
11234 // thisMBB (instructions are in pairs, except cmpxchg8b)
11235 // ld t1,t2 = [bitinstr.addr]
11237 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11238 // op t5, t6 <- out1, out2, [bitinstr.val]
11239 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11240 // mov ECX, EBX <- t5, t6
11241 // mov EAX, EDX <- t1, t2
11242 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11243 // mov t3, t4 <- EAX, EDX
11245 // result in out1, out2
11246 // fallthrough -->nextMBB
11248 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11249 const unsigned LoadOpc = X86::MOV32rm;
11250 const unsigned NotOpc = X86::NOT32r;
11251 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11252 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11253 MachineFunction::iterator MBBIter = MBB;
11256 /// First build the CFG
11257 MachineFunction *F = MBB->getParent();
11258 MachineBasicBlock *thisMBB = MBB;
11259 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11260 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11261 F->insert(MBBIter, newMBB);
11262 F->insert(MBBIter, nextMBB);
11264 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11265 nextMBB->splice(nextMBB->begin(), thisMBB,
11266 llvm::next(MachineBasicBlock::iterator(bInstr)),
11268 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11270 // Update thisMBB to fall through to newMBB
11271 thisMBB->addSuccessor(newMBB);
11273 // newMBB jumps to itself and fall through to nextMBB
11274 newMBB->addSuccessor(nextMBB);
11275 newMBB->addSuccessor(newMBB);
11277 DebugLoc dl = bInstr->getDebugLoc();
11278 // Insert instructions into newMBB based on incoming instruction
11279 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11280 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11281 "unexpected number of operands");
11282 MachineOperand& dest1Oper = bInstr->getOperand(0);
11283 MachineOperand& dest2Oper = bInstr->getOperand(1);
11284 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11285 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11286 argOpers[i] = &bInstr->getOperand(i+2);
11288 // We use some of the operands multiple times, so conservatively just
11289 // clear any kill flags that might be present.
11290 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11291 argOpers[i]->setIsKill(false);
11294 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11295 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11297 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11298 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11299 for (int i=0; i <= lastAddrIndx; ++i)
11300 (*MIB).addOperand(*argOpers[i]);
11301 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11302 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11303 // add 4 to displacement.
11304 for (int i=0; i <= lastAddrIndx-2; ++i)
11305 (*MIB).addOperand(*argOpers[i]);
11306 MachineOperand newOp3 = *(argOpers[3]);
11307 if (newOp3.isImm())
11308 newOp3.setImm(newOp3.getImm()+4);
11310 newOp3.setOffset(newOp3.getOffset()+4);
11311 (*MIB).addOperand(newOp3);
11312 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11314 // t3/4 are defined later, at the bottom of the loop
11315 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11316 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11317 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11318 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11319 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11320 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11322 // The subsequent operations should be using the destination registers of
11323 //the PHI instructions.
11325 t1 = F->getRegInfo().createVirtualRegister(RC);
11326 t2 = F->getRegInfo().createVirtualRegister(RC);
11327 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11328 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11330 t1 = dest1Oper.getReg();
11331 t2 = dest2Oper.getReg();
11334 int valArgIndx = lastAddrIndx + 1;
11335 assert((argOpers[valArgIndx]->isReg() ||
11336 argOpers[valArgIndx]->isImm()) &&
11337 "invalid operand");
11338 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11339 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11340 if (argOpers[valArgIndx]->isReg())
11341 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11343 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11344 if (regOpcL != X86::MOV32rr)
11346 (*MIB).addOperand(*argOpers[valArgIndx]);
11347 assert(argOpers[valArgIndx + 1]->isReg() ==
11348 argOpers[valArgIndx]->isReg());
11349 assert(argOpers[valArgIndx + 1]->isImm() ==
11350 argOpers[valArgIndx]->isImm());
11351 if (argOpers[valArgIndx + 1]->isReg())
11352 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11354 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11355 if (regOpcH != X86::MOV32rr)
11357 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11359 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11361 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11364 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11366 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11369 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11370 for (int i=0; i <= lastAddrIndx; ++i)
11371 (*MIB).addOperand(*argOpers[i]);
11373 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11374 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11375 bInstr->memoperands_end());
11377 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11378 MIB.addReg(X86::EAX);
11379 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11380 MIB.addReg(X86::EDX);
11383 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11385 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11389 // private utility function
11390 MachineBasicBlock *
11391 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11392 MachineBasicBlock *MBB,
11393 unsigned cmovOpc) const {
11394 // For the atomic min/max operator, we generate
11397 // ld t1 = [min/max.addr]
11398 // mov t2 = [min/max.val]
11400 // cmov[cond] t2 = t1
11402 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11404 // fallthrough -->nextMBB
11406 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11407 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11408 MachineFunction::iterator MBBIter = MBB;
11411 /// First build the CFG
11412 MachineFunction *F = MBB->getParent();
11413 MachineBasicBlock *thisMBB = MBB;
11414 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11415 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11416 F->insert(MBBIter, newMBB);
11417 F->insert(MBBIter, nextMBB);
11419 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11420 nextMBB->splice(nextMBB->begin(), thisMBB,
11421 llvm::next(MachineBasicBlock::iterator(mInstr)),
11423 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11425 // Update thisMBB to fall through to newMBB
11426 thisMBB->addSuccessor(newMBB);
11428 // newMBB jumps to newMBB and fall through to nextMBB
11429 newMBB->addSuccessor(nextMBB);
11430 newMBB->addSuccessor(newMBB);
11432 DebugLoc dl = mInstr->getDebugLoc();
11433 // Insert instructions into newMBB based on incoming instruction
11434 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11435 "unexpected number of operands");
11436 MachineOperand& destOper = mInstr->getOperand(0);
11437 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11438 int numArgs = mInstr->getNumOperands() - 1;
11439 for (int i=0; i < numArgs; ++i)
11440 argOpers[i] = &mInstr->getOperand(i+1);
11442 // x86 address has 4 operands: base, index, scale, and displacement
11443 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11444 int valArgIndx = lastAddrIndx + 1;
11446 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11447 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11448 for (int i=0; i <= lastAddrIndx; ++i)
11449 (*MIB).addOperand(*argOpers[i]);
11451 // We only support register and immediate values
11452 assert((argOpers[valArgIndx]->isReg() ||
11453 argOpers[valArgIndx]->isImm()) &&
11454 "invalid operand");
11456 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11457 if (argOpers[valArgIndx]->isReg())
11458 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11460 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11461 (*MIB).addOperand(*argOpers[valArgIndx]);
11463 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11466 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11471 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11472 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11476 // Cmp and exchange if none has modified the memory location
11477 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11478 for (int i=0; i <= lastAddrIndx; ++i)
11479 (*MIB).addOperand(*argOpers[i]);
11481 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11482 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11483 mInstr->memoperands_end());
11485 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11486 MIB.addReg(X86::EAX);
11489 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11491 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11495 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11496 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11497 // in the .td file.
11498 MachineBasicBlock *
11499 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11500 unsigned numArgs, bool memArg) const {
11501 assert(Subtarget->hasSSE42() &&
11502 "Target must have SSE4.2 or AVX features enabled");
11504 DebugLoc dl = MI->getDebugLoc();
11505 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11507 if (!Subtarget->hasAVX()) {
11509 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11511 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11514 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11516 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11519 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11520 for (unsigned i = 0; i < numArgs; ++i) {
11521 MachineOperand &Op = MI->getOperand(i+1);
11522 if (!(Op.isReg() && Op.isImplicit()))
11523 MIB.addOperand(Op);
11525 BuildMI(*BB, MI, dl,
11526 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11527 MI->getOperand(0).getReg())
11528 .addReg(X86::XMM0);
11530 MI->eraseFromParent();
11534 MachineBasicBlock *
11535 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11536 DebugLoc dl = MI->getDebugLoc();
11537 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11539 // Address into RAX/EAX, other two args into ECX, EDX.
11540 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11541 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11542 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11543 for (int i = 0; i < X86::AddrNumOperands; ++i)
11544 MIB.addOperand(MI->getOperand(i));
11546 unsigned ValOps = X86::AddrNumOperands;
11547 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11548 .addReg(MI->getOperand(ValOps).getReg());
11549 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11550 .addReg(MI->getOperand(ValOps+1).getReg());
11552 // The instruction doesn't actually take any operands though.
11553 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11555 MI->eraseFromParent(); // The pseudo is gone now.
11559 MachineBasicBlock *
11560 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11561 DebugLoc dl = MI->getDebugLoc();
11562 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11564 // First arg in ECX, the second in EAX.
11565 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11566 .addReg(MI->getOperand(0).getReg());
11567 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11568 .addReg(MI->getOperand(1).getReg());
11570 // The instruction doesn't actually take any operands though.
11571 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11573 MI->eraseFromParent(); // The pseudo is gone now.
11577 MachineBasicBlock *
11578 X86TargetLowering::EmitVAARG64WithCustomInserter(
11580 MachineBasicBlock *MBB) const {
11581 // Emit va_arg instruction on X86-64.
11583 // Operands to this pseudo-instruction:
11584 // 0 ) Output : destination address (reg)
11585 // 1-5) Input : va_list address (addr, i64mem)
11586 // 6 ) ArgSize : Size (in bytes) of vararg type
11587 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11588 // 8 ) Align : Alignment of type
11589 // 9 ) EFLAGS (implicit-def)
11591 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11592 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11594 unsigned DestReg = MI->getOperand(0).getReg();
11595 MachineOperand &Base = MI->getOperand(1);
11596 MachineOperand &Scale = MI->getOperand(2);
11597 MachineOperand &Index = MI->getOperand(3);
11598 MachineOperand &Disp = MI->getOperand(4);
11599 MachineOperand &Segment = MI->getOperand(5);
11600 unsigned ArgSize = MI->getOperand(6).getImm();
11601 unsigned ArgMode = MI->getOperand(7).getImm();
11602 unsigned Align = MI->getOperand(8).getImm();
11604 // Memory Reference
11605 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11606 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11607 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11609 // Machine Information
11610 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11611 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11612 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11613 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11614 DebugLoc DL = MI->getDebugLoc();
11616 // struct va_list {
11619 // i64 overflow_area (address)
11620 // i64 reg_save_area (address)
11622 // sizeof(va_list) = 24
11623 // alignment(va_list) = 8
11625 unsigned TotalNumIntRegs = 6;
11626 unsigned TotalNumXMMRegs = 8;
11627 bool UseGPOffset = (ArgMode == 1);
11628 bool UseFPOffset = (ArgMode == 2);
11629 unsigned MaxOffset = TotalNumIntRegs * 8 +
11630 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11632 /* Align ArgSize to a multiple of 8 */
11633 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11634 bool NeedsAlign = (Align > 8);
11636 MachineBasicBlock *thisMBB = MBB;
11637 MachineBasicBlock *overflowMBB;
11638 MachineBasicBlock *offsetMBB;
11639 MachineBasicBlock *endMBB;
11641 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11642 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11643 unsigned OffsetReg = 0;
11645 if (!UseGPOffset && !UseFPOffset) {
11646 // If we only pull from the overflow region, we don't create a branch.
11647 // We don't need to alter control flow.
11648 OffsetDestReg = 0; // unused
11649 OverflowDestReg = DestReg;
11652 overflowMBB = thisMBB;
11655 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11656 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11657 // If not, pull from overflow_area. (branch to overflowMBB)
11662 // offsetMBB overflowMBB
11667 // Registers for the PHI in endMBB
11668 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11669 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11671 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11672 MachineFunction *MF = MBB->getParent();
11673 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11674 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11675 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11677 MachineFunction::iterator MBBIter = MBB;
11680 // Insert the new basic blocks
11681 MF->insert(MBBIter, offsetMBB);
11682 MF->insert(MBBIter, overflowMBB);
11683 MF->insert(MBBIter, endMBB);
11685 // Transfer the remainder of MBB and its successor edges to endMBB.
11686 endMBB->splice(endMBB->begin(), thisMBB,
11687 llvm::next(MachineBasicBlock::iterator(MI)),
11689 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11691 // Make offsetMBB and overflowMBB successors of thisMBB
11692 thisMBB->addSuccessor(offsetMBB);
11693 thisMBB->addSuccessor(overflowMBB);
11695 // endMBB is a successor of both offsetMBB and overflowMBB
11696 offsetMBB->addSuccessor(endMBB);
11697 overflowMBB->addSuccessor(endMBB);
11699 // Load the offset value into a register
11700 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11701 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11705 .addDisp(Disp, UseFPOffset ? 4 : 0)
11706 .addOperand(Segment)
11707 .setMemRefs(MMOBegin, MMOEnd);
11709 // Check if there is enough room left to pull this argument.
11710 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11712 .addImm(MaxOffset + 8 - ArgSizeA8);
11714 // Branch to "overflowMBB" if offset >= max
11715 // Fall through to "offsetMBB" otherwise
11716 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11717 .addMBB(overflowMBB);
11720 // In offsetMBB, emit code to use the reg_save_area.
11722 assert(OffsetReg != 0);
11724 // Read the reg_save_area address.
11725 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11726 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11731 .addOperand(Segment)
11732 .setMemRefs(MMOBegin, MMOEnd);
11734 // Zero-extend the offset
11735 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11736 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11739 .addImm(X86::sub_32bit);
11741 // Add the offset to the reg_save_area to get the final address.
11742 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11743 .addReg(OffsetReg64)
11744 .addReg(RegSaveReg);
11746 // Compute the offset for the next argument
11747 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11748 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11750 .addImm(UseFPOffset ? 16 : 8);
11752 // Store it back into the va_list.
11753 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11757 .addDisp(Disp, UseFPOffset ? 4 : 0)
11758 .addOperand(Segment)
11759 .addReg(NextOffsetReg)
11760 .setMemRefs(MMOBegin, MMOEnd);
11763 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11768 // Emit code to use overflow area
11771 // Load the overflow_area address into a register.
11772 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11773 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11778 .addOperand(Segment)
11779 .setMemRefs(MMOBegin, MMOEnd);
11781 // If we need to align it, do so. Otherwise, just copy the address
11782 // to OverflowDestReg.
11784 // Align the overflow address
11785 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11786 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11788 // aligned_addr = (addr + (align-1)) & ~(align-1)
11789 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11790 .addReg(OverflowAddrReg)
11793 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11795 .addImm(~(uint64_t)(Align-1));
11797 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11798 .addReg(OverflowAddrReg);
11801 // Compute the next overflow address after this argument.
11802 // (the overflow address should be kept 8-byte aligned)
11803 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11804 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11805 .addReg(OverflowDestReg)
11806 .addImm(ArgSizeA8);
11808 // Store the new overflow address.
11809 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11814 .addOperand(Segment)
11815 .addReg(NextAddrReg)
11816 .setMemRefs(MMOBegin, MMOEnd);
11818 // If we branched, emit the PHI to the front of endMBB.
11820 BuildMI(*endMBB, endMBB->begin(), DL,
11821 TII->get(X86::PHI), DestReg)
11822 .addReg(OffsetDestReg).addMBB(offsetMBB)
11823 .addReg(OverflowDestReg).addMBB(overflowMBB);
11826 // Erase the pseudo instruction
11827 MI->eraseFromParent();
11832 MachineBasicBlock *
11833 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11835 MachineBasicBlock *MBB) const {
11836 // Emit code to save XMM registers to the stack. The ABI says that the
11837 // number of registers to save is given in %al, so it's theoretically
11838 // possible to do an indirect jump trick to avoid saving all of them,
11839 // however this code takes a simpler approach and just executes all
11840 // of the stores if %al is non-zero. It's less code, and it's probably
11841 // easier on the hardware branch predictor, and stores aren't all that
11842 // expensive anyway.
11844 // Create the new basic blocks. One block contains all the XMM stores,
11845 // and one block is the final destination regardless of whether any
11846 // stores were performed.
11847 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11848 MachineFunction *F = MBB->getParent();
11849 MachineFunction::iterator MBBIter = MBB;
11851 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11852 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11853 F->insert(MBBIter, XMMSaveMBB);
11854 F->insert(MBBIter, EndMBB);
11856 // Transfer the remainder of MBB and its successor edges to EndMBB.
11857 EndMBB->splice(EndMBB->begin(), MBB,
11858 llvm::next(MachineBasicBlock::iterator(MI)),
11860 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11862 // The original block will now fall through to the XMM save block.
11863 MBB->addSuccessor(XMMSaveMBB);
11864 // The XMMSaveMBB will fall through to the end block.
11865 XMMSaveMBB->addSuccessor(EndMBB);
11867 // Now add the instructions.
11868 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11869 DebugLoc DL = MI->getDebugLoc();
11871 unsigned CountReg = MI->getOperand(0).getReg();
11872 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11873 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11875 if (!Subtarget->isTargetWin64()) {
11876 // If %al is 0, branch around the XMM save block.
11877 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11878 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11879 MBB->addSuccessor(EndMBB);
11882 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11883 // In the XMM save block, save all the XMM argument registers.
11884 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11885 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11886 MachineMemOperand *MMO =
11887 F->getMachineMemOperand(
11888 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11889 MachineMemOperand::MOStore,
11890 /*Size=*/16, /*Align=*/16);
11891 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11892 .addFrameIndex(RegSaveFrameIndex)
11893 .addImm(/*Scale=*/1)
11894 .addReg(/*IndexReg=*/0)
11895 .addImm(/*Disp=*/Offset)
11896 .addReg(/*Segment=*/0)
11897 .addReg(MI->getOperand(i).getReg())
11898 .addMemOperand(MMO);
11901 MI->eraseFromParent(); // The pseudo instruction is gone now.
11906 MachineBasicBlock *
11907 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11908 MachineBasicBlock *BB) const {
11909 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11910 DebugLoc DL = MI->getDebugLoc();
11912 // To "insert" a SELECT_CC instruction, we actually have to insert the
11913 // diamond control-flow pattern. The incoming instruction knows the
11914 // destination vreg to set, the condition code register to branch on, the
11915 // true/false values to select between, and a branch opcode to use.
11916 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11917 MachineFunction::iterator It = BB;
11923 // cmpTY ccX, r1, r2
11925 // fallthrough --> copy0MBB
11926 MachineBasicBlock *thisMBB = BB;
11927 MachineFunction *F = BB->getParent();
11928 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11929 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11930 F->insert(It, copy0MBB);
11931 F->insert(It, sinkMBB);
11933 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11934 // live into the sink and copy blocks.
11935 if (!MI->killsRegister(X86::EFLAGS)) {
11936 copy0MBB->addLiveIn(X86::EFLAGS);
11937 sinkMBB->addLiveIn(X86::EFLAGS);
11940 // Transfer the remainder of BB and its successor edges to sinkMBB.
11941 sinkMBB->splice(sinkMBB->begin(), BB,
11942 llvm::next(MachineBasicBlock::iterator(MI)),
11944 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11946 // Add the true and fallthrough blocks as its successors.
11947 BB->addSuccessor(copy0MBB);
11948 BB->addSuccessor(sinkMBB);
11950 // Create the conditional branch instruction.
11952 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11953 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11956 // %FalseValue = ...
11957 // # fallthrough to sinkMBB
11958 copy0MBB->addSuccessor(sinkMBB);
11961 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11963 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11964 TII->get(X86::PHI), MI->getOperand(0).getReg())
11965 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11966 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11968 MI->eraseFromParent(); // The pseudo instruction is gone now.
11972 MachineBasicBlock *
11973 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
11974 bool Is64Bit) const {
11975 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11976 DebugLoc DL = MI->getDebugLoc();
11977 MachineFunction *MF = BB->getParent();
11978 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11980 assert(getTargetMachine().Options.EnableSegmentedStacks);
11982 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
11983 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
11986 // ... [Till the alloca]
11987 // If stacklet is not large enough, jump to mallocMBB
11990 // Allocate by subtracting from RSP
11991 // Jump to continueMBB
11994 // Allocate by call to runtime
11998 // [rest of original BB]
12001 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12002 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12003 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12005 MachineRegisterInfo &MRI = MF->getRegInfo();
12006 const TargetRegisterClass *AddrRegClass =
12007 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12009 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12010 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12011 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12012 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12013 sizeVReg = MI->getOperand(1).getReg(),
12014 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12016 MachineFunction::iterator MBBIter = BB;
12019 MF->insert(MBBIter, bumpMBB);
12020 MF->insert(MBBIter, mallocMBB);
12021 MF->insert(MBBIter, continueMBB);
12023 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12024 (MachineBasicBlock::iterator(MI)), BB->end());
12025 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12027 // Add code to the main basic block to check if the stack limit has been hit,
12028 // and if so, jump to mallocMBB otherwise to bumpMBB.
12029 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12030 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12031 .addReg(tmpSPVReg).addReg(sizeVReg);
12032 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12033 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12034 .addReg(SPLimitVReg);
12035 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12037 // bumpMBB simply decreases the stack pointer, since we know the current
12038 // stacklet has enough space.
12039 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12040 .addReg(SPLimitVReg);
12041 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12042 .addReg(SPLimitVReg);
12043 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12045 // Calls into a routine in libgcc to allocate more space from the heap.
12047 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12049 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12050 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
12052 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12054 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12055 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12056 .addExternalSymbol("__morestack_allocate_stack_space");
12060 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12063 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12064 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12065 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12067 // Set up the CFG correctly.
12068 BB->addSuccessor(bumpMBB);
12069 BB->addSuccessor(mallocMBB);
12070 mallocMBB->addSuccessor(continueMBB);
12071 bumpMBB->addSuccessor(continueMBB);
12073 // Take care of the PHI nodes.
12074 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12075 MI->getOperand(0).getReg())
12076 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12077 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12079 // Delete the original pseudo instruction.
12080 MI->eraseFromParent();
12083 return continueMBB;
12086 MachineBasicBlock *
12087 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12088 MachineBasicBlock *BB) const {
12089 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12090 DebugLoc DL = MI->getDebugLoc();
12092 assert(!Subtarget->isTargetEnvMacho());
12094 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12095 // non-trivial part is impdef of ESP.
12097 if (Subtarget->isTargetWin64()) {
12098 if (Subtarget->isTargetCygMing()) {
12099 // ___chkstk(Mingw64):
12100 // Clobbers R10, R11, RAX and EFLAGS.
12102 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12103 .addExternalSymbol("___chkstk")
12104 .addReg(X86::RAX, RegState::Implicit)
12105 .addReg(X86::RSP, RegState::Implicit)
12106 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12107 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12108 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12110 // __chkstk(MSVCRT): does not update stack pointer.
12111 // Clobbers R10, R11 and EFLAGS.
12112 // FIXME: RAX(allocated size) might be reused and not killed.
12113 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12114 .addExternalSymbol("__chkstk")
12115 .addReg(X86::RAX, RegState::Implicit)
12116 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12117 // RAX has the offset to subtracted from RSP.
12118 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12123 const char *StackProbeSymbol =
12124 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12126 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12127 .addExternalSymbol(StackProbeSymbol)
12128 .addReg(X86::EAX, RegState::Implicit)
12129 .addReg(X86::ESP, RegState::Implicit)
12130 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12131 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12132 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12135 MI->eraseFromParent(); // The pseudo instruction is gone now.
12139 MachineBasicBlock *
12140 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12141 MachineBasicBlock *BB) const {
12142 // This is pretty easy. We're taking the value that we received from
12143 // our load from the relocation, sticking it in either RDI (x86-64)
12144 // or EAX and doing an indirect call. The return value will then
12145 // be in the normal return register.
12146 const X86InstrInfo *TII
12147 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12148 DebugLoc DL = MI->getDebugLoc();
12149 MachineFunction *F = BB->getParent();
12151 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12152 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12154 if (Subtarget->is64Bit()) {
12155 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12156 TII->get(X86::MOV64rm), X86::RDI)
12158 .addImm(0).addReg(0)
12159 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12160 MI->getOperand(3).getTargetFlags())
12162 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12163 addDirectMem(MIB, X86::RDI);
12164 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12165 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12166 TII->get(X86::MOV32rm), X86::EAX)
12168 .addImm(0).addReg(0)
12169 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12170 MI->getOperand(3).getTargetFlags())
12172 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12173 addDirectMem(MIB, X86::EAX);
12175 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12176 TII->get(X86::MOV32rm), X86::EAX)
12177 .addReg(TII->getGlobalBaseReg(F))
12178 .addImm(0).addReg(0)
12179 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12180 MI->getOperand(3).getTargetFlags())
12182 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12183 addDirectMem(MIB, X86::EAX);
12186 MI->eraseFromParent(); // The pseudo instruction is gone now.
12190 MachineBasicBlock *
12191 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12192 MachineBasicBlock *BB) const {
12193 switch (MI->getOpcode()) {
12194 default: assert(0 && "Unexpected instr type to insert");
12195 case X86::TAILJMPd64:
12196 case X86::TAILJMPr64:
12197 case X86::TAILJMPm64:
12198 assert(0 && "TAILJMP64 would not be touched here.");
12199 case X86::TCRETURNdi64:
12200 case X86::TCRETURNri64:
12201 case X86::TCRETURNmi64:
12202 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
12203 // On AMD64, additional defs should be added before register allocation.
12204 if (!Subtarget->isTargetWin64()) {
12205 MI->addRegisterDefined(X86::RSI);
12206 MI->addRegisterDefined(X86::RDI);
12207 MI->addRegisterDefined(X86::XMM6);
12208 MI->addRegisterDefined(X86::XMM7);
12209 MI->addRegisterDefined(X86::XMM8);
12210 MI->addRegisterDefined(X86::XMM9);
12211 MI->addRegisterDefined(X86::XMM10);
12212 MI->addRegisterDefined(X86::XMM11);
12213 MI->addRegisterDefined(X86::XMM12);
12214 MI->addRegisterDefined(X86::XMM13);
12215 MI->addRegisterDefined(X86::XMM14);
12216 MI->addRegisterDefined(X86::XMM15);
12219 case X86::WIN_ALLOCA:
12220 return EmitLoweredWinAlloca(MI, BB);
12221 case X86::SEG_ALLOCA_32:
12222 return EmitLoweredSegAlloca(MI, BB, false);
12223 case X86::SEG_ALLOCA_64:
12224 return EmitLoweredSegAlloca(MI, BB, true);
12225 case X86::TLSCall_32:
12226 case X86::TLSCall_64:
12227 return EmitLoweredTLSCall(MI, BB);
12228 case X86::CMOV_GR8:
12229 case X86::CMOV_FR32:
12230 case X86::CMOV_FR64:
12231 case X86::CMOV_V4F32:
12232 case X86::CMOV_V2F64:
12233 case X86::CMOV_V2I64:
12234 case X86::CMOV_V8F32:
12235 case X86::CMOV_V4F64:
12236 case X86::CMOV_V4I64:
12237 case X86::CMOV_GR16:
12238 case X86::CMOV_GR32:
12239 case X86::CMOV_RFP32:
12240 case X86::CMOV_RFP64:
12241 case X86::CMOV_RFP80:
12242 return EmitLoweredSelect(MI, BB);
12244 case X86::FP32_TO_INT16_IN_MEM:
12245 case X86::FP32_TO_INT32_IN_MEM:
12246 case X86::FP32_TO_INT64_IN_MEM:
12247 case X86::FP64_TO_INT16_IN_MEM:
12248 case X86::FP64_TO_INT32_IN_MEM:
12249 case X86::FP64_TO_INT64_IN_MEM:
12250 case X86::FP80_TO_INT16_IN_MEM:
12251 case X86::FP80_TO_INT32_IN_MEM:
12252 case X86::FP80_TO_INT64_IN_MEM: {
12253 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12254 DebugLoc DL = MI->getDebugLoc();
12256 // Change the floating point control register to use "round towards zero"
12257 // mode when truncating to an integer value.
12258 MachineFunction *F = BB->getParent();
12259 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12260 addFrameReference(BuildMI(*BB, MI, DL,
12261 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12263 // Load the old value of the high byte of the control word...
12265 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12266 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12269 // Set the high part to be round to zero...
12270 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12273 // Reload the modified control word now...
12274 addFrameReference(BuildMI(*BB, MI, DL,
12275 TII->get(X86::FLDCW16m)), CWFrameIdx);
12277 // Restore the memory image of control word to original value
12278 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12281 // Get the X86 opcode to use.
12283 switch (MI->getOpcode()) {
12284 default: llvm_unreachable("illegal opcode!");
12285 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12286 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12287 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12288 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12289 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12290 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12291 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12292 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12293 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12297 MachineOperand &Op = MI->getOperand(0);
12299 AM.BaseType = X86AddressMode::RegBase;
12300 AM.Base.Reg = Op.getReg();
12302 AM.BaseType = X86AddressMode::FrameIndexBase;
12303 AM.Base.FrameIndex = Op.getIndex();
12305 Op = MI->getOperand(1);
12307 AM.Scale = Op.getImm();
12308 Op = MI->getOperand(2);
12310 AM.IndexReg = Op.getImm();
12311 Op = MI->getOperand(3);
12312 if (Op.isGlobal()) {
12313 AM.GV = Op.getGlobal();
12315 AM.Disp = Op.getImm();
12317 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12318 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12320 // Reload the original control word now.
12321 addFrameReference(BuildMI(*BB, MI, DL,
12322 TII->get(X86::FLDCW16m)), CWFrameIdx);
12324 MI->eraseFromParent(); // The pseudo instruction is gone now.
12327 // String/text processing lowering.
12328 case X86::PCMPISTRM128REG:
12329 case X86::VPCMPISTRM128REG:
12330 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12331 case X86::PCMPISTRM128MEM:
12332 case X86::VPCMPISTRM128MEM:
12333 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12334 case X86::PCMPESTRM128REG:
12335 case X86::VPCMPESTRM128REG:
12336 return EmitPCMP(MI, BB, 5, false /* in mem */);
12337 case X86::PCMPESTRM128MEM:
12338 case X86::VPCMPESTRM128MEM:
12339 return EmitPCMP(MI, BB, 5, true /* in mem */);
12341 // Thread synchronization.
12343 return EmitMonitor(MI, BB);
12345 return EmitMwait(MI, BB);
12347 // Atomic Lowering.
12348 case X86::ATOMAND32:
12349 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12350 X86::AND32ri, X86::MOV32rm,
12352 X86::NOT32r, X86::EAX,
12353 X86::GR32RegisterClass);
12354 case X86::ATOMOR32:
12355 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12356 X86::OR32ri, X86::MOV32rm,
12358 X86::NOT32r, X86::EAX,
12359 X86::GR32RegisterClass);
12360 case X86::ATOMXOR32:
12361 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12362 X86::XOR32ri, X86::MOV32rm,
12364 X86::NOT32r, X86::EAX,
12365 X86::GR32RegisterClass);
12366 case X86::ATOMNAND32:
12367 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12368 X86::AND32ri, X86::MOV32rm,
12370 X86::NOT32r, X86::EAX,
12371 X86::GR32RegisterClass, true);
12372 case X86::ATOMMIN32:
12373 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12374 case X86::ATOMMAX32:
12375 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12376 case X86::ATOMUMIN32:
12377 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12378 case X86::ATOMUMAX32:
12379 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12381 case X86::ATOMAND16:
12382 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12383 X86::AND16ri, X86::MOV16rm,
12385 X86::NOT16r, X86::AX,
12386 X86::GR16RegisterClass);
12387 case X86::ATOMOR16:
12388 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12389 X86::OR16ri, X86::MOV16rm,
12391 X86::NOT16r, X86::AX,
12392 X86::GR16RegisterClass);
12393 case X86::ATOMXOR16:
12394 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12395 X86::XOR16ri, X86::MOV16rm,
12397 X86::NOT16r, X86::AX,
12398 X86::GR16RegisterClass);
12399 case X86::ATOMNAND16:
12400 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12401 X86::AND16ri, X86::MOV16rm,
12403 X86::NOT16r, X86::AX,
12404 X86::GR16RegisterClass, true);
12405 case X86::ATOMMIN16:
12406 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12407 case X86::ATOMMAX16:
12408 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12409 case X86::ATOMUMIN16:
12410 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12411 case X86::ATOMUMAX16:
12412 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12414 case X86::ATOMAND8:
12415 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12416 X86::AND8ri, X86::MOV8rm,
12418 X86::NOT8r, X86::AL,
12419 X86::GR8RegisterClass);
12421 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12422 X86::OR8ri, X86::MOV8rm,
12424 X86::NOT8r, X86::AL,
12425 X86::GR8RegisterClass);
12426 case X86::ATOMXOR8:
12427 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12428 X86::XOR8ri, X86::MOV8rm,
12430 X86::NOT8r, X86::AL,
12431 X86::GR8RegisterClass);
12432 case X86::ATOMNAND8:
12433 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12434 X86::AND8ri, X86::MOV8rm,
12436 X86::NOT8r, X86::AL,
12437 X86::GR8RegisterClass, true);
12438 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12439 // This group is for 64-bit host.
12440 case X86::ATOMAND64:
12441 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12442 X86::AND64ri32, X86::MOV64rm,
12444 X86::NOT64r, X86::RAX,
12445 X86::GR64RegisterClass);
12446 case X86::ATOMOR64:
12447 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12448 X86::OR64ri32, X86::MOV64rm,
12450 X86::NOT64r, X86::RAX,
12451 X86::GR64RegisterClass);
12452 case X86::ATOMXOR64:
12453 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12454 X86::XOR64ri32, X86::MOV64rm,
12456 X86::NOT64r, X86::RAX,
12457 X86::GR64RegisterClass);
12458 case X86::ATOMNAND64:
12459 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12460 X86::AND64ri32, X86::MOV64rm,
12462 X86::NOT64r, X86::RAX,
12463 X86::GR64RegisterClass, true);
12464 case X86::ATOMMIN64:
12465 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12466 case X86::ATOMMAX64:
12467 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12468 case X86::ATOMUMIN64:
12469 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12470 case X86::ATOMUMAX64:
12471 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12473 // This group does 64-bit operations on a 32-bit host.
12474 case X86::ATOMAND6432:
12475 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12476 X86::AND32rr, X86::AND32rr,
12477 X86::AND32ri, X86::AND32ri,
12479 case X86::ATOMOR6432:
12480 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12481 X86::OR32rr, X86::OR32rr,
12482 X86::OR32ri, X86::OR32ri,
12484 case X86::ATOMXOR6432:
12485 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12486 X86::XOR32rr, X86::XOR32rr,
12487 X86::XOR32ri, X86::XOR32ri,
12489 case X86::ATOMNAND6432:
12490 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12491 X86::AND32rr, X86::AND32rr,
12492 X86::AND32ri, X86::AND32ri,
12494 case X86::ATOMADD6432:
12495 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12496 X86::ADD32rr, X86::ADC32rr,
12497 X86::ADD32ri, X86::ADC32ri,
12499 case X86::ATOMSUB6432:
12500 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12501 X86::SUB32rr, X86::SBB32rr,
12502 X86::SUB32ri, X86::SBB32ri,
12504 case X86::ATOMSWAP6432:
12505 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12506 X86::MOV32rr, X86::MOV32rr,
12507 X86::MOV32ri, X86::MOV32ri,
12509 case X86::VASTART_SAVE_XMM_REGS:
12510 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12512 case X86::VAARG_64:
12513 return EmitVAARG64WithCustomInserter(MI, BB);
12517 //===----------------------------------------------------------------------===//
12518 // X86 Optimization Hooks
12519 //===----------------------------------------------------------------------===//
12521 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12525 const SelectionDAG &DAG,
12526 unsigned Depth) const {
12527 unsigned Opc = Op.getOpcode();
12528 assert((Opc >= ISD::BUILTIN_OP_END ||
12529 Opc == ISD::INTRINSIC_WO_CHAIN ||
12530 Opc == ISD::INTRINSIC_W_CHAIN ||
12531 Opc == ISD::INTRINSIC_VOID) &&
12532 "Should use MaskedValueIsZero if you don't know whether Op"
12533 " is a target node!");
12535 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12549 // These nodes' second result is a boolean.
12550 if (Op.getResNo() == 0)
12553 case X86ISD::SETCC:
12554 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12555 Mask.getBitWidth() - 1);
12557 case ISD::INTRINSIC_WO_CHAIN: {
12558 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12559 unsigned NumLoBits = 0;
12562 case Intrinsic::x86_sse_movmsk_ps:
12563 case Intrinsic::x86_avx_movmsk_ps_256:
12564 case Intrinsic::x86_sse2_movmsk_pd:
12565 case Intrinsic::x86_avx_movmsk_pd_256:
12566 case Intrinsic::x86_mmx_pmovmskb:
12567 case Intrinsic::x86_sse2_pmovmskb_128:
12568 case Intrinsic::x86_avx2_pmovmskb: {
12569 // High bits of movmskp{s|d}, pmovmskb are known zero.
12571 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12572 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12573 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12574 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12575 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12576 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12577 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12579 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12580 Mask.getBitWidth() - NumLoBits);
12589 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12590 unsigned Depth) const {
12591 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12592 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12593 return Op.getValueType().getScalarType().getSizeInBits();
12599 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12600 /// node is a GlobalAddress + offset.
12601 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12602 const GlobalValue* &GA,
12603 int64_t &Offset) const {
12604 if (N->getOpcode() == X86ISD::Wrapper) {
12605 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12606 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12607 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12611 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12614 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12615 /// same as extracting the high 128-bit part of 256-bit vector and then
12616 /// inserting the result into the low part of a new 256-bit vector
12617 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12618 EVT VT = SVOp->getValueType(0);
12619 int NumElems = VT.getVectorNumElements();
12621 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12622 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12623 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12624 SVOp->getMaskElt(j) >= 0)
12630 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12631 /// same as extracting the low 128-bit part of 256-bit vector and then
12632 /// inserting the result into the high part of a new 256-bit vector
12633 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12634 EVT VT = SVOp->getValueType(0);
12635 int NumElems = VT.getVectorNumElements();
12637 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12638 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12639 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12640 SVOp->getMaskElt(j) >= 0)
12646 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12647 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12648 TargetLowering::DAGCombinerInfo &DCI,
12650 DebugLoc dl = N->getDebugLoc();
12651 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12652 SDValue V1 = SVOp->getOperand(0);
12653 SDValue V2 = SVOp->getOperand(1);
12654 EVT VT = SVOp->getValueType(0);
12655 int NumElems = VT.getVectorNumElements();
12657 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12658 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12662 // V UNDEF BUILD_VECTOR UNDEF
12664 // CONCAT_VECTOR CONCAT_VECTOR
12667 // RESULT: V + zero extended
12669 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12670 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12671 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12674 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12677 // To match the shuffle mask, the first half of the mask should
12678 // be exactly the first vector, and all the rest a splat with the
12679 // first element of the second one.
12680 for (int i = 0; i < NumElems/2; ++i)
12681 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12682 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12685 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12686 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12687 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12688 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12690 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12692 Ld->getPointerInfo(),
12693 Ld->getAlignment(),
12694 false/*isVolatile*/, true/*ReadMem*/,
12695 false/*WriteMem*/);
12696 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12699 // Emit a zeroed vector and insert the desired subvector on its
12701 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, HasAVX2, DAG, dl);
12702 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12703 DAG.getConstant(0, MVT::i32), DAG, dl);
12704 return DCI.CombineTo(N, InsV);
12707 //===--------------------------------------------------------------------===//
12708 // Combine some shuffles into subvector extracts and inserts:
12711 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12712 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12713 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12715 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12716 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12717 return DCI.CombineTo(N, InsV);
12720 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12721 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12722 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12723 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12724 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12725 return DCI.CombineTo(N, InsV);
12731 /// PerformShuffleCombine - Performs several different shuffle combines.
12732 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12733 TargetLowering::DAGCombinerInfo &DCI,
12734 const X86Subtarget *Subtarget) {
12735 DebugLoc dl = N->getDebugLoc();
12736 EVT VT = N->getValueType(0);
12738 // Don't create instructions with illegal types after legalize types has run.
12739 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12740 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12743 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12744 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12745 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12746 return PerformShuffleCombine256(N, DAG, DCI, Subtarget->hasAVX2());
12748 // Only handle 128 wide vector from here on.
12749 if (VT.getSizeInBits() != 128)
12752 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12753 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12754 // consecutive, non-overlapping, and in the right order.
12755 SmallVector<SDValue, 16> Elts;
12756 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12757 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12759 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12762 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12763 /// generation and convert it from being a bunch of shuffles and extracts
12764 /// to a simple store and scalar loads to extract the elements.
12765 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12766 const TargetLowering &TLI) {
12767 SDValue InputVector = N->getOperand(0);
12769 // Only operate on vectors of 4 elements, where the alternative shuffling
12770 // gets to be more expensive.
12771 if (InputVector.getValueType() != MVT::v4i32)
12774 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12775 // single use which is a sign-extend or zero-extend, and all elements are
12777 SmallVector<SDNode *, 4> Uses;
12778 unsigned ExtractedElements = 0;
12779 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12780 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12781 if (UI.getUse().getResNo() != InputVector.getResNo())
12784 SDNode *Extract = *UI;
12785 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12788 if (Extract->getValueType(0) != MVT::i32)
12790 if (!Extract->hasOneUse())
12792 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12793 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12795 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12798 // Record which element was extracted.
12799 ExtractedElements |=
12800 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12802 Uses.push_back(Extract);
12805 // If not all the elements were used, this may not be worthwhile.
12806 if (ExtractedElements != 15)
12809 // Ok, we've now decided to do the transformation.
12810 DebugLoc dl = InputVector.getDebugLoc();
12812 // Store the value to a temporary stack slot.
12813 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12814 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12815 MachinePointerInfo(), false, false, 0);
12817 // Replace each use (extract) with a load of the appropriate element.
12818 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12819 UE = Uses.end(); UI != UE; ++UI) {
12820 SDNode *Extract = *UI;
12822 // cOMpute the element's address.
12823 SDValue Idx = Extract->getOperand(1);
12825 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12826 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12827 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12829 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12830 StackPtr, OffsetVal);
12832 // Load the scalar.
12833 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12834 ScalarAddr, MachinePointerInfo(),
12835 false, false, false, 0);
12837 // Replace the exact with the load.
12838 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12841 // The replacement was made in place; don't return anything.
12845 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
12847 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12848 TargetLowering::DAGCombinerInfo &DCI,
12849 const X86Subtarget *Subtarget) {
12850 DebugLoc DL = N->getDebugLoc();
12851 SDValue Cond = N->getOperand(0);
12852 // Get the LHS/RHS of the select.
12853 SDValue LHS = N->getOperand(1);
12854 SDValue RHS = N->getOperand(2);
12855 EVT VT = LHS.getValueType();
12857 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12858 // instructions match the semantics of the common C idiom x<y?x:y but not
12859 // x<=y?x:y, because of how they handle negative zero (which can be
12860 // ignored in unsafe-math mode).
12861 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
12862 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
12863 (Subtarget->hasSSE2() ||
12864 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
12865 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12867 unsigned Opcode = 0;
12868 // Check for x CC y ? x : y.
12869 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12870 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12874 // Converting this to a min would handle NaNs incorrectly, and swapping
12875 // the operands would cause it to handle comparisons between positive
12876 // and negative zero incorrectly.
12877 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12878 if (!DAG.getTarget().Options.UnsafeFPMath &&
12879 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12881 std::swap(LHS, RHS);
12883 Opcode = X86ISD::FMIN;
12886 // Converting this to a min would handle comparisons between positive
12887 // and negative zero incorrectly.
12888 if (!DAG.getTarget().Options.UnsafeFPMath &&
12889 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12891 Opcode = X86ISD::FMIN;
12894 // Converting this to a min would handle both negative zeros and NaNs
12895 // incorrectly, but we can swap the operands to fix both.
12896 std::swap(LHS, RHS);
12900 Opcode = X86ISD::FMIN;
12904 // Converting this to a max would handle comparisons between positive
12905 // and negative zero incorrectly.
12906 if (!DAG.getTarget().Options.UnsafeFPMath &&
12907 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12909 Opcode = X86ISD::FMAX;
12912 // Converting this to a max would handle NaNs incorrectly, and swapping
12913 // the operands would cause it to handle comparisons between positive
12914 // and negative zero incorrectly.
12915 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12916 if (!DAG.getTarget().Options.UnsafeFPMath &&
12917 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12919 std::swap(LHS, RHS);
12921 Opcode = X86ISD::FMAX;
12924 // Converting this to a max would handle both negative zeros and NaNs
12925 // incorrectly, but we can swap the operands to fix both.
12926 std::swap(LHS, RHS);
12930 Opcode = X86ISD::FMAX;
12933 // Check for x CC y ? y : x -- a min/max with reversed arms.
12934 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12935 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12939 // Converting this to a min would handle comparisons between positive
12940 // and negative zero incorrectly, and swapping the operands would
12941 // cause it to handle NaNs incorrectly.
12942 if (!DAG.getTarget().Options.UnsafeFPMath &&
12943 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12944 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12946 std::swap(LHS, RHS);
12948 Opcode = X86ISD::FMIN;
12951 // Converting this to a min would handle NaNs incorrectly.
12952 if (!DAG.getTarget().Options.UnsafeFPMath &&
12953 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12955 Opcode = X86ISD::FMIN;
12958 // Converting this to a min would handle both negative zeros and NaNs
12959 // incorrectly, but we can swap the operands to fix both.
12960 std::swap(LHS, RHS);
12964 Opcode = X86ISD::FMIN;
12968 // Converting this to a max would handle NaNs incorrectly.
12969 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12971 Opcode = X86ISD::FMAX;
12974 // Converting this to a max would handle comparisons between positive
12975 // and negative zero incorrectly, and swapping the operands would
12976 // cause it to handle NaNs incorrectly.
12977 if (!DAG.getTarget().Options.UnsafeFPMath &&
12978 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12979 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12981 std::swap(LHS, RHS);
12983 Opcode = X86ISD::FMAX;
12986 // Converting this to a max would handle both negative zeros and NaNs
12987 // incorrectly, but we can swap the operands to fix both.
12988 std::swap(LHS, RHS);
12992 Opcode = X86ISD::FMAX;
12998 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13001 // If this is a select between two integer constants, try to do some
13003 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13004 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13005 // Don't do this for crazy integer types.
13006 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13007 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13008 // so that TrueC (the true value) is larger than FalseC.
13009 bool NeedsCondInvert = false;
13011 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13012 // Efficiently invertible.
13013 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13014 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13015 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13016 NeedsCondInvert = true;
13017 std::swap(TrueC, FalseC);
13020 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13021 if (FalseC->getAPIntValue() == 0 &&
13022 TrueC->getAPIntValue().isPowerOf2()) {
13023 if (NeedsCondInvert) // Invert the condition if needed.
13024 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13025 DAG.getConstant(1, Cond.getValueType()));
13027 // Zero extend the condition if needed.
13028 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13030 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13031 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13032 DAG.getConstant(ShAmt, MVT::i8));
13035 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13036 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13037 if (NeedsCondInvert) // Invert the condition if needed.
13038 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13039 DAG.getConstant(1, Cond.getValueType()));
13041 // Zero extend the condition if needed.
13042 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13043 FalseC->getValueType(0), Cond);
13044 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13045 SDValue(FalseC, 0));
13048 // Optimize cases that will turn into an LEA instruction. This requires
13049 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13050 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13051 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13052 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13054 bool isFastMultiplier = false;
13056 switch ((unsigned char)Diff) {
13058 case 1: // result = add base, cond
13059 case 2: // result = lea base( , cond*2)
13060 case 3: // result = lea base(cond, cond*2)
13061 case 4: // result = lea base( , cond*4)
13062 case 5: // result = lea base(cond, cond*4)
13063 case 8: // result = lea base( , cond*8)
13064 case 9: // result = lea base(cond, cond*8)
13065 isFastMultiplier = true;
13070 if (isFastMultiplier) {
13071 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13072 if (NeedsCondInvert) // Invert the condition if needed.
13073 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13074 DAG.getConstant(1, Cond.getValueType()));
13076 // Zero extend the condition if needed.
13077 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13079 // Scale the condition by the difference.
13081 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13082 DAG.getConstant(Diff, Cond.getValueType()));
13084 // Add the base if non-zero.
13085 if (FalseC->getAPIntValue() != 0)
13086 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13087 SDValue(FalseC, 0));
13094 // Canonicalize max and min:
13095 // (x > y) ? x : y -> (x >= y) ? x : y
13096 // (x < y) ? x : y -> (x <= y) ? x : y
13097 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13098 // the need for an extra compare
13099 // against zero. e.g.
13100 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13102 // testl %edi, %edi
13104 // cmovgl %edi, %eax
13108 // cmovsl %eax, %edi
13109 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13110 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13111 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13112 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13117 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13118 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13119 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13120 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13125 // If we know that this node is legal then we know that it is going to be
13126 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13127 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13128 // to simplify previous instructions.
13129 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13130 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13131 !DCI.isBeforeLegalize() &&
13132 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13133 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13134 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13135 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13137 APInt KnownZero, KnownOne;
13138 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13139 DCI.isBeforeLegalizeOps());
13140 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13141 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13142 DCI.CommitTargetLoweringOpt(TLO);
13148 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13149 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13150 TargetLowering::DAGCombinerInfo &DCI) {
13151 DebugLoc DL = N->getDebugLoc();
13153 // If the flag operand isn't dead, don't touch this CMOV.
13154 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13157 SDValue FalseOp = N->getOperand(0);
13158 SDValue TrueOp = N->getOperand(1);
13159 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13160 SDValue Cond = N->getOperand(3);
13161 if (CC == X86::COND_E || CC == X86::COND_NE) {
13162 switch (Cond.getOpcode()) {
13166 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13167 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13168 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13172 // If this is a select between two integer constants, try to do some
13173 // optimizations. Note that the operands are ordered the opposite of SELECT
13175 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13176 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13177 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13178 // larger than FalseC (the false value).
13179 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13180 CC = X86::GetOppositeBranchCondition(CC);
13181 std::swap(TrueC, FalseC);
13184 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13185 // This is efficient for any integer data type (including i8/i16) and
13187 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13188 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13189 DAG.getConstant(CC, MVT::i8), Cond);
13191 // Zero extend the condition if needed.
13192 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13194 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13195 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13196 DAG.getConstant(ShAmt, MVT::i8));
13197 if (N->getNumValues() == 2) // Dead flag value?
13198 return DCI.CombineTo(N, Cond, SDValue());
13202 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13203 // for any integer data type, including i8/i16.
13204 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13205 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13206 DAG.getConstant(CC, MVT::i8), Cond);
13208 // Zero extend the condition if needed.
13209 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13210 FalseC->getValueType(0), Cond);
13211 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13212 SDValue(FalseC, 0));
13214 if (N->getNumValues() == 2) // Dead flag value?
13215 return DCI.CombineTo(N, Cond, SDValue());
13219 // Optimize cases that will turn into an LEA instruction. This requires
13220 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13221 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13222 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13223 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13225 bool isFastMultiplier = false;
13227 switch ((unsigned char)Diff) {
13229 case 1: // result = add base, cond
13230 case 2: // result = lea base( , cond*2)
13231 case 3: // result = lea base(cond, cond*2)
13232 case 4: // result = lea base( , cond*4)
13233 case 5: // result = lea base(cond, cond*4)
13234 case 8: // result = lea base( , cond*8)
13235 case 9: // result = lea base(cond, cond*8)
13236 isFastMultiplier = true;
13241 if (isFastMultiplier) {
13242 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13243 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13244 DAG.getConstant(CC, MVT::i8), Cond);
13245 // Zero extend the condition if needed.
13246 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13248 // Scale the condition by the difference.
13250 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13251 DAG.getConstant(Diff, Cond.getValueType()));
13253 // Add the base if non-zero.
13254 if (FalseC->getAPIntValue() != 0)
13255 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13256 SDValue(FalseC, 0));
13257 if (N->getNumValues() == 2) // Dead flag value?
13258 return DCI.CombineTo(N, Cond, SDValue());
13268 /// PerformMulCombine - Optimize a single multiply with constant into two
13269 /// in order to implement it with two cheaper instructions, e.g.
13270 /// LEA + SHL, LEA + LEA.
13271 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13272 TargetLowering::DAGCombinerInfo &DCI) {
13273 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13276 EVT VT = N->getValueType(0);
13277 if (VT != MVT::i64)
13280 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13283 uint64_t MulAmt = C->getZExtValue();
13284 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13287 uint64_t MulAmt1 = 0;
13288 uint64_t MulAmt2 = 0;
13289 if ((MulAmt % 9) == 0) {
13291 MulAmt2 = MulAmt / 9;
13292 } else if ((MulAmt % 5) == 0) {
13294 MulAmt2 = MulAmt / 5;
13295 } else if ((MulAmt % 3) == 0) {
13297 MulAmt2 = MulAmt / 3;
13300 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13301 DebugLoc DL = N->getDebugLoc();
13303 if (isPowerOf2_64(MulAmt2) &&
13304 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13305 // If second multiplifer is pow2, issue it first. We want the multiply by
13306 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13308 std::swap(MulAmt1, MulAmt2);
13311 if (isPowerOf2_64(MulAmt1))
13312 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13313 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13315 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13316 DAG.getConstant(MulAmt1, VT));
13318 if (isPowerOf2_64(MulAmt2))
13319 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13320 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13322 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13323 DAG.getConstant(MulAmt2, VT));
13325 // Do not add new nodes to DAG combiner worklist.
13326 DCI.CombineTo(N, NewMul, false);
13331 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13332 SDValue N0 = N->getOperand(0);
13333 SDValue N1 = N->getOperand(1);
13334 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13335 EVT VT = N0.getValueType();
13337 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13338 // since the result of setcc_c is all zero's or all ones.
13339 if (VT.isInteger() && !VT.isVector() &&
13340 N1C && N0.getOpcode() == ISD::AND &&
13341 N0.getOperand(1).getOpcode() == ISD::Constant) {
13342 SDValue N00 = N0.getOperand(0);
13343 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13344 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13345 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13346 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13347 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13348 APInt ShAmt = N1C->getAPIntValue();
13349 Mask = Mask.shl(ShAmt);
13351 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13352 N00, DAG.getConstant(Mask, VT));
13357 // Hardware support for vector shifts is sparse which makes us scalarize the
13358 // vector operations in many cases. Also, on sandybridge ADD is faster than
13360 // (shl V, 1) -> add V,V
13361 if (isSplatVector(N1.getNode())) {
13362 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13363 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13364 // We shift all of the values by one. In many cases we do not have
13365 // hardware support for this operation. This is better expressed as an ADD
13367 if (N1C && (1 == N1C->getZExtValue())) {
13368 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13375 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13377 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13378 const X86Subtarget *Subtarget) {
13379 EVT VT = N->getValueType(0);
13380 if (N->getOpcode() == ISD::SHL) {
13381 SDValue V = PerformSHLCombine(N, DAG);
13382 if (V.getNode()) return V;
13385 // On X86 with SSE2 support, we can transform this to a vector shift if
13386 // all elements are shifted by the same amount. We can't do this in legalize
13387 // because the a constant vector is typically transformed to a constant pool
13388 // so we have no knowledge of the shift amount.
13389 if (!Subtarget->hasSSE2())
13392 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13393 (!Subtarget->hasAVX2() ||
13394 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13397 SDValue ShAmtOp = N->getOperand(1);
13398 EVT EltVT = VT.getVectorElementType();
13399 DebugLoc DL = N->getDebugLoc();
13400 SDValue BaseShAmt = SDValue();
13401 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13402 unsigned NumElts = VT.getVectorNumElements();
13404 for (; i != NumElts; ++i) {
13405 SDValue Arg = ShAmtOp.getOperand(i);
13406 if (Arg.getOpcode() == ISD::UNDEF) continue;
13410 // Handle the case where the build_vector is all undef
13411 // FIXME: Should DAG allow this?
13415 for (; i != NumElts; ++i) {
13416 SDValue Arg = ShAmtOp.getOperand(i);
13417 if (Arg.getOpcode() == ISD::UNDEF) continue;
13418 if (Arg != BaseShAmt) {
13422 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13423 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13424 SDValue InVec = ShAmtOp.getOperand(0);
13425 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13426 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13428 for (; i != NumElts; ++i) {
13429 SDValue Arg = InVec.getOperand(i);
13430 if (Arg.getOpcode() == ISD::UNDEF) continue;
13434 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13435 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13436 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13437 if (C->getZExtValue() == SplatIdx)
13438 BaseShAmt = InVec.getOperand(1);
13441 if (BaseShAmt.getNode() == 0)
13442 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13443 DAG.getIntPtrConstant(0));
13447 // The shift amount is an i32.
13448 if (EltVT.bitsGT(MVT::i32))
13449 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13450 else if (EltVT.bitsLT(MVT::i32))
13451 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13453 // The shift amount is identical so we can do a vector shift.
13454 SDValue ValOp = N->getOperand(0);
13455 switch (N->getOpcode()) {
13457 llvm_unreachable("Unknown shift opcode!");
13460 if (VT == MVT::v2i64)
13461 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13462 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
13464 if (VT == MVT::v4i32)
13465 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13466 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
13468 if (VT == MVT::v8i16)
13469 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13470 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
13472 if (VT == MVT::v4i64)
13473 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13474 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
13476 if (VT == MVT::v8i32)
13477 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13478 DAG.getConstant(Intrinsic::x86_avx2_pslli_d, MVT::i32),
13480 if (VT == MVT::v16i16)
13481 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13482 DAG.getConstant(Intrinsic::x86_avx2_pslli_w, MVT::i32),
13486 if (VT == MVT::v4i32)
13487 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13488 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
13490 if (VT == MVT::v8i16)
13491 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13492 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
13494 if (VT == MVT::v8i32)
13495 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13496 DAG.getConstant(Intrinsic::x86_avx2_psrai_d, MVT::i32),
13498 if (VT == MVT::v16i16)
13499 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13500 DAG.getConstant(Intrinsic::x86_avx2_psrai_w, MVT::i32),
13504 if (VT == MVT::v2i64)
13505 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13506 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
13508 if (VT == MVT::v4i32)
13509 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13510 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
13512 if (VT == MVT::v8i16)
13513 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13514 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
13516 if (VT == MVT::v4i64)
13517 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13518 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
13520 if (VT == MVT::v8i32)
13521 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13522 DAG.getConstant(Intrinsic::x86_avx2_psrli_d, MVT::i32),
13524 if (VT == MVT::v16i16)
13525 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13526 DAG.getConstant(Intrinsic::x86_avx2_psrli_w, MVT::i32),
13534 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13535 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13536 // and friends. Likewise for OR -> CMPNEQSS.
13537 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13538 TargetLowering::DAGCombinerInfo &DCI,
13539 const X86Subtarget *Subtarget) {
13542 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13543 // we're requiring SSE2 for both.
13544 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13545 SDValue N0 = N->getOperand(0);
13546 SDValue N1 = N->getOperand(1);
13547 SDValue CMP0 = N0->getOperand(1);
13548 SDValue CMP1 = N1->getOperand(1);
13549 DebugLoc DL = N->getDebugLoc();
13551 // The SETCCs should both refer to the same CMP.
13552 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13555 SDValue CMP00 = CMP0->getOperand(0);
13556 SDValue CMP01 = CMP0->getOperand(1);
13557 EVT VT = CMP00.getValueType();
13559 if (VT == MVT::f32 || VT == MVT::f64) {
13560 bool ExpectingFlags = false;
13561 // Check for any users that want flags:
13562 for (SDNode::use_iterator UI = N->use_begin(),
13564 !ExpectingFlags && UI != UE; ++UI)
13565 switch (UI->getOpcode()) {
13570 ExpectingFlags = true;
13572 case ISD::CopyToReg:
13573 case ISD::SIGN_EXTEND:
13574 case ISD::ZERO_EXTEND:
13575 case ISD::ANY_EXTEND:
13579 if (!ExpectingFlags) {
13580 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13581 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13583 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13584 X86::CondCode tmp = cc0;
13589 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13590 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13591 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13592 X86ISD::NodeType NTOperator = is64BitFP ?
13593 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13594 // FIXME: need symbolic constants for these magic numbers.
13595 // See X86ATTInstPrinter.cpp:printSSECC().
13596 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13597 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13598 DAG.getConstant(x86cc, MVT::i8));
13599 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13601 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13602 DAG.getConstant(1, MVT::i32));
13603 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13604 return OneBitOfTruth;
13612 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13613 /// so it can be folded inside ANDNP.
13614 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13615 EVT VT = N->getValueType(0);
13617 // Match direct AllOnes for 128 and 256-bit vectors
13618 if (ISD::isBuildVectorAllOnes(N))
13621 // Look through a bit convert.
13622 if (N->getOpcode() == ISD::BITCAST)
13623 N = N->getOperand(0).getNode();
13625 // Sometimes the operand may come from a insert_subvector building a 256-bit
13627 if (VT.getSizeInBits() == 256 &&
13628 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13629 SDValue V1 = N->getOperand(0);
13630 SDValue V2 = N->getOperand(1);
13632 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13633 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13634 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13635 ISD::isBuildVectorAllOnes(V2.getNode()))
13642 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13643 TargetLowering::DAGCombinerInfo &DCI,
13644 const X86Subtarget *Subtarget) {
13645 if (DCI.isBeforeLegalizeOps())
13648 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13652 EVT VT = N->getValueType(0);
13654 // Create ANDN, BLSI, and BLSR instructions
13655 // BLSI is X & (-X)
13656 // BLSR is X & (X-1)
13657 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13658 SDValue N0 = N->getOperand(0);
13659 SDValue N1 = N->getOperand(1);
13660 DebugLoc DL = N->getDebugLoc();
13662 // Check LHS for not
13663 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13664 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13665 // Check RHS for not
13666 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13667 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13669 // Check LHS for neg
13670 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13671 isZero(N0.getOperand(0)))
13672 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13674 // Check RHS for neg
13675 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13676 isZero(N1.getOperand(0)))
13677 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13679 // Check LHS for X-1
13680 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13681 isAllOnes(N0.getOperand(1)))
13682 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13684 // Check RHS for X-1
13685 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13686 isAllOnes(N1.getOperand(1)))
13687 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13692 // Want to form ANDNP nodes:
13693 // 1) In the hopes of then easily combining them with OR and AND nodes
13694 // to form PBLEND/PSIGN.
13695 // 2) To match ANDN packed intrinsics
13696 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13699 SDValue N0 = N->getOperand(0);
13700 SDValue N1 = N->getOperand(1);
13701 DebugLoc DL = N->getDebugLoc();
13703 // Check LHS for vnot
13704 if (N0.getOpcode() == ISD::XOR &&
13705 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13706 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13707 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13709 // Check RHS for vnot
13710 if (N1.getOpcode() == ISD::XOR &&
13711 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13712 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13713 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13718 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13719 TargetLowering::DAGCombinerInfo &DCI,
13720 const X86Subtarget *Subtarget) {
13721 if (DCI.isBeforeLegalizeOps())
13724 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13728 EVT VT = N->getValueType(0);
13730 SDValue N0 = N->getOperand(0);
13731 SDValue N1 = N->getOperand(1);
13733 // look for psign/blend
13734 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13735 if (!Subtarget->hasSSSE3() ||
13736 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13739 // Canonicalize pandn to RHS
13740 if (N0.getOpcode() == X86ISD::ANDNP)
13742 // or (and (m, y), (pandn m, x))
13743 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13744 SDValue Mask = N1.getOperand(0);
13745 SDValue X = N1.getOperand(1);
13747 if (N0.getOperand(0) == Mask)
13748 Y = N0.getOperand(1);
13749 if (N0.getOperand(1) == Mask)
13750 Y = N0.getOperand(0);
13752 // Check to see if the mask appeared in both the AND and ANDNP and
13756 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13757 if (Mask.getOpcode() != ISD::BITCAST ||
13758 X.getOpcode() != ISD::BITCAST ||
13759 Y.getOpcode() != ISD::BITCAST)
13762 // Look through mask bitcast.
13763 Mask = Mask.getOperand(0);
13764 EVT MaskVT = Mask.getValueType();
13766 // Validate that the Mask operand is a vector sra node. The sra node
13767 // will be an intrinsic.
13768 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13771 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13772 // there is no psrai.b
13773 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13774 case Intrinsic::x86_sse2_psrai_w:
13775 case Intrinsic::x86_sse2_psrai_d:
13776 case Intrinsic::x86_avx2_psrai_w:
13777 case Intrinsic::x86_avx2_psrai_d:
13779 default: return SDValue();
13782 // Check that the SRA is all signbits.
13783 SDValue SraC = Mask.getOperand(2);
13784 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13785 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13786 if ((SraAmt + 1) != EltBits)
13789 DebugLoc DL = N->getDebugLoc();
13791 // Now we know we at least have a plendvb with the mask val. See if
13792 // we can form a psignb/w/d.
13793 // psign = x.type == y.type == mask.type && y = sub(0, x);
13794 X = X.getOperand(0);
13795 Y = Y.getOperand(0);
13796 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13797 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13798 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType() &&
13799 (EltBits == 8 || EltBits == 16 || EltBits == 32)) {
13800 SDValue Sign = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X,
13801 Mask.getOperand(1));
13802 return DAG.getNode(ISD::BITCAST, DL, VT, Sign);
13804 // PBLENDVB only available on SSE 4.1
13805 if (!Subtarget->hasSSE41())
13808 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
13810 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
13811 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
13812 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
13813 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
13814 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
13818 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
13821 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13822 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13824 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13826 if (!N0.hasOneUse() || !N1.hasOneUse())
13829 SDValue ShAmt0 = N0.getOperand(1);
13830 if (ShAmt0.getValueType() != MVT::i8)
13832 SDValue ShAmt1 = N1.getOperand(1);
13833 if (ShAmt1.getValueType() != MVT::i8)
13835 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13836 ShAmt0 = ShAmt0.getOperand(0);
13837 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13838 ShAmt1 = ShAmt1.getOperand(0);
13840 DebugLoc DL = N->getDebugLoc();
13841 unsigned Opc = X86ISD::SHLD;
13842 SDValue Op0 = N0.getOperand(0);
13843 SDValue Op1 = N1.getOperand(0);
13844 if (ShAmt0.getOpcode() == ISD::SUB) {
13845 Opc = X86ISD::SHRD;
13846 std::swap(Op0, Op1);
13847 std::swap(ShAmt0, ShAmt1);
13850 unsigned Bits = VT.getSizeInBits();
13851 if (ShAmt1.getOpcode() == ISD::SUB) {
13852 SDValue Sum = ShAmt1.getOperand(0);
13853 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13854 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13855 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13856 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13857 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13858 return DAG.getNode(Opc, DL, VT,
13860 DAG.getNode(ISD::TRUNCATE, DL,
13863 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13864 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13866 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13867 return DAG.getNode(Opc, DL, VT,
13868 N0.getOperand(0), N1.getOperand(0),
13869 DAG.getNode(ISD::TRUNCATE, DL,
13876 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
13877 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
13878 TargetLowering::DAGCombinerInfo &DCI,
13879 const X86Subtarget *Subtarget) {
13880 if (DCI.isBeforeLegalizeOps())
13883 EVT VT = N->getValueType(0);
13885 if (VT != MVT::i32 && VT != MVT::i64)
13888 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
13890 // Create BLSMSK instructions by finding X ^ (X-1)
13891 SDValue N0 = N->getOperand(0);
13892 SDValue N1 = N->getOperand(1);
13893 DebugLoc DL = N->getDebugLoc();
13895 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13896 isAllOnes(N0.getOperand(1)))
13897 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
13899 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13900 isAllOnes(N1.getOperand(1)))
13901 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
13906 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
13907 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
13908 const X86Subtarget *Subtarget) {
13909 LoadSDNode *Ld = cast<LoadSDNode>(N);
13910 EVT RegVT = Ld->getValueType(0);
13911 EVT MemVT = Ld->getMemoryVT();
13912 DebugLoc dl = Ld->getDebugLoc();
13913 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13915 ISD::LoadExtType Ext = Ld->getExtensionType();
13917 // If this is a vector EXT Load then attempt to optimize it using a
13918 // shuffle. We need SSE4 for the shuffles.
13919 // TODO: It is possible to support ZExt by zeroing the undef values
13920 // during the shuffle phase or after the shuffle.
13921 if (RegVT.isVector() && RegVT.isInteger() &&
13922 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
13923 assert(MemVT != RegVT && "Cannot extend to the same type");
13924 assert(MemVT.isVector() && "Must load a vector from memory");
13926 unsigned NumElems = RegVT.getVectorNumElements();
13927 unsigned RegSz = RegVT.getSizeInBits();
13928 unsigned MemSz = MemVT.getSizeInBits();
13929 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13930 // All sizes must be a power of two
13931 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
13933 // Attempt to load the original value using a single load op.
13934 // Find a scalar type which is equal to the loaded word size.
13935 MVT SclrLoadTy = MVT::i8;
13936 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13937 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13938 MVT Tp = (MVT::SimpleValueType)tp;
13939 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
13945 // Proceed if a load word is found.
13946 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
13948 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
13949 RegSz/SclrLoadTy.getSizeInBits());
13951 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13952 RegSz/MemVT.getScalarType().getSizeInBits());
13953 // Can't shuffle using an illegal type.
13954 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13956 // Perform a single load.
13957 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
13959 Ld->getPointerInfo(), Ld->isVolatile(),
13960 Ld->isNonTemporal(), Ld->isInvariant(),
13961 Ld->getAlignment());
13963 // Insert the word loaded into a vector.
13964 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13965 LoadUnitVecVT, ScalarLoad);
13967 // Bitcast the loaded value to a vector of the original element type, in
13968 // the size of the target vector type.
13969 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
13971 unsigned SizeRatio = RegSz/MemSz;
13973 // Redistribute the loaded elements into the different locations.
13974 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13975 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
13977 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13978 DAG.getUNDEF(SlicedVec.getValueType()),
13979 ShuffleVec.data());
13981 // Bitcast to the requested type.
13982 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13983 // Replace the original load with the new sequence
13984 // and return the new chain.
13985 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
13986 return SDValue(ScalarLoad.getNode(), 1);
13992 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13993 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13994 const X86Subtarget *Subtarget) {
13995 StoreSDNode *St = cast<StoreSDNode>(N);
13996 EVT VT = St->getValue().getValueType();
13997 EVT StVT = St->getMemoryVT();
13998 DebugLoc dl = St->getDebugLoc();
13999 SDValue StoredVal = St->getOperand(1);
14000 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14002 // If we are saving a concatenation of two XMM registers, perform two stores.
14003 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14004 // 128-bit ones. If in the future the cost becomes only one memory access the
14005 // first version would be better.
14006 if (VT.getSizeInBits() == 256 &&
14007 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14008 StoredVal.getNumOperands() == 2) {
14010 SDValue Value0 = StoredVal.getOperand(0);
14011 SDValue Value1 = StoredVal.getOperand(1);
14013 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14014 SDValue Ptr0 = St->getBasePtr();
14015 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14017 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14018 St->getPointerInfo(), St->isVolatile(),
14019 St->isNonTemporal(), St->getAlignment());
14020 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14021 St->getPointerInfo(), St->isVolatile(),
14022 St->isNonTemporal(), St->getAlignment());
14023 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14026 // Optimize trunc store (of multiple scalars) to shuffle and store.
14027 // First, pack all of the elements in one place. Next, store to memory
14028 // in fewer chunks.
14029 if (St->isTruncatingStore() && VT.isVector()) {
14030 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14031 unsigned NumElems = VT.getVectorNumElements();
14032 assert(StVT != VT && "Cannot truncate to the same type");
14033 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14034 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14036 // From, To sizes and ElemCount must be pow of two
14037 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14038 // We are going to use the original vector elt for storing.
14039 // Accumulated smaller vector elements must be a multiple of the store size.
14040 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14042 unsigned SizeRatio = FromSz / ToSz;
14044 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14046 // Create a type on which we perform the shuffle
14047 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14048 StVT.getScalarType(), NumElems*SizeRatio);
14050 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14052 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14053 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14054 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14056 // Can't shuffle using an illegal type
14057 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14059 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14060 DAG.getUNDEF(WideVec.getValueType()),
14061 ShuffleVec.data());
14062 // At this point all of the data is stored at the bottom of the
14063 // register. We now need to save it to mem.
14065 // Find the largest store unit
14066 MVT StoreType = MVT::i8;
14067 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14068 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14069 MVT Tp = (MVT::SimpleValueType)tp;
14070 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14074 // Bitcast the original vector into a vector of store-size units
14075 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14076 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14077 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14078 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14079 SmallVector<SDValue, 8> Chains;
14080 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14081 TLI.getPointerTy());
14082 SDValue Ptr = St->getBasePtr();
14084 // Perform one or more big stores into memory.
14085 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14086 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14087 StoreType, ShuffWide,
14088 DAG.getIntPtrConstant(i));
14089 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14090 St->getPointerInfo(), St->isVolatile(),
14091 St->isNonTemporal(), St->getAlignment());
14092 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14093 Chains.push_back(Ch);
14096 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14101 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14102 // the FP state in cases where an emms may be missing.
14103 // A preferable solution to the general problem is to figure out the right
14104 // places to insert EMMS. This qualifies as a quick hack.
14106 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14107 if (VT.getSizeInBits() != 64)
14110 const Function *F = DAG.getMachineFunction().getFunction();
14111 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14112 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14113 && Subtarget->hasSSE2();
14114 if ((VT.isVector() ||
14115 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14116 isa<LoadSDNode>(St->getValue()) &&
14117 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14118 St->getChain().hasOneUse() && !St->isVolatile()) {
14119 SDNode* LdVal = St->getValue().getNode();
14120 LoadSDNode *Ld = 0;
14121 int TokenFactorIndex = -1;
14122 SmallVector<SDValue, 8> Ops;
14123 SDNode* ChainVal = St->getChain().getNode();
14124 // Must be a store of a load. We currently handle two cases: the load
14125 // is a direct child, and it's under an intervening TokenFactor. It is
14126 // possible to dig deeper under nested TokenFactors.
14127 if (ChainVal == LdVal)
14128 Ld = cast<LoadSDNode>(St->getChain());
14129 else if (St->getValue().hasOneUse() &&
14130 ChainVal->getOpcode() == ISD::TokenFactor) {
14131 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
14132 if (ChainVal->getOperand(i).getNode() == LdVal) {
14133 TokenFactorIndex = i;
14134 Ld = cast<LoadSDNode>(St->getValue());
14136 Ops.push_back(ChainVal->getOperand(i));
14140 if (!Ld || !ISD::isNormalLoad(Ld))
14143 // If this is not the MMX case, i.e. we are just turning i64 load/store
14144 // into f64 load/store, avoid the transformation if there are multiple
14145 // uses of the loaded value.
14146 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14149 DebugLoc LdDL = Ld->getDebugLoc();
14150 DebugLoc StDL = N->getDebugLoc();
14151 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14152 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14154 if (Subtarget->is64Bit() || F64IsLegal) {
14155 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14156 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14157 Ld->getPointerInfo(), Ld->isVolatile(),
14158 Ld->isNonTemporal(), Ld->isInvariant(),
14159 Ld->getAlignment());
14160 SDValue NewChain = NewLd.getValue(1);
14161 if (TokenFactorIndex != -1) {
14162 Ops.push_back(NewChain);
14163 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14166 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14167 St->getPointerInfo(),
14168 St->isVolatile(), St->isNonTemporal(),
14169 St->getAlignment());
14172 // Otherwise, lower to two pairs of 32-bit loads / stores.
14173 SDValue LoAddr = Ld->getBasePtr();
14174 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14175 DAG.getConstant(4, MVT::i32));
14177 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14178 Ld->getPointerInfo(),
14179 Ld->isVolatile(), Ld->isNonTemporal(),
14180 Ld->isInvariant(), Ld->getAlignment());
14181 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14182 Ld->getPointerInfo().getWithOffset(4),
14183 Ld->isVolatile(), Ld->isNonTemporal(),
14185 MinAlign(Ld->getAlignment(), 4));
14187 SDValue NewChain = LoLd.getValue(1);
14188 if (TokenFactorIndex != -1) {
14189 Ops.push_back(LoLd);
14190 Ops.push_back(HiLd);
14191 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14195 LoAddr = St->getBasePtr();
14196 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14197 DAG.getConstant(4, MVT::i32));
14199 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14200 St->getPointerInfo(),
14201 St->isVolatile(), St->isNonTemporal(),
14202 St->getAlignment());
14203 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14204 St->getPointerInfo().getWithOffset(4),
14206 St->isNonTemporal(),
14207 MinAlign(St->getAlignment(), 4));
14208 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14213 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14214 /// and return the operands for the horizontal operation in LHS and RHS. A
14215 /// horizontal operation performs the binary operation on successive elements
14216 /// of its first operand, then on successive elements of its second operand,
14217 /// returning the resulting values in a vector. For example, if
14218 /// A = < float a0, float a1, float a2, float a3 >
14220 /// B = < float b0, float b1, float b2, float b3 >
14221 /// then the result of doing a horizontal operation on A and B is
14222 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14223 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14224 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14225 /// set to A, RHS to B, and the routine returns 'true'.
14226 /// Note that the binary operation should have the property that if one of the
14227 /// operands is UNDEF then the result is UNDEF.
14228 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14229 // Look for the following pattern: if
14230 // A = < float a0, float a1, float a2, float a3 >
14231 // B = < float b0, float b1, float b2, float b3 >
14233 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14234 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14235 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14236 // which is A horizontal-op B.
14238 // At least one of the operands should be a vector shuffle.
14239 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14240 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14243 EVT VT = LHS.getValueType();
14245 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14246 "Unsupported vector type for horizontal add/sub");
14248 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14249 // operate independently on 128-bit lanes.
14250 unsigned NumElts = VT.getVectorNumElements();
14251 unsigned NumLanes = VT.getSizeInBits()/128;
14252 unsigned NumLaneElts = NumElts / NumLanes;
14253 assert((NumLaneElts % 2 == 0) &&
14254 "Vector type should have an even number of elements in each lane");
14255 unsigned HalfLaneElts = NumLaneElts/2;
14257 // View LHS in the form
14258 // LHS = VECTOR_SHUFFLE A, B, LMask
14259 // If LHS is not a shuffle then pretend it is the shuffle
14260 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14261 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14264 SmallVector<int, 16> LMask(NumElts);
14265 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14266 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14267 A = LHS.getOperand(0);
14268 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14269 B = LHS.getOperand(1);
14270 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14271 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14273 if (LHS.getOpcode() != ISD::UNDEF)
14275 for (unsigned i = 0; i != NumElts; ++i)
14279 // Likewise, view RHS in the form
14280 // RHS = VECTOR_SHUFFLE C, D, RMask
14282 SmallVector<int, 16> RMask(NumElts);
14283 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14284 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14285 C = RHS.getOperand(0);
14286 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14287 D = RHS.getOperand(1);
14288 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14289 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14291 if (RHS.getOpcode() != ISD::UNDEF)
14293 for (unsigned i = 0; i != NumElts; ++i)
14297 // Check that the shuffles are both shuffling the same vectors.
14298 if (!(A == C && B == D) && !(A == D && B == C))
14301 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14302 if (!A.getNode() && !B.getNode())
14305 // If A and B occur in reverse order in RHS, then "swap" them (which means
14306 // rewriting the mask).
14308 CommuteVectorShuffleMask(RMask, NumElts);
14310 // At this point LHS and RHS are equivalent to
14311 // LHS = VECTOR_SHUFFLE A, B, LMask
14312 // RHS = VECTOR_SHUFFLE A, B, RMask
14313 // Check that the masks correspond to performing a horizontal operation.
14314 for (unsigned i = 0; i != NumElts; ++i) {
14315 int LIdx = LMask[i], RIdx = RMask[i];
14317 // Ignore any UNDEF components.
14318 if (LIdx < 0 || RIdx < 0 ||
14319 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14320 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14323 // Check that successive elements are being operated on. If not, this is
14324 // not a horizontal operation.
14325 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14326 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14327 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14328 if (!(LIdx == Index && RIdx == Index + 1) &&
14329 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14333 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14334 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14338 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14339 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14340 const X86Subtarget *Subtarget) {
14341 EVT VT = N->getValueType(0);
14342 SDValue LHS = N->getOperand(0);
14343 SDValue RHS = N->getOperand(1);
14345 // Try to synthesize horizontal adds from adds of shuffles.
14346 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14347 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14348 isHorizontalBinOp(LHS, RHS, true))
14349 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14353 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14354 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14355 const X86Subtarget *Subtarget) {
14356 EVT VT = N->getValueType(0);
14357 SDValue LHS = N->getOperand(0);
14358 SDValue RHS = N->getOperand(1);
14360 // Try to synthesize horizontal subs from subs of shuffles.
14361 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14362 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14363 isHorizontalBinOp(LHS, RHS, false))
14364 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14368 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14369 /// X86ISD::FXOR nodes.
14370 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14371 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14372 // F[X]OR(0.0, x) -> x
14373 // F[X]OR(x, 0.0) -> x
14374 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14375 if (C->getValueAPF().isPosZero())
14376 return N->getOperand(1);
14377 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14378 if (C->getValueAPF().isPosZero())
14379 return N->getOperand(0);
14383 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14384 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14385 // FAND(0.0, x) -> 0.0
14386 // FAND(x, 0.0) -> 0.0
14387 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14388 if (C->getValueAPF().isPosZero())
14389 return N->getOperand(0);
14390 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14391 if (C->getValueAPF().isPosZero())
14392 return N->getOperand(1);
14396 static SDValue PerformBTCombine(SDNode *N,
14398 TargetLowering::DAGCombinerInfo &DCI) {
14399 // BT ignores high bits in the bit index operand.
14400 SDValue Op1 = N->getOperand(1);
14401 if (Op1.hasOneUse()) {
14402 unsigned BitWidth = Op1.getValueSizeInBits();
14403 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14404 APInt KnownZero, KnownOne;
14405 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14406 !DCI.isBeforeLegalizeOps());
14407 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14408 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14409 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14410 DCI.CommitTargetLoweringOpt(TLO);
14415 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14416 SDValue Op = N->getOperand(0);
14417 if (Op.getOpcode() == ISD::BITCAST)
14418 Op = Op.getOperand(0);
14419 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14420 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14421 VT.getVectorElementType().getSizeInBits() ==
14422 OpVT.getVectorElementType().getSizeInBits()) {
14423 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14428 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
14429 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14430 // (and (i32 x86isd::setcc_carry), 1)
14431 // This eliminates the zext. This transformation is necessary because
14432 // ISD::SETCC is always legalized to i8.
14433 DebugLoc dl = N->getDebugLoc();
14434 SDValue N0 = N->getOperand(0);
14435 EVT VT = N->getValueType(0);
14436 if (N0.getOpcode() == ISD::AND &&
14438 N0.getOperand(0).hasOneUse()) {
14439 SDValue N00 = N0.getOperand(0);
14440 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14442 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14443 if (!C || C->getZExtValue() != 1)
14445 return DAG.getNode(ISD::AND, dl, VT,
14446 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14447 N00.getOperand(0), N00.getOperand(1)),
14448 DAG.getConstant(1, VT));
14454 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14455 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14456 unsigned X86CC = N->getConstantOperandVal(0);
14457 SDValue EFLAG = N->getOperand(1);
14458 DebugLoc DL = N->getDebugLoc();
14460 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14461 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14463 if (X86CC == X86::COND_B)
14464 return DAG.getNode(ISD::AND, DL, MVT::i8,
14465 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14466 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14467 DAG.getConstant(1, MVT::i8));
14472 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14473 const X86TargetLowering *XTLI) {
14474 SDValue Op0 = N->getOperand(0);
14475 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14476 // a 32-bit target where SSE doesn't support i64->FP operations.
14477 if (Op0.getOpcode() == ISD::LOAD) {
14478 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14479 EVT VT = Ld->getValueType(0);
14480 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14481 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14482 !XTLI->getSubtarget()->is64Bit() &&
14483 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14484 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14485 Ld->getChain(), Op0, DAG);
14486 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14493 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14494 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14495 X86TargetLowering::DAGCombinerInfo &DCI) {
14496 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14497 // the result is either zero or one (depending on the input carry bit).
14498 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14499 if (X86::isZeroNode(N->getOperand(0)) &&
14500 X86::isZeroNode(N->getOperand(1)) &&
14501 // We don't have a good way to replace an EFLAGS use, so only do this when
14503 SDValue(N, 1).use_empty()) {
14504 DebugLoc DL = N->getDebugLoc();
14505 EVT VT = N->getValueType(0);
14506 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14507 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14508 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14509 DAG.getConstant(X86::COND_B,MVT::i8),
14511 DAG.getConstant(1, VT));
14512 return DCI.CombineTo(N, Res1, CarryOut);
14518 // fold (add Y, (sete X, 0)) -> adc 0, Y
14519 // (add Y, (setne X, 0)) -> sbb -1, Y
14520 // (sub (sete X, 0), Y) -> sbb 0, Y
14521 // (sub (setne X, 0), Y) -> adc -1, Y
14522 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14523 DebugLoc DL = N->getDebugLoc();
14525 // Look through ZExts.
14526 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14527 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14530 SDValue SetCC = Ext.getOperand(0);
14531 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14534 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14535 if (CC != X86::COND_E && CC != X86::COND_NE)
14538 SDValue Cmp = SetCC.getOperand(1);
14539 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14540 !X86::isZeroNode(Cmp.getOperand(1)) ||
14541 !Cmp.getOperand(0).getValueType().isInteger())
14544 SDValue CmpOp0 = Cmp.getOperand(0);
14545 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14546 DAG.getConstant(1, CmpOp0.getValueType()));
14548 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14549 if (CC == X86::COND_NE)
14550 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14551 DL, OtherVal.getValueType(), OtherVal,
14552 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14553 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14554 DL, OtherVal.getValueType(), OtherVal,
14555 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14558 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14559 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14560 const X86Subtarget *Subtarget) {
14561 EVT VT = N->getValueType(0);
14562 SDValue Op0 = N->getOperand(0);
14563 SDValue Op1 = N->getOperand(1);
14565 // Try to synthesize horizontal adds from adds of shuffles.
14566 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14567 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14568 isHorizontalBinOp(Op0, Op1, true))
14569 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14571 return OptimizeConditionalInDecrement(N, DAG);
14574 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14575 const X86Subtarget *Subtarget) {
14576 SDValue Op0 = N->getOperand(0);
14577 SDValue Op1 = N->getOperand(1);
14579 // X86 can't encode an immediate LHS of a sub. See if we can push the
14580 // negation into a preceding instruction.
14581 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14582 // If the RHS of the sub is a XOR with one use and a constant, invert the
14583 // immediate. Then add one to the LHS of the sub so we can turn
14584 // X-Y -> X+~Y+1, saving one register.
14585 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14586 isa<ConstantSDNode>(Op1.getOperand(1))) {
14587 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14588 EVT VT = Op0.getValueType();
14589 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14591 DAG.getConstant(~XorC, VT));
14592 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14593 DAG.getConstant(C->getAPIntValue()+1, VT));
14597 // Try to synthesize horizontal adds from adds of shuffles.
14598 EVT VT = N->getValueType(0);
14599 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14600 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14601 isHorizontalBinOp(Op0, Op1, true))
14602 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14604 return OptimizeConditionalInDecrement(N, DAG);
14607 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14608 DAGCombinerInfo &DCI) const {
14609 SelectionDAG &DAG = DCI.DAG;
14610 switch (N->getOpcode()) {
14612 case ISD::EXTRACT_VECTOR_ELT:
14613 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14615 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
14616 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14617 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14618 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14619 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14620 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14623 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
14624 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14625 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14626 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14627 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14628 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14629 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14630 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14631 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14633 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14634 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14635 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14636 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14637 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
14638 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14639 case X86ISD::SHUFP: // Handle all target specific shuffles
14640 case X86ISD::PALIGN:
14641 case X86ISD::UNPCKH:
14642 case X86ISD::UNPCKL:
14643 case X86ISD::MOVHLPS:
14644 case X86ISD::MOVLHPS:
14645 case X86ISD::PSHUFD:
14646 case X86ISD::PSHUFHW:
14647 case X86ISD::PSHUFLW:
14648 case X86ISD::MOVSS:
14649 case X86ISD::MOVSD:
14650 case X86ISD::VPERMILP:
14651 case X86ISD::VPERM2X128:
14652 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14658 /// isTypeDesirableForOp - Return true if the target has native support for
14659 /// the specified value type and it is 'desirable' to use the type for the
14660 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14661 /// instruction encodings are longer and some i16 instructions are slow.
14662 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14663 if (!isTypeLegal(VT))
14665 if (VT != MVT::i16)
14672 case ISD::SIGN_EXTEND:
14673 case ISD::ZERO_EXTEND:
14674 case ISD::ANY_EXTEND:
14687 /// IsDesirableToPromoteOp - This method query the target whether it is
14688 /// beneficial for dag combiner to promote the specified node. If true, it
14689 /// should return the desired promotion type by reference.
14690 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14691 EVT VT = Op.getValueType();
14692 if (VT != MVT::i16)
14695 bool Promote = false;
14696 bool Commute = false;
14697 switch (Op.getOpcode()) {
14700 LoadSDNode *LD = cast<LoadSDNode>(Op);
14701 // If the non-extending load has a single use and it's not live out, then it
14702 // might be folded.
14703 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14704 Op.hasOneUse()*/) {
14705 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14706 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14707 // The only case where we'd want to promote LOAD (rather then it being
14708 // promoted as an operand is when it's only use is liveout.
14709 if (UI->getOpcode() != ISD::CopyToReg)
14716 case ISD::SIGN_EXTEND:
14717 case ISD::ZERO_EXTEND:
14718 case ISD::ANY_EXTEND:
14723 SDValue N0 = Op.getOperand(0);
14724 // Look out for (store (shl (load), x)).
14725 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
14738 SDValue N0 = Op.getOperand(0);
14739 SDValue N1 = Op.getOperand(1);
14740 if (!Commute && MayFoldLoad(N1))
14742 // Avoid disabling potential load folding opportunities.
14743 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14745 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14755 //===----------------------------------------------------------------------===//
14756 // X86 Inline Assembly Support
14757 //===----------------------------------------------------------------------===//
14760 // Helper to match a string separated by whitespace.
14761 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
14762 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
14764 for (unsigned i = 0, e = args.size(); i != e; ++i) {
14765 StringRef piece(*args[i]);
14766 if (!s.startswith(piece)) // Check if the piece matches.
14769 s = s.substr(piece.size());
14770 StringRef::size_type pos = s.find_first_not_of(" \t");
14771 if (pos == 0) // We matched a prefix.
14779 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
14782 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
14783 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
14785 std::string AsmStr = IA->getAsmString();
14787 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14788 if (!Ty || Ty->getBitWidth() % 16 != 0)
14791 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
14792 SmallVector<StringRef, 4> AsmPieces;
14793 SplitString(AsmStr, AsmPieces, ";\n");
14795 switch (AsmPieces.size()) {
14796 default: return false;
14798 // FIXME: this should verify that we are targeting a 486 or better. If not,
14799 // we will turn this bswap into something that will be lowered to logical
14800 // ops instead of emitting the bswap asm. For now, we don't support 486 or
14801 // lower so don't worry about this.
14803 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
14804 matchAsm(AsmPieces[0], "bswapl", "$0") ||
14805 matchAsm(AsmPieces[0], "bswapq", "$0") ||
14806 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
14807 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
14808 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
14809 // No need to check constraints, nothing other than the equivalent of
14810 // "=r,0" would be valid here.
14811 return IntrinsicLowering::LowerToByteSwap(CI);
14814 // rorw $$8, ${0:w} --> llvm.bswap.i16
14815 if (CI->getType()->isIntegerTy(16) &&
14816 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
14817 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
14818 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
14820 const std::string &ConstraintsStr = IA->getConstraintString();
14821 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14822 std::sort(AsmPieces.begin(), AsmPieces.end());
14823 if (AsmPieces.size() == 4 &&
14824 AsmPieces[0] == "~{cc}" &&
14825 AsmPieces[1] == "~{dirflag}" &&
14826 AsmPieces[2] == "~{flags}" &&
14827 AsmPieces[3] == "~{fpsr}")
14828 return IntrinsicLowering::LowerToByteSwap(CI);
14832 if (CI->getType()->isIntegerTy(32) &&
14833 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
14834 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
14835 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
14836 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
14838 const std::string &ConstraintsStr = IA->getConstraintString();
14839 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14840 std::sort(AsmPieces.begin(), AsmPieces.end());
14841 if (AsmPieces.size() == 4 &&
14842 AsmPieces[0] == "~{cc}" &&
14843 AsmPieces[1] == "~{dirflag}" &&
14844 AsmPieces[2] == "~{flags}" &&
14845 AsmPieces[3] == "~{fpsr}")
14846 return IntrinsicLowering::LowerToByteSwap(CI);
14849 if (CI->getType()->isIntegerTy(64)) {
14850 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
14851 if (Constraints.size() >= 2 &&
14852 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
14853 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
14854 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
14855 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
14856 matchAsm(AsmPieces[1], "bswap", "%edx") &&
14857 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
14858 return IntrinsicLowering::LowerToByteSwap(CI);
14868 /// getConstraintType - Given a constraint letter, return the type of
14869 /// constraint it is for this target.
14870 X86TargetLowering::ConstraintType
14871 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
14872 if (Constraint.size() == 1) {
14873 switch (Constraint[0]) {
14884 return C_RegisterClass;
14908 return TargetLowering::getConstraintType(Constraint);
14911 /// Examine constraint type and operand type and determine a weight value.
14912 /// This object must already have been set up with the operand type
14913 /// and the current alternative constraint selected.
14914 TargetLowering::ConstraintWeight
14915 X86TargetLowering::getSingleConstraintMatchWeight(
14916 AsmOperandInfo &info, const char *constraint) const {
14917 ConstraintWeight weight = CW_Invalid;
14918 Value *CallOperandVal = info.CallOperandVal;
14919 // If we don't have a value, we can't do a match,
14920 // but allow it at the lowest weight.
14921 if (CallOperandVal == NULL)
14923 Type *type = CallOperandVal->getType();
14924 // Look at the constraint type.
14925 switch (*constraint) {
14927 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14938 if (CallOperandVal->getType()->isIntegerTy())
14939 weight = CW_SpecificReg;
14944 if (type->isFloatingPointTy())
14945 weight = CW_SpecificReg;
14948 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14949 weight = CW_SpecificReg;
14953 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
14954 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
14955 weight = CW_Register;
14958 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
14959 if (C->getZExtValue() <= 31)
14960 weight = CW_Constant;
14964 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14965 if (C->getZExtValue() <= 63)
14966 weight = CW_Constant;
14970 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14971 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
14972 weight = CW_Constant;
14976 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14977 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14978 weight = CW_Constant;
14982 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14983 if (C->getZExtValue() <= 3)
14984 weight = CW_Constant;
14988 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14989 if (C->getZExtValue() <= 0xff)
14990 weight = CW_Constant;
14995 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14996 weight = CW_Constant;
15000 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15001 if ((C->getSExtValue() >= -0x80000000LL) &&
15002 (C->getSExtValue() <= 0x7fffffffLL))
15003 weight = CW_Constant;
15007 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15008 if (C->getZExtValue() <= 0xffffffff)
15009 weight = CW_Constant;
15016 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15017 /// with another that has more specific requirements based on the type of the
15018 /// corresponding operand.
15019 const char *X86TargetLowering::
15020 LowerXConstraint(EVT ConstraintVT) const {
15021 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15022 // 'f' like normal targets.
15023 if (ConstraintVT.isFloatingPoint()) {
15024 if (Subtarget->hasSSE2())
15026 if (Subtarget->hasSSE1())
15030 return TargetLowering::LowerXConstraint(ConstraintVT);
15033 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15034 /// vector. If it is invalid, don't add anything to Ops.
15035 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15036 std::string &Constraint,
15037 std::vector<SDValue>&Ops,
15038 SelectionDAG &DAG) const {
15039 SDValue Result(0, 0);
15041 // Only support length 1 constraints for now.
15042 if (Constraint.length() > 1) return;
15044 char ConstraintLetter = Constraint[0];
15045 switch (ConstraintLetter) {
15048 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15049 if (C->getZExtValue() <= 31) {
15050 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15056 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15057 if (C->getZExtValue() <= 63) {
15058 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15064 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15065 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15066 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15072 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15073 if (C->getZExtValue() <= 255) {
15074 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15080 // 32-bit signed value
15081 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15082 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15083 C->getSExtValue())) {
15084 // Widen to 64 bits here to get it sign extended.
15085 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15088 // FIXME gcc accepts some relocatable values here too, but only in certain
15089 // memory models; it's complicated.
15094 // 32-bit unsigned value
15095 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15096 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15097 C->getZExtValue())) {
15098 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15102 // FIXME gcc accepts some relocatable values here too, but only in certain
15103 // memory models; it's complicated.
15107 // Literal immediates are always ok.
15108 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15109 // Widen to 64 bits here to get it sign extended.
15110 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15114 // In any sort of PIC mode addresses need to be computed at runtime by
15115 // adding in a register or some sort of table lookup. These can't
15116 // be used as immediates.
15117 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15120 // If we are in non-pic codegen mode, we allow the address of a global (with
15121 // an optional displacement) to be used with 'i'.
15122 GlobalAddressSDNode *GA = 0;
15123 int64_t Offset = 0;
15125 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15127 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15128 Offset += GA->getOffset();
15130 } else if (Op.getOpcode() == ISD::ADD) {
15131 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15132 Offset += C->getZExtValue();
15133 Op = Op.getOperand(0);
15136 } else if (Op.getOpcode() == ISD::SUB) {
15137 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15138 Offset += -C->getZExtValue();
15139 Op = Op.getOperand(0);
15144 // Otherwise, this isn't something we can handle, reject it.
15148 const GlobalValue *GV = GA->getGlobal();
15149 // If we require an extra load to get this address, as in PIC mode, we
15150 // can't accept it.
15151 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15152 getTargetMachine())))
15155 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15156 GA->getValueType(0), Offset);
15161 if (Result.getNode()) {
15162 Ops.push_back(Result);
15165 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15168 std::pair<unsigned, const TargetRegisterClass*>
15169 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15171 // First, see if this is a constraint that directly corresponds to an LLVM
15173 if (Constraint.size() == 1) {
15174 // GCC Constraint Letters
15175 switch (Constraint[0]) {
15177 // TODO: Slight differences here in allocation order and leaving
15178 // RIP in the class. Do they matter any more here than they do
15179 // in the normal allocation?
15180 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15181 if (Subtarget->is64Bit()) {
15182 if (VT == MVT::i32 || VT == MVT::f32)
15183 return std::make_pair(0U, X86::GR32RegisterClass);
15184 else if (VT == MVT::i16)
15185 return std::make_pair(0U, X86::GR16RegisterClass);
15186 else if (VT == MVT::i8 || VT == MVT::i1)
15187 return std::make_pair(0U, X86::GR8RegisterClass);
15188 else if (VT == MVT::i64 || VT == MVT::f64)
15189 return std::make_pair(0U, X86::GR64RegisterClass);
15192 // 32-bit fallthrough
15193 case 'Q': // Q_REGS
15194 if (VT == MVT::i32 || VT == MVT::f32)
15195 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15196 else if (VT == MVT::i16)
15197 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15198 else if (VT == MVT::i8 || VT == MVT::i1)
15199 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15200 else if (VT == MVT::i64)
15201 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15203 case 'r': // GENERAL_REGS
15204 case 'l': // INDEX_REGS
15205 if (VT == MVT::i8 || VT == MVT::i1)
15206 return std::make_pair(0U, X86::GR8RegisterClass);
15207 if (VT == MVT::i16)
15208 return std::make_pair(0U, X86::GR16RegisterClass);
15209 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15210 return std::make_pair(0U, X86::GR32RegisterClass);
15211 return std::make_pair(0U, X86::GR64RegisterClass);
15212 case 'R': // LEGACY_REGS
15213 if (VT == MVT::i8 || VT == MVT::i1)
15214 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15215 if (VT == MVT::i16)
15216 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15217 if (VT == MVT::i32 || !Subtarget->is64Bit())
15218 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15219 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15220 case 'f': // FP Stack registers.
15221 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15222 // value to the correct fpstack register class.
15223 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15224 return std::make_pair(0U, X86::RFP32RegisterClass);
15225 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15226 return std::make_pair(0U, X86::RFP64RegisterClass);
15227 return std::make_pair(0U, X86::RFP80RegisterClass);
15228 case 'y': // MMX_REGS if MMX allowed.
15229 if (!Subtarget->hasMMX()) break;
15230 return std::make_pair(0U, X86::VR64RegisterClass);
15231 case 'Y': // SSE_REGS if SSE2 allowed
15232 if (!Subtarget->hasSSE2()) break;
15234 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15235 if (!Subtarget->hasSSE1()) break;
15237 switch (VT.getSimpleVT().SimpleTy) {
15239 // Scalar SSE types.
15242 return std::make_pair(0U, X86::FR32RegisterClass);
15245 return std::make_pair(0U, X86::FR64RegisterClass);
15253 return std::make_pair(0U, X86::VR128RegisterClass);
15261 return std::make_pair(0U, X86::VR256RegisterClass);
15268 // Use the default implementation in TargetLowering to convert the register
15269 // constraint into a member of a register class.
15270 std::pair<unsigned, const TargetRegisterClass*> Res;
15271 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15273 // Not found as a standard register?
15274 if (Res.second == 0) {
15275 // Map st(0) -> st(7) -> ST0
15276 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15277 tolower(Constraint[1]) == 's' &&
15278 tolower(Constraint[2]) == 't' &&
15279 Constraint[3] == '(' &&
15280 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15281 Constraint[5] == ')' &&
15282 Constraint[6] == '}') {
15284 Res.first = X86::ST0+Constraint[4]-'0';
15285 Res.second = X86::RFP80RegisterClass;
15289 // GCC allows "st(0)" to be called just plain "st".
15290 if (StringRef("{st}").equals_lower(Constraint)) {
15291 Res.first = X86::ST0;
15292 Res.second = X86::RFP80RegisterClass;
15297 if (StringRef("{flags}").equals_lower(Constraint)) {
15298 Res.first = X86::EFLAGS;
15299 Res.second = X86::CCRRegisterClass;
15303 // 'A' means EAX + EDX.
15304 if (Constraint == "A") {
15305 Res.first = X86::EAX;
15306 Res.second = X86::GR32_ADRegisterClass;
15312 // Otherwise, check to see if this is a register class of the wrong value
15313 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15314 // turn into {ax},{dx}.
15315 if (Res.second->hasType(VT))
15316 return Res; // Correct type already, nothing to do.
15318 // All of the single-register GCC register classes map their values onto
15319 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15320 // really want an 8-bit or 32-bit register, map to the appropriate register
15321 // class and return the appropriate register.
15322 if (Res.second == X86::GR16RegisterClass) {
15323 if (VT == MVT::i8) {
15324 unsigned DestReg = 0;
15325 switch (Res.first) {
15327 case X86::AX: DestReg = X86::AL; break;
15328 case X86::DX: DestReg = X86::DL; break;
15329 case X86::CX: DestReg = X86::CL; break;
15330 case X86::BX: DestReg = X86::BL; break;
15333 Res.first = DestReg;
15334 Res.second = X86::GR8RegisterClass;
15336 } else if (VT == MVT::i32) {
15337 unsigned DestReg = 0;
15338 switch (Res.first) {
15340 case X86::AX: DestReg = X86::EAX; break;
15341 case X86::DX: DestReg = X86::EDX; break;
15342 case X86::CX: DestReg = X86::ECX; break;
15343 case X86::BX: DestReg = X86::EBX; break;
15344 case X86::SI: DestReg = X86::ESI; break;
15345 case X86::DI: DestReg = X86::EDI; break;
15346 case X86::BP: DestReg = X86::EBP; break;
15347 case X86::SP: DestReg = X86::ESP; break;
15350 Res.first = DestReg;
15351 Res.second = X86::GR32RegisterClass;
15353 } else if (VT == MVT::i64) {
15354 unsigned DestReg = 0;
15355 switch (Res.first) {
15357 case X86::AX: DestReg = X86::RAX; break;
15358 case X86::DX: DestReg = X86::RDX; break;
15359 case X86::CX: DestReg = X86::RCX; break;
15360 case X86::BX: DestReg = X86::RBX; break;
15361 case X86::SI: DestReg = X86::RSI; break;
15362 case X86::DI: DestReg = X86::RDI; break;
15363 case X86::BP: DestReg = X86::RBP; break;
15364 case X86::SP: DestReg = X86::RSP; break;
15367 Res.first = DestReg;
15368 Res.second = X86::GR64RegisterClass;
15371 } else if (Res.second == X86::FR32RegisterClass ||
15372 Res.second == X86::FR64RegisterClass ||
15373 Res.second == X86::VR128RegisterClass) {
15374 // Handle references to XMM physical registers that got mapped into the
15375 // wrong class. This can happen with constraints like {xmm0} where the
15376 // target independent register mapper will just pick the first match it can
15377 // find, ignoring the required type.
15378 if (VT == MVT::f32)
15379 Res.second = X86::FR32RegisterClass;
15380 else if (VT == MVT::f64)
15381 Res.second = X86::FR64RegisterClass;
15382 else if (X86::VR128RegisterClass->hasType(VT))
15383 Res.second = X86::VR128RegisterClass;