1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
55 using namespace dwarf;
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
63 static SDValue Insert128BitVector(SDValue Result,
69 static SDValue Extract128BitVector(SDValue Vec,
74 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
75 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
76 /// simple subregister reference. Idx is an index in the 128 bits we
77 /// want. It need not be aligned to a 128-bit bounday. That makes
78 /// lowering EXTRACT_VECTOR_ELT operations easier.
79 static SDValue Extract128BitVector(SDValue Vec,
83 EVT VT = Vec.getValueType();
84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
85 EVT ElVT = VT.getVectorElementType();
86 int Factor = VT.getSizeInBits()/128;
87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
88 VT.getVectorNumElements()/Factor);
90 // Extract from UNDEF is UNDEF.
91 if (Vec.getOpcode() == ISD::UNDEF)
92 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
94 if (isa<ConstantSDNode>(Idx)) {
95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
98 // we can match to VEXTRACTF128.
99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
101 // This is the index of the first element of the 128-bit chunk
103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
116 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
117 /// sets things up to match to an AVX VINSERTF128 instruction or a
118 /// simple superregister reference. Idx is an index in the 128 bits
119 /// we want. It need not be aligned to a 128-bit bounday. That makes
120 /// lowering INSERT_VECTOR_ELT operations easier.
121 static SDValue Insert128BitVector(SDValue Result,
126 if (isa<ConstantSDNode>(Idx)) {
127 EVT VT = Vec.getValueType();
128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
130 EVT ElVT = VT.getVectorElementType();
131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
132 EVT ResultVT = Result.getValueType();
134 // Insert the relevant 128 bits.
135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
137 // This is the index of the first element of the 128-bit chunk
139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
151 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
153 bool is64Bit = Subtarget->is64Bit();
155 if (Subtarget->isTargetEnvMacho()) {
157 return new X8664_MachoTargetObjectFile();
158 return new TargetLoweringObjectFileMachO();
161 if (Subtarget->isTargetELF())
162 return new TargetLoweringObjectFileELF();
163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
164 return new TargetLoweringObjectFileCOFF();
165 llvm_unreachable("unknown subtarget type");
168 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
169 : TargetLowering(TM, createTLOF(TM)) {
170 Subtarget = &TM.getSubtarget<X86Subtarget>();
171 X86ScalarSSEf64 = Subtarget->hasXMMInt();
172 X86ScalarSSEf32 = Subtarget->hasXMM();
173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
175 RegInfo = TM.getRegisterInfo();
176 TD = getTargetData();
178 // Set up the TargetLowering object.
179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
181 // X86 is weird, it always uses i8 for shift amounts and setcc results.
182 setBooleanContents(ZeroOrOneBooleanContent);
184 // For 64-bit since we have so many registers use the ILP scheduler, for
185 // 32-bit code use the register pressure specific scheduling.
186 if (Subtarget->is64Bit())
187 setSchedulingPreference(Sched::ILP);
189 setSchedulingPreference(Sched::RegPressure);
190 setStackPointerRegisterToSaveRestore(X86StackPtr);
192 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
193 // Setup Windows compiler runtime calls.
194 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
195 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
196 setLibcallName(RTLIB::SREM_I64, "_allrem");
197 setLibcallName(RTLIB::UREM_I64, "_aullrem");
198 setLibcallName(RTLIB::MUL_I64, "_allmul");
199 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
200 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
201 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
202 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
203 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
207 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
210 if (Subtarget->isTargetDarwin()) {
211 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
212 setUseUnderscoreSetJmp(false);
213 setUseUnderscoreLongJmp(false);
214 } else if (Subtarget->isTargetMingw()) {
215 // MS runtime is weird: it exports _setjmp, but longjmp!
216 setUseUnderscoreSetJmp(true);
217 setUseUnderscoreLongJmp(false);
219 setUseUnderscoreSetJmp(true);
220 setUseUnderscoreLongJmp(true);
223 // Set up the register classes.
224 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
225 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
226 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
227 if (Subtarget->is64Bit())
228 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
232 // We don't accept any truncstore of integer registers.
233 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
235 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
236 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
237 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
238 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
240 // SETOEQ and SETUNE require checking two conditions.
241 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
243 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
248 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
254 if (Subtarget->is64Bit()) {
255 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
257 } else if (!UseSoftFloat) {
258 // We have an algorithm for SSE2->double, and we turn this into a
259 // 64-bit FILD followed by conditional FADD for other targets.
260 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
261 // We have an algorithm for SSE2, and we turn this into a 64-bit
262 // FILD for other targets.
263 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
272 // SSE has no i16 to fp conversion, only i32
273 if (X86ScalarSSEf32) {
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
275 // f32 and f64 cases are Legal, f80 case is not
276 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
286 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
287 // are Legal, f80 is custom lowered.
288 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
289 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
291 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
293 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
294 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
296 if (X86ScalarSSEf32) {
297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
298 // f32 and f64 cases are Legal, f80 case is not
299 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
305 // Handle FP_TO_UINT by promoting the destination to a larger signed
307 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
309 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
311 if (Subtarget->is64Bit()) {
312 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
313 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
314 } else if (!UseSoftFloat) {
315 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
327 if (!X86ScalarSSEf64) {
328 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
329 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
330 if (Subtarget->is64Bit()) {
331 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
332 // Without SSE, i64->f64 goes through memory.
333 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
337 // Scalar integer divide and remainder are lowered to use operations that
338 // produce two results, to match the available instructions. This exposes
339 // the two-result form to trivial CSE, which is able to combine x/y and x%y
340 // into a single instruction.
342 // Scalar integer multiply-high is also lowered to use two-result
343 // operations, to match the available instructions. However, plain multiply
344 // (low) operations are left as Legal, as there are single-result
345 // instructions for this in x86. Using the two-result multiply instructions
346 // when both high and low results are needed must be arranged by dagcombine.
347 for (unsigned i = 0, e = 4; i != e; ++i) {
349 setOperationAction(ISD::MULHS, VT, Expand);
350 setOperationAction(ISD::MULHU, VT, Expand);
351 setOperationAction(ISD::SDIV, VT, Expand);
352 setOperationAction(ISD::UDIV, VT, Expand);
353 setOperationAction(ISD::SREM, VT, Expand);
354 setOperationAction(ISD::UREM, VT, Expand);
356 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
357 setOperationAction(ISD::ADDC, VT, Custom);
358 setOperationAction(ISD::ADDE, VT, Custom);
359 setOperationAction(ISD::SUBC, VT, Custom);
360 setOperationAction(ISD::SUBE, VT, Custom);
363 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
364 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
365 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
366 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
367 if (Subtarget->is64Bit())
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
372 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
373 setOperationAction(ISD::FREM , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f64 , Expand);
375 setOperationAction(ISD::FREM , MVT::f80 , Expand);
376 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
378 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
379 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
380 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
381 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
382 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
383 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
384 if (Subtarget->is64Bit()) {
385 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
386 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
400 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
402 // These should be promoted to a larger select which is supported.
403 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
404 // X86 wants to expand cmov itself.
405 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
406 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
407 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
408 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
409 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
412 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
414 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
415 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
421 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
425 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
426 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
427 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
430 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
431 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
432 if (Subtarget->is64Bit()) {
433 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
434 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
435 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
436 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
437 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
439 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
440 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
441 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
442 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
443 if (Subtarget->is64Bit()) {
444 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
449 if (Subtarget->hasXMM())
450 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
452 // We may not have a libcall for MEMBARRIER so we should lower this.
453 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
455 // On X86 and X86-64, atomic operations are lowered to locked instructions.
456 // Locked instructions, in turn, have implicit fence semantics (all memory
457 // operations are flushed before issuing the locked instruction, and they
458 // are not buffered), so we can fold away the common pattern of
459 // fence-atomic-fence.
460 setShouldFoldAtomicFences(true);
462 // Expand certain atomics
463 for (unsigned i = 0, e = 4; i != e; ++i) {
465 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
466 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 if (!Subtarget->is64Bit()) {
470 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
471 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
472 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
473 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
474 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
475 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
476 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
479 // FIXME - use subtarget debug flags
480 if (!Subtarget->isTargetDarwin() &&
481 !Subtarget->isTargetELF() &&
482 !Subtarget->isTargetCygMing()) {
483 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
486 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
487 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
488 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
489 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
490 if (Subtarget->is64Bit()) {
491 setExceptionPointerRegister(X86::RAX);
492 setExceptionSelectorRegister(X86::RDX);
494 setExceptionPointerRegister(X86::EAX);
495 setExceptionSelectorRegister(X86::EDX);
497 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
498 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
500 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
502 setOperationAction(ISD::TRAP, MVT::Other, Legal);
504 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
505 setOperationAction(ISD::VASTART , MVT::Other, Custom);
506 setOperationAction(ISD::VAEND , MVT::Other, Expand);
507 if (Subtarget->is64Bit()) {
508 setOperationAction(ISD::VAARG , MVT::Other, Custom);
509 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
511 setOperationAction(ISD::VAARG , MVT::Other, Expand);
512 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
515 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
516 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
517 setOperationAction(ISD::DYNAMIC_STACKALLOC,
518 (Subtarget->is64Bit() ? MVT::i64 : MVT::i32),
519 (Subtarget->isTargetCOFF()
520 && !Subtarget->isTargetEnvMacho()
523 if (!UseSoftFloat && X86ScalarSSEf64) {
524 // f32 and f64 use SSE.
525 // Set up the FP register classes.
526 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
527 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
529 // Use ANDPD to simulate FABS.
530 setOperationAction(ISD::FABS , MVT::f64, Custom);
531 setOperationAction(ISD::FABS , MVT::f32, Custom);
533 // Use XORP to simulate FNEG.
534 setOperationAction(ISD::FNEG , MVT::f64, Custom);
535 setOperationAction(ISD::FNEG , MVT::f32, Custom);
537 // Use ANDPD and ORPD to simulate FCOPYSIGN.
538 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
539 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
541 // Lower this to FGETSIGNx86 plus an AND.
542 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
543 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
545 // We don't support sin/cos/fmod
546 setOperationAction(ISD::FSIN , MVT::f64, Expand);
547 setOperationAction(ISD::FCOS , MVT::f64, Expand);
548 setOperationAction(ISD::FSIN , MVT::f32, Expand);
549 setOperationAction(ISD::FCOS , MVT::f32, Expand);
551 // Expand FP immediates into loads from the stack, except for the special
553 addLegalFPImmediate(APFloat(+0.0)); // xorpd
554 addLegalFPImmediate(APFloat(+0.0f)); // xorps
555 } else if (!UseSoftFloat && X86ScalarSSEf32) {
556 // Use SSE for f32, x87 for f64.
557 // Set up the FP register classes.
558 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
559 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
561 // Use ANDPS to simulate FABS.
562 setOperationAction(ISD::FABS , MVT::f32, Custom);
564 // Use XORP to simulate FNEG.
565 setOperationAction(ISD::FNEG , MVT::f32, Custom);
567 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
569 // Use ANDPS and ORPS to simulate FCOPYSIGN.
570 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
571 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
573 // We don't support sin/cos/fmod
574 setOperationAction(ISD::FSIN , MVT::f32, Expand);
575 setOperationAction(ISD::FCOS , MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
585 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
586 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
588 } else if (!UseSoftFloat) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
592 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
601 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
603 addLegalFPImmediate(APFloat(+0.0)); // FLD0
604 addLegalFPImmediate(APFloat(+1.0)); // FLD1
605 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
606 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
607 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
613 // We don't support FMA.
614 setOperationAction(ISD::FMA, MVT::f64, Expand);
615 setOperationAction(ISD::FMA, MVT::f32, Expand);
617 // Long double always uses X87.
619 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
620 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
621 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
623 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
624 addLegalFPImmediate(TmpFlt); // FLD0
626 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
629 APFloat TmpFlt2(+1.0);
630 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
632 addLegalFPImmediate(TmpFlt2); // FLD1
633 TmpFlt2.changeSign();
634 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
638 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
639 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
642 setOperationAction(ISD::FMA, MVT::f80, Expand);
645 // Always use a library call for pow.
646 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
647 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
648 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
650 setOperationAction(ISD::FLOG, MVT::f80, Expand);
651 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
652 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
653 setOperationAction(ISD::FEXP, MVT::f80, Expand);
654 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
656 // First set operation action for all vector types to either promote
657 // (for widening) or expand (for scalarization). Then we will selectively
658 // turn on ones that can be effectively codegen'd.
659 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
660 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
661 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
662 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
663 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
664 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
665 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
666 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
667 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
668 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
669 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
670 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
671 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
672 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
673 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
674 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
675 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
676 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
677 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
678 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
679 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
680 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
681 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
682 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
683 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
684 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
685 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
686 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
687 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
688 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
689 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
690 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
691 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
692 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
693 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
694 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
695 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
711 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
715 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
716 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
717 setTruncStoreAction((MVT::SimpleValueType)VT,
718 (MVT::SimpleValueType)InnerVT, Expand);
719 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
720 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
721 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
724 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
725 // with -msoft-float, disable use of MMX as well.
726 if (!UseSoftFloat && Subtarget->hasMMX()) {
727 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
728 // No operations on x86mmx supported, everything uses intrinsics.
731 // MMX-sized vectors (other than x86mmx) are expected to be expanded
732 // into smaller operations.
733 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
734 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
735 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
736 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
737 setOperationAction(ISD::AND, MVT::v8i8, Expand);
738 setOperationAction(ISD::AND, MVT::v4i16, Expand);
739 setOperationAction(ISD::AND, MVT::v2i32, Expand);
740 setOperationAction(ISD::AND, MVT::v1i64, Expand);
741 setOperationAction(ISD::OR, MVT::v8i8, Expand);
742 setOperationAction(ISD::OR, MVT::v4i16, Expand);
743 setOperationAction(ISD::OR, MVT::v2i32, Expand);
744 setOperationAction(ISD::OR, MVT::v1i64, Expand);
745 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
746 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
747 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
748 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
749 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
750 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
751 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
752 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
753 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
754 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
755 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
756 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
757 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
758 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
759 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
760 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
761 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
763 if (!UseSoftFloat && Subtarget->hasXMM()) {
764 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
766 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
767 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
768 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
769 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
770 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
771 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
772 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
773 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
774 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
776 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
777 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
780 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
781 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
783 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
784 // registers cannot be used even for integer operations.
785 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
786 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
787 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
788 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
790 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
791 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
792 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
793 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
794 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
795 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
796 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
797 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
798 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
799 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
800 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
801 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
802 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
803 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
804 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
805 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
807 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
808 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
809 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
810 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
812 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
813 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
814 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
815 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
816 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
818 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
819 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
820 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
821 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
822 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
824 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
825 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
826 EVT VT = (MVT::SimpleValueType)i;
827 // Do not attempt to custom lower non-power-of-2 vectors
828 if (!isPowerOf2_32(VT.getVectorNumElements()))
830 // Do not attempt to custom lower non-128-bit vectors
831 if (!VT.is128BitVector())
833 setOperationAction(ISD::BUILD_VECTOR,
834 VT.getSimpleVT().SimpleTy, Custom);
835 setOperationAction(ISD::VECTOR_SHUFFLE,
836 VT.getSimpleVT().SimpleTy, Custom);
837 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
838 VT.getSimpleVT().SimpleTy, Custom);
841 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
842 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
843 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
844 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
846 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
848 if (Subtarget->is64Bit()) {
849 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
850 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
853 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
854 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
855 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
858 // Do not attempt to promote non-128-bit vectors
859 if (!VT.is128BitVector())
862 setOperationAction(ISD::AND, SVT, Promote);
863 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
864 setOperationAction(ISD::OR, SVT, Promote);
865 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
866 setOperationAction(ISD::XOR, SVT, Promote);
867 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
868 setOperationAction(ISD::LOAD, SVT, Promote);
869 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
870 setOperationAction(ISD::SELECT, SVT, Promote);
871 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
874 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
876 // Custom lower v2i64 and v2f64 selects.
877 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
878 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
879 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
880 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
882 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
883 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
886 if (Subtarget->hasSSE41()) {
887 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
888 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
889 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
890 setOperationAction(ISD::FRINT, MVT::f32, Legal);
891 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
892 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
893 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
894 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
895 setOperationAction(ISD::FRINT, MVT::f64, Legal);
896 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
898 // FIXME: Do we need to handle scalar-to-vector here?
899 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
901 // Can turn SHL into an integer multiply.
902 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
903 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
905 // i8 and i16 vectors are custom , because the source register and source
906 // source memory operand types are not the same width. f32 vectors are
907 // custom since the immediate controlling the insert encodes additional
909 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
910 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
914 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
916 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
917 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
919 if (Subtarget->is64Bit()) {
920 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
921 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
925 if (Subtarget->hasSSE2()) {
926 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
927 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
928 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
930 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
931 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
932 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
934 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
935 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
938 if (Subtarget->hasSSE42())
939 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
941 if (!UseSoftFloat && Subtarget->hasAVX()) {
942 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
943 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
944 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
945 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
946 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
947 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
949 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
950 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
951 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
953 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
954 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
955 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
956 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
957 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
958 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
960 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
961 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
962 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
963 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
964 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
965 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
967 // Custom lower several nodes for 256-bit types.
968 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
969 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
970 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
973 // Extract subvector is special because the value type
974 // (result) is 128-bit but the source is 256-bit wide.
975 if (VT.is128BitVector())
976 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
978 // Do not attempt to custom lower other non-256-bit vectors
979 if (!VT.is256BitVector())
982 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
983 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
984 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
985 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
986 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
987 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
990 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
991 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
992 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
995 // Do not attempt to promote non-256-bit vectors
996 if (!VT.is256BitVector())
999 setOperationAction(ISD::AND, SVT, Promote);
1000 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1001 setOperationAction(ISD::OR, SVT, Promote);
1002 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1003 setOperationAction(ISD::XOR, SVT, Promote);
1004 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1005 setOperationAction(ISD::LOAD, SVT, Promote);
1006 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1007 setOperationAction(ISD::SELECT, SVT, Promote);
1008 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1012 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1013 // of this type with custom code.
1014 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1015 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1016 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1019 // We want to custom lower some of our intrinsics.
1020 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1023 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1024 // handle type legalization for these operations here.
1026 // FIXME: We really should do custom legalization for addition and
1027 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1028 // than generic legalization for 64-bit multiplication-with-overflow, though.
1029 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1030 // Add/Sub/Mul with overflow operations are custom lowered.
1032 setOperationAction(ISD::SADDO, VT, Custom);
1033 setOperationAction(ISD::UADDO, VT, Custom);
1034 setOperationAction(ISD::SSUBO, VT, Custom);
1035 setOperationAction(ISD::USUBO, VT, Custom);
1036 setOperationAction(ISD::SMULO, VT, Custom);
1037 setOperationAction(ISD::UMULO, VT, Custom);
1040 // There are no 8-bit 3-address imul/mul instructions
1041 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1042 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1044 if (!Subtarget->is64Bit()) {
1045 // These libcalls are not available in 32-bit.
1046 setLibcallName(RTLIB::SHL_I128, 0);
1047 setLibcallName(RTLIB::SRL_I128, 0);
1048 setLibcallName(RTLIB::SRA_I128, 0);
1051 // We have target-specific dag combine patterns for the following nodes:
1052 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1053 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1054 setTargetDAGCombine(ISD::BUILD_VECTOR);
1055 setTargetDAGCombine(ISD::SELECT);
1056 setTargetDAGCombine(ISD::SHL);
1057 setTargetDAGCombine(ISD::SRA);
1058 setTargetDAGCombine(ISD::SRL);
1059 setTargetDAGCombine(ISD::OR);
1060 setTargetDAGCombine(ISD::AND);
1061 setTargetDAGCombine(ISD::ADD);
1062 setTargetDAGCombine(ISD::SUB);
1063 setTargetDAGCombine(ISD::STORE);
1064 setTargetDAGCombine(ISD::ZERO_EXTEND);
1065 setTargetDAGCombine(ISD::SINT_TO_FP);
1066 if (Subtarget->is64Bit())
1067 setTargetDAGCombine(ISD::MUL);
1069 computeRegisterProperties();
1071 // On Darwin, -Os means optimize for size without hurting performance,
1072 // do not reduce the limit.
1073 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1074 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1075 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1076 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1077 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1078 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1079 setPrefLoopAlignment(16);
1080 benefitFromCodePlacementOpt = true;
1082 setPrefFunctionAlignment(4);
1086 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1091 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1092 /// the desired ByVal argument alignment.
1093 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1096 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1097 if (VTy->getBitWidth() == 128)
1099 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1100 unsigned EltAlign = 0;
1101 getMaxByValAlign(ATy->getElementType(), EltAlign);
1102 if (EltAlign > MaxAlign)
1103 MaxAlign = EltAlign;
1104 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1105 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1106 unsigned EltAlign = 0;
1107 getMaxByValAlign(STy->getElementType(i), EltAlign);
1108 if (EltAlign > MaxAlign)
1109 MaxAlign = EltAlign;
1117 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1118 /// function arguments in the caller parameter area. For X86, aggregates
1119 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1120 /// are at 4-byte boundaries.
1121 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1122 if (Subtarget->is64Bit()) {
1123 // Max of 8 and alignment of type.
1124 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1131 if (Subtarget->hasXMM())
1132 getMaxByValAlign(Ty, Align);
1136 /// getOptimalMemOpType - Returns the target specific optimal type for load
1137 /// and store operations as a result of memset, memcpy, and memmove
1138 /// lowering. If DstAlign is zero that means it's safe to destination
1139 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1140 /// means there isn't a need to check it against alignment requirement,
1141 /// probably because the source does not need to be loaded. If
1142 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1143 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1144 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1145 /// constant so it does not need to be loaded.
1146 /// It returns EVT::Other if the type should be determined using generic
1147 /// target-independent logic.
1149 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1150 unsigned DstAlign, unsigned SrcAlign,
1151 bool NonScalarIntSafe,
1153 MachineFunction &MF) const {
1154 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1155 // linux. This is because the stack realignment code can't handle certain
1156 // cases like PR2962. This should be removed when PR2962 is fixed.
1157 const Function *F = MF.getFunction();
1158 if (NonScalarIntSafe &&
1159 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1161 (Subtarget->isUnalignedMemAccessFast() ||
1162 ((DstAlign == 0 || DstAlign >= 16) &&
1163 (SrcAlign == 0 || SrcAlign >= 16))) &&
1164 Subtarget->getStackAlignment() >= 16) {
1165 if (Subtarget->hasSSE2())
1167 if (Subtarget->hasSSE1())
1169 } else if (!MemcpyStrSrc && Size >= 8 &&
1170 !Subtarget->is64Bit() &&
1171 Subtarget->getStackAlignment() >= 8 &&
1172 Subtarget->hasXMMInt()) {
1173 // Do not use f64 to lower memcpy if source is string constant. It's
1174 // better to use i32 to avoid the loads.
1178 if (Subtarget->is64Bit() && Size >= 8)
1183 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1184 /// current function. The returned value is a member of the
1185 /// MachineJumpTableInfo::JTEntryKind enum.
1186 unsigned X86TargetLowering::getJumpTableEncoding() const {
1187 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1189 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1190 Subtarget->isPICStyleGOT())
1191 return MachineJumpTableInfo::EK_Custom32;
1193 // Otherwise, use the normal jump table encoding heuristics.
1194 return TargetLowering::getJumpTableEncoding();
1198 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1199 const MachineBasicBlock *MBB,
1200 unsigned uid,MCContext &Ctx) const{
1201 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1202 Subtarget->isPICStyleGOT());
1203 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1205 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1206 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1209 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1211 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1212 SelectionDAG &DAG) const {
1213 if (!Subtarget->is64Bit())
1214 // This doesn't have DebugLoc associated with it, but is not really the
1215 // same as a Register.
1216 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1220 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1221 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1223 const MCExpr *X86TargetLowering::
1224 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1225 MCContext &Ctx) const {
1226 // X86-64 uses RIP relative addressing based on the jump table label.
1227 if (Subtarget->isPICStyleRIPRel())
1228 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1230 // Otherwise, the reference is relative to the PIC base.
1231 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1234 // FIXME: Why this routine is here? Move to RegInfo!
1235 std::pair<const TargetRegisterClass*, uint8_t>
1236 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1237 const TargetRegisterClass *RRC = 0;
1239 switch (VT.getSimpleVT().SimpleTy) {
1241 return TargetLowering::findRepresentativeClass(VT);
1242 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1243 RRC = (Subtarget->is64Bit()
1244 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1247 RRC = X86::VR64RegisterClass;
1249 case MVT::f32: case MVT::f64:
1250 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1251 case MVT::v4f32: case MVT::v2f64:
1252 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1254 RRC = X86::VR128RegisterClass;
1257 return std::make_pair(RRC, Cost);
1260 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1261 unsigned &Offset) const {
1262 if (!Subtarget->isTargetLinux())
1265 if (Subtarget->is64Bit()) {
1266 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1268 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1281 //===----------------------------------------------------------------------===//
1282 // Return Value Calling Convention Implementation
1283 //===----------------------------------------------------------------------===//
1285 #include "X86GenCallingConv.inc"
1288 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1289 MachineFunction &MF, bool isVarArg,
1290 const SmallVectorImpl<ISD::OutputArg> &Outs,
1291 LLVMContext &Context) const {
1292 SmallVector<CCValAssign, 16> RVLocs;
1293 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1295 return CCInfo.CheckReturn(Outs, RetCC_X86);
1299 X86TargetLowering::LowerReturn(SDValue Chain,
1300 CallingConv::ID CallConv, bool isVarArg,
1301 const SmallVectorImpl<ISD::OutputArg> &Outs,
1302 const SmallVectorImpl<SDValue> &OutVals,
1303 DebugLoc dl, SelectionDAG &DAG) const {
1304 MachineFunction &MF = DAG.getMachineFunction();
1305 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1307 SmallVector<CCValAssign, 16> RVLocs;
1308 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1309 RVLocs, *DAG.getContext());
1310 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1312 // Add the regs to the liveout set for the function.
1313 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1314 for (unsigned i = 0; i != RVLocs.size(); ++i)
1315 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1316 MRI.addLiveOut(RVLocs[i].getLocReg());
1320 SmallVector<SDValue, 6> RetOps;
1321 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1322 // Operand #1 = Bytes To Pop
1323 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1326 // Copy the result values into the output registers.
1327 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1328 CCValAssign &VA = RVLocs[i];
1329 assert(VA.isRegLoc() && "Can only return in registers!");
1330 SDValue ValToCopy = OutVals[i];
1331 EVT ValVT = ValToCopy.getValueType();
1333 // If this is x86-64, and we disabled SSE, we can't return FP values,
1334 // or SSE or MMX vectors.
1335 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1336 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1337 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1338 report_fatal_error("SSE register return with SSE disabled");
1340 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1341 // llvm-gcc has never done it right and no one has noticed, so this
1342 // should be OK for now.
1343 if (ValVT == MVT::f64 &&
1344 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1345 report_fatal_error("SSE2 register return with SSE2 disabled");
1347 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1348 // the RET instruction and handled by the FP Stackifier.
1349 if (VA.getLocReg() == X86::ST0 ||
1350 VA.getLocReg() == X86::ST1) {
1351 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1352 // change the value to the FP stack register class.
1353 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1354 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1355 RetOps.push_back(ValToCopy);
1356 // Don't emit a copytoreg.
1360 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1361 // which is returned in RAX / RDX.
1362 if (Subtarget->is64Bit()) {
1363 if (ValVT == MVT::x86mmx) {
1364 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1365 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1366 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1368 // If we don't have SSE2 available, convert to v4f32 so the generated
1369 // register is legal.
1370 if (!Subtarget->hasSSE2())
1371 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1376 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1377 Flag = Chain.getValue(1);
1380 // The x86-64 ABI for returning structs by value requires that we copy
1381 // the sret argument into %rax for the return. We saved the argument into
1382 // a virtual register in the entry block, so now we copy the value out
1384 if (Subtarget->is64Bit() &&
1385 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1386 MachineFunction &MF = DAG.getMachineFunction();
1387 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1388 unsigned Reg = FuncInfo->getSRetReturnReg();
1390 "SRetReturnReg should have been set in LowerFormalArguments().");
1391 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1393 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1394 Flag = Chain.getValue(1);
1396 // RAX now acts like a return value.
1397 MRI.addLiveOut(X86::RAX);
1400 RetOps[0] = Chain; // Update chain.
1402 // Add the flag if we have it.
1404 RetOps.push_back(Flag);
1406 return DAG.getNode(X86ISD::RET_FLAG, dl,
1407 MVT::Other, &RetOps[0], RetOps.size());
1410 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1411 if (N->getNumValues() != 1)
1413 if (!N->hasNUsesOfValue(1, 0))
1416 SDNode *Copy = *N->use_begin();
1417 if (Copy->getOpcode() != ISD::CopyToReg &&
1418 Copy->getOpcode() != ISD::FP_EXTEND)
1421 bool HasRet = false;
1422 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1424 if (UI->getOpcode() != X86ISD::RET_FLAG)
1433 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1434 ISD::NodeType ExtendKind) const {
1436 // TODO: Is this also valid on 32-bit?
1437 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1438 ReturnMVT = MVT::i8;
1440 ReturnMVT = MVT::i32;
1442 EVT MinVT = getRegisterType(Context, ReturnMVT);
1443 return VT.bitsLT(MinVT) ? MinVT : VT;
1446 /// LowerCallResult - Lower the result values of a call into the
1447 /// appropriate copies out of appropriate physical registers.
1450 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1451 CallingConv::ID CallConv, bool isVarArg,
1452 const SmallVectorImpl<ISD::InputArg> &Ins,
1453 DebugLoc dl, SelectionDAG &DAG,
1454 SmallVectorImpl<SDValue> &InVals) const {
1456 // Assign locations to each value returned by this call.
1457 SmallVector<CCValAssign, 16> RVLocs;
1458 bool Is64Bit = Subtarget->is64Bit();
1459 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1460 getTargetMachine(), RVLocs, *DAG.getContext());
1461 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1463 // Copy all of the result registers out of their specified physreg.
1464 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1465 CCValAssign &VA = RVLocs[i];
1466 EVT CopyVT = VA.getValVT();
1468 // If this is x86-64, and we disabled SSE, we can't return FP values
1469 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1470 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1471 report_fatal_error("SSE register return with SSE disabled");
1476 // If this is a call to a function that returns an fp value on the floating
1477 // point stack, we must guarantee the the value is popped from the stack, so
1478 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1479 // if the return value is not used. We use the FpPOP_RETVAL instruction
1481 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1482 // If we prefer to use the value in xmm registers, copy it out as f80 and
1483 // use a truncate to move it from fp stack reg to xmm reg.
1484 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1485 SDValue Ops[] = { Chain, InFlag };
1486 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1487 MVT::Other, MVT::Glue, Ops, 2), 1);
1488 Val = Chain.getValue(0);
1490 // Round the f80 to the right size, which also moves it to the appropriate
1492 if (CopyVT != VA.getValVT())
1493 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1494 // This truncation won't change the value.
1495 DAG.getIntPtrConstant(1));
1497 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1498 CopyVT, InFlag).getValue(1);
1499 Val = Chain.getValue(0);
1501 InFlag = Chain.getValue(2);
1502 InVals.push_back(Val);
1509 //===----------------------------------------------------------------------===//
1510 // C & StdCall & Fast Calling Convention implementation
1511 //===----------------------------------------------------------------------===//
1512 // StdCall calling convention seems to be standard for many Windows' API
1513 // routines and around. It differs from C calling convention just a little:
1514 // callee should clean up the stack, not caller. Symbols should be also
1515 // decorated in some fancy way :) It doesn't support any vector arguments.
1516 // For info on fast calling convention see Fast Calling Convention (tail call)
1517 // implementation LowerX86_32FastCCCallTo.
1519 /// CallIsStructReturn - Determines whether a call uses struct return
1521 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1525 return Outs[0].Flags.isSRet();
1528 /// ArgsAreStructReturn - Determines whether a function uses struct
1529 /// return semantics.
1531 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1535 return Ins[0].Flags.isSRet();
1538 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1539 /// by "Src" to address "Dst" with size and alignment information specified by
1540 /// the specific parameter attribute. The copy will be passed as a byval
1541 /// function parameter.
1543 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1544 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1546 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1548 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1549 /*isVolatile*/false, /*AlwaysInline=*/true,
1550 MachinePointerInfo(), MachinePointerInfo());
1553 /// IsTailCallConvention - Return true if the calling convention is one that
1554 /// supports tail call optimization.
1555 static bool IsTailCallConvention(CallingConv::ID CC) {
1556 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1559 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1560 if (!CI->isTailCall())
1564 CallingConv::ID CalleeCC = CS.getCallingConv();
1565 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1571 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1572 /// a tailcall target by changing its ABI.
1573 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1574 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1578 X86TargetLowering::LowerMemArgument(SDValue Chain,
1579 CallingConv::ID CallConv,
1580 const SmallVectorImpl<ISD::InputArg> &Ins,
1581 DebugLoc dl, SelectionDAG &DAG,
1582 const CCValAssign &VA,
1583 MachineFrameInfo *MFI,
1585 // Create the nodes corresponding to a load from this parameter slot.
1586 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1587 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1588 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1591 // If value is passed by pointer we have address passed instead of the value
1593 if (VA.getLocInfo() == CCValAssign::Indirect)
1594 ValVT = VA.getLocVT();
1596 ValVT = VA.getValVT();
1598 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1599 // changed with more analysis.
1600 // In case of tail call optimization mark all arguments mutable. Since they
1601 // could be overwritten by lowering of arguments in case of a tail call.
1602 if (Flags.isByVal()) {
1603 unsigned Bytes = Flags.getByValSize();
1604 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1605 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1606 return DAG.getFrameIndex(FI, getPointerTy());
1608 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1609 VA.getLocMemOffset(), isImmutable);
1610 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1611 return DAG.getLoad(ValVT, dl, Chain, FIN,
1612 MachinePointerInfo::getFixedStack(FI),
1618 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1619 CallingConv::ID CallConv,
1621 const SmallVectorImpl<ISD::InputArg> &Ins,
1624 SmallVectorImpl<SDValue> &InVals)
1626 MachineFunction &MF = DAG.getMachineFunction();
1627 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1629 const Function* Fn = MF.getFunction();
1630 if (Fn->hasExternalLinkage() &&
1631 Subtarget->isTargetCygMing() &&
1632 Fn->getName() == "main")
1633 FuncInfo->setForceFramePointer(true);
1635 MachineFrameInfo *MFI = MF.getFrameInfo();
1636 bool Is64Bit = Subtarget->is64Bit();
1637 bool IsWin64 = Subtarget->isTargetWin64();
1639 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1640 "Var args not supported with calling convention fastcc or ghc");
1642 // Assign locations to all of the incoming arguments.
1643 SmallVector<CCValAssign, 16> ArgLocs;
1644 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1645 ArgLocs, *DAG.getContext());
1647 // Allocate shadow area for Win64
1649 CCInfo.AllocateStack(32, 8);
1652 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1654 unsigned LastVal = ~0U;
1656 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1657 CCValAssign &VA = ArgLocs[i];
1658 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1660 assert(VA.getValNo() != LastVal &&
1661 "Don't support value assigned to multiple locs yet");
1662 LastVal = VA.getValNo();
1664 if (VA.isRegLoc()) {
1665 EVT RegVT = VA.getLocVT();
1666 TargetRegisterClass *RC = NULL;
1667 if (RegVT == MVT::i32)
1668 RC = X86::GR32RegisterClass;
1669 else if (Is64Bit && RegVT == MVT::i64)
1670 RC = X86::GR64RegisterClass;
1671 else if (RegVT == MVT::f32)
1672 RC = X86::FR32RegisterClass;
1673 else if (RegVT == MVT::f64)
1674 RC = X86::FR64RegisterClass;
1675 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1676 RC = X86::VR256RegisterClass;
1677 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1678 RC = X86::VR128RegisterClass;
1679 else if (RegVT == MVT::x86mmx)
1680 RC = X86::VR64RegisterClass;
1682 llvm_unreachable("Unknown argument type!");
1684 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1685 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1687 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1688 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1690 if (VA.getLocInfo() == CCValAssign::SExt)
1691 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1692 DAG.getValueType(VA.getValVT()));
1693 else if (VA.getLocInfo() == CCValAssign::ZExt)
1694 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1695 DAG.getValueType(VA.getValVT()));
1696 else if (VA.getLocInfo() == CCValAssign::BCvt)
1697 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1699 if (VA.isExtInLoc()) {
1700 // Handle MMX values passed in XMM regs.
1701 if (RegVT.isVector()) {
1702 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1705 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1708 assert(VA.isMemLoc());
1709 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1712 // If value is passed via pointer - do a load.
1713 if (VA.getLocInfo() == CCValAssign::Indirect)
1714 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1715 MachinePointerInfo(), false, false, 0);
1717 InVals.push_back(ArgValue);
1720 // The x86-64 ABI for returning structs by value requires that we copy
1721 // the sret argument into %rax for the return. Save the argument into
1722 // a virtual register so that we can access it from the return points.
1723 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1724 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1725 unsigned Reg = FuncInfo->getSRetReturnReg();
1727 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1728 FuncInfo->setSRetReturnReg(Reg);
1730 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1731 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1734 unsigned StackSize = CCInfo.getNextStackOffset();
1735 // Align stack specially for tail calls.
1736 if (FuncIsMadeTailCallSafe(CallConv))
1737 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1739 // If the function takes variable number of arguments, make a frame index for
1740 // the start of the first vararg value... for expansion of llvm.va_start.
1742 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1743 CallConv != CallingConv::X86_ThisCall)) {
1744 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1747 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1749 // FIXME: We should really autogenerate these arrays
1750 static const unsigned GPR64ArgRegsWin64[] = {
1751 X86::RCX, X86::RDX, X86::R8, X86::R9
1753 static const unsigned GPR64ArgRegs64Bit[] = {
1754 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1756 static const unsigned XMMArgRegs64Bit[] = {
1757 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1758 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1760 const unsigned *GPR64ArgRegs;
1761 unsigned NumXMMRegs = 0;
1764 // The XMM registers which might contain var arg parameters are shadowed
1765 // in their paired GPR. So we only need to save the GPR to their home
1767 TotalNumIntRegs = 4;
1768 GPR64ArgRegs = GPR64ArgRegsWin64;
1770 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1771 GPR64ArgRegs = GPR64ArgRegs64Bit;
1773 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1775 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1778 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1779 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1780 "SSE register cannot be used when SSE is disabled!");
1781 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1782 "SSE register cannot be used when SSE is disabled!");
1783 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1784 // Kernel mode asks for SSE to be disabled, so don't push them
1786 TotalNumXMMRegs = 0;
1789 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1790 // Get to the caller-allocated home save location. Add 8 to account
1791 // for the return address.
1792 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1793 FuncInfo->setRegSaveFrameIndex(
1794 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1795 // Fixup to set vararg frame on shadow area (4 x i64).
1797 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1799 // For X86-64, if there are vararg parameters that are passed via
1800 // registers, then we must store them to their spots on the stack so they
1801 // may be loaded by deferencing the result of va_next.
1802 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1803 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1804 FuncInfo->setRegSaveFrameIndex(
1805 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1809 // Store the integer parameter registers.
1810 SmallVector<SDValue, 8> MemOps;
1811 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1813 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1814 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1815 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1816 DAG.getIntPtrConstant(Offset));
1817 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1818 X86::GR64RegisterClass);
1819 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1821 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1822 MachinePointerInfo::getFixedStack(
1823 FuncInfo->getRegSaveFrameIndex(), Offset),
1825 MemOps.push_back(Store);
1829 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1830 // Now store the XMM (fp + vector) parameter registers.
1831 SmallVector<SDValue, 11> SaveXMMOps;
1832 SaveXMMOps.push_back(Chain);
1834 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1835 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1836 SaveXMMOps.push_back(ALVal);
1838 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1839 FuncInfo->getRegSaveFrameIndex()));
1840 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1841 FuncInfo->getVarArgsFPOffset()));
1843 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1844 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1845 X86::VR128RegisterClass);
1846 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1847 SaveXMMOps.push_back(Val);
1849 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1851 &SaveXMMOps[0], SaveXMMOps.size()));
1854 if (!MemOps.empty())
1855 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1856 &MemOps[0], MemOps.size());
1860 // Some CCs need callee pop.
1861 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
1862 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1864 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1865 // If this is an sret function, the return should pop the hidden pointer.
1866 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1867 FuncInfo->setBytesToPopOnReturn(4);
1871 // RegSaveFrameIndex is X86-64 only.
1872 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1873 if (CallConv == CallingConv::X86_FastCall ||
1874 CallConv == CallingConv::X86_ThisCall)
1875 // fastcc functions can't have varargs.
1876 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1883 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1884 SDValue StackPtr, SDValue Arg,
1885 DebugLoc dl, SelectionDAG &DAG,
1886 const CCValAssign &VA,
1887 ISD::ArgFlagsTy Flags) const {
1888 unsigned LocMemOffset = VA.getLocMemOffset();
1889 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1890 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1891 if (Flags.isByVal())
1892 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1894 return DAG.getStore(Chain, dl, Arg, PtrOff,
1895 MachinePointerInfo::getStack(LocMemOffset),
1899 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1900 /// optimization is performed and it is required.
1902 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1903 SDValue &OutRetAddr, SDValue Chain,
1904 bool IsTailCall, bool Is64Bit,
1905 int FPDiff, DebugLoc dl) const {
1906 // Adjust the Return address stack slot.
1907 EVT VT = getPointerTy();
1908 OutRetAddr = getReturnAddressFrameIndex(DAG);
1910 // Load the "old" Return address.
1911 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1913 return SDValue(OutRetAddr.getNode(), 1);
1916 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
1917 /// optimization is performed and it is required (FPDiff!=0).
1919 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1920 SDValue Chain, SDValue RetAddrFrIdx,
1921 bool Is64Bit, int FPDiff, DebugLoc dl) {
1922 // Store the return address to the appropriate stack slot.
1923 if (!FPDiff) return Chain;
1924 // Calculate the new stack slot for the return address.
1925 int SlotSize = Is64Bit ? 8 : 4;
1926 int NewReturnAddrFI =
1927 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1928 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1929 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1930 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1931 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1937 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1938 CallingConv::ID CallConv, bool isVarArg,
1940 const SmallVectorImpl<ISD::OutputArg> &Outs,
1941 const SmallVectorImpl<SDValue> &OutVals,
1942 const SmallVectorImpl<ISD::InputArg> &Ins,
1943 DebugLoc dl, SelectionDAG &DAG,
1944 SmallVectorImpl<SDValue> &InVals) const {
1945 MachineFunction &MF = DAG.getMachineFunction();
1946 bool Is64Bit = Subtarget->is64Bit();
1947 bool IsWin64 = Subtarget->isTargetWin64();
1948 bool IsStructRet = CallIsStructReturn(Outs);
1949 bool IsSibcall = false;
1952 // Check if it's really possible to do a tail call.
1953 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1954 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1955 Outs, OutVals, Ins, DAG);
1957 // Sibcalls are automatically detected tailcalls which do not require
1959 if (!GuaranteedTailCallOpt && isTailCall)
1966 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1967 "Var args not supported with calling convention fastcc or ghc");
1969 // Analyze operands of the call, assigning locations to each operand.
1970 SmallVector<CCValAssign, 16> ArgLocs;
1971 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1972 ArgLocs, *DAG.getContext());
1974 // Allocate shadow area for Win64
1976 CCInfo.AllocateStack(32, 8);
1979 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
1981 // Get a count of how many bytes are to be pushed on the stack.
1982 unsigned NumBytes = CCInfo.getNextStackOffset();
1984 // This is a sibcall. The memory operands are available in caller's
1985 // own caller's stack.
1987 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1988 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1991 if (isTailCall && !IsSibcall) {
1992 // Lower arguments at fp - stackoffset + fpdiff.
1993 unsigned NumBytesCallerPushed =
1994 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1995 FPDiff = NumBytesCallerPushed - NumBytes;
1997 // Set the delta of movement of the returnaddr stackslot.
1998 // But only set if delta is greater than previous delta.
1999 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2000 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2004 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2006 SDValue RetAddrFrIdx;
2007 // Load return address for tail calls.
2008 if (isTailCall && FPDiff)
2009 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2010 Is64Bit, FPDiff, dl);
2012 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2013 SmallVector<SDValue, 8> MemOpChains;
2016 // Walk the register/memloc assignments, inserting copies/loads. In the case
2017 // of tail call optimization arguments are handle later.
2018 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2019 CCValAssign &VA = ArgLocs[i];
2020 EVT RegVT = VA.getLocVT();
2021 SDValue Arg = OutVals[i];
2022 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2023 bool isByVal = Flags.isByVal();
2025 // Promote the value if needed.
2026 switch (VA.getLocInfo()) {
2027 default: llvm_unreachable("Unknown loc info!");
2028 case CCValAssign::Full: break;
2029 case CCValAssign::SExt:
2030 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2032 case CCValAssign::ZExt:
2033 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2035 case CCValAssign::AExt:
2036 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2037 // Special case: passing MMX values in XMM registers.
2038 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2039 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2040 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2042 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2044 case CCValAssign::BCvt:
2045 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2047 case CCValAssign::Indirect: {
2048 // Store the argument.
2049 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2050 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2051 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2052 MachinePointerInfo::getFixedStack(FI),
2059 if (VA.isRegLoc()) {
2060 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2061 if (isVarArg && IsWin64) {
2062 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2063 // shadow reg if callee is a varargs function.
2064 unsigned ShadowReg = 0;
2065 switch (VA.getLocReg()) {
2066 case X86::XMM0: ShadowReg = X86::RCX; break;
2067 case X86::XMM1: ShadowReg = X86::RDX; break;
2068 case X86::XMM2: ShadowReg = X86::R8; break;
2069 case X86::XMM3: ShadowReg = X86::R9; break;
2072 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2074 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2075 assert(VA.isMemLoc());
2076 if (StackPtr.getNode() == 0)
2077 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2078 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2079 dl, DAG, VA, Flags));
2083 if (!MemOpChains.empty())
2084 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2085 &MemOpChains[0], MemOpChains.size());
2087 // Build a sequence of copy-to-reg nodes chained together with token chain
2088 // and flag operands which copy the outgoing args into registers.
2090 // Tail call byval lowering might overwrite argument registers so in case of
2091 // tail call optimization the copies to registers are lowered later.
2093 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2094 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2095 RegsToPass[i].second, InFlag);
2096 InFlag = Chain.getValue(1);
2099 if (Subtarget->isPICStyleGOT()) {
2100 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2103 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2104 DAG.getNode(X86ISD::GlobalBaseReg,
2105 DebugLoc(), getPointerTy()),
2107 InFlag = Chain.getValue(1);
2109 // If we are tail calling and generating PIC/GOT style code load the
2110 // address of the callee into ECX. The value in ecx is used as target of
2111 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2112 // for tail calls on PIC/GOT architectures. Normally we would just put the
2113 // address of GOT into ebx and then call target@PLT. But for tail calls
2114 // ebx would be restored (since ebx is callee saved) before jumping to the
2117 // Note: The actual moving to ECX is done further down.
2118 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2119 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2120 !G->getGlobal()->hasProtectedVisibility())
2121 Callee = LowerGlobalAddress(Callee, DAG);
2122 else if (isa<ExternalSymbolSDNode>(Callee))
2123 Callee = LowerExternalSymbol(Callee, DAG);
2127 if (Is64Bit && isVarArg && !IsWin64) {
2128 // From AMD64 ABI document:
2129 // For calls that may call functions that use varargs or stdargs
2130 // (prototype-less calls or calls to functions containing ellipsis (...) in
2131 // the declaration) %al is used as hidden argument to specify the number
2132 // of SSE registers used. The contents of %al do not need to match exactly
2133 // the number of registers, but must be an ubound on the number of SSE
2134 // registers used and is in the range 0 - 8 inclusive.
2136 // Count the number of XMM registers allocated.
2137 static const unsigned XMMArgRegs[] = {
2138 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2139 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2141 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2142 assert((Subtarget->hasXMM() || !NumXMMRegs)
2143 && "SSE registers cannot be used when SSE is disabled");
2145 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2146 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2147 InFlag = Chain.getValue(1);
2151 // For tail calls lower the arguments to the 'real' stack slot.
2153 // Force all the incoming stack arguments to be loaded from the stack
2154 // before any new outgoing arguments are stored to the stack, because the
2155 // outgoing stack slots may alias the incoming argument stack slots, and
2156 // the alias isn't otherwise explicit. This is slightly more conservative
2157 // than necessary, because it means that each store effectively depends
2158 // on every argument instead of just those arguments it would clobber.
2159 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2161 SmallVector<SDValue, 8> MemOpChains2;
2164 // Do not flag preceding copytoreg stuff together with the following stuff.
2166 if (GuaranteedTailCallOpt) {
2167 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2168 CCValAssign &VA = ArgLocs[i];
2171 assert(VA.isMemLoc());
2172 SDValue Arg = OutVals[i];
2173 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2174 // Create frame index.
2175 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2176 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2177 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2178 FIN = DAG.getFrameIndex(FI, getPointerTy());
2180 if (Flags.isByVal()) {
2181 // Copy relative to framepointer.
2182 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2183 if (StackPtr.getNode() == 0)
2184 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2186 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2188 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2192 // Store relative to framepointer.
2193 MemOpChains2.push_back(
2194 DAG.getStore(ArgChain, dl, Arg, FIN,
2195 MachinePointerInfo::getFixedStack(FI),
2201 if (!MemOpChains2.empty())
2202 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2203 &MemOpChains2[0], MemOpChains2.size());
2205 // Copy arguments to their registers.
2206 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2207 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2208 RegsToPass[i].second, InFlag);
2209 InFlag = Chain.getValue(1);
2213 // Store the return address to the appropriate stack slot.
2214 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2218 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2219 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2220 // In the 64-bit large code model, we have to make all calls
2221 // through a register, since the call instruction's 32-bit
2222 // pc-relative offset may not be large enough to hold the whole
2224 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2225 // If the callee is a GlobalAddress node (quite common, every direct call
2226 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2229 // We should use extra load for direct calls to dllimported functions in
2231 const GlobalValue *GV = G->getGlobal();
2232 if (!GV->hasDLLImportLinkage()) {
2233 unsigned char OpFlags = 0;
2234 bool ExtraLoad = false;
2235 unsigned WrapperKind = ISD::DELETED_NODE;
2237 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2238 // external symbols most go through the PLT in PIC mode. If the symbol
2239 // has hidden or protected visibility, or if it is static or local, then
2240 // we don't need to use the PLT - we can directly call it.
2241 if (Subtarget->isTargetELF() &&
2242 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2243 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2244 OpFlags = X86II::MO_PLT;
2245 } else if (Subtarget->isPICStyleStubAny() &&
2246 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2247 (!Subtarget->getTargetTriple().isMacOSX() ||
2248 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2249 // PC-relative references to external symbols should go through $stub,
2250 // unless we're building with the leopard linker or later, which
2251 // automatically synthesizes these stubs.
2252 OpFlags = X86II::MO_DARWIN_STUB;
2253 } else if (Subtarget->isPICStyleRIPRel() &&
2254 isa<Function>(GV) &&
2255 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2256 // If the function is marked as non-lazy, generate an indirect call
2257 // which loads from the GOT directly. This avoids runtime overhead
2258 // at the cost of eager binding (and one extra byte of encoding).
2259 OpFlags = X86II::MO_GOTPCREL;
2260 WrapperKind = X86ISD::WrapperRIP;
2264 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2265 G->getOffset(), OpFlags);
2267 // Add a wrapper if needed.
2268 if (WrapperKind != ISD::DELETED_NODE)
2269 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2270 // Add extra indirection if needed.
2272 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2273 MachinePointerInfo::getGOT(),
2276 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2277 unsigned char OpFlags = 0;
2279 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2280 // external symbols should go through the PLT.
2281 if (Subtarget->isTargetELF() &&
2282 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2283 OpFlags = X86II::MO_PLT;
2284 } else if (Subtarget->isPICStyleStubAny() &&
2285 (!Subtarget->getTargetTriple().isMacOSX() ||
2286 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2287 // PC-relative references to external symbols should go through $stub,
2288 // unless we're building with the leopard linker or later, which
2289 // automatically synthesizes these stubs.
2290 OpFlags = X86II::MO_DARWIN_STUB;
2293 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2297 // Returns a chain & a flag for retval copy to use.
2298 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2299 SmallVector<SDValue, 8> Ops;
2301 if (!IsSibcall && isTailCall) {
2302 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2303 DAG.getIntPtrConstant(0, true), InFlag);
2304 InFlag = Chain.getValue(1);
2307 Ops.push_back(Chain);
2308 Ops.push_back(Callee);
2311 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2313 // Add argument registers to the end of the list so that they are known live
2315 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2316 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2317 RegsToPass[i].second.getValueType()));
2319 // Add an implicit use GOT pointer in EBX.
2320 if (!isTailCall && Subtarget->isPICStyleGOT())
2321 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2323 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2324 if (Is64Bit && isVarArg && !IsWin64)
2325 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2327 if (InFlag.getNode())
2328 Ops.push_back(InFlag);
2332 //// If this is the first return lowered for this function, add the regs
2333 //// to the liveout set for the function.
2334 // This isn't right, although it's probably harmless on x86; liveouts
2335 // should be computed from returns not tail calls. Consider a void
2336 // function making a tail call to a function returning int.
2337 return DAG.getNode(X86ISD::TC_RETURN, dl,
2338 NodeTys, &Ops[0], Ops.size());
2341 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2342 InFlag = Chain.getValue(1);
2344 // Create the CALLSEQ_END node.
2345 unsigned NumBytesForCalleeToPush;
2346 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
2347 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2348 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2349 // If this is a call to a struct-return function, the callee
2350 // pops the hidden struct pointer, so we have to push it back.
2351 // This is common for Darwin/X86, Linux & Mingw32 targets.
2352 NumBytesForCalleeToPush = 4;
2354 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2356 // Returns a flag for retval copy to use.
2358 Chain = DAG.getCALLSEQ_END(Chain,
2359 DAG.getIntPtrConstant(NumBytes, true),
2360 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2363 InFlag = Chain.getValue(1);
2366 // Handle result values, copying them out of physregs into vregs that we
2368 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2369 Ins, dl, DAG, InVals);
2373 //===----------------------------------------------------------------------===//
2374 // Fast Calling Convention (tail call) implementation
2375 //===----------------------------------------------------------------------===//
2377 // Like std call, callee cleans arguments, convention except that ECX is
2378 // reserved for storing the tail called function address. Only 2 registers are
2379 // free for argument passing (inreg). Tail call optimization is performed
2381 // * tailcallopt is enabled
2382 // * caller/callee are fastcc
2383 // On X86_64 architecture with GOT-style position independent code only local
2384 // (within module) calls are supported at the moment.
2385 // To keep the stack aligned according to platform abi the function
2386 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2387 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2388 // If a tail called function callee has more arguments than the caller the
2389 // caller needs to make sure that there is room to move the RETADDR to. This is
2390 // achieved by reserving an area the size of the argument delta right after the
2391 // original REtADDR, but before the saved framepointer or the spilled registers
2392 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2404 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2405 /// for a 16 byte align requirement.
2407 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2408 SelectionDAG& DAG) const {
2409 MachineFunction &MF = DAG.getMachineFunction();
2410 const TargetMachine &TM = MF.getTarget();
2411 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2412 unsigned StackAlignment = TFI.getStackAlignment();
2413 uint64_t AlignMask = StackAlignment - 1;
2414 int64_t Offset = StackSize;
2415 uint64_t SlotSize = TD->getPointerSize();
2416 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2417 // Number smaller than 12 so just add the difference.
2418 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2420 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2421 Offset = ((~AlignMask) & Offset) + StackAlignment +
2422 (StackAlignment-SlotSize);
2427 /// MatchingStackOffset - Return true if the given stack call argument is
2428 /// already available in the same position (relatively) of the caller's
2429 /// incoming argument stack.
2431 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2432 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2433 const X86InstrInfo *TII) {
2434 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2436 if (Arg.getOpcode() == ISD::CopyFromReg) {
2437 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2438 if (!TargetRegisterInfo::isVirtualRegister(VR))
2440 MachineInstr *Def = MRI->getVRegDef(VR);
2443 if (!Flags.isByVal()) {
2444 if (!TII->isLoadFromStackSlot(Def, FI))
2447 unsigned Opcode = Def->getOpcode();
2448 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2449 Def->getOperand(1).isFI()) {
2450 FI = Def->getOperand(1).getIndex();
2451 Bytes = Flags.getByValSize();
2455 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2456 if (Flags.isByVal())
2457 // ByVal argument is passed in as a pointer but it's now being
2458 // dereferenced. e.g.
2459 // define @foo(%struct.X* %A) {
2460 // tail call @bar(%struct.X* byval %A)
2463 SDValue Ptr = Ld->getBasePtr();
2464 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2467 FI = FINode->getIndex();
2468 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2469 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2470 FI = FINode->getIndex();
2471 Bytes = Flags.getByValSize();
2475 assert(FI != INT_MAX);
2476 if (!MFI->isFixedObjectIndex(FI))
2478 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2481 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2482 /// for tail call optimization. Targets which want to do tail call
2483 /// optimization should implement this function.
2485 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2486 CallingConv::ID CalleeCC,
2488 bool isCalleeStructRet,
2489 bool isCallerStructRet,
2490 const SmallVectorImpl<ISD::OutputArg> &Outs,
2491 const SmallVectorImpl<SDValue> &OutVals,
2492 const SmallVectorImpl<ISD::InputArg> &Ins,
2493 SelectionDAG& DAG) const {
2494 if (!IsTailCallConvention(CalleeCC) &&
2495 CalleeCC != CallingConv::C)
2498 // If -tailcallopt is specified, make fastcc functions tail-callable.
2499 const MachineFunction &MF = DAG.getMachineFunction();
2500 const Function *CallerF = DAG.getMachineFunction().getFunction();
2501 CallingConv::ID CallerCC = CallerF->getCallingConv();
2502 bool CCMatch = CallerCC == CalleeCC;
2504 if (GuaranteedTailCallOpt) {
2505 if (IsTailCallConvention(CalleeCC) && CCMatch)
2510 // Look for obvious safe cases to perform tail call optimization that do not
2511 // require ABI changes. This is what gcc calls sibcall.
2513 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2514 // emit a special epilogue.
2515 if (RegInfo->needsStackRealignment(MF))
2518 // Also avoid sibcall optimization if either caller or callee uses struct
2519 // return semantics.
2520 if (isCalleeStructRet || isCallerStructRet)
2523 // An stdcall caller is expected to clean up its arguments; the callee
2524 // isn't going to do that.
2525 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2528 // Do not sibcall optimize vararg calls unless all arguments are passed via
2530 if (isVarArg && !Outs.empty()) {
2532 // Optimizing for varargs on Win64 is unlikely to be safe without
2533 // additional testing.
2534 if (Subtarget->isTargetWin64())
2537 SmallVector<CCValAssign, 16> ArgLocs;
2538 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2539 getTargetMachine(), ArgLocs, *DAG.getContext());
2541 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2542 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2543 if (!ArgLocs[i].isRegLoc())
2547 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2548 // Therefore if it's not used by the call it is not safe to optimize this into
2550 bool Unused = false;
2551 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2558 SmallVector<CCValAssign, 16> RVLocs;
2559 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2560 getTargetMachine(), RVLocs, *DAG.getContext());
2561 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2562 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2563 CCValAssign &VA = RVLocs[i];
2564 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2569 // If the calling conventions do not match, then we'd better make sure the
2570 // results are returned in the same way as what the caller expects.
2572 SmallVector<CCValAssign, 16> RVLocs1;
2573 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2574 getTargetMachine(), RVLocs1, *DAG.getContext());
2575 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2577 SmallVector<CCValAssign, 16> RVLocs2;
2578 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2579 getTargetMachine(), RVLocs2, *DAG.getContext());
2580 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2582 if (RVLocs1.size() != RVLocs2.size())
2584 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2585 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2587 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2589 if (RVLocs1[i].isRegLoc()) {
2590 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2593 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2599 // If the callee takes no arguments then go on to check the results of the
2601 if (!Outs.empty()) {
2602 // Check if stack adjustment is needed. For now, do not do this if any
2603 // argument is passed on the stack.
2604 SmallVector<CCValAssign, 16> ArgLocs;
2605 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2606 getTargetMachine(), ArgLocs, *DAG.getContext());
2608 // Allocate shadow area for Win64
2609 if (Subtarget->isTargetWin64()) {
2610 CCInfo.AllocateStack(32, 8);
2613 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2614 if (CCInfo.getNextStackOffset()) {
2615 MachineFunction &MF = DAG.getMachineFunction();
2616 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2619 // Check if the arguments are already laid out in the right way as
2620 // the caller's fixed stack objects.
2621 MachineFrameInfo *MFI = MF.getFrameInfo();
2622 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2623 const X86InstrInfo *TII =
2624 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2625 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2626 CCValAssign &VA = ArgLocs[i];
2627 SDValue Arg = OutVals[i];
2628 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2629 if (VA.getLocInfo() == CCValAssign::Indirect)
2631 if (!VA.isRegLoc()) {
2632 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2639 // If the tailcall address may be in a register, then make sure it's
2640 // possible to register allocate for it. In 32-bit, the call address can
2641 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2642 // callee-saved registers are restored. These happen to be the same
2643 // registers used to pass 'inreg' arguments so watch out for those.
2644 if (!Subtarget->is64Bit() &&
2645 !isa<GlobalAddressSDNode>(Callee) &&
2646 !isa<ExternalSymbolSDNode>(Callee)) {
2647 unsigned NumInRegs = 0;
2648 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2649 CCValAssign &VA = ArgLocs[i];
2652 unsigned Reg = VA.getLocReg();
2655 case X86::EAX: case X86::EDX: case X86::ECX:
2656 if (++NumInRegs == 3)
2668 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2669 return X86::createFastISel(funcInfo);
2673 //===----------------------------------------------------------------------===//
2674 // Other Lowering Hooks
2675 //===----------------------------------------------------------------------===//
2677 static bool MayFoldLoad(SDValue Op) {
2678 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2681 static bool MayFoldIntoStore(SDValue Op) {
2682 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2685 static bool isTargetShuffle(unsigned Opcode) {
2687 default: return false;
2688 case X86ISD::PSHUFD:
2689 case X86ISD::PSHUFHW:
2690 case X86ISD::PSHUFLW:
2691 case X86ISD::SHUFPD:
2692 case X86ISD::PALIGN:
2693 case X86ISD::SHUFPS:
2694 case X86ISD::MOVLHPS:
2695 case X86ISD::MOVLHPD:
2696 case X86ISD::MOVHLPS:
2697 case X86ISD::MOVLPS:
2698 case X86ISD::MOVLPD:
2699 case X86ISD::MOVSHDUP:
2700 case X86ISD::MOVSLDUP:
2701 case X86ISD::MOVDDUP:
2704 case X86ISD::UNPCKLPS:
2705 case X86ISD::UNPCKLPD:
2706 case X86ISD::VUNPCKLPSY:
2707 case X86ISD::VUNPCKLPDY:
2708 case X86ISD::PUNPCKLWD:
2709 case X86ISD::PUNPCKLBW:
2710 case X86ISD::PUNPCKLDQ:
2711 case X86ISD::PUNPCKLQDQ:
2712 case X86ISD::UNPCKHPS:
2713 case X86ISD::UNPCKHPD:
2714 case X86ISD::VUNPCKHPSY:
2715 case X86ISD::VUNPCKHPDY:
2716 case X86ISD::PUNPCKHWD:
2717 case X86ISD::PUNPCKHBW:
2718 case X86ISD::PUNPCKHDQ:
2719 case X86ISD::PUNPCKHQDQ:
2720 case X86ISD::VPERMILPS:
2721 case X86ISD::VPERMILPSY:
2722 case X86ISD::VPERMILPD:
2723 case X86ISD::VPERMILPDY:
2729 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2730 SDValue V1, SelectionDAG &DAG) {
2732 default: llvm_unreachable("Unknown x86 shuffle node");
2733 case X86ISD::MOVSHDUP:
2734 case X86ISD::MOVSLDUP:
2735 case X86ISD::MOVDDUP:
2736 return DAG.getNode(Opc, dl, VT, V1);
2742 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2743 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2745 default: llvm_unreachable("Unknown x86 shuffle node");
2746 case X86ISD::PSHUFD:
2747 case X86ISD::PSHUFHW:
2748 case X86ISD::PSHUFLW:
2749 case X86ISD::VPERMILPS:
2750 case X86ISD::VPERMILPSY:
2751 case X86ISD::VPERMILPD:
2752 case X86ISD::VPERMILPDY:
2753 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2759 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2760 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2762 default: llvm_unreachable("Unknown x86 shuffle node");
2763 case X86ISD::PALIGN:
2764 case X86ISD::SHUFPD:
2765 case X86ISD::SHUFPS:
2766 return DAG.getNode(Opc, dl, VT, V1, V2,
2767 DAG.getConstant(TargetMask, MVT::i8));
2772 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2773 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2775 default: llvm_unreachable("Unknown x86 shuffle node");
2776 case X86ISD::MOVLHPS:
2777 case X86ISD::MOVLHPD:
2778 case X86ISD::MOVHLPS:
2779 case X86ISD::MOVLPS:
2780 case X86ISD::MOVLPD:
2783 case X86ISD::UNPCKLPS:
2784 case X86ISD::UNPCKLPD:
2785 case X86ISD::VUNPCKLPSY:
2786 case X86ISD::VUNPCKLPDY:
2787 case X86ISD::PUNPCKLWD:
2788 case X86ISD::PUNPCKLBW:
2789 case X86ISD::PUNPCKLDQ:
2790 case X86ISD::PUNPCKLQDQ:
2791 case X86ISD::UNPCKHPS:
2792 case X86ISD::UNPCKHPD:
2793 case X86ISD::VUNPCKHPSY:
2794 case X86ISD::VUNPCKHPDY:
2795 case X86ISD::PUNPCKHWD:
2796 case X86ISD::PUNPCKHBW:
2797 case X86ISD::PUNPCKHDQ:
2798 case X86ISD::PUNPCKHQDQ:
2799 return DAG.getNode(Opc, dl, VT, V1, V2);
2804 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2805 MachineFunction &MF = DAG.getMachineFunction();
2806 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2807 int ReturnAddrIndex = FuncInfo->getRAIndex();
2809 if (ReturnAddrIndex == 0) {
2810 // Set up a frame object for the return address.
2811 uint64_t SlotSize = TD->getPointerSize();
2812 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2814 FuncInfo->setRAIndex(ReturnAddrIndex);
2817 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2821 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2822 bool hasSymbolicDisplacement) {
2823 // Offset should fit into 32 bit immediate field.
2824 if (!isInt<32>(Offset))
2827 // If we don't have a symbolic displacement - we don't have any extra
2829 if (!hasSymbolicDisplacement)
2832 // FIXME: Some tweaks might be needed for medium code model.
2833 if (M != CodeModel::Small && M != CodeModel::Kernel)
2836 // For small code model we assume that latest object is 16MB before end of 31
2837 // bits boundary. We may also accept pretty large negative constants knowing
2838 // that all objects are in the positive half of address space.
2839 if (M == CodeModel::Small && Offset < 16*1024*1024)
2842 // For kernel code model we know that all object resist in the negative half
2843 // of 32bits address space. We may not accept negative offsets, since they may
2844 // be just off and we may accept pretty large positive ones.
2845 if (M == CodeModel::Kernel && Offset > 0)
2851 /// isCalleePop - Determines whether the callee is required to pop its
2852 /// own arguments. Callee pop is necessary to support tail calls.
2853 bool X86::isCalleePop(CallingConv::ID CallingConv,
2854 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2858 switch (CallingConv) {
2861 case CallingConv::X86_StdCall:
2863 case CallingConv::X86_FastCall:
2865 case CallingConv::X86_ThisCall:
2867 case CallingConv::Fast:
2869 case CallingConv::GHC:
2874 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2875 /// specific condition code, returning the condition code and the LHS/RHS of the
2876 /// comparison to make.
2877 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2878 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2880 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2881 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2882 // X > -1 -> X == 0, jump !sign.
2883 RHS = DAG.getConstant(0, RHS.getValueType());
2884 return X86::COND_NS;
2885 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2886 // X < 0 -> X == 0, jump on sign.
2888 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2890 RHS = DAG.getConstant(0, RHS.getValueType());
2891 return X86::COND_LE;
2895 switch (SetCCOpcode) {
2896 default: llvm_unreachable("Invalid integer condition!");
2897 case ISD::SETEQ: return X86::COND_E;
2898 case ISD::SETGT: return X86::COND_G;
2899 case ISD::SETGE: return X86::COND_GE;
2900 case ISD::SETLT: return X86::COND_L;
2901 case ISD::SETLE: return X86::COND_LE;
2902 case ISD::SETNE: return X86::COND_NE;
2903 case ISD::SETULT: return X86::COND_B;
2904 case ISD::SETUGT: return X86::COND_A;
2905 case ISD::SETULE: return X86::COND_BE;
2906 case ISD::SETUGE: return X86::COND_AE;
2910 // First determine if it is required or is profitable to flip the operands.
2912 // If LHS is a foldable load, but RHS is not, flip the condition.
2913 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
2914 !ISD::isNON_EXTLoad(RHS.getNode())) {
2915 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2916 std::swap(LHS, RHS);
2919 switch (SetCCOpcode) {
2925 std::swap(LHS, RHS);
2929 // On a floating point condition, the flags are set as follows:
2931 // 0 | 0 | 0 | X > Y
2932 // 0 | 0 | 1 | X < Y
2933 // 1 | 0 | 0 | X == Y
2934 // 1 | 1 | 1 | unordered
2935 switch (SetCCOpcode) {
2936 default: llvm_unreachable("Condcode should be pre-legalized away");
2938 case ISD::SETEQ: return X86::COND_E;
2939 case ISD::SETOLT: // flipped
2941 case ISD::SETGT: return X86::COND_A;
2942 case ISD::SETOLE: // flipped
2944 case ISD::SETGE: return X86::COND_AE;
2945 case ISD::SETUGT: // flipped
2947 case ISD::SETLT: return X86::COND_B;
2948 case ISD::SETUGE: // flipped
2950 case ISD::SETLE: return X86::COND_BE;
2952 case ISD::SETNE: return X86::COND_NE;
2953 case ISD::SETUO: return X86::COND_P;
2954 case ISD::SETO: return X86::COND_NP;
2956 case ISD::SETUNE: return X86::COND_INVALID;
2960 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2961 /// code. Current x86 isa includes the following FP cmov instructions:
2962 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2963 static bool hasFPCMov(unsigned X86CC) {
2979 /// isFPImmLegal - Returns true if the target can instruction select the
2980 /// specified FP immediate natively. If false, the legalizer will
2981 /// materialize the FP immediate as a load from a constant pool.
2982 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2983 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2984 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2990 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2991 /// the specified range (L, H].
2992 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2993 return (Val < 0) || (Val >= Low && Val < Hi);
2996 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2997 /// specified value.
2998 static bool isUndefOrEqual(int Val, int CmpVal) {
2999 if (Val < 0 || Val == CmpVal)
3004 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3005 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3006 /// the second operand.
3007 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3008 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3009 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3010 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3011 return (Mask[0] < 2 && Mask[1] < 2);
3015 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3016 SmallVector<int, 8> M;
3018 return ::isPSHUFDMask(M, N->getValueType(0));
3021 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3022 /// is suitable for input to PSHUFHW.
3023 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3024 if (VT != MVT::v8i16)
3027 // Lower quadword copied in order or undef.
3028 for (int i = 0; i != 4; ++i)
3029 if (Mask[i] >= 0 && Mask[i] != i)
3032 // Upper quadword shuffled.
3033 for (int i = 4; i != 8; ++i)
3034 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3040 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3041 SmallVector<int, 8> M;
3043 return ::isPSHUFHWMask(M, N->getValueType(0));
3046 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3047 /// is suitable for input to PSHUFLW.
3048 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3049 if (VT != MVT::v8i16)
3052 // Upper quadword copied in order.
3053 for (int i = 4; i != 8; ++i)
3054 if (Mask[i] >= 0 && Mask[i] != i)
3057 // Lower quadword shuffled.
3058 for (int i = 0; i != 4; ++i)
3065 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3066 SmallVector<int, 8> M;
3068 return ::isPSHUFLWMask(M, N->getValueType(0));
3071 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3072 /// is suitable for input to PALIGNR.
3073 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3075 int i, e = VT.getVectorNumElements();
3077 // Do not handle v2i64 / v2f64 shuffles with palignr.
3078 if (e < 4 || !hasSSSE3)
3081 for (i = 0; i != e; ++i)
3085 // All undef, not a palignr.
3089 // Make sure we're shifting in the right direction.
3093 int s = Mask[i] - i;
3095 // Check the rest of the elements to see if they are consecutive.
3096 for (++i; i != e; ++i) {
3098 if (m >= 0 && m != s+i)
3104 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
3105 SmallVector<int, 8> M;
3107 return ::isPALIGNRMask(M, N->getValueType(0), true);
3110 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3111 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
3112 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3113 int NumElems = VT.getVectorNumElements();
3114 if (NumElems != 2 && NumElems != 4)
3117 int Half = NumElems / 2;
3118 for (int i = 0; i < Half; ++i)
3119 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3121 for (int i = Half; i < NumElems; ++i)
3122 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3128 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3129 SmallVector<int, 8> M;
3131 return ::isSHUFPMask(M, N->getValueType(0));
3134 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3135 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3136 /// half elements to come from vector 1 (which would equal the dest.) and
3137 /// the upper half to come from vector 2.
3138 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3139 int NumElems = VT.getVectorNumElements();
3141 if (NumElems != 2 && NumElems != 4)
3144 int Half = NumElems / 2;
3145 for (int i = 0; i < Half; ++i)
3146 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3148 for (int i = Half; i < NumElems; ++i)
3149 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3154 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3155 SmallVector<int, 8> M;
3157 return isCommutedSHUFPMask(M, N->getValueType(0));
3160 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3161 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3162 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3163 if (N->getValueType(0).getVectorNumElements() != 4)
3166 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3167 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3168 isUndefOrEqual(N->getMaskElt(1), 7) &&
3169 isUndefOrEqual(N->getMaskElt(2), 2) &&
3170 isUndefOrEqual(N->getMaskElt(3), 3);
3173 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3174 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3176 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3177 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3182 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3183 isUndefOrEqual(N->getMaskElt(1), 3) &&
3184 isUndefOrEqual(N->getMaskElt(2), 2) &&
3185 isUndefOrEqual(N->getMaskElt(3), 3);
3188 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3189 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3190 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3191 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3193 if (NumElems != 2 && NumElems != 4)
3196 for (unsigned i = 0; i < NumElems/2; ++i)
3197 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3200 for (unsigned i = NumElems/2; i < NumElems; ++i)
3201 if (!isUndefOrEqual(N->getMaskElt(i), i))
3207 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3208 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3209 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3210 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3212 if ((NumElems != 2 && NumElems != 4)
3213 || N->getValueType(0).getSizeInBits() > 128)
3216 for (unsigned i = 0; i < NumElems/2; ++i)
3217 if (!isUndefOrEqual(N->getMaskElt(i), i))
3220 for (unsigned i = 0; i < NumElems/2; ++i)
3221 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3227 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3228 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3229 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3230 bool V2IsSplat = false) {
3231 int NumElts = VT.getVectorNumElements();
3233 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3234 "Unsupported vector type for unpckh");
3236 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3239 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3240 // independently on 128-bit lanes.
3241 unsigned NumLanes = VT.getSizeInBits()/128;
3242 unsigned NumLaneElts = NumElts/NumLanes;
3245 unsigned End = NumLaneElts;
3246 for (unsigned s = 0; s < NumLanes; ++s) {
3247 for (unsigned i = Start, j = s * NumLaneElts;
3251 int BitI1 = Mask[i+1];
3252 if (!isUndefOrEqual(BitI, j))
3255 if (!isUndefOrEqual(BitI1, NumElts))
3258 if (!isUndefOrEqual(BitI1, j + NumElts))
3262 // Process the next 128 bits.
3263 Start += NumLaneElts;
3270 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3271 SmallVector<int, 8> M;
3273 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3276 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3277 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3278 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3279 bool V2IsSplat = false) {
3280 int NumElts = VT.getVectorNumElements();
3282 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3283 "Unsupported vector type for unpckh");
3285 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3288 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3289 // independently on 128-bit lanes.
3290 unsigned NumLanes = VT.getSizeInBits()/128;
3291 unsigned NumLaneElts = NumElts/NumLanes;
3294 unsigned End = NumLaneElts;
3295 for (unsigned l = 0; l != NumLanes; ++l) {
3296 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
3297 i != End; i += 2, ++j) {
3299 int BitI1 = Mask[i+1];
3300 if (!isUndefOrEqual(BitI, j))
3303 if (isUndefOrEqual(BitI1, NumElts))
3306 if (!isUndefOrEqual(BitI1, j+NumElts))
3310 // Process the next 128 bits.
3311 Start += NumLaneElts;
3317 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3318 SmallVector<int, 8> M;
3320 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3323 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3324 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3326 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3327 int NumElems = VT.getVectorNumElements();
3328 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3331 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3332 // independently on 128-bit lanes.
3333 unsigned NumLanes = VT.getSizeInBits() / 128;
3334 unsigned NumLaneElts = NumElems / NumLanes;
3336 for (unsigned s = 0; s < NumLanes; ++s) {
3337 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
3338 i != NumLaneElts * (s + 1);
3341 int BitI1 = Mask[i+1];
3343 if (!isUndefOrEqual(BitI, j))
3345 if (!isUndefOrEqual(BitI1, j))
3353 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3354 SmallVector<int, 8> M;
3356 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3359 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3360 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3362 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3363 int NumElems = VT.getVectorNumElements();
3364 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3367 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3369 int BitI1 = Mask[i+1];
3370 if (!isUndefOrEqual(BitI, j))
3372 if (!isUndefOrEqual(BitI1, j))
3378 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3379 SmallVector<int, 8> M;
3381 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3384 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3385 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3386 /// MOVSD, and MOVD, i.e. setting the lowest element.
3387 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3388 if (VT.getVectorElementType().getSizeInBits() < 32)
3391 int NumElts = VT.getVectorNumElements();
3393 if (!isUndefOrEqual(Mask[0], NumElts))
3396 for (int i = 1; i < NumElts; ++i)
3397 if (!isUndefOrEqual(Mask[i], i))
3403 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3404 SmallVector<int, 8> M;
3406 return ::isMOVLMask(M, N->getValueType(0));
3409 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand
3410 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3411 /// Note that VPERMIL mask matching is different depending whether theunderlying
3412 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3413 /// to the same elements of the low, but to the higher half of the source.
3414 /// In VPERMILPD the two lanes could be shuffled independently of each other
3415 /// with the same restriction that lanes can't be crossed.
3416 static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
3417 const X86Subtarget *Subtarget) {
3418 int NumElts = VT.getVectorNumElements();
3419 int NumLanes = VT.getSizeInBits()/128;
3421 if (!Subtarget->hasAVX())
3424 // Match any permutation of 128-bit vector with 64-bit types
3425 if (NumLanes == 1 && NumElts != 2)
3428 // Only match 256-bit with 32 types
3429 if (VT.getSizeInBits() == 256 && NumElts != 4)
3432 // The mask on the high lane is independent of the low. Both can match
3433 // any element in inside its own lane, but can't cross.
3434 int LaneSize = NumElts/NumLanes;
3435 for (int l = 0; l < NumLanes; ++l)
3436 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3437 int LaneStart = l*LaneSize;
3438 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize))
3445 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand
3446 /// specifies a shuffle of elements that is suitable for input to VPERMILPS*.
3447 /// Note that VPERMIL mask matching is different depending whether theunderlying
3448 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3449 /// to the same elements of the low, but to the higher half of the source.
3450 /// In VPERMILPD the two lanes could be shuffled independently of each other
3451 /// with the same restriction that lanes can't be crossed.
3452 static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
3453 const X86Subtarget *Subtarget) {
3454 unsigned NumElts = VT.getVectorNumElements();
3455 unsigned NumLanes = VT.getSizeInBits()/128;
3457 if (!Subtarget->hasAVX())
3460 // Match any permutation of 128-bit vector with 32-bit types
3461 if (NumLanes == 1 && NumElts != 4)
3464 // Only match 256-bit with 32 types
3465 if (VT.getSizeInBits() == 256 && NumElts != 8)
3468 // The mask on the high lane should be the same as the low. Actually,
3469 // they can differ if any of the corresponding index in a lane is undef.
3470 int LaneSize = NumElts/NumLanes;
3471 for (int i = 0; i < LaneSize; ++i) {
3472 int HighElt = i+LaneSize;
3473 if (Mask[i] < 0 || Mask[HighElt] < 0)
3475 if (Mask[HighElt]-Mask[i] != LaneSize)
3482 /// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle
3483 /// the specified VECTOR_MASK mask with VPERMILPS* instructions.
3484 static unsigned getShuffleVPERMILPSImmediate(SDNode *N) {
3485 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3486 EVT VT = SVOp->getValueType(0);
3488 int NumElts = VT.getVectorNumElements();
3489 int NumLanes = VT.getSizeInBits()/128;
3492 for (int i = 0; i < NumElts/NumLanes /* lane size */; ++i)
3493 Mask |= SVOp->getMaskElt(i) << (i*2);
3498 /// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle
3499 /// the specified VECTOR_MASK mask with VPERMILPD* instructions.
3500 static unsigned getShuffleVPERMILPDImmediate(SDNode *N) {
3501 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3502 EVT VT = SVOp->getValueType(0);
3504 int NumElts = VT.getVectorNumElements();
3505 int NumLanes = VT.getSizeInBits()/128;
3508 int LaneSize = NumElts/NumLanes;
3509 for (int l = 0; l < NumLanes; ++l)
3510 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i)
3511 Mask |= (SVOp->getMaskElt(i)-l*LaneSize) << i;
3516 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3517 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3518 /// element of vector 2 and the other elements to come from vector 1 in order.
3519 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3520 bool V2IsSplat = false, bool V2IsUndef = false) {
3521 int NumOps = VT.getVectorNumElements();
3522 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3525 if (!isUndefOrEqual(Mask[0], 0))
3528 for (int i = 1; i < NumOps; ++i)
3529 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3530 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3531 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3537 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3538 bool V2IsUndef = false) {
3539 SmallVector<int, 8> M;
3541 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3544 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3545 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3546 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3547 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3548 const X86Subtarget *Subtarget) {
3549 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3552 // The second vector must be undef
3553 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3556 EVT VT = N->getValueType(0);
3557 unsigned NumElems = VT.getVectorNumElements();
3559 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3560 (VT.getSizeInBits() == 256 && NumElems != 8))
3563 // "i+1" is the value the indexed mask element must have
3564 for (unsigned i = 0; i < NumElems; i += 2)
3565 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3566 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3572 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3573 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3574 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3575 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3576 const X86Subtarget *Subtarget) {
3577 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3580 // The second vector must be undef
3581 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3584 EVT VT = N->getValueType(0);
3585 unsigned NumElems = VT.getVectorNumElements();
3587 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3588 (VT.getSizeInBits() == 256 && NumElems != 8))
3591 // "i" is the value the indexed mask element must have
3592 for (unsigned i = 0; i < NumElems; i += 2)
3593 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3594 !isUndefOrEqual(N->getMaskElt(i+1), i))
3600 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3601 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3602 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3603 int e = N->getValueType(0).getVectorNumElements() / 2;
3605 for (int i = 0; i < e; ++i)
3606 if (!isUndefOrEqual(N->getMaskElt(i), i))
3608 for (int i = 0; i < e; ++i)
3609 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3614 /// isVEXTRACTF128Index - Return true if the specified
3615 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3616 /// suitable for input to VEXTRACTF128.
3617 bool X86::isVEXTRACTF128Index(SDNode *N) {
3618 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3621 // The index should be aligned on a 128-bit boundary.
3623 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3625 unsigned VL = N->getValueType(0).getVectorNumElements();
3626 unsigned VBits = N->getValueType(0).getSizeInBits();
3627 unsigned ElSize = VBits / VL;
3628 bool Result = (Index * ElSize) % 128 == 0;
3633 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3634 /// operand specifies a subvector insert that is suitable for input to
3636 bool X86::isVINSERTF128Index(SDNode *N) {
3637 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3640 // The index should be aligned on a 128-bit boundary.
3642 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3644 unsigned VL = N->getValueType(0).getVectorNumElements();
3645 unsigned VBits = N->getValueType(0).getSizeInBits();
3646 unsigned ElSize = VBits / VL;
3647 bool Result = (Index * ElSize) % 128 == 0;
3652 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3653 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3654 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3655 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3656 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3658 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3660 for (int i = 0; i < NumOperands; ++i) {
3661 int Val = SVOp->getMaskElt(NumOperands-i-1);
3662 if (Val < 0) Val = 0;
3663 if (Val >= NumOperands) Val -= NumOperands;
3665 if (i != NumOperands - 1)
3671 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3672 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3673 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3674 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3676 // 8 nodes, but we only care about the last 4.
3677 for (unsigned i = 7; i >= 4; --i) {
3678 int Val = SVOp->getMaskElt(i);
3687 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3688 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3689 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3690 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3692 // 8 nodes, but we only care about the first 4.
3693 for (int i = 3; i >= 0; --i) {
3694 int Val = SVOp->getMaskElt(i);
3703 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3704 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3705 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3706 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3707 EVT VVT = N->getValueType(0);
3708 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3712 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3713 Val = SVOp->getMaskElt(i);
3717 assert(Val - i > 0 && "PALIGNR imm should be positive");
3718 return (Val - i) * EltSize;
3721 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3722 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3724 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3725 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3726 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3729 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3731 EVT VecVT = N->getOperand(0).getValueType();
3732 EVT ElVT = VecVT.getVectorElementType();
3734 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3735 return Index / NumElemsPerChunk;
3738 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3739 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3741 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3742 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3743 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3746 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3748 EVT VecVT = N->getValueType(0);
3749 EVT ElVT = VecVT.getVectorElementType();
3751 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3752 return Index / NumElemsPerChunk;
3755 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3757 bool X86::isZeroNode(SDValue Elt) {
3758 return ((isa<ConstantSDNode>(Elt) &&
3759 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3760 (isa<ConstantFPSDNode>(Elt) &&
3761 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3764 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3765 /// their permute mask.
3766 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3767 SelectionDAG &DAG) {
3768 EVT VT = SVOp->getValueType(0);
3769 unsigned NumElems = VT.getVectorNumElements();
3770 SmallVector<int, 8> MaskVec;
3772 for (unsigned i = 0; i != NumElems; ++i) {
3773 int idx = SVOp->getMaskElt(i);
3775 MaskVec.push_back(idx);
3776 else if (idx < (int)NumElems)
3777 MaskVec.push_back(idx + NumElems);
3779 MaskVec.push_back(idx - NumElems);
3781 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3782 SVOp->getOperand(0), &MaskVec[0]);
3785 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3786 /// the two vector operands have swapped position.
3787 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3788 unsigned NumElems = VT.getVectorNumElements();
3789 for (unsigned i = 0; i != NumElems; ++i) {
3793 else if (idx < (int)NumElems)
3794 Mask[i] = idx + NumElems;
3796 Mask[i] = idx - NumElems;
3800 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3801 /// match movhlps. The lower half elements should come from upper half of
3802 /// V1 (and in order), and the upper half elements should come from the upper
3803 /// half of V2 (and in order).
3804 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3805 if (Op->getValueType(0).getVectorNumElements() != 4)
3807 for (unsigned i = 0, e = 2; i != e; ++i)
3808 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3810 for (unsigned i = 2; i != 4; ++i)
3811 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3816 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3817 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3819 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3820 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3822 N = N->getOperand(0).getNode();
3823 if (!ISD::isNON_EXTLoad(N))
3826 *LD = cast<LoadSDNode>(N);
3830 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3831 /// match movlp{s|d}. The lower half elements should come from lower half of
3832 /// V1 (and in order), and the upper half elements should come from the upper
3833 /// half of V2 (and in order). And since V1 will become the source of the
3834 /// MOVLP, it must be either a vector load or a scalar load to vector.
3835 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3836 ShuffleVectorSDNode *Op) {
3837 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3839 // Is V2 is a vector load, don't do this transformation. We will try to use
3840 // load folding shufps op.
3841 if (ISD::isNON_EXTLoad(V2))
3844 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3846 if (NumElems != 2 && NumElems != 4)
3848 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3849 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3851 for (unsigned i = NumElems/2; i != NumElems; ++i)
3852 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3857 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3859 static bool isSplatVector(SDNode *N) {
3860 if (N->getOpcode() != ISD::BUILD_VECTOR)
3863 SDValue SplatValue = N->getOperand(0);
3864 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3865 if (N->getOperand(i) != SplatValue)
3870 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3871 /// to an zero vector.
3872 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3873 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3874 SDValue V1 = N->getOperand(0);
3875 SDValue V2 = N->getOperand(1);
3876 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3877 for (unsigned i = 0; i != NumElems; ++i) {
3878 int Idx = N->getMaskElt(i);
3879 if (Idx >= (int)NumElems) {
3880 unsigned Opc = V2.getOpcode();
3881 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3883 if (Opc != ISD::BUILD_VECTOR ||
3884 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3886 } else if (Idx >= 0) {
3887 unsigned Opc = V1.getOpcode();
3888 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3890 if (Opc != ISD::BUILD_VECTOR ||
3891 !X86::isZeroNode(V1.getOperand(Idx)))
3898 /// getZeroVector - Returns a vector of specified type with all zero elements.
3900 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3902 assert(VT.isVector() && "Expected a vector type");
3904 // Always build SSE zero vectors as <4 x i32> bitcasted
3905 // to their dest type. This ensures they get CSE'd.
3907 if (VT.getSizeInBits() == 128) { // SSE
3908 if (HasSSE2) { // SSE2
3909 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3910 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3912 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3913 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3915 } else if (VT.getSizeInBits() == 256) { // AVX
3916 // 256-bit logic and arithmetic instructions in AVX are
3917 // all floating-point, no support for integer ops. Default
3918 // to emitting fp zeroed vectors then.
3919 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3920 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3921 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
3923 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3926 /// getOnesVector - Returns a vector of specified type with all bits set.
3927 /// Always build ones vectors as <4 x i32>. For 256-bit types, use two
3928 /// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
3929 /// original type, ensuring they get CSE'd.
3930 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3931 assert(VT.isVector() && "Expected a vector type");
3932 assert((VT.is128BitVector() || VT.is256BitVector())
3933 && "Expected a 128-bit or 256-bit vector type");
3935 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3936 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
3937 Cst, Cst, Cst, Cst);
3939 if (VT.is256BitVector()) {
3940 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
3941 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
3942 Vec = Insert128BitVector(InsV, Vec,
3943 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
3946 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3949 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3950 /// that point to V2 points to its first element.
3951 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3952 EVT VT = SVOp->getValueType(0);
3953 unsigned NumElems = VT.getVectorNumElements();
3955 bool Changed = false;
3956 SmallVector<int, 8> MaskVec;
3957 SVOp->getMask(MaskVec);
3959 for (unsigned i = 0; i != NumElems; ++i) {
3960 if (MaskVec[i] > (int)NumElems) {
3961 MaskVec[i] = NumElems;
3966 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3967 SVOp->getOperand(1), &MaskVec[0]);
3968 return SDValue(SVOp, 0);
3971 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3972 /// operation of specified width.
3973 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3975 unsigned NumElems = VT.getVectorNumElements();
3976 SmallVector<int, 8> Mask;
3977 Mask.push_back(NumElems);
3978 for (unsigned i = 1; i != NumElems; ++i)
3980 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3983 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3984 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3986 unsigned NumElems = VT.getVectorNumElements();
3987 SmallVector<int, 8> Mask;
3988 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3990 Mask.push_back(i + NumElems);
3992 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3995 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
3996 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3998 unsigned NumElems = VT.getVectorNumElements();
3999 unsigned Half = NumElems/2;
4000 SmallVector<int, 8> Mask;
4001 for (unsigned i = 0; i != Half; ++i) {
4002 Mask.push_back(i + Half);
4003 Mask.push_back(i + NumElems + Half);
4005 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4008 // PromoteSplatv8v16 - All i16 and i8 vector types can't be used directly by
4009 // a generic shuffle instruction because the target has no such instructions.
4010 // Generate shuffles which repeat i16 and i8 several times until they can be
4011 // represented by v4f32 and then be manipulated by target suported shuffles.
4012 static SDValue PromoteSplatv8v16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4013 EVT VT = V.getValueType();
4014 int NumElems = VT.getVectorNumElements();
4015 DebugLoc dl = V.getDebugLoc();
4017 while (NumElems > 4) {
4018 if (EltNo < NumElems/2) {
4019 V = getUnpackl(DAG, dl, VT, V, V);
4021 V = getUnpackh(DAG, dl, VT, V, V);
4022 EltNo -= NumElems/2;
4029 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4030 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4031 EVT VT = V.getValueType();
4032 DebugLoc dl = V.getDebugLoc();
4033 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4034 && "Vector size not supported");
4036 bool Is128 = VT.getSizeInBits() == 128;
4037 EVT NVT = Is128 ? MVT::v4f32 : MVT::v8f32;
4038 V = DAG.getNode(ISD::BITCAST, dl, NVT, V);
4041 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4042 V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]);
4044 // The second half of indicies refer to the higher part, which is a
4045 // duplication of the lower one. This makes this shuffle a perfect match
4046 // for the VPERM instruction.
4047 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4048 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4049 V = DAG.getVectorShuffle(NVT, dl, V, DAG.getUNDEF(NVT), &SplatMask[0]);
4052 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4055 /// PromoteVectorToScalarSplat - Since there's no native support for
4056 /// scalar_to_vector for 256-bit AVX, a 128-bit scalar_to_vector +
4057 /// INSERT_SUBVECTOR is generated. Recognize this idiom and do the
4058 /// shuffle before the insertion, this yields less instructions in the end.
4059 static SDValue PromoteVectorToScalarSplat(ShuffleVectorSDNode *SV,
4060 SelectionDAG &DAG) {
4061 EVT SrcVT = SV->getValueType(0);
4062 SDValue V1 = SV->getOperand(0);
4063 DebugLoc dl = SV->getDebugLoc();
4064 int NumElems = SrcVT.getVectorNumElements();
4066 assert(SrcVT.is256BitVector() && "unknown howto handle vector type");
4068 SmallVector<int, 4> Mask;
4069 for (int i = 0; i < NumElems/2; ++i)
4070 Mask.push_back(SV->getMaskElt(i));
4072 EVT SVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
4074 SDValue SV1 = DAG.getVectorShuffle(SVT, dl, V1.getOperand(1),
4075 DAG.getUNDEF(SVT), &Mask[0]);
4076 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), SV1,
4077 DAG.getConstant(0, MVT::i32), DAG, dl);
4079 return Insert128BitVector(InsV, SV1,
4080 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4083 /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32 and
4084 /// v8i32, v16i16 or v32i8 to v8f32.
4085 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4086 EVT SrcVT = SV->getValueType(0);
4087 SDValue V1 = SV->getOperand(0);
4088 DebugLoc dl = SV->getDebugLoc();
4090 int EltNo = SV->getSplatIndex();
4091 int NumElems = SrcVT.getVectorNumElements();
4092 unsigned Size = SrcVT.getSizeInBits();
4094 // Extract the 128-bit part containing the splat element and update
4095 // the splat element index when it refers to the higher register.
4097 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4098 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4100 EltNo -= NumElems/2;
4103 // Make this 128-bit vector duplicate i8 and i16 elements
4105 V1 = PromoteSplatv8v16(V1, DAG, EltNo);
4107 // Recreate the 256-bit vector and place the same 128-bit vector
4108 // into the low and high part. This is necessary because we want
4109 // to use VPERM to shuffle the v8f32 vector, and VPERM only shuffles
4110 // inside each separate v4f32 lane.
4112 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4113 DAG.getConstant(0, MVT::i32), DAG, dl);
4114 V1 = Insert128BitVector(InsV, V1,
4115 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4118 return getLegalSplat(DAG, V1, EltNo);
4121 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4122 /// vector of zero or undef vector. This produces a shuffle where the low
4123 /// element of V2 is swizzled into the zero/undef vector, landing at element
4124 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4125 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4126 bool isZero, bool HasSSE2,
4127 SelectionDAG &DAG) {
4128 EVT VT = V2.getValueType();
4130 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4131 unsigned NumElems = VT.getVectorNumElements();
4132 SmallVector<int, 16> MaskVec;
4133 for (unsigned i = 0; i != NumElems; ++i)
4134 // If this is the insertion idx, put the low elt of V2 here.
4135 MaskVec.push_back(i == Idx ? NumElems : i);
4136 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4139 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4140 /// element of the result of the vector shuffle.
4141 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4144 return SDValue(); // Limit search depth.
4146 SDValue V = SDValue(N, 0);
4147 EVT VT = V.getValueType();
4148 unsigned Opcode = V.getOpcode();
4150 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4151 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4152 Index = SV->getMaskElt(Index);
4155 return DAG.getUNDEF(VT.getVectorElementType());
4157 int NumElems = VT.getVectorNumElements();
4158 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4159 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4162 // Recurse into target specific vector shuffles to find scalars.
4163 if (isTargetShuffle(Opcode)) {
4164 int NumElems = VT.getVectorNumElements();
4165 SmallVector<unsigned, 16> ShuffleMask;
4169 case X86ISD::SHUFPS:
4170 case X86ISD::SHUFPD:
4171 ImmN = N->getOperand(N->getNumOperands()-1);
4172 DecodeSHUFPSMask(NumElems,
4173 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4176 case X86ISD::PUNPCKHBW:
4177 case X86ISD::PUNPCKHWD:
4178 case X86ISD::PUNPCKHDQ:
4179 case X86ISD::PUNPCKHQDQ:
4180 DecodePUNPCKHMask(NumElems, ShuffleMask);
4182 case X86ISD::UNPCKHPS:
4183 case X86ISD::UNPCKHPD:
4184 case X86ISD::VUNPCKHPSY:
4185 case X86ISD::VUNPCKHPDY:
4186 DecodeUNPCKHPMask(NumElems, ShuffleMask);
4188 case X86ISD::PUNPCKLBW:
4189 case X86ISD::PUNPCKLWD:
4190 case X86ISD::PUNPCKLDQ:
4191 case X86ISD::PUNPCKLQDQ:
4192 DecodePUNPCKLMask(VT, ShuffleMask);
4194 case X86ISD::UNPCKLPS:
4195 case X86ISD::UNPCKLPD:
4196 case X86ISD::VUNPCKLPSY:
4197 case X86ISD::VUNPCKLPDY:
4198 DecodeUNPCKLPMask(VT, ShuffleMask);
4200 case X86ISD::MOVHLPS:
4201 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4203 case X86ISD::MOVLHPS:
4204 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4206 case X86ISD::PSHUFD:
4207 ImmN = N->getOperand(N->getNumOperands()-1);
4208 DecodePSHUFMask(NumElems,
4209 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4212 case X86ISD::PSHUFHW:
4213 ImmN = N->getOperand(N->getNumOperands()-1);
4214 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4217 case X86ISD::PSHUFLW:
4218 ImmN = N->getOperand(N->getNumOperands()-1);
4219 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4223 case X86ISD::MOVSD: {
4224 // The index 0 always comes from the first element of the second source,
4225 // this is why MOVSS and MOVSD are used in the first place. The other
4226 // elements come from the other positions of the first source vector.
4227 unsigned OpNum = (Index == 0) ? 1 : 0;
4228 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4231 case X86ISD::VPERMILPS:
4232 case X86ISD::VPERMILPSY:
4233 // FIXME: Implement the other types
4234 ImmN = N->getOperand(N->getNumOperands()-1);
4235 DecodeVPERMILMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4238 assert("not implemented for target shuffle node");
4242 Index = ShuffleMask[Index];
4244 return DAG.getUNDEF(VT.getVectorElementType());
4246 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4247 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4251 // Actual nodes that may contain scalar elements
4252 if (Opcode == ISD::BITCAST) {
4253 V = V.getOperand(0);
4254 EVT SrcVT = V.getValueType();
4255 unsigned NumElems = VT.getVectorNumElements();
4257 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4261 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4262 return (Index == 0) ? V.getOperand(0)
4263 : DAG.getUNDEF(VT.getVectorElementType());
4265 if (V.getOpcode() == ISD::BUILD_VECTOR)
4266 return V.getOperand(Index);
4271 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4272 /// shuffle operation which come from a consecutively from a zero. The
4273 /// search can start in two different directions, from left or right.
4275 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4276 bool ZerosFromLeft, SelectionDAG &DAG) {
4279 while (i < NumElems) {
4280 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4281 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4282 if (!(Elt.getNode() &&
4283 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4291 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4292 /// MaskE correspond consecutively to elements from one of the vector operands,
4293 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4295 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4296 int OpIdx, int NumElems, unsigned &OpNum) {
4297 bool SeenV1 = false;
4298 bool SeenV2 = false;
4300 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4301 int Idx = SVOp->getMaskElt(i);
4302 // Ignore undef indicies
4311 // Only accept consecutive elements from the same vector
4312 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4316 OpNum = SeenV1 ? 0 : 1;
4320 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4321 /// logical left shift of a vector.
4322 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4323 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4324 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4325 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4326 false /* check zeros from right */, DAG);
4332 // Considering the elements in the mask that are not consecutive zeros,
4333 // check if they consecutively come from only one of the source vectors.
4335 // V1 = {X, A, B, C} 0
4337 // vector_shuffle V1, V2 <1, 2, 3, X>
4339 if (!isShuffleMaskConsecutive(SVOp,
4340 0, // Mask Start Index
4341 NumElems-NumZeros-1, // Mask End Index
4342 NumZeros, // Where to start looking in the src vector
4343 NumElems, // Number of elements in vector
4344 OpSrc)) // Which source operand ?
4349 ShVal = SVOp->getOperand(OpSrc);
4353 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4354 /// logical left shift of a vector.
4355 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4356 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4357 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4358 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4359 true /* check zeros from left */, DAG);
4365 // Considering the elements in the mask that are not consecutive zeros,
4366 // check if they consecutively come from only one of the source vectors.
4368 // 0 { A, B, X, X } = V2
4370 // vector_shuffle V1, V2 <X, X, 4, 5>
4372 if (!isShuffleMaskConsecutive(SVOp,
4373 NumZeros, // Mask Start Index
4374 NumElems-1, // Mask End Index
4375 0, // Where to start looking in the src vector
4376 NumElems, // Number of elements in vector
4377 OpSrc)) // Which source operand ?
4382 ShVal = SVOp->getOperand(OpSrc);
4386 /// isVectorShift - Returns true if the shuffle can be implemented as a
4387 /// logical left or right shift of a vector.
4388 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4389 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4390 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4391 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4397 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4399 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4400 unsigned NumNonZero, unsigned NumZero,
4402 const TargetLowering &TLI) {
4406 DebugLoc dl = Op.getDebugLoc();
4409 for (unsigned i = 0; i < 16; ++i) {
4410 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4411 if (ThisIsNonZero && First) {
4413 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4415 V = DAG.getUNDEF(MVT::v8i16);
4420 SDValue ThisElt(0, 0), LastElt(0, 0);
4421 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4422 if (LastIsNonZero) {
4423 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4424 MVT::i16, Op.getOperand(i-1));
4426 if (ThisIsNonZero) {
4427 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4428 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4429 ThisElt, DAG.getConstant(8, MVT::i8));
4431 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4435 if (ThisElt.getNode())
4436 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4437 DAG.getIntPtrConstant(i/2));
4441 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4444 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4446 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4447 unsigned NumNonZero, unsigned NumZero,
4449 const TargetLowering &TLI) {
4453 DebugLoc dl = Op.getDebugLoc();
4456 for (unsigned i = 0; i < 8; ++i) {
4457 bool isNonZero = (NonZeros & (1 << i)) != 0;
4461 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4463 V = DAG.getUNDEF(MVT::v8i16);
4466 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4467 MVT::v8i16, V, Op.getOperand(i),
4468 DAG.getIntPtrConstant(i));
4475 /// getVShift - Return a vector logical shift node.
4477 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4478 unsigned NumBits, SelectionDAG &DAG,
4479 const TargetLowering &TLI, DebugLoc dl) {
4480 EVT ShVT = MVT::v2i64;
4481 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4482 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4483 return DAG.getNode(ISD::BITCAST, dl, VT,
4484 DAG.getNode(Opc, dl, ShVT, SrcOp,
4485 DAG.getConstant(NumBits,
4486 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4490 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4491 SelectionDAG &DAG) const {
4493 // Check if the scalar load can be widened into a vector load. And if
4494 // the address is "base + cst" see if the cst can be "absorbed" into
4495 // the shuffle mask.
4496 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4497 SDValue Ptr = LD->getBasePtr();
4498 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4500 EVT PVT = LD->getValueType(0);
4501 if (PVT != MVT::i32 && PVT != MVT::f32)
4506 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4507 FI = FINode->getIndex();
4509 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4510 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4511 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4512 Offset = Ptr.getConstantOperandVal(1);
4513 Ptr = Ptr.getOperand(0);
4518 SDValue Chain = LD->getChain();
4519 // Make sure the stack object alignment is at least 16.
4520 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4521 if (DAG.InferPtrAlignment(Ptr) < 16) {
4522 if (MFI->isFixedObjectIndex(FI)) {
4523 // Can't change the alignment. FIXME: It's possible to compute
4524 // the exact stack offset and reference FI + adjust offset instead.
4525 // If someone *really* cares about this. That's the way to implement it.
4528 MFI->setObjectAlignment(FI, 16);
4532 // (Offset % 16) must be multiple of 4. Then address is then
4533 // Ptr + (Offset & ~15).
4536 if ((Offset % 16) & 3)
4538 int64_t StartOffset = Offset & ~15;
4540 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4541 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4543 int EltNo = (Offset - StartOffset) >> 2;
4544 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
4545 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
4546 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,
4547 LD->getPointerInfo().getWithOffset(StartOffset),
4549 // Canonicalize it to a v4i32 shuffle.
4550 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
4551 return DAG.getNode(ISD::BITCAST, dl, VT,
4552 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
4553 DAG.getUNDEF(MVT::v4i32),&Mask[0]));
4559 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4560 /// vector of type 'VT', see if the elements can be replaced by a single large
4561 /// load which has the same value as a build_vector whose operands are 'elts'.
4563 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4565 /// FIXME: we'd also like to handle the case where the last elements are zero
4566 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4567 /// There's even a handy isZeroNode for that purpose.
4568 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4569 DebugLoc &DL, SelectionDAG &DAG) {
4570 EVT EltVT = VT.getVectorElementType();
4571 unsigned NumElems = Elts.size();
4573 LoadSDNode *LDBase = NULL;
4574 unsigned LastLoadedElt = -1U;
4576 // For each element in the initializer, see if we've found a load or an undef.
4577 // If we don't find an initial load element, or later load elements are
4578 // non-consecutive, bail out.
4579 for (unsigned i = 0; i < NumElems; ++i) {
4580 SDValue Elt = Elts[i];
4582 if (!Elt.getNode() ||
4583 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4586 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4588 LDBase = cast<LoadSDNode>(Elt.getNode());
4592 if (Elt.getOpcode() == ISD::UNDEF)
4595 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4596 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4601 // If we have found an entire vector of loads and undefs, then return a large
4602 // load of the entire vector width starting at the base pointer. If we found
4603 // consecutive loads for the low half, generate a vzext_load node.
4604 if (LastLoadedElt == NumElems - 1) {
4605 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4606 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4607 LDBase->getPointerInfo(),
4608 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4609 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4610 LDBase->getPointerInfo(),
4611 LDBase->isVolatile(), LDBase->isNonTemporal(),
4612 LDBase->getAlignment());
4613 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4614 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4615 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4616 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4617 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4619 LDBase->getMemOperand());
4620 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4626 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4627 DebugLoc dl = Op.getDebugLoc();
4629 EVT VT = Op.getValueType();
4630 EVT ExtVT = VT.getVectorElementType();
4631 unsigned NumElems = Op.getNumOperands();
4634 // - pxor (SSE2), xorps (SSE1), vpxor (128 AVX), xorp[s|d] (256 AVX)
4636 // - pcmpeqd (SSE2 and 128 AVX), fallback to constant pools (256 AVX)
4637 if (ISD::isBuildVectorAllZeros(Op.getNode()) ||
4638 ISD::isBuildVectorAllOnes(Op.getNode())) {
4639 // Canonicalize this to <4 x i32> or <8 x 32> (SSE) to
4640 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
4641 // eliminated on x86-32 hosts.
4642 if (Op.getValueType() == MVT::v4i32 ||
4643 Op.getValueType() == MVT::v8i32)
4646 if (ISD::isBuildVectorAllOnes(Op.getNode()))
4647 return getOnesVector(Op.getValueType(), DAG, dl);
4648 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4651 unsigned EVTBits = ExtVT.getSizeInBits();
4653 unsigned NumZero = 0;
4654 unsigned NumNonZero = 0;
4655 unsigned NonZeros = 0;
4656 bool IsAllConstants = true;
4657 SmallSet<SDValue, 8> Values;
4658 for (unsigned i = 0; i < NumElems; ++i) {
4659 SDValue Elt = Op.getOperand(i);
4660 if (Elt.getOpcode() == ISD::UNDEF)
4663 if (Elt.getOpcode() != ISD::Constant &&
4664 Elt.getOpcode() != ISD::ConstantFP)
4665 IsAllConstants = false;
4666 if (X86::isZeroNode(Elt))
4669 NonZeros |= (1 << i);
4674 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4675 if (NumNonZero == 0)
4676 return DAG.getUNDEF(VT);
4678 // Special case for single non-zero, non-undef, element.
4679 if (NumNonZero == 1) {
4680 unsigned Idx = CountTrailingZeros_32(NonZeros);
4681 SDValue Item = Op.getOperand(Idx);
4683 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4684 // the value are obviously zero, truncate the value to i32 and do the
4685 // insertion that way. Only do this if the value is non-constant or if the
4686 // value is a constant being inserted into element 0. It is cheaper to do
4687 // a constant pool load than it is to do a movd + shuffle.
4688 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4689 (!IsAllConstants || Idx == 0)) {
4690 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4692 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
4693 EVT VecVT = MVT::v4i32;
4694 unsigned VecElts = 4;
4696 // Truncate the value (which may itself be a constant) to i32, and
4697 // convert it to a vector with movd (S2V+shuffle to zero extend).
4698 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4699 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4700 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4701 Subtarget->hasSSE2(), DAG);
4703 // Now we have our 32-bit value zero extended in the low element of
4704 // a vector. If Idx != 0, swizzle it into place.
4706 SmallVector<int, 4> Mask;
4707 Mask.push_back(Idx);
4708 for (unsigned i = 1; i != VecElts; ++i)
4710 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4711 DAG.getUNDEF(Item.getValueType()),
4714 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
4718 // If we have a constant or non-constant insertion into the low element of
4719 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4720 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4721 // depending on what the source datatype is.
4724 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4725 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4726 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4727 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4728 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4729 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4731 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4732 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4733 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
4734 EVT MiddleVT = MVT::v4i32;
4735 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4736 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4737 Subtarget->hasSSE2(), DAG);
4738 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
4742 // Is it a vector logical left shift?
4743 if (NumElems == 2 && Idx == 1 &&
4744 X86::isZeroNode(Op.getOperand(0)) &&
4745 !X86::isZeroNode(Op.getOperand(1))) {
4746 unsigned NumBits = VT.getSizeInBits();
4747 return getVShift(true, VT,
4748 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4749 VT, Op.getOperand(1)),
4750 NumBits/2, DAG, *this, dl);
4753 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4756 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4757 // is a non-constant being inserted into an element other than the low one,
4758 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4759 // movd/movss) to move this into the low element, then shuffle it into
4761 if (EVTBits == 32) {
4762 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4764 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4765 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4766 Subtarget->hasSSE2(), DAG);
4767 SmallVector<int, 8> MaskVec;
4768 for (unsigned i = 0; i < NumElems; i++)
4769 MaskVec.push_back(i == Idx ? 0 : 1);
4770 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4774 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4775 if (Values.size() == 1) {
4776 if (EVTBits == 32) {
4777 // Instead of a shuffle like this:
4778 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4779 // Check if it's possible to issue this instead.
4780 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4781 unsigned Idx = CountTrailingZeros_32(NonZeros);
4782 SDValue Item = Op.getOperand(Idx);
4783 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4784 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4789 // A vector full of immediates; various special cases are already
4790 // handled, so this is best done with a single constant-pool load.
4794 // For AVX-length vectors, build the individual 128-bit pieces and use
4795 // shuffles to put them in place.
4796 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
4797 SmallVector<SDValue, 32> V;
4798 for (unsigned i = 0; i < NumElems; ++i)
4799 V.push_back(Op.getOperand(i));
4801 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
4803 // Build both the lower and upper subvector.
4804 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
4805 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
4808 // Recreate the wider vector with the lower and upper part.
4809 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Upper,
4810 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4811 return Insert128BitVector(Vec, Lower, DAG.getConstant(0, MVT::i32),
4815 // Let legalizer expand 2-wide build_vectors.
4816 if (EVTBits == 64) {
4817 if (NumNonZero == 1) {
4818 // One half is zero or undef.
4819 unsigned Idx = CountTrailingZeros_32(NonZeros);
4820 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4821 Op.getOperand(Idx));
4822 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4823 Subtarget->hasSSE2(), DAG);
4828 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4829 if (EVTBits == 8 && NumElems == 16) {
4830 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4832 if (V.getNode()) return V;
4835 if (EVTBits == 16 && NumElems == 8) {
4836 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4838 if (V.getNode()) return V;
4841 // If element VT is == 32 bits, turn it into a number of shuffles.
4842 SmallVector<SDValue, 8> V;
4844 if (NumElems == 4 && NumZero > 0) {
4845 for (unsigned i = 0; i < 4; ++i) {
4846 bool isZero = !(NonZeros & (1 << i));
4848 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4850 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4853 for (unsigned i = 0; i < 2; ++i) {
4854 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4857 V[i] = V[i*2]; // Must be a zero vector.
4860 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4863 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4866 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4871 SmallVector<int, 8> MaskVec;
4872 bool Reverse = (NonZeros & 0x3) == 2;
4873 for (unsigned i = 0; i < 2; ++i)
4874 MaskVec.push_back(Reverse ? 1-i : i);
4875 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4876 for (unsigned i = 0; i < 2; ++i)
4877 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4878 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4881 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4882 // Check for a build vector of consecutive loads.
4883 for (unsigned i = 0; i < NumElems; ++i)
4884 V[i] = Op.getOperand(i);
4886 // Check for elements which are consecutive loads.
4887 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4891 // For SSE 4.1, use insertps to put the high elements into the low element.
4892 if (getSubtarget()->hasSSE41()) {
4894 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
4895 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
4897 Result = DAG.getUNDEF(VT);
4899 for (unsigned i = 1; i < NumElems; ++i) {
4900 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
4901 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
4902 Op.getOperand(i), DAG.getIntPtrConstant(i));
4907 // Otherwise, expand into a number of unpckl*, start by extending each of
4908 // our (non-undef) elements to the full vector width with the element in the
4909 // bottom slot of the vector (which generates no code for SSE).
4910 for (unsigned i = 0; i < NumElems; ++i) {
4911 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4912 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4914 V[i] = DAG.getUNDEF(VT);
4917 // Next, we iteratively mix elements, e.g. for v4f32:
4918 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4919 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4920 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4921 unsigned EltStride = NumElems >> 1;
4922 while (EltStride != 0) {
4923 for (unsigned i = 0; i < EltStride; ++i) {
4924 // If V[i+EltStride] is undef and this is the first round of mixing,
4925 // then it is safe to just drop this shuffle: V[i] is already in the
4926 // right place, the one element (since it's the first round) being
4927 // inserted as undef can be dropped. This isn't safe for successive
4928 // rounds because they will permute elements within both vectors.
4929 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
4930 EltStride == NumElems/2)
4933 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
4943 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4944 // We support concatenate two MMX registers and place them in a MMX
4945 // register. This is better than doing a stack convert.
4946 DebugLoc dl = Op.getDebugLoc();
4947 EVT ResVT = Op.getValueType();
4948 assert(Op.getNumOperands() == 2);
4949 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4950 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4952 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
4953 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4954 InVec = Op.getOperand(1);
4955 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4956 unsigned NumElts = ResVT.getVectorNumElements();
4957 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
4958 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4959 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4961 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
4962 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4963 Mask[0] = 0; Mask[1] = 2;
4964 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4966 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
4969 // v8i16 shuffles - Prefer shuffles in the following order:
4970 // 1. [all] pshuflw, pshufhw, optional move
4971 // 2. [ssse3] 1 x pshufb
4972 // 3. [ssse3] 2 x pshufb + 1 x por
4973 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4975 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
4976 SelectionDAG &DAG) const {
4977 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4978 SDValue V1 = SVOp->getOperand(0);
4979 SDValue V2 = SVOp->getOperand(1);
4980 DebugLoc dl = SVOp->getDebugLoc();
4981 SmallVector<int, 8> MaskVals;
4983 // Determine if more than 1 of the words in each of the low and high quadwords
4984 // of the result come from the same quadword of one of the two inputs. Undef
4985 // mask values count as coming from any quadword, for better codegen.
4986 SmallVector<unsigned, 4> LoQuad(4);
4987 SmallVector<unsigned, 4> HiQuad(4);
4988 BitVector InputQuads(4);
4989 for (unsigned i = 0; i < 8; ++i) {
4990 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4991 int EltIdx = SVOp->getMaskElt(i);
4992 MaskVals.push_back(EltIdx);
5001 InputQuads.set(EltIdx / 4);
5004 int BestLoQuad = -1;
5005 unsigned MaxQuad = 1;
5006 for (unsigned i = 0; i < 4; ++i) {
5007 if (LoQuad[i] > MaxQuad) {
5009 MaxQuad = LoQuad[i];
5013 int BestHiQuad = -1;
5015 for (unsigned i = 0; i < 4; ++i) {
5016 if (HiQuad[i] > MaxQuad) {
5018 MaxQuad = HiQuad[i];
5022 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5023 // of the two input vectors, shuffle them into one input vector so only a
5024 // single pshufb instruction is necessary. If There are more than 2 input
5025 // quads, disable the next transformation since it does not help SSSE3.
5026 bool V1Used = InputQuads[0] || InputQuads[1];
5027 bool V2Used = InputQuads[2] || InputQuads[3];
5028 if (Subtarget->hasSSSE3()) {
5029 if (InputQuads.count() == 2 && V1Used && V2Used) {
5030 BestLoQuad = InputQuads.find_first();
5031 BestHiQuad = InputQuads.find_next(BestLoQuad);
5033 if (InputQuads.count() > 2) {
5039 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5040 // the shuffle mask. If a quad is scored as -1, that means that it contains
5041 // words from all 4 input quadwords.
5043 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5044 SmallVector<int, 8> MaskV;
5045 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5046 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5047 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5048 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5049 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5050 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5052 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5053 // source words for the shuffle, to aid later transformations.
5054 bool AllWordsInNewV = true;
5055 bool InOrder[2] = { true, true };
5056 for (unsigned i = 0; i != 8; ++i) {
5057 int idx = MaskVals[i];
5059 InOrder[i/4] = false;
5060 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5062 AllWordsInNewV = false;
5066 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5067 if (AllWordsInNewV) {
5068 for (int i = 0; i != 8; ++i) {
5069 int idx = MaskVals[i];
5072 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5073 if ((idx != i) && idx < 4)
5075 if ((idx != i) && idx > 3)
5084 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5085 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5086 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5087 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5088 unsigned TargetMask = 0;
5089 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5090 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5091 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5092 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5093 V1 = NewV.getOperand(0);
5094 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5098 // If we have SSSE3, and all words of the result are from 1 input vector,
5099 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5100 // is present, fall back to case 4.
5101 if (Subtarget->hasSSSE3()) {
5102 SmallVector<SDValue,16> pshufbMask;
5104 // If we have elements from both input vectors, set the high bit of the
5105 // shuffle mask element to zero out elements that come from V2 in the V1
5106 // mask, and elements that come from V1 in the V2 mask, so that the two
5107 // results can be OR'd together.
5108 bool TwoInputs = V1Used && V2Used;
5109 for (unsigned i = 0; i != 8; ++i) {
5110 int EltIdx = MaskVals[i] * 2;
5111 if (TwoInputs && (EltIdx >= 16)) {
5112 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5113 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5116 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5117 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5119 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5120 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5121 DAG.getNode(ISD::BUILD_VECTOR, dl,
5122 MVT::v16i8, &pshufbMask[0], 16));
5124 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5126 // Calculate the shuffle mask for the second input, shuffle it, and
5127 // OR it with the first shuffled input.
5129 for (unsigned i = 0; i != 8; ++i) {
5130 int EltIdx = MaskVals[i] * 2;
5132 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5133 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5136 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5137 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5139 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5140 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5141 DAG.getNode(ISD::BUILD_VECTOR, dl,
5142 MVT::v16i8, &pshufbMask[0], 16));
5143 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5144 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5147 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5148 // and update MaskVals with new element order.
5149 BitVector InOrder(8);
5150 if (BestLoQuad >= 0) {
5151 SmallVector<int, 8> MaskV;
5152 for (int i = 0; i != 4; ++i) {
5153 int idx = MaskVals[i];
5155 MaskV.push_back(-1);
5157 } else if ((idx / 4) == BestLoQuad) {
5158 MaskV.push_back(idx & 3);
5161 MaskV.push_back(-1);
5164 for (unsigned i = 4; i != 8; ++i)
5166 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5169 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5170 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5172 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5176 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5177 // and update MaskVals with the new element order.
5178 if (BestHiQuad >= 0) {
5179 SmallVector<int, 8> MaskV;
5180 for (unsigned i = 0; i != 4; ++i)
5182 for (unsigned i = 4; i != 8; ++i) {
5183 int idx = MaskVals[i];
5185 MaskV.push_back(-1);
5187 } else if ((idx / 4) == BestHiQuad) {
5188 MaskV.push_back((idx & 3) + 4);
5191 MaskV.push_back(-1);
5194 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5197 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5198 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5200 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5204 // In case BestHi & BestLo were both -1, which means each quadword has a word
5205 // from each of the four input quadwords, calculate the InOrder bitvector now
5206 // before falling through to the insert/extract cleanup.
5207 if (BestLoQuad == -1 && BestHiQuad == -1) {
5209 for (int i = 0; i != 8; ++i)
5210 if (MaskVals[i] < 0 || MaskVals[i] == i)
5214 // The other elements are put in the right place using pextrw and pinsrw.
5215 for (unsigned i = 0; i != 8; ++i) {
5218 int EltIdx = MaskVals[i];
5221 SDValue ExtOp = (EltIdx < 8)
5222 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5223 DAG.getIntPtrConstant(EltIdx))
5224 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5225 DAG.getIntPtrConstant(EltIdx - 8));
5226 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5227 DAG.getIntPtrConstant(i));
5232 // v16i8 shuffles - Prefer shuffles in the following order:
5233 // 1. [ssse3] 1 x pshufb
5234 // 2. [ssse3] 2 x pshufb + 1 x por
5235 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5237 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5239 const X86TargetLowering &TLI) {
5240 SDValue V1 = SVOp->getOperand(0);
5241 SDValue V2 = SVOp->getOperand(1);
5242 DebugLoc dl = SVOp->getDebugLoc();
5243 SmallVector<int, 16> MaskVals;
5244 SVOp->getMask(MaskVals);
5246 // If we have SSSE3, case 1 is generated when all result bytes come from
5247 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5248 // present, fall back to case 3.
5249 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5252 for (unsigned i = 0; i < 16; ++i) {
5253 int EltIdx = MaskVals[i];
5262 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5263 if (TLI.getSubtarget()->hasSSSE3()) {
5264 SmallVector<SDValue,16> pshufbMask;
5266 // If all result elements are from one input vector, then only translate
5267 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5269 // Otherwise, we have elements from both input vectors, and must zero out
5270 // elements that come from V2 in the first mask, and V1 in the second mask
5271 // so that we can OR them together.
5272 bool TwoInputs = !(V1Only || V2Only);
5273 for (unsigned i = 0; i != 16; ++i) {
5274 int EltIdx = MaskVals[i];
5275 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5276 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5279 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5281 // If all the elements are from V2, assign it to V1 and return after
5282 // building the first pshufb.
5285 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5286 DAG.getNode(ISD::BUILD_VECTOR, dl,
5287 MVT::v16i8, &pshufbMask[0], 16));
5291 // Calculate the shuffle mask for the second input, shuffle it, and
5292 // OR it with the first shuffled input.
5294 for (unsigned i = 0; i != 16; ++i) {
5295 int EltIdx = MaskVals[i];
5297 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5300 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5302 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5303 DAG.getNode(ISD::BUILD_VECTOR, dl,
5304 MVT::v16i8, &pshufbMask[0], 16));
5305 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5308 // No SSSE3 - Calculate in place words and then fix all out of place words
5309 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5310 // the 16 different words that comprise the two doublequadword input vectors.
5311 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5312 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5313 SDValue NewV = V2Only ? V2 : V1;
5314 for (int i = 0; i != 8; ++i) {
5315 int Elt0 = MaskVals[i*2];
5316 int Elt1 = MaskVals[i*2+1];
5318 // This word of the result is all undef, skip it.
5319 if (Elt0 < 0 && Elt1 < 0)
5322 // This word of the result is already in the correct place, skip it.
5323 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5325 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5328 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5329 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5332 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5333 // using a single extract together, load it and store it.
5334 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5335 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5336 DAG.getIntPtrConstant(Elt1 / 2));
5337 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5338 DAG.getIntPtrConstant(i));
5342 // If Elt1 is defined, extract it from the appropriate source. If the
5343 // source byte is not also odd, shift the extracted word left 8 bits
5344 // otherwise clear the bottom 8 bits if we need to do an or.
5346 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5347 DAG.getIntPtrConstant(Elt1 / 2));
5348 if ((Elt1 & 1) == 0)
5349 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5351 TLI.getShiftAmountTy(InsElt.getValueType())));
5353 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5354 DAG.getConstant(0xFF00, MVT::i16));
5356 // If Elt0 is defined, extract it from the appropriate source. If the
5357 // source byte is not also even, shift the extracted word right 8 bits. If
5358 // Elt1 was also defined, OR the extracted values together before
5359 // inserting them in the result.
5361 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5362 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5363 if ((Elt0 & 1) != 0)
5364 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5366 TLI.getShiftAmountTy(InsElt0.getValueType())));
5368 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5369 DAG.getConstant(0x00FF, MVT::i16));
5370 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5373 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5374 DAG.getIntPtrConstant(i));
5376 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5379 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5380 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5381 /// done when every pair / quad of shuffle mask elements point to elements in
5382 /// the right sequence. e.g.
5383 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5385 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5386 SelectionDAG &DAG, DebugLoc dl) {
5387 EVT VT = SVOp->getValueType(0);
5388 SDValue V1 = SVOp->getOperand(0);
5389 SDValue V2 = SVOp->getOperand(1);
5390 unsigned NumElems = VT.getVectorNumElements();
5391 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5393 switch (VT.getSimpleVT().SimpleTy) {
5394 default: assert(false && "Unexpected!");
5395 case MVT::v4f32: NewVT = MVT::v2f64; break;
5396 case MVT::v4i32: NewVT = MVT::v2i64; break;
5397 case MVT::v8i16: NewVT = MVT::v4i32; break;
5398 case MVT::v16i8: NewVT = MVT::v4i32; break;
5401 int Scale = NumElems / NewWidth;
5402 SmallVector<int, 8> MaskVec;
5403 for (unsigned i = 0; i < NumElems; i += Scale) {
5405 for (int j = 0; j < Scale; ++j) {
5406 int EltIdx = SVOp->getMaskElt(i+j);
5410 StartIdx = EltIdx - (EltIdx % Scale);
5411 if (EltIdx != StartIdx + j)
5415 MaskVec.push_back(-1);
5417 MaskVec.push_back(StartIdx / Scale);
5420 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5421 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5422 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5425 /// getVZextMovL - Return a zero-extending vector move low node.
5427 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5428 SDValue SrcOp, SelectionDAG &DAG,
5429 const X86Subtarget *Subtarget, DebugLoc dl) {
5430 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5431 LoadSDNode *LD = NULL;
5432 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5433 LD = dyn_cast<LoadSDNode>(SrcOp);
5435 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5437 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5438 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5439 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5440 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5441 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5443 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5444 return DAG.getNode(ISD::BITCAST, dl, VT,
5445 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5446 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5454 return DAG.getNode(ISD::BITCAST, dl, VT,
5455 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5456 DAG.getNode(ISD::BITCAST, dl,
5460 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5461 /// which could not be matched by any known target speficic shuffle
5463 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5467 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5468 /// 4 elements, and match them with several different shuffle types.
5470 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5471 SDValue V1 = SVOp->getOperand(0);
5472 SDValue V2 = SVOp->getOperand(1);
5473 DebugLoc dl = SVOp->getDebugLoc();
5474 EVT VT = SVOp->getValueType(0);
5476 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
5478 SmallVector<std::pair<int, int>, 8> Locs;
5480 SmallVector<int, 8> Mask1(4U, -1);
5481 SmallVector<int, 8> PermMask;
5482 SVOp->getMask(PermMask);
5486 for (unsigned i = 0; i != 4; ++i) {
5487 int Idx = PermMask[i];
5489 Locs[i] = std::make_pair(-1, -1);
5491 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5493 Locs[i] = std::make_pair(0, NumLo);
5497 Locs[i] = std::make_pair(1, NumHi);
5499 Mask1[2+NumHi] = Idx;
5505 if (NumLo <= 2 && NumHi <= 2) {
5506 // If no more than two elements come from either vector. This can be
5507 // implemented with two shuffles. First shuffle gather the elements.
5508 // The second shuffle, which takes the first shuffle as both of its
5509 // vector operands, put the elements into the right order.
5510 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5512 SmallVector<int, 8> Mask2(4U, -1);
5514 for (unsigned i = 0; i != 4; ++i) {
5515 if (Locs[i].first == -1)
5518 unsigned Idx = (i < 2) ? 0 : 4;
5519 Idx += Locs[i].first * 2 + Locs[i].second;
5524 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
5525 } else if (NumLo == 3 || NumHi == 3) {
5526 // Otherwise, we must have three elements from one vector, call it X, and
5527 // one element from the other, call it Y. First, use a shufps to build an
5528 // intermediate vector with the one element from Y and the element from X
5529 // that will be in the same half in the final destination (the indexes don't
5530 // matter). Then, use a shufps to build the final vector, taking the half
5531 // containing the element from Y from the intermediate, and the other half
5534 // Normalize it so the 3 elements come from V1.
5535 CommuteVectorShuffleMask(PermMask, VT);
5539 // Find the element from V2.
5541 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5542 int Val = PermMask[HiIndex];
5549 Mask1[0] = PermMask[HiIndex];
5551 Mask1[2] = PermMask[HiIndex^1];
5553 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5556 Mask1[0] = PermMask[0];
5557 Mask1[1] = PermMask[1];
5558 Mask1[2] = HiIndex & 1 ? 6 : 4;
5559 Mask1[3] = HiIndex & 1 ? 4 : 6;
5560 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5562 Mask1[0] = HiIndex & 1 ? 2 : 0;
5563 Mask1[1] = HiIndex & 1 ? 0 : 2;
5564 Mask1[2] = PermMask[2];
5565 Mask1[3] = PermMask[3];
5570 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5574 // Break it into (shuffle shuffle_hi, shuffle_lo).
5577 SmallVector<int,8> LoMask(4U, -1);
5578 SmallVector<int,8> HiMask(4U, -1);
5580 SmallVector<int,8> *MaskPtr = &LoMask;
5581 unsigned MaskIdx = 0;
5584 for (unsigned i = 0; i != 4; ++i) {
5591 int Idx = PermMask[i];
5593 Locs[i] = std::make_pair(-1, -1);
5594 } else if (Idx < 4) {
5595 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5596 (*MaskPtr)[LoIdx] = Idx;
5599 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5600 (*MaskPtr)[HiIdx] = Idx;
5605 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5606 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5607 SmallVector<int, 8> MaskOps;
5608 for (unsigned i = 0; i != 4; ++i) {
5609 if (Locs[i].first == -1) {
5610 MaskOps.push_back(-1);
5612 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5613 MaskOps.push_back(Idx);
5616 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5619 static bool MayFoldVectorLoad(SDValue V) {
5620 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5621 V = V.getOperand(0);
5622 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5623 V = V.getOperand(0);
5629 // FIXME: the version above should always be used. Since there's
5630 // a bug where several vector shuffles can't be folded because the
5631 // DAG is not updated during lowering and a node claims to have two
5632 // uses while it only has one, use this version, and let isel match
5633 // another instruction if the load really happens to have more than
5634 // one use. Remove this version after this bug get fixed.
5635 // rdar://8434668, PR8156
5636 static bool RelaxedMayFoldVectorLoad(SDValue V) {
5637 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5638 V = V.getOperand(0);
5639 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5640 V = V.getOperand(0);
5641 if (ISD::isNormalLoad(V.getNode()))
5646 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
5647 /// a vector extract, and if both can be later optimized into a single load.
5648 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
5649 /// here because otherwise a target specific shuffle node is going to be
5650 /// emitted for this shuffle, and the optimization not done.
5651 /// FIXME: This is probably not the best approach, but fix the problem
5652 /// until the right path is decided.
5654 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
5655 const TargetLowering &TLI) {
5656 EVT VT = V.getValueType();
5657 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
5659 // Be sure that the vector shuffle is present in a pattern like this:
5660 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
5664 SDNode *N = *V.getNode()->use_begin();
5665 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5668 SDValue EltNo = N->getOperand(1);
5669 if (!isa<ConstantSDNode>(EltNo))
5672 // If the bit convert changed the number of elements, it is unsafe
5673 // to examine the mask.
5674 bool HasShuffleIntoBitcast = false;
5675 if (V.getOpcode() == ISD::BITCAST) {
5676 EVT SrcVT = V.getOperand(0).getValueType();
5677 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
5679 V = V.getOperand(0);
5680 HasShuffleIntoBitcast = true;
5683 // Select the input vector, guarding against out of range extract vector.
5684 unsigned NumElems = VT.getVectorNumElements();
5685 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5686 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
5687 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
5689 // Skip one more bit_convert if necessary
5690 if (V.getOpcode() == ISD::BITCAST)
5691 V = V.getOperand(0);
5693 if (ISD::isNormalLoad(V.getNode())) {
5694 // Is the original load suitable?
5695 LoadSDNode *LN0 = cast<LoadSDNode>(V);
5697 // FIXME: avoid the multi-use bug that is preventing lots of
5698 // of foldings to be detected, this is still wrong of course, but
5699 // give the temporary desired behavior, and if it happens that
5700 // the load has real more uses, during isel it will not fold, and
5701 // will generate poor code.
5702 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
5705 if (!HasShuffleIntoBitcast)
5708 // If there's a bitcast before the shuffle, check if the load type and
5709 // alignment is valid.
5710 unsigned Align = LN0->getAlignment();
5712 TLI.getTargetData()->getABITypeAlignment(
5713 VT.getTypeForEVT(*DAG.getContext()));
5715 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
5723 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
5724 EVT VT = Op.getValueType();
5726 // Canonizalize to v2f64.
5727 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
5728 return DAG.getNode(ISD::BITCAST, dl, VT,
5729 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
5734 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
5736 SDValue V1 = Op.getOperand(0);
5737 SDValue V2 = Op.getOperand(1);
5738 EVT VT = Op.getValueType();
5740 assert(VT != MVT::v2i64 && "unsupported shuffle type");
5742 if (HasSSE2 && VT == MVT::v2f64)
5743 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
5746 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
5750 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
5751 SDValue V1 = Op.getOperand(0);
5752 SDValue V2 = Op.getOperand(1);
5753 EVT VT = Op.getValueType();
5755 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
5756 "unsupported shuffle type");
5758 if (V2.getOpcode() == ISD::UNDEF)
5762 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
5766 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
5767 SDValue V1 = Op.getOperand(0);
5768 SDValue V2 = Op.getOperand(1);
5769 EVT VT = Op.getValueType();
5770 unsigned NumElems = VT.getVectorNumElements();
5772 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
5773 // operand of these instructions is only memory, so check if there's a
5774 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
5776 bool CanFoldLoad = false;
5778 // Trivial case, when V2 comes from a load.
5779 if (MayFoldVectorLoad(V2))
5782 // When V1 is a load, it can be folded later into a store in isel, example:
5783 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
5785 // (MOVLPSmr addr:$src1, VR128:$src2)
5786 // So, recognize this potential and also use MOVLPS or MOVLPD
5787 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
5790 // Both of them can't be memory operations though.
5791 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
5792 CanFoldLoad = false;
5795 if (HasSSE2 && NumElems == 2)
5796 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
5799 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
5802 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5803 // movl and movlp will both match v2i64, but v2i64 is never matched by
5804 // movl earlier because we make it strict to avoid messing with the movlp load
5805 // folding logic (see the code above getMOVLP call). Match it here then,
5806 // this is horrible, but will stay like this until we move all shuffle
5807 // matching to x86 specific nodes. Note that for the 1st condition all
5808 // types are matched with movsd.
5809 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
5810 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5812 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5815 assert(VT != MVT::v4i32 && "unsupported shuffle type");
5817 // Invert the operand order and use SHUFPS to match it.
5818 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
5819 X86::getShuffleSHUFImmediate(SVOp), DAG);
5822 static inline unsigned getUNPCKLOpcode(EVT VT) {
5823 switch(VT.getSimpleVT().SimpleTy) {
5824 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
5825 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
5826 case MVT::v4f32: return X86ISD::UNPCKLPS;
5827 case MVT::v2f64: return X86ISD::UNPCKLPD;
5828 case MVT::v8f32: return X86ISD::VUNPCKLPSY;
5829 case MVT::v4f64: return X86ISD::VUNPCKLPDY;
5830 case MVT::v16i8: return X86ISD::PUNPCKLBW;
5831 case MVT::v8i16: return X86ISD::PUNPCKLWD;
5833 llvm_unreachable("Unknown type for unpckl");
5838 static inline unsigned getUNPCKHOpcode(EVT VT) {
5839 switch(VT.getSimpleVT().SimpleTy) {
5840 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
5841 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
5842 case MVT::v4f32: return X86ISD::UNPCKHPS;
5843 case MVT::v2f64: return X86ISD::UNPCKHPD;
5844 case MVT::v8f32: return X86ISD::VUNPCKHPSY;
5845 case MVT::v4f64: return X86ISD::VUNPCKHPDY;
5846 case MVT::v16i8: return X86ISD::PUNPCKHBW;
5847 case MVT::v8i16: return X86ISD::PUNPCKHWD;
5849 llvm_unreachable("Unknown type for unpckh");
5854 static inline unsigned getVPERMILOpcode(EVT VT) {
5855 switch(VT.getSimpleVT().SimpleTy) {
5857 case MVT::v4f32: return X86ISD::VPERMILPS;
5859 case MVT::v2f64: return X86ISD::VPERMILPD;
5861 case MVT::v8f32: return X86ISD::VPERMILPSY;
5863 case MVT::v4f64: return X86ISD::VPERMILPDY;
5865 llvm_unreachable("Unknown type for vpermil");
5871 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
5872 const TargetLowering &TLI,
5873 const X86Subtarget *Subtarget) {
5874 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5875 EVT VT = Op.getValueType();
5876 DebugLoc dl = Op.getDebugLoc();
5877 SDValue V1 = Op.getOperand(0);
5878 SDValue V2 = Op.getOperand(1);
5880 if (isZeroShuffle(SVOp))
5881 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5883 // Handle splat operations
5884 if (SVOp->isSplat()) {
5885 unsigned NumElem = VT.getVectorNumElements();
5886 // Special case, this is the only place now where it's allowed to return
5887 // a vector_shuffle operation without using a target specific node, because
5888 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
5889 // this be moved to DAGCombine instead?
5890 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
5893 // Since there's no native support for scalar_to_vector for 256-bit AVX, a
5894 // 128-bit scalar_to_vector + INSERT_SUBVECTOR is generated. Recognize this
5895 // idiom and do the shuffle before the insertion, this yields less
5896 // instructions in the end.
5897 if (VT.is256BitVector() &&
5898 V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
5899 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
5900 V1.getOperand(1).getOpcode() == ISD::SCALAR_TO_VECTOR)
5901 return PromoteVectorToScalarSplat(SVOp, DAG);
5903 // Handle splats by matching through known shuffle masks
5904 if ((VT.is128BitVector() && NumElem <= 4) ||
5905 (VT.is256BitVector() && NumElem <= 8))
5908 // All i16 and i8 vector types can't be used directly by a generic shuffle
5909 // instruction because the target has no such instruction. Generate shuffles
5910 // which repeat i16 and i8 several times until they fit in i32, and then can
5911 // be manipulated by target suported shuffles. After the insertion of the
5912 // necessary shuffles, the result is bitcasted back to v4f32 or v8f32.
5913 return PromoteSplat(SVOp, DAG);
5916 // If the shuffle can be profitably rewritten as a narrower shuffle, then
5918 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
5919 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5920 if (NewOp.getNode())
5921 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
5922 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
5923 // FIXME: Figure out a cleaner way to do this.
5924 // Try to make use of movq to zero out the top part.
5925 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
5926 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5927 if (NewOp.getNode()) {
5928 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
5929 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
5930 DAG, Subtarget, dl);
5932 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
5933 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5934 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
5935 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
5936 DAG, Subtarget, dl);
5943 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
5944 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5945 SDValue V1 = Op.getOperand(0);
5946 SDValue V2 = Op.getOperand(1);
5947 EVT VT = Op.getValueType();
5948 DebugLoc dl = Op.getDebugLoc();
5949 unsigned NumElems = VT.getVectorNumElements();
5950 bool isMMX = VT.getSizeInBits() == 64;
5951 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
5952 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5953 bool V1IsSplat = false;
5954 bool V2IsSplat = false;
5955 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
5956 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
5957 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
5958 MachineFunction &MF = DAG.getMachineFunction();
5959 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
5961 // Shuffle operations on MMX not supported.
5965 // Vector shuffle lowering takes 3 steps:
5967 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
5968 // narrowing and commutation of operands should be handled.
5969 // 2) Matching of shuffles with known shuffle masks to x86 target specific
5971 // 3) Rewriting of unmatched masks into new generic shuffle operations,
5972 // so the shuffle can be broken into other shuffles and the legalizer can
5973 // try the lowering again.
5975 // The general ideia is that no vector_shuffle operation should be left to
5976 // be matched during isel, all of them must be converted to a target specific
5979 // Normalize the input vectors. Here splats, zeroed vectors, profitable
5980 // narrowing and commutation of operands should be handled. The actual code
5981 // doesn't include all of those, work in progress...
5982 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
5983 if (NewOp.getNode())
5986 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
5987 // unpckh_undef). Only use pshufd if speed is more important than size.
5988 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
5989 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5990 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
5991 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5993 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
5994 RelaxedMayFoldVectorLoad(V1))
5995 return getMOVDDup(Op, dl, V1, DAG);
5997 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
5998 return getMOVHighToLow(Op, dl, DAG);
6000 // Use to match splats
6001 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
6002 (VT == MVT::v2f64 || VT == MVT::v2i64))
6003 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6005 if (X86::isPSHUFDMask(SVOp)) {
6006 // The actual implementation will match the mask in the if above and then
6007 // during isel it can match several different instructions, not only pshufd
6008 // as its name says, sad but true, emulate the behavior for now...
6009 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6010 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6012 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6014 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6015 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6017 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6018 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
6021 if (VT == MVT::v4f32)
6022 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
6026 // Check if this can be converted into a logical shift.
6027 bool isLeft = false;
6030 bool isShift = getSubtarget()->hasSSE2() &&
6031 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6032 if (isShift && ShVal.hasOneUse()) {
6033 // If the shifted value has multiple uses, it may be cheaper to use
6034 // v_set0 + movlhps or movhlps, etc.
6035 EVT EltVT = VT.getVectorElementType();
6036 ShAmt *= EltVT.getSizeInBits();
6037 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6040 if (X86::isMOVLMask(SVOp)) {
6043 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6044 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6045 if (!X86::isMOVLPMask(SVOp)) {
6046 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6047 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6049 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6050 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6054 // FIXME: fold these into legal mask.
6055 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
6056 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6058 if (X86::isMOVHLPSMask(SVOp))
6059 return getMOVHighToLow(Op, dl, DAG);
6061 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6062 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6064 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6065 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6067 if (X86::isMOVLPMask(SVOp))
6068 return getMOVLP(Op, dl, DAG, HasSSE2);
6070 if (ShouldXformToMOVHLPS(SVOp) ||
6071 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6072 return CommuteVectorShuffle(SVOp, DAG);
6075 // No better options. Use a vshl / vsrl.
6076 EVT EltVT = VT.getVectorElementType();
6077 ShAmt *= EltVT.getSizeInBits();
6078 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6081 bool Commuted = false;
6082 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6083 // 1,1,1,1 -> v8i16 though.
6084 V1IsSplat = isSplatVector(V1.getNode());
6085 V2IsSplat = isSplatVector(V2.getNode());
6087 // Canonicalize the splat or undef, if present, to be on the RHS.
6088 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
6089 Op = CommuteVectorShuffle(SVOp, DAG);
6090 SVOp = cast<ShuffleVectorSDNode>(Op);
6091 V1 = SVOp->getOperand(0);
6092 V2 = SVOp->getOperand(1);
6093 std::swap(V1IsSplat, V2IsSplat);
6094 std::swap(V1IsUndef, V2IsUndef);
6098 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
6099 // Shuffling low element of v1 into undef, just return v1.
6102 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6103 // the instruction selector will not match, so get a canonical MOVL with
6104 // swapped operands to undo the commute.
6105 return getMOVL(DAG, dl, VT, V2, V1);
6108 if (X86::isUNPCKLMask(SVOp))
6109 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
6111 if (X86::isUNPCKHMask(SVOp))
6112 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
6115 // Normalize mask so all entries that point to V2 points to its first
6116 // element then try to match unpck{h|l} again. If match, return a
6117 // new vector_shuffle with the corrected mask.
6118 SDValue NewMask = NormalizeMask(SVOp, DAG);
6119 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6120 if (NSVOp != SVOp) {
6121 if (X86::isUNPCKLMask(NSVOp, true)) {
6123 } else if (X86::isUNPCKHMask(NSVOp, true)) {
6130 // Commute is back and try unpck* again.
6131 // FIXME: this seems wrong.
6132 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6133 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6135 if (X86::isUNPCKLMask(NewSVOp))
6136 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
6138 if (X86::isUNPCKHMask(NewSVOp))
6139 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
6142 // Normalize the node to match x86 shuffle ops if needed
6143 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
6144 return CommuteVectorShuffle(SVOp, DAG);
6146 // The checks below are all present in isShuffleMaskLegal, but they are
6147 // inlined here right now to enable us to directly emit target specific
6148 // nodes, and remove one by one until they don't return Op anymore.
6149 SmallVector<int, 16> M;
6152 if (isPALIGNRMask(M, VT, HasSSSE3))
6153 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6154 X86::getShufflePALIGNRImmediate(SVOp),
6157 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6158 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6159 if (VT == MVT::v2f64)
6160 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
6161 if (VT == MVT::v2i64)
6162 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
6165 if (isPSHUFHWMask(M, VT))
6166 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6167 X86::getShufflePSHUFHWImmediate(SVOp),
6170 if (isPSHUFLWMask(M, VT))
6171 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6172 X86::getShufflePSHUFLWImmediate(SVOp),
6175 if (isSHUFPMask(M, VT)) {
6176 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6177 if (VT == MVT::v4f32 || VT == MVT::v4i32)
6178 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
6180 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6181 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
6185 if (X86::isUNPCKL_v_undef_Mask(SVOp))
6186 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6187 if (X86::isUNPCKH_v_undef_Mask(SVOp))
6188 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6190 //===--------------------------------------------------------------------===//
6191 // Generate target specific nodes for 128 or 256-bit shuffles only
6192 // supported in the AVX instruction set.
6195 // Handle VPERMILPS* permutations
6196 if (isVPERMILPSMask(M, VT, Subtarget))
6197 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6198 getShuffleVPERMILPSImmediate(SVOp), DAG);
6200 // Handle VPERMILPD* permutations
6201 if (isVPERMILPDMask(M, VT, Subtarget))
6202 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6203 getShuffleVPERMILPDImmediate(SVOp), DAG);
6205 //===--------------------------------------------------------------------===//
6206 // Since no target specific shuffle was selected for this generic one,
6207 // lower it into other known shuffles. FIXME: this isn't true yet, but
6208 // this is the plan.
6211 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6212 if (VT == MVT::v8i16) {
6213 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6214 if (NewOp.getNode())
6218 if (VT == MVT::v16i8) {
6219 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6220 if (NewOp.getNode())
6224 // Handle all 128-bit wide vectors with 4 elements, and match them with
6225 // several different shuffle types.
6226 if (NumElems == 4 && VT.getSizeInBits() == 128)
6227 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6229 // Handle general 256-bit shuffles
6230 if (VT.is256BitVector())
6231 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6237 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6238 SelectionDAG &DAG) const {
6239 EVT VT = Op.getValueType();
6240 DebugLoc dl = Op.getDebugLoc();
6241 if (VT.getSizeInBits() == 8) {
6242 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6243 Op.getOperand(0), Op.getOperand(1));
6244 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6245 DAG.getValueType(VT));
6246 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6247 } else if (VT.getSizeInBits() == 16) {
6248 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6249 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6251 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6252 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6253 DAG.getNode(ISD::BITCAST, dl,
6257 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6258 Op.getOperand(0), Op.getOperand(1));
6259 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6260 DAG.getValueType(VT));
6261 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6262 } else if (VT == MVT::f32) {
6263 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6264 // the result back to FR32 register. It's only worth matching if the
6265 // result has a single use which is a store or a bitcast to i32. And in
6266 // the case of a store, it's not worth it if the index is a constant 0,
6267 // because a MOVSSmr can be used instead, which is smaller and faster.
6268 if (!Op.hasOneUse())
6270 SDNode *User = *Op.getNode()->use_begin();
6271 if ((User->getOpcode() != ISD::STORE ||
6272 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6273 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6274 (User->getOpcode() != ISD::BITCAST ||
6275 User->getValueType(0) != MVT::i32))
6277 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6278 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6281 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6282 } else if (VT == MVT::i32) {
6283 // ExtractPS works with constant index.
6284 if (isa<ConstantSDNode>(Op.getOperand(1)))
6292 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6293 SelectionDAG &DAG) const {
6294 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6297 SDValue Vec = Op.getOperand(0);
6298 EVT VecVT = Vec.getValueType();
6300 // If this is a 256-bit vector result, first extract the 128-bit
6301 // vector and then extract from the 128-bit vector.
6302 if (VecVT.getSizeInBits() > 128) {
6303 DebugLoc dl = Op.getNode()->getDebugLoc();
6304 unsigned NumElems = VecVT.getVectorNumElements();
6305 SDValue Idx = Op.getOperand(1);
6307 if (!isa<ConstantSDNode>(Idx))
6310 unsigned ExtractNumElems = NumElems / (VecVT.getSizeInBits() / 128);
6311 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6313 // Get the 128-bit vector.
6314 bool Upper = IdxVal >= ExtractNumElems;
6315 Vec = Extract128BitVector(Vec, Idx, DAG, dl);
6318 SDValue ScaledIdx = Idx;
6320 ScaledIdx = DAG.getNode(ISD::SUB, dl, Idx.getValueType(), Idx,
6321 DAG.getConstant(ExtractNumElems,
6322 Idx.getValueType()));
6323 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6327 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6329 if (Subtarget->hasSSE41()) {
6330 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6335 EVT VT = Op.getValueType();
6336 DebugLoc dl = Op.getDebugLoc();
6337 // TODO: handle v16i8.
6338 if (VT.getSizeInBits() == 16) {
6339 SDValue Vec = Op.getOperand(0);
6340 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6342 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6343 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6344 DAG.getNode(ISD::BITCAST, dl,
6347 // Transform it so it match pextrw which produces a 32-bit result.
6348 EVT EltVT = MVT::i32;
6349 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6350 Op.getOperand(0), Op.getOperand(1));
6351 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6352 DAG.getValueType(VT));
6353 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6354 } else if (VT.getSizeInBits() == 32) {
6355 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6359 // SHUFPS the element to the lowest double word, then movss.
6360 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6361 EVT VVT = Op.getOperand(0).getValueType();
6362 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6363 DAG.getUNDEF(VVT), Mask);
6364 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6365 DAG.getIntPtrConstant(0));
6366 } else if (VT.getSizeInBits() == 64) {
6367 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6368 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6369 // to match extract_elt for f64.
6370 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6374 // UNPCKHPD the element to the lowest double word, then movsd.
6375 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6376 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6377 int Mask[2] = { 1, -1 };
6378 EVT VVT = Op.getOperand(0).getValueType();
6379 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6380 DAG.getUNDEF(VVT), Mask);
6381 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6382 DAG.getIntPtrConstant(0));
6389 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6390 SelectionDAG &DAG) const {
6391 EVT VT = Op.getValueType();
6392 EVT EltVT = VT.getVectorElementType();
6393 DebugLoc dl = Op.getDebugLoc();
6395 SDValue N0 = Op.getOperand(0);
6396 SDValue N1 = Op.getOperand(1);
6397 SDValue N2 = Op.getOperand(2);
6399 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6400 isa<ConstantSDNode>(N2)) {
6402 if (VT == MVT::v8i16)
6403 Opc = X86ISD::PINSRW;
6404 else if (VT == MVT::v16i8)
6405 Opc = X86ISD::PINSRB;
6407 Opc = X86ISD::PINSRB;
6409 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6411 if (N1.getValueType() != MVT::i32)
6412 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6413 if (N2.getValueType() != MVT::i32)
6414 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6415 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6416 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6417 // Bits [7:6] of the constant are the source select. This will always be
6418 // zero here. The DAG Combiner may combine an extract_elt index into these
6419 // bits. For example (insert (extract, 3), 2) could be matched by putting
6420 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6421 // Bits [5:4] of the constant are the destination select. This is the
6422 // value of the incoming immediate.
6423 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6424 // combine either bitwise AND or insert of float 0.0 to set these bits.
6425 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6426 // Create this as a scalar to vector..
6427 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6428 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6429 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
6430 // PINSR* works with constant index.
6437 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6438 EVT VT = Op.getValueType();
6439 EVT EltVT = VT.getVectorElementType();
6441 DebugLoc dl = Op.getDebugLoc();
6442 SDValue N0 = Op.getOperand(0);
6443 SDValue N1 = Op.getOperand(1);
6444 SDValue N2 = Op.getOperand(2);
6446 // If this is a 256-bit vector result, first insert into a 128-bit
6447 // vector and then insert into the 256-bit vector.
6448 if (VT.getSizeInBits() > 128) {
6449 if (!isa<ConstantSDNode>(N2))
6452 // Get the 128-bit vector.
6453 unsigned NumElems = VT.getVectorNumElements();
6454 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6455 bool Upper = IdxVal >= NumElems / 2;
6457 SDValue SubN0 = Extract128BitVector(N0, N2, DAG, dl);
6460 SDValue ScaledN2 = N2;
6462 ScaledN2 = DAG.getNode(ISD::SUB, dl, N2.getValueType(), N2,
6463 DAG.getConstant(NumElems /
6464 (VT.getSizeInBits() / 128),
6465 N2.getValueType()));
6466 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubN0.getValueType(), SubN0,
6469 // Insert the 128-bit vector
6470 // FIXME: Why UNDEF?
6471 return Insert128BitVector(N0, Op, N2, DAG, dl);
6474 if (Subtarget->hasSSE41())
6475 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6477 if (EltVT == MVT::i8)
6480 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6481 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6482 // as its second argument.
6483 if (N1.getValueType() != MVT::i32)
6484 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6485 if (N2.getValueType() != MVT::i32)
6486 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6487 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6493 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6494 LLVMContext *Context = DAG.getContext();
6495 DebugLoc dl = Op.getDebugLoc();
6496 EVT OpVT = Op.getValueType();
6498 // If this is a 256-bit vector result, first insert into a 128-bit
6499 // vector and then insert into the 256-bit vector.
6500 if (OpVT.getSizeInBits() > 128) {
6501 // Insert into a 128-bit vector.
6502 EVT VT128 = EVT::getVectorVT(*Context,
6503 OpVT.getVectorElementType(),
6504 OpVT.getVectorNumElements() / 2);
6506 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6508 // Insert the 128-bit vector.
6509 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6510 DAG.getConstant(0, MVT::i32),
6514 if (Op.getValueType() == MVT::v1i64 &&
6515 Op.getOperand(0).getValueType() == MVT::i64)
6516 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6518 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6519 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6520 "Expected an SSE type!");
6521 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6522 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6525 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6526 // a simple subregister reference or explicit instructions to grab
6527 // upper bits of a vector.
6529 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6530 if (Subtarget->hasAVX()) {
6531 DebugLoc dl = Op.getNode()->getDebugLoc();
6532 SDValue Vec = Op.getNode()->getOperand(0);
6533 SDValue Idx = Op.getNode()->getOperand(1);
6535 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
6536 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
6537 return Extract128BitVector(Vec, Idx, DAG, dl);
6543 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6544 // simple superregister reference or explicit instructions to insert
6545 // the upper bits of a vector.
6547 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6548 if (Subtarget->hasAVX()) {
6549 DebugLoc dl = Op.getNode()->getDebugLoc();
6550 SDValue Vec = Op.getNode()->getOperand(0);
6551 SDValue SubVec = Op.getNode()->getOperand(1);
6552 SDValue Idx = Op.getNode()->getOperand(2);
6554 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
6555 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
6556 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
6562 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
6563 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
6564 // one of the above mentioned nodes. It has to be wrapped because otherwise
6565 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
6566 // be used to form addressing mode. These wrapped nodes will be selected
6569 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
6570 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
6572 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6574 unsigned char OpFlag = 0;
6575 unsigned WrapperKind = X86ISD::Wrapper;
6576 CodeModel::Model M = getTargetMachine().getCodeModel();
6578 if (Subtarget->isPICStyleRIPRel() &&
6579 (M == CodeModel::Small || M == CodeModel::Kernel))
6580 WrapperKind = X86ISD::WrapperRIP;
6581 else if (Subtarget->isPICStyleGOT())
6582 OpFlag = X86II::MO_GOTOFF;
6583 else if (Subtarget->isPICStyleStubPIC())
6584 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6586 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
6588 CP->getOffset(), OpFlag);
6589 DebugLoc DL = CP->getDebugLoc();
6590 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6591 // With PIC, the address is actually $g + Offset.
6593 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6594 DAG.getNode(X86ISD::GlobalBaseReg,
6595 DebugLoc(), getPointerTy()),
6602 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
6603 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
6605 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6607 unsigned char OpFlag = 0;
6608 unsigned WrapperKind = X86ISD::Wrapper;
6609 CodeModel::Model M = getTargetMachine().getCodeModel();
6611 if (Subtarget->isPICStyleRIPRel() &&
6612 (M == CodeModel::Small || M == CodeModel::Kernel))
6613 WrapperKind = X86ISD::WrapperRIP;
6614 else if (Subtarget->isPICStyleGOT())
6615 OpFlag = X86II::MO_GOTOFF;
6616 else if (Subtarget->isPICStyleStubPIC())
6617 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6619 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
6621 DebugLoc DL = JT->getDebugLoc();
6622 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6624 // With PIC, the address is actually $g + Offset.
6626 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6627 DAG.getNode(X86ISD::GlobalBaseReg,
6628 DebugLoc(), getPointerTy()),
6635 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
6636 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
6638 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6640 unsigned char OpFlag = 0;
6641 unsigned WrapperKind = X86ISD::Wrapper;
6642 CodeModel::Model M = getTargetMachine().getCodeModel();
6644 if (Subtarget->isPICStyleRIPRel() &&
6645 (M == CodeModel::Small || M == CodeModel::Kernel))
6646 WrapperKind = X86ISD::WrapperRIP;
6647 else if (Subtarget->isPICStyleGOT())
6648 OpFlag = X86II::MO_GOTOFF;
6649 else if (Subtarget->isPICStyleStubPIC())
6650 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6652 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
6654 DebugLoc DL = Op.getDebugLoc();
6655 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6658 // With PIC, the address is actually $g + Offset.
6659 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
6660 !Subtarget->is64Bit()) {
6661 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6662 DAG.getNode(X86ISD::GlobalBaseReg,
6663 DebugLoc(), getPointerTy()),
6671 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
6672 // Create the TargetBlockAddressAddress node.
6673 unsigned char OpFlags =
6674 Subtarget->ClassifyBlockAddressReference();
6675 CodeModel::Model M = getTargetMachine().getCodeModel();
6676 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
6677 DebugLoc dl = Op.getDebugLoc();
6678 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
6679 /*isTarget=*/true, OpFlags);
6681 if (Subtarget->isPICStyleRIPRel() &&
6682 (M == CodeModel::Small || M == CodeModel::Kernel))
6683 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
6685 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
6687 // With PIC, the address is actually $g + Offset.
6688 if (isGlobalRelativeToPICBase(OpFlags)) {
6689 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6690 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
6698 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
6700 SelectionDAG &DAG) const {
6701 // Create the TargetGlobalAddress node, folding in the constant
6702 // offset if it is legal.
6703 unsigned char OpFlags =
6704 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
6705 CodeModel::Model M = getTargetMachine().getCodeModel();
6707 if (OpFlags == X86II::MO_NO_FLAG &&
6708 X86::isOffsetSuitableForCodeModel(Offset, M)) {
6709 // A direct static reference to a global.
6710 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
6713 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
6716 if (Subtarget->isPICStyleRIPRel() &&
6717 (M == CodeModel::Small || M == CodeModel::Kernel))
6718 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
6720 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
6722 // With PIC, the address is actually $g + Offset.
6723 if (isGlobalRelativeToPICBase(OpFlags)) {
6724 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6725 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
6729 // For globals that require a load from a stub to get the address, emit the
6731 if (isGlobalStubReference(OpFlags))
6732 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
6733 MachinePointerInfo::getGOT(), false, false, 0);
6735 // If there was a non-zero offset that we didn't fold, create an explicit
6738 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
6739 DAG.getConstant(Offset, getPointerTy()));
6745 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
6746 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
6747 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
6748 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
6752 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
6753 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
6754 unsigned char OperandFlags) {
6755 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6756 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6757 DebugLoc dl = GA->getDebugLoc();
6758 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6759 GA->getValueType(0),
6763 SDValue Ops[] = { Chain, TGA, *InFlag };
6764 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
6766 SDValue Ops[] = { Chain, TGA };
6767 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
6770 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
6771 MFI->setAdjustsStack(true);
6773 SDValue Flag = Chain.getValue(1);
6774 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
6777 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
6779 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6782 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
6783 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
6784 DAG.getNode(X86ISD::GlobalBaseReg,
6785 DebugLoc(), PtrVT), InFlag);
6786 InFlag = Chain.getValue(1);
6788 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
6791 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
6793 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6795 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
6796 X86::RAX, X86II::MO_TLSGD);
6799 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
6800 // "local exec" model.
6801 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6802 const EVT PtrVT, TLSModel::Model model,
6804 DebugLoc dl = GA->getDebugLoc();
6806 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
6807 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
6808 is64Bit ? 257 : 256));
6810 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
6811 DAG.getIntPtrConstant(0),
6812 MachinePointerInfo(Ptr), false, false, 0);
6814 unsigned char OperandFlags = 0;
6815 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
6817 unsigned WrapperKind = X86ISD::Wrapper;
6818 if (model == TLSModel::LocalExec) {
6819 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
6820 } else if (is64Bit) {
6821 assert(model == TLSModel::InitialExec);
6822 OperandFlags = X86II::MO_GOTTPOFF;
6823 WrapperKind = X86ISD::WrapperRIP;
6825 assert(model == TLSModel::InitialExec);
6826 OperandFlags = X86II::MO_INDNTPOFF;
6829 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
6831 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6832 GA->getValueType(0),
6833 GA->getOffset(), OperandFlags);
6834 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
6836 if (model == TLSModel::InitialExec)
6837 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
6838 MachinePointerInfo::getGOT(), false, false, 0);
6840 // The address of the thread local variable is the add of the thread
6841 // pointer with the offset of the variable.
6842 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
6846 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
6848 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6849 const GlobalValue *GV = GA->getGlobal();
6851 if (Subtarget->isTargetELF()) {
6852 // TODO: implement the "local dynamic" model
6853 // TODO: implement the "initial exec"model for pic executables
6855 // If GV is an alias then use the aliasee for determining
6856 // thread-localness.
6857 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
6858 GV = GA->resolveAliasedGlobal(false);
6860 TLSModel::Model model
6861 = getTLSModel(GV, getTargetMachine().getRelocationModel());
6864 case TLSModel::GeneralDynamic:
6865 case TLSModel::LocalDynamic: // not implemented
6866 if (Subtarget->is64Bit())
6867 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
6868 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
6870 case TLSModel::InitialExec:
6871 case TLSModel::LocalExec:
6872 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
6873 Subtarget->is64Bit());
6875 } else if (Subtarget->isTargetDarwin()) {
6876 // Darwin only has one model of TLS. Lower to that.
6877 unsigned char OpFlag = 0;
6878 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
6879 X86ISD::WrapperRIP : X86ISD::Wrapper;
6881 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6883 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
6884 !Subtarget->is64Bit();
6886 OpFlag = X86II::MO_TLVP_PIC_BASE;
6888 OpFlag = X86II::MO_TLVP;
6889 DebugLoc DL = Op.getDebugLoc();
6890 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
6891 GA->getValueType(0),
6892 GA->getOffset(), OpFlag);
6893 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6895 // With PIC32, the address is actually $g + Offset.
6897 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6898 DAG.getNode(X86ISD::GlobalBaseReg,
6899 DebugLoc(), getPointerTy()),
6902 // Lowering the machine isd will make sure everything is in the right
6904 SDValue Chain = DAG.getEntryNode();
6905 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6906 SDValue Args[] = { Chain, Offset };
6907 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
6909 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
6910 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6911 MFI->setAdjustsStack(true);
6913 // And our return value (tls address) is in the standard call return value
6915 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
6916 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
6920 "TLS not implemented for this target.");
6922 llvm_unreachable("Unreachable");
6927 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
6928 /// take a 2 x i32 value to shift plus a shift amount.
6929 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
6930 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
6931 EVT VT = Op.getValueType();
6932 unsigned VTBits = VT.getSizeInBits();
6933 DebugLoc dl = Op.getDebugLoc();
6934 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
6935 SDValue ShOpLo = Op.getOperand(0);
6936 SDValue ShOpHi = Op.getOperand(1);
6937 SDValue ShAmt = Op.getOperand(2);
6938 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
6939 DAG.getConstant(VTBits - 1, MVT::i8))
6940 : DAG.getConstant(0, VT);
6943 if (Op.getOpcode() == ISD::SHL_PARTS) {
6944 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
6945 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6947 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
6948 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
6951 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
6952 DAG.getConstant(VTBits, MVT::i8));
6953 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6954 AndNode, DAG.getConstant(0, MVT::i8));
6957 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6958 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
6959 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
6961 if (Op.getOpcode() == ISD::SHL_PARTS) {
6962 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6963 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6965 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6966 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6969 SDValue Ops[2] = { Lo, Hi };
6970 return DAG.getMergeValues(Ops, 2, dl);
6973 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
6974 SelectionDAG &DAG) const {
6975 EVT SrcVT = Op.getOperand(0).getValueType();
6977 if (SrcVT.isVector())
6980 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
6981 "Unknown SINT_TO_FP to lower!");
6983 // These are really Legal; return the operand so the caller accepts it as
6985 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
6987 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
6988 Subtarget->is64Bit()) {
6992 DebugLoc dl = Op.getDebugLoc();
6993 unsigned Size = SrcVT.getSizeInBits()/8;
6994 MachineFunction &MF = DAG.getMachineFunction();
6995 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
6996 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6997 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6999 MachinePointerInfo::getFixedStack(SSFI),
7001 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7004 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7006 SelectionDAG &DAG) const {
7008 DebugLoc DL = Op.getDebugLoc();
7010 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7012 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7014 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7016 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7018 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7019 MachineMemOperand *MMO;
7021 int SSFI = FI->getIndex();
7023 DAG.getMachineFunction()
7024 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7025 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7027 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7028 StackSlot = StackSlot.getOperand(1);
7030 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7031 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7033 Tys, Ops, array_lengthof(Ops),
7037 Chain = Result.getValue(1);
7038 SDValue InFlag = Result.getValue(2);
7040 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7041 // shouldn't be necessary except that RFP cannot be live across
7042 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7043 MachineFunction &MF = DAG.getMachineFunction();
7044 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7045 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7046 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7047 Tys = DAG.getVTList(MVT::Other);
7049 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7051 MachineMemOperand *MMO =
7052 DAG.getMachineFunction()
7053 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7054 MachineMemOperand::MOStore, SSFISize, SSFISize);
7056 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7057 Ops, array_lengthof(Ops),
7058 Op.getValueType(), MMO);
7059 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7060 MachinePointerInfo::getFixedStack(SSFI),
7067 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7068 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7069 SelectionDAG &DAG) const {
7070 // This algorithm is not obvious. Here it is in C code, more or less:
7072 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7073 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7074 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7076 // Copy ints to xmm registers.
7077 __m128i xh = _mm_cvtsi32_si128( hi );
7078 __m128i xl = _mm_cvtsi32_si128( lo );
7080 // Combine into low half of a single xmm register.
7081 __m128i x = _mm_unpacklo_epi32( xh, xl );
7085 // Merge in appropriate exponents to give the integer bits the right
7087 x = _mm_unpacklo_epi32( x, exp );
7089 // Subtract away the biases to deal with the IEEE-754 double precision
7091 d = _mm_sub_pd( (__m128d) x, bias );
7093 // All conversions up to here are exact. The correctly rounded result is
7094 // calculated using the current rounding mode using the following
7096 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7097 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7098 // store doesn't really need to be here (except
7099 // maybe to zero the other double)
7104 DebugLoc dl = Op.getDebugLoc();
7105 LLVMContext *Context = DAG.getContext();
7107 // Build some magic constants.
7108 std::vector<Constant*> CV0;
7109 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7110 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7111 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7112 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7113 Constant *C0 = ConstantVector::get(CV0);
7114 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7116 std::vector<Constant*> CV1;
7118 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7120 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7121 Constant *C1 = ConstantVector::get(CV1);
7122 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7124 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7125 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7127 DAG.getIntPtrConstant(1)));
7128 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7129 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7131 DAG.getIntPtrConstant(0)));
7132 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7133 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7134 MachinePointerInfo::getConstantPool(),
7136 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7137 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7138 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7139 MachinePointerInfo::getConstantPool(),
7141 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7143 // Add the halves; easiest way is to swap them into another reg first.
7144 int ShufMask[2] = { 1, -1 };
7145 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7146 DAG.getUNDEF(MVT::v2f64), ShufMask);
7147 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7148 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7149 DAG.getIntPtrConstant(0));
7152 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7153 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7154 SelectionDAG &DAG) const {
7155 DebugLoc dl = Op.getDebugLoc();
7156 // FP constant to bias correct the final result.
7157 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7160 // Load the 32-bit value into an XMM register.
7161 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7162 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7164 DAG.getIntPtrConstant(0)));
7166 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7167 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7168 DAG.getIntPtrConstant(0));
7170 // Or the load with the bias.
7171 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7172 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7173 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7175 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7176 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7177 MVT::v2f64, Bias)));
7178 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7179 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7180 DAG.getIntPtrConstant(0));
7182 // Subtract the bias.
7183 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7185 // Handle final rounding.
7186 EVT DestVT = Op.getValueType();
7188 if (DestVT.bitsLT(MVT::f64)) {
7189 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7190 DAG.getIntPtrConstant(0));
7191 } else if (DestVT.bitsGT(MVT::f64)) {
7192 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7195 // Handle final rounding.
7199 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7200 SelectionDAG &DAG) const {
7201 SDValue N0 = Op.getOperand(0);
7202 DebugLoc dl = Op.getDebugLoc();
7204 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7205 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7206 // the optimization here.
7207 if (DAG.SignBitIsZero(N0))
7208 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7210 EVT SrcVT = N0.getValueType();
7211 EVT DstVT = Op.getValueType();
7212 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7213 return LowerUINT_TO_FP_i64(Op, DAG);
7214 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7215 return LowerUINT_TO_FP_i32(Op, DAG);
7217 // Make a 64-bit buffer, and use it to build an FILD.
7218 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7219 if (SrcVT == MVT::i32) {
7220 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7221 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7222 getPointerTy(), StackSlot, WordOff);
7223 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7224 StackSlot, MachinePointerInfo(),
7226 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7227 OffsetSlot, MachinePointerInfo(),
7229 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7233 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7234 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7235 StackSlot, MachinePointerInfo(),
7237 // For i64 source, we need to add the appropriate power of 2 if the input
7238 // was negative. This is the same as the optimization in
7239 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7240 // we must be careful to do the computation in x87 extended precision, not
7241 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7242 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7243 MachineMemOperand *MMO =
7244 DAG.getMachineFunction()
7245 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7246 MachineMemOperand::MOLoad, 8, 8);
7248 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7249 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7250 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7253 APInt FF(32, 0x5F800000ULL);
7255 // Check whether the sign bit is set.
7256 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7257 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7260 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7261 SDValue FudgePtr = DAG.getConstantPool(
7262 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7265 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7266 SDValue Zero = DAG.getIntPtrConstant(0);
7267 SDValue Four = DAG.getIntPtrConstant(4);
7268 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7270 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7272 // Load the value out, extending it from f32 to f80.
7273 // FIXME: Avoid the extend by constructing the right constant pool?
7274 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7275 FudgePtr, MachinePointerInfo::getConstantPool(),
7276 MVT::f32, false, false, 4);
7277 // Extend everything to 80 bits to force it to be done on x87.
7278 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7279 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7282 std::pair<SDValue,SDValue> X86TargetLowering::
7283 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7284 DebugLoc DL = Op.getDebugLoc();
7286 EVT DstTy = Op.getValueType();
7289 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7293 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7294 DstTy.getSimpleVT() >= MVT::i16 &&
7295 "Unknown FP_TO_SINT to lower!");
7297 // These are really Legal.
7298 if (DstTy == MVT::i32 &&
7299 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7300 return std::make_pair(SDValue(), SDValue());
7301 if (Subtarget->is64Bit() &&
7302 DstTy == MVT::i64 &&
7303 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7304 return std::make_pair(SDValue(), SDValue());
7306 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7308 MachineFunction &MF = DAG.getMachineFunction();
7309 unsigned MemSize = DstTy.getSizeInBits()/8;
7310 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7311 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7316 switch (DstTy.getSimpleVT().SimpleTy) {
7317 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7318 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7319 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7320 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7323 SDValue Chain = DAG.getEntryNode();
7324 SDValue Value = Op.getOperand(0);
7325 EVT TheVT = Op.getOperand(0).getValueType();
7326 if (isScalarFPTypeInSSEReg(TheVT)) {
7327 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7328 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7329 MachinePointerInfo::getFixedStack(SSFI),
7331 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7333 Chain, StackSlot, DAG.getValueType(TheVT)
7336 MachineMemOperand *MMO =
7337 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7338 MachineMemOperand::MOLoad, MemSize, MemSize);
7339 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7341 Chain = Value.getValue(1);
7342 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7343 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7346 MachineMemOperand *MMO =
7347 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7348 MachineMemOperand::MOStore, MemSize, MemSize);
7350 // Build the FP_TO_INT*_IN_MEM
7351 SDValue Ops[] = { Chain, Value, StackSlot };
7352 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7353 Ops, 3, DstTy, MMO);
7355 return std::make_pair(FIST, StackSlot);
7358 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7359 SelectionDAG &DAG) const {
7360 if (Op.getValueType().isVector())
7363 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7364 SDValue FIST = Vals.first, StackSlot = Vals.second;
7365 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7366 if (FIST.getNode() == 0) return Op;
7369 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7370 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7373 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7374 SelectionDAG &DAG) const {
7375 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7376 SDValue FIST = Vals.first, StackSlot = Vals.second;
7377 assert(FIST.getNode() && "Unexpected failure");
7380 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7381 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7384 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7385 SelectionDAG &DAG) const {
7386 LLVMContext *Context = DAG.getContext();
7387 DebugLoc dl = Op.getDebugLoc();
7388 EVT VT = Op.getValueType();
7391 EltVT = VT.getVectorElementType();
7392 std::vector<Constant*> CV;
7393 if (EltVT == MVT::f64) {
7394 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7398 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7404 Constant *C = ConstantVector::get(CV);
7405 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7406 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7407 MachinePointerInfo::getConstantPool(),
7409 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7412 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7413 LLVMContext *Context = DAG.getContext();
7414 DebugLoc dl = Op.getDebugLoc();
7415 EVT VT = Op.getValueType();
7418 EltVT = VT.getVectorElementType();
7419 std::vector<Constant*> CV;
7420 if (EltVT == MVT::f64) {
7421 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7425 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7431 Constant *C = ConstantVector::get(CV);
7432 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7433 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7434 MachinePointerInfo::getConstantPool(),
7436 if (VT.isVector()) {
7437 return DAG.getNode(ISD::BITCAST, dl, VT,
7438 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
7439 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7441 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
7443 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7447 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7448 LLVMContext *Context = DAG.getContext();
7449 SDValue Op0 = Op.getOperand(0);
7450 SDValue Op1 = Op.getOperand(1);
7451 DebugLoc dl = Op.getDebugLoc();
7452 EVT VT = Op.getValueType();
7453 EVT SrcVT = Op1.getValueType();
7455 // If second operand is smaller, extend it first.
7456 if (SrcVT.bitsLT(VT)) {
7457 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7460 // And if it is bigger, shrink it first.
7461 if (SrcVT.bitsGT(VT)) {
7462 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7466 // At this point the operands and the result should have the same
7467 // type, and that won't be f80 since that is not custom lowered.
7469 // First get the sign bit of second operand.
7470 std::vector<Constant*> CV;
7471 if (SrcVT == MVT::f64) {
7472 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7473 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7475 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7476 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7477 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7478 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7480 Constant *C = ConstantVector::get(CV);
7481 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7482 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7483 MachinePointerInfo::getConstantPool(),
7485 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7487 // Shift sign bit right or left if the two operands have different types.
7488 if (SrcVT.bitsGT(VT)) {
7489 // Op0 is MVT::f32, Op1 is MVT::f64.
7490 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7491 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7492 DAG.getConstant(32, MVT::i32));
7493 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7494 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7495 DAG.getIntPtrConstant(0));
7498 // Clear first operand sign bit.
7500 if (VT == MVT::f64) {
7501 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7502 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7504 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7505 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7506 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7507 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7509 C = ConstantVector::get(CV);
7510 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7511 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7512 MachinePointerInfo::getConstantPool(),
7514 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7516 // Or the value with the sign bit.
7517 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
7520 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
7521 SDValue N0 = Op.getOperand(0);
7522 DebugLoc dl = Op.getDebugLoc();
7523 EVT VT = Op.getValueType();
7525 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
7526 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
7527 DAG.getConstant(1, VT));
7528 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
7531 /// Emit nodes that will be selected as "test Op0,Op0", or something
7533 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
7534 SelectionDAG &DAG) const {
7535 DebugLoc dl = Op.getDebugLoc();
7537 // CF and OF aren't always set the way we want. Determine which
7538 // of these we need.
7539 bool NeedCF = false;
7540 bool NeedOF = false;
7543 case X86::COND_A: case X86::COND_AE:
7544 case X86::COND_B: case X86::COND_BE:
7547 case X86::COND_G: case X86::COND_GE:
7548 case X86::COND_L: case X86::COND_LE:
7549 case X86::COND_O: case X86::COND_NO:
7554 // See if we can use the EFLAGS value from the operand instead of
7555 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
7556 // we prove that the arithmetic won't overflow, we can't use OF or CF.
7557 if (Op.getResNo() != 0 || NeedOF || NeedCF)
7558 // Emit a CMP with 0, which is the TEST pattern.
7559 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
7560 DAG.getConstant(0, Op.getValueType()));
7562 unsigned Opcode = 0;
7563 unsigned NumOperands = 0;
7564 switch (Op.getNode()->getOpcode()) {
7566 // Due to an isel shortcoming, be conservative if this add is likely to be
7567 // selected as part of a load-modify-store instruction. When the root node
7568 // in a match is a store, isel doesn't know how to remap non-chain non-flag
7569 // uses of other nodes in the match, such as the ADD in this case. This
7570 // leads to the ADD being left around and reselected, with the result being
7571 // two adds in the output. Alas, even if none our users are stores, that
7572 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
7573 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
7574 // climbing the DAG back to the root, and it doesn't seem to be worth the
7576 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7577 UE = Op.getNode()->use_end(); UI != UE; ++UI)
7578 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
7581 if (ConstantSDNode *C =
7582 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
7583 // An add of one will be selected as an INC.
7584 if (C->getAPIntValue() == 1) {
7585 Opcode = X86ISD::INC;
7590 // An add of negative one (subtract of one) will be selected as a DEC.
7591 if (C->getAPIntValue().isAllOnesValue()) {
7592 Opcode = X86ISD::DEC;
7598 // Otherwise use a regular EFLAGS-setting add.
7599 Opcode = X86ISD::ADD;
7603 // If the primary and result isn't used, don't bother using X86ISD::AND,
7604 // because a TEST instruction will be better.
7605 bool NonFlagUse = false;
7606 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7607 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
7609 unsigned UOpNo = UI.getOperandNo();
7610 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
7611 // Look pass truncate.
7612 UOpNo = User->use_begin().getOperandNo();
7613 User = *User->use_begin();
7616 if (User->getOpcode() != ISD::BRCOND &&
7617 User->getOpcode() != ISD::SETCC &&
7618 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
7631 // Due to the ISEL shortcoming noted above, be conservative if this op is
7632 // likely to be selected as part of a load-modify-store instruction.
7633 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7634 UE = Op.getNode()->use_end(); UI != UE; ++UI)
7635 if (UI->getOpcode() == ISD::STORE)
7638 // Otherwise use a regular EFLAGS-setting instruction.
7639 switch (Op.getNode()->getOpcode()) {
7640 default: llvm_unreachable("unexpected operator!");
7641 case ISD::SUB: Opcode = X86ISD::SUB; break;
7642 case ISD::OR: Opcode = X86ISD::OR; break;
7643 case ISD::XOR: Opcode = X86ISD::XOR; break;
7644 case ISD::AND: Opcode = X86ISD::AND; break;
7656 return SDValue(Op.getNode(), 1);
7663 // Emit a CMP with 0, which is the TEST pattern.
7664 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
7665 DAG.getConstant(0, Op.getValueType()));
7667 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
7668 SmallVector<SDValue, 4> Ops;
7669 for (unsigned i = 0; i != NumOperands; ++i)
7670 Ops.push_back(Op.getOperand(i));
7672 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
7673 DAG.ReplaceAllUsesWith(Op, New);
7674 return SDValue(New.getNode(), 1);
7677 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
7679 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
7680 SelectionDAG &DAG) const {
7681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
7682 if (C->getAPIntValue() == 0)
7683 return EmitTest(Op0, X86CC, DAG);
7685 DebugLoc dl = Op0.getDebugLoc();
7686 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
7689 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
7690 /// if it's possible.
7691 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
7692 DebugLoc dl, SelectionDAG &DAG) const {
7693 SDValue Op0 = And.getOperand(0);
7694 SDValue Op1 = And.getOperand(1);
7695 if (Op0.getOpcode() == ISD::TRUNCATE)
7696 Op0 = Op0.getOperand(0);
7697 if (Op1.getOpcode() == ISD::TRUNCATE)
7698 Op1 = Op1.getOperand(0);
7701 if (Op1.getOpcode() == ISD::SHL)
7702 std::swap(Op0, Op1);
7703 if (Op0.getOpcode() == ISD::SHL) {
7704 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
7705 if (And00C->getZExtValue() == 1) {
7706 // If we looked past a truncate, check that it's only truncating away
7708 unsigned BitWidth = Op0.getValueSizeInBits();
7709 unsigned AndBitWidth = And.getValueSizeInBits();
7710 if (BitWidth > AndBitWidth) {
7711 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
7712 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
7713 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
7717 RHS = Op0.getOperand(1);
7719 } else if (Op1.getOpcode() == ISD::Constant) {
7720 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
7721 SDValue AndLHS = Op0;
7722 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
7723 LHS = AndLHS.getOperand(0);
7724 RHS = AndLHS.getOperand(1);
7728 if (LHS.getNode()) {
7729 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
7730 // instruction. Since the shift amount is in-range-or-undefined, we know
7731 // that doing a bittest on the i32 value is ok. We extend to i32 because
7732 // the encoding for the i16 version is larger than the i32 version.
7733 // Also promote i16 to i32 for performance / code size reason.
7734 if (LHS.getValueType() == MVT::i8 ||
7735 LHS.getValueType() == MVT::i16)
7736 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
7738 // If the operand types disagree, extend the shift amount to match. Since
7739 // BT ignores high bits (like shifts) we can use anyextend.
7740 if (LHS.getValueType() != RHS.getValueType())
7741 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
7743 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
7744 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
7745 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7746 DAG.getConstant(Cond, MVT::i8), BT);
7752 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
7753 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
7754 SDValue Op0 = Op.getOperand(0);
7755 SDValue Op1 = Op.getOperand(1);
7756 DebugLoc dl = Op.getDebugLoc();
7757 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7759 // Optimize to BT if possible.
7760 // Lower (X & (1 << N)) == 0 to BT(X, N).
7761 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
7762 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
7763 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
7764 Op1.getOpcode() == ISD::Constant &&
7765 cast<ConstantSDNode>(Op1)->isNullValue() &&
7766 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7767 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
7768 if (NewSetCC.getNode())
7772 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
7774 if (Op1.getOpcode() == ISD::Constant &&
7775 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
7776 cast<ConstantSDNode>(Op1)->isNullValue()) &&
7777 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7779 // If the input is a setcc, then reuse the input setcc or use a new one with
7780 // the inverted condition.
7781 if (Op0.getOpcode() == X86ISD::SETCC) {
7782 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
7783 bool Invert = (CC == ISD::SETNE) ^
7784 cast<ConstantSDNode>(Op1)->isNullValue();
7785 if (!Invert) return Op0;
7787 CCode = X86::GetOppositeBranchCondition(CCode);
7788 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7789 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
7793 bool isFP = Op1.getValueType().isFloatingPoint();
7794 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
7795 if (X86CC == X86::COND_INVALID)
7798 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
7799 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7800 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
7803 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
7805 SDValue Op0 = Op.getOperand(0);
7806 SDValue Op1 = Op.getOperand(1);
7807 SDValue CC = Op.getOperand(2);
7808 EVT VT = Op.getValueType();
7809 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
7810 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
7811 DebugLoc dl = Op.getDebugLoc();
7815 EVT VT0 = Op0.getValueType();
7816 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
7817 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
7820 switch (SetCCOpcode) {
7823 case ISD::SETEQ: SSECC = 0; break;
7825 case ISD::SETGT: Swap = true; // Fallthrough
7827 case ISD::SETOLT: SSECC = 1; break;
7829 case ISD::SETGE: Swap = true; // Fallthrough
7831 case ISD::SETOLE: SSECC = 2; break;
7832 case ISD::SETUO: SSECC = 3; break;
7834 case ISD::SETNE: SSECC = 4; break;
7835 case ISD::SETULE: Swap = true;
7836 case ISD::SETUGE: SSECC = 5; break;
7837 case ISD::SETULT: Swap = true;
7838 case ISD::SETUGT: SSECC = 6; break;
7839 case ISD::SETO: SSECC = 7; break;
7842 std::swap(Op0, Op1);
7844 // In the two special cases we can't handle, emit two comparisons.
7846 if (SetCCOpcode == ISD::SETUEQ) {
7848 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
7849 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
7850 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
7852 else if (SetCCOpcode == ISD::SETONE) {
7854 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
7855 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
7856 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
7858 llvm_unreachable("Illegal FP comparison");
7860 // Handle all other FP comparisons here.
7861 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
7864 // We are handling one of the integer comparisons here. Since SSE only has
7865 // GT and EQ comparisons for integer, swapping operands and multiple
7866 // operations may be required for some comparisons.
7867 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
7868 bool Swap = false, Invert = false, FlipSigns = false;
7870 switch (VT.getSimpleVT().SimpleTy) {
7872 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
7873 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
7874 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
7875 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
7878 switch (SetCCOpcode) {
7880 case ISD::SETNE: Invert = true;
7881 case ISD::SETEQ: Opc = EQOpc; break;
7882 case ISD::SETLT: Swap = true;
7883 case ISD::SETGT: Opc = GTOpc; break;
7884 case ISD::SETGE: Swap = true;
7885 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
7886 case ISD::SETULT: Swap = true;
7887 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
7888 case ISD::SETUGE: Swap = true;
7889 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
7892 std::swap(Op0, Op1);
7894 // Since SSE has no unsigned integer comparisons, we need to flip the sign
7895 // bits of the inputs before performing those operations.
7897 EVT EltVT = VT.getVectorElementType();
7898 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
7900 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
7901 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
7903 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
7904 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
7907 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
7909 // If the logical-not of the result is required, perform that now.
7911 Result = DAG.getNOT(dl, Result, VT);
7916 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
7917 static bool isX86LogicalCmp(SDValue Op) {
7918 unsigned Opc = Op.getNode()->getOpcode();
7919 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
7921 if (Op.getResNo() == 1 &&
7922 (Opc == X86ISD::ADD ||
7923 Opc == X86ISD::SUB ||
7924 Opc == X86ISD::ADC ||
7925 Opc == X86ISD::SBB ||
7926 Opc == X86ISD::SMUL ||
7927 Opc == X86ISD::UMUL ||
7928 Opc == X86ISD::INC ||
7929 Opc == X86ISD::DEC ||
7930 Opc == X86ISD::OR ||
7931 Opc == X86ISD::XOR ||
7932 Opc == X86ISD::AND))
7935 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
7941 static bool isZero(SDValue V) {
7942 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
7943 return C && C->isNullValue();
7946 static bool isAllOnes(SDValue V) {
7947 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
7948 return C && C->isAllOnesValue();
7951 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
7952 bool addTest = true;
7953 SDValue Cond = Op.getOperand(0);
7954 SDValue Op1 = Op.getOperand(1);
7955 SDValue Op2 = Op.getOperand(2);
7956 DebugLoc DL = Op.getDebugLoc();
7959 if (Cond.getOpcode() == ISD::SETCC) {
7960 SDValue NewCond = LowerSETCC(Cond, DAG);
7961 if (NewCond.getNode())
7965 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
7966 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
7967 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
7968 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
7969 if (Cond.getOpcode() == X86ISD::SETCC &&
7970 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
7971 isZero(Cond.getOperand(1).getOperand(1))) {
7972 SDValue Cmp = Cond.getOperand(1);
7974 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
7976 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
7977 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
7978 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
7980 SDValue CmpOp0 = Cmp.getOperand(0);
7981 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
7982 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
7984 SDValue Res = // Res = 0 or -1.
7985 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
7986 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
7988 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
7989 Res = DAG.getNOT(DL, Res, Res.getValueType());
7991 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
7992 if (N2C == 0 || !N2C->isNullValue())
7993 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
7998 // Look past (and (setcc_carry (cmp ...)), 1).
7999 if (Cond.getOpcode() == ISD::AND &&
8000 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8001 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8002 if (C && C->getAPIntValue() == 1)
8003 Cond = Cond.getOperand(0);
8006 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8007 // setting operand in place of the X86ISD::SETCC.
8008 if (Cond.getOpcode() == X86ISD::SETCC ||
8009 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8010 CC = Cond.getOperand(0);
8012 SDValue Cmp = Cond.getOperand(1);
8013 unsigned Opc = Cmp.getOpcode();
8014 EVT VT = Op.getValueType();
8016 bool IllegalFPCMov = false;
8017 if (VT.isFloatingPoint() && !VT.isVector() &&
8018 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8019 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8021 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8022 Opc == X86ISD::BT) { // FIXME
8029 // Look pass the truncate.
8030 if (Cond.getOpcode() == ISD::TRUNCATE)
8031 Cond = Cond.getOperand(0);
8033 // We know the result of AND is compared against zero. Try to match
8035 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8036 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8037 if (NewSetCC.getNode()) {
8038 CC = NewSetCC.getOperand(0);
8039 Cond = NewSetCC.getOperand(1);
8046 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8047 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8050 // a < b ? -1 : 0 -> RES = ~setcc_carry
8051 // a < b ? 0 : -1 -> RES = setcc_carry
8052 // a >= b ? -1 : 0 -> RES = setcc_carry
8053 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8054 if (Cond.getOpcode() == X86ISD::CMP) {
8055 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8057 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8058 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8059 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8060 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8061 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8062 return DAG.getNOT(DL, Res, Res.getValueType());
8067 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8068 // condition is true.
8069 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8070 SDValue Ops[] = { Op2, Op1, CC, Cond };
8071 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8074 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8075 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8076 // from the AND / OR.
8077 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8078 Opc = Op.getOpcode();
8079 if (Opc != ISD::OR && Opc != ISD::AND)
8081 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8082 Op.getOperand(0).hasOneUse() &&
8083 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8084 Op.getOperand(1).hasOneUse());
8087 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8088 // 1 and that the SETCC node has a single use.
8089 static bool isXor1OfSetCC(SDValue Op) {
8090 if (Op.getOpcode() != ISD::XOR)
8092 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8093 if (N1C && N1C->getAPIntValue() == 1) {
8094 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8095 Op.getOperand(0).hasOneUse();
8100 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8101 bool addTest = true;
8102 SDValue Chain = Op.getOperand(0);
8103 SDValue Cond = Op.getOperand(1);
8104 SDValue Dest = Op.getOperand(2);
8105 DebugLoc dl = Op.getDebugLoc();
8108 if (Cond.getOpcode() == ISD::SETCC) {
8109 SDValue NewCond = LowerSETCC(Cond, DAG);
8110 if (NewCond.getNode())
8114 // FIXME: LowerXALUO doesn't handle these!!
8115 else if (Cond.getOpcode() == X86ISD::ADD ||
8116 Cond.getOpcode() == X86ISD::SUB ||
8117 Cond.getOpcode() == X86ISD::SMUL ||
8118 Cond.getOpcode() == X86ISD::UMUL)
8119 Cond = LowerXALUO(Cond, DAG);
8122 // Look pass (and (setcc_carry (cmp ...)), 1).
8123 if (Cond.getOpcode() == ISD::AND &&
8124 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8125 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8126 if (C && C->getAPIntValue() == 1)
8127 Cond = Cond.getOperand(0);
8130 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8131 // setting operand in place of the X86ISD::SETCC.
8132 if (Cond.getOpcode() == X86ISD::SETCC ||
8133 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8134 CC = Cond.getOperand(0);
8136 SDValue Cmp = Cond.getOperand(1);
8137 unsigned Opc = Cmp.getOpcode();
8138 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8139 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8143 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8147 // These can only come from an arithmetic instruction with overflow,
8148 // e.g. SADDO, UADDO.
8149 Cond = Cond.getNode()->getOperand(1);
8156 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8157 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8158 if (CondOpc == ISD::OR) {
8159 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8160 // two branches instead of an explicit OR instruction with a
8162 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8163 isX86LogicalCmp(Cmp)) {
8164 CC = Cond.getOperand(0).getOperand(0);
8165 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8166 Chain, Dest, CC, Cmp);
8167 CC = Cond.getOperand(1).getOperand(0);
8171 } else { // ISD::AND
8172 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8173 // two branches instead of an explicit AND instruction with a
8174 // separate test. However, we only do this if this block doesn't
8175 // have a fall-through edge, because this requires an explicit
8176 // jmp when the condition is false.
8177 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8178 isX86LogicalCmp(Cmp) &&
8179 Op.getNode()->hasOneUse()) {
8180 X86::CondCode CCode =
8181 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8182 CCode = X86::GetOppositeBranchCondition(CCode);
8183 CC = DAG.getConstant(CCode, MVT::i8);
8184 SDNode *User = *Op.getNode()->use_begin();
8185 // Look for an unconditional branch following this conditional branch.
8186 // We need this because we need to reverse the successors in order
8187 // to implement FCMP_OEQ.
8188 if (User->getOpcode() == ISD::BR) {
8189 SDValue FalseBB = User->getOperand(1);
8191 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8192 assert(NewBR == User);
8196 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8197 Chain, Dest, CC, Cmp);
8198 X86::CondCode CCode =
8199 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8200 CCode = X86::GetOppositeBranchCondition(CCode);
8201 CC = DAG.getConstant(CCode, MVT::i8);
8207 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8208 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8209 // It should be transformed during dag combiner except when the condition
8210 // is set by a arithmetics with overflow node.
8211 X86::CondCode CCode =
8212 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8213 CCode = X86::GetOppositeBranchCondition(CCode);
8214 CC = DAG.getConstant(CCode, MVT::i8);
8215 Cond = Cond.getOperand(0).getOperand(1);
8221 // Look pass the truncate.
8222 if (Cond.getOpcode() == ISD::TRUNCATE)
8223 Cond = Cond.getOperand(0);
8225 // We know the result of AND is compared against zero. Try to match
8227 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8228 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8229 if (NewSetCC.getNode()) {
8230 CC = NewSetCC.getOperand(0);
8231 Cond = NewSetCC.getOperand(1);
8238 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8239 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8241 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8242 Chain, Dest, CC, Cond);
8246 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8247 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8248 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8249 // that the guard pages used by the OS virtual memory manager are allocated in
8250 // correct sequence.
8252 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8253 SelectionDAG &DAG) const {
8254 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
8255 "This should be used only on Windows targets");
8256 assert(!Subtarget->isTargetEnvMacho());
8257 DebugLoc dl = Op.getDebugLoc();
8260 SDValue Chain = Op.getOperand(0);
8261 SDValue Size = Op.getOperand(1);
8262 // FIXME: Ensure alignment here
8266 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
8267 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8269 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8270 Flag = Chain.getValue(1);
8272 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8274 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8275 Flag = Chain.getValue(1);
8277 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8279 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8280 return DAG.getMergeValues(Ops1, 2, dl);
8283 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8284 MachineFunction &MF = DAG.getMachineFunction();
8285 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8287 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8288 DebugLoc DL = Op.getDebugLoc();
8290 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8291 // vastart just stores the address of the VarArgsFrameIndex slot into the
8292 // memory location argument.
8293 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8295 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8296 MachinePointerInfo(SV), false, false, 0);
8300 // gp_offset (0 - 6 * 8)
8301 // fp_offset (48 - 48 + 8 * 16)
8302 // overflow_arg_area (point to parameters coming in memory).
8304 SmallVector<SDValue, 8> MemOps;
8305 SDValue FIN = Op.getOperand(1);
8307 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8308 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
8310 FIN, MachinePointerInfo(SV), false, false, 0);
8311 MemOps.push_back(Store);
8314 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8315 FIN, DAG.getIntPtrConstant(4));
8316 Store = DAG.getStore(Op.getOperand(0), DL,
8317 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
8319 FIN, MachinePointerInfo(SV, 4), false, false, 0);
8320 MemOps.push_back(Store);
8322 // Store ptr to overflow_arg_area
8323 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8324 FIN, DAG.getIntPtrConstant(4));
8325 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8327 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
8328 MachinePointerInfo(SV, 8),
8330 MemOps.push_back(Store);
8332 // Store ptr to reg_save_area.
8333 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8334 FIN, DAG.getIntPtrConstant(8));
8335 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
8337 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
8338 MachinePointerInfo(SV, 16), false, false, 0);
8339 MemOps.push_back(Store);
8340 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
8341 &MemOps[0], MemOps.size());
8344 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
8345 assert(Subtarget->is64Bit() &&
8346 "LowerVAARG only handles 64-bit va_arg!");
8347 assert((Subtarget->isTargetLinux() ||
8348 Subtarget->isTargetDarwin()) &&
8349 "Unhandled target in LowerVAARG");
8350 assert(Op.getNode()->getNumOperands() == 4);
8351 SDValue Chain = Op.getOperand(0);
8352 SDValue SrcPtr = Op.getOperand(1);
8353 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8354 unsigned Align = Op.getConstantOperandVal(3);
8355 DebugLoc dl = Op.getDebugLoc();
8357 EVT ArgVT = Op.getNode()->getValueType(0);
8358 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
8359 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
8362 // Decide which area this value should be read from.
8363 // TODO: Implement the AMD64 ABI in its entirety. This simple
8364 // selection mechanism works only for the basic types.
8365 if (ArgVT == MVT::f80) {
8366 llvm_unreachable("va_arg for f80 not yet implemented");
8367 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
8368 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
8369 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
8370 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
8372 llvm_unreachable("Unhandled argument type in LowerVAARG");
8376 // Sanity Check: Make sure using fp_offset makes sense.
8377 assert(!UseSoftFloat &&
8378 !(DAG.getMachineFunction()
8379 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
8380 Subtarget->hasXMM());
8383 // Insert VAARG_64 node into the DAG
8384 // VAARG_64 returns two values: Variable Argument Address, Chain
8385 SmallVector<SDValue, 11> InstOps;
8386 InstOps.push_back(Chain);
8387 InstOps.push_back(SrcPtr);
8388 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
8389 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
8390 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
8391 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
8392 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
8393 VTs, &InstOps[0], InstOps.size(),
8395 MachinePointerInfo(SV),
8400 Chain = VAARG.getValue(1);
8402 // Load the next argument and return it
8403 return DAG.getLoad(ArgVT, dl,
8406 MachinePointerInfo(),
8410 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
8411 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
8412 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
8413 SDValue Chain = Op.getOperand(0);
8414 SDValue DstPtr = Op.getOperand(1);
8415 SDValue SrcPtr = Op.getOperand(2);
8416 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
8417 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8418 DebugLoc DL = Op.getDebugLoc();
8420 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
8421 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
8423 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
8427 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
8428 DebugLoc dl = Op.getDebugLoc();
8429 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8431 default: return SDValue(); // Don't custom lower most intrinsics.
8432 // Comparison intrinsics.
8433 case Intrinsic::x86_sse_comieq_ss:
8434 case Intrinsic::x86_sse_comilt_ss:
8435 case Intrinsic::x86_sse_comile_ss:
8436 case Intrinsic::x86_sse_comigt_ss:
8437 case Intrinsic::x86_sse_comige_ss:
8438 case Intrinsic::x86_sse_comineq_ss:
8439 case Intrinsic::x86_sse_ucomieq_ss:
8440 case Intrinsic::x86_sse_ucomilt_ss:
8441 case Intrinsic::x86_sse_ucomile_ss:
8442 case Intrinsic::x86_sse_ucomigt_ss:
8443 case Intrinsic::x86_sse_ucomige_ss:
8444 case Intrinsic::x86_sse_ucomineq_ss:
8445 case Intrinsic::x86_sse2_comieq_sd:
8446 case Intrinsic::x86_sse2_comilt_sd:
8447 case Intrinsic::x86_sse2_comile_sd:
8448 case Intrinsic::x86_sse2_comigt_sd:
8449 case Intrinsic::x86_sse2_comige_sd:
8450 case Intrinsic::x86_sse2_comineq_sd:
8451 case Intrinsic::x86_sse2_ucomieq_sd:
8452 case Intrinsic::x86_sse2_ucomilt_sd:
8453 case Intrinsic::x86_sse2_ucomile_sd:
8454 case Intrinsic::x86_sse2_ucomigt_sd:
8455 case Intrinsic::x86_sse2_ucomige_sd:
8456 case Intrinsic::x86_sse2_ucomineq_sd: {
8458 ISD::CondCode CC = ISD::SETCC_INVALID;
8461 case Intrinsic::x86_sse_comieq_ss:
8462 case Intrinsic::x86_sse2_comieq_sd:
8466 case Intrinsic::x86_sse_comilt_ss:
8467 case Intrinsic::x86_sse2_comilt_sd:
8471 case Intrinsic::x86_sse_comile_ss:
8472 case Intrinsic::x86_sse2_comile_sd:
8476 case Intrinsic::x86_sse_comigt_ss:
8477 case Intrinsic::x86_sse2_comigt_sd:
8481 case Intrinsic::x86_sse_comige_ss:
8482 case Intrinsic::x86_sse2_comige_sd:
8486 case Intrinsic::x86_sse_comineq_ss:
8487 case Intrinsic::x86_sse2_comineq_sd:
8491 case Intrinsic::x86_sse_ucomieq_ss:
8492 case Intrinsic::x86_sse2_ucomieq_sd:
8493 Opc = X86ISD::UCOMI;
8496 case Intrinsic::x86_sse_ucomilt_ss:
8497 case Intrinsic::x86_sse2_ucomilt_sd:
8498 Opc = X86ISD::UCOMI;
8501 case Intrinsic::x86_sse_ucomile_ss:
8502 case Intrinsic::x86_sse2_ucomile_sd:
8503 Opc = X86ISD::UCOMI;
8506 case Intrinsic::x86_sse_ucomigt_ss:
8507 case Intrinsic::x86_sse2_ucomigt_sd:
8508 Opc = X86ISD::UCOMI;
8511 case Intrinsic::x86_sse_ucomige_ss:
8512 case Intrinsic::x86_sse2_ucomige_sd:
8513 Opc = X86ISD::UCOMI;
8516 case Intrinsic::x86_sse_ucomineq_ss:
8517 case Intrinsic::x86_sse2_ucomineq_sd:
8518 Opc = X86ISD::UCOMI;
8523 SDValue LHS = Op.getOperand(1);
8524 SDValue RHS = Op.getOperand(2);
8525 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
8526 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
8527 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
8528 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8529 DAG.getConstant(X86CC, MVT::i8), Cond);
8530 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
8532 // ptest and testp intrinsics. The intrinsic these come from are designed to
8533 // return an integer value, not just an instruction so lower it to the ptest
8534 // or testp pattern and a setcc for the result.
8535 case Intrinsic::x86_sse41_ptestz:
8536 case Intrinsic::x86_sse41_ptestc:
8537 case Intrinsic::x86_sse41_ptestnzc:
8538 case Intrinsic::x86_avx_ptestz_256:
8539 case Intrinsic::x86_avx_ptestc_256:
8540 case Intrinsic::x86_avx_ptestnzc_256:
8541 case Intrinsic::x86_avx_vtestz_ps:
8542 case Intrinsic::x86_avx_vtestc_ps:
8543 case Intrinsic::x86_avx_vtestnzc_ps:
8544 case Intrinsic::x86_avx_vtestz_pd:
8545 case Intrinsic::x86_avx_vtestc_pd:
8546 case Intrinsic::x86_avx_vtestnzc_pd:
8547 case Intrinsic::x86_avx_vtestz_ps_256:
8548 case Intrinsic::x86_avx_vtestc_ps_256:
8549 case Intrinsic::x86_avx_vtestnzc_ps_256:
8550 case Intrinsic::x86_avx_vtestz_pd_256:
8551 case Intrinsic::x86_avx_vtestc_pd_256:
8552 case Intrinsic::x86_avx_vtestnzc_pd_256: {
8553 bool IsTestPacked = false;
8556 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
8557 case Intrinsic::x86_avx_vtestz_ps:
8558 case Intrinsic::x86_avx_vtestz_pd:
8559 case Intrinsic::x86_avx_vtestz_ps_256:
8560 case Intrinsic::x86_avx_vtestz_pd_256:
8561 IsTestPacked = true; // Fallthrough
8562 case Intrinsic::x86_sse41_ptestz:
8563 case Intrinsic::x86_avx_ptestz_256:
8565 X86CC = X86::COND_E;
8567 case Intrinsic::x86_avx_vtestc_ps:
8568 case Intrinsic::x86_avx_vtestc_pd:
8569 case Intrinsic::x86_avx_vtestc_ps_256:
8570 case Intrinsic::x86_avx_vtestc_pd_256:
8571 IsTestPacked = true; // Fallthrough
8572 case Intrinsic::x86_sse41_ptestc:
8573 case Intrinsic::x86_avx_ptestc_256:
8575 X86CC = X86::COND_B;
8577 case Intrinsic::x86_avx_vtestnzc_ps:
8578 case Intrinsic::x86_avx_vtestnzc_pd:
8579 case Intrinsic::x86_avx_vtestnzc_ps_256:
8580 case Intrinsic::x86_avx_vtestnzc_pd_256:
8581 IsTestPacked = true; // Fallthrough
8582 case Intrinsic::x86_sse41_ptestnzc:
8583 case Intrinsic::x86_avx_ptestnzc_256:
8585 X86CC = X86::COND_A;
8589 SDValue LHS = Op.getOperand(1);
8590 SDValue RHS = Op.getOperand(2);
8591 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
8592 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
8593 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
8594 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
8595 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
8598 // Fix vector shift instructions where the last operand is a non-immediate
8600 case Intrinsic::x86_sse2_pslli_w:
8601 case Intrinsic::x86_sse2_pslli_d:
8602 case Intrinsic::x86_sse2_pslli_q:
8603 case Intrinsic::x86_sse2_psrli_w:
8604 case Intrinsic::x86_sse2_psrli_d:
8605 case Intrinsic::x86_sse2_psrli_q:
8606 case Intrinsic::x86_sse2_psrai_w:
8607 case Intrinsic::x86_sse2_psrai_d:
8608 case Intrinsic::x86_mmx_pslli_w:
8609 case Intrinsic::x86_mmx_pslli_d:
8610 case Intrinsic::x86_mmx_pslli_q:
8611 case Intrinsic::x86_mmx_psrli_w:
8612 case Intrinsic::x86_mmx_psrli_d:
8613 case Intrinsic::x86_mmx_psrli_q:
8614 case Intrinsic::x86_mmx_psrai_w:
8615 case Intrinsic::x86_mmx_psrai_d: {
8616 SDValue ShAmt = Op.getOperand(2);
8617 if (isa<ConstantSDNode>(ShAmt))
8620 unsigned NewIntNo = 0;
8621 EVT ShAmtVT = MVT::v4i32;
8623 case Intrinsic::x86_sse2_pslli_w:
8624 NewIntNo = Intrinsic::x86_sse2_psll_w;
8626 case Intrinsic::x86_sse2_pslli_d:
8627 NewIntNo = Intrinsic::x86_sse2_psll_d;
8629 case Intrinsic::x86_sse2_pslli_q:
8630 NewIntNo = Intrinsic::x86_sse2_psll_q;
8632 case Intrinsic::x86_sse2_psrli_w:
8633 NewIntNo = Intrinsic::x86_sse2_psrl_w;
8635 case Intrinsic::x86_sse2_psrli_d:
8636 NewIntNo = Intrinsic::x86_sse2_psrl_d;
8638 case Intrinsic::x86_sse2_psrli_q:
8639 NewIntNo = Intrinsic::x86_sse2_psrl_q;
8641 case Intrinsic::x86_sse2_psrai_w:
8642 NewIntNo = Intrinsic::x86_sse2_psra_w;
8644 case Intrinsic::x86_sse2_psrai_d:
8645 NewIntNo = Intrinsic::x86_sse2_psra_d;
8648 ShAmtVT = MVT::v2i32;
8650 case Intrinsic::x86_mmx_pslli_w:
8651 NewIntNo = Intrinsic::x86_mmx_psll_w;
8653 case Intrinsic::x86_mmx_pslli_d:
8654 NewIntNo = Intrinsic::x86_mmx_psll_d;
8656 case Intrinsic::x86_mmx_pslli_q:
8657 NewIntNo = Intrinsic::x86_mmx_psll_q;
8659 case Intrinsic::x86_mmx_psrli_w:
8660 NewIntNo = Intrinsic::x86_mmx_psrl_w;
8662 case Intrinsic::x86_mmx_psrli_d:
8663 NewIntNo = Intrinsic::x86_mmx_psrl_d;
8665 case Intrinsic::x86_mmx_psrli_q:
8666 NewIntNo = Intrinsic::x86_mmx_psrl_q;
8668 case Intrinsic::x86_mmx_psrai_w:
8669 NewIntNo = Intrinsic::x86_mmx_psra_w;
8671 case Intrinsic::x86_mmx_psrai_d:
8672 NewIntNo = Intrinsic::x86_mmx_psra_d;
8674 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
8680 // The vector shift intrinsics with scalars uses 32b shift amounts but
8681 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
8685 ShOps[1] = DAG.getConstant(0, MVT::i32);
8686 if (ShAmtVT == MVT::v4i32) {
8687 ShOps[2] = DAG.getUNDEF(MVT::i32);
8688 ShOps[3] = DAG.getUNDEF(MVT::i32);
8689 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
8691 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
8692 // FIXME this must be lowered to get rid of the invalid type.
8695 EVT VT = Op.getValueType();
8696 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
8697 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8698 DAG.getConstant(NewIntNo, MVT::i32),
8699 Op.getOperand(1), ShAmt);
8704 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
8705 SelectionDAG &DAG) const {
8706 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8707 MFI->setReturnAddressIsTaken(true);
8709 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8710 DebugLoc dl = Op.getDebugLoc();
8713 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8715 DAG.getConstant(TD->getPointerSize(),
8716 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
8717 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8718 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8720 MachinePointerInfo(), false, false, 0);
8723 // Just load the return address.
8724 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
8725 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8726 RetAddrFI, MachinePointerInfo(), false, false, 0);
8729 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
8730 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8731 MFI->setFrameAddressIsTaken(true);
8733 EVT VT = Op.getValueType();
8734 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
8735 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8736 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
8737 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
8739 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
8740 MachinePointerInfo(),
8745 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
8746 SelectionDAG &DAG) const {
8747 return DAG.getIntPtrConstant(2*TD->getPointerSize());
8750 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
8751 MachineFunction &MF = DAG.getMachineFunction();
8752 SDValue Chain = Op.getOperand(0);
8753 SDValue Offset = Op.getOperand(1);
8754 SDValue Handler = Op.getOperand(2);
8755 DebugLoc dl = Op.getDebugLoc();
8757 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
8758 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
8760 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
8762 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
8763 DAG.getIntPtrConstant(TD->getPointerSize()));
8764 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
8765 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
8767 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
8768 MF.getRegInfo().addLiveOut(StoreAddrReg);
8770 return DAG.getNode(X86ISD::EH_RETURN, dl,
8772 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
8775 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
8776 SelectionDAG &DAG) const {
8777 SDValue Root = Op.getOperand(0);
8778 SDValue Trmp = Op.getOperand(1); // trampoline
8779 SDValue FPtr = Op.getOperand(2); // nested function
8780 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
8781 DebugLoc dl = Op.getDebugLoc();
8783 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8785 if (Subtarget->is64Bit()) {
8786 SDValue OutChains[6];
8788 // Large code-model.
8789 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
8790 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
8792 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
8793 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
8795 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
8797 // Load the pointer to the nested function into R11.
8798 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
8799 SDValue Addr = Trmp;
8800 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8801 Addr, MachinePointerInfo(TrmpAddr),
8804 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8805 DAG.getConstant(2, MVT::i64));
8806 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
8807 MachinePointerInfo(TrmpAddr, 2),
8810 // Load the 'nest' parameter value into R10.
8811 // R10 is specified in X86CallingConv.td
8812 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
8813 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8814 DAG.getConstant(10, MVT::i64));
8815 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8816 Addr, MachinePointerInfo(TrmpAddr, 10),
8819 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8820 DAG.getConstant(12, MVT::i64));
8821 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
8822 MachinePointerInfo(TrmpAddr, 12),
8825 // Jump to the nested function.
8826 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
8827 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8828 DAG.getConstant(20, MVT::i64));
8829 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8830 Addr, MachinePointerInfo(TrmpAddr, 20),
8833 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
8834 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8835 DAG.getConstant(22, MVT::i64));
8836 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
8837 MachinePointerInfo(TrmpAddr, 22),
8841 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
8842 return DAG.getMergeValues(Ops, 2, dl);
8844 const Function *Func =
8845 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
8846 CallingConv::ID CC = Func->getCallingConv();
8851 llvm_unreachable("Unsupported calling convention");
8852 case CallingConv::C:
8853 case CallingConv::X86_StdCall: {
8854 // Pass 'nest' parameter in ECX.
8855 // Must be kept in sync with X86CallingConv.td
8858 // Check that ECX wasn't needed by an 'inreg' parameter.
8859 FunctionType *FTy = Func->getFunctionType();
8860 const AttrListPtr &Attrs = Func->getAttributes();
8862 if (!Attrs.isEmpty() && !Func->isVarArg()) {
8863 unsigned InRegCount = 0;
8866 for (FunctionType::param_iterator I = FTy->param_begin(),
8867 E = FTy->param_end(); I != E; ++I, ++Idx)
8868 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
8869 // FIXME: should only count parameters that are lowered to integers.
8870 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
8872 if (InRegCount > 2) {
8873 report_fatal_error("Nest register in use - reduce number of inreg"
8879 case CallingConv::X86_FastCall:
8880 case CallingConv::X86_ThisCall:
8881 case CallingConv::Fast:
8882 // Pass 'nest' parameter in EAX.
8883 // Must be kept in sync with X86CallingConv.td
8888 SDValue OutChains[4];
8891 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8892 DAG.getConstant(10, MVT::i32));
8893 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
8895 // This is storing the opcode for MOV32ri.
8896 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
8897 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
8898 OutChains[0] = DAG.getStore(Root, dl,
8899 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
8900 Trmp, MachinePointerInfo(TrmpAddr),
8903 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8904 DAG.getConstant(1, MVT::i32));
8905 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
8906 MachinePointerInfo(TrmpAddr, 1),
8909 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
8910 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8911 DAG.getConstant(5, MVT::i32));
8912 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
8913 MachinePointerInfo(TrmpAddr, 5),
8916 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8917 DAG.getConstant(6, MVT::i32));
8918 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
8919 MachinePointerInfo(TrmpAddr, 6),
8923 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
8924 return DAG.getMergeValues(Ops, 2, dl);
8928 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
8929 SelectionDAG &DAG) const {
8931 The rounding mode is in bits 11:10 of FPSR, and has the following
8938 FLT_ROUNDS, on the other hand, expects the following:
8945 To perform the conversion, we do:
8946 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
8949 MachineFunction &MF = DAG.getMachineFunction();
8950 const TargetMachine &TM = MF.getTarget();
8951 const TargetFrameLowering &TFI = *TM.getFrameLowering();
8952 unsigned StackAlignment = TFI.getStackAlignment();
8953 EVT VT = Op.getValueType();
8954 DebugLoc DL = Op.getDebugLoc();
8956 // Save FP Control Word to stack slot
8957 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
8958 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8961 MachineMemOperand *MMO =
8962 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8963 MachineMemOperand::MOStore, 2, 2);
8965 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
8966 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
8967 DAG.getVTList(MVT::Other),
8968 Ops, 2, MVT::i16, MMO);
8970 // Load FP Control Word from stack slot
8971 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
8972 MachinePointerInfo(), false, false, 0);
8974 // Transform as necessary
8976 DAG.getNode(ISD::SRL, DL, MVT::i16,
8977 DAG.getNode(ISD::AND, DL, MVT::i16,
8978 CWD, DAG.getConstant(0x800, MVT::i16)),
8979 DAG.getConstant(11, MVT::i8));
8981 DAG.getNode(ISD::SRL, DL, MVT::i16,
8982 DAG.getNode(ISD::AND, DL, MVT::i16,
8983 CWD, DAG.getConstant(0x400, MVT::i16)),
8984 DAG.getConstant(9, MVT::i8));
8987 DAG.getNode(ISD::AND, DL, MVT::i16,
8988 DAG.getNode(ISD::ADD, DL, MVT::i16,
8989 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
8990 DAG.getConstant(1, MVT::i16)),
8991 DAG.getConstant(3, MVT::i16));
8994 return DAG.getNode((VT.getSizeInBits() < 16 ?
8995 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
8998 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
8999 EVT VT = Op.getValueType();
9001 unsigned NumBits = VT.getSizeInBits();
9002 DebugLoc dl = Op.getDebugLoc();
9004 Op = Op.getOperand(0);
9005 if (VT == MVT::i8) {
9006 // Zero extend to i32 since there is not an i8 bsr.
9008 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9011 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9012 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9013 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9015 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9018 DAG.getConstant(NumBits+NumBits-1, OpVT),
9019 DAG.getConstant(X86::COND_E, MVT::i8),
9022 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9024 // Finally xor with NumBits-1.
9025 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9028 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9032 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9033 EVT VT = Op.getValueType();
9035 unsigned NumBits = VT.getSizeInBits();
9036 DebugLoc dl = Op.getDebugLoc();
9038 Op = Op.getOperand(0);
9039 if (VT == MVT::i8) {
9041 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9044 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9045 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9046 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9048 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9051 DAG.getConstant(NumBits, OpVT),
9052 DAG.getConstant(X86::COND_E, MVT::i8),
9055 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9058 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9062 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
9063 EVT VT = Op.getValueType();
9064 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9065 DebugLoc dl = Op.getDebugLoc();
9067 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9068 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9069 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9070 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9071 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9073 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9074 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9075 // return AloBlo + AloBhi + AhiBlo;
9077 SDValue A = Op.getOperand(0);
9078 SDValue B = Op.getOperand(1);
9080 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9081 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9082 A, DAG.getConstant(32, MVT::i32));
9083 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9084 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9085 B, DAG.getConstant(32, MVT::i32));
9086 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9087 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9089 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9090 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9092 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9093 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9095 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9096 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9097 AloBhi, DAG.getConstant(32, MVT::i32));
9098 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9099 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9100 AhiBlo, DAG.getConstant(32, MVT::i32));
9101 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9102 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9106 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9108 EVT VT = Op.getValueType();
9109 DebugLoc dl = Op.getDebugLoc();
9110 SDValue R = Op.getOperand(0);
9111 SDValue Amt = Op.getOperand(1);
9113 LLVMContext *Context = DAG.getContext();
9116 if (!Subtarget->hasSSE2()) return SDValue();
9118 // Optimize shl/srl/sra with constant shift amount.
9119 if (isSplatVector(Amt.getNode())) {
9120 SDValue SclrAmt = Amt->getOperand(0);
9121 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
9122 uint64_t ShiftAmt = C->getZExtValue();
9124 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
9125 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9126 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9127 R, DAG.getConstant(ShiftAmt, MVT::i32));
9129 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
9130 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9131 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9132 R, DAG.getConstant(ShiftAmt, MVT::i32));
9134 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
9135 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9136 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9137 R, DAG.getConstant(ShiftAmt, MVT::i32));
9139 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
9140 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9141 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9142 R, DAG.getConstant(ShiftAmt, MVT::i32));
9144 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
9145 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9146 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9147 R, DAG.getConstant(ShiftAmt, MVT::i32));
9149 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
9150 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9151 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9152 R, DAG.getConstant(ShiftAmt, MVT::i32));
9154 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
9155 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9156 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9157 R, DAG.getConstant(ShiftAmt, MVT::i32));
9159 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
9160 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9161 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9162 R, DAG.getConstant(ShiftAmt, MVT::i32));
9166 // Lower SHL with variable shift amount.
9167 // Cannot lower SHL without SSE2 or later.
9168 if (!Subtarget->hasSSE2()) return SDValue();
9170 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
9171 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9172 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9173 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
9175 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
9177 std::vector<Constant*> CV(4, CI);
9178 Constant *C = ConstantVector::get(CV);
9179 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9180 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9181 MachinePointerInfo::getConstantPool(),
9184 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
9185 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
9186 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
9187 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
9189 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
9191 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9192 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9193 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
9195 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
9196 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
9198 std::vector<Constant*> CVM1(16, CM1);
9199 std::vector<Constant*> CVM2(16, CM2);
9200 Constant *C = ConstantVector::get(CVM1);
9201 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9202 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9203 MachinePointerInfo::getConstantPool(),
9206 // r = pblendv(r, psllw(r & (char16)15, 4), a);
9207 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9208 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9209 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9210 DAG.getConstant(4, MVT::i32));
9211 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9213 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9215 C = ConstantVector::get(CVM2);
9216 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9217 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9218 MachinePointerInfo::getConstantPool(),
9221 // r = pblendv(r, psllw(r & (char16)63, 2), a);
9222 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9223 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9224 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9225 DAG.getConstant(2, MVT::i32));
9226 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9228 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9230 // return pblendv(r, r+r, a);
9231 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
9232 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
9238 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
9239 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
9240 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
9241 // looks for this combo and may remove the "setcc" instruction if the "setcc"
9242 // has only one use.
9243 SDNode *N = Op.getNode();
9244 SDValue LHS = N->getOperand(0);
9245 SDValue RHS = N->getOperand(1);
9246 unsigned BaseOp = 0;
9248 DebugLoc DL = Op.getDebugLoc();
9249 switch (Op.getOpcode()) {
9250 default: llvm_unreachable("Unknown ovf instruction!");
9252 // A subtract of one will be selected as a INC. Note that INC doesn't
9253 // set CF, so we can't do this for UADDO.
9254 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9256 BaseOp = X86ISD::INC;
9260 BaseOp = X86ISD::ADD;
9264 BaseOp = X86ISD::ADD;
9268 // A subtract of one will be selected as a DEC. Note that DEC doesn't
9269 // set CF, so we can't do this for USUBO.
9270 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9272 BaseOp = X86ISD::DEC;
9276 BaseOp = X86ISD::SUB;
9280 BaseOp = X86ISD::SUB;
9284 BaseOp = X86ISD::SMUL;
9287 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
9288 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
9290 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
9293 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9294 DAG.getConstant(X86::COND_O, MVT::i32),
9295 SDValue(Sum.getNode(), 2));
9297 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9301 // Also sets EFLAGS.
9302 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
9303 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
9306 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
9307 DAG.getConstant(Cond, MVT::i32),
9308 SDValue(Sum.getNode(), 1));
9310 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9313 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
9314 DebugLoc dl = Op.getDebugLoc();
9315 SDNode* Node = Op.getNode();
9316 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
9317 EVT VT = Node->getValueType(0);
9319 if (Subtarget->hasSSE2() && VT.isVector()) {
9320 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
9321 ExtraVT.getScalarType().getSizeInBits();
9322 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
9324 unsigned SHLIntrinsicsID = 0;
9325 unsigned SRAIntrinsicsID = 0;
9326 switch (VT.getSimpleVT().SimpleTy) {
9330 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q;
9331 SRAIntrinsicsID = 0;
9335 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
9336 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
9340 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
9341 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
9346 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9347 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
9348 Node->getOperand(0), ShAmt);
9350 // In case of 1 bit sext, no need to shr
9351 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
9353 if (SRAIntrinsicsID) {
9354 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9355 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
9365 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
9366 DebugLoc dl = Op.getDebugLoc();
9368 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
9369 // There isn't any reason to disable it if the target processor supports it.
9370 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
9371 SDValue Chain = Op.getOperand(0);
9372 SDValue Zero = DAG.getConstant(0, MVT::i32);
9374 DAG.getRegister(X86::ESP, MVT::i32), // Base
9375 DAG.getTargetConstant(1, MVT::i8), // Scale
9376 DAG.getRegister(0, MVT::i32), // Index
9377 DAG.getTargetConstant(0, MVT::i32), // Disp
9378 DAG.getRegister(0, MVT::i32), // Segment.
9383 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
9384 array_lengthof(Ops));
9385 return SDValue(Res, 0);
9388 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
9390 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
9392 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9393 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
9394 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
9395 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
9397 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
9398 if (!Op1 && !Op2 && !Op3 && Op4)
9399 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
9401 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
9402 if (Op1 && !Op2 && !Op3 && !Op4)
9403 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
9405 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
9407 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
9410 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
9411 EVT T = Op.getValueType();
9412 DebugLoc DL = Op.getDebugLoc();
9415 switch(T.getSimpleVT().SimpleTy) {
9417 assert(false && "Invalid value type!");
9418 case MVT::i8: Reg = X86::AL; size = 1; break;
9419 case MVT::i16: Reg = X86::AX; size = 2; break;
9420 case MVT::i32: Reg = X86::EAX; size = 4; break;
9422 assert(Subtarget->is64Bit() && "Node not type legal!");
9423 Reg = X86::RAX; size = 8;
9426 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
9427 Op.getOperand(2), SDValue());
9428 SDValue Ops[] = { cpIn.getValue(0),
9431 DAG.getTargetConstant(size, MVT::i8),
9433 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9434 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
9435 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
9438 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
9442 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
9443 SelectionDAG &DAG) const {
9444 assert(Subtarget->is64Bit() && "Result not type legalized?");
9445 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9446 SDValue TheChain = Op.getOperand(0);
9447 DebugLoc dl = Op.getDebugLoc();
9448 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
9449 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
9450 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
9452 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
9453 DAG.getConstant(32, MVT::i8));
9455 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
9458 return DAG.getMergeValues(Ops, 2, dl);
9461 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
9462 SelectionDAG &DAG) const {
9463 EVT SrcVT = Op.getOperand(0).getValueType();
9464 EVT DstVT = Op.getValueType();
9465 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
9466 Subtarget->hasMMX() && "Unexpected custom BITCAST");
9467 assert((DstVT == MVT::i64 ||
9468 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
9469 "Unexpected custom BITCAST");
9470 // i64 <=> MMX conversions are Legal.
9471 if (SrcVT==MVT::i64 && DstVT.isVector())
9473 if (DstVT==MVT::i64 && SrcVT.isVector())
9475 // MMX <=> MMX conversions are Legal.
9476 if (SrcVT.isVector() && DstVT.isVector())
9478 // All other conversions need to be expanded.
9482 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
9483 SDNode *Node = Op.getNode();
9484 DebugLoc dl = Node->getDebugLoc();
9485 EVT T = Node->getValueType(0);
9486 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
9487 DAG.getConstant(0, T), Node->getOperand(2));
9488 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
9489 cast<AtomicSDNode>(Node)->getMemoryVT(),
9490 Node->getOperand(0),
9491 Node->getOperand(1), negOp,
9492 cast<AtomicSDNode>(Node)->getSrcValue(),
9493 cast<AtomicSDNode>(Node)->getAlignment());
9496 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
9497 EVT VT = Op.getNode()->getValueType(0);
9499 // Let legalize expand this if it isn't a legal type yet.
9500 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
9503 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
9506 bool ExtraOp = false;
9507 switch (Op.getOpcode()) {
9508 default: assert(0 && "Invalid code");
9509 case ISD::ADDC: Opc = X86ISD::ADD; break;
9510 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
9511 case ISD::SUBC: Opc = X86ISD::SUB; break;
9512 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
9516 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
9518 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
9519 Op.getOperand(1), Op.getOperand(2));
9522 /// LowerOperation - Provide custom lowering hooks for some operations.
9524 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
9525 switch (Op.getOpcode()) {
9526 default: llvm_unreachable("Should not custom lower this!");
9527 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
9528 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
9529 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
9530 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
9531 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
9532 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
9533 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
9534 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
9535 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
9536 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
9537 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
9538 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
9539 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
9540 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
9541 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
9542 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
9543 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
9544 case ISD::SHL_PARTS:
9545 case ISD::SRA_PARTS:
9546 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
9547 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
9548 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
9549 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
9550 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
9551 case ISD::FABS: return LowerFABS(Op, DAG);
9552 case ISD::FNEG: return LowerFNEG(Op, DAG);
9553 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
9554 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
9555 case ISD::SETCC: return LowerSETCC(Op, DAG);
9556 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
9557 case ISD::SELECT: return LowerSELECT(Op, DAG);
9558 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
9559 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
9560 case ISD::VASTART: return LowerVASTART(Op, DAG);
9561 case ISD::VAARG: return LowerVAARG(Op, DAG);
9562 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
9563 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
9564 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
9565 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
9566 case ISD::FRAME_TO_ARGS_OFFSET:
9567 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
9568 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
9569 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
9570 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
9571 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
9572 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
9573 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
9574 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
9577 case ISD::SHL: return LowerShift(Op, DAG);
9583 case ISD::UMULO: return LowerXALUO(Op, DAG);
9584 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
9585 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
9589 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
9593 void X86TargetLowering::
9594 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
9595 SelectionDAG &DAG, unsigned NewOp) const {
9596 EVT T = Node->getValueType(0);
9597 DebugLoc dl = Node->getDebugLoc();
9598 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
9600 SDValue Chain = Node->getOperand(0);
9601 SDValue In1 = Node->getOperand(1);
9602 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
9603 Node->getOperand(2), DAG.getIntPtrConstant(0));
9604 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
9605 Node->getOperand(2), DAG.getIntPtrConstant(1));
9606 SDValue Ops[] = { Chain, In1, In2L, In2H };
9607 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
9609 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
9610 cast<MemSDNode>(Node)->getMemOperand());
9611 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
9612 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
9613 Results.push_back(Result.getValue(2));
9616 /// ReplaceNodeResults - Replace a node with an illegal result type
9617 /// with a new node built out of custom code.
9618 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
9619 SmallVectorImpl<SDValue>&Results,
9620 SelectionDAG &DAG) const {
9621 DebugLoc dl = N->getDebugLoc();
9622 switch (N->getOpcode()) {
9624 assert(false && "Do not know how to custom type legalize this operation!");
9626 case ISD::SIGN_EXTEND_INREG:
9631 // We don't want to expand or promote these.
9633 case ISD::FP_TO_SINT: {
9634 std::pair<SDValue,SDValue> Vals =
9635 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
9636 SDValue FIST = Vals.first, StackSlot = Vals.second;
9637 if (FIST.getNode() != 0) {
9638 EVT VT = N->getValueType(0);
9639 // Return a load from the stack slot.
9640 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
9641 MachinePointerInfo(), false, false, 0));
9645 case ISD::READCYCLECOUNTER: {
9646 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9647 SDValue TheChain = N->getOperand(0);
9648 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
9649 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
9651 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
9653 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
9654 SDValue Ops[] = { eax, edx };
9655 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
9656 Results.push_back(edx.getValue(1));
9659 case ISD::ATOMIC_CMP_SWAP: {
9660 EVT T = N->getValueType(0);
9661 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
9662 SDValue cpInL, cpInH;
9663 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
9664 DAG.getConstant(0, MVT::i32));
9665 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
9666 DAG.getConstant(1, MVT::i32));
9667 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
9668 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
9670 SDValue swapInL, swapInH;
9671 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
9672 DAG.getConstant(0, MVT::i32));
9673 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
9674 DAG.getConstant(1, MVT::i32));
9675 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
9677 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
9678 swapInL.getValue(1));
9679 SDValue Ops[] = { swapInH.getValue(0),
9681 swapInH.getValue(1) };
9682 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9683 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
9684 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys,
9686 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
9687 MVT::i32, Result.getValue(1));
9688 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
9689 MVT::i32, cpOutL.getValue(2));
9690 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
9691 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
9692 Results.push_back(cpOutH.getValue(1));
9695 case ISD::ATOMIC_LOAD_ADD:
9696 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
9698 case ISD::ATOMIC_LOAD_AND:
9699 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
9701 case ISD::ATOMIC_LOAD_NAND:
9702 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
9704 case ISD::ATOMIC_LOAD_OR:
9705 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
9707 case ISD::ATOMIC_LOAD_SUB:
9708 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
9710 case ISD::ATOMIC_LOAD_XOR:
9711 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
9713 case ISD::ATOMIC_SWAP:
9714 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
9719 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
9721 default: return NULL;
9722 case X86ISD::BSF: return "X86ISD::BSF";
9723 case X86ISD::BSR: return "X86ISD::BSR";
9724 case X86ISD::SHLD: return "X86ISD::SHLD";
9725 case X86ISD::SHRD: return "X86ISD::SHRD";
9726 case X86ISD::FAND: return "X86ISD::FAND";
9727 case X86ISD::FOR: return "X86ISD::FOR";
9728 case X86ISD::FXOR: return "X86ISD::FXOR";
9729 case X86ISD::FSRL: return "X86ISD::FSRL";
9730 case X86ISD::FILD: return "X86ISD::FILD";
9731 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
9732 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
9733 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
9734 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
9735 case X86ISD::FLD: return "X86ISD::FLD";
9736 case X86ISD::FST: return "X86ISD::FST";
9737 case X86ISD::CALL: return "X86ISD::CALL";
9738 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
9739 case X86ISD::BT: return "X86ISD::BT";
9740 case X86ISD::CMP: return "X86ISD::CMP";
9741 case X86ISD::COMI: return "X86ISD::COMI";
9742 case X86ISD::UCOMI: return "X86ISD::UCOMI";
9743 case X86ISD::SETCC: return "X86ISD::SETCC";
9744 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
9745 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
9746 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
9747 case X86ISD::CMOV: return "X86ISD::CMOV";
9748 case X86ISD::BRCOND: return "X86ISD::BRCOND";
9749 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
9750 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
9751 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
9752 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
9753 case X86ISD::Wrapper: return "X86ISD::Wrapper";
9754 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
9755 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
9756 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
9757 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
9758 case X86ISD::PINSRB: return "X86ISD::PINSRB";
9759 case X86ISD::PINSRW: return "X86ISD::PINSRW";
9760 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
9761 case X86ISD::ANDNP: return "X86ISD::ANDNP";
9762 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
9763 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
9764 case X86ISD::PSIGND: return "X86ISD::PSIGND";
9765 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
9766 case X86ISD::FMAX: return "X86ISD::FMAX";
9767 case X86ISD::FMIN: return "X86ISD::FMIN";
9768 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
9769 case X86ISD::FRCP: return "X86ISD::FRCP";
9770 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
9771 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
9772 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
9773 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
9774 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
9775 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
9776 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
9777 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
9778 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
9779 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
9780 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
9781 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
9782 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
9783 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
9784 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
9785 case X86ISD::VSHL: return "X86ISD::VSHL";
9786 case X86ISD::VSRL: return "X86ISD::VSRL";
9787 case X86ISD::CMPPD: return "X86ISD::CMPPD";
9788 case X86ISD::CMPPS: return "X86ISD::CMPPS";
9789 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
9790 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
9791 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
9792 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
9793 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
9794 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
9795 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
9796 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
9797 case X86ISD::ADD: return "X86ISD::ADD";
9798 case X86ISD::SUB: return "X86ISD::SUB";
9799 case X86ISD::ADC: return "X86ISD::ADC";
9800 case X86ISD::SBB: return "X86ISD::SBB";
9801 case X86ISD::SMUL: return "X86ISD::SMUL";
9802 case X86ISD::UMUL: return "X86ISD::UMUL";
9803 case X86ISD::INC: return "X86ISD::INC";
9804 case X86ISD::DEC: return "X86ISD::DEC";
9805 case X86ISD::OR: return "X86ISD::OR";
9806 case X86ISD::XOR: return "X86ISD::XOR";
9807 case X86ISD::AND: return "X86ISD::AND";
9808 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
9809 case X86ISD::PTEST: return "X86ISD::PTEST";
9810 case X86ISD::TESTP: return "X86ISD::TESTP";
9811 case X86ISD::PALIGN: return "X86ISD::PALIGN";
9812 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
9813 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
9814 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
9815 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
9816 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
9817 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
9818 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
9819 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
9820 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
9821 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
9822 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
9823 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
9824 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
9825 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
9826 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
9827 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
9828 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
9829 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
9830 case X86ISD::MOVSD: return "X86ISD::MOVSD";
9831 case X86ISD::MOVSS: return "X86ISD::MOVSS";
9832 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
9833 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
9834 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
9835 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
9836 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
9837 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
9838 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
9839 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
9840 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
9841 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
9842 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
9843 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
9844 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
9845 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
9846 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY";
9847 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
9848 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY";
9849 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
9850 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
9851 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
9855 // isLegalAddressingMode - Return true if the addressing mode represented
9856 // by AM is legal for this target, for a load/store of the specified type.
9857 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
9859 // X86 supports extremely general addressing modes.
9860 CodeModel::Model M = getTargetMachine().getCodeModel();
9861 Reloc::Model R = getTargetMachine().getRelocationModel();
9863 // X86 allows a sign-extended 32-bit immediate field as a displacement.
9864 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
9869 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
9871 // If a reference to this global requires an extra load, we can't fold it.
9872 if (isGlobalStubReference(GVFlags))
9875 // If BaseGV requires a register for the PIC base, we cannot also have a
9876 // BaseReg specified.
9877 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
9880 // If lower 4G is not available, then we must use rip-relative addressing.
9881 if ((M != CodeModel::Small || R != Reloc::Static) &&
9882 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
9892 // These scales always work.
9897 // These scales are formed with basereg+scalereg. Only accept if there is
9902 default: // Other stuff never works.
9910 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9911 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9913 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9914 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9915 if (NumBits1 <= NumBits2)
9920 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9921 if (!VT1.isInteger() || !VT2.isInteger())
9923 unsigned NumBits1 = VT1.getSizeInBits();
9924 unsigned NumBits2 = VT2.getSizeInBits();
9925 if (NumBits1 <= NumBits2)
9930 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
9931 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
9932 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
9935 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
9936 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
9937 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
9940 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
9941 // i16 instructions are longer (0x66 prefix) and potentially slower.
9942 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
9945 /// isShuffleMaskLegal - Targets can use this to indicate that they only
9946 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
9947 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
9948 /// are assumed to be legal.
9950 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
9952 // Very little shuffling can be done for 64-bit vectors right now.
9953 if (VT.getSizeInBits() == 64)
9954 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
9956 // FIXME: pshufb, blends, shifts.
9957 return (VT.getVectorNumElements() == 2 ||
9958 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
9959 isMOVLMask(M, VT) ||
9960 isSHUFPMask(M, VT) ||
9961 isPSHUFDMask(M, VT) ||
9962 isPSHUFHWMask(M, VT) ||
9963 isPSHUFLWMask(M, VT) ||
9964 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
9965 isUNPCKLMask(M, VT) ||
9966 isUNPCKHMask(M, VT) ||
9967 isUNPCKL_v_undef_Mask(M, VT) ||
9968 isUNPCKH_v_undef_Mask(M, VT));
9972 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
9974 unsigned NumElts = VT.getVectorNumElements();
9975 // FIXME: This collection of masks seems suspect.
9978 if (NumElts == 4 && VT.getSizeInBits() == 128) {
9979 return (isMOVLMask(Mask, VT) ||
9980 isCommutedMOVLMask(Mask, VT, true) ||
9981 isSHUFPMask(Mask, VT) ||
9982 isCommutedSHUFPMask(Mask, VT));
9987 //===----------------------------------------------------------------------===//
9988 // X86 Scheduler Hooks
9989 //===----------------------------------------------------------------------===//
9991 // private utility function
9993 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
9994 MachineBasicBlock *MBB,
10001 TargetRegisterClass *RC,
10002 bool invSrc) const {
10003 // For the atomic bitwise operator, we generate
10006 // ld t1 = [bitinstr.addr]
10007 // op t2 = t1, [bitinstr.val]
10009 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10011 // fallthrough -->nextMBB
10012 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10013 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10014 MachineFunction::iterator MBBIter = MBB;
10017 /// First build the CFG
10018 MachineFunction *F = MBB->getParent();
10019 MachineBasicBlock *thisMBB = MBB;
10020 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10021 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10022 F->insert(MBBIter, newMBB);
10023 F->insert(MBBIter, nextMBB);
10025 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10026 nextMBB->splice(nextMBB->begin(), thisMBB,
10027 llvm::next(MachineBasicBlock::iterator(bInstr)),
10029 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10031 // Update thisMBB to fall through to newMBB
10032 thisMBB->addSuccessor(newMBB);
10034 // newMBB jumps to itself and fall through to nextMBB
10035 newMBB->addSuccessor(nextMBB);
10036 newMBB->addSuccessor(newMBB);
10038 // Insert instructions into newMBB based on incoming instruction
10039 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10040 "unexpected number of operands");
10041 DebugLoc dl = bInstr->getDebugLoc();
10042 MachineOperand& destOper = bInstr->getOperand(0);
10043 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10044 int numArgs = bInstr->getNumOperands() - 1;
10045 for (int i=0; i < numArgs; ++i)
10046 argOpers[i] = &bInstr->getOperand(i+1);
10048 // x86 address has 4 operands: base, index, scale, and displacement
10049 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10050 int valArgIndx = lastAddrIndx + 1;
10052 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10053 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
10054 for (int i=0; i <= lastAddrIndx; ++i)
10055 (*MIB).addOperand(*argOpers[i]);
10057 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
10059 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
10064 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10065 assert((argOpers[valArgIndx]->isReg() ||
10066 argOpers[valArgIndx]->isImm()) &&
10067 "invalid operand");
10068 if (argOpers[valArgIndx]->isReg())
10069 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
10071 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
10073 (*MIB).addOperand(*argOpers[valArgIndx]);
10075 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
10078 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
10079 for (int i=0; i <= lastAddrIndx; ++i)
10080 (*MIB).addOperand(*argOpers[i]);
10082 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10083 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10084 bInstr->memoperands_end());
10086 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10087 MIB.addReg(EAXreg);
10090 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10092 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10096 // private utility function: 64 bit atomics on 32 bit host.
10097 MachineBasicBlock *
10098 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
10099 MachineBasicBlock *MBB,
10104 bool invSrc) const {
10105 // For the atomic bitwise operator, we generate
10106 // thisMBB (instructions are in pairs, except cmpxchg8b)
10107 // ld t1,t2 = [bitinstr.addr]
10109 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
10110 // op t5, t6 <- out1, out2, [bitinstr.val]
10111 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
10112 // mov ECX, EBX <- t5, t6
10113 // mov EAX, EDX <- t1, t2
10114 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
10115 // mov t3, t4 <- EAX, EDX
10117 // result in out1, out2
10118 // fallthrough -->nextMBB
10120 const TargetRegisterClass *RC = X86::GR32RegisterClass;
10121 const unsigned LoadOpc = X86::MOV32rm;
10122 const unsigned NotOpc = X86::NOT32r;
10123 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10124 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10125 MachineFunction::iterator MBBIter = MBB;
10128 /// First build the CFG
10129 MachineFunction *F = MBB->getParent();
10130 MachineBasicBlock *thisMBB = MBB;
10131 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10132 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10133 F->insert(MBBIter, newMBB);
10134 F->insert(MBBIter, nextMBB);
10136 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10137 nextMBB->splice(nextMBB->begin(), thisMBB,
10138 llvm::next(MachineBasicBlock::iterator(bInstr)),
10140 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10142 // Update thisMBB to fall through to newMBB
10143 thisMBB->addSuccessor(newMBB);
10145 // newMBB jumps to itself and fall through to nextMBB
10146 newMBB->addSuccessor(nextMBB);
10147 newMBB->addSuccessor(newMBB);
10149 DebugLoc dl = bInstr->getDebugLoc();
10150 // Insert instructions into newMBB based on incoming instruction
10151 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
10152 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
10153 "unexpected number of operands");
10154 MachineOperand& dest1Oper = bInstr->getOperand(0);
10155 MachineOperand& dest2Oper = bInstr->getOperand(1);
10156 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10157 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
10158 argOpers[i] = &bInstr->getOperand(i+2);
10160 // We use some of the operands multiple times, so conservatively just
10161 // clear any kill flags that might be present.
10162 if (argOpers[i]->isReg() && argOpers[i]->isUse())
10163 argOpers[i]->setIsKill(false);
10166 // x86 address has 5 operands: base, index, scale, displacement, and segment.
10167 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10169 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10170 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
10171 for (int i=0; i <= lastAddrIndx; ++i)
10172 (*MIB).addOperand(*argOpers[i]);
10173 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10174 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
10175 // add 4 to displacement.
10176 for (int i=0; i <= lastAddrIndx-2; ++i)
10177 (*MIB).addOperand(*argOpers[i]);
10178 MachineOperand newOp3 = *(argOpers[3]);
10179 if (newOp3.isImm())
10180 newOp3.setImm(newOp3.getImm()+4);
10182 newOp3.setOffset(newOp3.getOffset()+4);
10183 (*MIB).addOperand(newOp3);
10184 (*MIB).addOperand(*argOpers[lastAddrIndx]);
10186 // t3/4 are defined later, at the bottom of the loop
10187 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
10188 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
10189 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
10190 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
10191 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
10192 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
10194 // The subsequent operations should be using the destination registers of
10195 //the PHI instructions.
10197 t1 = F->getRegInfo().createVirtualRegister(RC);
10198 t2 = F->getRegInfo().createVirtualRegister(RC);
10199 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
10200 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
10202 t1 = dest1Oper.getReg();
10203 t2 = dest2Oper.getReg();
10206 int valArgIndx = lastAddrIndx + 1;
10207 assert((argOpers[valArgIndx]->isReg() ||
10208 argOpers[valArgIndx]->isImm()) &&
10209 "invalid operand");
10210 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
10211 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
10212 if (argOpers[valArgIndx]->isReg())
10213 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
10215 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
10216 if (regOpcL != X86::MOV32rr)
10218 (*MIB).addOperand(*argOpers[valArgIndx]);
10219 assert(argOpers[valArgIndx + 1]->isReg() ==
10220 argOpers[valArgIndx]->isReg());
10221 assert(argOpers[valArgIndx + 1]->isImm() ==
10222 argOpers[valArgIndx]->isImm());
10223 if (argOpers[valArgIndx + 1]->isReg())
10224 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
10226 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
10227 if (regOpcH != X86::MOV32rr)
10229 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
10231 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
10233 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
10236 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
10238 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
10241 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
10242 for (int i=0; i <= lastAddrIndx; ++i)
10243 (*MIB).addOperand(*argOpers[i]);
10245 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10246 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10247 bInstr->memoperands_end());
10249 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
10250 MIB.addReg(X86::EAX);
10251 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
10252 MIB.addReg(X86::EDX);
10255 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10257 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10261 // private utility function
10262 MachineBasicBlock *
10263 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
10264 MachineBasicBlock *MBB,
10265 unsigned cmovOpc) const {
10266 // For the atomic min/max operator, we generate
10269 // ld t1 = [min/max.addr]
10270 // mov t2 = [min/max.val]
10272 // cmov[cond] t2 = t1
10274 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10276 // fallthrough -->nextMBB
10278 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10279 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10280 MachineFunction::iterator MBBIter = MBB;
10283 /// First build the CFG
10284 MachineFunction *F = MBB->getParent();
10285 MachineBasicBlock *thisMBB = MBB;
10286 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10287 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10288 F->insert(MBBIter, newMBB);
10289 F->insert(MBBIter, nextMBB);
10291 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10292 nextMBB->splice(nextMBB->begin(), thisMBB,
10293 llvm::next(MachineBasicBlock::iterator(mInstr)),
10295 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10297 // Update thisMBB to fall through to newMBB
10298 thisMBB->addSuccessor(newMBB);
10300 // newMBB jumps to newMBB and fall through to nextMBB
10301 newMBB->addSuccessor(nextMBB);
10302 newMBB->addSuccessor(newMBB);
10304 DebugLoc dl = mInstr->getDebugLoc();
10305 // Insert instructions into newMBB based on incoming instruction
10306 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10307 "unexpected number of operands");
10308 MachineOperand& destOper = mInstr->getOperand(0);
10309 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10310 int numArgs = mInstr->getNumOperands() - 1;
10311 for (int i=0; i < numArgs; ++i)
10312 argOpers[i] = &mInstr->getOperand(i+1);
10314 // x86 address has 4 operands: base, index, scale, and displacement
10315 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10316 int valArgIndx = lastAddrIndx + 1;
10318 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10319 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
10320 for (int i=0; i <= lastAddrIndx; ++i)
10321 (*MIB).addOperand(*argOpers[i]);
10323 // We only support register and immediate values
10324 assert((argOpers[valArgIndx]->isReg() ||
10325 argOpers[valArgIndx]->isImm()) &&
10326 "invalid operand");
10328 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10329 if (argOpers[valArgIndx]->isReg())
10330 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
10332 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
10333 (*MIB).addOperand(*argOpers[valArgIndx]);
10335 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
10338 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
10343 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
10344 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
10348 // Cmp and exchange if none has modified the memory location
10349 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
10350 for (int i=0; i <= lastAddrIndx; ++i)
10351 (*MIB).addOperand(*argOpers[i]);
10353 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10354 (*MIB).setMemRefs(mInstr->memoperands_begin(),
10355 mInstr->memoperands_end());
10357 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10358 MIB.addReg(X86::EAX);
10361 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10363 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
10367 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
10368 // or XMM0_V32I8 in AVX all of this code can be replaced with that
10369 // in the .td file.
10370 MachineBasicBlock *
10371 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
10372 unsigned numArgs, bool memArg) const {
10373 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
10374 "Target must have SSE4.2 or AVX features enabled");
10376 DebugLoc dl = MI->getDebugLoc();
10377 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10379 if (!Subtarget->hasAVX()) {
10381 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
10383 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
10386 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
10388 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
10391 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
10392 for (unsigned i = 0; i < numArgs; ++i) {
10393 MachineOperand &Op = MI->getOperand(i+1);
10394 if (!(Op.isReg() && Op.isImplicit()))
10395 MIB.addOperand(Op);
10397 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
10398 .addReg(X86::XMM0);
10400 MI->eraseFromParent();
10404 MachineBasicBlock *
10405 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
10406 DebugLoc dl = MI->getDebugLoc();
10407 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10409 // Address into RAX/EAX, other two args into ECX, EDX.
10410 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
10411 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10412 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
10413 for (int i = 0; i < X86::AddrNumOperands; ++i)
10414 MIB.addOperand(MI->getOperand(i));
10416 unsigned ValOps = X86::AddrNumOperands;
10417 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
10418 .addReg(MI->getOperand(ValOps).getReg());
10419 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
10420 .addReg(MI->getOperand(ValOps+1).getReg());
10422 // The instruction doesn't actually take any operands though.
10423 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
10425 MI->eraseFromParent(); // The pseudo is gone now.
10429 MachineBasicBlock *
10430 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
10431 DebugLoc dl = MI->getDebugLoc();
10432 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10434 // First arg in ECX, the second in EAX.
10435 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
10436 .addReg(MI->getOperand(0).getReg());
10437 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
10438 .addReg(MI->getOperand(1).getReg());
10440 // The instruction doesn't actually take any operands though.
10441 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
10443 MI->eraseFromParent(); // The pseudo is gone now.
10447 MachineBasicBlock *
10448 X86TargetLowering::EmitVAARG64WithCustomInserter(
10450 MachineBasicBlock *MBB) const {
10451 // Emit va_arg instruction on X86-64.
10453 // Operands to this pseudo-instruction:
10454 // 0 ) Output : destination address (reg)
10455 // 1-5) Input : va_list address (addr, i64mem)
10456 // 6 ) ArgSize : Size (in bytes) of vararg type
10457 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
10458 // 8 ) Align : Alignment of type
10459 // 9 ) EFLAGS (implicit-def)
10461 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
10462 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
10464 unsigned DestReg = MI->getOperand(0).getReg();
10465 MachineOperand &Base = MI->getOperand(1);
10466 MachineOperand &Scale = MI->getOperand(2);
10467 MachineOperand &Index = MI->getOperand(3);
10468 MachineOperand &Disp = MI->getOperand(4);
10469 MachineOperand &Segment = MI->getOperand(5);
10470 unsigned ArgSize = MI->getOperand(6).getImm();
10471 unsigned ArgMode = MI->getOperand(7).getImm();
10472 unsigned Align = MI->getOperand(8).getImm();
10474 // Memory Reference
10475 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
10476 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
10477 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
10479 // Machine Information
10480 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10481 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
10482 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
10483 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
10484 DebugLoc DL = MI->getDebugLoc();
10486 // struct va_list {
10489 // i64 overflow_area (address)
10490 // i64 reg_save_area (address)
10492 // sizeof(va_list) = 24
10493 // alignment(va_list) = 8
10495 unsigned TotalNumIntRegs = 6;
10496 unsigned TotalNumXMMRegs = 8;
10497 bool UseGPOffset = (ArgMode == 1);
10498 bool UseFPOffset = (ArgMode == 2);
10499 unsigned MaxOffset = TotalNumIntRegs * 8 +
10500 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
10502 /* Align ArgSize to a multiple of 8 */
10503 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
10504 bool NeedsAlign = (Align > 8);
10506 MachineBasicBlock *thisMBB = MBB;
10507 MachineBasicBlock *overflowMBB;
10508 MachineBasicBlock *offsetMBB;
10509 MachineBasicBlock *endMBB;
10511 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
10512 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
10513 unsigned OffsetReg = 0;
10515 if (!UseGPOffset && !UseFPOffset) {
10516 // If we only pull from the overflow region, we don't create a branch.
10517 // We don't need to alter control flow.
10518 OffsetDestReg = 0; // unused
10519 OverflowDestReg = DestReg;
10522 overflowMBB = thisMBB;
10525 // First emit code to check if gp_offset (or fp_offset) is below the bound.
10526 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
10527 // If not, pull from overflow_area. (branch to overflowMBB)
10532 // offsetMBB overflowMBB
10537 // Registers for the PHI in endMBB
10538 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
10539 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
10541 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10542 MachineFunction *MF = MBB->getParent();
10543 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10544 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10545 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10547 MachineFunction::iterator MBBIter = MBB;
10550 // Insert the new basic blocks
10551 MF->insert(MBBIter, offsetMBB);
10552 MF->insert(MBBIter, overflowMBB);
10553 MF->insert(MBBIter, endMBB);
10555 // Transfer the remainder of MBB and its successor edges to endMBB.
10556 endMBB->splice(endMBB->begin(), thisMBB,
10557 llvm::next(MachineBasicBlock::iterator(MI)),
10559 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10561 // Make offsetMBB and overflowMBB successors of thisMBB
10562 thisMBB->addSuccessor(offsetMBB);
10563 thisMBB->addSuccessor(overflowMBB);
10565 // endMBB is a successor of both offsetMBB and overflowMBB
10566 offsetMBB->addSuccessor(endMBB);
10567 overflowMBB->addSuccessor(endMBB);
10569 // Load the offset value into a register
10570 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
10571 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
10575 .addDisp(Disp, UseFPOffset ? 4 : 0)
10576 .addOperand(Segment)
10577 .setMemRefs(MMOBegin, MMOEnd);
10579 // Check if there is enough room left to pull this argument.
10580 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
10582 .addImm(MaxOffset + 8 - ArgSizeA8);
10584 // Branch to "overflowMBB" if offset >= max
10585 // Fall through to "offsetMBB" otherwise
10586 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
10587 .addMBB(overflowMBB);
10590 // In offsetMBB, emit code to use the reg_save_area.
10592 assert(OffsetReg != 0);
10594 // Read the reg_save_area address.
10595 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
10596 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
10601 .addOperand(Segment)
10602 .setMemRefs(MMOBegin, MMOEnd);
10604 // Zero-extend the offset
10605 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
10606 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
10609 .addImm(X86::sub_32bit);
10611 // Add the offset to the reg_save_area to get the final address.
10612 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
10613 .addReg(OffsetReg64)
10614 .addReg(RegSaveReg);
10616 // Compute the offset for the next argument
10617 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
10618 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
10620 .addImm(UseFPOffset ? 16 : 8);
10622 // Store it back into the va_list.
10623 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
10627 .addDisp(Disp, UseFPOffset ? 4 : 0)
10628 .addOperand(Segment)
10629 .addReg(NextOffsetReg)
10630 .setMemRefs(MMOBegin, MMOEnd);
10633 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
10638 // Emit code to use overflow area
10641 // Load the overflow_area address into a register.
10642 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
10643 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
10648 .addOperand(Segment)
10649 .setMemRefs(MMOBegin, MMOEnd);
10651 // If we need to align it, do so. Otherwise, just copy the address
10652 // to OverflowDestReg.
10654 // Align the overflow address
10655 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
10656 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
10658 // aligned_addr = (addr + (align-1)) & ~(align-1)
10659 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
10660 .addReg(OverflowAddrReg)
10663 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
10665 .addImm(~(uint64_t)(Align-1));
10667 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
10668 .addReg(OverflowAddrReg);
10671 // Compute the next overflow address after this argument.
10672 // (the overflow address should be kept 8-byte aligned)
10673 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
10674 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
10675 .addReg(OverflowDestReg)
10676 .addImm(ArgSizeA8);
10678 // Store the new overflow address.
10679 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
10684 .addOperand(Segment)
10685 .addReg(NextAddrReg)
10686 .setMemRefs(MMOBegin, MMOEnd);
10688 // If we branched, emit the PHI to the front of endMBB.
10690 BuildMI(*endMBB, endMBB->begin(), DL,
10691 TII->get(X86::PHI), DestReg)
10692 .addReg(OffsetDestReg).addMBB(offsetMBB)
10693 .addReg(OverflowDestReg).addMBB(overflowMBB);
10696 // Erase the pseudo instruction
10697 MI->eraseFromParent();
10702 MachineBasicBlock *
10703 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
10705 MachineBasicBlock *MBB) const {
10706 // Emit code to save XMM registers to the stack. The ABI says that the
10707 // number of registers to save is given in %al, so it's theoretically
10708 // possible to do an indirect jump trick to avoid saving all of them,
10709 // however this code takes a simpler approach and just executes all
10710 // of the stores if %al is non-zero. It's less code, and it's probably
10711 // easier on the hardware branch predictor, and stores aren't all that
10712 // expensive anyway.
10714 // Create the new basic blocks. One block contains all the XMM stores,
10715 // and one block is the final destination regardless of whether any
10716 // stores were performed.
10717 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10718 MachineFunction *F = MBB->getParent();
10719 MachineFunction::iterator MBBIter = MBB;
10721 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
10722 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
10723 F->insert(MBBIter, XMMSaveMBB);
10724 F->insert(MBBIter, EndMBB);
10726 // Transfer the remainder of MBB and its successor edges to EndMBB.
10727 EndMBB->splice(EndMBB->begin(), MBB,
10728 llvm::next(MachineBasicBlock::iterator(MI)),
10730 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
10732 // The original block will now fall through to the XMM save block.
10733 MBB->addSuccessor(XMMSaveMBB);
10734 // The XMMSaveMBB will fall through to the end block.
10735 XMMSaveMBB->addSuccessor(EndMBB);
10737 // Now add the instructions.
10738 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10739 DebugLoc DL = MI->getDebugLoc();
10741 unsigned CountReg = MI->getOperand(0).getReg();
10742 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
10743 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
10745 if (!Subtarget->isTargetWin64()) {
10746 // If %al is 0, branch around the XMM save block.
10747 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
10748 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
10749 MBB->addSuccessor(EndMBB);
10752 // In the XMM save block, save all the XMM argument registers.
10753 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
10754 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
10755 MachineMemOperand *MMO =
10756 F->getMachineMemOperand(
10757 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
10758 MachineMemOperand::MOStore,
10759 /*Size=*/16, /*Align=*/16);
10760 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
10761 .addFrameIndex(RegSaveFrameIndex)
10762 .addImm(/*Scale=*/1)
10763 .addReg(/*IndexReg=*/0)
10764 .addImm(/*Disp=*/Offset)
10765 .addReg(/*Segment=*/0)
10766 .addReg(MI->getOperand(i).getReg())
10767 .addMemOperand(MMO);
10770 MI->eraseFromParent(); // The pseudo instruction is gone now.
10775 MachineBasicBlock *
10776 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
10777 MachineBasicBlock *BB) const {
10778 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10779 DebugLoc DL = MI->getDebugLoc();
10781 // To "insert" a SELECT_CC instruction, we actually have to insert the
10782 // diamond control-flow pattern. The incoming instruction knows the
10783 // destination vreg to set, the condition code register to branch on, the
10784 // true/false values to select between, and a branch opcode to use.
10785 const BasicBlock *LLVM_BB = BB->getBasicBlock();
10786 MachineFunction::iterator It = BB;
10792 // cmpTY ccX, r1, r2
10794 // fallthrough --> copy0MBB
10795 MachineBasicBlock *thisMBB = BB;
10796 MachineFunction *F = BB->getParent();
10797 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
10798 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
10799 F->insert(It, copy0MBB);
10800 F->insert(It, sinkMBB);
10802 // If the EFLAGS register isn't dead in the terminator, then claim that it's
10803 // live into the sink and copy blocks.
10804 const MachineFunction *MF = BB->getParent();
10805 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
10806 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
10808 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
10809 const MachineOperand &MO = MI->getOperand(I);
10810 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
10811 unsigned Reg = MO.getReg();
10812 if (Reg != X86::EFLAGS) continue;
10813 copy0MBB->addLiveIn(Reg);
10814 sinkMBB->addLiveIn(Reg);
10817 // Transfer the remainder of BB and its successor edges to sinkMBB.
10818 sinkMBB->splice(sinkMBB->begin(), BB,
10819 llvm::next(MachineBasicBlock::iterator(MI)),
10821 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
10823 // Add the true and fallthrough blocks as its successors.
10824 BB->addSuccessor(copy0MBB);
10825 BB->addSuccessor(sinkMBB);
10827 // Create the conditional branch instruction.
10829 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
10830 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
10833 // %FalseValue = ...
10834 // # fallthrough to sinkMBB
10835 copy0MBB->addSuccessor(sinkMBB);
10838 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
10840 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
10841 TII->get(X86::PHI), MI->getOperand(0).getReg())
10842 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
10843 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
10845 MI->eraseFromParent(); // The pseudo instruction is gone now.
10849 MachineBasicBlock *
10850 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
10851 MachineBasicBlock *BB) const {
10852 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10853 DebugLoc DL = MI->getDebugLoc();
10855 assert(!Subtarget->isTargetEnvMacho());
10857 // The lowering is pretty easy: we're just emitting the call to _alloca. The
10858 // non-trivial part is impdef of ESP.
10860 if (Subtarget->isTargetWin64()) {
10861 if (Subtarget->isTargetCygMing()) {
10862 // ___chkstk(Mingw64):
10863 // Clobbers R10, R11, RAX and EFLAGS.
10865 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
10866 .addExternalSymbol("___chkstk")
10867 .addReg(X86::RAX, RegState::Implicit)
10868 .addReg(X86::RSP, RegState::Implicit)
10869 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
10870 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
10871 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
10873 // __chkstk(MSVCRT): does not update stack pointer.
10874 // Clobbers R10, R11 and EFLAGS.
10875 // FIXME: RAX(allocated size) might be reused and not killed.
10876 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
10877 .addExternalSymbol("__chkstk")
10878 .addReg(X86::RAX, RegState::Implicit)
10879 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
10880 // RAX has the offset to subtracted from RSP.
10881 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
10886 const char *StackProbeSymbol =
10887 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
10889 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
10890 .addExternalSymbol(StackProbeSymbol)
10891 .addReg(X86::EAX, RegState::Implicit)
10892 .addReg(X86::ESP, RegState::Implicit)
10893 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
10894 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
10895 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
10898 MI->eraseFromParent(); // The pseudo instruction is gone now.
10902 MachineBasicBlock *
10903 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
10904 MachineBasicBlock *BB) const {
10905 // This is pretty easy. We're taking the value that we received from
10906 // our load from the relocation, sticking it in either RDI (x86-64)
10907 // or EAX and doing an indirect call. The return value will then
10908 // be in the normal return register.
10909 const X86InstrInfo *TII
10910 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
10911 DebugLoc DL = MI->getDebugLoc();
10912 MachineFunction *F = BB->getParent();
10914 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
10915 assert(MI->getOperand(3).isGlobal() && "This should be a global");
10917 if (Subtarget->is64Bit()) {
10918 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10919 TII->get(X86::MOV64rm), X86::RDI)
10921 .addImm(0).addReg(0)
10922 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10923 MI->getOperand(3).getTargetFlags())
10925 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
10926 addDirectMem(MIB, X86::RDI);
10927 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
10928 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10929 TII->get(X86::MOV32rm), X86::EAX)
10931 .addImm(0).addReg(0)
10932 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10933 MI->getOperand(3).getTargetFlags())
10935 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
10936 addDirectMem(MIB, X86::EAX);
10938 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10939 TII->get(X86::MOV32rm), X86::EAX)
10940 .addReg(TII->getGlobalBaseReg(F))
10941 .addImm(0).addReg(0)
10942 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10943 MI->getOperand(3).getTargetFlags())
10945 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
10946 addDirectMem(MIB, X86::EAX);
10949 MI->eraseFromParent(); // The pseudo instruction is gone now.
10953 MachineBasicBlock *
10954 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
10955 MachineBasicBlock *BB) const {
10956 switch (MI->getOpcode()) {
10957 default: assert(false && "Unexpected instr type to insert");
10958 case X86::TAILJMPd64:
10959 case X86::TAILJMPr64:
10960 case X86::TAILJMPm64:
10961 assert(!"TAILJMP64 would not be touched here.");
10962 case X86::TCRETURNdi64:
10963 case X86::TCRETURNri64:
10964 case X86::TCRETURNmi64:
10965 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
10966 // On AMD64, additional defs should be added before register allocation.
10967 if (!Subtarget->isTargetWin64()) {
10968 MI->addRegisterDefined(X86::RSI);
10969 MI->addRegisterDefined(X86::RDI);
10970 MI->addRegisterDefined(X86::XMM6);
10971 MI->addRegisterDefined(X86::XMM7);
10972 MI->addRegisterDefined(X86::XMM8);
10973 MI->addRegisterDefined(X86::XMM9);
10974 MI->addRegisterDefined(X86::XMM10);
10975 MI->addRegisterDefined(X86::XMM11);
10976 MI->addRegisterDefined(X86::XMM12);
10977 MI->addRegisterDefined(X86::XMM13);
10978 MI->addRegisterDefined(X86::XMM14);
10979 MI->addRegisterDefined(X86::XMM15);
10982 case X86::WIN_ALLOCA:
10983 return EmitLoweredWinAlloca(MI, BB);
10984 case X86::TLSCall_32:
10985 case X86::TLSCall_64:
10986 return EmitLoweredTLSCall(MI, BB);
10987 case X86::CMOV_GR8:
10988 case X86::CMOV_FR32:
10989 case X86::CMOV_FR64:
10990 case X86::CMOV_V4F32:
10991 case X86::CMOV_V2F64:
10992 case X86::CMOV_V2I64:
10993 case X86::CMOV_GR16:
10994 case X86::CMOV_GR32:
10995 case X86::CMOV_RFP32:
10996 case X86::CMOV_RFP64:
10997 case X86::CMOV_RFP80:
10998 return EmitLoweredSelect(MI, BB);
11000 case X86::FP32_TO_INT16_IN_MEM:
11001 case X86::FP32_TO_INT32_IN_MEM:
11002 case X86::FP32_TO_INT64_IN_MEM:
11003 case X86::FP64_TO_INT16_IN_MEM:
11004 case X86::FP64_TO_INT32_IN_MEM:
11005 case X86::FP64_TO_INT64_IN_MEM:
11006 case X86::FP80_TO_INT16_IN_MEM:
11007 case X86::FP80_TO_INT32_IN_MEM:
11008 case X86::FP80_TO_INT64_IN_MEM: {
11009 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11010 DebugLoc DL = MI->getDebugLoc();
11012 // Change the floating point control register to use "round towards zero"
11013 // mode when truncating to an integer value.
11014 MachineFunction *F = BB->getParent();
11015 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
11016 addFrameReference(BuildMI(*BB, MI, DL,
11017 TII->get(X86::FNSTCW16m)), CWFrameIdx);
11019 // Load the old value of the high byte of the control word...
11021 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
11022 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
11025 // Set the high part to be round to zero...
11026 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
11029 // Reload the modified control word now...
11030 addFrameReference(BuildMI(*BB, MI, DL,
11031 TII->get(X86::FLDCW16m)), CWFrameIdx);
11033 // Restore the memory image of control word to original value
11034 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
11037 // Get the X86 opcode to use.
11039 switch (MI->getOpcode()) {
11040 default: llvm_unreachable("illegal opcode!");
11041 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
11042 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
11043 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
11044 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
11045 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
11046 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
11047 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
11048 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
11049 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
11053 MachineOperand &Op = MI->getOperand(0);
11055 AM.BaseType = X86AddressMode::RegBase;
11056 AM.Base.Reg = Op.getReg();
11058 AM.BaseType = X86AddressMode::FrameIndexBase;
11059 AM.Base.FrameIndex = Op.getIndex();
11061 Op = MI->getOperand(1);
11063 AM.Scale = Op.getImm();
11064 Op = MI->getOperand(2);
11066 AM.IndexReg = Op.getImm();
11067 Op = MI->getOperand(3);
11068 if (Op.isGlobal()) {
11069 AM.GV = Op.getGlobal();
11071 AM.Disp = Op.getImm();
11073 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
11074 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
11076 // Reload the original control word now.
11077 addFrameReference(BuildMI(*BB, MI, DL,
11078 TII->get(X86::FLDCW16m)), CWFrameIdx);
11080 MI->eraseFromParent(); // The pseudo instruction is gone now.
11083 // String/text processing lowering.
11084 case X86::PCMPISTRM128REG:
11085 case X86::VPCMPISTRM128REG:
11086 return EmitPCMP(MI, BB, 3, false /* in-mem */);
11087 case X86::PCMPISTRM128MEM:
11088 case X86::VPCMPISTRM128MEM:
11089 return EmitPCMP(MI, BB, 3, true /* in-mem */);
11090 case X86::PCMPESTRM128REG:
11091 case X86::VPCMPESTRM128REG:
11092 return EmitPCMP(MI, BB, 5, false /* in mem */);
11093 case X86::PCMPESTRM128MEM:
11094 case X86::VPCMPESTRM128MEM:
11095 return EmitPCMP(MI, BB, 5, true /* in mem */);
11097 // Thread synchronization.
11099 return EmitMonitor(MI, BB);
11101 return EmitMwait(MI, BB);
11103 // Atomic Lowering.
11104 case X86::ATOMAND32:
11105 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11106 X86::AND32ri, X86::MOV32rm,
11108 X86::NOT32r, X86::EAX,
11109 X86::GR32RegisterClass);
11110 case X86::ATOMOR32:
11111 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
11112 X86::OR32ri, X86::MOV32rm,
11114 X86::NOT32r, X86::EAX,
11115 X86::GR32RegisterClass);
11116 case X86::ATOMXOR32:
11117 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
11118 X86::XOR32ri, X86::MOV32rm,
11120 X86::NOT32r, X86::EAX,
11121 X86::GR32RegisterClass);
11122 case X86::ATOMNAND32:
11123 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11124 X86::AND32ri, X86::MOV32rm,
11126 X86::NOT32r, X86::EAX,
11127 X86::GR32RegisterClass, true);
11128 case X86::ATOMMIN32:
11129 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
11130 case X86::ATOMMAX32:
11131 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
11132 case X86::ATOMUMIN32:
11133 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
11134 case X86::ATOMUMAX32:
11135 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
11137 case X86::ATOMAND16:
11138 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11139 X86::AND16ri, X86::MOV16rm,
11141 X86::NOT16r, X86::AX,
11142 X86::GR16RegisterClass);
11143 case X86::ATOMOR16:
11144 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
11145 X86::OR16ri, X86::MOV16rm,
11147 X86::NOT16r, X86::AX,
11148 X86::GR16RegisterClass);
11149 case X86::ATOMXOR16:
11150 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
11151 X86::XOR16ri, X86::MOV16rm,
11153 X86::NOT16r, X86::AX,
11154 X86::GR16RegisterClass);
11155 case X86::ATOMNAND16:
11156 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11157 X86::AND16ri, X86::MOV16rm,
11159 X86::NOT16r, X86::AX,
11160 X86::GR16RegisterClass, true);
11161 case X86::ATOMMIN16:
11162 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
11163 case X86::ATOMMAX16:
11164 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
11165 case X86::ATOMUMIN16:
11166 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
11167 case X86::ATOMUMAX16:
11168 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
11170 case X86::ATOMAND8:
11171 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11172 X86::AND8ri, X86::MOV8rm,
11174 X86::NOT8r, X86::AL,
11175 X86::GR8RegisterClass);
11177 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
11178 X86::OR8ri, X86::MOV8rm,
11180 X86::NOT8r, X86::AL,
11181 X86::GR8RegisterClass);
11182 case X86::ATOMXOR8:
11183 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
11184 X86::XOR8ri, X86::MOV8rm,
11186 X86::NOT8r, X86::AL,
11187 X86::GR8RegisterClass);
11188 case X86::ATOMNAND8:
11189 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11190 X86::AND8ri, X86::MOV8rm,
11192 X86::NOT8r, X86::AL,
11193 X86::GR8RegisterClass, true);
11194 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
11195 // This group is for 64-bit host.
11196 case X86::ATOMAND64:
11197 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
11198 X86::AND64ri32, X86::MOV64rm,
11200 X86::NOT64r, X86::RAX,
11201 X86::GR64RegisterClass);
11202 case X86::ATOMOR64:
11203 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
11204 X86::OR64ri32, X86::MOV64rm,
11206 X86::NOT64r, X86::RAX,
11207 X86::GR64RegisterClass);
11208 case X86::ATOMXOR64:
11209 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
11210 X86::XOR64ri32, X86::MOV64rm,
11212 X86::NOT64r, X86::RAX,
11213 X86::GR64RegisterClass);
11214 case X86::ATOMNAND64:
11215 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
11216 X86::AND64ri32, X86::MOV64rm,
11218 X86::NOT64r, X86::RAX,
11219 X86::GR64RegisterClass, true);
11220 case X86::ATOMMIN64:
11221 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
11222 case X86::ATOMMAX64:
11223 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
11224 case X86::ATOMUMIN64:
11225 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
11226 case X86::ATOMUMAX64:
11227 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
11229 // This group does 64-bit operations on a 32-bit host.
11230 case X86::ATOMAND6432:
11231 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11232 X86::AND32rr, X86::AND32rr,
11233 X86::AND32ri, X86::AND32ri,
11235 case X86::ATOMOR6432:
11236 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11237 X86::OR32rr, X86::OR32rr,
11238 X86::OR32ri, X86::OR32ri,
11240 case X86::ATOMXOR6432:
11241 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11242 X86::XOR32rr, X86::XOR32rr,
11243 X86::XOR32ri, X86::XOR32ri,
11245 case X86::ATOMNAND6432:
11246 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11247 X86::AND32rr, X86::AND32rr,
11248 X86::AND32ri, X86::AND32ri,
11250 case X86::ATOMADD6432:
11251 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11252 X86::ADD32rr, X86::ADC32rr,
11253 X86::ADD32ri, X86::ADC32ri,
11255 case X86::ATOMSUB6432:
11256 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11257 X86::SUB32rr, X86::SBB32rr,
11258 X86::SUB32ri, X86::SBB32ri,
11260 case X86::ATOMSWAP6432:
11261 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11262 X86::MOV32rr, X86::MOV32rr,
11263 X86::MOV32ri, X86::MOV32ri,
11265 case X86::VASTART_SAVE_XMM_REGS:
11266 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
11268 case X86::VAARG_64:
11269 return EmitVAARG64WithCustomInserter(MI, BB);
11273 //===----------------------------------------------------------------------===//
11274 // X86 Optimization Hooks
11275 //===----------------------------------------------------------------------===//
11277 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
11281 const SelectionDAG &DAG,
11282 unsigned Depth) const {
11283 unsigned Opc = Op.getOpcode();
11284 assert((Opc >= ISD::BUILTIN_OP_END ||
11285 Opc == ISD::INTRINSIC_WO_CHAIN ||
11286 Opc == ISD::INTRINSIC_W_CHAIN ||
11287 Opc == ISD::INTRINSIC_VOID) &&
11288 "Should use MaskedValueIsZero if you don't know whether Op"
11289 " is a target node!");
11291 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
11305 // These nodes' second result is a boolean.
11306 if (Op.getResNo() == 0)
11309 case X86ISD::SETCC:
11310 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
11311 Mask.getBitWidth() - 1);
11316 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
11317 unsigned Depth) const {
11318 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
11319 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
11320 return Op.getValueType().getScalarType().getSizeInBits();
11326 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
11327 /// node is a GlobalAddress + offset.
11328 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
11329 const GlobalValue* &GA,
11330 int64_t &Offset) const {
11331 if (N->getOpcode() == X86ISD::Wrapper) {
11332 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
11333 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
11334 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
11338 return TargetLowering::isGAPlusOffset(N, GA, Offset);
11341 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
11342 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
11343 TargetLowering::DAGCombinerInfo &DCI) {
11344 DebugLoc dl = N->getDebugLoc();
11345 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
11346 SDValue V1 = SVOp->getOperand(0);
11347 SDValue V2 = SVOp->getOperand(1);
11348 EVT VT = SVOp->getValueType(0);
11350 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
11351 V2.getOpcode() == ISD::CONCAT_VECTORS) {
11355 // V UNDEF BUILD_VECTOR UNDEF
11357 // CONCAT_VECTOR CONCAT_VECTOR
11360 // RESULT: V + zero extended
11362 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
11363 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
11364 V1.getOperand(1).getOpcode() != ISD::UNDEF)
11367 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
11370 // To match the shuffle mask, the first half of the mask should
11371 // be exactly the first vector, and all the rest a splat with the
11372 // first element of the second one.
11373 int NumElems = VT.getVectorNumElements();
11374 for (int i = 0; i < NumElems/2; ++i)
11375 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
11376 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
11379 // Emit a zeroed vector and insert the desired subvector on its
11381 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl);
11382 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
11383 DAG.getConstant(0, MVT::i32), DAG, dl);
11384 return DCI.CombineTo(N, InsV);
11390 /// PerformShuffleCombine - Performs several different shuffle combines.
11391 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
11392 TargetLowering::DAGCombinerInfo &DCI) {
11393 DebugLoc dl = N->getDebugLoc();
11394 EVT VT = N->getValueType(0);
11396 // Don't create instructions with illegal types after legalize types has run.
11397 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11398 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
11401 // Only handle pure VECTOR_SHUFFLE nodes.
11402 if (VT.getSizeInBits() == 256 && N->getOpcode() == ISD::VECTOR_SHUFFLE)
11403 return PerformShuffleCombine256(N, DAG, DCI);
11405 // Only handle 128 wide vector from here on.
11406 if (VT.getSizeInBits() != 128)
11409 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
11410 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
11411 // consecutive, non-overlapping, and in the right order.
11412 SmallVector<SDValue, 16> Elts;
11413 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
11414 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
11416 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
11419 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
11420 /// generation and convert it from being a bunch of shuffles and extracts
11421 /// to a simple store and scalar loads to extract the elements.
11422 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
11423 const TargetLowering &TLI) {
11424 SDValue InputVector = N->getOperand(0);
11426 // Only operate on vectors of 4 elements, where the alternative shuffling
11427 // gets to be more expensive.
11428 if (InputVector.getValueType() != MVT::v4i32)
11431 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
11432 // single use which is a sign-extend or zero-extend, and all elements are
11434 SmallVector<SDNode *, 4> Uses;
11435 unsigned ExtractedElements = 0;
11436 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
11437 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
11438 if (UI.getUse().getResNo() != InputVector.getResNo())
11441 SDNode *Extract = *UI;
11442 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11445 if (Extract->getValueType(0) != MVT::i32)
11447 if (!Extract->hasOneUse())
11449 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
11450 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
11452 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
11455 // Record which element was extracted.
11456 ExtractedElements |=
11457 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
11459 Uses.push_back(Extract);
11462 // If not all the elements were used, this may not be worthwhile.
11463 if (ExtractedElements != 15)
11466 // Ok, we've now decided to do the transformation.
11467 DebugLoc dl = InputVector.getDebugLoc();
11469 // Store the value to a temporary stack slot.
11470 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
11471 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
11472 MachinePointerInfo(), false, false, 0);
11474 // Replace each use (extract) with a load of the appropriate element.
11475 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
11476 UE = Uses.end(); UI != UE; ++UI) {
11477 SDNode *Extract = *UI;
11479 // cOMpute the element's address.
11480 SDValue Idx = Extract->getOperand(1);
11482 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
11483 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
11484 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
11486 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
11487 StackPtr, OffsetVal);
11489 // Load the scalar.
11490 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
11491 ScalarAddr, MachinePointerInfo(),
11494 // Replace the exact with the load.
11495 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
11498 // The replacement was made in place; don't return anything.
11502 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
11503 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
11504 const X86Subtarget *Subtarget) {
11505 DebugLoc DL = N->getDebugLoc();
11506 SDValue Cond = N->getOperand(0);
11507 // Get the LHS/RHS of the select.
11508 SDValue LHS = N->getOperand(1);
11509 SDValue RHS = N->getOperand(2);
11511 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
11512 // instructions match the semantics of the common C idiom x<y?x:y but not
11513 // x<=y?x:y, because of how they handle negative zero (which can be
11514 // ignored in unsafe-math mode).
11515 if (Subtarget->hasSSE2() &&
11516 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
11517 Cond.getOpcode() == ISD::SETCC) {
11518 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
11520 unsigned Opcode = 0;
11521 // Check for x CC y ? x : y.
11522 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
11523 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
11527 // Converting this to a min would handle NaNs incorrectly, and swapping
11528 // the operands would cause it to handle comparisons between positive
11529 // and negative zero incorrectly.
11530 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
11531 if (!UnsafeFPMath &&
11532 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
11534 std::swap(LHS, RHS);
11536 Opcode = X86ISD::FMIN;
11539 // Converting this to a min would handle comparisons between positive
11540 // and negative zero incorrectly.
11541 if (!UnsafeFPMath &&
11542 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
11544 Opcode = X86ISD::FMIN;
11547 // Converting this to a min would handle both negative zeros and NaNs
11548 // incorrectly, but we can swap the operands to fix both.
11549 std::swap(LHS, RHS);
11553 Opcode = X86ISD::FMIN;
11557 // Converting this to a max would handle comparisons between positive
11558 // and negative zero incorrectly.
11559 if (!UnsafeFPMath &&
11560 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
11562 Opcode = X86ISD::FMAX;
11565 // Converting this to a max would handle NaNs incorrectly, and swapping
11566 // the operands would cause it to handle comparisons between positive
11567 // and negative zero incorrectly.
11568 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
11569 if (!UnsafeFPMath &&
11570 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
11572 std::swap(LHS, RHS);
11574 Opcode = X86ISD::FMAX;
11577 // Converting this to a max would handle both negative zeros and NaNs
11578 // incorrectly, but we can swap the operands to fix both.
11579 std::swap(LHS, RHS);
11583 Opcode = X86ISD::FMAX;
11586 // Check for x CC y ? y : x -- a min/max with reversed arms.
11587 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
11588 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
11592 // Converting this to a min would handle comparisons between positive
11593 // and negative zero incorrectly, and swapping the operands would
11594 // cause it to handle NaNs incorrectly.
11595 if (!UnsafeFPMath &&
11596 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
11597 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
11599 std::swap(LHS, RHS);
11601 Opcode = X86ISD::FMIN;
11604 // Converting this to a min would handle NaNs incorrectly.
11605 if (!UnsafeFPMath &&
11606 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
11608 Opcode = X86ISD::FMIN;
11611 // Converting this to a min would handle both negative zeros and NaNs
11612 // incorrectly, but we can swap the operands to fix both.
11613 std::swap(LHS, RHS);
11617 Opcode = X86ISD::FMIN;
11621 // Converting this to a max would handle NaNs incorrectly.
11622 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
11624 Opcode = X86ISD::FMAX;
11627 // Converting this to a max would handle comparisons between positive
11628 // and negative zero incorrectly, and swapping the operands would
11629 // cause it to handle NaNs incorrectly.
11630 if (!UnsafeFPMath &&
11631 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
11632 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
11634 std::swap(LHS, RHS);
11636 Opcode = X86ISD::FMAX;
11639 // Converting this to a max would handle both negative zeros and NaNs
11640 // incorrectly, but we can swap the operands to fix both.
11641 std::swap(LHS, RHS);
11645 Opcode = X86ISD::FMAX;
11651 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
11654 // If this is a select between two integer constants, try to do some
11656 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
11657 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
11658 // Don't do this for crazy integer types.
11659 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
11660 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
11661 // so that TrueC (the true value) is larger than FalseC.
11662 bool NeedsCondInvert = false;
11664 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
11665 // Efficiently invertible.
11666 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
11667 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
11668 isa<ConstantSDNode>(Cond.getOperand(1))))) {
11669 NeedsCondInvert = true;
11670 std::swap(TrueC, FalseC);
11673 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
11674 if (FalseC->getAPIntValue() == 0 &&
11675 TrueC->getAPIntValue().isPowerOf2()) {
11676 if (NeedsCondInvert) // Invert the condition if needed.
11677 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
11678 DAG.getConstant(1, Cond.getValueType()));
11680 // Zero extend the condition if needed.
11681 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
11683 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
11684 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
11685 DAG.getConstant(ShAmt, MVT::i8));
11688 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
11689 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
11690 if (NeedsCondInvert) // Invert the condition if needed.
11691 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
11692 DAG.getConstant(1, Cond.getValueType()));
11694 // Zero extend the condition if needed.
11695 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
11696 FalseC->getValueType(0), Cond);
11697 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
11698 SDValue(FalseC, 0));
11701 // Optimize cases that will turn into an LEA instruction. This requires
11702 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
11703 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
11704 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
11705 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
11707 bool isFastMultiplier = false;
11709 switch ((unsigned char)Diff) {
11711 case 1: // result = add base, cond
11712 case 2: // result = lea base( , cond*2)
11713 case 3: // result = lea base(cond, cond*2)
11714 case 4: // result = lea base( , cond*4)
11715 case 5: // result = lea base(cond, cond*4)
11716 case 8: // result = lea base( , cond*8)
11717 case 9: // result = lea base(cond, cond*8)
11718 isFastMultiplier = true;
11723 if (isFastMultiplier) {
11724 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
11725 if (NeedsCondInvert) // Invert the condition if needed.
11726 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
11727 DAG.getConstant(1, Cond.getValueType()));
11729 // Zero extend the condition if needed.
11730 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
11732 // Scale the condition by the difference.
11734 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
11735 DAG.getConstant(Diff, Cond.getValueType()));
11737 // Add the base if non-zero.
11738 if (FalseC->getAPIntValue() != 0)
11739 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
11740 SDValue(FalseC, 0));
11750 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
11751 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
11752 TargetLowering::DAGCombinerInfo &DCI) {
11753 DebugLoc DL = N->getDebugLoc();
11755 // If the flag operand isn't dead, don't touch this CMOV.
11756 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
11759 SDValue FalseOp = N->getOperand(0);
11760 SDValue TrueOp = N->getOperand(1);
11761 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
11762 SDValue Cond = N->getOperand(3);
11763 if (CC == X86::COND_E || CC == X86::COND_NE) {
11764 switch (Cond.getOpcode()) {
11768 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
11769 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
11770 return (CC == X86::COND_E) ? FalseOp : TrueOp;
11774 // If this is a select between two integer constants, try to do some
11775 // optimizations. Note that the operands are ordered the opposite of SELECT
11777 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
11778 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
11779 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
11780 // larger than FalseC (the false value).
11781 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
11782 CC = X86::GetOppositeBranchCondition(CC);
11783 std::swap(TrueC, FalseC);
11786 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
11787 // This is efficient for any integer data type (including i8/i16) and
11789 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
11790 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11791 DAG.getConstant(CC, MVT::i8), Cond);
11793 // Zero extend the condition if needed.
11794 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
11796 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
11797 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
11798 DAG.getConstant(ShAmt, MVT::i8));
11799 if (N->getNumValues() == 2) // Dead flag value?
11800 return DCI.CombineTo(N, Cond, SDValue());
11804 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
11805 // for any integer data type, including i8/i16.
11806 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
11807 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11808 DAG.getConstant(CC, MVT::i8), Cond);
11810 // Zero extend the condition if needed.
11811 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
11812 FalseC->getValueType(0), Cond);
11813 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
11814 SDValue(FalseC, 0));
11816 if (N->getNumValues() == 2) // Dead flag value?
11817 return DCI.CombineTo(N, Cond, SDValue());
11821 // Optimize cases that will turn into an LEA instruction. This requires
11822 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
11823 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
11824 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
11825 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
11827 bool isFastMultiplier = false;
11829 switch ((unsigned char)Diff) {
11831 case 1: // result = add base, cond
11832 case 2: // result = lea base( , cond*2)
11833 case 3: // result = lea base(cond, cond*2)
11834 case 4: // result = lea base( , cond*4)
11835 case 5: // result = lea base(cond, cond*4)
11836 case 8: // result = lea base( , cond*8)
11837 case 9: // result = lea base(cond, cond*8)
11838 isFastMultiplier = true;
11843 if (isFastMultiplier) {
11844 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
11845 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11846 DAG.getConstant(CC, MVT::i8), Cond);
11847 // Zero extend the condition if needed.
11848 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
11850 // Scale the condition by the difference.
11852 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
11853 DAG.getConstant(Diff, Cond.getValueType()));
11855 // Add the base if non-zero.
11856 if (FalseC->getAPIntValue() != 0)
11857 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
11858 SDValue(FalseC, 0));
11859 if (N->getNumValues() == 2) // Dead flag value?
11860 return DCI.CombineTo(N, Cond, SDValue());
11870 /// PerformMulCombine - Optimize a single multiply with constant into two
11871 /// in order to implement it with two cheaper instructions, e.g.
11872 /// LEA + SHL, LEA + LEA.
11873 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
11874 TargetLowering::DAGCombinerInfo &DCI) {
11875 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
11878 EVT VT = N->getValueType(0);
11879 if (VT != MVT::i64)
11882 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
11885 uint64_t MulAmt = C->getZExtValue();
11886 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
11889 uint64_t MulAmt1 = 0;
11890 uint64_t MulAmt2 = 0;
11891 if ((MulAmt % 9) == 0) {
11893 MulAmt2 = MulAmt / 9;
11894 } else if ((MulAmt % 5) == 0) {
11896 MulAmt2 = MulAmt / 5;
11897 } else if ((MulAmt % 3) == 0) {
11899 MulAmt2 = MulAmt / 3;
11902 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
11903 DebugLoc DL = N->getDebugLoc();
11905 if (isPowerOf2_64(MulAmt2) &&
11906 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
11907 // If second multiplifer is pow2, issue it first. We want the multiply by
11908 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
11910 std::swap(MulAmt1, MulAmt2);
11913 if (isPowerOf2_64(MulAmt1))
11914 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
11915 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
11917 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
11918 DAG.getConstant(MulAmt1, VT));
11920 if (isPowerOf2_64(MulAmt2))
11921 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
11922 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
11924 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
11925 DAG.getConstant(MulAmt2, VT));
11927 // Do not add new nodes to DAG combiner worklist.
11928 DCI.CombineTo(N, NewMul, false);
11933 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
11934 SDValue N0 = N->getOperand(0);
11935 SDValue N1 = N->getOperand(1);
11936 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
11937 EVT VT = N0.getValueType();
11939 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
11940 // since the result of setcc_c is all zero's or all ones.
11941 if (N1C && N0.getOpcode() == ISD::AND &&
11942 N0.getOperand(1).getOpcode() == ISD::Constant) {
11943 SDValue N00 = N0.getOperand(0);
11944 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
11945 ((N00.getOpcode() == ISD::ANY_EXTEND ||
11946 N00.getOpcode() == ISD::ZERO_EXTEND) &&
11947 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
11948 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
11949 APInt ShAmt = N1C->getAPIntValue();
11950 Mask = Mask.shl(ShAmt);
11952 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
11953 N00, DAG.getConstant(Mask, VT));
11960 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
11962 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
11963 const X86Subtarget *Subtarget) {
11964 EVT VT = N->getValueType(0);
11965 if (!VT.isVector() && VT.isInteger() &&
11966 N->getOpcode() == ISD::SHL)
11967 return PerformSHLCombine(N, DAG);
11969 // On X86 with SSE2 support, we can transform this to a vector shift if
11970 // all elements are shifted by the same amount. We can't do this in legalize
11971 // because the a constant vector is typically transformed to a constant pool
11972 // so we have no knowledge of the shift amount.
11973 if (!Subtarget->hasSSE2())
11976 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
11979 SDValue ShAmtOp = N->getOperand(1);
11980 EVT EltVT = VT.getVectorElementType();
11981 DebugLoc DL = N->getDebugLoc();
11982 SDValue BaseShAmt = SDValue();
11983 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
11984 unsigned NumElts = VT.getVectorNumElements();
11986 for (; i != NumElts; ++i) {
11987 SDValue Arg = ShAmtOp.getOperand(i);
11988 if (Arg.getOpcode() == ISD::UNDEF) continue;
11992 for (; i != NumElts; ++i) {
11993 SDValue Arg = ShAmtOp.getOperand(i);
11994 if (Arg.getOpcode() == ISD::UNDEF) continue;
11995 if (Arg != BaseShAmt) {
11999 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
12000 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
12001 SDValue InVec = ShAmtOp.getOperand(0);
12002 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12003 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12005 for (; i != NumElts; ++i) {
12006 SDValue Arg = InVec.getOperand(i);
12007 if (Arg.getOpcode() == ISD::UNDEF) continue;
12011 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12012 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12013 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
12014 if (C->getZExtValue() == SplatIdx)
12015 BaseShAmt = InVec.getOperand(1);
12018 if (BaseShAmt.getNode() == 0)
12019 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
12020 DAG.getIntPtrConstant(0));
12024 // The shift amount is an i32.
12025 if (EltVT.bitsGT(MVT::i32))
12026 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
12027 else if (EltVT.bitsLT(MVT::i32))
12028 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
12030 // The shift amount is identical so we can do a vector shift.
12031 SDValue ValOp = N->getOperand(0);
12032 switch (N->getOpcode()) {
12034 llvm_unreachable("Unknown shift opcode!");
12037 if (VT == MVT::v2i64)
12038 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12039 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
12041 if (VT == MVT::v4i32)
12042 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12043 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
12045 if (VT == MVT::v8i16)
12046 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12047 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
12051 if (VT == MVT::v4i32)
12052 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12053 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
12055 if (VT == MVT::v8i16)
12056 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12057 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
12061 if (VT == MVT::v2i64)
12062 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12063 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
12065 if (VT == MVT::v4i32)
12066 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12067 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
12069 if (VT == MVT::v8i16)
12070 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12071 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
12079 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
12080 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
12081 // and friends. Likewise for OR -> CMPNEQSS.
12082 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
12083 TargetLowering::DAGCombinerInfo &DCI,
12084 const X86Subtarget *Subtarget) {
12087 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
12088 // we're requiring SSE2 for both.
12089 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
12090 SDValue N0 = N->getOperand(0);
12091 SDValue N1 = N->getOperand(1);
12092 SDValue CMP0 = N0->getOperand(1);
12093 SDValue CMP1 = N1->getOperand(1);
12094 DebugLoc DL = N->getDebugLoc();
12096 // The SETCCs should both refer to the same CMP.
12097 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
12100 SDValue CMP00 = CMP0->getOperand(0);
12101 SDValue CMP01 = CMP0->getOperand(1);
12102 EVT VT = CMP00.getValueType();
12104 if (VT == MVT::f32 || VT == MVT::f64) {
12105 bool ExpectingFlags = false;
12106 // Check for any users that want flags:
12107 for (SDNode::use_iterator UI = N->use_begin(),
12109 !ExpectingFlags && UI != UE; ++UI)
12110 switch (UI->getOpcode()) {
12115 ExpectingFlags = true;
12117 case ISD::CopyToReg:
12118 case ISD::SIGN_EXTEND:
12119 case ISD::ZERO_EXTEND:
12120 case ISD::ANY_EXTEND:
12124 if (!ExpectingFlags) {
12125 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
12126 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
12128 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
12129 X86::CondCode tmp = cc0;
12134 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
12135 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
12136 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
12137 X86ISD::NodeType NTOperator = is64BitFP ?
12138 X86ISD::FSETCCsd : X86ISD::FSETCCss;
12139 // FIXME: need symbolic constants for these magic numbers.
12140 // See X86ATTInstPrinter.cpp:printSSECC().
12141 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
12142 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
12143 DAG.getConstant(x86cc, MVT::i8));
12144 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
12146 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
12147 DAG.getConstant(1, MVT::i32));
12148 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
12149 return OneBitOfTruth;
12157 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
12158 /// so it can be folded inside ANDNP.
12159 static bool CanFoldXORWithAllOnes(const SDNode *N) {
12160 EVT VT = N->getValueType(0);
12162 // Match direct AllOnes for 128 and 256-bit vectors
12163 if (ISD::isBuildVectorAllOnes(N))
12166 // Look through a bit convert.
12167 if (N->getOpcode() == ISD::BITCAST)
12168 N = N->getOperand(0).getNode();
12170 // Sometimes the operand may come from a insert_subvector building a 256-bit
12172 SDValue V1 = N->getOperand(0);
12173 SDValue V2 = N->getOperand(1);
12175 if (VT.getSizeInBits() == 256 &&
12176 N->getOpcode() == ISD::INSERT_SUBVECTOR &&
12177 V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
12178 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
12179 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
12180 ISD::isBuildVectorAllOnes(V2.getNode()))
12186 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
12187 TargetLowering::DAGCombinerInfo &DCI,
12188 const X86Subtarget *Subtarget) {
12189 if (DCI.isBeforeLegalizeOps())
12192 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
12196 // Want to form ANDNP nodes:
12197 // 1) In the hopes of then easily combining them with OR and AND nodes
12198 // to form PBLEND/PSIGN.
12199 // 2) To match ANDN packed intrinsics
12200 EVT VT = N->getValueType(0);
12201 if (VT != MVT::v2i64 && VT != MVT::v4i64)
12204 SDValue N0 = N->getOperand(0);
12205 SDValue N1 = N->getOperand(1);
12206 DebugLoc DL = N->getDebugLoc();
12208 // Check LHS for vnot
12209 if (N0.getOpcode() == ISD::XOR &&
12210 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
12211 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
12212 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
12214 // Check RHS for vnot
12215 if (N1.getOpcode() == ISD::XOR &&
12216 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
12217 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
12218 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
12223 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
12224 TargetLowering::DAGCombinerInfo &DCI,
12225 const X86Subtarget *Subtarget) {
12226 if (DCI.isBeforeLegalizeOps())
12229 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
12233 EVT VT = N->getValueType(0);
12234 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
12237 SDValue N0 = N->getOperand(0);
12238 SDValue N1 = N->getOperand(1);
12240 // look for psign/blend
12241 if (Subtarget->hasSSSE3()) {
12242 if (VT == MVT::v2i64) {
12243 // Canonicalize pandn to RHS
12244 if (N0.getOpcode() == X86ISD::ANDNP)
12246 // or (and (m, x), (pandn m, y))
12247 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
12248 SDValue Mask = N1.getOperand(0);
12249 SDValue X = N1.getOperand(1);
12251 if (N0.getOperand(0) == Mask)
12252 Y = N0.getOperand(1);
12253 if (N0.getOperand(1) == Mask)
12254 Y = N0.getOperand(0);
12256 // Check to see if the mask appeared in both the AND and ANDNP and
12260 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
12261 if (Mask.getOpcode() != ISD::BITCAST ||
12262 X.getOpcode() != ISD::BITCAST ||
12263 Y.getOpcode() != ISD::BITCAST)
12266 // Look through mask bitcast.
12267 Mask = Mask.getOperand(0);
12268 EVT MaskVT = Mask.getValueType();
12270 // Validate that the Mask operand is a vector sra node. The sra node
12271 // will be an intrinsic.
12272 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
12275 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
12276 // there is no psrai.b
12277 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
12278 case Intrinsic::x86_sse2_psrai_w:
12279 case Intrinsic::x86_sse2_psrai_d:
12281 default: return SDValue();
12284 // Check that the SRA is all signbits.
12285 SDValue SraC = Mask.getOperand(2);
12286 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
12287 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
12288 if ((SraAmt + 1) != EltBits)
12291 DebugLoc DL = N->getDebugLoc();
12293 // Now we know we at least have a plendvb with the mask val. See if
12294 // we can form a psignb/w/d.
12295 // psign = x.type == y.type == mask.type && y = sub(0, x);
12296 X = X.getOperand(0);
12297 Y = Y.getOperand(0);
12298 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
12299 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
12300 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
12303 case 8: Opc = X86ISD::PSIGNB; break;
12304 case 16: Opc = X86ISD::PSIGNW; break;
12305 case 32: Opc = X86ISD::PSIGND; break;
12309 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
12310 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
12313 // PBLENDVB only available on SSE 4.1
12314 if (!Subtarget->hasSSE41())
12317 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
12318 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
12319 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
12320 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
12321 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
12326 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
12327 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
12329 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
12331 if (!N0.hasOneUse() || !N1.hasOneUse())
12334 SDValue ShAmt0 = N0.getOperand(1);
12335 if (ShAmt0.getValueType() != MVT::i8)
12337 SDValue ShAmt1 = N1.getOperand(1);
12338 if (ShAmt1.getValueType() != MVT::i8)
12340 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
12341 ShAmt0 = ShAmt0.getOperand(0);
12342 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
12343 ShAmt1 = ShAmt1.getOperand(0);
12345 DebugLoc DL = N->getDebugLoc();
12346 unsigned Opc = X86ISD::SHLD;
12347 SDValue Op0 = N0.getOperand(0);
12348 SDValue Op1 = N1.getOperand(0);
12349 if (ShAmt0.getOpcode() == ISD::SUB) {
12350 Opc = X86ISD::SHRD;
12351 std::swap(Op0, Op1);
12352 std::swap(ShAmt0, ShAmt1);
12355 unsigned Bits = VT.getSizeInBits();
12356 if (ShAmt1.getOpcode() == ISD::SUB) {
12357 SDValue Sum = ShAmt1.getOperand(0);
12358 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
12359 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
12360 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
12361 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
12362 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
12363 return DAG.getNode(Opc, DL, VT,
12365 DAG.getNode(ISD::TRUNCATE, DL,
12368 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
12369 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
12371 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
12372 return DAG.getNode(Opc, DL, VT,
12373 N0.getOperand(0), N1.getOperand(0),
12374 DAG.getNode(ISD::TRUNCATE, DL,
12381 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
12382 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
12383 const X86Subtarget *Subtarget) {
12384 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
12385 // the FP state in cases where an emms may be missing.
12386 // A preferable solution to the general problem is to figure out the right
12387 // places to insert EMMS. This qualifies as a quick hack.
12389 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
12390 StoreSDNode *St = cast<StoreSDNode>(N);
12391 EVT VT = St->getValue().getValueType();
12392 if (VT.getSizeInBits() != 64)
12395 const Function *F = DAG.getMachineFunction().getFunction();
12396 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
12397 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
12398 && Subtarget->hasSSE2();
12399 if ((VT.isVector() ||
12400 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
12401 isa<LoadSDNode>(St->getValue()) &&
12402 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
12403 St->getChain().hasOneUse() && !St->isVolatile()) {
12404 SDNode* LdVal = St->getValue().getNode();
12405 LoadSDNode *Ld = 0;
12406 int TokenFactorIndex = -1;
12407 SmallVector<SDValue, 8> Ops;
12408 SDNode* ChainVal = St->getChain().getNode();
12409 // Must be a store of a load. We currently handle two cases: the load
12410 // is a direct child, and it's under an intervening TokenFactor. It is
12411 // possible to dig deeper under nested TokenFactors.
12412 if (ChainVal == LdVal)
12413 Ld = cast<LoadSDNode>(St->getChain());
12414 else if (St->getValue().hasOneUse() &&
12415 ChainVal->getOpcode() == ISD::TokenFactor) {
12416 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
12417 if (ChainVal->getOperand(i).getNode() == LdVal) {
12418 TokenFactorIndex = i;
12419 Ld = cast<LoadSDNode>(St->getValue());
12421 Ops.push_back(ChainVal->getOperand(i));
12425 if (!Ld || !ISD::isNormalLoad(Ld))
12428 // If this is not the MMX case, i.e. we are just turning i64 load/store
12429 // into f64 load/store, avoid the transformation if there are multiple
12430 // uses of the loaded value.
12431 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
12434 DebugLoc LdDL = Ld->getDebugLoc();
12435 DebugLoc StDL = N->getDebugLoc();
12436 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
12437 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
12439 if (Subtarget->is64Bit() || F64IsLegal) {
12440 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
12441 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
12442 Ld->getPointerInfo(), Ld->isVolatile(),
12443 Ld->isNonTemporal(), Ld->getAlignment());
12444 SDValue NewChain = NewLd.getValue(1);
12445 if (TokenFactorIndex != -1) {
12446 Ops.push_back(NewChain);
12447 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
12450 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
12451 St->getPointerInfo(),
12452 St->isVolatile(), St->isNonTemporal(),
12453 St->getAlignment());
12456 // Otherwise, lower to two pairs of 32-bit loads / stores.
12457 SDValue LoAddr = Ld->getBasePtr();
12458 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
12459 DAG.getConstant(4, MVT::i32));
12461 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
12462 Ld->getPointerInfo(),
12463 Ld->isVolatile(), Ld->isNonTemporal(),
12464 Ld->getAlignment());
12465 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
12466 Ld->getPointerInfo().getWithOffset(4),
12467 Ld->isVolatile(), Ld->isNonTemporal(),
12468 MinAlign(Ld->getAlignment(), 4));
12470 SDValue NewChain = LoLd.getValue(1);
12471 if (TokenFactorIndex != -1) {
12472 Ops.push_back(LoLd);
12473 Ops.push_back(HiLd);
12474 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
12478 LoAddr = St->getBasePtr();
12479 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
12480 DAG.getConstant(4, MVT::i32));
12482 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
12483 St->getPointerInfo(),
12484 St->isVolatile(), St->isNonTemporal(),
12485 St->getAlignment());
12486 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
12487 St->getPointerInfo().getWithOffset(4),
12489 St->isNonTemporal(),
12490 MinAlign(St->getAlignment(), 4));
12491 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
12496 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
12497 /// X86ISD::FXOR nodes.
12498 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
12499 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
12500 // F[X]OR(0.0, x) -> x
12501 // F[X]OR(x, 0.0) -> x
12502 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
12503 if (C->getValueAPF().isPosZero())
12504 return N->getOperand(1);
12505 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
12506 if (C->getValueAPF().isPosZero())
12507 return N->getOperand(0);
12511 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
12512 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
12513 // FAND(0.0, x) -> 0.0
12514 // FAND(x, 0.0) -> 0.0
12515 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
12516 if (C->getValueAPF().isPosZero())
12517 return N->getOperand(0);
12518 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
12519 if (C->getValueAPF().isPosZero())
12520 return N->getOperand(1);
12524 static SDValue PerformBTCombine(SDNode *N,
12526 TargetLowering::DAGCombinerInfo &DCI) {
12527 // BT ignores high bits in the bit index operand.
12528 SDValue Op1 = N->getOperand(1);
12529 if (Op1.hasOneUse()) {
12530 unsigned BitWidth = Op1.getValueSizeInBits();
12531 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
12532 APInt KnownZero, KnownOne;
12533 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
12534 !DCI.isBeforeLegalizeOps());
12535 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12536 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
12537 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
12538 DCI.CommitTargetLoweringOpt(TLO);
12543 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
12544 SDValue Op = N->getOperand(0);
12545 if (Op.getOpcode() == ISD::BITCAST)
12546 Op = Op.getOperand(0);
12547 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
12548 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
12549 VT.getVectorElementType().getSizeInBits() ==
12550 OpVT.getVectorElementType().getSizeInBits()) {
12551 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
12556 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
12557 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
12558 // (and (i32 x86isd::setcc_carry), 1)
12559 // This eliminates the zext. This transformation is necessary because
12560 // ISD::SETCC is always legalized to i8.
12561 DebugLoc dl = N->getDebugLoc();
12562 SDValue N0 = N->getOperand(0);
12563 EVT VT = N->getValueType(0);
12564 if (N0.getOpcode() == ISD::AND &&
12566 N0.getOperand(0).hasOneUse()) {
12567 SDValue N00 = N0.getOperand(0);
12568 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
12570 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
12571 if (!C || C->getZExtValue() != 1)
12573 return DAG.getNode(ISD::AND, dl, VT,
12574 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
12575 N00.getOperand(0), N00.getOperand(1)),
12576 DAG.getConstant(1, VT));
12582 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
12583 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
12584 unsigned X86CC = N->getConstantOperandVal(0);
12585 SDValue EFLAG = N->getOperand(1);
12586 DebugLoc DL = N->getDebugLoc();
12588 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
12589 // a zext and produces an all-ones bit which is more useful than 0/1 in some
12591 if (X86CC == X86::COND_B)
12592 return DAG.getNode(ISD::AND, DL, MVT::i8,
12593 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
12594 DAG.getConstant(X86CC, MVT::i8), EFLAG),
12595 DAG.getConstant(1, MVT::i8));
12600 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
12601 const X86TargetLowering *XTLI) {
12602 SDValue Op0 = N->getOperand(0);
12603 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
12604 // a 32-bit target where SSE doesn't support i64->FP operations.
12605 if (Op0.getOpcode() == ISD::LOAD) {
12606 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
12607 EVT VT = Ld->getValueType(0);
12608 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
12609 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
12610 !XTLI->getSubtarget()->is64Bit() &&
12611 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
12612 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
12613 Ld->getChain(), Op0, DAG);
12614 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
12621 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
12622 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
12623 X86TargetLowering::DAGCombinerInfo &DCI) {
12624 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
12625 // the result is either zero or one (depending on the input carry bit).
12626 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
12627 if (X86::isZeroNode(N->getOperand(0)) &&
12628 X86::isZeroNode(N->getOperand(1)) &&
12629 // We don't have a good way to replace an EFLAGS use, so only do this when
12631 SDValue(N, 1).use_empty()) {
12632 DebugLoc DL = N->getDebugLoc();
12633 EVT VT = N->getValueType(0);
12634 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
12635 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
12636 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
12637 DAG.getConstant(X86::COND_B,MVT::i8),
12639 DAG.getConstant(1, VT));
12640 return DCI.CombineTo(N, Res1, CarryOut);
12646 // fold (add Y, (sete X, 0)) -> adc 0, Y
12647 // (add Y, (setne X, 0)) -> sbb -1, Y
12648 // (sub (sete X, 0), Y) -> sbb 0, Y
12649 // (sub (setne X, 0), Y) -> adc -1, Y
12650 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
12651 DebugLoc DL = N->getDebugLoc();
12653 // Look through ZExts.
12654 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
12655 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
12658 SDValue SetCC = Ext.getOperand(0);
12659 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
12662 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
12663 if (CC != X86::COND_E && CC != X86::COND_NE)
12666 SDValue Cmp = SetCC.getOperand(1);
12667 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
12668 !X86::isZeroNode(Cmp.getOperand(1)) ||
12669 !Cmp.getOperand(0).getValueType().isInteger())
12672 SDValue CmpOp0 = Cmp.getOperand(0);
12673 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
12674 DAG.getConstant(1, CmpOp0.getValueType()));
12676 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
12677 if (CC == X86::COND_NE)
12678 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
12679 DL, OtherVal.getValueType(), OtherVal,
12680 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
12681 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
12682 DL, OtherVal.getValueType(), OtherVal,
12683 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
12686 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) {
12687 SDValue Op0 = N->getOperand(0);
12688 SDValue Op1 = N->getOperand(1);
12690 // X86 can't encode an immediate LHS of a sub. See if we can push the
12691 // negation into a preceding instruction.
12692 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
12693 uint64_t Op0C = C->getSExtValue();
12695 // If the RHS of the sub is a XOR with one use and a constant, invert the
12696 // immediate. Then add one to the LHS of the sub so we can turn
12697 // X-Y -> X+~Y+1, saving one register.
12698 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
12699 isa<ConstantSDNode>(Op1.getOperand(1))) {
12700 uint64_t XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getSExtValue();
12701 EVT VT = Op0.getValueType();
12702 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
12704 DAG.getConstant(~XorC, VT));
12705 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
12706 DAG.getConstant(Op0C+1, VT));
12710 return OptimizeConditionalInDecrement(N, DAG);
12713 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
12714 DAGCombinerInfo &DCI) const {
12715 SelectionDAG &DAG = DCI.DAG;
12716 switch (N->getOpcode()) {
12718 case ISD::EXTRACT_VECTOR_ELT:
12719 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
12720 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
12721 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
12722 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);
12723 case ISD::SUB: return PerformSubCombine(N, DAG);
12724 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
12725 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
12728 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
12729 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
12730 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
12731 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
12732 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
12734 case X86ISD::FOR: return PerformFORCombine(N, DAG);
12735 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
12736 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
12737 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
12738 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
12739 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
12740 case X86ISD::SHUFPS: // Handle all target specific shuffles
12741 case X86ISD::SHUFPD:
12742 case X86ISD::PALIGN:
12743 case X86ISD::PUNPCKHBW:
12744 case X86ISD::PUNPCKHWD:
12745 case X86ISD::PUNPCKHDQ:
12746 case X86ISD::PUNPCKHQDQ:
12747 case X86ISD::UNPCKHPS:
12748 case X86ISD::UNPCKHPD:
12749 case X86ISD::VUNPCKHPSY:
12750 case X86ISD::VUNPCKHPDY:
12751 case X86ISD::PUNPCKLBW:
12752 case X86ISD::PUNPCKLWD:
12753 case X86ISD::PUNPCKLDQ:
12754 case X86ISD::PUNPCKLQDQ:
12755 case X86ISD::UNPCKLPS:
12756 case X86ISD::UNPCKLPD:
12757 case X86ISD::VUNPCKLPSY:
12758 case X86ISD::VUNPCKLPDY:
12759 case X86ISD::MOVHLPS:
12760 case X86ISD::MOVLHPS:
12761 case X86ISD::PSHUFD:
12762 case X86ISD::PSHUFHW:
12763 case X86ISD::PSHUFLW:
12764 case X86ISD::MOVSS:
12765 case X86ISD::MOVSD:
12766 case X86ISD::VPERMILPS:
12767 case X86ISD::VPERMILPSY:
12768 case X86ISD::VPERMILPD:
12769 case X86ISD::VPERMILPDY:
12770 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI);
12776 /// isTypeDesirableForOp - Return true if the target has native support for
12777 /// the specified value type and it is 'desirable' to use the type for the
12778 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
12779 /// instruction encodings are longer and some i16 instructions are slow.
12780 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
12781 if (!isTypeLegal(VT))
12783 if (VT != MVT::i16)
12790 case ISD::SIGN_EXTEND:
12791 case ISD::ZERO_EXTEND:
12792 case ISD::ANY_EXTEND:
12805 /// IsDesirableToPromoteOp - This method query the target whether it is
12806 /// beneficial for dag combiner to promote the specified node. If true, it
12807 /// should return the desired promotion type by reference.
12808 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
12809 EVT VT = Op.getValueType();
12810 if (VT != MVT::i16)
12813 bool Promote = false;
12814 bool Commute = false;
12815 switch (Op.getOpcode()) {
12818 LoadSDNode *LD = cast<LoadSDNode>(Op);
12819 // If the non-extending load has a single use and it's not live out, then it
12820 // might be folded.
12821 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
12822 Op.hasOneUse()*/) {
12823 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12824 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
12825 // The only case where we'd want to promote LOAD (rather then it being
12826 // promoted as an operand is when it's only use is liveout.
12827 if (UI->getOpcode() != ISD::CopyToReg)
12834 case ISD::SIGN_EXTEND:
12835 case ISD::ZERO_EXTEND:
12836 case ISD::ANY_EXTEND:
12841 SDValue N0 = Op.getOperand(0);
12842 // Look out for (store (shl (load), x)).
12843 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
12856 SDValue N0 = Op.getOperand(0);
12857 SDValue N1 = Op.getOperand(1);
12858 if (!Commute && MayFoldLoad(N1))
12860 // Avoid disabling potential load folding opportunities.
12861 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
12863 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
12873 //===----------------------------------------------------------------------===//
12874 // X86 Inline Assembly Support
12875 //===----------------------------------------------------------------------===//
12877 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
12878 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
12880 std::string AsmStr = IA->getAsmString();
12882 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
12883 SmallVector<StringRef, 4> AsmPieces;
12884 SplitString(AsmStr, AsmPieces, ";\n");
12886 switch (AsmPieces.size()) {
12887 default: return false;
12889 AsmStr = AsmPieces[0];
12891 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
12893 // FIXME: this should verify that we are targeting a 486 or better. If not,
12894 // we will turn this bswap into something that will be lowered to logical ops
12895 // instead of emitting the bswap asm. For now, we don't support 486 or lower
12896 // so don't worry about this.
12898 if (AsmPieces.size() == 2 &&
12899 (AsmPieces[0] == "bswap" ||
12900 AsmPieces[0] == "bswapq" ||
12901 AsmPieces[0] == "bswapl") &&
12902 (AsmPieces[1] == "$0" ||
12903 AsmPieces[1] == "${0:q}")) {
12904 // No need to check constraints, nothing other than the equivalent of
12905 // "=r,0" would be valid here.
12906 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
12907 if (!Ty || Ty->getBitWidth() % 16 != 0)
12909 return IntrinsicLowering::LowerToByteSwap(CI);
12911 // rorw $$8, ${0:w} --> llvm.bswap.i16
12912 if (CI->getType()->isIntegerTy(16) &&
12913 AsmPieces.size() == 3 &&
12914 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
12915 AsmPieces[1] == "$$8," &&
12916 AsmPieces[2] == "${0:w}" &&
12917 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
12919 const std::string &ConstraintsStr = IA->getConstraintString();
12920 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
12921 std::sort(AsmPieces.begin(), AsmPieces.end());
12922 if (AsmPieces.size() == 4 &&
12923 AsmPieces[0] == "~{cc}" &&
12924 AsmPieces[1] == "~{dirflag}" &&
12925 AsmPieces[2] == "~{flags}" &&
12926 AsmPieces[3] == "~{fpsr}") {
12927 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
12928 if (!Ty || Ty->getBitWidth() % 16 != 0)
12930 return IntrinsicLowering::LowerToByteSwap(CI);
12935 if (CI->getType()->isIntegerTy(32) &&
12936 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
12937 SmallVector<StringRef, 4> Words;
12938 SplitString(AsmPieces[0], Words, " \t,");
12939 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
12940 Words[2] == "${0:w}") {
12942 SplitString(AsmPieces[1], Words, " \t,");
12943 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
12944 Words[2] == "$0") {
12946 SplitString(AsmPieces[2], Words, " \t,");
12947 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
12948 Words[2] == "${0:w}") {
12950 const std::string &ConstraintsStr = IA->getConstraintString();
12951 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
12952 std::sort(AsmPieces.begin(), AsmPieces.end());
12953 if (AsmPieces.size() == 4 &&
12954 AsmPieces[0] == "~{cc}" &&
12955 AsmPieces[1] == "~{dirflag}" &&
12956 AsmPieces[2] == "~{flags}" &&
12957 AsmPieces[3] == "~{fpsr}") {
12958 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
12959 if (!Ty || Ty->getBitWidth() % 16 != 0)
12961 return IntrinsicLowering::LowerToByteSwap(CI);
12968 if (CI->getType()->isIntegerTy(64)) {
12969 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
12970 if (Constraints.size() >= 2 &&
12971 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
12972 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
12973 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
12974 SmallVector<StringRef, 4> Words;
12975 SplitString(AsmPieces[0], Words, " \t");
12976 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
12978 SplitString(AsmPieces[1], Words, " \t");
12979 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
12981 SplitString(AsmPieces[2], Words, " \t,");
12982 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
12983 Words[2] == "%edx") {
12984 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
12985 if (!Ty || Ty->getBitWidth() % 16 != 0)
12987 return IntrinsicLowering::LowerToByteSwap(CI);
13000 /// getConstraintType - Given a constraint letter, return the type of
13001 /// constraint it is for this target.
13002 X86TargetLowering::ConstraintType
13003 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
13004 if (Constraint.size() == 1) {
13005 switch (Constraint[0]) {
13016 return C_RegisterClass;
13040 return TargetLowering::getConstraintType(Constraint);
13043 /// Examine constraint type and operand type and determine a weight value.
13044 /// This object must already have been set up with the operand type
13045 /// and the current alternative constraint selected.
13046 TargetLowering::ConstraintWeight
13047 X86TargetLowering::getSingleConstraintMatchWeight(
13048 AsmOperandInfo &info, const char *constraint) const {
13049 ConstraintWeight weight = CW_Invalid;
13050 Value *CallOperandVal = info.CallOperandVal;
13051 // If we don't have a value, we can't do a match,
13052 // but allow it at the lowest weight.
13053 if (CallOperandVal == NULL)
13055 Type *type = CallOperandVal->getType();
13056 // Look at the constraint type.
13057 switch (*constraint) {
13059 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
13070 if (CallOperandVal->getType()->isIntegerTy())
13071 weight = CW_SpecificReg;
13076 if (type->isFloatingPointTy())
13077 weight = CW_SpecificReg;
13080 if (type->isX86_MMXTy() && Subtarget->hasMMX())
13081 weight = CW_SpecificReg;
13085 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
13086 weight = CW_Register;
13089 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
13090 if (C->getZExtValue() <= 31)
13091 weight = CW_Constant;
13095 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13096 if (C->getZExtValue() <= 63)
13097 weight = CW_Constant;
13101 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13102 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
13103 weight = CW_Constant;
13107 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13108 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
13109 weight = CW_Constant;
13113 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13114 if (C->getZExtValue() <= 3)
13115 weight = CW_Constant;
13119 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13120 if (C->getZExtValue() <= 0xff)
13121 weight = CW_Constant;
13126 if (dyn_cast<ConstantFP>(CallOperandVal)) {
13127 weight = CW_Constant;
13131 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13132 if ((C->getSExtValue() >= -0x80000000LL) &&
13133 (C->getSExtValue() <= 0x7fffffffLL))
13134 weight = CW_Constant;
13138 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13139 if (C->getZExtValue() <= 0xffffffff)
13140 weight = CW_Constant;
13147 /// LowerXConstraint - try to replace an X constraint, which matches anything,
13148 /// with another that has more specific requirements based on the type of the
13149 /// corresponding operand.
13150 const char *X86TargetLowering::
13151 LowerXConstraint(EVT ConstraintVT) const {
13152 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
13153 // 'f' like normal targets.
13154 if (ConstraintVT.isFloatingPoint()) {
13155 if (Subtarget->hasXMMInt())
13157 if (Subtarget->hasXMM())
13161 return TargetLowering::LowerXConstraint(ConstraintVT);
13164 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
13165 /// vector. If it is invalid, don't add anything to Ops.
13166 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
13167 std::string &Constraint,
13168 std::vector<SDValue>&Ops,
13169 SelectionDAG &DAG) const {
13170 SDValue Result(0, 0);
13172 // Only support length 1 constraints for now.
13173 if (Constraint.length() > 1) return;
13175 char ConstraintLetter = Constraint[0];
13176 switch (ConstraintLetter) {
13179 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13180 if (C->getZExtValue() <= 31) {
13181 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13187 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13188 if (C->getZExtValue() <= 63) {
13189 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13195 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13196 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
13197 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13203 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13204 if (C->getZExtValue() <= 255) {
13205 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13211 // 32-bit signed value
13212 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13213 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
13214 C->getSExtValue())) {
13215 // Widen to 64 bits here to get it sign extended.
13216 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
13219 // FIXME gcc accepts some relocatable values here too, but only in certain
13220 // memory models; it's complicated.
13225 // 32-bit unsigned value
13226 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
13227 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
13228 C->getZExtValue())) {
13229 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
13233 // FIXME gcc accepts some relocatable values here too, but only in certain
13234 // memory models; it's complicated.
13238 // Literal immediates are always ok.
13239 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
13240 // Widen to 64 bits here to get it sign extended.
13241 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
13245 // In any sort of PIC mode addresses need to be computed at runtime by
13246 // adding in a register or some sort of table lookup. These can't
13247 // be used as immediates.
13248 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
13251 // If we are in non-pic codegen mode, we allow the address of a global (with
13252 // an optional displacement) to be used with 'i'.
13253 GlobalAddressSDNode *GA = 0;
13254 int64_t Offset = 0;
13256 // Match either (GA), (GA+C), (GA+C1+C2), etc.
13258 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
13259 Offset += GA->getOffset();
13261 } else if (Op.getOpcode() == ISD::ADD) {
13262 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
13263 Offset += C->getZExtValue();
13264 Op = Op.getOperand(0);
13267 } else if (Op.getOpcode() == ISD::SUB) {
13268 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
13269 Offset += -C->getZExtValue();
13270 Op = Op.getOperand(0);
13275 // Otherwise, this isn't something we can handle, reject it.
13279 const GlobalValue *GV = GA->getGlobal();
13280 // If we require an extra load to get this address, as in PIC mode, we
13281 // can't accept it.
13282 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
13283 getTargetMachine())))
13286 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
13287 GA->getValueType(0), Offset);
13292 if (Result.getNode()) {
13293 Ops.push_back(Result);
13296 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
13299 std::pair<unsigned, const TargetRegisterClass*>
13300 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
13302 // First, see if this is a constraint that directly corresponds to an LLVM
13304 if (Constraint.size() == 1) {
13305 // GCC Constraint Letters
13306 switch (Constraint[0]) {
13308 // TODO: Slight differences here in allocation order and leaving
13309 // RIP in the class. Do they matter any more here than they do
13310 // in the normal allocation?
13311 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
13312 if (Subtarget->is64Bit()) {
13313 if (VT == MVT::i32 || VT == MVT::f32)
13314 return std::make_pair(0U, X86::GR32RegisterClass);
13315 else if (VT == MVT::i16)
13316 return std::make_pair(0U, X86::GR16RegisterClass);
13317 else if (VT == MVT::i8 || VT == MVT::i1)
13318 return std::make_pair(0U, X86::GR8RegisterClass);
13319 else if (VT == MVT::i64 || VT == MVT::f64)
13320 return std::make_pair(0U, X86::GR64RegisterClass);
13323 // 32-bit fallthrough
13324 case 'Q': // Q_REGS
13325 if (VT == MVT::i32 || VT == MVT::f32)
13326 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
13327 else if (VT == MVT::i16)
13328 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
13329 else if (VT == MVT::i8 || VT == MVT::i1)
13330 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
13331 else if (VT == MVT::i64)
13332 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
13334 case 'r': // GENERAL_REGS
13335 case 'l': // INDEX_REGS
13336 if (VT == MVT::i8 || VT == MVT::i1)
13337 return std::make_pair(0U, X86::GR8RegisterClass);
13338 if (VT == MVT::i16)
13339 return std::make_pair(0U, X86::GR16RegisterClass);
13340 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
13341 return std::make_pair(0U, X86::GR32RegisterClass);
13342 return std::make_pair(0U, X86::GR64RegisterClass);
13343 case 'R': // LEGACY_REGS
13344 if (VT == MVT::i8 || VT == MVT::i1)
13345 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
13346 if (VT == MVT::i16)
13347 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
13348 if (VT == MVT::i32 || !Subtarget->is64Bit())
13349 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
13350 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
13351 case 'f': // FP Stack registers.
13352 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
13353 // value to the correct fpstack register class.
13354 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
13355 return std::make_pair(0U, X86::RFP32RegisterClass);
13356 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
13357 return std::make_pair(0U, X86::RFP64RegisterClass);
13358 return std::make_pair(0U, X86::RFP80RegisterClass);
13359 case 'y': // MMX_REGS if MMX allowed.
13360 if (!Subtarget->hasMMX()) break;
13361 return std::make_pair(0U, X86::VR64RegisterClass);
13362 case 'Y': // SSE_REGS if SSE2 allowed
13363 if (!Subtarget->hasXMMInt()) break;
13365 case 'x': // SSE_REGS if SSE1 allowed
13366 if (!Subtarget->hasXMM()) break;
13368 switch (VT.getSimpleVT().SimpleTy) {
13370 // Scalar SSE types.
13373 return std::make_pair(0U, X86::FR32RegisterClass);
13376 return std::make_pair(0U, X86::FR64RegisterClass);
13384 return std::make_pair(0U, X86::VR128RegisterClass);
13390 // Use the default implementation in TargetLowering to convert the register
13391 // constraint into a member of a register class.
13392 std::pair<unsigned, const TargetRegisterClass*> Res;
13393 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
13395 // Not found as a standard register?
13396 if (Res.second == 0) {
13397 // Map st(0) -> st(7) -> ST0
13398 if (Constraint.size() == 7 && Constraint[0] == '{' &&
13399 tolower(Constraint[1]) == 's' &&
13400 tolower(Constraint[2]) == 't' &&
13401 Constraint[3] == '(' &&
13402 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
13403 Constraint[5] == ')' &&
13404 Constraint[6] == '}') {
13406 Res.first = X86::ST0+Constraint[4]-'0';
13407 Res.second = X86::RFP80RegisterClass;
13411 // GCC allows "st(0)" to be called just plain "st".
13412 if (StringRef("{st}").equals_lower(Constraint)) {
13413 Res.first = X86::ST0;
13414 Res.second = X86::RFP80RegisterClass;
13419 if (StringRef("{flags}").equals_lower(Constraint)) {
13420 Res.first = X86::EFLAGS;
13421 Res.second = X86::CCRRegisterClass;
13425 // 'A' means EAX + EDX.
13426 if (Constraint == "A") {
13427 Res.first = X86::EAX;
13428 Res.second = X86::GR32_ADRegisterClass;
13434 // Otherwise, check to see if this is a register class of the wrong value
13435 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
13436 // turn into {ax},{dx}.
13437 if (Res.second->hasType(VT))
13438 return Res; // Correct type already, nothing to do.
13440 // All of the single-register GCC register classes map their values onto
13441 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
13442 // really want an 8-bit or 32-bit register, map to the appropriate register
13443 // class and return the appropriate register.
13444 if (Res.second == X86::GR16RegisterClass) {
13445 if (VT == MVT::i8) {
13446 unsigned DestReg = 0;
13447 switch (Res.first) {
13449 case X86::AX: DestReg = X86::AL; break;
13450 case X86::DX: DestReg = X86::DL; break;
13451 case X86::CX: DestReg = X86::CL; break;
13452 case X86::BX: DestReg = X86::BL; break;
13455 Res.first = DestReg;
13456 Res.second = X86::GR8RegisterClass;
13458 } else if (VT == MVT::i32) {
13459 unsigned DestReg = 0;
13460 switch (Res.first) {
13462 case X86::AX: DestReg = X86::EAX; break;
13463 case X86::DX: DestReg = X86::EDX; break;
13464 case X86::CX: DestReg = X86::ECX; break;
13465 case X86::BX: DestReg = X86::EBX; break;
13466 case X86::SI: DestReg = X86::ESI; break;
13467 case X86::DI: DestReg = X86::EDI; break;
13468 case X86::BP: DestReg = X86::EBP; break;
13469 case X86::SP: DestReg = X86::ESP; break;
13472 Res.first = DestReg;
13473 Res.second = X86::GR32RegisterClass;
13475 } else if (VT == MVT::i64) {
13476 unsigned DestReg = 0;
13477 switch (Res.first) {
13479 case X86::AX: DestReg = X86::RAX; break;
13480 case X86::DX: DestReg = X86::RDX; break;
13481 case X86::CX: DestReg = X86::RCX; break;
13482 case X86::BX: DestReg = X86::RBX; break;
13483 case X86::SI: DestReg = X86::RSI; break;
13484 case X86::DI: DestReg = X86::RDI; break;
13485 case X86::BP: DestReg = X86::RBP; break;
13486 case X86::SP: DestReg = X86::RSP; break;
13489 Res.first = DestReg;
13490 Res.second = X86::GR64RegisterClass;
13493 } else if (Res.second == X86::FR32RegisterClass ||
13494 Res.second == X86::FR64RegisterClass ||
13495 Res.second == X86::VR128RegisterClass) {
13496 // Handle references to XMM physical registers that got mapped into the
13497 // wrong class. This can happen with constraints like {xmm0} where the
13498 // target independent register mapper will just pick the first match it can
13499 // find, ignoring the required type.
13500 if (VT == MVT::f32)
13501 Res.second = X86::FR32RegisterClass;
13502 else if (VT == MVT::f64)
13503 Res.second = X86::FR64RegisterClass;
13504 else if (X86::VR128RegisterClass->hasType(VT))
13505 Res.second = X86::VR128RegisterClass;