1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/IR/Instructions.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
38 #define DEBUG_TYPE "x86-isel"
40 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
42 //===----------------------------------------------------------------------===//
43 // Pattern Matcher Implementation
44 //===----------------------------------------------------------------------===//
47 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
48 /// SDValue's instead of register numbers for the leaves of the matched
50 struct X86ISelAddressMode {
56 // This is really a union, discriminated by BaseType!
64 const GlobalValue *GV;
66 const BlockAddress *BlockAddr;
69 unsigned Align; // CP alignment.
70 unsigned char SymbolFlags; // X86II::MO_*
73 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
74 Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr),
75 JT(-1), Align(0), SymbolFlags(X86II::MO_NO_FLAG) {
78 bool hasSymbolicDisplacement() const {
79 return GV != nullptr || CP != nullptr || ES != nullptr ||
80 JT != -1 || BlockAddr != nullptr;
83 bool hasBaseOrIndexReg() const {
84 return BaseType == FrameIndexBase ||
85 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
88 /// isRIPRelative - Return true if this addressing mode is already RIP
90 bool isRIPRelative() const {
91 if (BaseType != RegBase) return false;
92 if (RegisterSDNode *RegNode =
93 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
94 return RegNode->getReg() == X86::RIP;
98 void setBaseReg(SDValue Reg) {
103 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
105 dbgs() << "X86ISelAddressMode " << this << '\n';
106 dbgs() << "Base_Reg ";
107 if (Base_Reg.getNode())
108 Base_Reg.getNode()->dump();
111 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
112 << " Scale" << Scale << '\n'
114 if (IndexReg.getNode())
115 IndexReg.getNode()->dump();
118 dbgs() << " Disp " << Disp << '\n'
135 dbgs() << " JT" << JT << " Align" << Align << '\n';
142 //===--------------------------------------------------------------------===//
143 /// ISel - X86 specific code to select X86 machine instructions for
144 /// SelectionDAG operations.
146 class X86DAGToDAGISel final : public SelectionDAGISel {
147 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
148 /// make the right decision when generating code for different targets.
149 const X86Subtarget *Subtarget;
151 /// OptForSize - If true, selector should try to optimize for code size
152 /// instead of performance.
156 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
157 : SelectionDAGISel(tm, OptLevel),
158 Subtarget(&tm.getSubtarget<X86Subtarget>()),
161 const char *getPassName() const override {
162 return "X86 DAG->DAG Instruction Selection";
165 bool runOnMachineFunction(MachineFunction &MF) override {
166 // Reset the subtarget each time through.
167 Subtarget = &TM.getSubtarget<X86Subtarget>();
168 SelectionDAGISel::runOnMachineFunction(MF);
172 void EmitFunctionEntryCode() override;
174 bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
176 void PreprocessISelDAG() override;
178 inline bool immSext8(SDNode *N) const {
179 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
182 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
183 // sign extended field.
184 inline bool i64immSExt32(SDNode *N) const {
185 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
186 return (int64_t)v == (int32_t)v;
189 // Include the pieces autogenerated from the target description.
190 #include "X86GenDAGISel.inc"
193 SDNode *Select(SDNode *N) override;
194 SDNode *SelectGather(SDNode *N, unsigned Opc);
195 SDNode *SelectAtomicLoadArith(SDNode *Node, MVT NVT);
197 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
198 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
199 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
200 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
201 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
203 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
204 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
205 SDValue &Scale, SDValue &Index, SDValue &Disp,
207 bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
208 bool SelectLEAAddr(SDValue N, SDValue &Base,
209 SDValue &Scale, SDValue &Index, SDValue &Disp,
211 bool SelectLEA64_32Addr(SDValue N, SDValue &Base,
212 SDValue &Scale, SDValue &Index, SDValue &Disp,
214 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
215 SDValue &Scale, SDValue &Index, SDValue &Disp,
217 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
218 SDValue &Base, SDValue &Scale,
219 SDValue &Index, SDValue &Disp,
221 SDValue &NodeWithChain);
223 bool TryFoldLoad(SDNode *P, SDValue N,
224 SDValue &Base, SDValue &Scale,
225 SDValue &Index, SDValue &Disp,
228 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
229 /// inline asm expressions.
230 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
232 std::vector<SDValue> &OutOps) override;
234 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
236 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
237 SDValue &Scale, SDValue &Index,
238 SDValue &Disp, SDValue &Segment) {
239 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
240 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex,
241 getTargetLowering()->getPointerTy()) :
243 Scale = getI8Imm(AM.Scale);
245 // These are 32-bit even in 64-bit mode since RIP relative offset
248 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(),
252 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
253 AM.Align, AM.Disp, AM.SymbolFlags);
255 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
256 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
257 } else if (AM.JT != -1) {
258 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
259 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
260 } else if (AM.BlockAddr)
261 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
264 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
266 if (AM.Segment.getNode())
267 Segment = AM.Segment;
269 Segment = CurDAG->getRegister(0, MVT::i32);
272 /// getI8Imm - Return a target constant with the specified value, of type
274 inline SDValue getI8Imm(unsigned Imm) {
275 return CurDAG->getTargetConstant(Imm, MVT::i8);
278 /// getI32Imm - Return a target constant with the specified value, of type
280 inline SDValue getI32Imm(unsigned Imm) {
281 return CurDAG->getTargetConstant(Imm, MVT::i32);
284 /// getGlobalBaseReg - Return an SDNode that returns the value of
285 /// the global base register. Output instructions required to
286 /// initialize the global base register, if necessary.
288 SDNode *getGlobalBaseReg();
290 /// getTargetMachine - Return a reference to the TargetMachine, casted
291 /// to the target-specific type.
292 const X86TargetMachine &getTargetMachine() const {
293 return static_cast<const X86TargetMachine &>(TM);
296 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
297 /// to the target-specific type.
298 const X86InstrInfo *getInstrInfo() const {
299 return getTargetMachine().getSubtargetImpl()->getInstrInfo();
306 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
307 if (OptLevel == CodeGenOpt::None) return false;
312 if (N.getOpcode() != ISD::LOAD)
315 // If N is a load, do additional profitability checks.
317 switch (U->getOpcode()) {
330 SDValue Op1 = U->getOperand(1);
332 // If the other operand is a 8-bit immediate we should fold the immediate
333 // instead. This reduces code size.
335 // movl 4(%esp), %eax
339 // addl 4(%esp), %eax
340 // The former is 2 bytes shorter. In case where the increment is 1, then
341 // the saving can be 4 bytes (by using incl %eax).
342 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
343 if (Imm->getAPIntValue().isSignedIntN(8))
346 // If the other operand is a TLS address, we should fold it instead.
349 // leal i@NTPOFF(%eax), %eax
351 // movl $i@NTPOFF, %eax
353 // if the block also has an access to a second TLS address this will save
355 // FIXME: This is probably also true for non-TLS addresses.
356 if (Op1.getOpcode() == X86ISD::Wrapper) {
357 SDValue Val = Op1.getOperand(0);
358 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
368 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
369 /// load's chain operand and move load below the call's chain operand.
370 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
371 SDValue Call, SDValue OrigChain) {
372 SmallVector<SDValue, 8> Ops;
373 SDValue Chain = OrigChain.getOperand(0);
374 if (Chain.getNode() == Load.getNode())
375 Ops.push_back(Load.getOperand(0));
377 assert(Chain.getOpcode() == ISD::TokenFactor &&
378 "Unexpected chain operand");
379 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
380 if (Chain.getOperand(i).getNode() == Load.getNode())
381 Ops.push_back(Load.getOperand(0));
383 Ops.push_back(Chain.getOperand(i));
385 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops);
387 Ops.push_back(NewChain);
389 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
390 Ops.push_back(OrigChain.getOperand(i));
391 CurDAG->UpdateNodeOperands(OrigChain.getNode(), Ops);
392 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
393 Load.getOperand(1), Load.getOperand(2));
395 unsigned NumOps = Call.getNode()->getNumOperands();
397 Ops.push_back(SDValue(Load.getNode(), 1));
398 for (unsigned i = 1, e = NumOps; i != e; ++i)
399 Ops.push_back(Call.getOperand(i));
400 CurDAG->UpdateNodeOperands(Call.getNode(), Ops);
403 /// isCalleeLoad - Return true if call address is a load and it can be
404 /// moved below CALLSEQ_START and the chains leading up to the call.
405 /// Return the CALLSEQ_START by reference as a second output.
406 /// In the case of a tail call, there isn't a callseq node between the call
407 /// chain and the load.
408 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
409 // The transformation is somewhat dangerous if the call's chain was glued to
410 // the call. After MoveBelowOrigChain the load is moved between the call and
411 // the chain, this can create a cycle if the load is not folded. So it is
412 // *really* important that we are sure the load will be folded.
413 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
415 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
418 LD->getAddressingMode() != ISD::UNINDEXED ||
419 LD->getExtensionType() != ISD::NON_EXTLOAD)
422 // Now let's find the callseq_start.
423 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
424 if (!Chain.hasOneUse())
426 Chain = Chain.getOperand(0);
429 if (!Chain.getNumOperands())
431 // Since we are not checking for AA here, conservatively abort if the chain
432 // writes to memory. It's not safe to move the callee (a load) across a store.
433 if (isa<MemSDNode>(Chain.getNode()) &&
434 cast<MemSDNode>(Chain.getNode())->writeMem())
436 if (Chain.getOperand(0).getNode() == Callee.getNode())
438 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
439 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
440 Callee.getValue(1).hasOneUse())
445 void X86DAGToDAGISel::PreprocessISelDAG() {
446 // OptForSize is used in pattern predicates that isel is matching.
447 OptForSize = MF->getFunction()->getAttributes().
448 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
450 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
451 E = CurDAG->allnodes_end(); I != E; ) {
452 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
454 if (OptLevel != CodeGenOpt::None &&
455 // Only does this when target favors doesn't favor register indirect
457 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
458 (N->getOpcode() == X86ISD::TC_RETURN &&
459 // Only does this if load can be folded into TC_RETURN.
460 (Subtarget->is64Bit() ||
461 getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
462 /// Also try moving call address load from outside callseq_start to just
463 /// before the call to allow it to be folded.
481 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
482 SDValue Chain = N->getOperand(0);
483 SDValue Load = N->getOperand(1);
484 if (!isCalleeLoad(Load, Chain, HasCallSeq))
486 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
491 // Lower fpround and fpextend nodes that target the FP stack to be store and
492 // load to the stack. This is a gross hack. We would like to simply mark
493 // these as being illegal, but when we do that, legalize produces these when
494 // it expands calls, then expands these in the same legalize pass. We would
495 // like dag combine to be able to hack on these between the call expansion
496 // and the node legalization. As such this pass basically does "really
497 // late" legalization of these inline with the X86 isel pass.
498 // FIXME: This should only happen when not compiled with -O0.
499 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
502 MVT SrcVT = N->getOperand(0).getSimpleValueType();
503 MVT DstVT = N->getSimpleValueType(0);
505 // If any of the sources are vectors, no fp stack involved.
506 if (SrcVT.isVector() || DstVT.isVector())
509 // If the source and destination are SSE registers, then this is a legal
510 // conversion that should not be lowered.
511 const X86TargetLowering *X86Lowering =
512 static_cast<const X86TargetLowering *>(getTargetLowering());
513 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
514 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
515 if (SrcIsSSE && DstIsSSE)
518 if (!SrcIsSSE && !DstIsSSE) {
519 // If this is an FPStack extension, it is a noop.
520 if (N->getOpcode() == ISD::FP_EXTEND)
522 // If this is a value-preserving FPStack truncation, it is a noop.
523 if (N->getConstantOperandVal(1))
527 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
528 // FPStack has extload and truncstore. SSE can fold direct loads into other
529 // operations. Based on this, decide what we want to do.
531 if (N->getOpcode() == ISD::FP_ROUND)
532 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
534 MemVT = SrcIsSSE ? SrcVT : DstVT;
536 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
539 // FIXME: optimize the case where the src/dest is a load or store?
540 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
542 MemTmp, MachinePointerInfo(), MemVT,
544 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
545 MachinePointerInfo(),
546 MemVT, false, false, false, 0);
548 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
549 // extload we created. This will cause general havok on the dag because
550 // anything below the conversion could be folded into other existing nodes.
551 // To avoid invalidating 'I', back it up to the convert node.
553 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
555 // Now that we did that, the node is dead. Increment the iterator to the
556 // next node to process, then delete N.
558 CurDAG->DeleteNode(N);
563 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
564 /// the main function.
565 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
566 MachineFrameInfo *MFI) {
567 const TargetInstrInfo *TII = TM.getSubtargetImpl()->getInstrInfo();
568 if (Subtarget->isTargetCygMing()) {
570 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
571 BuildMI(BB, DebugLoc(),
572 TII->get(CallOp)).addExternalSymbol("__main");
576 void X86DAGToDAGISel::EmitFunctionEntryCode() {
577 // If this is main, emit special code for main.
578 if (const Function *Fn = MF->getFunction())
579 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
580 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
583 static bool isDispSafeForFrameIndex(int64_t Val) {
584 // On 64-bit platforms, we can run into an issue where a frame index
585 // includes a displacement that, when added to the explicit displacement,
586 // will overflow the displacement field. Assuming that the frame index
587 // displacement fits into a 31-bit integer (which is only slightly more
588 // aggressive than the current fundamental assumption that it fits into
589 // a 32-bit integer), a 31-bit disp should always be safe.
590 return isInt<31>(Val);
593 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
594 X86ISelAddressMode &AM) {
595 int64_t Val = AM.Disp + Offset;
596 CodeModel::Model M = TM.getCodeModel();
597 if (Subtarget->is64Bit()) {
598 if (!X86::isOffsetSuitableForCodeModel(Val, M,
599 AM.hasSymbolicDisplacement()))
601 // In addition to the checks required for a register base, check that
602 // we do not try to use an unsafe Disp with a frame index.
603 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
604 !isDispSafeForFrameIndex(Val))
612 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
613 SDValue Address = N->getOperand(1);
615 // load gs:0 -> GS segment register.
616 // load fs:0 -> FS segment register.
618 // This optimization is valid because the GNU TLS model defines that
619 // gs:0 (or fs:0 on X86-64) contains its own address.
620 // For more information see http://people.redhat.com/drepper/tls.pdf
621 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
622 if (C->getSExtValue() == 0 && AM.Segment.getNode() == nullptr &&
623 Subtarget->isTargetLinux())
624 switch (N->getPointerInfo().getAddrSpace()) {
626 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
629 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
636 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
637 /// into an addressing mode. These wrap things that will resolve down into a
638 /// symbol reference. If no match is possible, this returns true, otherwise it
640 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
641 // If the addressing mode already has a symbol as the displacement, we can
642 // never match another symbol.
643 if (AM.hasSymbolicDisplacement())
646 SDValue N0 = N.getOperand(0);
647 CodeModel::Model M = TM.getCodeModel();
649 // Handle X86-64 rip-relative addresses. We check this before checking direct
650 // folding because RIP is preferable to non-RIP accesses.
651 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
652 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
653 // they cannot be folded into immediate fields.
654 // FIXME: This can be improved for kernel and other models?
655 (M == CodeModel::Small || M == CodeModel::Kernel)) {
656 // Base and index reg must be 0 in order to use %rip as base.
657 if (AM.hasBaseOrIndexReg())
659 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
660 X86ISelAddressMode Backup = AM;
661 AM.GV = G->getGlobal();
662 AM.SymbolFlags = G->getTargetFlags();
663 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
667 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
668 X86ISelAddressMode Backup = AM;
669 AM.CP = CP->getConstVal();
670 AM.Align = CP->getAlignment();
671 AM.SymbolFlags = CP->getTargetFlags();
672 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
676 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
677 AM.ES = S->getSymbol();
678 AM.SymbolFlags = S->getTargetFlags();
679 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
680 AM.JT = J->getIndex();
681 AM.SymbolFlags = J->getTargetFlags();
682 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
683 X86ISelAddressMode Backup = AM;
684 AM.BlockAddr = BA->getBlockAddress();
685 AM.SymbolFlags = BA->getTargetFlags();
686 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
691 llvm_unreachable("Unhandled symbol reference node.");
693 if (N.getOpcode() == X86ISD::WrapperRIP)
694 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
698 // Handle the case when globals fit in our immediate field: This is true for
699 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
700 // mode, this only applies to a non-RIP-relative computation.
701 if (!Subtarget->is64Bit() ||
702 M == CodeModel::Small || M == CodeModel::Kernel) {
703 assert(N.getOpcode() != X86ISD::WrapperRIP &&
704 "RIP-relative addressing already handled");
705 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
706 AM.GV = G->getGlobal();
707 AM.Disp += G->getOffset();
708 AM.SymbolFlags = G->getTargetFlags();
709 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
710 AM.CP = CP->getConstVal();
711 AM.Align = CP->getAlignment();
712 AM.Disp += CP->getOffset();
713 AM.SymbolFlags = CP->getTargetFlags();
714 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
715 AM.ES = S->getSymbol();
716 AM.SymbolFlags = S->getTargetFlags();
717 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
718 AM.JT = J->getIndex();
719 AM.SymbolFlags = J->getTargetFlags();
720 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
721 AM.BlockAddr = BA->getBlockAddress();
722 AM.Disp += BA->getOffset();
723 AM.SymbolFlags = BA->getTargetFlags();
725 llvm_unreachable("Unhandled symbol reference node.");
732 /// MatchAddress - Add the specified node to the specified addressing mode,
733 /// returning true if it cannot be done. This just pattern matches for the
735 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
736 if (MatchAddressRecursively(N, AM, 0))
739 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
740 // a smaller encoding and avoids a scaled-index.
742 AM.BaseType == X86ISelAddressMode::RegBase &&
743 AM.Base_Reg.getNode() == nullptr) {
744 AM.Base_Reg = AM.IndexReg;
748 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
749 // because it has a smaller encoding.
750 // TODO: Which other code models can use this?
751 if (TM.getCodeModel() == CodeModel::Small &&
752 Subtarget->is64Bit() &&
754 AM.BaseType == X86ISelAddressMode::RegBase &&
755 AM.Base_Reg.getNode() == nullptr &&
756 AM.IndexReg.getNode() == nullptr &&
757 AM.SymbolFlags == X86II::MO_NO_FLAG &&
758 AM.hasSymbolicDisplacement())
759 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
764 // Insert a node into the DAG at least before the Pos node's position. This
765 // will reposition the node as needed, and will assign it a node ID that is <=
766 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
767 // IDs! The selection DAG must no longer depend on their uniqueness when this
769 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
770 if (N.getNode()->getNodeId() == -1 ||
771 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
772 DAG.RepositionNode(Pos.getNode(), N.getNode());
773 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
777 // Transform "(X >> (8-C1)) & C2" to "(X >> 8) & 0xff)" if safe. This
778 // allows us to convert the shift and and into an h-register extract and
779 // a scaled index. Returns false if the simplification is performed.
780 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
782 SDValue Shift, SDValue X,
783 X86ISelAddressMode &AM) {
784 if (Shift.getOpcode() != ISD::SRL ||
785 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
789 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
790 if (ScaleLog <= 0 || ScaleLog >= 4 ||
791 Mask != (0xffu << ScaleLog))
794 MVT VT = N.getSimpleValueType();
796 SDValue Eight = DAG.getConstant(8, MVT::i8);
797 SDValue NewMask = DAG.getConstant(0xff, VT);
798 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
799 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
800 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
801 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
803 // Insert the new nodes into the topological ordering. We must do this in
804 // a valid topological ordering as nothing is going to go back and re-sort
805 // these nodes. We continually insert before 'N' in sequence as this is
806 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
807 // hierarchy left to express.
808 InsertDAGNode(DAG, N, Eight);
809 InsertDAGNode(DAG, N, Srl);
810 InsertDAGNode(DAG, N, NewMask);
811 InsertDAGNode(DAG, N, And);
812 InsertDAGNode(DAG, N, ShlCount);
813 InsertDAGNode(DAG, N, Shl);
814 DAG.ReplaceAllUsesWith(N, Shl);
816 AM.Scale = (1 << ScaleLog);
820 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
821 // allows us to fold the shift into this addressing mode. Returns false if the
822 // transform succeeded.
823 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
825 SDValue Shift, SDValue X,
826 X86ISelAddressMode &AM) {
827 if (Shift.getOpcode() != ISD::SHL ||
828 !isa<ConstantSDNode>(Shift.getOperand(1)))
831 // Not likely to be profitable if either the AND or SHIFT node has more
832 // than one use (unless all uses are for address computation). Besides,
833 // isel mechanism requires their node ids to be reused.
834 if (!N.hasOneUse() || !Shift.hasOneUse())
837 // Verify that the shift amount is something we can fold.
838 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
839 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
842 MVT VT = N.getSimpleValueType();
844 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
845 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
846 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
848 // Insert the new nodes into the topological ordering. We must do this in
849 // a valid topological ordering as nothing is going to go back and re-sort
850 // these nodes. We continually insert before 'N' in sequence as this is
851 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
852 // hierarchy left to express.
853 InsertDAGNode(DAG, N, NewMask);
854 InsertDAGNode(DAG, N, NewAnd);
855 InsertDAGNode(DAG, N, NewShift);
856 DAG.ReplaceAllUsesWith(N, NewShift);
858 AM.Scale = 1 << ShiftAmt;
859 AM.IndexReg = NewAnd;
863 // Implement some heroics to detect shifts of masked values where the mask can
864 // be replaced by extending the shift and undoing that in the addressing mode
865 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
866 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
867 // the addressing mode. This results in code such as:
869 // int f(short *y, int *lookup_table) {
871 // return *y + lookup_table[*y >> 11];
875 // movzwl (%rdi), %eax
878 // addl (%rsi,%rcx,4), %eax
881 // movzwl (%rdi), %eax
885 // addl (%rsi,%rcx), %eax
887 // Note that this function assumes the mask is provided as a mask *after* the
888 // value is shifted. The input chain may or may not match that, but computing
889 // such a mask is trivial.
890 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
892 SDValue Shift, SDValue X,
893 X86ISelAddressMode &AM) {
894 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
895 !isa<ConstantSDNode>(Shift.getOperand(1)))
898 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
899 unsigned MaskLZ = countLeadingZeros(Mask);
900 unsigned MaskTZ = countTrailingZeros(Mask);
902 // The amount of shift we're trying to fit into the addressing mode is taken
903 // from the trailing zeros of the mask.
904 unsigned AMShiftAmt = MaskTZ;
906 // There is nothing we can do here unless the mask is removing some bits.
907 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
908 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
910 // We also need to ensure that mask is a continuous run of bits.
911 if (CountTrailingOnes_64(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
913 // Scale the leading zero count down based on the actual size of the value.
914 // Also scale it down based on the size of the shift.
915 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
917 // The final check is to ensure that any masked out high bits of X are
918 // already known to be zero. Otherwise, the mask has a semantic impact
919 // other than masking out a couple of low bits. Unfortunately, because of
920 // the mask, zero extensions will be removed from operands in some cases.
921 // This code works extra hard to look through extensions because we can
922 // replace them with zero extensions cheaply if necessary.
923 bool ReplacingAnyExtend = false;
924 if (X.getOpcode() == ISD::ANY_EXTEND) {
925 unsigned ExtendBits = X.getSimpleValueType().getSizeInBits() -
926 X.getOperand(0).getSimpleValueType().getSizeInBits();
927 // Assume that we'll replace the any-extend with a zero-extend, and
928 // narrow the search to the extended value.
930 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
931 ReplacingAnyExtend = true;
933 APInt MaskedHighBits =
934 APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
935 APInt KnownZero, KnownOne;
936 DAG.computeKnownBits(X, KnownZero, KnownOne);
937 if (MaskedHighBits != KnownZero) return true;
939 // We've identified a pattern that can be transformed into a single shift
940 // and an addressing mode. Make it so.
941 MVT VT = N.getSimpleValueType();
942 if (ReplacingAnyExtend) {
943 assert(X.getValueType() != VT);
944 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
945 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
946 InsertDAGNode(DAG, N, NewX);
950 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
951 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
952 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
953 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
955 // Insert the new nodes into the topological ordering. We must do this in
956 // a valid topological ordering as nothing is going to go back and re-sort
957 // these nodes. We continually insert before 'N' in sequence as this is
958 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
959 // hierarchy left to express.
960 InsertDAGNode(DAG, N, NewSRLAmt);
961 InsertDAGNode(DAG, N, NewSRL);
962 InsertDAGNode(DAG, N, NewSHLAmt);
963 InsertDAGNode(DAG, N, NewSHL);
964 DAG.ReplaceAllUsesWith(N, NewSHL);
966 AM.Scale = 1 << AMShiftAmt;
967 AM.IndexReg = NewSRL;
971 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
975 dbgs() << "MatchAddress: ";
980 return MatchAddressBase(N, AM);
982 // If this is already a %rip relative address, we can only merge immediates
983 // into it. Instead of handling this in every case, we handle it here.
984 // RIP relative addressing: %rip + 32-bit displacement!
985 if (AM.isRIPRelative()) {
986 // FIXME: JumpTable and ExternalSymbol address currently don't like
987 // displacements. It isn't very important, but this should be fixed for
989 if (!AM.ES && AM.JT != -1) return true;
991 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
992 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
997 switch (N.getOpcode()) {
999 case ISD::Constant: {
1000 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1001 if (!FoldOffsetIntoAddress(Val, AM))
1006 case X86ISD::Wrapper:
1007 case X86ISD::WrapperRIP:
1008 if (!MatchWrapper(N, AM))
1013 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
1017 case ISD::FrameIndex:
1018 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1019 AM.Base_Reg.getNode() == nullptr &&
1020 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
1021 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
1022 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1028 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1)
1032 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1033 unsigned Val = CN->getZExtValue();
1034 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1035 // that the base operand remains free for further matching. If
1036 // the base doesn't end up getting used, a post-processing step
1037 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1038 if (Val == 1 || Val == 2 || Val == 3) {
1039 AM.Scale = 1 << Val;
1040 SDValue ShVal = N.getNode()->getOperand(0);
1042 // Okay, we know that we have a scale by now. However, if the scaled
1043 // value is an add of something and a constant, we can fold the
1044 // constant into the disp field here.
1045 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1046 AM.IndexReg = ShVal.getNode()->getOperand(0);
1047 ConstantSDNode *AddVal =
1048 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1049 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1050 if (!FoldOffsetIntoAddress(Disp, AM))
1054 AM.IndexReg = ShVal;
1061 // Scale must not be used already.
1062 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1064 SDValue And = N.getOperand(0);
1065 if (And.getOpcode() != ISD::AND) break;
1066 SDValue X = And.getOperand(0);
1068 // We only handle up to 64-bit values here as those are what matter for
1069 // addressing mode optimizations.
1070 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1072 // The mask used for the transform is expected to be post-shift, but we
1073 // found the shift first so just apply the shift to the mask before passing
1075 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1076 !isa<ConstantSDNode>(And.getOperand(1)))
1078 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1080 // Try to fold the mask and shift into the scale, and return false if we
1082 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1087 case ISD::SMUL_LOHI:
1088 case ISD::UMUL_LOHI:
1089 // A mul_lohi where we need the low part can be folded as a plain multiply.
1090 if (N.getResNo() != 0) break;
1093 case X86ISD::MUL_IMM:
1094 // X*[3,5,9] -> X+X*[2,4,8]
1095 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1096 AM.Base_Reg.getNode() == nullptr &&
1097 AM.IndexReg.getNode() == nullptr) {
1099 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1100 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1101 CN->getZExtValue() == 9) {
1102 AM.Scale = unsigned(CN->getZExtValue())-1;
1104 SDValue MulVal = N.getNode()->getOperand(0);
1107 // Okay, we know that we have a scale by now. However, if the scaled
1108 // value is an add of something and a constant, we can fold the
1109 // constant into the disp field here.
1110 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1111 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1112 Reg = MulVal.getNode()->getOperand(0);
1113 ConstantSDNode *AddVal =
1114 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1115 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1116 if (FoldOffsetIntoAddress(Disp, AM))
1117 Reg = N.getNode()->getOperand(0);
1119 Reg = N.getNode()->getOperand(0);
1122 AM.IndexReg = AM.Base_Reg = Reg;
1129 // Given A-B, if A can be completely folded into the address and
1130 // the index field with the index field unused, use -B as the index.
1131 // This is a win if a has multiple parts that can be folded into
1132 // the address. Also, this saves a mov if the base register has
1133 // other uses, since it avoids a two-address sub instruction, however
1134 // it costs an additional mov if the index register has other uses.
1136 // Add an artificial use to this node so that we can keep track of
1137 // it if it gets CSE'd with a different node.
1138 HandleSDNode Handle(N);
1140 // Test if the LHS of the sub can be folded.
1141 X86ISelAddressMode Backup = AM;
1142 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1146 // Test if the index field is free for use.
1147 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1153 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1154 // If the RHS involves a register with multiple uses, this
1155 // transformation incurs an extra mov, due to the neg instruction
1156 // clobbering its operand.
1157 if (!RHS.getNode()->hasOneUse() ||
1158 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1159 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1160 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1161 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1162 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1164 // If the base is a register with multiple uses, this
1165 // transformation may save a mov.
1166 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1167 AM.Base_Reg.getNode() &&
1168 !AM.Base_Reg.getNode()->hasOneUse()) ||
1169 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1171 // If the folded LHS was interesting, this transformation saves
1172 // address arithmetic.
1173 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1174 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1175 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1177 // If it doesn't look like it may be an overall win, don't do it.
1183 // Ok, the transformation is legal and appears profitable. Go for it.
1184 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1185 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1189 // Insert the new nodes into the topological ordering.
1190 InsertDAGNode(*CurDAG, N, Zero);
1191 InsertDAGNode(*CurDAG, N, Neg);
1196 // Add an artificial use to this node so that we can keep track of
1197 // it if it gets CSE'd with a different node.
1198 HandleSDNode Handle(N);
1200 X86ISelAddressMode Backup = AM;
1201 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1202 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1206 // Try again after commuting the operands.
1207 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1208 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1212 // If we couldn't fold both operands into the address at the same time,
1213 // see if we can just put each operand into a register and fold at least
1215 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1216 !AM.Base_Reg.getNode() &&
1217 !AM.IndexReg.getNode()) {
1218 N = Handle.getValue();
1219 AM.Base_Reg = N.getOperand(0);
1220 AM.IndexReg = N.getOperand(1);
1224 N = Handle.getValue();
1229 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1230 if (CurDAG->isBaseWithConstantOffset(N)) {
1231 X86ISelAddressMode Backup = AM;
1232 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1234 // Start with the LHS as an addr mode.
1235 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1236 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1243 // Perform some heroic transforms on an and of a constant-count shift
1244 // with a constant to enable use of the scaled offset field.
1246 // Scale must not be used already.
1247 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1249 SDValue Shift = N.getOperand(0);
1250 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1251 SDValue X = Shift.getOperand(0);
1253 // We only handle up to 64-bit values here as those are what matter for
1254 // addressing mode optimizations.
1255 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1257 if (!isa<ConstantSDNode>(N.getOperand(1)))
1259 uint64_t Mask = N.getConstantOperandVal(1);
1261 // Try to fold the mask and shift into an extract and scale.
1262 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1265 // Try to fold the mask and shift directly into the scale.
1266 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1269 // Try to swap the mask and shift to place shifts which can be done as
1270 // a scale on the outside of the mask.
1271 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1277 return MatchAddressBase(N, AM);
1280 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1281 /// specified addressing mode without any further recursion.
1282 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1283 // Is the base register already occupied?
1284 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1285 // If so, check to see if the scale index register is set.
1286 if (!AM.IndexReg.getNode()) {
1292 // Otherwise, we cannot select it.
1296 // Default, generate it as a register.
1297 AM.BaseType = X86ISelAddressMode::RegBase;
1302 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1303 /// It returns the operands which make up the maximal addressing mode it can
1304 /// match by reference.
1306 /// Parent is the parent node of the addr operand that is being matched. It
1307 /// is always a load, store, atomic node, or null. It is only null when
1308 /// checking memory operands for inline asm nodes.
1309 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1310 SDValue &Scale, SDValue &Index,
1311 SDValue &Disp, SDValue &Segment) {
1312 X86ISelAddressMode AM;
1315 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1316 // that are not a MemSDNode, and thus don't have proper addrspace info.
1317 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1318 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1319 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
1320 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
1321 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
1322 unsigned AddrSpace =
1323 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1324 // AddrSpace 256 -> GS, 257 -> FS.
1325 if (AddrSpace == 256)
1326 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1327 if (AddrSpace == 257)
1328 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1331 if (MatchAddress(N, AM))
1334 MVT VT = N.getSimpleValueType();
1335 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1336 if (!AM.Base_Reg.getNode())
1337 AM.Base_Reg = CurDAG->getRegister(0, VT);
1340 if (!AM.IndexReg.getNode())
1341 AM.IndexReg = CurDAG->getRegister(0, VT);
1343 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1347 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1348 /// match a load whose top elements are either undef or zeros. The load flavor
1349 /// is derived from the type of N, which is either v4f32 or v2f64.
1352 /// PatternChainNode: this is the matched node that has a chain input and
1354 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1355 SDValue N, SDValue &Base,
1356 SDValue &Scale, SDValue &Index,
1357 SDValue &Disp, SDValue &Segment,
1358 SDValue &PatternNodeWithChain) {
1359 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1360 PatternNodeWithChain = N.getOperand(0);
1361 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1362 PatternNodeWithChain.hasOneUse() &&
1363 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1364 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1365 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1366 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1372 // Also handle the case where we explicitly require zeros in the top
1373 // elements. This is a vector shuffle from the zero vector.
1374 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1375 // Check to see if the top elements are all zeros (or bitcast of zeros).
1376 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1377 N.getOperand(0).getNode()->hasOneUse() &&
1378 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1379 N.getOperand(0).getOperand(0).hasOneUse() &&
1380 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1381 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1382 // Okay, this is a zero extending load. Fold it.
1383 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1384 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1386 PatternNodeWithChain = SDValue(LD, 0);
1393 bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
1394 if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1395 uint64_t ImmVal = CN->getZExtValue();
1396 if ((uint32_t)ImmVal != (uint64_t)ImmVal)
1399 Imm = CurDAG->getTargetConstant(ImmVal, MVT::i64);
1403 // In static codegen with small code model, we can get the address of a label
1404 // into a register with 'movl'. TableGen has already made sure we're looking
1405 // at a label of some kind.
1406 assert(N->getOpcode() == X86ISD::Wrapper &&
1407 "Unexpected node type for MOV32ri64");
1408 N = N.getOperand(0);
1410 if (N->getOpcode() != ISD::TargetConstantPool &&
1411 N->getOpcode() != ISD::TargetJumpTable &&
1412 N->getOpcode() != ISD::TargetGlobalAddress &&
1413 N->getOpcode() != ISD::TargetExternalSymbol &&
1414 N->getOpcode() != ISD::TargetBlockAddress)
1418 return TM.getCodeModel() == CodeModel::Small;
1421 bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
1422 SDValue &Scale, SDValue &Index,
1423 SDValue &Disp, SDValue &Segment) {
1424 if (!SelectLEAAddr(N, Base, Scale, Index, Disp, Segment))
1428 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
1429 if (RN && RN->getReg() == 0)
1430 Base = CurDAG->getRegister(0, MVT::i64);
1431 else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(N)) {
1432 // Base could already be %rip, particularly in the x32 ABI.
1433 Base = SDValue(CurDAG->getMachineNode(
1434 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1435 CurDAG->getTargetConstant(0, MVT::i64),
1437 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1441 RN = dyn_cast<RegisterSDNode>(Index);
1442 if (RN && RN->getReg() == 0)
1443 Index = CurDAG->getRegister(0, MVT::i64);
1445 assert(Index.getValueType() == MVT::i32 &&
1446 "Expect to be extending 32-bit registers for use in LEA");
1447 Index = SDValue(CurDAG->getMachineNode(
1448 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1449 CurDAG->getTargetConstant(0, MVT::i64),
1451 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1458 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1459 /// mode it matches can be cost effectively emitted as an LEA instruction.
1460 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1461 SDValue &Base, SDValue &Scale,
1462 SDValue &Index, SDValue &Disp,
1464 X86ISelAddressMode AM;
1466 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1468 SDValue Copy = AM.Segment;
1469 SDValue T = CurDAG->getRegister(0, MVT::i32);
1471 if (MatchAddress(N, AM))
1473 assert (T == AM.Segment);
1476 MVT VT = N.getSimpleValueType();
1477 unsigned Complexity = 0;
1478 if (AM.BaseType == X86ISelAddressMode::RegBase)
1479 if (AM.Base_Reg.getNode())
1482 AM.Base_Reg = CurDAG->getRegister(0, VT);
1483 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1486 if (AM.IndexReg.getNode())
1489 AM.IndexReg = CurDAG->getRegister(0, VT);
1491 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1496 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1497 // to a LEA. This is determined with some expermentation but is by no means
1498 // optimal (especially for code size consideration). LEA is nice because of
1499 // its three-address nature. Tweak the cost function again when we can run
1500 // convertToThreeAddress() at register allocation time.
1501 if (AM.hasSymbolicDisplacement()) {
1502 // For X86-64, we should always use lea to materialize RIP relative
1504 if (Subtarget->is64Bit())
1510 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1513 // If it isn't worth using an LEA, reject it.
1514 if (Complexity <= 2)
1517 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1521 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1522 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1523 SDValue &Scale, SDValue &Index,
1524 SDValue &Disp, SDValue &Segment) {
1525 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1526 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1528 X86ISelAddressMode AM;
1529 AM.GV = GA->getGlobal();
1530 AM.Disp += GA->getOffset();
1531 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1532 AM.SymbolFlags = GA->getTargetFlags();
1534 if (N.getValueType() == MVT::i32) {
1536 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1538 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1541 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1546 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1547 SDValue &Base, SDValue &Scale,
1548 SDValue &Index, SDValue &Disp,
1550 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1551 !IsProfitableToFold(N, P, P) ||
1552 !IsLegalToFold(N, P, P, OptLevel))
1555 return SelectAddr(N.getNode(),
1556 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1559 /// getGlobalBaseReg - Return an SDNode that returns the value of
1560 /// the global base register. Output instructions required to
1561 /// initialize the global base register, if necessary.
1563 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1564 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1565 return CurDAG->getRegister(GlobalBaseReg,
1566 getTargetLowering()->getPointerTy()).getNode();
1569 /// Atomic opcode table
1597 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1608 X86::LOCK_ADD64mi32,
1621 X86::LOCK_SUB64mi32,
1673 X86::LOCK_AND64mi32,
1686 X86::LOCK_XOR64mi32,
1691 // Return the target constant operand for atomic-load-op and do simple
1692 // translations, such as from atomic-load-add to lock-sub. The return value is
1693 // one of the following 3 cases:
1694 // + target-constant, the operand could be supported as a target constant.
1695 // + empty, the operand is not needed any more with the new op selected.
1696 // + non-empty, otherwise.
1697 static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
1699 enum AtomicOpc &Op, MVT NVT,
1701 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
1702 int64_t CNVal = CN->getSExtValue();
1703 // Quit if not 32-bit imm.
1704 if ((int32_t)CNVal != CNVal)
1706 // For atomic-load-add, we could do some optimizations.
1708 // Translate to INC/DEC if ADD by 1 or -1.
1709 if ((CNVal == 1) || (CNVal == -1)) {
1710 Op = (CNVal == 1) ? INC : DEC;
1711 // No more constant operand after being translated into INC/DEC.
1714 // Translate to SUB if ADD by negative value.
1720 return CurDAG->getTargetConstant(CNVal, NVT);
1723 // If the value operand is single-used, try to optimize it.
1724 if (Op == ADD && Val.hasOneUse()) {
1725 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
1726 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1728 return Val.getOperand(1);
1730 // A special case for i16, which needs truncating as, in most cases, it's
1731 // promoted to i32. We will translate
1732 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
1733 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1734 Val.getOperand(0).getOpcode() == ISD::SUB &&
1735 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1737 Val = Val.getOperand(0);
1738 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1746 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, MVT NVT) {
1747 if (Node->hasAnyUseOfValue(0))
1752 // Optimize common patterns for __sync_or_and_fetch and similar arith
1753 // operations where the result is not used. This allows us to use the "lock"
1754 // version of the arithmetic instruction.
1755 SDValue Chain = Node->getOperand(0);
1756 SDValue Ptr = Node->getOperand(1);
1757 SDValue Val = Node->getOperand(2);
1758 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1759 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1762 // Which index into the table.
1764 switch (Node->getOpcode()) {
1767 case ISD::ATOMIC_LOAD_OR:
1770 case ISD::ATOMIC_LOAD_AND:
1773 case ISD::ATOMIC_LOAD_XOR:
1776 case ISD::ATOMIC_LOAD_ADD:
1781 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val);
1782 bool isUnOp = !Val.getNode();
1783 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
1786 switch (NVT.SimpleTy) {
1787 default: return nullptr;
1790 Opc = AtomicOpcTbl[Op][ConstantI8];
1792 Opc = AtomicOpcTbl[Op][I8];
1796 if (immSext8(Val.getNode()))
1797 Opc = AtomicOpcTbl[Op][SextConstantI16];
1799 Opc = AtomicOpcTbl[Op][ConstantI16];
1801 Opc = AtomicOpcTbl[Op][I16];
1805 if (immSext8(Val.getNode()))
1806 Opc = AtomicOpcTbl[Op][SextConstantI32];
1808 Opc = AtomicOpcTbl[Op][ConstantI32];
1810 Opc = AtomicOpcTbl[Op][I32];
1813 Opc = AtomicOpcTbl[Op][I64];
1815 if (immSext8(Val.getNode()))
1816 Opc = AtomicOpcTbl[Op][SextConstantI64];
1817 else if (i64immSExt32(Val.getNode()))
1818 Opc = AtomicOpcTbl[Op][ConstantI64];
1823 assert(Opc != 0 && "Invalid arith lock transform!");
1826 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1828 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1829 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1831 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1832 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1834 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1835 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1837 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1838 SDValue RetVals[] = { Undef, Ret };
1839 return CurDAG->getMergeValues(RetVals, dl).getNode();
1842 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1843 /// any uses which require the SF or OF bits to be accurate.
1844 static bool HasNoSignedComparisonUses(SDNode *N) {
1845 // Examine each user of the node.
1846 for (SDNode::use_iterator UI = N->use_begin(),
1847 UE = N->use_end(); UI != UE; ++UI) {
1848 // Only examine CopyToReg uses.
1849 if (UI->getOpcode() != ISD::CopyToReg)
1851 // Only examine CopyToReg uses that copy to EFLAGS.
1852 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1855 // Examine each user of the CopyToReg use.
1856 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1857 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1858 // Only examine the Flag result.
1859 if (FlagUI.getUse().getResNo() != 1) continue;
1860 // Anything unusual: assume conservatively.
1861 if (!FlagUI->isMachineOpcode()) return false;
1862 // Examine the opcode of the user.
1863 switch (FlagUI->getMachineOpcode()) {
1864 // These comparisons don't treat the most significant bit specially.
1865 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1866 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1867 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1868 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1869 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
1870 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
1871 case X86::CMOVA16rr: case X86::CMOVA16rm:
1872 case X86::CMOVA32rr: case X86::CMOVA32rm:
1873 case X86::CMOVA64rr: case X86::CMOVA64rm:
1874 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1875 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1876 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1877 case X86::CMOVB16rr: case X86::CMOVB16rm:
1878 case X86::CMOVB32rr: case X86::CMOVB32rm:
1879 case X86::CMOVB64rr: case X86::CMOVB64rm:
1880 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1881 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1882 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1883 case X86::CMOVE16rr: case X86::CMOVE16rm:
1884 case X86::CMOVE32rr: case X86::CMOVE32rm:
1885 case X86::CMOVE64rr: case X86::CMOVE64rm:
1886 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1887 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1888 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1889 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1890 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1891 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1892 case X86::CMOVP16rr: case X86::CMOVP16rm:
1893 case X86::CMOVP32rr: case X86::CMOVP32rm:
1894 case X86::CMOVP64rr: case X86::CMOVP64rm:
1896 // Anything else: assume conservatively.
1897 default: return false;
1904 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1905 /// is suitable for doing the {load; increment or decrement; store} to modify
1907 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1908 SDValue StoredVal, SelectionDAG *CurDAG,
1909 LoadSDNode* &LoadNode, SDValue &InputChain) {
1911 // is the value stored the result of a DEC or INC?
1912 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1914 // is the stored value result 0 of the load?
1915 if (StoredVal.getResNo() != 0) return false;
1917 // are there other uses of the loaded value than the inc or dec?
1918 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1920 // is the store non-extending and non-indexed?
1921 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1924 SDValue Load = StoredVal->getOperand(0);
1925 // Is the stored value a non-extending and non-indexed load?
1926 if (!ISD::isNormalLoad(Load.getNode())) return false;
1928 // Return LoadNode by reference.
1929 LoadNode = cast<LoadSDNode>(Load);
1930 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
1931 EVT LdVT = LoadNode->getMemoryVT();
1932 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1936 // Is store the only read of the loaded value?
1937 if (!Load.hasOneUse())
1940 // Is the address of the store the same as the load?
1941 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1942 LoadNode->getOffset() != StoreNode->getOffset())
1945 // Check if the chain is produced by the load or is a TokenFactor with
1946 // the load output chain as an operand. Return InputChain by reference.
1947 SDValue Chain = StoreNode->getChain();
1949 bool ChainCheck = false;
1950 if (Chain == Load.getValue(1)) {
1952 InputChain = LoadNode->getChain();
1953 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1954 SmallVector<SDValue, 4> ChainOps;
1955 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
1956 SDValue Op = Chain.getOperand(i);
1957 if (Op == Load.getValue(1)) {
1962 // Make sure using Op as part of the chain would not cause a cycle here.
1963 // In theory, we could check whether the chain node is a predecessor of
1964 // the load. But that can be very expensive. Instead visit the uses and
1965 // make sure they all have smaller node id than the load.
1966 int LoadId = LoadNode->getNodeId();
1967 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
1968 UE = UI->use_end(); UI != UE; ++UI) {
1969 if (UI.getUse().getResNo() != 0)
1971 if (UI->getNodeId() > LoadId)
1975 ChainOps.push_back(Op);
1979 // Make a new TokenFactor with all the other input chains except
1981 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
1982 MVT::Other, ChainOps);
1990 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
1991 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
1992 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
1993 if (Opc == X86ISD::DEC) {
1994 if (LdVT == MVT::i64) return X86::DEC64m;
1995 if (LdVT == MVT::i32) return X86::DEC32m;
1996 if (LdVT == MVT::i16) return X86::DEC16m;
1997 if (LdVT == MVT::i8) return X86::DEC8m;
1999 assert(Opc == X86ISD::INC && "unrecognized opcode");
2000 if (LdVT == MVT::i64) return X86::INC64m;
2001 if (LdVT == MVT::i32) return X86::INC32m;
2002 if (LdVT == MVT::i16) return X86::INC16m;
2003 if (LdVT == MVT::i8) return X86::INC8m;
2005 llvm_unreachable("unrecognized size for LdVT");
2008 /// SelectGather - Customized ISel for GATHER operations.
2010 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
2011 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
2012 SDValue Chain = Node->getOperand(0);
2013 SDValue VSrc = Node->getOperand(2);
2014 SDValue Base = Node->getOperand(3);
2015 SDValue VIdx = Node->getOperand(4);
2016 SDValue VMask = Node->getOperand(5);
2017 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
2021 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
2024 // Memory Operands: Base, Scale, Index, Disp, Segment
2025 SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
2026 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
2027 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,
2028 Disp, Segment, VMask, Chain};
2029 SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node), VTs, Ops);
2030 // Node has 2 outputs: VDst and MVT::Other.
2031 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
2032 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
2034 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
2035 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
2039 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
2040 MVT NVT = Node->getSimpleValueType(0);
2042 unsigned Opcode = Node->getOpcode();
2045 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
2047 if (Node->isMachineOpcode()) {
2048 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
2049 Node->setNodeId(-1);
2050 return nullptr; // Already selected.
2055 case ISD::INTRINSIC_W_CHAIN: {
2056 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2059 case Intrinsic::x86_avx2_gather_d_pd:
2060 case Intrinsic::x86_avx2_gather_d_pd_256:
2061 case Intrinsic::x86_avx2_gather_q_pd:
2062 case Intrinsic::x86_avx2_gather_q_pd_256:
2063 case Intrinsic::x86_avx2_gather_d_ps:
2064 case Intrinsic::x86_avx2_gather_d_ps_256:
2065 case Intrinsic::x86_avx2_gather_q_ps:
2066 case Intrinsic::x86_avx2_gather_q_ps_256:
2067 case Intrinsic::x86_avx2_gather_d_q:
2068 case Intrinsic::x86_avx2_gather_d_q_256:
2069 case Intrinsic::x86_avx2_gather_q_q:
2070 case Intrinsic::x86_avx2_gather_q_q_256:
2071 case Intrinsic::x86_avx2_gather_d_d:
2072 case Intrinsic::x86_avx2_gather_d_d_256:
2073 case Intrinsic::x86_avx2_gather_q_d:
2074 case Intrinsic::x86_avx2_gather_q_d_256: {
2075 if (!Subtarget->hasAVX2())
2079 default: llvm_unreachable("Impossible intrinsic");
2080 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2081 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2082 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2083 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2084 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2085 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2086 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2087 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2088 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2089 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2090 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2091 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2092 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2093 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2094 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2095 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2097 SDNode *RetVal = SelectGather(Node, Opc);
2099 // We already called ReplaceUses inside SelectGather.
2106 case X86ISD::GlobalBaseReg:
2107 return getGlobalBaseReg();
2110 case ISD::ATOMIC_LOAD_XOR:
2111 case ISD::ATOMIC_LOAD_AND:
2112 case ISD::ATOMIC_LOAD_OR:
2113 case ISD::ATOMIC_LOAD_ADD: {
2114 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2122 // For operations of the form (x << C1) op C2, check if we can use a smaller
2123 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2124 SDValue N0 = Node->getOperand(0);
2125 SDValue N1 = Node->getOperand(1);
2127 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2130 // i8 is unshrinkable, i16 should be promoted to i32.
2131 if (NVT != MVT::i32 && NVT != MVT::i64)
2134 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2135 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2136 if (!Cst || !ShlCst)
2139 int64_t Val = Cst->getSExtValue();
2140 uint64_t ShlVal = ShlCst->getZExtValue();
2142 // Make sure that we don't change the operation by removing bits.
2143 // This only matters for OR and XOR, AND is unaffected.
2144 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2145 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2151 // Check the minimum bitwidth for the new constant.
2152 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2153 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2154 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2155 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2157 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2160 // Bail if there is no smaller encoding.
2164 switch (NVT.SimpleTy) {
2165 default: llvm_unreachable("Unsupported VT!");
2167 assert(CstVT == MVT::i8);
2168 ShlOp = X86::SHL32ri;
2171 default: llvm_unreachable("Impossible opcode");
2172 case ISD::AND: Op = X86::AND32ri8; break;
2173 case ISD::OR: Op = X86::OR32ri8; break;
2174 case ISD::XOR: Op = X86::XOR32ri8; break;
2178 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2179 ShlOp = X86::SHL64ri;
2182 default: llvm_unreachable("Impossible opcode");
2183 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2184 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2185 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2190 // Emit the smaller op and the shift.
2191 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
2192 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2193 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2196 case X86ISD::UMUL: {
2197 SDValue N0 = Node->getOperand(0);
2198 SDValue N1 = Node->getOperand(1);
2201 switch (NVT.SimpleTy) {
2202 default: llvm_unreachable("Unsupported VT!");
2203 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2204 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2205 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2206 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2209 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2210 N0, SDValue()).getValue(1);
2212 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2213 SDValue Ops[] = {N1, InFlag};
2214 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2216 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2217 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2218 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2222 case ISD::SMUL_LOHI:
2223 case ISD::UMUL_LOHI: {
2224 SDValue N0 = Node->getOperand(0);
2225 SDValue N1 = Node->getOperand(1);
2227 bool isSigned = Opcode == ISD::SMUL_LOHI;
2228 bool hasBMI2 = Subtarget->hasBMI2();
2230 switch (NVT.SimpleTy) {
2231 default: llvm_unreachable("Unsupported VT!");
2232 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2233 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2234 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2235 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2236 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2237 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2240 switch (NVT.SimpleTy) {
2241 default: llvm_unreachable("Unsupported VT!");
2242 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2243 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2244 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2245 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2249 unsigned SrcReg, LoReg, HiReg;
2251 default: llvm_unreachable("Unknown MUL opcode!");
2254 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2258 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2262 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2266 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2269 SrcReg = X86::EDX; LoReg = HiReg = 0;
2272 SrcReg = X86::RDX; LoReg = HiReg = 0;
2276 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2277 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2278 // Multiply is commmutative.
2280 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2285 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2286 N0, SDValue()).getValue(1);
2287 SDValue ResHi, ResLo;
2291 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2293 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2294 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2295 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2296 ResHi = SDValue(CNode, 0);
2297 ResLo = SDValue(CNode, 1);
2298 Chain = SDValue(CNode, 2);
2299 InFlag = SDValue(CNode, 3);
2301 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2302 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2303 Chain = SDValue(CNode, 0);
2304 InFlag = SDValue(CNode, 1);
2307 // Update the chain.
2308 ReplaceUses(N1.getValue(1), Chain);
2310 SDValue Ops[] = { N1, InFlag };
2311 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2312 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2313 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2314 ResHi = SDValue(CNode, 0);
2315 ResLo = SDValue(CNode, 1);
2316 InFlag = SDValue(CNode, 2);
2318 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2319 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2320 InFlag = SDValue(CNode, 0);
2324 // Prevent use of AH in a REX instruction by referencing AX instead.
2325 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2326 !SDValue(Node, 1).use_empty()) {
2327 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2328 X86::AX, MVT::i16, InFlag);
2329 InFlag = Result.getValue(2);
2330 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2332 if (!SDValue(Node, 0).use_empty())
2333 ReplaceUses(SDValue(Node, 1),
2334 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2336 // Shift AX down 8 bits.
2337 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2339 CurDAG->getTargetConstant(8, MVT::i8)), 0);
2340 // Then truncate it down to i8.
2341 ReplaceUses(SDValue(Node, 1),
2342 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2344 // Copy the low half of the result, if it is needed.
2345 if (!SDValue(Node, 0).use_empty()) {
2346 if (!ResLo.getNode()) {
2347 assert(LoReg && "Register for low half is not defined!");
2348 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2350 InFlag = ResLo.getValue(2);
2352 ReplaceUses(SDValue(Node, 0), ResLo);
2353 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2355 // Copy the high half of the result, if it is needed.
2356 if (!SDValue(Node, 1).use_empty()) {
2357 if (!ResHi.getNode()) {
2358 assert(HiReg && "Register for high half is not defined!");
2359 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2361 InFlag = ResHi.getValue(2);
2363 ReplaceUses(SDValue(Node, 1), ResHi);
2364 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2371 case ISD::UDIVREM: {
2372 SDValue N0 = Node->getOperand(0);
2373 SDValue N1 = Node->getOperand(1);
2375 bool isSigned = Opcode == ISD::SDIVREM;
2377 switch (NVT.SimpleTy) {
2378 default: llvm_unreachable("Unsupported VT!");
2379 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2380 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2381 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2382 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2385 switch (NVT.SimpleTy) {
2386 default: llvm_unreachable("Unsupported VT!");
2387 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2388 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2389 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2390 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2394 unsigned LoReg, HiReg, ClrReg;
2395 unsigned SExtOpcode;
2396 switch (NVT.SimpleTy) {
2397 default: llvm_unreachable("Unsupported VT!");
2399 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2400 SExtOpcode = X86::CBW;
2403 LoReg = X86::AX; HiReg = X86::DX;
2405 SExtOpcode = X86::CWD;
2408 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2409 SExtOpcode = X86::CDQ;
2412 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2413 SExtOpcode = X86::CQO;
2417 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2418 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2419 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2422 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2423 // Special case for div8, just use a move with zero extension to AX to
2424 // clear the upper 8 bits (AH).
2425 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2426 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2427 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2429 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2430 MVT::Other, Ops), 0);
2431 Chain = Move.getValue(1);
2432 ReplaceUses(N0.getValue(1), Chain);
2435 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2436 Chain = CurDAG->getEntryNode();
2438 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2439 InFlag = Chain.getValue(1);
2442 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2443 LoReg, N0, SDValue()).getValue(1);
2444 if (isSigned && !signBitIsZero) {
2445 // Sign extend the low part into the high part.
2447 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2449 // Zero out the high part, effectively zero extending the input.
2450 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
2451 switch (NVT.SimpleTy) {
2454 SDValue(CurDAG->getMachineNode(
2455 TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
2456 CurDAG->getTargetConstant(X86::sub_16bit, MVT::i32)),
2463 SDValue(CurDAG->getMachineNode(
2464 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2465 CurDAG->getTargetConstant(0, MVT::i64), ClrNode,
2466 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
2470 llvm_unreachable("Unexpected division source");
2473 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2474 ClrNode, InFlag).getValue(1);
2479 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2482 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops);
2483 InFlag = SDValue(CNode, 1);
2484 // Update the chain.
2485 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2488 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2491 // Prevent use of AH in a REX instruction by referencing AX instead.
2492 // Shift it down 8 bits.
2494 // The current assumption of the register allocator is that isel
2495 // won't generate explicit references to the GPR8_NOREX registers. If
2496 // the allocator and/or the backend get enhanced to be more robust in
2497 // that regard, this can be, and should be, removed.
2498 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2499 !SDValue(Node, 1).use_empty()) {
2500 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2501 X86::AX, MVT::i16, InFlag);
2502 InFlag = Result.getValue(2);
2504 // If we also need AL (the quotient), get it by extracting a subreg from
2505 // Result. The fast register allocator does not like multiple CopyFromReg
2506 // nodes using aliasing registers.
2507 if (!SDValue(Node, 0).use_empty())
2508 ReplaceUses(SDValue(Node, 0),
2509 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2511 // Shift AX right by 8 bits instead of using AH.
2512 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2514 CurDAG->getTargetConstant(8, MVT::i8)),
2516 ReplaceUses(SDValue(Node, 1),
2517 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2519 // Copy the division (low) result, if it is needed.
2520 if (!SDValue(Node, 0).use_empty()) {
2521 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2522 LoReg, NVT, InFlag);
2523 InFlag = Result.getValue(2);
2524 ReplaceUses(SDValue(Node, 0), Result);
2525 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2527 // Copy the remainder (high) result, if it is needed.
2528 if (!SDValue(Node, 1).use_empty()) {
2529 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2530 HiReg, NVT, InFlag);
2531 InFlag = Result.getValue(2);
2532 ReplaceUses(SDValue(Node, 1), Result);
2533 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2540 // Sometimes a SUB is used to perform comparison.
2541 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2542 // This node is not a CMP.
2544 SDValue N0 = Node->getOperand(0);
2545 SDValue N1 = Node->getOperand(1);
2547 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2548 // use a smaller encoding.
2549 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2550 HasNoSignedComparisonUses(Node))
2551 // Look past the truncate if CMP is the only use of it.
2552 N0 = N0.getOperand(0);
2553 if ((N0.getNode()->getOpcode() == ISD::AND ||
2554 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2555 N0.getNode()->hasOneUse() &&
2556 N0.getValueType() != MVT::i8 &&
2557 X86::isZeroNode(N1)) {
2558 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2561 // For example, convert "testl %eax, $8" to "testb %al, $8"
2562 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2563 (!(C->getZExtValue() & 0x80) ||
2564 HasNoSignedComparisonUses(Node))) {
2565 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2566 SDValue Reg = N0.getNode()->getOperand(0);
2568 // On x86-32, only the ABCD registers have 8-bit subregisters.
2569 if (!Subtarget->is64Bit()) {
2570 const TargetRegisterClass *TRC;
2571 switch (N0.getSimpleValueType().SimpleTy) {
2572 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2573 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2574 default: llvm_unreachable("Unsupported TEST operand type!");
2576 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2577 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2578 Reg.getValueType(), Reg, RC), 0);
2581 // Extract the l-register.
2582 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2586 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2588 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2589 // one, do not call ReplaceAllUsesWith.
2590 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2591 SDValue(NewNode, 0));
2595 // For example, "testl %eax, $2048" to "testb %ah, $8".
2596 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2597 (!(C->getZExtValue() & 0x8000) ||
2598 HasNoSignedComparisonUses(Node))) {
2599 // Shift the immediate right by 8 bits.
2600 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2602 SDValue Reg = N0.getNode()->getOperand(0);
2604 // Put the value in an ABCD register.
2605 const TargetRegisterClass *TRC;
2606 switch (N0.getSimpleValueType().SimpleTy) {
2607 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2608 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2609 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2610 default: llvm_unreachable("Unsupported TEST operand type!");
2612 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2613 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2614 Reg.getValueType(), Reg, RC), 0);
2616 // Extract the h-register.
2617 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2620 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2621 // target GR8_NOREX registers, so make sure the register class is
2623 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2624 MVT::i32, Subreg, ShiftedImm);
2625 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2626 // one, do not call ReplaceAllUsesWith.
2627 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2628 SDValue(NewNode, 0));
2632 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2633 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2634 N0.getValueType() != MVT::i16 &&
2635 (!(C->getZExtValue() & 0x8000) ||
2636 HasNoSignedComparisonUses(Node))) {
2637 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2638 SDValue Reg = N0.getNode()->getOperand(0);
2640 // Extract the 16-bit subregister.
2641 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2645 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2647 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2648 // one, do not call ReplaceAllUsesWith.
2649 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2650 SDValue(NewNode, 0));
2654 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2655 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2656 N0.getValueType() == MVT::i64 &&
2657 (!(C->getZExtValue() & 0x80000000) ||
2658 HasNoSignedComparisonUses(Node))) {
2659 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2660 SDValue Reg = N0.getNode()->getOperand(0);
2662 // Extract the 32-bit subregister.
2663 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2667 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2669 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2670 // one, do not call ReplaceAllUsesWith.
2671 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2672 SDValue(NewNode, 0));
2679 // Change a chain of {load; incr or dec; store} of the same value into
2680 // a simple increment or decrement through memory of that value, if the
2681 // uses of the modified value and its address are suitable.
2682 // The DEC64m tablegen pattern is currently not able to match the case where
2683 // the EFLAGS on the original DEC are used. (This also applies to
2684 // {INC,DEC}X{64,32,16,8}.)
2685 // We'll need to improve tablegen to allow flags to be transferred from a
2686 // node in the pattern to the result node. probably with a new keyword
2687 // for example, we have this
2688 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2689 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2690 // (implicit EFLAGS)]>;
2691 // but maybe need something like this
2692 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2693 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2694 // (transferrable EFLAGS)]>;
2696 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2697 SDValue StoredVal = StoreNode->getOperand(1);
2698 unsigned Opc = StoredVal->getOpcode();
2700 LoadSDNode *LoadNode = nullptr;
2702 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2703 LoadNode, InputChain))
2706 SDValue Base, Scale, Index, Disp, Segment;
2707 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2708 Base, Scale, Index, Disp, Segment))
2711 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2712 MemOp[0] = StoreNode->getMemOperand();
2713 MemOp[1] = LoadNode->getMemOperand();
2714 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2715 EVT LdVT = LoadNode->getMemoryVT();
2716 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2717 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2719 MVT::i32, MVT::Other, Ops);
2720 Result->setMemRefs(MemOp, MemOp + 2);
2722 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2723 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2729 SDNode *ResNode = SelectCode(Node);
2731 DEBUG(dbgs() << "=> ";
2732 if (ResNode == nullptr || ResNode == Node)
2735 ResNode->dump(CurDAG);
2741 bool X86DAGToDAGISel::
2742 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2743 std::vector<SDValue> &OutOps) {
2744 SDValue Op0, Op1, Op2, Op3, Op4;
2745 switch (ConstraintCode) {
2746 case 'o': // offsetable ??
2747 case 'v': // not offsetable ??
2748 default: return true;
2750 if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
2755 OutOps.push_back(Op0);
2756 OutOps.push_back(Op1);
2757 OutOps.push_back(Op2);
2758 OutOps.push_back(Op3);
2759 OutOps.push_back(Op4);
2763 /// createX86ISelDag - This pass converts a legalized DAG into a
2764 /// X86-specific DAG, ready for instruction scheduling.
2766 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2767 CodeGenOpt::Level OptLevel) {
2768 return new X86DAGToDAGISel(TM, OptLevel);