1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
40 #define DEBUG_TYPE "x86-isel"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
50 /// SDValue's instead of register numbers for the leaves of the matched
52 struct X86ISelAddressMode {
58 // This is really a union, discriminated by BaseType!
66 const GlobalValue *GV;
68 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr),
77 JT(-1), Align(0), SymbolFlags(X86II::MO_NO_FLAG) {
80 bool hasSymbolicDisplacement() const {
81 return GV != nullptr || CP != nullptr || ES != nullptr ||
82 JT != -1 || BlockAddr != nullptr;
85 bool hasBaseOrIndexReg() const {
86 return BaseType == FrameIndexBase ||
87 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
90 /// isRIPRelative - Return true if this addressing mode is already RIP
92 bool isRIPRelative() const {
93 if (BaseType != RegBase) return false;
94 if (RegisterSDNode *RegNode =
95 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
96 return RegNode->getReg() == X86::RIP;
100 void setBaseReg(SDValue Reg) {
105 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
107 dbgs() << "X86ISelAddressMode " << this << '\n';
108 dbgs() << "Base_Reg ";
109 if (Base_Reg.getNode())
110 Base_Reg.getNode()->dump();
113 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
114 << " Scale" << Scale << '\n'
116 if (IndexReg.getNode())
117 IndexReg.getNode()->dump();
120 dbgs() << " Disp " << Disp << '\n'
137 dbgs() << " JT" << JT << " Align" << Align << '\n';
144 //===--------------------------------------------------------------------===//
145 /// ISel - X86 specific code to select X86 machine instructions for
146 /// SelectionDAG operations.
148 class X86DAGToDAGISel final : public SelectionDAGISel {
149 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
150 /// make the right decision when generating code for different targets.
151 const X86Subtarget *Subtarget;
153 /// OptForSize - If true, selector should try to optimize for code size
154 /// instead of performance.
158 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
159 : SelectionDAGISel(tm, OptLevel), OptForSize(false) {}
161 const char *getPassName() const override {
162 return "X86 DAG->DAG Instruction Selection";
165 bool runOnMachineFunction(MachineFunction &MF) override {
166 // Reset the subtarget each time through.
167 Subtarget = &MF.getSubtarget<X86Subtarget>();
168 SelectionDAGISel::runOnMachineFunction(MF);
172 void EmitFunctionEntryCode() override;
174 bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
176 void PreprocessISelDAG() override;
178 inline bool immSext8(SDNode *N) const {
179 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
182 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
183 // sign extended field.
184 inline bool i64immSExt32(SDNode *N) const {
185 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
186 return (int64_t)v == (int32_t)v;
189 // Include the pieces autogenerated from the target description.
190 #include "X86GenDAGISel.inc"
193 SDNode *Select(SDNode *N) override;
194 SDNode *SelectGather(SDNode *N, unsigned Opc);
195 SDNode *SelectAtomicLoadArith(SDNode *Node, MVT NVT);
197 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
198 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
199 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
200 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
201 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
203 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
204 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
205 SDValue &Scale, SDValue &Index, SDValue &Disp,
207 bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
208 bool SelectLEAAddr(SDValue N, SDValue &Base,
209 SDValue &Scale, SDValue &Index, SDValue &Disp,
211 bool SelectLEA64_32Addr(SDValue N, SDValue &Base,
212 SDValue &Scale, SDValue &Index, SDValue &Disp,
214 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
215 SDValue &Scale, SDValue &Index, SDValue &Disp,
217 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
218 SDValue &Base, SDValue &Scale,
219 SDValue &Index, SDValue &Disp,
221 SDValue &NodeWithChain);
223 bool TryFoldLoad(SDNode *P, SDValue N,
224 SDValue &Base, SDValue &Scale,
225 SDValue &Index, SDValue &Disp,
228 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
229 /// inline asm expressions.
230 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
231 unsigned ConstraintID,
232 std::vector<SDValue> &OutOps) override;
234 void EmitSpecialCodeForMain();
236 inline void getAddressOperands(X86ISelAddressMode &AM, SDLoc DL,
237 SDValue &Base, SDValue &Scale,
238 SDValue &Index, SDValue &Disp,
240 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
241 ? CurDAG->getTargetFrameIndex(AM.Base_FrameIndex,
244 Scale = getI8Imm(AM.Scale, DL);
246 // These are 32-bit even in 64-bit mode since RIP relative offset
249 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(),
253 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
254 AM.Align, AM.Disp, AM.SymbolFlags);
256 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
257 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
258 } else if (AM.JT != -1) {
259 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
260 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
261 } else if (AM.BlockAddr)
262 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
265 Disp = CurDAG->getTargetConstant(AM.Disp, DL, MVT::i32);
267 if (AM.Segment.getNode())
268 Segment = AM.Segment;
270 Segment = CurDAG->getRegister(0, MVT::i32);
273 /// getI8Imm - Return a target constant with the specified value, of type
275 inline SDValue getI8Imm(unsigned Imm, SDLoc DL) {
276 return CurDAG->getTargetConstant(Imm, DL, MVT::i8);
279 /// getI32Imm - Return a target constant with the specified value, of type
281 inline SDValue getI32Imm(unsigned Imm, SDLoc DL) {
282 return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
285 /// getGlobalBaseReg - Return an SDNode that returns the value of
286 /// the global base register. Output instructions required to
287 /// initialize the global base register, if necessary.
289 SDNode *getGlobalBaseReg();
291 /// getTargetMachine - Return a reference to the TargetMachine, casted
292 /// to the target-specific type.
293 const X86TargetMachine &getTargetMachine() const {
294 return static_cast<const X86TargetMachine &>(TM);
297 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
298 /// to the target-specific type.
299 const X86InstrInfo *getInstrInfo() const {
300 return Subtarget->getInstrInfo();
303 /// \brief Address-mode matching performs shift-of-and to and-of-shift
304 /// reassociation in order to expose more scaled addressing
306 bool ComplexPatternFuncMutatesDAG() const override {
314 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
315 if (OptLevel == CodeGenOpt::None) return false;
320 if (N.getOpcode() != ISD::LOAD)
323 // If N is a load, do additional profitability checks.
325 switch (U->getOpcode()) {
338 SDValue Op1 = U->getOperand(1);
340 // If the other operand is a 8-bit immediate we should fold the immediate
341 // instead. This reduces code size.
343 // movl 4(%esp), %eax
347 // addl 4(%esp), %eax
348 // The former is 2 bytes shorter. In case where the increment is 1, then
349 // the saving can be 4 bytes (by using incl %eax).
350 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
351 if (Imm->getAPIntValue().isSignedIntN(8))
354 // If the other operand is a TLS address, we should fold it instead.
357 // leal i@NTPOFF(%eax), %eax
359 // movl $i@NTPOFF, %eax
361 // if the block also has an access to a second TLS address this will save
363 // FIXME: This is probably also true for non-TLS addresses.
364 if (Op1.getOpcode() == X86ISD::Wrapper) {
365 SDValue Val = Op1.getOperand(0);
366 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
376 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
377 /// load's chain operand and move load below the call's chain operand.
378 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
379 SDValue Call, SDValue OrigChain) {
380 SmallVector<SDValue, 8> Ops;
381 SDValue Chain = OrigChain.getOperand(0);
382 if (Chain.getNode() == Load.getNode())
383 Ops.push_back(Load.getOperand(0));
385 assert(Chain.getOpcode() == ISD::TokenFactor &&
386 "Unexpected chain operand");
387 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
388 if (Chain.getOperand(i).getNode() == Load.getNode())
389 Ops.push_back(Load.getOperand(0));
391 Ops.push_back(Chain.getOperand(i));
393 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops);
395 Ops.push_back(NewChain);
397 Ops.append(OrigChain->op_begin() + 1, OrigChain->op_end());
398 CurDAG->UpdateNodeOperands(OrigChain.getNode(), Ops);
399 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
400 Load.getOperand(1), Load.getOperand(2));
403 Ops.push_back(SDValue(Load.getNode(), 1));
404 Ops.append(Call->op_begin() + 1, Call->op_end());
405 CurDAG->UpdateNodeOperands(Call.getNode(), Ops);
408 /// isCalleeLoad - Return true if call address is a load and it can be
409 /// moved below CALLSEQ_START and the chains leading up to the call.
410 /// Return the CALLSEQ_START by reference as a second output.
411 /// In the case of a tail call, there isn't a callseq node between the call
412 /// chain and the load.
413 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
414 // The transformation is somewhat dangerous if the call's chain was glued to
415 // the call. After MoveBelowOrigChain the load is moved between the call and
416 // the chain, this can create a cycle if the load is not folded. So it is
417 // *really* important that we are sure the load will be folded.
418 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
420 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
423 LD->getAddressingMode() != ISD::UNINDEXED ||
424 LD->getExtensionType() != ISD::NON_EXTLOAD)
427 // Now let's find the callseq_start.
428 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
429 if (!Chain.hasOneUse())
431 Chain = Chain.getOperand(0);
434 if (!Chain.getNumOperands())
436 // Since we are not checking for AA here, conservatively abort if the chain
437 // writes to memory. It's not safe to move the callee (a load) across a store.
438 if (isa<MemSDNode>(Chain.getNode()) &&
439 cast<MemSDNode>(Chain.getNode())->writeMem())
441 if (Chain.getOperand(0).getNode() == Callee.getNode())
443 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
444 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
445 Callee.getValue(1).hasOneUse())
450 void X86DAGToDAGISel::PreprocessISelDAG() {
451 // OptForSize is used in pattern predicates that isel is matching.
452 OptForSize = MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
454 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
455 E = CurDAG->allnodes_end(); I != E; ) {
456 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
458 if (OptLevel != CodeGenOpt::None &&
459 // Only does this when target favors doesn't favor register indirect
461 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
462 (N->getOpcode() == X86ISD::TC_RETURN &&
463 // Only does this if load can be folded into TC_RETURN.
464 (Subtarget->is64Bit() ||
465 getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
466 /// Also try moving call address load from outside callseq_start to just
467 /// before the call to allow it to be folded.
485 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
486 SDValue Chain = N->getOperand(0);
487 SDValue Load = N->getOperand(1);
488 if (!isCalleeLoad(Load, Chain, HasCallSeq))
490 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
495 // Lower fpround and fpextend nodes that target the FP stack to be store and
496 // load to the stack. This is a gross hack. We would like to simply mark
497 // these as being illegal, but when we do that, legalize produces these when
498 // it expands calls, then expands these in the same legalize pass. We would
499 // like dag combine to be able to hack on these between the call expansion
500 // and the node legalization. As such this pass basically does "really
501 // late" legalization of these inline with the X86 isel pass.
502 // FIXME: This should only happen when not compiled with -O0.
503 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
506 MVT SrcVT = N->getOperand(0).getSimpleValueType();
507 MVT DstVT = N->getSimpleValueType(0);
509 // If any of the sources are vectors, no fp stack involved.
510 if (SrcVT.isVector() || DstVT.isVector())
513 // If the source and destination are SSE registers, then this is a legal
514 // conversion that should not be lowered.
515 const X86TargetLowering *X86Lowering =
516 static_cast<const X86TargetLowering *>(TLI);
517 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
518 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
519 if (SrcIsSSE && DstIsSSE)
522 if (!SrcIsSSE && !DstIsSSE) {
523 // If this is an FPStack extension, it is a noop.
524 if (N->getOpcode() == ISD::FP_EXTEND)
526 // If this is a value-preserving FPStack truncation, it is a noop.
527 if (N->getConstantOperandVal(1))
531 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
532 // FPStack has extload and truncstore. SSE can fold direct loads into other
533 // operations. Based on this, decide what we want to do.
535 if (N->getOpcode() == ISD::FP_ROUND)
536 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
538 MemVT = SrcIsSSE ? SrcVT : DstVT;
540 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
543 // FIXME: optimize the case where the src/dest is a load or store?
544 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
546 MemTmp, MachinePointerInfo(), MemVT,
548 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
549 MachinePointerInfo(),
550 MemVT, false, false, false, 0);
552 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
553 // extload we created. This will cause general havok on the dag because
554 // anything below the conversion could be folded into other existing nodes.
555 // To avoid invalidating 'I', back it up to the convert node.
557 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
559 // Now that we did that, the node is dead. Increment the iterator to the
560 // next node to process, then delete N.
562 CurDAG->DeleteNode(N);
567 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
568 /// the main function.
569 void X86DAGToDAGISel::EmitSpecialCodeForMain() {
570 if (Subtarget->isTargetCygMing()) {
571 TargetLowering::ArgListTy Args;
573 TargetLowering::CallLoweringInfo CLI(*CurDAG);
574 CLI.setChain(CurDAG->getRoot())
575 .setCallee(CallingConv::C, Type::getVoidTy(*CurDAG->getContext()),
576 CurDAG->getExternalSymbol("__main", TLI->getPointerTy()),
578 const TargetLowering &TLI = CurDAG->getTargetLoweringInfo();
579 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
580 CurDAG->setRoot(Result.second);
584 void X86DAGToDAGISel::EmitFunctionEntryCode() {
585 // If this is main, emit special code for main.
586 if (const Function *Fn = MF->getFunction())
587 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
588 EmitSpecialCodeForMain();
591 static bool isDispSafeForFrameIndex(int64_t Val) {
592 // On 64-bit platforms, we can run into an issue where a frame index
593 // includes a displacement that, when added to the explicit displacement,
594 // will overflow the displacement field. Assuming that the frame index
595 // displacement fits into a 31-bit integer (which is only slightly more
596 // aggressive than the current fundamental assumption that it fits into
597 // a 32-bit integer), a 31-bit disp should always be safe.
598 return isInt<31>(Val);
601 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
602 X86ISelAddressMode &AM) {
603 int64_t Val = AM.Disp + Offset;
604 CodeModel::Model M = TM.getCodeModel();
605 if (Subtarget->is64Bit()) {
606 if (!X86::isOffsetSuitableForCodeModel(Val, M,
607 AM.hasSymbolicDisplacement()))
609 // In addition to the checks required for a register base, check that
610 // we do not try to use an unsafe Disp with a frame index.
611 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
612 !isDispSafeForFrameIndex(Val))
620 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
621 SDValue Address = N->getOperand(1);
623 // load gs:0 -> GS segment register.
624 // load fs:0 -> FS segment register.
626 // This optimization is valid because the GNU TLS model defines that
627 // gs:0 (or fs:0 on X86-64) contains its own address.
628 // For more information see http://people.redhat.com/drepper/tls.pdf
629 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
630 if (C->getSExtValue() == 0 && AM.Segment.getNode() == nullptr &&
631 Subtarget->isTargetLinux())
632 switch (N->getPointerInfo().getAddrSpace()) {
634 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
637 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
644 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
645 /// into an addressing mode. These wrap things that will resolve down into a
646 /// symbol reference. If no match is possible, this returns true, otherwise it
648 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
649 // If the addressing mode already has a symbol as the displacement, we can
650 // never match another symbol.
651 if (AM.hasSymbolicDisplacement())
654 SDValue N0 = N.getOperand(0);
655 CodeModel::Model M = TM.getCodeModel();
657 // Handle X86-64 rip-relative addresses. We check this before checking direct
658 // folding because RIP is preferable to non-RIP accesses.
659 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
660 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
661 // they cannot be folded into immediate fields.
662 // FIXME: This can be improved for kernel and other models?
663 (M == CodeModel::Small || M == CodeModel::Kernel)) {
664 // Base and index reg must be 0 in order to use %rip as base.
665 if (AM.hasBaseOrIndexReg())
667 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
668 X86ISelAddressMode Backup = AM;
669 AM.GV = G->getGlobal();
670 AM.SymbolFlags = G->getTargetFlags();
671 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
675 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
676 X86ISelAddressMode Backup = AM;
677 AM.CP = CP->getConstVal();
678 AM.Align = CP->getAlignment();
679 AM.SymbolFlags = CP->getTargetFlags();
680 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
684 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
685 AM.ES = S->getSymbol();
686 AM.SymbolFlags = S->getTargetFlags();
687 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
688 AM.JT = J->getIndex();
689 AM.SymbolFlags = J->getTargetFlags();
690 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
691 X86ISelAddressMode Backup = AM;
692 AM.BlockAddr = BA->getBlockAddress();
693 AM.SymbolFlags = BA->getTargetFlags();
694 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
699 llvm_unreachable("Unhandled symbol reference node.");
701 if (N.getOpcode() == X86ISD::WrapperRIP)
702 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
706 // Handle the case when globals fit in our immediate field: This is true for
707 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
708 // mode, this only applies to a non-RIP-relative computation.
709 if (!Subtarget->is64Bit() ||
710 M == CodeModel::Small || M == CodeModel::Kernel) {
711 assert(N.getOpcode() != X86ISD::WrapperRIP &&
712 "RIP-relative addressing already handled");
713 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
714 AM.GV = G->getGlobal();
715 AM.Disp += G->getOffset();
716 AM.SymbolFlags = G->getTargetFlags();
717 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
718 AM.CP = CP->getConstVal();
719 AM.Align = CP->getAlignment();
720 AM.Disp += CP->getOffset();
721 AM.SymbolFlags = CP->getTargetFlags();
722 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
723 AM.ES = S->getSymbol();
724 AM.SymbolFlags = S->getTargetFlags();
725 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
726 AM.JT = J->getIndex();
727 AM.SymbolFlags = J->getTargetFlags();
728 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
729 AM.BlockAddr = BA->getBlockAddress();
730 AM.Disp += BA->getOffset();
731 AM.SymbolFlags = BA->getTargetFlags();
733 llvm_unreachable("Unhandled symbol reference node.");
740 /// MatchAddress - Add the specified node to the specified addressing mode,
741 /// returning true if it cannot be done. This just pattern matches for the
743 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
744 if (MatchAddressRecursively(N, AM, 0))
747 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
748 // a smaller encoding and avoids a scaled-index.
750 AM.BaseType == X86ISelAddressMode::RegBase &&
751 AM.Base_Reg.getNode() == nullptr) {
752 AM.Base_Reg = AM.IndexReg;
756 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
757 // because it has a smaller encoding.
758 // TODO: Which other code models can use this?
759 if (TM.getCodeModel() == CodeModel::Small &&
760 Subtarget->is64Bit() &&
762 AM.BaseType == X86ISelAddressMode::RegBase &&
763 AM.Base_Reg.getNode() == nullptr &&
764 AM.IndexReg.getNode() == nullptr &&
765 AM.SymbolFlags == X86II::MO_NO_FLAG &&
766 AM.hasSymbolicDisplacement())
767 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
772 // Insert a node into the DAG at least before the Pos node's position. This
773 // will reposition the node as needed, and will assign it a node ID that is <=
774 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
775 // IDs! The selection DAG must no longer depend on their uniqueness when this
777 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
778 if (N.getNode()->getNodeId() == -1 ||
779 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
780 DAG.RepositionNode(Pos.getNode(), N.getNode());
781 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
785 // Transform "(X >> (8-C1)) & (0xff << C1)" to "((X >> 8) & 0xff) << C1" if
786 // safe. This allows us to convert the shift and and into an h-register
787 // extract and a scaled index. Returns false if the simplification is
789 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
791 SDValue Shift, SDValue X,
792 X86ISelAddressMode &AM) {
793 if (Shift.getOpcode() != ISD::SRL ||
794 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
798 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
799 if (ScaleLog <= 0 || ScaleLog >= 4 ||
800 Mask != (0xffu << ScaleLog))
803 MVT VT = N.getSimpleValueType();
805 SDValue Eight = DAG.getConstant(8, DL, MVT::i8);
806 SDValue NewMask = DAG.getConstant(0xff, DL, VT);
807 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
808 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
809 SDValue ShlCount = DAG.getConstant(ScaleLog, DL, MVT::i8);
810 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
812 // Insert the new nodes into the topological ordering. We must do this in
813 // a valid topological ordering as nothing is going to go back and re-sort
814 // these nodes. We continually insert before 'N' in sequence as this is
815 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
816 // hierarchy left to express.
817 InsertDAGNode(DAG, N, Eight);
818 InsertDAGNode(DAG, N, Srl);
819 InsertDAGNode(DAG, N, NewMask);
820 InsertDAGNode(DAG, N, And);
821 InsertDAGNode(DAG, N, ShlCount);
822 InsertDAGNode(DAG, N, Shl);
823 DAG.ReplaceAllUsesWith(N, Shl);
825 AM.Scale = (1 << ScaleLog);
829 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
830 // allows us to fold the shift into this addressing mode. Returns false if the
831 // transform succeeded.
832 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
834 SDValue Shift, SDValue X,
835 X86ISelAddressMode &AM) {
836 if (Shift.getOpcode() != ISD::SHL ||
837 !isa<ConstantSDNode>(Shift.getOperand(1)))
840 // Not likely to be profitable if either the AND or SHIFT node has more
841 // than one use (unless all uses are for address computation). Besides,
842 // isel mechanism requires their node ids to be reused.
843 if (!N.hasOneUse() || !Shift.hasOneUse())
846 // Verify that the shift amount is something we can fold.
847 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
848 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
851 MVT VT = N.getSimpleValueType();
853 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT);
854 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
855 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
857 // Insert the new nodes into the topological ordering. We must do this in
858 // a valid topological ordering as nothing is going to go back and re-sort
859 // these nodes. We continually insert before 'N' in sequence as this is
860 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
861 // hierarchy left to express.
862 InsertDAGNode(DAG, N, NewMask);
863 InsertDAGNode(DAG, N, NewAnd);
864 InsertDAGNode(DAG, N, NewShift);
865 DAG.ReplaceAllUsesWith(N, NewShift);
867 AM.Scale = 1 << ShiftAmt;
868 AM.IndexReg = NewAnd;
872 // Implement some heroics to detect shifts of masked values where the mask can
873 // be replaced by extending the shift and undoing that in the addressing mode
874 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
875 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
876 // the addressing mode. This results in code such as:
878 // int f(short *y, int *lookup_table) {
880 // return *y + lookup_table[*y >> 11];
884 // movzwl (%rdi), %eax
887 // addl (%rsi,%rcx,4), %eax
890 // movzwl (%rdi), %eax
894 // addl (%rsi,%rcx), %eax
896 // Note that this function assumes the mask is provided as a mask *after* the
897 // value is shifted. The input chain may or may not match that, but computing
898 // such a mask is trivial.
899 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
901 SDValue Shift, SDValue X,
902 X86ISelAddressMode &AM) {
903 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
904 !isa<ConstantSDNode>(Shift.getOperand(1)))
907 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
908 unsigned MaskLZ = countLeadingZeros(Mask);
909 unsigned MaskTZ = countTrailingZeros(Mask);
911 // The amount of shift we're trying to fit into the addressing mode is taken
912 // from the trailing zeros of the mask.
913 unsigned AMShiftAmt = MaskTZ;
915 // There is nothing we can do here unless the mask is removing some bits.
916 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
917 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
919 // We also need to ensure that mask is a continuous run of bits.
920 if (countTrailingOnes(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
922 // Scale the leading zero count down based on the actual size of the value.
923 // Also scale it down based on the size of the shift.
924 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
926 // The final check is to ensure that any masked out high bits of X are
927 // already known to be zero. Otherwise, the mask has a semantic impact
928 // other than masking out a couple of low bits. Unfortunately, because of
929 // the mask, zero extensions will be removed from operands in some cases.
930 // This code works extra hard to look through extensions because we can
931 // replace them with zero extensions cheaply if necessary.
932 bool ReplacingAnyExtend = false;
933 if (X.getOpcode() == ISD::ANY_EXTEND) {
934 unsigned ExtendBits = X.getSimpleValueType().getSizeInBits() -
935 X.getOperand(0).getSimpleValueType().getSizeInBits();
936 // Assume that we'll replace the any-extend with a zero-extend, and
937 // narrow the search to the extended value.
939 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
940 ReplacingAnyExtend = true;
942 APInt MaskedHighBits =
943 APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
944 APInt KnownZero, KnownOne;
945 DAG.computeKnownBits(X, KnownZero, KnownOne);
946 if (MaskedHighBits != KnownZero) return true;
948 // We've identified a pattern that can be transformed into a single shift
949 // and an addressing mode. Make it so.
950 MVT VT = N.getSimpleValueType();
951 if (ReplacingAnyExtend) {
952 assert(X.getValueType() != VT);
953 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
954 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
955 InsertDAGNode(DAG, N, NewX);
959 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8);
960 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
961 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, DL, MVT::i8);
962 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
964 // Insert the new nodes into the topological ordering. We must do this in
965 // a valid topological ordering as nothing is going to go back and re-sort
966 // these nodes. We continually insert before 'N' in sequence as this is
967 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
968 // hierarchy left to express.
969 InsertDAGNode(DAG, N, NewSRLAmt);
970 InsertDAGNode(DAG, N, NewSRL);
971 InsertDAGNode(DAG, N, NewSHLAmt);
972 InsertDAGNode(DAG, N, NewSHL);
973 DAG.ReplaceAllUsesWith(N, NewSHL);
975 AM.Scale = 1 << AMShiftAmt;
976 AM.IndexReg = NewSRL;
980 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
984 dbgs() << "MatchAddress: ";
989 return MatchAddressBase(N, AM);
991 // If this is already a %rip relative address, we can only merge immediates
992 // into it. Instead of handling this in every case, we handle it here.
993 // RIP relative addressing: %rip + 32-bit displacement!
994 if (AM.isRIPRelative()) {
995 // FIXME: JumpTable and ExternalSymbol address currently don't like
996 // displacements. It isn't very important, but this should be fixed for
998 if (!AM.ES && AM.JT != -1) return true;
1000 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
1001 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
1006 switch (N.getOpcode()) {
1008 case ISD::FRAME_ALLOC_RECOVER: {
1009 if (!AM.hasSymbolicDisplacement())
1010 if (const auto *ESNode = dyn_cast<ExternalSymbolSDNode>(N.getOperand(0)))
1011 if (ESNode->getOpcode() == ISD::TargetExternalSymbol) {
1012 // Use the symbol and don't prefix it.
1013 AM.ES = ESNode->getSymbol();
1014 AM.SymbolFlags = X86II::MO_NOPREFIX;
1019 case ISD::Constant: {
1020 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1021 if (!FoldOffsetIntoAddress(Val, AM))
1026 case X86ISD::Wrapper:
1027 case X86ISD::WrapperRIP:
1028 if (!MatchWrapper(N, AM))
1033 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
1037 case ISD::FrameIndex:
1038 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1039 AM.Base_Reg.getNode() == nullptr &&
1040 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
1041 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
1042 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1048 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1)
1052 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1053 unsigned Val = CN->getZExtValue();
1054 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1055 // that the base operand remains free for further matching. If
1056 // the base doesn't end up getting used, a post-processing step
1057 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1058 if (Val == 1 || Val == 2 || Val == 3) {
1059 AM.Scale = 1 << Val;
1060 SDValue ShVal = N.getNode()->getOperand(0);
1062 // Okay, we know that we have a scale by now. However, if the scaled
1063 // value is an add of something and a constant, we can fold the
1064 // constant into the disp field here.
1065 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1066 AM.IndexReg = ShVal.getNode()->getOperand(0);
1067 ConstantSDNode *AddVal =
1068 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1069 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1070 if (!FoldOffsetIntoAddress(Disp, AM))
1074 AM.IndexReg = ShVal;
1081 // Scale must not be used already.
1082 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1084 SDValue And = N.getOperand(0);
1085 if (And.getOpcode() != ISD::AND) break;
1086 SDValue X = And.getOperand(0);
1088 // We only handle up to 64-bit values here as those are what matter for
1089 // addressing mode optimizations.
1090 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1092 // The mask used for the transform is expected to be post-shift, but we
1093 // found the shift first so just apply the shift to the mask before passing
1095 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1096 !isa<ConstantSDNode>(And.getOperand(1)))
1098 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1100 // Try to fold the mask and shift into the scale, and return false if we
1102 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1107 case ISD::SMUL_LOHI:
1108 case ISD::UMUL_LOHI:
1109 // A mul_lohi where we need the low part can be folded as a plain multiply.
1110 if (N.getResNo() != 0) break;
1113 case X86ISD::MUL_IMM:
1114 // X*[3,5,9] -> X+X*[2,4,8]
1115 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1116 AM.Base_Reg.getNode() == nullptr &&
1117 AM.IndexReg.getNode() == nullptr) {
1119 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1120 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1121 CN->getZExtValue() == 9) {
1122 AM.Scale = unsigned(CN->getZExtValue())-1;
1124 SDValue MulVal = N.getNode()->getOperand(0);
1127 // Okay, we know that we have a scale by now. However, if the scaled
1128 // value is an add of something and a constant, we can fold the
1129 // constant into the disp field here.
1130 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1131 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1132 Reg = MulVal.getNode()->getOperand(0);
1133 ConstantSDNode *AddVal =
1134 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1135 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1136 if (FoldOffsetIntoAddress(Disp, AM))
1137 Reg = N.getNode()->getOperand(0);
1139 Reg = N.getNode()->getOperand(0);
1142 AM.IndexReg = AM.Base_Reg = Reg;
1149 // Given A-B, if A can be completely folded into the address and
1150 // the index field with the index field unused, use -B as the index.
1151 // This is a win if a has multiple parts that can be folded into
1152 // the address. Also, this saves a mov if the base register has
1153 // other uses, since it avoids a two-address sub instruction, however
1154 // it costs an additional mov if the index register has other uses.
1156 // Add an artificial use to this node so that we can keep track of
1157 // it if it gets CSE'd with a different node.
1158 HandleSDNode Handle(N);
1160 // Test if the LHS of the sub can be folded.
1161 X86ISelAddressMode Backup = AM;
1162 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1166 // Test if the index field is free for use.
1167 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1173 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1174 // If the RHS involves a register with multiple uses, this
1175 // transformation incurs an extra mov, due to the neg instruction
1176 // clobbering its operand.
1177 if (!RHS.getNode()->hasOneUse() ||
1178 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1179 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1180 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1181 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1182 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1184 // If the base is a register with multiple uses, this
1185 // transformation may save a mov.
1186 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1187 AM.Base_Reg.getNode() &&
1188 !AM.Base_Reg.getNode()->hasOneUse()) ||
1189 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1191 // If the folded LHS was interesting, this transformation saves
1192 // address arithmetic.
1193 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1194 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1195 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1197 // If it doesn't look like it may be an overall win, don't do it.
1203 // Ok, the transformation is legal and appears profitable. Go for it.
1204 SDValue Zero = CurDAG->getConstant(0, dl, N.getValueType());
1205 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1209 // Insert the new nodes into the topological ordering.
1210 InsertDAGNode(*CurDAG, N, Zero);
1211 InsertDAGNode(*CurDAG, N, Neg);
1216 // Add an artificial use to this node so that we can keep track of
1217 // it if it gets CSE'd with a different node.
1218 HandleSDNode Handle(N);
1220 X86ISelAddressMode Backup = AM;
1221 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1222 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1226 // Try again after commuting the operands.
1227 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1228 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1232 // If we couldn't fold both operands into the address at the same time,
1233 // see if we can just put each operand into a register and fold at least
1235 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1236 !AM.Base_Reg.getNode() &&
1237 !AM.IndexReg.getNode()) {
1238 N = Handle.getValue();
1239 AM.Base_Reg = N.getOperand(0);
1240 AM.IndexReg = N.getOperand(1);
1244 N = Handle.getValue();
1249 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1250 if (CurDAG->isBaseWithConstantOffset(N)) {
1251 X86ISelAddressMode Backup = AM;
1252 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1254 // Start with the LHS as an addr mode.
1255 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1256 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1263 // Perform some heroic transforms on an and of a constant-count shift
1264 // with a constant to enable use of the scaled offset field.
1266 // Scale must not be used already.
1267 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1269 SDValue Shift = N.getOperand(0);
1270 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1271 SDValue X = Shift.getOperand(0);
1273 // We only handle up to 64-bit values here as those are what matter for
1274 // addressing mode optimizations.
1275 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1277 if (!isa<ConstantSDNode>(N.getOperand(1)))
1279 uint64_t Mask = N.getConstantOperandVal(1);
1281 // Try to fold the mask and shift into an extract and scale.
1282 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1285 // Try to fold the mask and shift directly into the scale.
1286 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1289 // Try to swap the mask and shift to place shifts which can be done as
1290 // a scale on the outside of the mask.
1291 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1297 return MatchAddressBase(N, AM);
1300 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1301 /// specified addressing mode without any further recursion.
1302 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1303 // Is the base register already occupied?
1304 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1305 // If so, check to see if the scale index register is set.
1306 if (!AM.IndexReg.getNode()) {
1312 // Otherwise, we cannot select it.
1316 // Default, generate it as a register.
1317 AM.BaseType = X86ISelAddressMode::RegBase;
1322 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1323 /// It returns the operands which make up the maximal addressing mode it can
1324 /// match by reference.
1326 /// Parent is the parent node of the addr operand that is being matched. It
1327 /// is always a load, store, atomic node, or null. It is only null when
1328 /// checking memory operands for inline asm nodes.
1329 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1330 SDValue &Scale, SDValue &Index,
1331 SDValue &Disp, SDValue &Segment) {
1332 X86ISelAddressMode AM;
1335 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1336 // that are not a MemSDNode, and thus don't have proper addrspace info.
1337 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1338 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1339 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
1340 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
1341 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
1342 unsigned AddrSpace =
1343 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1344 // AddrSpace 256 -> GS, 257 -> FS.
1345 if (AddrSpace == 256)
1346 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1347 if (AddrSpace == 257)
1348 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1351 if (MatchAddress(N, AM))
1354 MVT VT = N.getSimpleValueType();
1355 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1356 if (!AM.Base_Reg.getNode())
1357 AM.Base_Reg = CurDAG->getRegister(0, VT);
1360 if (!AM.IndexReg.getNode())
1361 AM.IndexReg = CurDAG->getRegister(0, VT);
1363 getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
1367 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1368 /// match a load whose top elements are either undef or zeros. The load flavor
1369 /// is derived from the type of N, which is either v4f32 or v2f64.
1372 /// PatternChainNode: this is the matched node that has a chain input and
1374 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1375 SDValue N, SDValue &Base,
1376 SDValue &Scale, SDValue &Index,
1377 SDValue &Disp, SDValue &Segment,
1378 SDValue &PatternNodeWithChain) {
1379 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1380 PatternNodeWithChain = N.getOperand(0);
1381 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1382 PatternNodeWithChain.hasOneUse() &&
1383 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1384 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1385 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1386 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1392 // Also handle the case where we explicitly require zeros in the top
1393 // elements. This is a vector shuffle from the zero vector.
1394 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1395 // Check to see if the top elements are all zeros (or bitcast of zeros).
1396 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1397 N.getOperand(0).getNode()->hasOneUse() &&
1398 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1399 N.getOperand(0).getOperand(0).hasOneUse() &&
1400 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1401 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1402 // Okay, this is a zero extending load. Fold it.
1403 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1404 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1406 PatternNodeWithChain = SDValue(LD, 0);
1413 bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
1414 if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1415 uint64_t ImmVal = CN->getZExtValue();
1416 if ((uint32_t)ImmVal != (uint64_t)ImmVal)
1419 Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), MVT::i64);
1423 // In static codegen with small code model, we can get the address of a label
1424 // into a register with 'movl'. TableGen has already made sure we're looking
1425 // at a label of some kind.
1426 assert(N->getOpcode() == X86ISD::Wrapper &&
1427 "Unexpected node type for MOV32ri64");
1428 N = N.getOperand(0);
1430 if (N->getOpcode() != ISD::TargetConstantPool &&
1431 N->getOpcode() != ISD::TargetJumpTable &&
1432 N->getOpcode() != ISD::TargetGlobalAddress &&
1433 N->getOpcode() != ISD::TargetExternalSymbol &&
1434 N->getOpcode() != ISD::TargetBlockAddress)
1438 return TM.getCodeModel() == CodeModel::Small;
1441 bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
1442 SDValue &Scale, SDValue &Index,
1443 SDValue &Disp, SDValue &Segment) {
1444 if (!SelectLEAAddr(N, Base, Scale, Index, Disp, Segment))
1448 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
1449 if (RN && RN->getReg() == 0)
1450 Base = CurDAG->getRegister(0, MVT::i64);
1451 else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(Base)) {
1452 // Base could already be %rip, particularly in the x32 ABI.
1453 Base = SDValue(CurDAG->getMachineNode(
1454 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1455 CurDAG->getTargetConstant(0, DL, MVT::i64),
1457 CurDAG->getTargetConstant(X86::sub_32bit, DL, MVT::i32)),
1461 RN = dyn_cast<RegisterSDNode>(Index);
1462 if (RN && RN->getReg() == 0)
1463 Index = CurDAG->getRegister(0, MVT::i64);
1465 assert(Index.getValueType() == MVT::i32 &&
1466 "Expect to be extending 32-bit registers for use in LEA");
1467 Index = SDValue(CurDAG->getMachineNode(
1468 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1469 CurDAG->getTargetConstant(0, DL, MVT::i64),
1471 CurDAG->getTargetConstant(X86::sub_32bit, DL,
1479 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1480 /// mode it matches can be cost effectively emitted as an LEA instruction.
1481 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1482 SDValue &Base, SDValue &Scale,
1483 SDValue &Index, SDValue &Disp,
1485 X86ISelAddressMode AM;
1487 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1489 SDValue Copy = AM.Segment;
1490 SDValue T = CurDAG->getRegister(0, MVT::i32);
1492 if (MatchAddress(N, AM))
1494 assert (T == AM.Segment);
1497 MVT VT = N.getSimpleValueType();
1498 unsigned Complexity = 0;
1499 if (AM.BaseType == X86ISelAddressMode::RegBase)
1500 if (AM.Base_Reg.getNode())
1503 AM.Base_Reg = CurDAG->getRegister(0, VT);
1504 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1507 if (AM.IndexReg.getNode())
1510 AM.IndexReg = CurDAG->getRegister(0, VT);
1512 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1517 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1518 // to a LEA. This is determined with some expermentation but is by no means
1519 // optimal (especially for code size consideration). LEA is nice because of
1520 // its three-address nature. Tweak the cost function again when we can run
1521 // convertToThreeAddress() at register allocation time.
1522 if (AM.hasSymbolicDisplacement()) {
1523 // For X86-64, we should always use lea to materialize RIP relative
1525 if (Subtarget->is64Bit())
1531 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1534 // If it isn't worth using an LEA, reject it.
1535 if (Complexity <= 2)
1538 getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
1542 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1543 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1544 SDValue &Scale, SDValue &Index,
1545 SDValue &Disp, SDValue &Segment) {
1546 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1547 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1549 X86ISelAddressMode AM;
1550 AM.GV = GA->getGlobal();
1551 AM.Disp += GA->getOffset();
1552 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1553 AM.SymbolFlags = GA->getTargetFlags();
1555 if (N.getValueType() == MVT::i32) {
1557 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1559 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1562 getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
1567 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1568 SDValue &Base, SDValue &Scale,
1569 SDValue &Index, SDValue &Disp,
1571 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1572 !IsProfitableToFold(N, P, P) ||
1573 !IsLegalToFold(N, P, P, OptLevel))
1576 return SelectAddr(N.getNode(),
1577 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1580 /// getGlobalBaseReg - Return an SDNode that returns the value of
1581 /// the global base register. Output instructions required to
1582 /// initialize the global base register, if necessary.
1584 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1585 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1586 return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy()).getNode();
1589 /// Atomic opcode table
1617 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1628 X86::LOCK_ADD64mi32,
1641 X86::LOCK_SUB64mi32,
1693 X86::LOCK_AND64mi32,
1706 X86::LOCK_XOR64mi32,
1711 // Return the target constant operand for atomic-load-op and do simple
1712 // translations, such as from atomic-load-add to lock-sub. The return value is
1713 // one of the following 3 cases:
1714 // + target-constant, the operand could be supported as a target constant.
1715 // + empty, the operand is not needed any more with the new op selected.
1716 // + non-empty, otherwise.
1717 static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
1719 enum AtomicOpc &Op, MVT NVT,
1721 const X86Subtarget *Subtarget) {
1722 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
1723 int64_t CNVal = CN->getSExtValue();
1724 // Quit if not 32-bit imm.
1725 if ((int32_t)CNVal != CNVal)
1727 // Quit if INT32_MIN: it would be negated as it is negative and overflow,
1728 // producing an immediate that does not fit in the 32 bits available for
1729 // an immediate operand to sub. However, it still fits in 32 bits for the
1730 // add (since it is not negated) so we can return target-constant.
1731 if (CNVal == INT32_MIN)
1732 return CurDAG->getTargetConstant(CNVal, dl, NVT);
1733 // For atomic-load-add, we could do some optimizations.
1735 // Translate to INC/DEC if ADD by 1 or -1.
1736 if (((CNVal == 1) || (CNVal == -1)) && !Subtarget->slowIncDec()) {
1737 Op = (CNVal == 1) ? INC : DEC;
1738 // No more constant operand after being translated into INC/DEC.
1741 // Translate to SUB if ADD by negative value.
1747 return CurDAG->getTargetConstant(CNVal, dl, NVT);
1750 // If the value operand is single-used, try to optimize it.
1751 if (Op == ADD && Val.hasOneUse()) {
1752 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
1753 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1755 return Val.getOperand(1);
1757 // A special case for i16, which needs truncating as, in most cases, it's
1758 // promoted to i32. We will translate
1759 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
1760 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1761 Val.getOperand(0).getOpcode() == ISD::SUB &&
1762 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1764 Val = Val.getOperand(0);
1765 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1773 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, MVT NVT) {
1774 if (Node->hasAnyUseOfValue(0))
1779 // Optimize common patterns for __sync_or_and_fetch and similar arith
1780 // operations where the result is not used. This allows us to use the "lock"
1781 // version of the arithmetic instruction.
1782 SDValue Chain = Node->getOperand(0);
1783 SDValue Ptr = Node->getOperand(1);
1784 SDValue Val = Node->getOperand(2);
1785 SDValue Base, Scale, Index, Disp, Segment;
1786 if (!SelectAddr(Node, Ptr, Base, Scale, Index, Disp, Segment))
1789 // Which index into the table.
1791 switch (Node->getOpcode()) {
1794 case ISD::ATOMIC_LOAD_OR:
1797 case ISD::ATOMIC_LOAD_AND:
1800 case ISD::ATOMIC_LOAD_XOR:
1803 case ISD::ATOMIC_LOAD_ADD:
1808 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val, Subtarget);
1809 bool isUnOp = !Val.getNode();
1810 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
1813 switch (NVT.SimpleTy) {
1814 default: return nullptr;
1817 Opc = AtomicOpcTbl[Op][ConstantI8];
1819 Opc = AtomicOpcTbl[Op][I8];
1823 if (immSext8(Val.getNode()))
1824 Opc = AtomicOpcTbl[Op][SextConstantI16];
1826 Opc = AtomicOpcTbl[Op][ConstantI16];
1828 Opc = AtomicOpcTbl[Op][I16];
1832 if (immSext8(Val.getNode()))
1833 Opc = AtomicOpcTbl[Op][SextConstantI32];
1835 Opc = AtomicOpcTbl[Op][ConstantI32];
1837 Opc = AtomicOpcTbl[Op][I32];
1841 if (immSext8(Val.getNode()))
1842 Opc = AtomicOpcTbl[Op][SextConstantI64];
1843 else if (i64immSExt32(Val.getNode()))
1844 Opc = AtomicOpcTbl[Op][ConstantI64];
1846 llvm_unreachable("True 64 bits constant in SelectAtomicLoadArith");
1848 Opc = AtomicOpcTbl[Op][I64];
1852 assert(Opc != 0 && "Invalid arith lock transform!");
1854 // Building the new node.
1857 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Chain };
1858 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1860 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Val, Chain };
1861 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1864 // Copying the MachineMemOperand.
1865 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1866 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1867 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1869 // We need to have two outputs as that is what the original instruction had.
1870 // So we add a dummy, undefined output. This is safe as we checked first
1871 // that no-one uses our output anyway.
1872 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1874 SDValue RetVals[] = { Undef, Ret };
1875 return CurDAG->getMergeValues(RetVals, dl).getNode();
1878 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1879 /// any uses which require the SF or OF bits to be accurate.
1880 static bool HasNoSignedComparisonUses(SDNode *N) {
1881 // Examine each user of the node.
1882 for (SDNode::use_iterator UI = N->use_begin(),
1883 UE = N->use_end(); UI != UE; ++UI) {
1884 // Only examine CopyToReg uses.
1885 if (UI->getOpcode() != ISD::CopyToReg)
1887 // Only examine CopyToReg uses that copy to EFLAGS.
1888 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1891 // Examine each user of the CopyToReg use.
1892 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1893 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1894 // Only examine the Flag result.
1895 if (FlagUI.getUse().getResNo() != 1) continue;
1896 // Anything unusual: assume conservatively.
1897 if (!FlagUI->isMachineOpcode()) return false;
1898 // Examine the opcode of the user.
1899 switch (FlagUI->getMachineOpcode()) {
1900 // These comparisons don't treat the most significant bit specially.
1901 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1902 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1903 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1904 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1905 case X86::JA_1: case X86::JAE_1: case X86::JB_1: case X86::JBE_1:
1906 case X86::JE_1: case X86::JNE_1: case X86::JP_1: case X86::JNP_1:
1907 case X86::CMOVA16rr: case X86::CMOVA16rm:
1908 case X86::CMOVA32rr: case X86::CMOVA32rm:
1909 case X86::CMOVA64rr: case X86::CMOVA64rm:
1910 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1911 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1912 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1913 case X86::CMOVB16rr: case X86::CMOVB16rm:
1914 case X86::CMOVB32rr: case X86::CMOVB32rm:
1915 case X86::CMOVB64rr: case X86::CMOVB64rm:
1916 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1917 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1918 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1919 case X86::CMOVE16rr: case X86::CMOVE16rm:
1920 case X86::CMOVE32rr: case X86::CMOVE32rm:
1921 case X86::CMOVE64rr: case X86::CMOVE64rm:
1922 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1923 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1924 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1925 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1926 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1927 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1928 case X86::CMOVP16rr: case X86::CMOVP16rm:
1929 case X86::CMOVP32rr: case X86::CMOVP32rm:
1930 case X86::CMOVP64rr: case X86::CMOVP64rm:
1932 // Anything else: assume conservatively.
1933 default: return false;
1940 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1941 /// is suitable for doing the {load; increment or decrement; store} to modify
1943 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1944 SDValue StoredVal, SelectionDAG *CurDAG,
1945 LoadSDNode* &LoadNode, SDValue &InputChain) {
1947 // is the value stored the result of a DEC or INC?
1948 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1950 // is the stored value result 0 of the load?
1951 if (StoredVal.getResNo() != 0) return false;
1953 // are there other uses of the loaded value than the inc or dec?
1954 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1956 // is the store non-extending and non-indexed?
1957 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1960 SDValue Load = StoredVal->getOperand(0);
1961 // Is the stored value a non-extending and non-indexed load?
1962 if (!ISD::isNormalLoad(Load.getNode())) return false;
1964 // Return LoadNode by reference.
1965 LoadNode = cast<LoadSDNode>(Load);
1966 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
1967 EVT LdVT = LoadNode->getMemoryVT();
1968 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1972 // Is store the only read of the loaded value?
1973 if (!Load.hasOneUse())
1976 // Is the address of the store the same as the load?
1977 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1978 LoadNode->getOffset() != StoreNode->getOffset())
1981 // Check if the chain is produced by the load or is a TokenFactor with
1982 // the load output chain as an operand. Return InputChain by reference.
1983 SDValue Chain = StoreNode->getChain();
1985 bool ChainCheck = false;
1986 if (Chain == Load.getValue(1)) {
1988 InputChain = LoadNode->getChain();
1989 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1990 SmallVector<SDValue, 4> ChainOps;
1991 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
1992 SDValue Op = Chain.getOperand(i);
1993 if (Op == Load.getValue(1)) {
1998 // Make sure using Op as part of the chain would not cause a cycle here.
1999 // In theory, we could check whether the chain node is a predecessor of
2000 // the load. But that can be very expensive. Instead visit the uses and
2001 // make sure they all have smaller node id than the load.
2002 int LoadId = LoadNode->getNodeId();
2003 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
2004 UE = UI->use_end(); UI != UE; ++UI) {
2005 if (UI.getUse().getResNo() != 0)
2007 if (UI->getNodeId() > LoadId)
2011 ChainOps.push_back(Op);
2015 // Make a new TokenFactor with all the other input chains except
2017 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
2018 MVT::Other, ChainOps);
2026 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
2027 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
2028 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
2029 if (Opc == X86ISD::DEC) {
2030 if (LdVT == MVT::i64) return X86::DEC64m;
2031 if (LdVT == MVT::i32) return X86::DEC32m;
2032 if (LdVT == MVT::i16) return X86::DEC16m;
2033 if (LdVT == MVT::i8) return X86::DEC8m;
2035 assert(Opc == X86ISD::INC && "unrecognized opcode");
2036 if (LdVT == MVT::i64) return X86::INC64m;
2037 if (LdVT == MVT::i32) return X86::INC32m;
2038 if (LdVT == MVT::i16) return X86::INC16m;
2039 if (LdVT == MVT::i8) return X86::INC8m;
2041 llvm_unreachable("unrecognized size for LdVT");
2044 /// SelectGather - Customized ISel for GATHER operations.
2046 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
2047 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
2048 SDValue Chain = Node->getOperand(0);
2049 SDValue VSrc = Node->getOperand(2);
2050 SDValue Base = Node->getOperand(3);
2051 SDValue VIdx = Node->getOperand(4);
2052 SDValue VMask = Node->getOperand(5);
2053 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
2057 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
2062 // Memory Operands: Base, Scale, Index, Disp, Segment
2063 SDValue Disp = CurDAG->getTargetConstant(0, DL, MVT::i32);
2064 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
2065 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue(), DL), VIdx,
2066 Disp, Segment, VMask, Chain};
2067 SDNode *ResNode = CurDAG->getMachineNode(Opc, DL, VTs, Ops);
2068 // Node has 2 outputs: VDst and MVT::Other.
2069 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
2070 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
2072 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
2073 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
2077 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
2078 MVT NVT = Node->getSimpleValueType(0);
2080 unsigned Opcode = Node->getOpcode();
2083 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
2085 if (Node->isMachineOpcode()) {
2086 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
2087 Node->setNodeId(-1);
2088 return nullptr; // Already selected.
2093 case ISD::INTRINSIC_W_CHAIN: {
2094 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2097 case Intrinsic::x86_avx2_gather_d_pd:
2098 case Intrinsic::x86_avx2_gather_d_pd_256:
2099 case Intrinsic::x86_avx2_gather_q_pd:
2100 case Intrinsic::x86_avx2_gather_q_pd_256:
2101 case Intrinsic::x86_avx2_gather_d_ps:
2102 case Intrinsic::x86_avx2_gather_d_ps_256:
2103 case Intrinsic::x86_avx2_gather_q_ps:
2104 case Intrinsic::x86_avx2_gather_q_ps_256:
2105 case Intrinsic::x86_avx2_gather_d_q:
2106 case Intrinsic::x86_avx2_gather_d_q_256:
2107 case Intrinsic::x86_avx2_gather_q_q:
2108 case Intrinsic::x86_avx2_gather_q_q_256:
2109 case Intrinsic::x86_avx2_gather_d_d:
2110 case Intrinsic::x86_avx2_gather_d_d_256:
2111 case Intrinsic::x86_avx2_gather_q_d:
2112 case Intrinsic::x86_avx2_gather_q_d_256: {
2113 if (!Subtarget->hasAVX2())
2117 default: llvm_unreachable("Impossible intrinsic");
2118 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2119 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2120 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2121 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2122 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2123 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2124 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2125 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2126 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2127 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2128 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2129 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2130 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2131 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2132 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2133 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2135 SDNode *RetVal = SelectGather(Node, Opc);
2137 // We already called ReplaceUses inside SelectGather.
2144 case X86ISD::GlobalBaseReg:
2145 return getGlobalBaseReg();
2147 case X86ISD::SHRUNKBLEND: {
2148 // SHRUNKBLEND selects like a regular VSELECT.
2149 SDValue VSelect = CurDAG->getNode(
2150 ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0),
2151 Node->getOperand(1), Node->getOperand(2));
2152 ReplaceUses(SDValue(Node, 0), VSelect);
2153 SelectCode(VSelect.getNode());
2154 // We already called ReplaceUses.
2158 case ISD::ATOMIC_LOAD_XOR:
2159 case ISD::ATOMIC_LOAD_AND:
2160 case ISD::ATOMIC_LOAD_OR:
2161 case ISD::ATOMIC_LOAD_ADD: {
2162 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2170 // For operations of the form (x << C1) op C2, check if we can use a smaller
2171 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2172 SDValue N0 = Node->getOperand(0);
2173 SDValue N1 = Node->getOperand(1);
2175 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2178 // i8 is unshrinkable, i16 should be promoted to i32.
2179 if (NVT != MVT::i32 && NVT != MVT::i64)
2182 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2183 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2184 if (!Cst || !ShlCst)
2187 int64_t Val = Cst->getSExtValue();
2188 uint64_t ShlVal = ShlCst->getZExtValue();
2190 // Make sure that we don't change the operation by removing bits.
2191 // This only matters for OR and XOR, AND is unaffected.
2192 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2193 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2196 unsigned ShlOp, AddOp, Op;
2199 // Check the minimum bitwidth for the new constant.
2200 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2201 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2202 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2203 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2205 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2208 // Bail if there is no smaller encoding.
2212 switch (NVT.SimpleTy) {
2213 default: llvm_unreachable("Unsupported VT!");
2215 assert(CstVT == MVT::i8);
2216 ShlOp = X86::SHL32ri;
2217 AddOp = X86::ADD32rr;
2220 default: llvm_unreachable("Impossible opcode");
2221 case ISD::AND: Op = X86::AND32ri8; break;
2222 case ISD::OR: Op = X86::OR32ri8; break;
2223 case ISD::XOR: Op = X86::XOR32ri8; break;
2227 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2228 ShlOp = X86::SHL64ri;
2229 AddOp = X86::ADD64rr;
2232 default: llvm_unreachable("Impossible opcode");
2233 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2234 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2235 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2240 // Emit the smaller op and the shift.
2241 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, dl, CstVT);
2242 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2244 return CurDAG->SelectNodeTo(Node, AddOp, NVT, SDValue(New, 0),
2246 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2247 getI8Imm(ShlVal, dl));
2250 case X86ISD::SMUL8: {
2251 SDValue N0 = Node->getOperand(0);
2252 SDValue N1 = Node->getOperand(1);
2254 Opc = (Opcode == X86ISD::SMUL8 ? X86::IMUL8r : X86::MUL8r);
2256 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::AL,
2257 N0, SDValue()).getValue(1);
2259 SDVTList VTs = CurDAG->getVTList(NVT, MVT::i32);
2260 SDValue Ops[] = {N1, InFlag};
2261 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2263 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2264 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2268 case X86ISD::UMUL: {
2269 SDValue N0 = Node->getOperand(0);
2270 SDValue N1 = Node->getOperand(1);
2273 switch (NVT.SimpleTy) {
2274 default: llvm_unreachable("Unsupported VT!");
2275 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2276 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2277 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2278 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2281 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2282 N0, SDValue()).getValue(1);
2284 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2285 SDValue Ops[] = {N1, InFlag};
2286 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2288 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2289 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2290 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2294 case ISD::SMUL_LOHI:
2295 case ISD::UMUL_LOHI: {
2296 SDValue N0 = Node->getOperand(0);
2297 SDValue N1 = Node->getOperand(1);
2299 bool isSigned = Opcode == ISD::SMUL_LOHI;
2300 bool hasBMI2 = Subtarget->hasBMI2();
2302 switch (NVT.SimpleTy) {
2303 default: llvm_unreachable("Unsupported VT!");
2304 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2305 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2306 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2307 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2308 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2309 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2312 switch (NVT.SimpleTy) {
2313 default: llvm_unreachable("Unsupported VT!");
2314 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2315 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2316 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2317 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2321 unsigned SrcReg, LoReg, HiReg;
2323 default: llvm_unreachable("Unknown MUL opcode!");
2326 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2330 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2334 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2338 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2341 SrcReg = X86::EDX; LoReg = HiReg = 0;
2344 SrcReg = X86::RDX; LoReg = HiReg = 0;
2348 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2349 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2350 // Multiply is commmutative.
2352 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2357 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2358 N0, SDValue()).getValue(1);
2359 SDValue ResHi, ResLo;
2363 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2365 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2366 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2367 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2368 ResHi = SDValue(CNode, 0);
2369 ResLo = SDValue(CNode, 1);
2370 Chain = SDValue(CNode, 2);
2371 InFlag = SDValue(CNode, 3);
2373 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2374 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2375 Chain = SDValue(CNode, 0);
2376 InFlag = SDValue(CNode, 1);
2379 // Update the chain.
2380 ReplaceUses(N1.getValue(1), Chain);
2382 SDValue Ops[] = { N1, InFlag };
2383 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2384 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2385 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2386 ResHi = SDValue(CNode, 0);
2387 ResLo = SDValue(CNode, 1);
2388 InFlag = SDValue(CNode, 2);
2390 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2391 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2392 InFlag = SDValue(CNode, 0);
2396 // Prevent use of AH in a REX instruction by referencing AX instead.
2397 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2398 !SDValue(Node, 1).use_empty()) {
2399 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2400 X86::AX, MVT::i16, InFlag);
2401 InFlag = Result.getValue(2);
2402 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2404 if (!SDValue(Node, 0).use_empty())
2405 ReplaceUses(SDValue(Node, 1),
2406 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2408 // Shift AX down 8 bits.
2409 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2411 CurDAG->getTargetConstant(8, dl, MVT::i8)),
2413 // Then truncate it down to i8.
2414 ReplaceUses(SDValue(Node, 1),
2415 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2417 // Copy the low half of the result, if it is needed.
2418 if (!SDValue(Node, 0).use_empty()) {
2419 if (!ResLo.getNode()) {
2420 assert(LoReg && "Register for low half is not defined!");
2421 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2423 InFlag = ResLo.getValue(2);
2425 ReplaceUses(SDValue(Node, 0), ResLo);
2426 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2428 // Copy the high half of the result, if it is needed.
2429 if (!SDValue(Node, 1).use_empty()) {
2430 if (!ResHi.getNode()) {
2431 assert(HiReg && "Register for high half is not defined!");
2432 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2434 InFlag = ResHi.getValue(2);
2436 ReplaceUses(SDValue(Node, 1), ResHi);
2437 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2445 case X86ISD::SDIVREM8_SEXT_HREG:
2446 case X86ISD::UDIVREM8_ZEXT_HREG: {
2447 SDValue N0 = Node->getOperand(0);
2448 SDValue N1 = Node->getOperand(1);
2450 bool isSigned = (Opcode == ISD::SDIVREM ||
2451 Opcode == X86ISD::SDIVREM8_SEXT_HREG);
2453 switch (NVT.SimpleTy) {
2454 default: llvm_unreachable("Unsupported VT!");
2455 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2456 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2457 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2458 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2461 switch (NVT.SimpleTy) {
2462 default: llvm_unreachable("Unsupported VT!");
2463 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2464 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2465 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2466 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2470 unsigned LoReg, HiReg, ClrReg;
2471 unsigned SExtOpcode;
2472 switch (NVT.SimpleTy) {
2473 default: llvm_unreachable("Unsupported VT!");
2475 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2476 SExtOpcode = X86::CBW;
2479 LoReg = X86::AX; HiReg = X86::DX;
2481 SExtOpcode = X86::CWD;
2484 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2485 SExtOpcode = X86::CDQ;
2488 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2489 SExtOpcode = X86::CQO;
2493 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2494 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2495 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2498 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2499 // Special case for div8, just use a move with zero extension to AX to
2500 // clear the upper 8 bits (AH).
2501 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2502 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2503 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2505 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2506 MVT::Other, Ops), 0);
2507 Chain = Move.getValue(1);
2508 ReplaceUses(N0.getValue(1), Chain);
2511 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2512 Chain = CurDAG->getEntryNode();
2514 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2515 InFlag = Chain.getValue(1);
2518 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2519 LoReg, N0, SDValue()).getValue(1);
2520 if (isSigned && !signBitIsZero) {
2521 // Sign extend the low part into the high part.
2523 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2525 // Zero out the high part, effectively zero extending the input.
2526 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
2527 switch (NVT.SimpleTy) {
2530 SDValue(CurDAG->getMachineNode(
2531 TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
2532 CurDAG->getTargetConstant(X86::sub_16bit, dl,
2540 SDValue(CurDAG->getMachineNode(
2541 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2542 CurDAG->getTargetConstant(0, dl, MVT::i64), ClrNode,
2543 CurDAG->getTargetConstant(X86::sub_32bit, dl,
2548 llvm_unreachable("Unexpected division source");
2551 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2552 ClrNode, InFlag).getValue(1);
2557 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2560 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops);
2561 InFlag = SDValue(CNode, 1);
2562 // Update the chain.
2563 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2566 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2569 // Prevent use of AH in a REX instruction by explicitly copying it to
2570 // an ABCD_L register.
2572 // The current assumption of the register allocator is that isel
2573 // won't generate explicit references to the GR8_ABCD_H registers. If
2574 // the allocator and/or the backend get enhanced to be more robust in
2575 // that regard, this can be, and should be, removed.
2576 if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) {
2577 SDValue AHCopy = CurDAG->getRegister(X86::AH, MVT::i8);
2578 unsigned AHExtOpcode =
2579 isSigned ? X86::MOVSX32_NOREXrr8 : X86::MOVZX32_NOREXrr8;
2581 SDNode *RNode = CurDAG->getMachineNode(AHExtOpcode, dl, MVT::i32,
2582 MVT::Glue, AHCopy, InFlag);
2583 SDValue Result(RNode, 0);
2584 InFlag = SDValue(RNode, 1);
2586 if (Opcode == X86ISD::UDIVREM8_ZEXT_HREG ||
2587 Opcode == X86ISD::SDIVREM8_SEXT_HREG) {
2588 if (Node->getValueType(1) == MVT::i64) {
2589 // It's not possible to directly movsx AH to a 64bit register, because
2590 // the latter needs the REX prefix, but the former can't have it.
2591 assert(Opcode != X86ISD::SDIVREM8_SEXT_HREG &&
2592 "Unexpected i64 sext of h-register");
2594 SDValue(CurDAG->getMachineNode(
2595 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2596 CurDAG->getTargetConstant(0, dl, MVT::i64), Result,
2597 CurDAG->getTargetConstant(X86::sub_32bit, dl,
2603 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result);
2605 ReplaceUses(SDValue(Node, 1), Result);
2606 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2608 // Copy the division (low) result, if it is needed.
2609 if (!SDValue(Node, 0).use_empty()) {
2610 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2611 LoReg, NVT, InFlag);
2612 InFlag = Result.getValue(2);
2613 ReplaceUses(SDValue(Node, 0), Result);
2614 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2616 // Copy the remainder (high) result, if it is needed.
2617 if (!SDValue(Node, 1).use_empty()) {
2618 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2619 HiReg, NVT, InFlag);
2620 InFlag = Result.getValue(2);
2621 ReplaceUses(SDValue(Node, 1), Result);
2622 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2629 // Sometimes a SUB is used to perform comparison.
2630 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2631 // This node is not a CMP.
2633 SDValue N0 = Node->getOperand(0);
2634 SDValue N1 = Node->getOperand(1);
2636 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2637 HasNoSignedComparisonUses(Node))
2638 N0 = N0.getOperand(0);
2640 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2641 // use a smaller encoding.
2642 // Look past the truncate if CMP is the only use of it.
2643 if ((N0.getNode()->getOpcode() == ISD::AND ||
2644 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2645 N0.getNode()->hasOneUse() &&
2646 N0.getValueType() != MVT::i8 &&
2647 X86::isZeroNode(N1)) {
2648 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2651 // For example, convert "testl %eax, $8" to "testb %al, $8"
2652 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2653 (!(C->getZExtValue() & 0x80) ||
2654 HasNoSignedComparisonUses(Node))) {
2655 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl, MVT::i8);
2656 SDValue Reg = N0.getNode()->getOperand(0);
2658 // On x86-32, only the ABCD registers have 8-bit subregisters.
2659 if (!Subtarget->is64Bit()) {
2660 const TargetRegisterClass *TRC;
2661 switch (N0.getSimpleValueType().SimpleTy) {
2662 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2663 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2664 default: llvm_unreachable("Unsupported TEST operand type!");
2666 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
2667 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2668 Reg.getValueType(), Reg, RC), 0);
2671 // Extract the l-register.
2672 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2676 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2678 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2679 // one, do not call ReplaceAllUsesWith.
2680 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2681 SDValue(NewNode, 0));
2685 // For example, "testl %eax, $2048" to "testb %ah, $8".
2686 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2687 (!(C->getZExtValue() & 0x8000) ||
2688 HasNoSignedComparisonUses(Node))) {
2689 // Shift the immediate right by 8 bits.
2690 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2692 SDValue Reg = N0.getNode()->getOperand(0);
2694 // Put the value in an ABCD register.
2695 const TargetRegisterClass *TRC;
2696 switch (N0.getSimpleValueType().SimpleTy) {
2697 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2698 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2699 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2700 default: llvm_unreachable("Unsupported TEST operand type!");
2702 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
2703 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2704 Reg.getValueType(), Reg, RC), 0);
2706 // Extract the h-register.
2707 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2710 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2711 // target GR8_NOREX registers, so make sure the register class is
2713 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2714 MVT::i32, Subreg, ShiftedImm);
2715 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2716 // one, do not call ReplaceAllUsesWith.
2717 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2718 SDValue(NewNode, 0));
2722 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2723 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2724 N0.getValueType() != MVT::i16 &&
2725 (!(C->getZExtValue() & 0x8000) ||
2726 HasNoSignedComparisonUses(Node))) {
2727 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
2729 SDValue Reg = N0.getNode()->getOperand(0);
2731 // Extract the 16-bit subregister.
2732 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2736 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2738 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2739 // one, do not call ReplaceAllUsesWith.
2740 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2741 SDValue(NewNode, 0));
2745 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2746 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2747 N0.getValueType() == MVT::i64 &&
2748 (!(C->getZExtValue() & 0x80000000) ||
2749 HasNoSignedComparisonUses(Node))) {
2750 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
2752 SDValue Reg = N0.getNode()->getOperand(0);
2754 // Extract the 32-bit subregister.
2755 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2759 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2761 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2762 // one, do not call ReplaceAllUsesWith.
2763 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2764 SDValue(NewNode, 0));
2771 // Change a chain of {load; incr or dec; store} of the same value into
2772 // a simple increment or decrement through memory of that value, if the
2773 // uses of the modified value and its address are suitable.
2774 // The DEC64m tablegen pattern is currently not able to match the case where
2775 // the EFLAGS on the original DEC are used. (This also applies to
2776 // {INC,DEC}X{64,32,16,8}.)
2777 // We'll need to improve tablegen to allow flags to be transferred from a
2778 // node in the pattern to the result node. probably with a new keyword
2779 // for example, we have this
2780 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2781 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2782 // (implicit EFLAGS)]>;
2783 // but maybe need something like this
2784 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2785 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2786 // (transferrable EFLAGS)]>;
2788 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2789 SDValue StoredVal = StoreNode->getOperand(1);
2790 unsigned Opc = StoredVal->getOpcode();
2792 LoadSDNode *LoadNode = nullptr;
2794 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2795 LoadNode, InputChain))
2798 SDValue Base, Scale, Index, Disp, Segment;
2799 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2800 Base, Scale, Index, Disp, Segment))
2803 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2804 MemOp[0] = StoreNode->getMemOperand();
2805 MemOp[1] = LoadNode->getMemOperand();
2806 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2807 EVT LdVT = LoadNode->getMemoryVT();
2808 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2809 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2811 MVT::i32, MVT::Other, Ops);
2812 Result->setMemRefs(MemOp, MemOp + 2);
2814 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2815 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2821 SDNode *ResNode = SelectCode(Node);
2823 DEBUG(dbgs() << "=> ";
2824 if (ResNode == nullptr || ResNode == Node)
2827 ResNode->dump(CurDAG);
2833 bool X86DAGToDAGISel::
2834 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
2835 std::vector<SDValue> &OutOps) {
2836 SDValue Op0, Op1, Op2, Op3, Op4;
2837 switch (ConstraintID) {
2838 case InlineAsm::Constraint_o: // offsetable ??
2839 case InlineAsm::Constraint_v: // not offsetable ??
2840 default: return true;
2841 case InlineAsm::Constraint_m: // memory
2842 if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
2847 OutOps.push_back(Op0);
2848 OutOps.push_back(Op1);
2849 OutOps.push_back(Op2);
2850 OutOps.push_back(Op3);
2851 OutOps.push_back(Op4);
2855 /// createX86ISelDag - This pass converts a legalized DAG into a
2856 /// X86-specific DAG, ready for instruction scheduling.
2858 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2859 CodeGenOpt::Level OptLevel) {
2860 return new X86DAGToDAGISel(TM, OptLevel);