1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Debug.h"
36 // FIXME: completely move here.
37 extern cl::opt<bool> ForceStackAlign;
39 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
40 return !MF.getFrameInfo()->hasVarSizedObjects();
43 /// hasFP - Return true if the specified function should have a dedicated frame
44 /// pointer register. This is true if the function has variable sized allocas
45 /// or if frame pointer elimination is disabled.
46 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
47 const MachineFrameInfo *MFI = MF.getFrameInfo();
48 const MachineModuleInfo &MMI = MF.getMMI();
49 const TargetRegisterInfo *RegInfo =
50 MF.getTarget().getSubtargetImpl()->getRegisterInfo();
52 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
53 RegInfo->needsStackRealignment(MF) ||
54 MFI->hasVarSizedObjects() ||
55 MFI->isFrameAddressTaken() || MFI->hasInlineAsmWithSPAdjust() ||
56 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
57 MMI.callsUnwindInit() || MMI.callsEHReturn());
60 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
64 return X86::SUB64ri32;
72 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
76 return X86::ADD64ri32;
84 static unsigned getLEArOpcode(unsigned IsLP64) {
85 return IsLP64 ? X86::LEA64r : X86::LEA32r;
88 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
89 /// when it reaches the "return" instruction. We can then pop a stack object
90 /// to this register without worry about clobbering it.
91 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator &MBBI,
93 const TargetRegisterInfo &TRI,
95 const MachineFunction *MF = MBB.getParent();
96 const Function *F = MF->getFunction();
97 if (!F || MF->getMMI().callsEHReturn())
100 static const uint16_t CallerSavedRegs32Bit[] = {
101 X86::EAX, X86::EDX, X86::ECX, 0
104 static const uint16_t CallerSavedRegs64Bit[] = {
105 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
106 X86::R8, X86::R9, X86::R10, X86::R11, 0
109 unsigned Opc = MBBI->getOpcode();
116 case X86::TCRETURNdi:
117 case X86::TCRETURNri:
118 case X86::TCRETURNmi:
119 case X86::TCRETURNdi64:
120 case X86::TCRETURNri64:
121 case X86::TCRETURNmi64:
123 case X86::EH_RETURN64: {
124 SmallSet<uint16_t, 8> Uses;
125 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
126 MachineOperand &MO = MBBI->getOperand(i);
127 if (!MO.isReg() || MO.isDef())
129 unsigned Reg = MO.getReg();
132 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
136 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
138 if (!Uses.count(*CS))
147 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
148 /// stack pointer by a constant value.
150 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
151 unsigned StackPtr, int64_t NumBytes,
152 bool Is64Bit, bool IsLP64, bool UseLEA,
153 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
154 bool isSub = NumBytes < 0;
155 uint64_t Offset = isSub ? -NumBytes : NumBytes;
158 Opc = getLEArOpcode(IsLP64);
161 ? getSUBriOpcode(IsLP64, Offset)
162 : getADDriOpcode(IsLP64, Offset);
164 uint64_t Chunk = (1LL << 31) - 1;
165 DebugLoc DL = MBB.findDebugLoc(MBBI);
168 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
169 if (ThisVal == (Is64Bit ? 8 : 4)) {
170 // Use push / pop instead.
172 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
173 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
176 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
177 : (Is64Bit ? X86::POP64r : X86::POP32r);
178 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
179 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
181 MI->setFlag(MachineInstr::FrameSetup);
187 MachineInstr *MI = nullptr;
190 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
191 StackPtr, false, isSub ? -ThisVal : ThisVal);
193 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
196 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
200 MI->setFlag(MachineInstr::FrameSetup);
206 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
208 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
209 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
210 if (MBBI == MBB.begin()) return;
212 MachineBasicBlock::iterator PI = std::prev(MBBI);
213 unsigned Opc = PI->getOpcode();
214 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
215 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
216 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
217 PI->getOperand(0).getReg() == StackPtr) {
219 *NumBytes += PI->getOperand(2).getImm();
221 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
222 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
223 PI->getOperand(0).getReg() == StackPtr) {
225 *NumBytes -= PI->getOperand(2).getImm();
230 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower
233 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
234 MachineBasicBlock::iterator &MBBI,
235 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
236 // FIXME: THIS ISN'T RUN!!!
239 if (MBBI == MBB.end()) return;
241 MachineBasicBlock::iterator NI = std::next(MBBI);
242 if (NI == MBB.end()) return;
244 unsigned Opc = NI->getOpcode();
245 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
246 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
247 NI->getOperand(0).getReg() == StackPtr) {
249 *NumBytes -= NI->getOperand(2).getImm();
252 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
253 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
254 NI->getOperand(0).getReg() == StackPtr) {
256 *NumBytes += NI->getOperand(2).getImm();
262 /// mergeSPUpdates - Checks the instruction before/after the passed
263 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and
264 /// the stack adjustment is returned as a positive value for ADD/LEA and a
265 /// negative for SUB.
266 static int mergeSPUpdates(MachineBasicBlock &MBB,
267 MachineBasicBlock::iterator &MBBI, unsigned StackPtr,
268 bool doMergeWithPrevious) {
269 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
270 (!doMergeWithPrevious && MBBI == MBB.end()))
273 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
274 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
276 unsigned Opc = PI->getOpcode();
279 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
280 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
281 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
282 PI->getOperand(0).getReg() == StackPtr){
283 Offset += PI->getOperand(2).getImm();
285 if (!doMergeWithPrevious) MBBI = NI;
286 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
287 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
288 PI->getOperand(0).getReg() == StackPtr) {
289 Offset -= PI->getOperand(2).getImm();
291 if (!doMergeWithPrevious) MBBI = NI;
297 static bool isEAXLiveIn(MachineFunction &MF) {
298 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
299 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
300 unsigned Reg = II->first;
302 if (Reg == X86::EAX || Reg == X86::AX ||
303 Reg == X86::AH || Reg == X86::AL)
311 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
312 MachineBasicBlock::iterator MBBI,
314 MachineFunction &MF = *MBB.getParent();
315 MachineFrameInfo *MFI = MF.getFrameInfo();
316 MachineModuleInfo &MMI = MF.getMMI();
317 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
318 const TargetInstrInfo &TII =
319 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
321 // Add callee saved registers to move list.
322 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
323 if (CSI.empty()) return;
325 // Calculate offsets.
326 for (std::vector<CalleeSavedInfo>::const_iterator
327 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
328 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
329 unsigned Reg = I->getReg();
331 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
333 MMI.addFrameInst(MCCFIInstruction::createOffset(nullptr, DwarfReg,
335 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
336 .addCFIIndex(CFIIndex);
340 /// usesTheStack - This function checks if any of the users of EFLAGS
341 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
342 /// to use the stack, and if we don't adjust the stack we clobber the first
344 /// See X86InstrInfo::copyPhysReg.
345 static bool usesTheStack(const MachineFunction &MF) {
346 const MachineRegisterInfo &MRI = MF.getRegInfo();
348 for (MachineRegisterInfo::reg_instr_iterator
349 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
357 /// emitPrologue - Push callee-saved registers onto the stack, which
358 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
359 /// space for local variables. Also emit labels used by the exception handler to
360 /// generate the exception handling frames.
363 Here's a gist of what gets emitted:
365 ; Establish frame pointer, if needed
368 .cfi_def_cfa_offset 16
369 .cfi_offset %rbp, -16
372 .cfi_def_cfa_register %rbp
374 ; Spill general-purpose registers
375 [for all callee-saved GPRs]
378 .cfi_def_cfa_offset (offset from RETADDR)
381 ; If the required stack alignment > default stack alignment
382 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
383 ; of unknown size in the stack frame.
384 [if stack needs re-alignment]
387 ; Allocate space for locals
388 [if target is Windows and allocated space > 4096 bytes]
389 ; Windows needs special care for allocations larger
392 call ___chkstk_ms/___chkstk
398 .seh_stackalloc (size of XMM spill slots)
399 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
404 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
405 ; they may get spilled on any platform, if the current function
406 ; calls @llvm.eh.unwind.init
408 [for all callee-saved XMM registers]
409 movaps %<xmm reg>, -MMM(%rbp)
410 [for all callee-saved XMM registers]
411 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
412 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
414 [for all callee-saved XMM registers]
415 movaps %<xmm reg>, KKK(%rsp)
416 [for all callee-saved XMM registers]
417 .seh_savexmm %<xmm reg>, KKK
421 [if needs base pointer]
426 [for all callee-saved registers]
427 .cfi_offset %<reg>, (offset from %rbp)
429 .cfi_def_cfa_offset (offset from RETADDR)
430 [for all callee-saved registers]
431 .cfi_offset %<reg>, (offset from %rsp)
434 - .seh directives are emitted only for Windows 64 ABI
435 - .cfi directives are emitted for all other ABIs
436 - for 32-bit code, substitute %e?? registers for %r??
439 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
440 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
441 MachineBasicBlock::iterator MBBI = MBB.begin();
442 MachineFrameInfo *MFI = MF.getFrameInfo();
443 const Function *Fn = MF.getFunction();
444 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
445 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
446 const TargetInstrInfo &TII =
447 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
448 MachineModuleInfo &MMI = MF.getMMI();
449 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
450 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
451 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
452 bool HasFP = hasFP(MF);
453 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
454 bool Is64Bit = STI.is64Bit();
455 bool IsLP64 = STI.isTarget64BitLP64();
456 bool IsWin64 = STI.isTargetWin64();
458 MF.getTarget().getMCAsmInfo()->getExceptionHandlingType() ==
459 ExceptionHandling::WinEH; // Not necessarily synonymous with IsWin64.
460 bool NeedsWinEH = IsWinEH && Fn->needsUnwindTableEntry();
462 !IsWinEH && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
463 bool UseLEA = STI.useLeaForSP();
464 unsigned StackAlign = getStackAlignment();
465 unsigned SlotSize = RegInfo->getSlotSize();
466 unsigned FramePtr = RegInfo->getFrameRegister(MF);
467 unsigned StackPtr = RegInfo->getStackRegister();
468 unsigned BasePtr = RegInfo->getBaseRegister();
471 // If we're forcing a stack realignment we can't rely on just the frame
472 // info, we need to know the ABI stack alignment as well in case we
473 // have a call out. Otherwise just make sure we have some alignment - we'll
474 // go with the minimum SlotSize.
475 if (ForceStackAlign) {
477 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
478 else if (MaxAlign < SlotSize)
482 // Add RETADDR move area to callee saved frame size.
483 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
484 if (TailCallReturnAddrDelta < 0)
485 X86FI->setCalleeSavedFrameSize(
486 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
488 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
489 // function, and use up to 128 bytes of stack space, don't have a frame
490 // pointer, calls, or dynamic alloca then we do not need to adjust the
491 // stack pointer (we fit in the Red Zone). We also check that we don't
492 // push and pop from the stack.
493 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
494 Attribute::NoRedZone) &&
495 !RegInfo->needsStackRealignment(MF) &&
496 !MFI->hasVarSizedObjects() && // No dynamic alloca.
497 !MFI->adjustsStack() && // No calls.
498 !IsWin64 && // Win64 has no Red Zone
499 !usesTheStack(MF) && // Don't push and pop.
500 !MF.shouldSplitStack()) { // Regular stack
501 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
502 if (HasFP) MinSize += SlotSize;
503 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
504 MFI->setStackSize(StackSize);
507 // Insert stack pointer adjustment for later moving of return addr. Only
508 // applies to tail call optimized functions where the callee argument stack
509 // size is bigger than the callers.
510 if (TailCallReturnAddrDelta < 0) {
512 BuildMI(MBB, MBBI, DL,
513 TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)),
516 .addImm(-TailCallReturnAddrDelta)
517 .setMIFlag(MachineInstr::FrameSetup);
518 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
521 // Mapping for machine moves:
523 // DST: VirtualFP AND
524 // SRC: VirtualFP => DW_CFA_def_cfa_offset
525 // ELSE => DW_CFA_def_cfa
527 // SRC: VirtualFP AND
528 // DST: Register => DW_CFA_def_cfa_register
531 // OFFSET < 0 => DW_CFA_offset_extended_sf
532 // REG < 64 => DW_CFA_offset + Reg
533 // ELSE => DW_CFA_offset_extended
535 uint64_t NumBytes = 0;
536 int stackGrowth = -SlotSize;
539 // Calculate required stack adjustment.
540 uint64_t FrameSize = StackSize - SlotSize;
541 if (RegInfo->needsStackRealignment(MF)) {
542 // Callee-saved registers are pushed on stack before the stack
544 FrameSize -= X86FI->getCalleeSavedFrameSize();
545 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
547 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
550 // Get the offset of the stack slot for the EBP register, which is
551 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
552 // Update the frame offset adjustment.
553 MFI->setOffsetAdjustment(-NumBytes);
555 // Save EBP/RBP into the appropriate stack slot.
556 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
557 .addReg(FramePtr, RegState::Kill)
558 .setMIFlag(MachineInstr::FrameSetup);
561 // Mark the place where EBP/RBP was saved.
562 // Define the current CFA rule to use the provided offset.
564 unsigned CFIIndex = MMI.addFrameInst(
565 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
566 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
567 .addCFIIndex(CFIIndex);
569 // Change the rule for the FramePtr to be an "offset" rule.
570 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(FramePtr, true);
571 CFIIndex = MMI.addFrameInst(
572 MCCFIInstruction::createOffset(nullptr,
573 DwarfFramePtr, 2 * stackGrowth));
574 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
575 .addCFIIndex(CFIIndex);
579 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
581 .setMIFlag(MachineInstr::FrameSetup);
584 // Update EBP with the new base value.
585 BuildMI(MBB, MBBI, DL,
586 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
588 .setMIFlag(MachineInstr::FrameSetup);
591 // Mark effective beginning of when frame pointer becomes valid.
592 // Define the current CFA to use the EBP/RBP register.
593 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(FramePtr, true);
594 unsigned CFIIndex = MMI.addFrameInst(
595 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
596 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
597 .addCFIIndex(CFIIndex);
600 // Mark the FramePtr as live-in in every block.
601 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
602 I->addLiveIn(FramePtr);
604 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
607 // Skip the callee-saved push instructions.
608 bool PushedRegs = false;
609 int StackOffset = 2 * stackGrowth;
611 while (MBBI != MBB.end() &&
612 (MBBI->getOpcode() == X86::PUSH32r ||
613 MBBI->getOpcode() == X86::PUSH64r)) {
615 unsigned Reg = MBBI->getOperand(0).getReg();
618 if (!HasFP && NeedsDwarfCFI) {
619 // Mark callee-saved push instruction.
620 // Define the current CFA rule to use the provided offset.
622 unsigned CFIIndex = MMI.addFrameInst(
623 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
624 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
625 .addCFIIndex(CFIIndex);
626 StackOffset += stackGrowth;
630 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
631 MachineInstr::FrameSetup);
635 // Realign stack after we pushed callee-saved registers (so that we'll be
636 // able to calculate their offsets from the frame pointer).
637 if (RegInfo->needsStackRealignment(MF)) {
638 assert(HasFP && "There should be a frame pointer if stack is realigned.");
640 BuildMI(MBB, MBBI, DL,
641 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
644 .setMIFlag(MachineInstr::FrameSetup);
646 // The EFLAGS implicit def is dead.
647 MI->getOperand(3).setIsDead();
650 // If there is an SUB32ri of ESP immediately before this instruction, merge
651 // the two. This can be the case when tail call elimination is enabled and
652 // the callee has more arguments then the caller.
653 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
655 // If there is an ADD32ri or SUB32ri of ESP immediately after this
656 // instruction, merge the two instructions.
657 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
659 // Adjust stack pointer: ESP -= numbytes.
661 // Windows and cygwin/mingw require a prologue helper routine when allocating
662 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
663 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
664 // stack and adjust the stack pointer in one go. The 64-bit version of
665 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
666 // responsible for adjusting the stack pointer. Touching the stack at 4K
667 // increments is necessary to ensure that the guard pages used by the OS
668 // virtual memory manager are allocated in correct sequence.
669 if (NumBytes >= 4096 && STI.isOSWindows() && !STI.isTargetMacho()) {
670 const char *StackProbeSymbol;
673 if (STI.isTargetCygMing()) {
674 StackProbeSymbol = "___chkstk_ms";
676 StackProbeSymbol = "__chkstk";
678 } else if (STI.isTargetCygMing())
679 StackProbeSymbol = "_alloca";
681 StackProbeSymbol = "_chkstk";
683 // Check whether EAX is livein for this function.
684 bool isEAXAlive = isEAXLiveIn(MF);
687 // Sanity check that EAX is not livein for this function.
688 // It should not be, so throw an assert.
689 assert(!Is64Bit && "EAX is livein in x64 case!");
692 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
693 .addReg(X86::EAX, RegState::Kill)
694 .setMIFlag(MachineInstr::FrameSetup);
698 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
699 // Function prologue is responsible for adjusting the stack pointer.
700 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
702 .setMIFlag(MachineInstr::FrameSetup);
704 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
705 // We'll also use 4 already allocated bytes for EAX.
706 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
707 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
708 .setMIFlag(MachineInstr::FrameSetup);
711 BuildMI(MBB, MBBI, DL,
712 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
713 .addExternalSymbol(StackProbeSymbol)
714 .addReg(StackPtr, RegState::Define | RegState::Implicit)
715 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
716 .setMIFlag(MachineInstr::FrameSetup);
719 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
720 // themself. It also does not clobber %rax so we can reuse it when
722 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), StackPtr)
725 .setMIFlag(MachineInstr::FrameSetup);
729 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
731 StackPtr, false, NumBytes - 4);
732 MI->setFlag(MachineInstr::FrameSetup);
733 MBB.insert(MBBI, MI);
735 } else if (NumBytes) {
736 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
737 UseLEA, TII, *RegInfo);
740 int SEHFrameOffset = 0;
743 // We need to set frame base offset low enough such that all saved
744 // register offsets would be positive relative to it, but we can't
745 // just use NumBytes, because .seh_setframe offset must be <=240.
746 // So we pretend to have only allocated enough space to spill the
747 // non-volatile registers.
748 // We don't care about the rest of stack allocation, because unwinder
749 // will restore SP to (BP - SEHFrameOffset)
750 for (const CalleeSavedInfo &Info : MFI->getCalleeSavedInfo()) {
751 int offset = MFI->getObjectOffset(Info.getFrameIdx());
752 SEHFrameOffset = std::max(SEHFrameOffset, abs(offset));
754 SEHFrameOffset += SEHFrameOffset % 16; // ensure alignmant
756 // This only needs to account for XMM spill slots, GPR slots
757 // are covered by the .seh_pushreg's emitted above.
758 unsigned Size = SEHFrameOffset - X86FI->getCalleeSavedFrameSize();
760 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
762 .setMIFlag(MachineInstr::FrameSetup);
765 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
767 .addImm(SEHFrameOffset)
768 .setMIFlag(MachineInstr::FrameSetup);
770 // SP will be the base register for restoring XMMs
772 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
774 .setMIFlag(MachineInstr::FrameSetup);
779 // Skip the rest of register spilling code
780 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
783 // Emit SEH info for non-GPRs
785 for (const CalleeSavedInfo &Info : MFI->getCalleeSavedInfo()) {
786 unsigned Reg = Info.getReg();
787 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
789 assert(X86::FR64RegClass.contains(Reg) && "Unexpected register class");
791 int Offset = getFrameIndexOffset(MF, Info.getFrameIdx());
792 Offset += SEHFrameOffset;
794 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
797 .setMIFlag(MachineInstr::FrameSetup);
800 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
801 .setMIFlag(MachineInstr::FrameSetup);
804 // If we need a base pointer, set it up here. It's whatever the value
805 // of the stack pointer is at this point. Any variable size objects
806 // will be allocated after this, so we can still use the base pointer
807 // to reference locals.
808 if (RegInfo->hasBasePointer(MF)) {
809 // Update the base pointer with the current stack pointer.
810 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
811 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
813 .setMIFlag(MachineInstr::FrameSetup);
816 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
817 // Mark end of stack pointer adjustment.
818 if (!HasFP && NumBytes) {
819 // Define the current CFA rule to use the provided offset.
821 unsigned CFIIndex = MMI.addFrameInst(
822 MCCFIInstruction::createDefCfaOffset(nullptr,
823 -StackSize + stackGrowth));
825 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
826 .addCFIIndex(CFIIndex);
829 // Emit DWARF info specifying the offsets of the callee-saved registers.
831 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
835 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
836 MachineBasicBlock &MBB) const {
837 const MachineFrameInfo *MFI = MF.getFrameInfo();
838 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
839 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
840 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
841 const TargetInstrInfo &TII =
842 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
843 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
844 assert(MBBI != MBB.end() && "Returning block has no instructions");
845 unsigned RetOpcode = MBBI->getOpcode();
846 DebugLoc DL = MBBI->getDebugLoc();
847 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
848 bool Is64Bit = STI.is64Bit();
849 bool IsLP64 = STI.isTarget64BitLP64();
850 bool UseLEA = STI.useLeaForSP();
851 unsigned StackAlign = getStackAlignment();
852 unsigned SlotSize = RegInfo->getSlotSize();
853 unsigned FramePtr = RegInfo->getFrameRegister(MF);
854 unsigned StackPtr = RegInfo->getStackRegister();
857 MF.getTarget().getMCAsmInfo()->getExceptionHandlingType() ==
858 ExceptionHandling::WinEH;
859 bool NeedsWinEH = IsWinEH && MF.getFunction()->needsUnwindTableEntry();
863 llvm_unreachable("Can only insert epilog into returning blocks");
868 case X86::TCRETURNdi:
869 case X86::TCRETURNri:
870 case X86::TCRETURNmi:
871 case X86::TCRETURNdi64:
872 case X86::TCRETURNri64:
873 case X86::TCRETURNmi64:
875 case X86::EH_RETURN64:
876 break; // These are ok
879 // Get the number of bytes to allocate from the FrameInfo.
880 uint64_t StackSize = MFI->getStackSize();
881 uint64_t MaxAlign = MFI->getMaxAlignment();
882 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
883 uint64_t NumBytes = 0;
885 // If we're forcing a stack realignment we can't rely on just the frame
886 // info, we need to know the ABI stack alignment as well in case we
887 // have a call out. Otherwise just make sure we have some alignment - we'll
888 // go with the minimum.
889 if (ForceStackAlign) {
891 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
893 MaxAlign = MaxAlign ? MaxAlign : 4;
897 // Calculate required stack adjustment.
898 uint64_t FrameSize = StackSize - SlotSize;
899 if (RegInfo->needsStackRealignment(MF)) {
900 // Callee-saved registers were pushed on stack before the stack
903 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
905 NumBytes = FrameSize - CSSize;
909 BuildMI(MBB, MBBI, DL,
910 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
912 NumBytes = StackSize - CSSize;
915 // Skip the callee-saved pop instructions.
916 while (MBBI != MBB.begin()) {
917 MachineBasicBlock::iterator PI = std::prev(MBBI);
918 unsigned Opc = PI->getOpcode();
920 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
926 MachineBasicBlock::iterator FirstCSPop = MBBI;
928 DL = MBBI->getDebugLoc();
930 // If there is an ADD32ri or SUB32ri of ESP immediately before this
931 // instruction, merge the two instructions.
932 if (NumBytes || MFI->hasVarSizedObjects())
933 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
935 // If dynamic alloca is used, then reset esp to point to the last callee-saved
936 // slot before popping them off! Same applies for the case, when stack was
938 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
939 if (RegInfo->needsStackRealignment(MF))
942 unsigned Opc = getLEArOpcode(IsLP64);
943 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
944 FramePtr, false, -CSSize);
947 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
948 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
952 } else if (NumBytes) {
953 // Adjust stack pointer back: ESP += numbytes.
954 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, IsLP64, UseLEA,
959 // Windows unwinder will not invoke function's exception handler if IP is
960 // either in prologue or in epilogue. This behavior causes a problem when a
961 // call immediately precedes an epilogue, because the return address points
962 // into the epilogue. To cope with that, we insert an epilogue marker here,
963 // then replace it with a 'nop' if it ends up immediately after a CALL in the
964 // final emitted code.
966 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
968 // We're returning from function via eh_return.
969 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
970 MBBI = MBB.getLastNonDebugInstr();
971 MachineOperand &DestAddr = MBBI->getOperand(0);
972 assert(DestAddr.isReg() && "Offset should be in register!");
973 BuildMI(MBB, MBBI, DL,
974 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
975 StackPtr).addReg(DestAddr.getReg());
976 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
977 RetOpcode == X86::TCRETURNmi ||
978 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
979 RetOpcode == X86::TCRETURNmi64) {
980 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
981 // Tail call return: adjust the stack pointer and jump to callee.
982 MBBI = MBB.getLastNonDebugInstr();
983 MachineOperand &JumpTarget = MBBI->getOperand(0);
984 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
985 assert(StackAdjust.isImm() && "Expecting immediate value.");
987 // Adjust stack pointer.
988 int StackAdj = StackAdjust.getImm();
989 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
991 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
993 // Incoporate the retaddr area.
994 Offset = StackAdj-MaxTCDelta;
995 assert(Offset >= 0 && "Offset should never be negative");
998 // Check for possible merge with preceding ADD instruction.
999 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1000 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, IsLP64,
1001 UseLEA, TII, *RegInfo);
1004 // Jump to label or value in register.
1005 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1006 MachineInstrBuilder MIB =
1007 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1008 ? X86::TAILJMPd : X86::TAILJMPd64));
1009 if (JumpTarget.isGlobal())
1010 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1011 JumpTarget.getTargetFlags());
1013 assert(JumpTarget.isSymbol());
1014 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1015 JumpTarget.getTargetFlags());
1017 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1018 MachineInstrBuilder MIB =
1019 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1020 ? X86::TAILJMPm : X86::TAILJMPm64));
1021 for (unsigned i = 0; i != 5; ++i)
1022 MIB.addOperand(MBBI->getOperand(i));
1023 } else if (RetOpcode == X86::TCRETURNri64) {
1024 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1025 addReg(JumpTarget.getReg(), RegState::Kill);
1027 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1028 addReg(JumpTarget.getReg(), RegState::Kill);
1031 MachineInstr *NewMI = std::prev(MBBI);
1032 NewMI->copyImplicitOps(MF, MBBI);
1034 // Delete the pseudo instruction TCRETURN.
1036 } else if ((RetOpcode == X86::RETQ || RetOpcode == X86::RETL ||
1037 RetOpcode == X86::RETIQ || RetOpcode == X86::RETIL) &&
1038 (X86FI->getTCReturnAddrDelta() < 0)) {
1039 // Add the return addr area delta back since we are not tail calling.
1040 int delta = -1*X86FI->getTCReturnAddrDelta();
1041 MBBI = MBB.getLastNonDebugInstr();
1043 // Check for possible merge with preceding ADD instruction.
1044 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1045 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, IsLP64, UseLEA, TII,
1050 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF,
1052 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
1053 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
1054 const MachineFrameInfo *MFI = MF.getFrameInfo();
1055 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1056 uint64_t StackSize = MFI->getStackSize();
1058 if (RegInfo->hasBasePointer(MF)) {
1059 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!");
1061 // Skip the saved EBP.
1062 return Offset + RegInfo->getSlotSize();
1064 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1065 return Offset + StackSize;
1067 } else if (RegInfo->needsStackRealignment(MF)) {
1069 // Skip the saved EBP.
1070 return Offset + RegInfo->getSlotSize();
1072 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1073 return Offset + StackSize;
1075 // FIXME: Support tail calls
1078 return Offset + StackSize;
1080 // Skip the saved EBP.
1081 Offset += RegInfo->getSlotSize();
1083 // Skip the RETADDR move area
1084 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1085 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1086 if (TailCallReturnAddrDelta < 0)
1087 Offset -= TailCallReturnAddrDelta;
1093 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1094 unsigned &FrameReg) const {
1095 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
1096 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
1097 // We can't calculate offset from frame pointer if the stack is realigned,
1098 // so enforce usage of stack/base pointer. The base pointer is used when we
1099 // have dynamic allocas in addition to dynamic realignment.
1100 if (RegInfo->hasBasePointer(MF))
1101 FrameReg = RegInfo->getBaseRegister();
1102 else if (RegInfo->needsStackRealignment(MF))
1103 FrameReg = RegInfo->getStackRegister();
1105 FrameReg = RegInfo->getFrameRegister(MF);
1106 return getFrameIndexOffset(MF, FI);
1109 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1110 MachineFunction &MF, const TargetRegisterInfo *TRI,
1111 std::vector<CalleeSavedInfo> &CSI) const {
1112 MachineFrameInfo *MFI = MF.getFrameInfo();
1113 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
1114 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
1115 unsigned SlotSize = RegInfo->getSlotSize();
1116 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1118 unsigned CalleeSavedFrameSize = 0;
1119 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1122 // emitPrologue always spills frame register the first thing.
1123 SpillSlotOffset -= SlotSize;
1124 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1126 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1127 // the frame register, we can delete it from CSI list and not have to worry
1128 // about avoiding it later.
1129 unsigned FPReg = RegInfo->getFrameRegister(MF);
1130 for (unsigned i = 0; i < CSI.size(); ++i) {
1131 if (CSI[i].getReg() == FPReg) {
1132 CSI.erase(CSI.begin() + i);
1138 // Assign slots for GPRs. It increases frame size.
1139 for (unsigned i = CSI.size(); i != 0; --i) {
1140 unsigned Reg = CSI[i - 1].getReg();
1142 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1145 SpillSlotOffset -= SlotSize;
1146 CalleeSavedFrameSize += SlotSize;
1148 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1149 CSI[i - 1].setFrameIdx(SlotIndex);
1152 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1154 // Assign slots for XMMs.
1155 for (unsigned i = CSI.size(); i != 0; --i) {
1156 unsigned Reg = CSI[i - 1].getReg();
1157 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1160 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
1162 SpillSlotOffset -= abs(SpillSlotOffset) % RC->getAlignment();
1164 SpillSlotOffset -= RC->getSize();
1166 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1167 CSI[i - 1].setFrameIdx(SlotIndex);
1168 MFI->ensureMaxAlignment(RC->getAlignment());
1174 bool X86FrameLowering::spillCalleeSavedRegisters(
1175 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1176 const std::vector<CalleeSavedInfo> &CSI,
1177 const TargetRegisterInfo *TRI) const {
1178 DebugLoc DL = MBB.findDebugLoc(MI);
1180 MachineFunction &MF = *MBB.getParent();
1181 const TargetInstrInfo &TII =
1182 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
1183 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1185 // Push GPRs. It increases frame size.
1186 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1187 for (unsigned i = CSI.size(); i != 0; --i) {
1188 unsigned Reg = CSI[i - 1].getReg();
1190 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1192 // Add the callee-saved register as live-in. It's killed at the spill.
1195 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1196 .setMIFlag(MachineInstr::FrameSetup);
1199 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1200 // It can be done by spilling XMMs to stack frame.
1201 for (unsigned i = CSI.size(); i != 0; --i) {
1202 unsigned Reg = CSI[i-1].getReg();
1203 if (X86::GR64RegClass.contains(Reg) ||
1204 X86::GR32RegClass.contains(Reg))
1206 // Add the callee-saved register as live-in. It's killed at the spill.
1208 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1210 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1213 MI->setFlag(MachineInstr::FrameSetup);
1220 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1221 MachineBasicBlock::iterator MI,
1222 const std::vector<CalleeSavedInfo> &CSI,
1223 const TargetRegisterInfo *TRI) const {
1227 DebugLoc DL = MBB.findDebugLoc(MI);
1229 MachineFunction &MF = *MBB.getParent();
1230 const TargetInstrInfo &TII =
1231 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
1232 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1234 // Reload XMMs from stack frame.
1235 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1236 unsigned Reg = CSI[i].getReg();
1237 if (X86::GR64RegClass.contains(Reg) ||
1238 X86::GR32RegClass.contains(Reg))
1241 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1242 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1246 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1247 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1248 unsigned Reg = CSI[i].getReg();
1249 if (!X86::GR64RegClass.contains(Reg) &&
1250 !X86::GR32RegClass.contains(Reg))
1253 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1259 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1260 RegScavenger *RS) const {
1261 MachineFrameInfo *MFI = MF.getFrameInfo();
1262 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
1263 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
1264 unsigned SlotSize = RegInfo->getSlotSize();
1266 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1267 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1269 if (TailCallReturnAddrDelta < 0) {
1270 // create RETURNADDR area
1279 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1280 TailCallReturnAddrDelta - SlotSize, true);
1283 // Spill the BasePtr if it's used.
1284 if (RegInfo->hasBasePointer(MF))
1285 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1289 HasNestArgument(const MachineFunction *MF) {
1290 const Function *F = MF->getFunction();
1291 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1293 if (I->hasNestAttr())
1299 /// GetScratchRegister - Get a temp register for performing work in the
1300 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1301 /// and the properties of the function either one or two registers will be
1302 /// needed. Set primary to true for the first register, false for the second.
1304 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1305 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1308 if (CallingConvention == CallingConv::HiPE) {
1310 return Primary ? X86::R14 : X86::R13;
1312 return Primary ? X86::EBX : X86::EDI;
1316 return Primary ? X86::R11 : X86::R12;
1318 bool IsNested = HasNestArgument(&MF);
1320 if (CallingConvention == CallingConv::X86_FastCall ||
1321 CallingConvention == CallingConv::Fast) {
1323 report_fatal_error("Segmented stacks does not support fastcall with "
1324 "nested function.");
1325 return Primary ? X86::EAX : X86::ECX;
1328 return Primary ? X86::EDX : X86::EAX;
1329 return Primary ? X86::ECX : X86::EAX;
1332 // The stack limit in the TCB is set to this many bytes above the actual stack
1334 static const uint64_t kSplitStackAvailable = 256;
1337 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1338 MachineBasicBlock &prologueMBB = MF.front();
1339 MachineFrameInfo *MFI = MF.getFrameInfo();
1340 const TargetInstrInfo &TII =
1341 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
1343 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1344 bool Is64Bit = STI.is64Bit();
1345 unsigned TlsReg, TlsOffset;
1348 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1349 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1350 "Scratch register is live-in");
1352 if (MF.getFunction()->isVarArg())
1353 report_fatal_error("Segmented stacks do not support vararg functions.");
1354 if (!STI.isTargetLinux() && !STI.isTargetDarwin() &&
1355 !STI.isTargetWin32() && !STI.isTargetWin64() && !STI.isTargetFreeBSD())
1356 report_fatal_error("Segmented stacks not supported on this platform.");
1358 // Eventually StackSize will be calculated by a link-time pass; which will
1359 // also decide whether checking code needs to be injected into this particular
1361 StackSize = MFI->getStackSize();
1363 // Do not generate a prologue for functions with a stack of size zero
1367 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1368 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1369 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1370 bool IsNested = false;
1372 // We need to know if the function has a nest argument only in 64 bit mode.
1374 IsNested = HasNestArgument(&MF);
1376 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1377 // allocMBB needs to be last (terminating) instruction.
1379 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1380 e = prologueMBB.livein_end(); i != e; i++) {
1381 allocMBB->addLiveIn(*i);
1382 checkMBB->addLiveIn(*i);
1386 allocMBB->addLiveIn(X86::R10);
1388 MF.push_front(allocMBB);
1389 MF.push_front(checkMBB);
1391 // When the frame size is less than 256 we just compare the stack
1392 // boundary directly to the value of the stack pointer, per gcc.
1393 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1395 // Read the limit off the current stacklet off the stack_guard location.
1397 if (STI.isTargetLinux()) {
1400 } else if (STI.isTargetDarwin()) {
1402 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1403 } else if (STI.isTargetWin64()) {
1405 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1406 } else if (STI.isTargetFreeBSD()) {
1410 report_fatal_error("Segmented stacks not supported on this platform.");
1413 if (CompareStackPointer)
1414 ScratchReg = X86::RSP;
1416 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1417 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1419 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1420 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1422 if (STI.isTargetLinux()) {
1425 } else if (STI.isTargetDarwin()) {
1427 TlsOffset = 0x48 + 90*4;
1428 } else if (STI.isTargetWin32()) {
1430 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1431 } else if (STI.isTargetFreeBSD()) {
1432 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1434 report_fatal_error("Segmented stacks not supported on this platform.");
1437 if (CompareStackPointer)
1438 ScratchReg = X86::ESP;
1440 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1441 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1443 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64()) {
1444 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1445 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1446 } else if (STI.isTargetDarwin()) {
1448 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1449 unsigned ScratchReg2;
1451 if (CompareStackPointer) {
1452 // The primary scratch register is available for holding the TLS offset.
1453 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1454 SaveScratch2 = false;
1456 // Need to use a second register to hold the TLS offset
1457 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1459 // Unfortunately, with fastcc the second scratch register may hold an
1461 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1464 // If Scratch2 is live-in then it needs to be saved.
1465 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1466 "Scratch register is live-in and not saved");
1469 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1470 .addReg(ScratchReg2, RegState::Kill);
1472 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1474 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1476 .addReg(ScratchReg2).addImm(1).addReg(0)
1481 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1485 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1486 // It jumps to normal execution of the function body.
1487 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1489 // On 32 bit we first push the arguments size and then the frame size. On 64
1490 // bit, we pass the stack frame size in r10 and the argument size in r11.
1492 // Functions with nested arguments use R10, so it needs to be saved across
1493 // the call to _morestack
1496 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1498 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1500 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1501 .addImm(X86FI->getArgumentStackSize());
1502 MF.getRegInfo().setPhysRegUsed(X86::R10);
1503 MF.getRegInfo().setPhysRegUsed(X86::R11);
1505 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1506 .addImm(X86FI->getArgumentStackSize());
1507 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1511 // __morestack is in libgcc
1513 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1514 .addExternalSymbol("__morestack");
1516 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1517 .addExternalSymbol("__morestack");
1520 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1522 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1524 allocMBB->addSuccessor(&prologueMBB);
1526 checkMBB->addSuccessor(allocMBB);
1527 checkMBB->addSuccessor(&prologueMBB);
1534 /// Erlang programs may need a special prologue to handle the stack size they
1535 /// might need at runtime. That is because Erlang/OTP does not implement a C
1536 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1537 /// (for more information see Eric Stenman's Ph.D. thesis:
1538 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1541 /// temp0 = sp - MaxStack
1542 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1546 /// call inc_stack # doubles the stack space
1547 /// temp0 = sp - MaxStack
1548 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1549 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
1550 const TargetInstrInfo &TII =
1551 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
1552 MachineFrameInfo *MFI = MF.getFrameInfo();
1553 const unsigned SlotSize =
1554 static_cast<const X86RegisterInfo *>(
1555 MF.getTarget().getSubtargetImpl()->getRegisterInfo())->getSlotSize();
1556 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1557 const bool Is64Bit = STI.is64Bit();
1559 // HiPE-specific values
1560 const unsigned HipeLeafWords = 24;
1561 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1562 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1563 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1564 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1565 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1567 assert(STI.isTargetLinux() &&
1568 "HiPE prologue is only supported on Linux operating systems.");
1570 // Compute the largest caller's frame that is needed to fit the callees'
1571 // frames. This 'MaxStack' is computed from:
1573 // a) the fixed frame size, which is the space needed for all spilled temps,
1574 // b) outgoing on-stack parameter areas, and
1575 // c) the minimum stack space this function needs to make available for the
1576 // functions it calls (a tunable ABI property).
1577 if (MFI->hasCalls()) {
1578 unsigned MoreStackForCalls = 0;
1580 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1581 MBBI != MBBE; ++MBBI)
1582 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1587 // Get callee operand.
1588 const MachineOperand &MO = MI->getOperand(0);
1590 // Only take account of global function calls (no closures etc.).
1594 const Function *F = dyn_cast<Function>(MO.getGlobal());
1598 // Do not update 'MaxStack' for primitive and built-in functions
1599 // (encoded with names either starting with "erlang."/"bif_" or not
1600 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1601 // "_", such as the BIF "suspend_0") as they are executed on another
1603 if (F->getName().find("erlang.") != StringRef::npos ||
1604 F->getName().find("bif_") != StringRef::npos ||
1605 F->getName().find_first_of("._") == StringRef::npos)
1608 unsigned CalleeStkArity =
1609 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1610 if (HipeLeafWords - 1 > CalleeStkArity)
1611 MoreStackForCalls = std::max(MoreStackForCalls,
1612 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1614 MaxStack += MoreStackForCalls;
1617 // If the stack frame needed is larger than the guaranteed then runtime checks
1618 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1619 if (MaxStack > Guaranteed) {
1620 MachineBasicBlock &prologueMBB = MF.front();
1621 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1622 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1624 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
1625 E = prologueMBB.livein_end(); I != E; I++) {
1626 stackCheckMBB->addLiveIn(*I);
1627 incStackMBB->addLiveIn(*I);
1630 MF.push_front(incStackMBB);
1631 MF.push_front(stackCheckMBB);
1633 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1634 unsigned LEAop, CMPop, CALLop;
1638 LEAop = X86::LEA64r;
1639 CMPop = X86::CMP64rm;
1640 CALLop = X86::CALL64pcrel32;
1641 SPLimitOffset = 0x90;
1645 LEAop = X86::LEA32r;
1646 CMPop = X86::CMP32rm;
1647 CALLop = X86::CALLpcrel32;
1648 SPLimitOffset = 0x4c;
1651 ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1652 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1653 "HiPE prologue scratch register is live-in");
1655 // Create new MBB for StackCheck:
1656 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1657 SPReg, false, -MaxStack);
1658 // SPLimitOffset is in a fixed heap location (pointed by BP).
1659 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1660 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1661 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
1663 // Create new MBB for IncStack:
1664 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1665 addExternalSymbol("inc_stack_0");
1666 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1667 SPReg, false, -MaxStack);
1668 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1669 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1670 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
1672 stackCheckMBB->addSuccessor(&prologueMBB, 99);
1673 stackCheckMBB->addSuccessor(incStackMBB, 1);
1674 incStackMBB->addSuccessor(&prologueMBB, 99);
1675 incStackMBB->addSuccessor(incStackMBB, 1);
1682 void X86FrameLowering::
1683 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1684 MachineBasicBlock::iterator I) const {
1685 const TargetInstrInfo &TII =
1686 *MF.getTarget().getSubtargetImpl()->getInstrInfo();
1687 const X86RegisterInfo &RegInfo =
1688 *static_cast<const X86RegisterInfo *>(
1689 MF.getTarget().getSubtargetImpl()->getRegisterInfo());
1690 unsigned StackPtr = RegInfo.getStackRegister();
1691 bool reseveCallFrame = hasReservedCallFrame(MF);
1692 int Opcode = I->getOpcode();
1693 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1694 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1695 bool IsLP64 = STI.isTarget64BitLP64();
1696 DebugLoc DL = I->getDebugLoc();
1697 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
1698 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
1701 if (!reseveCallFrame) {
1702 // If the stack pointer can be changed after prologue, turn the
1703 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1704 // adjcallstackdown instruction into 'add ESP, <amt>'
1705 // TODO: consider using push / pop instead of sub + store / add
1709 // We need to keep the stack aligned properly. To do this, we round the
1710 // amount of space needed for the outgoing arguments up to the next
1711 // alignment boundary.
1712 unsigned StackAlign = MF.getTarget()
1714 ->getFrameLowering()
1715 ->getStackAlignment();
1716 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
1718 MachineInstr *New = nullptr;
1719 if (Opcode == TII.getCallFrameSetupOpcode()) {
1720 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)),
1725 assert(Opcode == TII.getCallFrameDestroyOpcode());
1727 // Factor out the amount the callee already popped.
1728 Amount -= CalleeAmt;
1731 unsigned Opc = getADDriOpcode(IsLP64, Amount);
1732 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1733 .addReg(StackPtr).addImm(Amount);
1738 // The EFLAGS implicit def is dead.
1739 New->getOperand(3).setIsDead();
1741 // Replace the pseudo instruction with a new instruction.
1748 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
1749 // If we are performing frame pointer elimination and if the callee pops
1750 // something off the stack pointer, add it back. We do this until we have
1751 // more advanced stack pointer tracking ability.
1752 unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt);
1753 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1754 .addReg(StackPtr).addImm(CalleeAmt);
1756 // The EFLAGS implicit def is dead.
1757 New->getOperand(3).setIsDead();
1759 // We are not tracking the stack pointer adjustment by the callee, so make
1760 // sure we restore the stack pointer immediately after the call, there may
1761 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1762 MachineBasicBlock::iterator B = MBB.begin();
1763 while (I != B && !std::prev(I)->isCall())