1 //===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the X86 machine instructions into
11 // relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86JITInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "X86Relocations.h"
22 #include "llvm/PassManager.h"
23 #include "llvm/CodeGen/MachineCodeEmitter.h"
24 #include "llvm/CodeGen/JITCodeEmitter.h"
25 #include "llvm/CodeGen/ObjectCodeEmitter.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/Function.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 STATISTIC(NumEmitted, "Number of machine instructions emitted");
42 template<class CodeEmitter>
43 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
44 const X86InstrInfo *II;
48 intptr_t PICBaseOffset;
53 explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce)
54 : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
55 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
56 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
57 Emitter(X86TargetMachine &tm, CodeEmitter &mce,
58 const X86InstrInfo &ii, const TargetData &td, bool is64)
59 : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
60 MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
61 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
63 bool runOnMachineFunction(MachineFunction &MF);
65 virtual const char *getPassName() const {
66 return "X86 Machine Code Emitter";
69 void emitInstruction(const MachineInstr &MI,
70 const TargetInstrDesc *Desc);
72 void getAnalysisUsage(AnalysisUsage &AU) const {
73 AU.addRequired<MachineModuleInfo>();
74 MachineFunctionPass::getAnalysisUsage(AU);
78 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
79 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
80 intptr_t Disp = 0, intptr_t PCAdj = 0,
81 bool NeedStub = false, bool Indirect = false);
82 void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
83 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0,
85 void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
88 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
91 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
92 void emitRegModRMByte(unsigned RegOpcodeField);
93 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
94 void emitConstant(uint64_t Val, unsigned Size);
96 void emitMemModRMByte(const MachineInstr &MI,
97 unsigned Op, unsigned RegOpcodeField,
100 unsigned getX86RegNum(unsigned RegNo) const;
102 bool gvNeedsNonLazyPtr(const GlobalValue *GV);
105 template<class CodeEmitter>
106 char Emitter<CodeEmitter>::ID = 0;
109 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
110 /// to the specified templated MachineCodeEmitter object.
112 FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
113 MachineCodeEmitter &MCE) {
114 return new Emitter<MachineCodeEmitter>(TM, MCE);
116 FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM,
117 JITCodeEmitter &JCE) {
118 return new Emitter<JITCodeEmitter>(TM, JCE);
120 FunctionPass *llvm::createX86ObjectCodeEmitterPass(X86TargetMachine &TM,
121 ObjectCodeEmitter &OCE) {
122 return new Emitter<ObjectCodeEmitter>(TM, OCE);
125 template<class CodeEmitter>
126 bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
128 MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
130 II = TM.getInstrInfo();
131 TD = TM.getTargetData();
132 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
133 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
136 DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
137 MCE.startFunction(MF);
138 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
140 MCE.StartMachineBasicBlock(MBB);
141 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
143 const TargetInstrDesc &Desc = I->getDesc();
144 emitInstruction(*I, &Desc);
145 // MOVPC32r is basically a call plus a pop instruction.
146 if (Desc.getOpcode() == X86::MOVPC32r)
147 emitInstruction(*I, &II->get(X86::POP32r));
148 NumEmitted++; // Keep track of the # of mi's emitted
151 } while (MCE.finishFunction(MF));
156 /// emitPCRelativeBlockAddress - This method keeps track of the information
157 /// necessary to resolve the address of this block later and emits a dummy
160 template<class CodeEmitter>
161 void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
162 // Remember where this reference was and where it is to so we can
163 // deal with it later.
164 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
165 X86::reloc_pcrel_word, MBB));
169 /// emitGlobalAddress - Emit the specified address to the code stream assuming
170 /// this is part of a "take the address of a global" instruction.
172 template<class CodeEmitter>
173 void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
174 intptr_t Disp /* = 0 */,
175 intptr_t PCAdj /* = 0 */,
176 bool NeedStub /* = false */,
177 bool Indirect /* = false */) {
178 intptr_t RelocCST = 0;
179 if (Reloc == X86::reloc_picrel_word)
180 RelocCST = PICBaseOffset;
181 else if (Reloc == X86::reloc_pcrel_word)
183 MachineRelocation MR = Indirect
184 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
185 GV, RelocCST, NeedStub)
186 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
187 GV, RelocCST, NeedStub);
188 MCE.addRelocation(MR);
189 // The relocated value will be added to the displacement
190 if (Reloc == X86::reloc_absolute_dword)
191 MCE.emitDWordLE(Disp);
193 MCE.emitWordLE((int32_t)Disp);
196 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
197 /// be emitted to the current location in the function, and allow it to be PC
199 template<class CodeEmitter>
200 void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
202 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
203 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
204 Reloc, ES, RelocCST));
205 if (Reloc == X86::reloc_absolute_dword)
211 /// emitConstPoolAddress - Arrange for the address of an constant pool
212 /// to be emitted to the current location in the function, and allow it to be PC
214 template<class CodeEmitter>
215 void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
216 intptr_t Disp /* = 0 */,
217 intptr_t PCAdj /* = 0 */) {
218 intptr_t RelocCST = 0;
219 if (Reloc == X86::reloc_picrel_word)
220 RelocCST = PICBaseOffset;
221 else if (Reloc == X86::reloc_pcrel_word)
223 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
224 Reloc, CPI, RelocCST));
225 // The relocated value will be added to the displacement
226 if (Reloc == X86::reloc_absolute_dword)
227 MCE.emitDWordLE(Disp);
229 MCE.emitWordLE((int32_t)Disp);
232 /// emitJumpTableAddress - Arrange for the address of a jump table to
233 /// be emitted to the current location in the function, and allow it to be PC
235 template<class CodeEmitter>
236 void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
237 intptr_t PCAdj /* = 0 */) {
238 intptr_t RelocCST = 0;
239 if (Reloc == X86::reloc_picrel_word)
240 RelocCST = PICBaseOffset;
241 else if (Reloc == X86::reloc_pcrel_word)
243 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
244 Reloc, JTI, RelocCST));
245 // The relocated value will be added to the displacement
246 if (Reloc == X86::reloc_absolute_dword)
252 template<class CodeEmitter>
253 unsigned Emitter<CodeEmitter>::getX86RegNum(unsigned RegNo) const {
254 return II->getRegisterInfo().getX86RegNum(RegNo);
257 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
259 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
260 return RM | (RegOpcode << 3) | (Mod << 6);
263 template<class CodeEmitter>
264 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg,
265 unsigned RegOpcodeFld){
266 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
269 template<class CodeEmitter>
270 void Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) {
271 MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
274 template<class CodeEmitter>
275 void Emitter<CodeEmitter>::emitSIBByte(unsigned SS,
278 // SIB byte is in the same format as the ModRMByte...
279 MCE.emitByte(ModRMByte(SS, Index, Base));
282 template<class CodeEmitter>
283 void Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) {
284 // Output the constant in little endian byte order...
285 for (unsigned i = 0; i != Size; ++i) {
286 MCE.emitByte(Val & 255);
291 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
292 /// sign-extended field.
293 static bool isDisp8(int Value) {
294 return Value == (signed char)Value;
297 template<class CodeEmitter>
298 bool Emitter<CodeEmitter>::gvNeedsNonLazyPtr(const GlobalValue *GV) {
299 // For Darwin, simulate the linktime GOT by using the same non-lazy-pointer
300 // mechanism as 32-bit mode.
301 return (!Is64BitMode || TM.getSubtarget<X86Subtarget>().isTargetDarwin()) &&
302 TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
305 template<class CodeEmitter>
306 void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp,
307 int DispVal, intptr_t PCAdj) {
308 // If this is a simple integer displacement that doesn't require a relocation,
311 emitConstant(DispVal, 4);
315 // Otherwise, this is something that requires a relocation. Emit it as such
317 if (RelocOp->isGlobal()) {
318 // In 64-bit static small code model, we could potentially emit absolute.
319 // But it's probably not beneficial.
320 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
321 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
322 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
323 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
324 bool NeedStub = isa<Function>(RelocOp->getGlobal());
325 bool Indirect = gvNeedsNonLazyPtr(RelocOp->getGlobal());
326 emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
327 PCAdj, NeedStub, Indirect);
328 } else if (RelocOp->isCPI()) {
329 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
330 emitConstPoolAddress(RelocOp->getIndex(), rt,
331 RelocOp->getOffset(), PCAdj);
332 } else if (RelocOp->isJTI()) {
333 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
334 emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
336 assert(0 && "Unknown value to relocate!");
340 template<class CodeEmitter>
341 void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI,
342 unsigned Op, unsigned RegOpcodeField,
344 const MachineOperand &Op3 = MI.getOperand(Op+3);
346 const MachineOperand *DispForReloc = 0;
348 // Figure out what sort of displacement we have to handle here.
349 if (Op3.isGlobal()) {
351 } else if (Op3.isCPI()) {
352 if (Is64BitMode || IsPIC) {
355 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
356 DispVal += Op3.getOffset();
358 } else if (Op3.isJTI()) {
359 if (Is64BitMode || IsPIC) {
362 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
365 DispVal = Op3.getImm();
368 const MachineOperand &Base = MI.getOperand(Op);
369 const MachineOperand &Scale = MI.getOperand(Op+1);
370 const MachineOperand &IndexReg = MI.getOperand(Op+2);
372 unsigned BaseReg = Base.getReg();
374 // Is a SIB byte needed?
375 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
376 IndexReg.getReg() == 0 &&
377 (BaseReg == 0 || BaseReg == X86::RIP ||
378 getX86RegNum(BaseReg) != N86::ESP)) {
380 BaseReg == X86::RIP) { // Just a displacement?
381 // Emit special case [disp32] encoding
382 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
384 emitDisplacementField(DispForReloc, DispVal, PCAdj);
386 unsigned BaseRegNo = getX86RegNum(BaseReg);
387 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
388 // Emit simple indirect register encoding... [EAX] f.e.
389 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
390 } else if (!DispForReloc && isDisp8(DispVal)) {
391 // Emit the disp8 encoding... [REG+disp8]
392 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
393 emitConstant(DispVal, 1);
395 // Emit the most general non-SIB encoding: [REG+disp32]
396 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
397 emitDisplacementField(DispForReloc, DispVal, PCAdj);
401 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
402 assert(IndexReg.getReg() != X86::ESP &&
403 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
405 bool ForceDisp32 = false;
406 bool ForceDisp8 = false;
408 // If there is no base register, we emit the special case SIB byte with
409 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
410 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
412 } else if (DispForReloc) {
413 // Emit the normal disp32 encoding.
414 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
416 } else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
417 // Emit no displacement ModR/M byte
418 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
419 } else if (isDisp8(DispVal)) {
420 // Emit the disp8 encoding...
421 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
422 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
424 // Emit the normal disp32 encoding...
425 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
428 // Calculate what the SS field value should be...
429 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
430 unsigned SS = SSTable[Scale.getImm()];
433 // Handle the SIB byte for the case where there is no base. The
434 // displacement has already been output.
436 if (IndexReg.getReg())
437 IndexRegNo = getX86RegNum(IndexReg.getReg());
439 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
440 emitSIBByte(SS, IndexRegNo, 5);
442 unsigned BaseRegNo = getX86RegNum(BaseReg);
444 if (IndexReg.getReg())
445 IndexRegNo = getX86RegNum(IndexReg.getReg());
447 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
448 emitSIBByte(SS, IndexRegNo, BaseRegNo);
451 // Do we need to output a displacement?
453 emitConstant(DispVal, 1);
454 } else if (DispVal != 0 || ForceDisp32) {
455 emitDisplacementField(DispForReloc, DispVal, PCAdj);
460 template<class CodeEmitter>
461 void Emitter<CodeEmitter>::emitInstruction(
462 const MachineInstr &MI,
463 const TargetInstrDesc *Desc) {
466 unsigned Opcode = Desc->Opcode;
468 // Emit the lock opcode prefix as needed.
469 if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
471 // Emit segment override opcode prefix as needed.
472 switch (Desc->TSFlags & X86II::SegOvrMask) {
479 default: assert(0 && "Invalid segment!");
480 case 0: break; // No segment override!
483 // Emit the repeat opcode prefix as needed.
484 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
486 // Emit the operand size opcode prefix as needed.
487 if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
489 // Emit the address size opcode prefix as needed.
490 if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
492 bool Need0FPrefix = false;
493 switch (Desc->TSFlags & X86II::Op0Mask) {
494 case X86II::TB: // Two-byte opcode prefix
495 case X86II::T8: // 0F 38
496 case X86II::TA: // 0F 3A
499 case X86II::REP: break; // already handled.
500 case X86II::XS: // F3 0F
504 case X86II::XD: // F2 0F
508 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
509 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
511 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
512 >> X86II::Op0Shift));
513 break; // Two-byte opcode prefix
514 default: assert(0 && "Invalid prefix!");
515 case 0: break; // No prefix!
520 unsigned REX = X86InstrInfo::determineREX(MI);
522 MCE.emitByte(0x40 | REX);
525 // 0x0F escape code must be emitted just before the opcode.
529 switch (Desc->TSFlags & X86II::Op0Mask) {
530 case X86II::T8: // 0F 38
533 case X86II::TA: // 0F 3A
538 // If this is a two-address instruction, skip one of the register operands.
539 unsigned NumOps = Desc->getNumOperands();
541 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
543 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
544 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
547 unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
548 switch (Desc->TSFlags & X86II::FormMask) {
549 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
551 // Remember the current PC offset, this is the PIC relocation
555 assert(0 && "psuedo instructions should be removed before code emission");
557 case TargetInstrInfo::INLINEASM: {
558 // We allow inline assembler nodes with empty bodies - they can
559 // implicitly define registers, which is ok for JIT.
560 if (MI.getOperand(0).getSymbolName()[0]) {
561 llvm_report_error("JIT does not support inline asm!");
565 case TargetInstrInfo::DBG_LABEL:
566 case TargetInstrInfo::EH_LABEL:
567 MCE.emitLabel(MI.getOperand(0).getImm());
569 case TargetInstrInfo::IMPLICIT_DEF:
570 case TargetInstrInfo::DECLARE:
572 case X86::FP_REG_KILL:
574 case X86::MOVPC32r: {
575 // This emits the "call" portion of this pseudo instruction.
576 MCE.emitByte(BaseOpcode);
577 emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
578 // Remember PIC base.
579 PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset();
580 X86JITInfo *JTI = TM.getJITInfo();
581 JTI->setPICBase(MCE.getCurrentPCValue());
588 MCE.emitByte(BaseOpcode);
590 if (CurOp != NumOps) {
591 const MachineOperand &MO = MI.getOperand(CurOp++);
593 DOUT << "RawFrm CurOp " << CurOp << "\n";
594 DOUT << "isMBB " << MO.isMBB() << "\n";
595 DOUT << "isGlobal " << MO.isGlobal() << "\n";
596 DOUT << "isSymbol " << MO.isSymbol() << "\n";
597 DOUT << "isImm " << MO.isImm() << "\n";
600 emitPCRelativeBlockAddress(MO.getMBB());
601 } else if (MO.isGlobal()) {
602 // Assume undefined functions may be outside the Small codespace.
605 (TM.getCodeModel() == CodeModel::Large ||
606 TM.getSubtarget<X86Subtarget>().isTargetDarwin())) ||
607 Opcode == X86::TAILJMPd;
608 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
609 MO.getOffset(), 0, NeedStub);
610 } else if (MO.isSymbol()) {
611 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
612 } else if (MO.isImm()) {
613 if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) {
614 // Fix up immediate operand for pc relative calls.
615 intptr_t Imm = (intptr_t)MO.getImm();
616 Imm = Imm - MCE.getCurrentPCValue() - 4;
617 emitConstant(Imm, X86InstrInfo::sizeOfImm(Desc));
619 emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
621 assert(0 && "Unknown RawFrm operand!");
626 case X86II::AddRegFrm:
627 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
629 if (CurOp != NumOps) {
630 const MachineOperand &MO1 = MI.getOperand(CurOp++);
631 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
633 emitConstant(MO1.getImm(), Size);
635 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
636 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
637 // This should not occur on Darwin for relocatable objects.
638 if (Opcode == X86::MOV64ri)
639 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
640 if (MO1.isGlobal()) {
641 bool NeedStub = isa<Function>(MO1.getGlobal());
642 bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal());
643 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
645 } else if (MO1.isSymbol())
646 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
647 else if (MO1.isCPI())
648 emitConstPoolAddress(MO1.getIndex(), rt);
649 else if (MO1.isJTI())
650 emitJumpTableAddress(MO1.getIndex(), rt);
655 case X86II::MRMDestReg: {
656 MCE.emitByte(BaseOpcode);
657 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
658 getX86RegNum(MI.getOperand(CurOp+1).getReg()));
661 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
664 case X86II::MRMDestMem: {
665 MCE.emitByte(BaseOpcode);
666 emitMemModRMByte(MI, CurOp,
667 getX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)
669 CurOp += X86AddrNumOperands + 1;
671 emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
675 case X86II::MRMSrcReg:
676 MCE.emitByte(BaseOpcode);
677 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
678 getX86RegNum(MI.getOperand(CurOp).getReg()));
681 emitConstant(MI.getOperand(CurOp++).getImm(),
682 X86InstrInfo::sizeOfImm(Desc));
685 case X86II::MRMSrcMem: {
686 // FIXME: Maybe lea should have its own form?
688 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
689 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
690 AddrOperands = X86AddrNumOperands - 1; // No segment register
692 AddrOperands = X86AddrNumOperands;
694 intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
695 X86InstrInfo::sizeOfImm(Desc) : 0;
697 MCE.emitByte(BaseOpcode);
698 emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
700 CurOp += AddrOperands + 1;
702 emitConstant(MI.getOperand(CurOp++).getImm(),
703 X86InstrInfo::sizeOfImm(Desc));
707 case X86II::MRM0r: case X86II::MRM1r:
708 case X86II::MRM2r: case X86II::MRM3r:
709 case X86II::MRM4r: case X86II::MRM5r:
710 case X86II::MRM6r: case X86II::MRM7r: {
711 MCE.emitByte(BaseOpcode);
713 // Special handling of lfence, mfence, monitor, and mwait.
714 if (Desc->getOpcode() == X86::LFENCE ||
715 Desc->getOpcode() == X86::MFENCE ||
716 Desc->getOpcode() == X86::MONITOR ||
717 Desc->getOpcode() == X86::MWAIT) {
718 emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
720 switch (Desc->getOpcode()) {
730 emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
731 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
734 if (CurOp != NumOps) {
735 const MachineOperand &MO1 = MI.getOperand(CurOp++);
736 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
738 emitConstant(MO1.getImm(), Size);
740 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
741 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
742 if (Opcode == X86::MOV64ri32)
743 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
744 if (MO1.isGlobal()) {
745 bool NeedStub = isa<Function>(MO1.getGlobal());
746 bool Indirect = gvNeedsNonLazyPtr(MO1.getGlobal());
747 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
749 } else if (MO1.isSymbol())
750 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
751 else if (MO1.isCPI())
752 emitConstPoolAddress(MO1.getIndex(), rt);
753 else if (MO1.isJTI())
754 emitJumpTableAddress(MO1.getIndex(), rt);
760 case X86II::MRM0m: case X86II::MRM1m:
761 case X86II::MRM2m: case X86II::MRM3m:
762 case X86II::MRM4m: case X86II::MRM5m:
763 case X86II::MRM6m: case X86II::MRM7m: {
764 intptr_t PCAdj = (CurOp + X86AddrNumOperands != NumOps) ?
765 (MI.getOperand(CurOp+X86AddrNumOperands).isImm() ?
766 X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
768 MCE.emitByte(BaseOpcode);
769 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
771 CurOp += X86AddrNumOperands;
773 if (CurOp != NumOps) {
774 const MachineOperand &MO = MI.getOperand(CurOp++);
775 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
777 emitConstant(MO.getImm(), Size);
779 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
780 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
781 if (Opcode == X86::MOV64mi32)
782 rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
784 bool NeedStub = isa<Function>(MO.getGlobal());
785 bool Indirect = gvNeedsNonLazyPtr(MO.getGlobal());
786 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
788 } else if (MO.isSymbol())
789 emitExternalSymbolAddress(MO.getSymbolName(), rt);
791 emitConstPoolAddress(MO.getIndex(), rt);
793 emitJumpTableAddress(MO.getIndex(), rt);
799 case X86II::MRMInitReg:
800 MCE.emitByte(BaseOpcode);
801 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
802 emitRegModRMByte(MI.getOperand(CurOp).getReg(),
803 getX86RegNum(MI.getOperand(CurOp).getReg()));
808 if (!Desc->isVariadic() && CurOp != NumOps) {
810 raw_string_ostream Msg(msg);
811 Msg << "Cannot encode: " << MI;
812 llvm_report_error(Msg.str());