1 //===-- X86/MachineCodeEmitter.cpp - Convert X86 code to machine code -----===//
3 // This file contains the pass that transforms the X86 machine instructions into
4 // actual executable machine code.
6 //===----------------------------------------------------------------------===//
8 #include "X86TargetMachine.h"
10 #include "llvm/PassManager.h"
11 #include "llvm/CodeGen/MachineCodeEmitter.h"
12 #include "llvm/CodeGen/MachineFunctionPass.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/Value.h"
17 class Emitter : public MachineFunctionPass {
18 const X86InstrInfo *II;
19 MachineCodeEmitter &MCE;
22 Emitter(MachineCodeEmitter &mce) : II(0), MCE(mce) {}
24 bool runOnMachineFunction(MachineFunction &MF);
26 virtual const char *getPassName() const {
27 return "X86 Machine Code Emitter";
31 void emitBasicBlock(MachineBasicBlock &MBB);
32 void emitInstruction(MachineInstr &MI);
34 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
35 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
36 void emitConstant(unsigned Val, unsigned Size);
38 void emitMemModRMByte(const MachineInstr &MI,
39 unsigned Op, unsigned RegOpcodeField);
45 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
46 /// machine code emitted. This uses a MAchineCodeEmitter object to handle
47 /// actually outputting the machine code and resolving things like the address
48 /// of functions. This method should returns true if machine code emission is
51 bool X86TargetMachine::addPassesToEmitMachineCode(PassManager &PM,
52 MachineCodeEmitter &MCE) {
53 PM.add(new Emitter(MCE));
57 bool Emitter::runOnMachineFunction(MachineFunction &MF) {
58 II = &((X86TargetMachine&)MF.getTarget()).getInstrInfo();
60 MCE.startFunction(MF);
61 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
63 MCE.finishFunction(MF);
67 void Emitter::emitBasicBlock(MachineBasicBlock &MBB) {
68 MCE.startBasicBlock(MBB);
69 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
74 namespace N86 { // Native X86 Register numbers...
76 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
81 // getX86RegNum - This function maps LLVM register identifiers to their X86
82 // specific numbering, which is used in various places encoding instructions.
84 static unsigned getX86RegNum(unsigned RegNo) {
86 case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
87 case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
88 case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
89 case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
90 case X86::ESP: case X86::SP: case X86::AH: return N86::ESP;
91 case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
92 case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
93 case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
95 assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
96 "Unknown physical register!");
97 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
102 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
104 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
105 return RM | (RegOpcode << 3) | (Mod << 6);
108 void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
109 MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
112 void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
113 // SIB byte is in the same format as the ModRMByte...
114 MCE.emitByte(ModRMByte(SS, Index, Base));
117 void Emitter::emitConstant(unsigned Val, unsigned Size) {
118 // Output the constant in little endian byte order...
119 for (unsigned i = 0; i != Size; ++i) {
120 MCE.emitByte(Val & 255);
125 static bool isDisp8(int Value) {
126 return Value == (signed char)Value;
129 void Emitter::emitMemModRMByte(const MachineInstr &MI,
130 unsigned Op, unsigned RegOpcodeField) {
131 const MachineOperand &BaseReg = MI.getOperand(Op);
132 const MachineOperand &Scale = MI.getOperand(Op+1);
133 const MachineOperand &IndexReg = MI.getOperand(Op+2);
134 const MachineOperand &Disp = MI.getOperand(Op+3);
136 // Is a SIB byte needed?
137 if (IndexReg.getReg() == 0 && BaseReg.getReg() != X86::ESP) {
138 if (BaseReg.getReg() == 0) { // Just a displacement?
139 // Emit special case [disp32] encoding
140 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
141 emitConstant(Disp.getImmedValue(), 4);
143 unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
144 if (Disp.getImmedValue() == 0 && BaseRegNo != N86::EBP) {
145 // Emit simple indirect register encoding... [EAX] f.e.
146 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
147 } else if (isDisp8(Disp.getImmedValue())) {
148 // Emit the disp8 encoding... [REG+disp8]
149 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
150 emitConstant(Disp.getImmedValue(), 1);
152 // Emit the most general non-SIB encoding: [REG+disp32]
153 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
154 emitConstant(Disp.getImmedValue(), 4);
158 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
159 assert(IndexReg.getReg() != X86::ESP && "Cannot use ESP as index reg!");
161 bool ForceDisp32 = false;
162 bool ForceDisp8 = false;
163 if (BaseReg.getReg() == 0) {
164 // If there is no base register, we emit the special case SIB byte with
165 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
166 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
168 } else if (Disp.getImmedValue() == 0 && BaseReg.getReg() != X86::EBP) {
169 // Emit no displacement ModR/M byte
170 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
171 } else if (isDisp8(Disp.getImmedValue())) {
172 // Emit the disp8 encoding...
173 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
174 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
176 // Emit the normal disp32 encoding...
177 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
180 // Calculate what the SS field value should be...
181 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
182 unsigned SS = SSTable[Scale.getImmedValue()];
184 if (BaseReg.getReg() == 0) {
185 // Handle the SIB byte for the case where there is no base. The
186 // displacement has already been output.
187 assert(IndexReg.getReg() && "Index register must be specified!");
188 emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
190 unsigned BaseRegNo = getX86RegNum(BaseReg.getReg());
192 if (IndexReg.getReg())
193 IndexRegNo = getX86RegNum(IndexReg.getReg());
195 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
196 emitSIBByte(SS, IndexRegNo, BaseRegNo);
199 // Do we need to output a displacement?
200 if (Disp.getImmedValue() != 0 || ForceDisp32 || ForceDisp8) {
201 if (!ForceDisp32 && isDisp8(Disp.getImmedValue()))
202 emitConstant(Disp.getImmedValue(), 1);
204 emitConstant(Disp.getImmedValue(), 4);
209 unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
210 switch (Desc.TSFlags & X86II::ArgMask) {
211 case X86II::Arg8: return 1;
212 case X86II::Arg16: return 2;
213 case X86II::Arg32: return 4;
214 case X86II::ArgF32: return 4;
215 case X86II::ArgF64: return 8;
216 case X86II::ArgF80: return 10;
217 default: assert(0 && "Memory size not set!");
223 void Emitter::emitInstruction(MachineInstr &MI) {
224 unsigned Opcode = MI.getOpcode();
225 const MachineInstrDescriptor &Desc = II->get(Opcode);
227 // Emit instruction prefixes if neccesary
228 if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
230 switch (Desc.TSFlags & X86II::Op0Mask) {
232 MCE.emitByte(0x0F); // Two-byte opcode prefix
234 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
235 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
236 MCE.emitByte(0xD8 + (Desc.TSFlags & X86II::Op0Mask)-X86II::D8);
237 break; // Two-byte opcode prefix
239 default: break; // No prefix!
242 unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
243 switch (Desc.TSFlags & X86II::FormMask) {
244 default: assert(0 && "Unknown FormMask value!");
246 std::cerr << "X86 Machine Code Emitter: Not emitting: " << MI;
249 MCE.emitByte(BaseOpcode);
251 if (MI.getNumOperands() == 1) {
252 assert(MI.getOperand(0).getType() == MachineOperand::MO_PCRelativeDisp);
253 MCE.emitPCRelativeDisp(MI.getOperand(0).getVRegValue());
256 case X86II::AddRegFrm:
257 MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(0).getReg()));
258 if (MI.getNumOperands() == 2 && (MI.getOperand(1).isImmediate() ||
259 MI.getOperand(1).getVRegValueOrNull())) {
260 unsigned Size = sizeOfPtr(Desc);
261 if (Value *V = MI.getOperand(1).getVRegValueOrNull()) {
262 assert(Size == 4 && "Don't know how to emit non-pointer values!");
263 MCE.emitGlobalAddress(cast<GlobalValue>(V));
265 emitConstant(MI.getOperand(1).getImmedValue(), Size);
269 case X86II::MRMDestReg:
270 MCE.emitByte(BaseOpcode);
271 emitRegModRMByte(MI.getOperand(0).getReg(),
272 getX86RegNum(MI.getOperand(MI.getNumOperands()-1).getReg()));
274 case X86II::MRMDestMem:
275 MCE.emitByte(BaseOpcode);
276 emitMemModRMByte(MI, 0, getX86RegNum(MI.getOperand(4).getReg()));
278 case X86II::MRMSrcReg:
279 MCE.emitByte(BaseOpcode);
280 emitRegModRMByte(MI.getOperand(MI.getNumOperands()-1).getReg(),
281 getX86RegNum(MI.getOperand(0).getReg()));
283 case X86II::MRMSrcMem:
284 MCE.emitByte(BaseOpcode);
285 emitMemModRMByte(MI, MI.getNumOperands()-4,
286 getX86RegNum(MI.getOperand(0).getReg()));
289 case X86II::MRMS0r: case X86II::MRMS1r:
290 case X86II::MRMS2r: case X86II::MRMS3r:
291 case X86II::MRMS4r: case X86II::MRMS5r:
292 case X86II::MRMS6r: case X86II::MRMS7r:
293 MCE.emitByte(BaseOpcode);
294 emitRegModRMByte(MI.getOperand(0).getReg(),
295 (Desc.TSFlags & X86II::FormMask)-X86II::MRMS0r);
297 if (MI.getOperand(MI.getNumOperands()-1).isImmediate()) {
298 unsigned Size = sizeOfPtr(Desc);
299 emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(), Size);