1 //===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the X86-32 and X86-64
13 //===----------------------------------------------------------------------===//
15 /// CCIfSubtarget - Match if the current subtarget has a feature F.
16 class CCIfSubtarget<string F, CCAction A>
17 : CCIf<!strconcat("State.getTarget().getSubtarget<X86Subtarget>().", F), A>;
19 //===----------------------------------------------------------------------===//
20 // Return Value Calling Conventions
21 //===----------------------------------------------------------------------===//
23 // Return-value conventions common to all X86 CC's.
24 def RetCC_X86Common : CallingConv<[
25 // Scalar values are returned in AX first, then DX.
26 CCIfType<[i8] , CCAssignToReg<[AL]>>,
27 CCIfType<[i16], CCAssignToReg<[AX, DX]>>,
28 CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>,
29 CCIfType<[i64], CCAssignToReg<[RAX, RDX]>>,
31 // Vector types are returned in XMM0 and XMM1, when they fit. If the target
32 // doesn't have XMM registers, it won't have vector types.
33 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
34 CCAssignToReg<[XMM0,XMM1]>>,
36 // MMX vector types are always returned in MM0. If the target doesn't have
37 // MM0, it doesn't support these vector types.
38 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToReg<[MM0]>>,
40 // Long double types are always returned in ST0 (even with SSE).
41 CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
44 // X86-32 C return-value convention.
45 def RetCC_X86_32_C : CallingConv<[
46 // The X86-32 calling convention returns FP values in ST0, otherwise it is the
47 // same as the common X86 calling conv.
48 CCIfType<[f32], CCAssignToReg<[ST0, ST1]>>,
49 CCIfType<[f64], CCAssignToReg<[ST0, ST1]>>,
50 CCDelegateTo<RetCC_X86Common>
53 // X86-32 FastCC return-value convention.
54 def RetCC_X86_32_Fast : CallingConv<[
55 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
56 // SSE2, otherwise it is the the C calling conventions.
57 // This can happen when a float, 2 x float, or 3 x float vector is split by
58 // target lowering, and is returned in 1-3 sse regs.
59 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
60 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
61 CCDelegateTo<RetCC_X86Common>
64 // X86-32 SSEregparm return-value convention.
65 def RetCC_X86_32_SSE : CallingConv<[
66 // The X86-32 sseregparm calling convention returns FP values in XMM0 if the
67 // target has SSE2, otherwise it is the C calling convention.
68 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>,
69 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0]>>>,
70 CCDelegateTo<RetCC_X86Common>
73 // X86-64 C return-value convention.
74 def RetCC_X86_64_C : CallingConv<[
75 // The X86-64 calling convention always returns FP values in XMM0.
76 CCIfType<[f32], CCAssignToReg<[XMM0]>>,
77 CCIfType<[f64], CCAssignToReg<[XMM0]>>,
78 CCDelegateTo<RetCC_X86Common>
81 // X86-Win64 C return-value convention.
82 def RetCC_X86_Win64_C : CallingConv<[
83 // The X86-Win64 calling convention always returns __m64 values in RAX.
84 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToReg<[RAX]>>,
86 // Otherwise, everything is the same as 'normal' X86-64 C CC.
87 CCDelegateTo<RetCC_X86_64_C>
91 // This is the root return-value convention for the X86-32 backend.
92 def RetCC_X86_32 : CallingConv<[
93 // If FastCC, use RetCC_X86_32_Fast.
94 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
95 // If SSECC, use RetCC_X86_32_SSE.
96 CCIfCC<"CallingConv::X86_SSECall", CCDelegateTo<RetCC_X86_32_SSE>>,
97 // Otherwise, use RetCC_X86_32_C.
98 CCDelegateTo<RetCC_X86_32_C>
101 // This is the root return-value convention for the X86-64 backend.
102 def RetCC_X86_64 : CallingConv<[
103 // Mingw64 and native Win64 use Win64 CC
104 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
106 // Otherwise, drop to normal X86-64 CC
107 CCDelegateTo<RetCC_X86_64_C>
110 // This is the return-value convention used for the entire X86 backend.
111 def RetCC_X86 : CallingConv<[
112 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
113 CCDelegateTo<RetCC_X86_32>
116 //===----------------------------------------------------------------------===//
117 // X86-64 Argument Calling Conventions
118 //===----------------------------------------------------------------------===//
120 def CC_X86_64_C : CallingConv<[
121 // Handles byval parameters.
122 CCIfByVal<CCPassByVal<8, 8>>,
124 // Promote i8/i16 arguments to i32.
125 CCIfType<[i8, i16], CCPromoteToType<i32>>,
127 // The 'nest' parameter, if any, is passed in R10.
128 CCIfNest<CCAssignToReg<[R10]>>,
130 // The first 6 integer arguments are passed in integer registers.
131 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
132 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
134 // The first 8 FP/Vector arguments are passed in XMM registers.
135 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
136 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
138 // The first 8 MMX vector arguments are passed in GPRs.
139 CCIfType<[v8i8, v4i16, v2i32, v1i64],
140 CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
142 // Integer/FP values get stored in stack slots that are 8 bytes in size and
143 // 8-byte aligned if there are no more registers to hold them.
144 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
146 // Long doubles get stack slots whose size and alignment depends on the
148 CCIfType<[f80], CCAssignToStack<0, 0>>,
150 // Vectors get 16-byte stack slots that are 16-byte aligned.
151 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
153 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
154 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
157 // Calling convention used on Win64
158 def CC_X86_Win64_C : CallingConv<[
159 // FIXME: Handle byval stuff.
160 // FIXME: Handle fp80.
161 // FIXME: Handle varargs.
163 // Promote i8/i16 arguments to i32.
164 CCIfType<[i8, i16], CCPromoteToType<i32>>,
166 // The 'nest' parameter, if any, is passed in R10.
167 CCIfNest<CCAssignToReg<[R10]>>,
169 // The first 4 integer arguments are passed in integer registers.
170 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
171 [XMM0, XMM1, XMM2, XMM3]>>,
172 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
173 [XMM0, XMM1, XMM2, XMM3]>>,
175 // The first 4 FP/Vector arguments are passed in XMM registers.
176 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
177 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
178 [RCX , RDX , R8 , R9 ]>>,
180 // The first 4 MMX vector arguments are passed in GPRs.
181 CCIfType<[v8i8, v4i16, v2i32, v1i64],
182 CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
183 [XMM0, XMM1, XMM2, XMM3]>>,
185 // Integer/FP values get stored in stack slots that are 8 bytes in size and
186 // 16-byte aligned if there are no more registers to hold them.
187 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 16>>,
189 // Vectors get 16-byte stack slots that are 16-byte aligned.
190 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
192 // __m64 vectors get 8-byte stack slots that are 16-byte aligned.
193 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 16>>
196 // Tail call convention (fast): One register is reserved for target address,
198 def CC_X86_64_TailCall : CallingConv<[
199 // Handles byval parameters.
200 CCIfByVal<CCPassByVal<8, 8>>,
202 // Promote i8/i16 arguments to i32.
203 CCIfType<[i8, i16], CCPromoteToType<i32>>,
205 // The 'nest' parameter, if any, is passed in R10.
206 CCIfNest<CCAssignToReg<[R10]>>,
208 // The first 6 integer arguments are passed in integer registers.
209 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D]>>,
210 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>,
212 // The first 8 FP/Vector arguments are passed in XMM registers.
213 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
214 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>,
216 // The first 8 MMX vector arguments are passed in GPRs.
217 CCIfType<[v8i8, v4i16, v2i32, v1i64],
218 CCAssignToReg<[RDI, RSI, RDX, RCX, R8]>>,
220 // Integer/FP values get stored in stack slots that are 8 bytes in size and
221 // 8-byte aligned if there are no more registers to hold them.
222 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
224 // Vectors get 16-byte stack slots that are 16-byte aligned.
225 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
227 // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
228 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
232 //===----------------------------------------------------------------------===//
233 // X86 C Calling Convention
234 //===----------------------------------------------------------------------===//
236 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
237 /// values are spilled on the stack, and the first 4 vector values go in XMM
239 def CC_X86_32_Common : CallingConv<[
240 // Handles byval parameters.
241 CCIfByVal<CCPassByVal<4, 4>>,
243 // The first 3 float or double arguments, if marked 'inreg' and if the call
244 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
245 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64], CCIfSubtarget<"hasSSE2()",
246 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
248 // Integer/Float values get stored in stack slots that are 4 bytes in
249 // size and 4-byte aligned.
250 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
252 // Doubles get 8-byte slots that are 4-byte aligned.
253 CCIfType<[f64], CCAssignToStack<8, 4>>,
255 // Long doubles get slots whose size depends on the subtarget.
256 CCIfType<[f80], CCAssignToStack<0, 4>>,
258 // The first 4 SSE vector arguments are passed in XMM registers.
259 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
260 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
262 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
263 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
265 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
266 // passed in the parameter area.
267 CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 4>>
270 def CC_X86_32_C : CallingConv<[
271 // Promote i8/i16 arguments to i32.
272 CCIfType<[i8, i16], CCPromoteToType<i32>>,
274 // The 'nest' parameter, if any, is passed in ECX.
275 CCIfNest<CCAssignToReg<[ECX]>>,
277 // The first 3 integer arguments, if marked 'inreg' and if the call is not
278 // a vararg call, are passed in integer registers.
279 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
281 // Otherwise, same as everything else.
282 CCDelegateTo<CC_X86_32_Common>
285 /// Same as C calling convention except for non-free ECX which is used for storing
286 /// a potential pointer to the tail called function.
287 def CC_X86_32_TailCall : CallingConv<[
288 // Promote i8/i16 arguments to i32.
289 CCIfType<[i8, i16], CCPromoteToType<i32>>,
291 // Nested function trampolines are currently not supported by fastcc.
293 // The first 3 integer arguments, if marked 'inreg' and if the call is not
294 // a vararg call, are passed in integer registers.
295 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>>>,
297 // Otherwise, same as everything else.
298 CCDelegateTo<CC_X86_32_Common>
301 def CC_X86_32_FastCall : CallingConv<[
302 // Promote i8/i16 arguments to i32.
303 CCIfType<[i8, i16], CCPromoteToType<i32>>,
305 // The 'nest' parameter, if any, is passed in EAX.
306 CCIfNest<CCAssignToReg<[EAX]>>,
308 // The first 2 integer arguments are passed in ECX/EDX
309 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
311 // Otherwise, same as everything else.
312 CCDelegateTo<CC_X86_32_Common>