1 //===-- X86ATTAsmPrinter.cpp - Convert X86 LLVM code to Intel assembly ----===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to AT&T format assembly
12 // language. This printer is the output mechanism used by `llc'.
14 //===----------------------------------------------------------------------===//
16 #include "X86ATTAsmPrinter.h"
18 #include "X86TargetMachine.h"
19 #include "X86TargetAsmInfo.h"
20 #include "llvm/Module.h"
21 #include "llvm/Support/Mangler.h"
22 #include "llvm/Target/TargetAsmInfo.h"
23 #include "llvm/Target/TargetOptions.h"
27 /// runOnMachineFunction - This uses the printMachineInstruction()
28 /// method to print assembly for each instruction.
30 bool X86ATTAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
31 if (Subtarget->isTargetDarwin()) {
32 // Let PassManager know we need debug information and relay
33 // the MachineDebugInfo address on to DwarfWriter.
34 DW.SetDebugInfo(&getAnalysis<MachineDebugInfo>());
37 SetupMachineFunction(MF);
40 // Print out constants referenced by the function
41 EmitConstantPool(MF.getConstantPool());
43 // Print out labels for the function.
44 const Function *F = MF.getFunction();
45 switch (F->getLinkage()) {
46 default: assert(0 && "Unknown linkage type!");
47 case Function::InternalLinkage: // Symbols default to internal.
48 SwitchToTextSection(TAI->getTextSection(), F);
49 EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
51 case Function::DLLExportLinkage:
52 DLLExportedFns.insert(Mang->makeNameProper(F->getName(), ""));
54 case Function::ExternalLinkage:
55 SwitchToTextSection(TAI->getTextSection(), F);
56 EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
57 O << "\t.globl\t" << CurrentFnName << "\n";
59 case Function::WeakLinkage:
60 case Function::LinkOnceLinkage:
61 if (Subtarget->isTargetDarwin()) {
63 ".section __TEXT,__textcoal_nt,coalesced,pure_instructions", F);
64 O << "\t.globl\t" << CurrentFnName << "\n";
65 O << "\t.weak_definition\t" << CurrentFnName << "\n";
66 } else if (Subtarget->TargetType == X86Subtarget::isCygwin) {
67 EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
68 O << "\t.section\t.llvm.linkonce.t." << CurrentFnName
70 SwitchToTextSection("", F);
71 O << "\t.weak " << CurrentFnName << "\n";
73 EmitAlignment(4, F); // FIXME: This should be parameterized somewhere.
74 O << "\t.section\t.llvm.linkonce.t." << CurrentFnName
75 << ",\"ax\",@progbits\n";
76 SwitchToTextSection("", F);
77 O << "\t.weak " << CurrentFnName << "\n";
81 O << CurrentFnName << ":\n";
83 if (Subtarget->isTargetDarwin()) {
84 // Emit pre-function debug information.
85 DW.BeginFunction(&MF);
88 // Print out code for the function.
89 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
91 // Print a label for the basic block.
92 if (I->pred_begin() != I->pred_end()) {
93 printBasicBlockLabel(I, true);
96 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
98 // Print the assembly for the instruction.
100 printMachineInstruction(II);
104 // Print out jump tables referenced by the function
105 // Mac OS X requires at least one non-local (e.g. L1) labels before local
106 // lables that are used in jump table expressions (e.g. LBB1_1-LJT1_0).
107 EmitJumpTableInfo(MF.getJumpTableInfo());
109 if (TAI->hasDotTypeDotSizeDirective())
110 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
112 if (Subtarget->isTargetDarwin()) {
113 // Emit post-function debug information.
117 // We didn't modify anything.
121 void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
122 const char *Modifier) {
123 const MachineOperand &MO = MI->getOperand(OpNo);
124 const MRegisterInfo &RI = *TM.getRegisterInfo();
125 switch (MO.getType()) {
126 case MachineOperand::MO_Register: {
127 assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
128 "Virtual registers should not make it this far!");
130 unsigned Reg = MO.getReg();
131 if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
132 MVT::ValueType VT = (strcmp(Modifier+6,"64") == 0) ?
133 MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
134 ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
135 Reg = getX86SubSuperRegister(Reg, VT);
137 for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
138 O << (char)tolower(*Name);
142 case MachineOperand::MO_Immediate:
143 if (!Modifier || strcmp(Modifier, "debug") != 0)
145 O << MO.getImmedValue();
147 case MachineOperand::MO_MachineBasicBlock:
148 printBasicBlockLabel(MO.getMachineBasicBlock());
150 case MachineOperand::MO_JumpTableIndex: {
151 bool isMemOp = Modifier && !strcmp(Modifier, "mem");
152 if (!isMemOp) O << '$';
153 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() << "_"
154 << MO.getJumpTableIndex();
155 if (X86PICStyle == PICStyle::Stub &&
156 TM.getRelocationModel() == Reloc::PIC_)
157 O << "-\"L" << getFunctionNumber() << "$pb\"";
158 if (Subtarget->is64Bit())
162 case MachineOperand::MO_ConstantPoolIndex: {
163 bool isMemOp = Modifier && !strcmp(Modifier, "mem");
164 if (!isMemOp) O << '$';
165 O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
166 << MO.getConstantPoolIndex();
167 if (X86PICStyle == PICStyle::Stub &&
168 TM.getRelocationModel() == Reloc::PIC_)
169 O << "-\"L" << getFunctionNumber() << "$pb\"";
170 int Offset = MO.getOffset();
176 if (Subtarget->is64Bit())
180 case MachineOperand::MO_GlobalAddress: {
181 bool isCallOp = Modifier && !strcmp(Modifier, "call");
182 bool isMemOp = Modifier && !strcmp(Modifier, "mem");
183 if (!isMemOp && !isCallOp) O << '$';
185 GlobalValue *GV = MO.getGlobal();
186 std::string Name = Mang->getValueName(GV);
188 bool isExt = (GV->isExternal() || GV->hasWeakLinkage() ||
189 GV->hasLinkOnceLinkage());
190 if (X86PICStyle == PICStyle::Stub &&
191 TM.getRelocationModel() != Reloc::Static) {
192 // Link-once, External, or Weakly-linked global variables need
193 // non-lazily-resolved stubs
195 // Dynamically-resolved functions need a stub for the function.
196 if (isCallOp && isa<Function>(GV)) {
197 FnStubs.insert(Name);
198 O << "L" << Name << "$stub";
200 GVStubs.insert(Name);
201 O << "L" << Name << "$non_lazy_ptr";
204 if (GV->hasDLLImportLinkage()) {
205 // FIXME: This should be fixed with full support of stdcall & fastcall
212 if (!isCallOp && TM.getRelocationModel() == Reloc::PIC_)
213 O << "-\"L" << getFunctionNumber() << "$pb\"";
215 if (GV->hasDLLImportLinkage()) {
216 // FIXME: This should be fixed with full support of stdcall & fastcall
224 int Offset = MO.getOffset();
231 Subtarget->is64Bit()) {
232 if (isExt && TM.getRelocationModel() != Reloc::Static)
239 case MachineOperand::MO_ExternalSymbol: {
240 bool isCallOp = Modifier && !strcmp(Modifier, "call");
242 X86PICStyle == PICStyle::Stub &&
243 TM.getRelocationModel() != Reloc::Static) {
244 std::string Name(TAI->getGlobalPrefix());
245 Name += MO.getSymbolName();
246 FnStubs.insert(Name);
247 O << "L" << Name << "$stub";
250 if (!isCallOp) O << '$';
251 O << TAI->getGlobalPrefix() << MO.getSymbolName();
254 Subtarget->is64Bit())
260 O << "<unknown operand type>"; return;
264 void X86ATTAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
265 unsigned char value = MI->getOperand(Op).getImmedValue();
266 assert(value <= 7 && "Invalid ssecc argument!");
268 case 0: O << "eq"; break;
269 case 1: O << "lt"; break;
270 case 2: O << "le"; break;
271 case 3: O << "unord"; break;
272 case 4: O << "neq"; break;
273 case 5: O << "nlt"; break;
274 case 6: O << "nle"; break;
275 case 7: O << "ord"; break;
279 void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
280 const char *Modifier){
281 assert(isMem(MI, Op) && "Invalid memory reference!");
283 const MachineOperand &BaseReg = MI->getOperand(Op);
284 int ScaleVal = MI->getOperand(Op+1).getImmedValue();
285 const MachineOperand &IndexReg = MI->getOperand(Op+2);
286 const MachineOperand &DispSpec = MI->getOperand(Op+3);
288 if (BaseReg.isFrameIndex()) {
289 O << "[frame slot #" << BaseReg.getFrameIndex();
290 if (DispSpec.getImmedValue())
291 O << " + " << DispSpec.getImmedValue();
296 if (DispSpec.isGlobalAddress() ||
297 DispSpec.isConstantPoolIndex() ||
298 DispSpec.isJumpTableIndex()) {
299 printOperand(MI, Op+3, "mem");
301 int DispVal = DispSpec.getImmedValue();
302 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
306 if (IndexReg.getReg() || BaseReg.getReg()) {
308 if (BaseReg.getReg()) {
309 printOperand(MI, Op, Modifier);
312 if (IndexReg.getReg()) {
314 printOperand(MI, Op+2, Modifier);
316 O << "," << ScaleVal;
323 void X86ATTAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) {
324 O << "\"L" << getFunctionNumber() << "$pb\"\n";
325 O << "\"L" << getFunctionNumber() << "$pb\":";
329 bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO,
331 const MRegisterInfo &RI = *TM.getRegisterInfo();
332 unsigned Reg = MO.getReg();
334 default: return true; // Unknown mode.
335 case 'b': // Print QImode register
336 Reg = getX86SubSuperRegister(Reg, MVT::i8);
338 case 'h': // Print QImode high register
339 Reg = getX86SubSuperRegister(Reg, MVT::i8, true);
341 case 'w': // Print HImode register
342 Reg = getX86SubSuperRegister(Reg, MVT::i16);
344 case 'k': // Print SImode register
345 Reg = getX86SubSuperRegister(Reg, MVT::i32);
350 for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
351 O << (char)tolower(*Name);
355 /// PrintAsmOperand - Print out an operand for an inline asm expression.
357 bool X86ATTAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
359 const char *ExtraCode) {
360 // Does this asm operand have a single letter operand modifier?
361 if (ExtraCode && ExtraCode[0]) {
362 if (ExtraCode[1] != 0) return true; // Unknown modifier.
364 switch (ExtraCode[0]) {
365 default: return true; // Unknown modifier.
366 case 'b': // Print QImode register
367 case 'h': // Print QImode high register
368 case 'w': // Print HImode register
369 case 'k': // Print SImode register
370 return printAsmMRegister(MI->getOperand(OpNo), ExtraCode[0]);
374 printOperand(MI, OpNo);
378 bool X86ATTAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
381 const char *ExtraCode) {
382 if (ExtraCode && ExtraCode[0])
383 return true; // Unknown modifier.
384 printMemReference(MI, OpNo);
388 /// printMachineInstruction -- Print out a single X86 LLVM instruction
389 /// MI in Intel syntax to the current output stream.
391 void X86ATTAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
394 // See if a truncate instruction can be turned into a nop.
395 switch (MI->getOpcode()) {
397 case X86::TRUNC_64to32:
398 case X86::TRUNC_64to16:
399 case X86::TRUNC_32to16:
400 case X86::TRUNC_32to8:
401 case X86::TRUNC_16to8:
402 case X86::TRUNC_32_to8:
403 case X86::TRUNC_16_to8: {
404 const MachineOperand &MO0 = MI->getOperand(0);
405 const MachineOperand &MO1 = MI->getOperand(1);
406 unsigned Reg0 = MO0.getReg();
407 unsigned Reg1 = MO1.getReg();
408 unsigned Opc = MI->getOpcode();
409 if (Opc == X86::TRUNC_64to32)
410 Reg1 = getX86SubSuperRegister(Reg1, MVT::i32);
411 else if (Opc == X86::TRUNC_32to16 || Opc == X86::TRUNC_64to16)
412 Reg1 = getX86SubSuperRegister(Reg1, MVT::i16);
414 Reg1 = getX86SubSuperRegister(Reg1, MVT::i8);
415 O << TAI->getCommentString() << " TRUNCATE ";
420 case X86::PsMOVZX64rr32:
421 O << TAI->getCommentString() << " ZERO-EXTEND " << "\n\t";
425 // Call the autogenerated instruction printer routines.
426 printInstruction(MI);
429 // Include the auto-generated portion of the assembly writer.
430 #include "X86GenAsmWriter.inc"