1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a target description file for the Intel i386 architecture, referred
11 // to here as the "X86" architecture.
13 //===----------------------------------------------------------------------===//
15 // Get the target-independent interfaces which we are implementing...
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // X86 Subtarget state
23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24 "64-bit mode (x86_64)">;
26 //===----------------------------------------------------------------------===//
27 // X86 Subtarget features
28 //===----------------------------------------------------------------------===//
30 def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
31 "Enable conditional move instructions">;
33 def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
34 "Support POPCNT instruction">;
37 def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
38 "Enable MMX instructions">;
39 def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
40 "Enable SSE instructions",
41 // SSE codegen depends on cmovs, and all
42 // SSE1+ processors support them.
43 [FeatureMMX, FeatureCMOV]>;
44 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
45 "Enable SSE2 instructions",
47 def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
48 "Enable SSE3 instructions",
50 def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
51 "Enable SSSE3 instructions",
53 def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
54 "Enable SSE 4.1 instructions",
56 def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
57 "Enable SSE 4.2 instructions",
59 def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
60 "Enable 3DNow! instructions",
62 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
63 "Enable 3DNow! Athlon instructions",
65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
67 // without disabling 64-bit mode.
68 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
69 "Support 64-bit instructions",
71 def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
72 "64-bit with cmpxchg16b",
74 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
75 "Bit testing of memory is slow">;
76 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
77 "IsUAMemFast", "true",
78 "Fast unaligned memory access">;
79 def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
80 "Support SSE 4a instructions",
83 def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX",
84 "Enable AVX instructions",
86 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
87 "Enable AVX2 instructions",
89 def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
90 "Enable packed carry-less multiplication instructions",
92 def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true",
93 "Enable three-operand fused multiple-add",
95 def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
96 "Enable four-operand fused multiple-add",
97 [FeatureAVX, FeatureSSE4A]>;
98 def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true",
99 "Enable XOP instructions",
101 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
102 "HasVectorUAMem", "true",
103 "Allow unaligned memory operands on vector/SIMD instructions">;
104 def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
105 "Enable AES instructions",
107 def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
108 "Support MOVBE instruction">;
109 def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true",
110 "Support RDRAND instruction">;
111 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
112 "Support 16-bit floating point conversion instructions">;
113 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
114 "Support FS/GS Base instructions">;
115 def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
116 "Support LZCNT instruction">;
117 def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
118 "Support BMI instructions">;
119 def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true",
120 "Support BMI2 instructions">;
121 def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true",
122 "Support RTM instructions">;
123 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
124 "Use LEA for adjusting the stack pointer">;
125 def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
126 "HasSlowDivide", "true",
127 "Use small divide for positive values less than 256">;
128 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
129 "PadShortFunctions", "true",
130 "Pad short functions">;
132 //===----------------------------------------------------------------------===//
133 // X86 processors supported.
134 //===----------------------------------------------------------------------===//
136 include "X86Schedule.td"
138 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
139 "Intel Atom processors">;
141 class Proc<string Name, list<SubtargetFeature> Features>
142 : ProcessorModel<Name, GenericModel, Features>;
144 class AtomProc<string Name, list<SubtargetFeature> Features>
145 : ProcessorModel<Name, AtomModel, Features>;
147 def : Proc<"generic", []>;
148 def : Proc<"i386", []>;
149 def : Proc<"i486", []>;
150 def : Proc<"i586", []>;
151 def : Proc<"pentium", []>;
152 def : Proc<"pentium-mmx", [FeatureMMX]>;
153 def : Proc<"i686", []>;
154 def : Proc<"pentiumpro", [FeatureCMOV]>;
155 def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
156 def : Proc<"pentium3", [FeatureSSE1]>;
157 def : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>;
158 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
159 def : Proc<"pentium4", [FeatureSSE2]>;
160 def : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>;
161 def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
163 def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
164 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
165 def : Proc<"nocona", [FeatureSSE3, FeatureCMPXCHG16B,
167 def : Proc<"core2", [FeatureSSSE3, FeatureCMPXCHG16B,
169 def : Proc<"penryn", [FeatureSSE41, FeatureCMPXCHG16B,
171 def : AtomProc<"atom", [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
172 FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
173 FeatureSlowDivide, FeaturePadShortFunctions]>;
174 // "Arrandale" along with corei3 and corei5
175 def : Proc<"corei7", [FeatureSSE42, FeatureCMPXCHG16B,
176 FeatureSlowBTMem, FeatureFastUAMem,
177 FeaturePOPCNT, FeatureAES]>;
178 def : Proc<"nehalem", [FeatureSSE42, FeatureCMPXCHG16B,
179 FeatureSlowBTMem, FeatureFastUAMem,
181 // Westmere is a similar machine to nehalem with some additional features.
182 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
183 def : Proc<"westmere", [FeatureSSE42, FeatureCMPXCHG16B,
184 FeatureSlowBTMem, FeatureFastUAMem,
185 FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
187 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
188 // rather than a superset.
189 def : Proc<"corei7-avx", [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
190 FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
192 def : Proc<"core-avx-i", [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
193 FeaturePOPCNT, FeatureAES, FeaturePCLMUL,
194 FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>;
197 def : Proc<"core-avx2", [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
198 FeaturePOPCNT, FeatureAES, FeaturePCLMUL,
199 FeatureRDRAND, FeatureF16C, FeatureFSGSBase,
200 FeatureMOVBE, FeatureLZCNT, FeatureBMI,
201 FeatureBMI2, FeatureFMA,
204 def : Proc<"k6", [FeatureMMX]>;
205 def : Proc<"k6-2", [Feature3DNow]>;
206 def : Proc<"k6-3", [Feature3DNow]>;
207 def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>;
208 def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>;
209 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
210 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
211 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
212 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
214 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
216 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
218 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
220 def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
222 def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
224 def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, FeatureCMPXCHG16B,
226 def : Proc<"amdfam10", [FeatureSSE4A,
227 Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
228 FeaturePOPCNT, FeatureSlowBTMem]>;
230 def : Proc<"btver1", [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
231 FeatureLZCNT, FeaturePOPCNT]>;
233 def : Proc<"bdver1", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
234 FeatureAES, FeaturePCLMUL,
235 FeatureLZCNT, FeaturePOPCNT]>;
236 // Enhanced Bulldozer
237 def : Proc<"bdver2", [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
238 FeatureAES, FeaturePCLMUL,
239 FeatureF16C, FeatureLZCNT,
240 FeaturePOPCNT, FeatureBMI, FeatureFMA]>;
241 def : Proc<"geode", [Feature3DNowA]>;
243 def : Proc<"winchip-c6", [FeatureMMX]>;
244 def : Proc<"winchip2", [Feature3DNow]>;
245 def : Proc<"c3", [Feature3DNow]>;
246 def : Proc<"c3-2", [FeatureSSE1]>;
248 //===----------------------------------------------------------------------===//
249 // Register File Description
250 //===----------------------------------------------------------------------===//
252 include "X86RegisterInfo.td"
254 //===----------------------------------------------------------------------===//
255 // Instruction Descriptions
256 //===----------------------------------------------------------------------===//
258 include "X86InstrInfo.td"
260 def X86InstrInfo : InstrInfo;
262 //===----------------------------------------------------------------------===//
263 // Calling Conventions
264 //===----------------------------------------------------------------------===//
266 include "X86CallingConv.td"
269 //===----------------------------------------------------------------------===//
271 //===----------------------------------------------------------------------===//
273 def ATTAsmParser : AsmParser {
274 string AsmParserClassName = "AsmParser";
277 def ATTAsmParserVariant : AsmParserVariant {
280 // Discard comments in assembly strings.
281 string CommentDelimiter = "#";
283 // Recognize hard coded registers.
284 string RegisterPrefix = "%";
287 def IntelAsmParserVariant : AsmParserVariant {
290 // Discard comments in assembly strings.
291 string CommentDelimiter = ";";
293 // Recognize hard coded registers.
294 string RegisterPrefix = "";
297 //===----------------------------------------------------------------------===//
299 //===----------------------------------------------------------------------===//
301 // The X86 target supports two different syntaxes for emitting machine code.
302 // This is controlled by the -x86-asm-syntax={att|intel}
303 def ATTAsmWriter : AsmWriter {
304 string AsmWriterClassName = "ATTInstPrinter";
306 bit isMCAsmWriter = 1;
308 def IntelAsmWriter : AsmWriter {
309 string AsmWriterClassName = "IntelInstPrinter";
311 bit isMCAsmWriter = 1;
315 // Information about the instructions...
316 let InstructionSet = X86InstrInfo;
317 let AssemblyParsers = [ATTAsmParser];
318 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
319 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];