lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40
  41 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  42                                       "Enable MMX instructions">;
  43 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  44                                       "Enable SSE instructions",
  45                                       // SSE codegen depends on cmovs, and all
  46                                       // SSE1+ processors support them.
  47                                       [FeatureMMX, FeatureCMOV]>;
  48 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  49                                       "Enable SSE2 instructions",
  50                                       [FeatureSSE1]>;
  51 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  52                                       "Enable SSE3 instructions",
  53                                       [FeatureSSE2]>;
  54 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  55                                       "Enable SSSE3 instructions",
  56                                       [FeatureSSE3]>;
  57 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  58                                       "Enable SSE 4.1 instructions",
  59                                       [FeatureSSSE3]>;
  60 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  61                                       "Enable SSE 4.2 instructions",
  62                                       [FeatureSSE41]>;
  63 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  64                                       "Enable 3DNow! instructions",
  65                                       [FeatureMMX]>;
  66 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  67                                       "Enable 3DNow! Athlon instructions",
  68                                       [Feature3DNow]>;
  69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  71 // without disabling 64-bit mode.
  72 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  73                                       "Support 64-bit instructions",
  74                                       [FeatureCMOV]>;
  75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  76                                       "64-bit with cmpxchg16b",
  77                                       [Feature64Bit]>;
  78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  79                                        "Bit testing of memory is slow">;
  80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  81                                        "SHLD instruction is slow">;
  82 // FIXME: This is a 16-byte (SSE/AVX) feature; we should rename it to make that
  83 // explicit. Also, it seems this would be the default state for most chips
  84 // going forward, so it would probably be better to negate the logic and
  85 // match the 32-byte "slow mem" feature below.
  86 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  87                                         "IsUAMemFast", "true",
  88                                         "Fast unaligned memory access">;
  89 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
  90                             "IsUAMem32Slow", "true",
  91                             "Slow unaligned 32-byte memory access">;
  92 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  93                                       "Support SSE 4a instructions",
  94                                       [FeatureSSE3]>;
  95
  96 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  97                                       "Enable AVX instructions",
  98                                       [FeatureSSE42]>;
  99 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 100                                       "Enable AVX2 instructions",
 101                                       [FeatureAVX]>;
 102 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 103                                       "Enable AVX-512 instructions",
 104                                       [FeatureAVX2]>;
 105 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 106                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 107                                       [FeatureAVX512]>;
 108 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 109                       "Enable AVX-512 Conflict Detection Instructions",
 110                                       [FeatureAVX512]>;
 111 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 112                       "Enable AVX-512 PreFetch Instructions",
 113                                       [FeatureAVX512]>;
 114 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 115                       "Enable AVX-512 Doubleword and Quadword Instructions",
 116                                       [FeatureAVX512]>;
 117 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 118                       "Enable AVX-512 Byte and Word Instructions",
 119                                       [FeatureAVX512]>;
 120 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 121                       "Enable AVX-512 Vector Length eXtensions",
 122                                       [FeatureAVX512]>;
 123 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 124                          "Enable packed carry-less multiplication instructions",
 125                                [FeatureSSE2]>;
 126 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 127                                       "Enable three-operand fused multiple-add",
 128                                       [FeatureAVX]>;
 129 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 130                                       "Enable four-operand fused multiple-add",
 131                                       [FeatureAVX, FeatureSSE4A]>;
 132 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 133                                       "Enable XOP instructions",
 134                                       [FeatureFMA4]>;
 135 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
 136                                           "HasVectorUAMem", "true",
 137                  "Allow unaligned memory operands on vector/SIMD instructions">;
 138 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 139                                       "Enable AES instructions",
 140                                       [FeatureSSE2]>;
 141 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 142                                       "Enable TBM instructions">;
 143 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 144                                       "Support MOVBE instruction">;
 145 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 146                                       "Support RDRAND instruction">;
 147 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 148                        "Support 16-bit floating point conversion instructions",
 149                        [FeatureAVX]>;
 150 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 151                                        "Support FS/GS Base instructions">;
 152 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 153                                       "Support LZCNT instruction">;
 154 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 155                                       "Support BMI instructions">;
 156 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 157                                       "Support BMI2 instructions">;
 158 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 159                                       "Support RTM instructions">;
 160 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 161                                       "Support HLE">;
 162 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 163                                       "Support ADX instructions">;
 164 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 165                                       "Enable SHA instructions",
 166                                       [FeatureSSE2]>;
 167 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
 168                                       "Support SGX instructions">;
 169 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 170                                       "Support PRFCHW instructions">;
 171 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 172                                       "Support RDSEED instruction">;
 173 def FeatureSMAP    : SubtargetFeature<"smap", "HasSMAP", "true",
 174                                       "Support SMAP instructions">;
 175 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 176                                      "Use LEA for adjusting the stack pointer">;
 177 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 178                                      "HasSlowDivide32", "true",
 179                                      "Use 8-bit divide for positive values less than 256">;
 180 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 181                                      "HasSlowDivide64", "true",
 182                                      "Use 16-bit divide for positive values less than 65536">;
 183 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 184                                      "PadShortFunctions", "true",
 185                                      "Pad short functions">;
 186 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 187                                      "CallRegIndirect", "true",
 188                                      "Call register indirect">;
 189 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 190                                    "LEA instruction needs inputs at AG stage">;
 191 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 192                                    "LEA instruction with certain arguments is slow">;
 193 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 194                                    "INC and DEC instructions are slower than ADD and SUB">;
 195 def FeatureUseSqrtEst : SubtargetFeature<"use-sqrt-est", "UseSqrtEst", "true",
 196                             "Use RSQRT* to optimize square root calculations">;
 197 def FeatureUseRecipEst : SubtargetFeature<"use-recip-est", "UseReciprocalEst",
 198                           "true", "Use RCP* to optimize division calculations">;
 199
 200 //===----------------------------------------------------------------------===//
 201 // X86 processors supported.
 202 //===----------------------------------------------------------------------===//
 203
 204 include "X86Schedule.td"
 205
 206 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 207                     "Intel Atom processors">;
 208 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 209                     "Intel Silvermont processors">;
 210
 211 class Proc<string Name, list<SubtargetFeature> Features>
 212  : ProcessorModel<Name, GenericModel, Features>;
 213
 214 def : Proc<"generic",         []>;
 215 def : Proc<"i386",            []>;
 216 def : Proc<"i486",            []>;
 217 def : Proc<"i586",            []>;
 218 def : Proc<"pentium",         []>;
 219 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 220 def : Proc<"i686",            []>;
 221 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 222 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 223 def : Proc<"pentium3",        [FeatureSSE1]>;
 224 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 225 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 226 def : Proc<"pentium4",        [FeatureSSE2]>;
 227 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 228
 229 // Intel Core Duo.
 230 def : ProcessorModel<"yonah", SandyBridgeModel,
 231                      [FeatureSSE3, FeatureSlowBTMem]>;
 232
 233 // NetBurst.
 234 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
 235 def : Proc<"nocona",   [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 236
 237 // Intel Core 2 Solo/Duo.
 238 def : ProcessorModel<"core2", SandyBridgeModel,
 239                      [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 240 def : ProcessorModel<"penryn", SandyBridgeModel,
 241                      [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 242
 243 // Atom.
 244 def : ProcessorModel<"atom", AtomModel,
 245                      [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
 246                       FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
 247                       FeatureSlowDivide32, FeatureSlowDivide64,
 248                       FeatureCallRegIndirect,
 249                       FeatureLEAUsesAG,
 250                       FeaturePadShortFunctions]>;
 251
 252 // Atom Silvermont.
 253 def : ProcessorModel<"slm",  SLMModel, [ProcIntelSLM,
 254                                FeatureSSE42, FeatureCMPXCHG16B,
 255                                FeatureMOVBE, FeaturePOPCNT,
 256                                FeaturePCLMUL, FeatureAES,
 257                                FeatureSlowDivide64,
 258                                FeatureCallRegIndirect,
 259                                FeaturePRFCHW,
 260                                FeatureSlowLEA, FeatureSlowIncDec,
 261                                FeatureSlowBTMem, FeatureFastUAMem]>;
 262 // "Arrandale" along with corei3 and corei5
 263 def : ProcessorModel<"corei7", SandyBridgeModel,
 264                      [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
 265                       FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>;
 266
 267 def : ProcessorModel<"nehalem", SandyBridgeModel,
 268                      [FeatureSSE42,  FeatureCMPXCHG16B, FeatureSlowBTMem,
 269                       FeatureFastUAMem, FeaturePOPCNT]>;
 270 // Westmere is a similar machine to nehalem with some additional features.
 271 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 272 def : ProcessorModel<"westmere", SandyBridgeModel,
 273                      [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
 274                       FeatureFastUAMem, FeaturePOPCNT, FeatureAES,
 275                       FeaturePCLMUL]>;
 276 // Sandy Bridge
 277 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 278 // rather than a superset.
 279 def : ProcessorModel<"corei7-avx", SandyBridgeModel,
 280                      [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
 281                       FeatureSlowUAMem32, FeaturePOPCNT, FeatureAES,
 282                       FeaturePCLMUL]>;
 283 // Ivy Bridge
 284 def : ProcessorModel<"core-avx-i", SandyBridgeModel,
 285                      [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
 286                       FeatureSlowUAMem32, FeaturePOPCNT, FeatureAES,
 287                       FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 288                       FeatureFSGSBase]>;
 289
 290 // Haswell
 291 def : ProcessorModel<"core-avx2", HaswellModel,
 292                      [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
 293                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
 294                       FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
 295                       FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
 296                       FeatureHLE, FeatureSlowIncDec]>;
 297
 298 // Broadwell
 299 def : ProcessorModel<"broadwell", HaswellModel,
 300                      [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
 301                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
 302                       FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
 303                       FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
 304                       FeatureHLE, FeatureADX, FeatureRDSEED, FeatureSMAP,
 305                       FeatureSlowIncDec]>;
 306 // KNL
 307 // FIXME: define KNL model
 308 def : ProcessorModel<"knl", HaswellModel,
 309                      [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
 310                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 311                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 312                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 313                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 314                       FeatureSlowIncDec]>;
 315
 316 // SKX
 317 // FIXME: define SKX model
 318 def : ProcessorModel<"skx", HaswellModel,
 319                      [FeatureAVX512, FeatureCDI,
 320                       FeatureDQI, FeatureBWI, FeatureVLX,
 321                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 322                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 323                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 324                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 325                       FeatureSlowIncDec, FeatureSGX]>;
 326
 327 def : Proc<"k6",              [FeatureMMX]>;
 328 def : Proc<"k6-2",            [Feature3DNow]>;
 329 def : Proc<"k6-3",            [Feature3DNow]>;
 330 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem,
 331                                FeatureSlowSHLD]>;
 332 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem,
 333                                FeatureSlowSHLD]>;
 334 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 335                                FeatureSlowSHLD]>;
 336 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 337                                FeatureSlowSHLD]>;
 338 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 339                                FeatureSlowSHLD]>;
 340 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 341                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 342 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 343                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 344 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 345                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 346 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 347                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 348 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 349                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 350 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 351                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 352 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 353                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 354 def : Proc<"amdfam10",        [FeatureSSE4A,
 355                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 356                                FeaturePOPCNT, FeatureSlowBTMem,
 357                                FeatureSlowSHLD]>;
 358 // Bobcat
 359 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
 360                                FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
 361                                FeatureSlowSHLD]>;
 362
 363 // Jaguar
 364 def : ProcessorModel<"btver2", BtVer2Model,
 365                      [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
 366                       FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
 367                       FeatureBMI, FeatureF16C, FeatureMOVBE,
 368                       FeatureLZCNT, FeaturePOPCNT, FeatureFastUAMem,
 369                       FeatureSlowSHLD, FeatureUseSqrtEst, FeatureUseRecipEst]>;
 370
 371 // TODO: We should probably add 'FeatureFastUAMem' to all of the AMD chips.
 372
 373 // Bulldozer
 374 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 375                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 376                                FeatureAVX, FeatureSSE4A, FeatureLZCNT,
 377                                FeaturePOPCNT, FeatureSlowSHLD]>;
 378 // Piledriver
 379 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 380                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 381                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 382                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 383                                FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
 384
 385 // Steamroller
 386 def : Proc<"bdver3",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 387                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 388                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 389                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 390                                FeatureTBM, FeatureFMA, FeatureSlowSHLD,
 391                                FeatureFSGSBase]>;
 392
 393 // Excavator
 394 def : Proc<"bdver4",          [FeatureAVX2, FeatureXOP, FeatureFMA4,
 395                                FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
 396                                FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
 397                                FeaturePOPCNT, FeatureBMI, FeatureBMI2,
 398                                FeatureTBM, FeatureFMA, FeatureSSE4A,
 399                                FeatureFSGSBase]>;
 400
 401 def : Proc<"geode",           [Feature3DNowA]>;
 402
 403 def : Proc<"winchip-c6",      [FeatureMMX]>;
 404 def : Proc<"winchip2",        [Feature3DNow]>;
 405 def : Proc<"c3",              [Feature3DNow]>;
 406 def : Proc<"c3-2",            [FeatureSSE1]>;
 407
 408 // We also provide a generic 64-bit specific x86 processor model which tries to
 409 // be good for modern chips without enabling instruction set encodings past the
 410 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 411 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 412 //
 413 // We currently use the Sandy Bridge model as the default scheduling model as
 414 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 415 // covers a huge swath of x86 processors. If there are specific scheduling
 416 // knobs which need to be tuned differently for AMD chips, we might consider
 417 // forming a common base for them.
 418 def : ProcessorModel<"x86-64", SandyBridgeModel,
 419                      [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
 420                       FeatureFastUAMem]>;
 421
 422 //===----------------------------------------------------------------------===//
 423 // Register File Description
 424 //===----------------------------------------------------------------------===//
 425
 426 include "X86RegisterInfo.td"
 427
 428 //===----------------------------------------------------------------------===//
 429 // Instruction Descriptions
 430 //===----------------------------------------------------------------------===//
 431
 432 include "X86InstrInfo.td"
 433
 434 def X86InstrInfo : InstrInfo;
 435
 436 //===----------------------------------------------------------------------===//
 437 // Calling Conventions
 438 //===----------------------------------------------------------------------===//
 439
 440 include "X86CallingConv.td"
 441
 442
 443 //===----------------------------------------------------------------------===//
 444 // Assembly Parser
 445 //===----------------------------------------------------------------------===//
 446
 447 def ATTAsmParser : AsmParser {
 448   string AsmParserClassName = "AsmParser";
 449 }
 450
 451 def ATTAsmParserVariant : AsmParserVariant {
 452   int Variant = 0;
 453
 454   // Variant name.
 455   string Name = "att";
 456
 457   // Discard comments in assembly strings.
 458   string CommentDelimiter = "#";
 459
 460   // Recognize hard coded registers.
 461   string RegisterPrefix = "%";
 462 }
 463
 464 def IntelAsmParserVariant : AsmParserVariant {
 465   int Variant = 1;
 466
 467   // Variant name.
 468   string Name = "intel";
 469
 470   // Discard comments in assembly strings.
 471   string CommentDelimiter = ";";
 472
 473   // Recognize hard coded registers.
 474   string RegisterPrefix = "";
 475 }
 476
 477 //===----------------------------------------------------------------------===//
 478 // Assembly Printers
 479 //===----------------------------------------------------------------------===//
 480
 481 // The X86 target supports two different syntaxes for emitting machine code.
 482 // This is controlled by the -x86-asm-syntax={att|intel}
 483 def ATTAsmWriter : AsmWriter {
 484   string AsmWriterClassName  = "ATTInstPrinter";
 485   int Variant = 0;
 486 }
 487 def IntelAsmWriter : AsmWriter {
 488   string AsmWriterClassName  = "IntelInstPrinter";
 489   int Variant = 1;
 490 }
 491
 492 def X86 : Target {
 493   // Information about the instructions...
 494   let InstructionSet = X86InstrInfo;
 495   let AssemblyParsers = [ATTAsmParser];
 496   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 497   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 498 }