lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25
  26 //===----------------------------------------------------------------------===//
  27 // X86 Subtarget features
  28 //===----------------------------------------------------------------------===//
  29
  30 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  31                                       "Enable conditional move instructions">;
  32
  33 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  34                                        "Support POPCNT instruction">;
  35
  36
  37 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  38                                       "Enable MMX instructions">;
  39 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  40                                       "Enable SSE instructions",
  41                                       // SSE codegen depends on cmovs, and all
  42                                       // SSE1+ processors support them.
  43                                       [FeatureMMX, FeatureCMOV]>;
  44 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  45                                       "Enable SSE2 instructions",
  46                                       [FeatureSSE1]>;
  47 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  48                                       "Enable SSE3 instructions",
  49                                       [FeatureSSE2]>;
  50 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  51                                       "Enable SSSE3 instructions",
  52                                       [FeatureSSE3]>;
  53 def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
  54                                       "Enable SSE 4.1 instructions",
  55                                       [FeatureSSSE3]>;
  56 def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
  57                                       "Enable SSE 4.2 instructions",
  58                                       [FeatureSSE41]>;
  59 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  60                                       "Enable 3DNow! instructions",
  61                                       [FeatureMMX]>;
  62 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  63                                       "Enable 3DNow! Athlon instructions",
  64                                       [Feature3DNow]>;
  65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  67 // without disabling 64-bit mode.
  68 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  69                                       "Support 64-bit instructions",
  70                                       [FeatureCMOV]>;
  71 def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
  72                                       "64-bit with cmpxchg16b",
  73                                       [Feature64Bit]>;
  74 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  75                                        "Bit testing of memory is slow">;
  76 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  77                                         "IsUAMemFast", "true",
  78                                         "Fast unaligned memory access">;
  79 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  80                                       "Support SSE 4a instructions",
  81                                       [FeatureSSE3]>;
  82
  83 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  84                                       "Enable AVX instructions",
  85                                       [FeatureSSE42]>;
  86 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
  87                                       "Enable AVX2 instructions",
  88                                       [FeatureAVX]>;
  89 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
  90                          "Enable packed carry-less multiplication instructions",
  91                                [FeatureSSE2]>;
  92 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
  93                                       "Enable three-operand fused multiple-add",
  94                                       [FeatureAVX]>;
  95 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
  96                                       "Enable four-operand fused multiple-add",
  97                                       [FeatureAVX, FeatureSSE4A]>;
  98 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
  99                                       "Enable XOP instructions",
 100                                       [FeatureFMA4]>;
 101 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
 102                                           "HasVectorUAMem", "true",
 103                  "Allow unaligned memory operands on vector/SIMD instructions">;
 104 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 105                                       "Enable AES instructions",
 106                                       [FeatureSSE2]>;
 107 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 108                                       "Support MOVBE instruction">;
 109 def FeatureRDRAND  : SubtargetFeature<"rdrand", "HasRDRAND", "true",
 110                                       "Support RDRAND instruction">;
 111 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 112                        "Support 16-bit floating point conversion instructions">;
 113 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 114                                        "Support FS/GS Base instructions">;
 115 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 116                                       "Support LZCNT instruction">;
 117 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 118                                       "Support BMI instructions">;
 119 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 120                                       "Support BMI2 instructions">;
 121 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 122                                       "Support RTM instructions">;
 123 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 124                                      "Use LEA for adjusting the stack pointer">;
 125 def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
 126                           "HasSlowDivide", "true",
 127                           "Use small divide for positive values less than 256">;
 128
 129 //===----------------------------------------------------------------------===//
 130 // X86 processors supported.
 131 //===----------------------------------------------------------------------===//
 132
 133 include "X86Schedule.td"
 134
 135 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 136                     "Intel Atom processors">;
 137
 138 class Proc<string Name, list<SubtargetFeature> Features>
 139  : ProcessorModel<Name, GenericModel, Features>;
 140
 141 class AtomProc<string Name, list<SubtargetFeature> Features>
 142  : ProcessorModel<Name, AtomModel, Features>;
 143
 144 def : Proc<"generic",         []>;
 145 def : Proc<"i386",            []>;
 146 def : Proc<"i486",            []>;
 147 def : Proc<"i586",            []>;
 148 def : Proc<"pentium",         []>;
 149 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 150 def : Proc<"i686",            []>;
 151 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 152 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 153 def : Proc<"pentium3",        [FeatureSSE1]>;
 154 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 155 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 156 def : Proc<"pentium4",        [FeatureSSE2]>;
 157 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 158 def : Proc<"x86-64",          [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
 159 def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
 160 def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
 161 def : Proc<"nocona",          [FeatureSSE3, FeatureCMPXCHG16B,
 162                                FeatureSlowBTMem]>;
 163 def : Proc<"core2",           [FeatureSSSE3, FeatureCMPXCHG16B,
 164                                FeatureSlowBTMem]>;
 165 def : Proc<"penryn",          [FeatureSSE41, FeatureCMPXCHG16B,
 166                                FeatureSlowBTMem]>;
 167 def : AtomProc<"atom",        [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
 168                                FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
 169                                FeatureSlowDivide]>;
 170 // "Arrandale" along with corei3 and corei5
 171 def : Proc<"corei7",          [FeatureSSE42, FeatureCMPXCHG16B,
 172                                FeatureSlowBTMem, FeatureFastUAMem,
 173                                FeaturePOPCNT, FeatureAES]>;
 174 def : Proc<"nehalem",         [FeatureSSE42,  FeatureCMPXCHG16B,
 175                                FeatureSlowBTMem, FeatureFastUAMem,
 176                                FeaturePOPCNT]>;
 177 // Westmere is a similar machine to nehalem with some additional features.
 178 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 179 def : Proc<"westmere",        [FeatureSSE42, FeatureCMPXCHG16B,
 180                                FeatureSlowBTMem, FeatureFastUAMem,
 181                                FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
 182 // Sandy Bridge
 183 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 184 // rather than a superset.
 185 def : Proc<"corei7-avx",      [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT,
 186                                FeatureAES, FeaturePCLMUL]>;
 187 // Ivy Bridge
 188 def : Proc<"core-avx-i",      [FeatureAVX, FeatureCMPXCHG16B, FeaturePOPCNT,
 189                                FeatureAES, FeaturePCLMUL,
 190                                FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>;
 191
 192 // Haswell
 193 def : Proc<"core-avx2",       [FeatureAVX2, FeatureCMPXCHG16B, FeaturePOPCNT,
 194                                FeatureAES, FeaturePCLMUL, FeatureRDRAND,
 195                                FeatureF16C, FeatureFSGSBase,
 196                                FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 197                                FeatureBMI2, FeatureFMA,
 198                                FeatureRTM]>;
 199
 200 def : Proc<"k6",              [FeatureMMX]>;
 201 def : Proc<"k6-2",            [Feature3DNow]>;
 202 def : Proc<"k6-3",            [Feature3DNow]>;
 203 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem]>;
 204 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem]>;
 205 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 206 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 207 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 208 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 209                                FeatureSlowBTMem]>;
 210 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 211                                FeatureSlowBTMem]>;
 212 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 213                                FeatureSlowBTMem]>;
 214 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 215                                FeatureSlowBTMem]>;
 216 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 217                                FeatureSlowBTMem]>;
 218 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 219                                FeatureSlowBTMem]>;
 220 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 221                                FeatureSlowBTMem]>;
 222 def : Proc<"amdfam10",        [FeatureSSE4A,
 223                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 224                                FeaturePOPCNT, FeatureSlowBTMem]>;
 225 // Bobcat
 226 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
 227                                FeatureLZCNT, FeaturePOPCNT]>;
 228 // Bulldozer
 229 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 230                                FeatureAES, FeaturePCLMUL,
 231                                FeatureLZCNT, FeaturePOPCNT]>;
 232 // Enhanced Bulldozer
 233 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 234                                FeatureAES, FeaturePCLMUL,
 235                                FeatureF16C, FeatureLZCNT,
 236                                FeaturePOPCNT, FeatureBMI, FeatureFMA]>;
 237 def : Proc<"geode",           [Feature3DNowA]>;
 238
 239 def : Proc<"winchip-c6",      [FeatureMMX]>;
 240 def : Proc<"winchip2",        [Feature3DNow]>;
 241 def : Proc<"c3",              [Feature3DNow]>;
 242 def : Proc<"c3-2",            [FeatureSSE1]>;
 243
 244 //===----------------------------------------------------------------------===//
 245 // Register File Description
 246 //===----------------------------------------------------------------------===//
 247
 248 include "X86RegisterInfo.td"
 249
 250 //===----------------------------------------------------------------------===//
 251 // Instruction Descriptions
 252 //===----------------------------------------------------------------------===//
 253
 254 include "X86InstrInfo.td"
 255
 256 def X86InstrInfo : InstrInfo;
 257
 258 //===----------------------------------------------------------------------===//
 259 // Calling Conventions
 260 //===----------------------------------------------------------------------===//
 261
 262 include "X86CallingConv.td"
 263
 264
 265 //===----------------------------------------------------------------------===//
 266 // Assembly Parser
 267 //===----------------------------------------------------------------------===//
 268
 269 def ATTAsmParser : AsmParser {
 270   string AsmParserClassName = "AsmParser";
 271 }
 272
 273 def ATTAsmParserVariant : AsmParserVariant {
 274   int Variant = 0;
 275
 276   // Discard comments in assembly strings.
 277   string CommentDelimiter = "#";
 278
 279   // Recognize hard coded registers.
 280   string RegisterPrefix = "%";
 281 }
 282
 283 def IntelAsmParserVariant : AsmParserVariant {
 284   int Variant = 1;
 285
 286   // Discard comments in assembly strings.
 287   string CommentDelimiter = ";";
 288
 289   // Recognize hard coded registers.
 290   string RegisterPrefix = "";
 291 }
 292
 293 //===----------------------------------------------------------------------===//
 294 // Assembly Printers
 295 //===----------------------------------------------------------------------===//
 296
 297 // The X86 target supports two different syntaxes for emitting machine code.
 298 // This is controlled by the -x86-asm-syntax={att|intel}
 299 def ATTAsmWriter : AsmWriter {
 300   string AsmWriterClassName  = "ATTInstPrinter";
 301   int Variant = 0;
 302   bit isMCAsmWriter = 1;
 303 }
 304 def IntelAsmWriter : AsmWriter {
 305   string AsmWriterClassName  = "IntelInstPrinter";
 306   int Variant = 1;
 307   bit isMCAsmWriter = 1;
 308 }
 309
 310 def X86 : Target {
 311   // Information about the instructions...
 312   let InstructionSet = X86InstrInfo;
 313   let AssemblyParsers = [ATTAsmParser];
 314   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 315   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 316 }