lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40
  41 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  42                                       "Enable MMX instructions">;
  43 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  44                                       "Enable SSE instructions",
  45                                       // SSE codegen depends on cmovs, and all
  46                                       // SSE1+ processors support them.
  47                                       [FeatureMMX, FeatureCMOV]>;
  48 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  49                                       "Enable SSE2 instructions",
  50                                       [FeatureSSE1]>;
  51 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  52                                       "Enable SSE3 instructions",
  53                                       [FeatureSSE2]>;
  54 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  55                                       "Enable SSSE3 instructions",
  56                                       [FeatureSSE3]>;
  57 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  58                                       "Enable SSE 4.1 instructions",
  59                                       [FeatureSSSE3]>;
  60 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  61                                       "Enable SSE 4.2 instructions",
  62                                       [FeatureSSE41]>;
  63 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  64                                       "Enable 3DNow! instructions",
  65                                       [FeatureMMX]>;
  66 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  67                                       "Enable 3DNow! Athlon instructions",
  68                                       [Feature3DNow]>;
  69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  71 // without disabling 64-bit mode.
  72 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  73                                       "Support 64-bit instructions",
  74                                       [FeatureCMOV]>;
  75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  76                                       "64-bit with cmpxchg16b",
  77                                       [Feature64Bit]>;
  78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  79                                        "Bit testing of memory is slow">;
  80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  81                                        "SHLD instruction is slow">;
  82 // FIXME: This should not apply to CPUs that do not have SSE.
  83 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
  84                                 "IsUAMem16Slow", "true",
  85                                 "Slow unaligned 16-byte memory access">;
  86 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
  87                                 "IsUAMem32Slow", "true",
  88                                 "Slow unaligned 32-byte memory access">;
  89 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  90                                       "Support SSE 4a instructions",
  91                                       [FeatureSSE3]>;
  92
  93 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  94                                       "Enable AVX instructions",
  95                                       [FeatureSSE42]>;
  96 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
  97                                       "Enable AVX2 instructions",
  98                                       [FeatureAVX]>;
  99 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 100                                       "Enable AVX-512 instructions",
 101                                       [FeatureAVX2]>;
 102 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 103                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 104                                       [FeatureAVX512]>;
 105 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 106                       "Enable AVX-512 Conflict Detection Instructions",
 107                                       [FeatureAVX512]>;
 108 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 109                       "Enable AVX-512 PreFetch Instructions",
 110                                       [FeatureAVX512]>;
 111 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 112                       "Enable AVX-512 Doubleword and Quadword Instructions",
 113                                       [FeatureAVX512]>;
 114 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 115                       "Enable AVX-512 Byte and Word Instructions",
 116                                       [FeatureAVX512]>;
 117 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 118                       "Enable AVX-512 Vector Length eXtensions",
 119                                       [FeatureAVX512]>;
 120 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 121                          "Enable packed carry-less multiplication instructions",
 122                                [FeatureSSE2]>;
 123 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 124                                       "Enable three-operand fused multiple-add",
 125                                       [FeatureAVX]>;
 126 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 127                                       "Enable four-operand fused multiple-add",
 128                                       [FeatureAVX, FeatureSSE4A]>;
 129 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 130                                       "Enable XOP instructions",
 131                                       [FeatureFMA4]>;
 132 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 133                                           "HasSSEUnalignedMem", "true",
 134                       "Allow unaligned memory operands with SSE instructions">;
 135 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 136                                       "Enable AES instructions",
 137                                       [FeatureSSE2]>;
 138 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 139                                       "Enable TBM instructions">;
 140 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 141                                       "Support MOVBE instruction">;
 142 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 143                                       "Support RDRAND instruction">;
 144 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 145                        "Support 16-bit floating point conversion instructions",
 146                        [FeatureAVX]>;
 147 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 148                                        "Support FS/GS Base instructions">;
 149 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 150                                       "Support LZCNT instruction">;
 151 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 152                                       "Support BMI instructions">;
 153 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 154                                       "Support BMI2 instructions">;
 155 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 156                                       "Support RTM instructions">;
 157 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 158                                       "Support HLE">;
 159 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 160                                       "Support ADX instructions">;
 161 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 162                                       "Enable SHA instructions",
 163                                       [FeatureSSE2]>;
 164 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 165                                       "Support PRFCHW instructions">;
 166 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 167                                       "Support RDSEED instruction">;
 168 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 169                                       "Support MPX instructions">;
 170 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 171                                      "Use LEA for adjusting the stack pointer">;
 172 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 173                                      "HasSlowDivide32", "true",
 174                                      "Use 8-bit divide for positive values less than 256">;
 175 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 176                                      "HasSlowDivide64", "true",
 177                                      "Use 16-bit divide for positive values less than 65536">;
 178 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 179                                      "PadShortFunctions", "true",
 180                                      "Pad short functions">;
 181 // TODO: This feature ought to be renamed.
 182 // What it really refers to are CPUs for which certain instructions
 183 // (which ones besides the example below?) are microcoded.
 184 // The best examples of this are the memory forms of CALL and PUSH
 185 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
 186 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 187                                      "CallRegIndirect", "true",
 188                                      "Call register indirect">;
 189 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 190                                    "LEA instruction needs inputs at AG stage">;
 191 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 192                                    "LEA instruction with certain arguments is slow">;
 193 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 194                                    "INC and DEC instructions are slower than ADD and SUB">;
 195 def FeatureSoftFloat
 196     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 197                        "Use software floating point features.">;
 198
 199 //===----------------------------------------------------------------------===//
 200 // X86 processors supported.
 201 //===----------------------------------------------------------------------===//
 202
 203 include "X86Schedule.td"
 204
 205 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 206                     "Intel Atom processors">;
 207 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 208                     "Intel Silvermont processors">;
 209
 210 class Proc<string Name, list<SubtargetFeature> Features>
 211  : ProcessorModel<Name, GenericModel, Features>;
 212
 213 def : Proc<"generic",         [FeatureSlowUAMem16]>;
 214 def : Proc<"i386",            [FeatureSlowUAMem16]>;
 215 def : Proc<"i486",            [FeatureSlowUAMem16]>;
 216 def : Proc<"i586",            [FeatureSlowUAMem16]>;
 217 def : Proc<"pentium",         [FeatureSlowUAMem16]>;
 218 def : Proc<"pentium-mmx",     [FeatureSlowUAMem16, FeatureMMX]>;
 219 def : Proc<"i686",            [FeatureSlowUAMem16]>;
 220 def : Proc<"pentiumpro",      [FeatureSlowUAMem16, FeatureCMOV]>;
 221 def : Proc<"pentium2",        [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV]>;
 222 def : Proc<"pentium3",        [FeatureSlowUAMem16, FeatureSSE1]>;
 223 def : Proc<"pentium3m",       [FeatureSlowUAMem16, FeatureSSE1,
 224                                FeatureSlowBTMem]>;
 225 def : Proc<"pentium-m",       [FeatureSlowUAMem16, FeatureSSE2,
 226                                FeatureSlowBTMem]>;
 227 def : Proc<"pentium4",        [FeatureSlowUAMem16, FeatureSSE2]>;
 228 def : Proc<"pentium4m",       [FeatureSlowUAMem16, FeatureSSE2,
 229                                FeatureSlowBTMem]>;
 230
 231 // Intel Core Duo.
 232 def : ProcessorModel<"yonah", SandyBridgeModel,
 233                      [FeatureSlowUAMem16, FeatureSSE3, FeatureSlowBTMem]>;
 234
 235 // NetBurst.
 236 def : Proc<"prescott", [FeatureSlowUAMem16, FeatureSSE3, FeatureSlowBTMem]>;
 237 def : Proc<"nocona",   [FeatureSlowUAMem16, FeatureSSE3, FeatureCMPXCHG16B,
 238                         FeatureSlowBTMem]>;
 239
 240 // Intel Core 2 Solo/Duo.
 241 def : ProcessorModel<"core2", SandyBridgeModel,
 242                      [FeatureSlowUAMem16, FeatureSSSE3, FeatureCMPXCHG16B,
 243                       FeatureSlowBTMem]>;
 244 def : ProcessorModel<"penryn", SandyBridgeModel,
 245                      [FeatureSlowUAMem16, FeatureSSE41, FeatureCMPXCHG16B,
 246                       FeatureSlowBTMem]>;
 247
 248 // Atom CPUs.
 249 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 250                                    ProcIntelAtom,
 251                                    FeatureSlowUAMem16,
 252                                    FeatureSSSE3,
 253                                    FeatureCMPXCHG16B,
 254                                    FeatureMOVBE,
 255                                    FeatureSlowBTMem,
 256                                    FeatureLeaForSP,
 257                                    FeatureSlowDivide32,
 258                                    FeatureSlowDivide64,
 259                                    FeatureCallRegIndirect,
 260                                    FeatureLEAUsesAG,
 261                                    FeaturePadShortFunctions
 262                                  ]>;
 263 def : BonnellProc<"bonnell">;
 264 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 265
 266 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 267                                       ProcIntelSLM,
 268                                       FeatureSSE42,
 269                                       FeatureCMPXCHG16B,
 270                                       FeatureMOVBE,
 271                                       FeaturePOPCNT,
 272                                       FeaturePCLMUL,
 273                                       FeatureAES,
 274                                       FeatureSlowDivide64,
 275                                       FeatureCallRegIndirect,
 276                                       FeaturePRFCHW,
 277                                       FeatureSlowLEA,
 278                                       FeatureSlowIncDec,
 279                                       FeatureSlowBTMem
 280                                     ]>;
 281 def : SilvermontProc<"silvermont">;
 282 def : SilvermontProc<"slm">; // Legacy alias.
 283
 284 // "Arrandale" along with corei3 and corei5
 285 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 286                                    FeatureSSE42,
 287                                    FeatureCMPXCHG16B,
 288                                    FeatureSlowBTMem,
 289                                    FeaturePOPCNT
 290                                  ]>;
 291 def : NehalemProc<"nehalem">;
 292 def : NehalemProc<"corei7">;
 293
 294 // Westmere is a similar machine to nehalem with some additional features.
 295 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 296 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 297                                     FeatureSSE42,
 298                                     FeatureCMPXCHG16B,
 299                                     FeatureSlowBTMem,
 300                                     FeaturePOPCNT,
 301                                     FeatureAES,
 302                                     FeaturePCLMUL
 303                                   ]>;
 304 def : WestmereProc<"westmere">;
 305
 306 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 307 // rather than a superset.
 308 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 309                                        FeatureAVX,
 310                                        FeatureCMPXCHG16B,
 311                                        FeatureSlowBTMem,
 312                                        FeatureSlowUAMem32,
 313                                        FeaturePOPCNT,
 314                                        FeatureAES,
 315                                        FeaturePCLMUL
 316                                      ]>;
 317 def : SandyBridgeProc<"sandybridge">;
 318 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 319
 320 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 321                                      FeatureAVX,
 322                                      FeatureCMPXCHG16B,
 323                                      FeatureSlowBTMem,
 324                                      FeatureSlowUAMem32,
 325                                      FeaturePOPCNT,
 326                                      FeatureAES,
 327                                      FeaturePCLMUL,
 328                                      FeatureRDRAND,
 329                                      FeatureF16C,
 330                                      FeatureFSGSBase
 331                                    ]>;
 332 def : IvyBridgeProc<"ivybridge">;
 333 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 334
 335 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 336                                    FeatureAVX2,
 337                                    FeatureCMPXCHG16B,
 338                                    FeatureSlowBTMem,
 339                                    FeaturePOPCNT,
 340                                    FeatureAES,
 341                                    FeaturePCLMUL,
 342                                    FeatureRDRAND,
 343                                    FeatureF16C,
 344                                    FeatureFSGSBase,
 345                                    FeatureMOVBE,
 346                                    FeatureLZCNT,
 347                                    FeatureBMI,
 348                                    FeatureBMI2,
 349                                    FeatureFMA,
 350                                    FeatureRTM,
 351                                    FeatureHLE,
 352                                    FeatureSlowIncDec
 353                                  ]>;
 354 def : HaswellProc<"haswell">;
 355 def : HaswellProc<"core-avx2">; // Legacy alias.
 356
 357 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 358                                      FeatureAVX2,
 359                                      FeatureCMPXCHG16B,
 360                                      FeatureSlowBTMem,
 361                                      FeaturePOPCNT,
 362                                      FeatureAES,
 363                                      FeaturePCLMUL,
 364                                      FeatureRDRAND,
 365                                      FeatureF16C,
 366                                      FeatureFSGSBase,
 367                                      FeatureMOVBE,
 368                                      FeatureLZCNT,
 369                                      FeatureBMI,
 370                                      FeatureBMI2,
 371                                      FeatureFMA,
 372                                      FeatureRTM,
 373                                      FeatureHLE,
 374                                      FeatureADX,
 375                                      FeatureRDSEED,
 376                                      FeatureSlowIncDec
 377                                    ]>;
 378 def : BroadwellProc<"broadwell">;
 379
 380 // FIXME: define KNL model
 381 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
 382                      [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
 383                       FeatureCMPXCHG16B, FeaturePOPCNT,
 384                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 385                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 386                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 387                       FeatureSlowIncDec, FeatureMPX]>;
 388 def : KnightsLandingProc<"knl">;
 389
 390 // FIXME: define SKX model
 391 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
 392                      [FeatureAVX512, FeatureCDI,
 393                       FeatureDQI, FeatureBWI, FeatureVLX,
 394                       FeatureCMPXCHG16B, FeatureSlowBTMem,
 395                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
 396                       FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
 397                       FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
 398                       FeatureHLE, FeatureADX, FeatureRDSEED, FeatureSlowIncDec,
 399                       FeatureMPX]>;
 400 def : SkylakeProc<"skylake">;
 401 def : SkylakeProc<"skx">; // Legacy alias.
 402
 403
 404 // AMD CPUs.
 405
 406 def : Proc<"k6",              [FeatureSlowUAMem16, FeatureMMX]>;
 407 def : Proc<"k6-2",            [FeatureSlowUAMem16, Feature3DNow]>;
 408 def : Proc<"k6-3",            [FeatureSlowUAMem16, Feature3DNow]>;
 409 def : Proc<"athlon",          [FeatureSlowUAMem16, Feature3DNowA,
 410                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 411 def : Proc<"athlon-tbird",    [FeatureSlowUAMem16, Feature3DNowA,
 412                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 413 def : Proc<"athlon-4",        [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 414                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 415 def : Proc<"athlon-xp",       [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 416                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 417 def : Proc<"athlon-mp",       [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 418                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 419 def : Proc<"k8",              [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
 420                                Feature64Bit, FeatureSlowBTMem,
 421                                FeatureSlowSHLD]>;
 422 def : Proc<"opteron",         [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
 423                                Feature64Bit, FeatureSlowBTMem,
 424                                FeatureSlowSHLD]>;
 425 def : Proc<"athlon64",        [FeatureSlowUAMem16, FeatureSSE2,   Feature3DNowA,
 426                                Feature64Bit, FeatureSlowBTMem,
 427                                FeatureSlowSHLD]>;
 428 def : Proc<"athlon-fx",       [FeatureSlowUAMem16, FeatureSSE2,   Feature3DNowA,
 429                                Feature64Bit, FeatureSlowBTMem,
 430                                FeatureSlowSHLD]>;
 431 def : Proc<"k8-sse3",         [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 432                                FeatureCMPXCHG16B, FeatureSlowBTMem,
 433                                FeatureSlowSHLD]>;
 434 def : Proc<"opteron-sse3",    [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 435                                FeatureCMPXCHG16B, FeatureSlowBTMem,
 436                                FeatureSlowSHLD]>;
 437 def : Proc<"athlon64-sse3",   [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 438                                FeatureCMPXCHG16B, FeatureSlowBTMem,
 439                                FeatureSlowSHLD]>;
 440 def : Proc<"amdfam10",        [FeatureSSE4A,
 441                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 442                                FeaturePOPCNT, FeatureSlowBTMem,
 443                                FeatureSlowSHLD]>;
 444 def : Proc<"barcelona",       [FeatureSSE4A,
 445                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 446                                FeaturePOPCNT, FeatureSlowBTMem,
 447                                FeatureSlowSHLD]>;
 448
 449 // Bobcat
 450 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
 451                                FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
 452                                FeatureSlowSHLD]>;
 453
 454 // Jaguar
 455 def : ProcessorModel<"btver2", BtVer2Model,
 456                      [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
 457                       FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
 458                       FeatureBMI, FeatureF16C, FeatureMOVBE,
 459                       FeatureLZCNT, FeaturePOPCNT,
 460                       FeatureSlowSHLD]>;
 461
 462 // Bulldozer
 463 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 464                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 465                                FeatureAVX, FeatureSSE4A, FeatureLZCNT,
 466                                FeaturePOPCNT, FeatureSlowSHLD]>;
 467 // Piledriver
 468 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 469                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 470                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 471                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 472                                FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
 473
 474 // Steamroller
 475 def : Proc<"bdver3",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 476                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 477                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 478                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 479                                FeatureTBM, FeatureFMA, FeatureSlowSHLD,
 480                                FeatureFSGSBase]>;
 481
 482 // Excavator
 483 def : Proc<"bdver4",          [FeatureAVX2, FeatureXOP, FeatureFMA4,
 484                                FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
 485                                FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
 486                                FeaturePOPCNT, FeatureBMI, FeatureBMI2,
 487                                FeatureTBM, FeatureFMA, FeatureSSE4A,
 488                                FeatureFSGSBase]>;
 489
 490 def : Proc<"geode",           [FeatureSlowUAMem16, Feature3DNowA]>;
 491
 492 def : Proc<"winchip-c6",      [FeatureSlowUAMem16, FeatureMMX]>;
 493 def : Proc<"winchip2",        [FeatureSlowUAMem16, Feature3DNow]>;
 494 def : Proc<"c3",              [FeatureSlowUAMem16, Feature3DNow]>;
 495 def : Proc<"c3-2",            [FeatureSlowUAMem16, FeatureSSE1]>;
 496
 497 // We also provide a generic 64-bit specific x86 processor model which tries to
 498 // be good for modern chips without enabling instruction set encodings past the
 499 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 500 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 501 //
 502 // We currently use the Sandy Bridge model as the default scheduling model as
 503 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 504 // covers a huge swath of x86 processors. If there are specific scheduling
 505 // knobs which need to be tuned differently for AMD chips, we might consider
 506 // forming a common base for them.
 507 def : ProcessorModel<"x86-64", SandyBridgeModel,
 508                      [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
 509
 510 //===----------------------------------------------------------------------===//
 511 // Register File Description
 512 //===----------------------------------------------------------------------===//
 513
 514 include "X86RegisterInfo.td"
 515
 516 //===----------------------------------------------------------------------===//
 517 // Instruction Descriptions
 518 //===----------------------------------------------------------------------===//
 519
 520 include "X86InstrInfo.td"
 521
 522 def X86InstrInfo : InstrInfo;
 523
 524 //===----------------------------------------------------------------------===//
 525 // Calling Conventions
 526 //===----------------------------------------------------------------------===//
 527
 528 include "X86CallingConv.td"
 529
 530
 531 //===----------------------------------------------------------------------===//
 532 // Assembly Parser
 533 //===----------------------------------------------------------------------===//
 534
 535 def ATTAsmParser : AsmParser {
 536   string AsmParserClassName = "AsmParser";
 537 }
 538
 539 def ATTAsmParserVariant : AsmParserVariant {
 540   int Variant = 0;
 541
 542   // Variant name.
 543   string Name = "att";
 544
 545   // Discard comments in assembly strings.
 546   string CommentDelimiter = "#";
 547
 548   // Recognize hard coded registers.
 549   string RegisterPrefix = "%";
 550 }
 551
 552 def IntelAsmParserVariant : AsmParserVariant {
 553   int Variant = 1;
 554
 555   // Variant name.
 556   string Name = "intel";
 557
 558   // Discard comments in assembly strings.
 559   string CommentDelimiter = ";";
 560
 561   // Recognize hard coded registers.
 562   string RegisterPrefix = "";
 563 }
 564
 565 //===----------------------------------------------------------------------===//
 566 // Assembly Printers
 567 //===----------------------------------------------------------------------===//
 568
 569 // The X86 target supports two different syntaxes for emitting machine code.
 570 // This is controlled by the -x86-asm-syntax={att|intel}
 571 def ATTAsmWriter : AsmWriter {
 572   string AsmWriterClassName  = "ATTInstPrinter";
 573   int Variant = 0;
 574 }
 575 def IntelAsmWriter : AsmWriter {
 576   string AsmWriterClassName  = "IntelInstPrinter";
 577   int Variant = 1;
 578 }
 579
 580 def X86 : Target {
 581   // Information about the instructions...
 582   let InstructionSet = X86InstrInfo;
 583   let AssemblyParsers = [ATTAsmParser];
 584   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 585   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 586 }