lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40
  41 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  42                                       "Enable MMX instructions">;
  43 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  44                                       "Enable SSE instructions",
  45                                       // SSE codegen depends on cmovs, and all
  46                                       // SSE1+ processors support them.
  47                                       [FeatureMMX, FeatureCMOV]>;
  48 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  49                                       "Enable SSE2 instructions",
  50                                       [FeatureSSE1]>;
  51 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  52                                       "Enable SSE3 instructions",
  53                                       [FeatureSSE2]>;
  54 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  55                                       "Enable SSSE3 instructions",
  56                                       [FeatureSSE3]>;
  57 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  58                                       "Enable SSE 4.1 instructions",
  59                                       [FeatureSSSE3]>;
  60 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  61                                       "Enable SSE 4.2 instructions",
  62                                       [FeatureSSE41]>;
  63 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  64                                       "Enable 3DNow! instructions",
  65                                       [FeatureMMX]>;
  66 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  67                                       "Enable 3DNow! Athlon instructions",
  68                                       [Feature3DNow]>;
  69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  71 // without disabling 64-bit mode.
  72 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  73                                       "Support 64-bit instructions",
  74                                       [FeatureCMOV]>;
  75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  76                                       "64-bit with cmpxchg16b",
  77                                       [Feature64Bit]>;
  78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  79                                        "Bit testing of memory is slow">;
  80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  81                                        "SHLD instruction is slow">;
  82 // FIXME: This is a 16-byte (SSE/AVX) feature; we should rename it to make that
  83 // explicit. Also, it seems this would be the default state for most chips
  84 // going forward, so it would probably be better to negate the logic and
  85 // match the 32-byte "slow mem" feature below.
  86 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  87                                         "IsUAMemFast", "true",
  88                                         "Fast unaligned memory access">;
  89 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
  90                             "IsUAMem32Slow", "true",
  91                             "Slow unaligned 32-byte memory access">;
  92 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  93                                       "Support SSE 4a instructions",
  94                                       [FeatureSSE3]>;
  95
  96 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  97                                       "Enable AVX instructions",
  98                                       [FeatureSSE42]>;
  99 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 100                                       "Enable AVX2 instructions",
 101                                       [FeatureAVX]>;
 102 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 103                                       "Enable AVX-512 instructions",
 104                                       [FeatureAVX2]>;
 105 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 106                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 107                                       [FeatureAVX512]>;
 108 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 109                       "Enable AVX-512 Conflict Detection Instructions",
 110                                       [FeatureAVX512]>;
 111 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 112                       "Enable AVX-512 PreFetch Instructions",
 113                                       [FeatureAVX512]>;
 114 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 115                       "Enable AVX-512 Doubleword and Quadword Instructions",
 116                                       [FeatureAVX512]>;
 117 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 118                       "Enable AVX-512 Byte and Word Instructions",
 119                                       [FeatureAVX512]>;
 120 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 121                       "Enable AVX-512 Vector Length eXtensions",
 122                                       [FeatureAVX512]>;
 123 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 124                          "Enable packed carry-less multiplication instructions",
 125                                [FeatureSSE2]>;
 126 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 127                                       "Enable three-operand fused multiple-add",
 128                                       [FeatureAVX]>;
 129 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 130                                       "Enable four-operand fused multiple-add",
 131                                       [FeatureAVX, FeatureSSE4A]>;
 132 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 133                                       "Enable XOP instructions",
 134                                       [FeatureFMA4]>;
 135 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 136                                           "HasSSEUnalignedMem", "true",
 137                       "Allow unaligned memory operands with SSE instructions">;
 138 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 139                                       "Enable AES instructions",
 140                                       [FeatureSSE2]>;
 141 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 142                                       "Enable TBM instructions">;
 143 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 144                                       "Support MOVBE instruction">;
 145 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 146                                       "Support RDRAND instruction">;
 147 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 148                        "Support 16-bit floating point conversion instructions",
 149                        [FeatureAVX]>;
 150 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 151                                        "Support FS/GS Base instructions">;
 152 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 153                                       "Support LZCNT instruction">;
 154 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 155                                       "Support BMI instructions">;
 156 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 157                                       "Support BMI2 instructions">;
 158 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 159                                       "Support RTM instructions">;
 160 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 161                                       "Support HLE">;
 162 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 163                                       "Support ADX instructions">;
 164 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 165                                       "Enable SHA instructions",
 166                                       [FeatureSSE2]>;
 167 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 168                                       "Support PRFCHW instructions">;
 169 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 170                                       "Support RDSEED instruction">;
 171 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 172                                      "Use LEA for adjusting the stack pointer">;
 173 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 174                                      "HasSlowDivide32", "true",
 175                                      "Use 8-bit divide for positive values less than 256">;
 176 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 177                                      "HasSlowDivide64", "true",
 178                                      "Use 16-bit divide for positive values less than 65536">;
 179 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 180                                      "PadShortFunctions", "true",
 181                                      "Pad short functions">;
 182 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 183                                      "CallRegIndirect", "true",
 184                                      "Call register indirect">;
 185 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 186                                    "LEA instruction needs inputs at AG stage">;
 187 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 188                                    "LEA instruction with certain arguments is slow">;
 189 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 190                                    "INC and DEC instructions are slower than ADD and SUB">;
 191 def FeatureSoftFloat
 192     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 193                        "Use software floating point features.">;
 194
 195 //===----------------------------------------------------------------------===//
 196 // X86 processors supported.
 197 //===----------------------------------------------------------------------===//
 198
 199 include "X86Schedule.td"
 200
 201 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 202                     "Intel Atom processors">;
 203 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 204                     "Intel Silvermont processors">;
 205
 206 class Proc<string Name, list<SubtargetFeature> Features>
 207  : ProcessorModel<Name, GenericModel, Features>;
 208
 209 def : Proc<"generic",         []>;
 210 def : Proc<"i386",            []>;
 211 def : Proc<"i486",            []>;
 212 def : Proc<"i586",            []>;
 213 def : Proc<"pentium",         []>;
 214 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 215 def : Proc<"i686",            []>;
 216 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 217 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 218 def : Proc<"pentium3",        [FeatureSSE1]>;
 219 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 220 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 221 def : Proc<"pentium4",        [FeatureSSE2]>;
 222 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 223
 224 // Intel Core Duo.
 225 def : ProcessorModel<"yonah", SandyBridgeModel,
 226                      [FeatureSSE3, FeatureSlowBTMem]>;
 227
 228 // NetBurst.
 229 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
 230 def : Proc<"nocona",   [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 231
 232 // Intel Core 2 Solo/Duo.
 233 def : ProcessorModel<"core2", SandyBridgeModel,
 234                      [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 235 def : ProcessorModel<"penryn", SandyBridgeModel,
 236                      [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 237
 238 // Atom CPUs.
 239 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 240                                    ProcIntelAtom,
 241                                    FeatureSSSE3,
 242                                    FeatureCMPXCHG16B,
 243                                    FeatureMOVBE,
 244                                    FeatureSlowBTMem,
 245                                    FeatureLeaForSP,
 246                                    FeatureSlowDivide32,
 247                                    FeatureSlowDivide64,
 248                                    FeatureCallRegIndirect,
 249                                    FeatureLEAUsesAG,
 250                                    FeaturePadShortFunctions
 251                                  ]>;
 252 def : BonnellProc<"bonnell">;
 253 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 254
 255 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 256                                       ProcIntelSLM,
 257                                       FeatureSSE42,
 258                                       FeatureCMPXCHG16B,
 259                                       FeatureMOVBE,
 260                                       FeaturePOPCNT,
 261                                       FeaturePCLMUL,
 262                                       FeatureAES,
 263                                       FeatureSlowDivide64,
 264                                       FeatureCallRegIndirect,
 265                                       FeaturePRFCHW,
 266                                       FeatureSlowLEA,
 267                                       FeatureSlowIncDec,
 268                                       FeatureSlowBTMem,
 269                                       FeatureFastUAMem
 270                                     ]>;
 271 def : SilvermontProc<"silvermont">;
 272 def : SilvermontProc<"slm">; // Legacy alias.
 273
 274 // "Arrandale" along with corei3 and corei5
 275 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 276                                    FeatureSSE42,
 277                                    FeatureCMPXCHG16B,
 278                                    FeatureSlowBTMem,
 279                                    FeatureFastUAMem,
 280                                    FeaturePOPCNT
 281                                  ]>;
 282 def : NehalemProc<"nehalem">;
 283 def : NehalemProc<"corei7">;
 284
 285 // Westmere is a similar machine to nehalem with some additional features.
 286 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 287 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 288                                     FeatureSSE42,
 289                                     FeatureCMPXCHG16B,
 290                                     FeatureSlowBTMem,
 291                                     FeatureFastUAMem,
 292                                     FeaturePOPCNT,
 293                                     FeatureAES,
 294                                     FeaturePCLMUL
 295                                   ]>;
 296 def : WestmereProc<"westmere">;
 297
 298 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 299 // rather than a superset.
 300 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 301                                        FeatureAVX,
 302                                        FeatureCMPXCHG16B,
 303                                        FeatureFastUAMem,
 304                                        FeatureSlowUAMem32,
 305                                        FeaturePOPCNT,
 306                                        FeatureAES,
 307                                        FeaturePCLMUL
 308                                      ]>;
 309 def : SandyBridgeProc<"sandybridge">;
 310 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 311
 312 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 313                                      FeatureAVX,
 314                                      FeatureCMPXCHG16B,
 315                                      FeatureFastUAMem,
 316                                      FeatureSlowUAMem32,
 317                                      FeaturePOPCNT,
 318                                      FeatureAES,
 319                                      FeaturePCLMUL,
 320                                      FeatureRDRAND,
 321                                      FeatureF16C,
 322                                      FeatureFSGSBase
 323                                    ]>;
 324 def : IvyBridgeProc<"ivybridge">;
 325 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 326
 327 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 328                                    FeatureAVX2,
 329                                    FeatureCMPXCHG16B,
 330                                    FeatureFastUAMem,
 331                                    FeaturePOPCNT,
 332                                    FeatureAES,
 333                                    FeaturePCLMUL,
 334                                    FeatureRDRAND,
 335                                    FeatureF16C,
 336                                    FeatureFSGSBase,
 337                                    FeatureMOVBE,
 338                                    FeatureLZCNT,
 339                                    FeatureBMI,
 340                                    FeatureBMI2,
 341                                    FeatureFMA,
 342                                    FeatureRTM,
 343                                    FeatureHLE,
 344                                    FeatureSlowIncDec
 345                                  ]>;
 346 def : HaswellProc<"haswell">;
 347 def : HaswellProc<"core-avx2">; // Legacy alias.
 348
 349 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 350                                      FeatureAVX2,
 351                                      FeatureCMPXCHG16B,
 352                                      FeatureFastUAMem,
 353                                      FeaturePOPCNT,
 354                                      FeatureAES,
 355                                      FeaturePCLMUL,
 356                                      FeatureRDRAND,
 357                                      FeatureF16C,
 358                                      FeatureFSGSBase,
 359                                      FeatureMOVBE,
 360                                      FeatureLZCNT,
 361                                      FeatureBMI,
 362                                      FeatureBMI2,
 363                                      FeatureFMA,
 364                                      FeatureRTM,
 365                                      FeatureHLE,
 366                                      FeatureADX,
 367                                      FeatureRDSEED,
 368                                      FeatureSlowIncDec
 369                                    ]>;
 370 def : BroadwellProc<"broadwell">;
 371
 372 // FIXME: define KNL model
 373 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
 374                      [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
 375                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 376                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 377                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 378                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 379                       FeatureSlowIncDec]>;
 380 def : KnightsLandingProc<"knl">;
 381
 382 // FIXME: define SKX model
 383 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
 384                      [FeatureAVX512, FeatureCDI,
 385                       FeatureDQI, FeatureBWI, FeatureVLX,
 386                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 387                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 388                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 389                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 390                       FeatureSlowIncDec]>;
 391 def : SkylakeProc<"skylake">;
 392 def : SkylakeProc<"skx">; // Legacy alias.
 393
 394
 395 // AMD CPUs.
 396
 397 def : Proc<"k6",              [FeatureMMX]>;
 398 def : Proc<"k6-2",            [Feature3DNow]>;
 399 def : Proc<"k6-3",            [Feature3DNow]>;
 400 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem,
 401                                FeatureSlowSHLD]>;
 402 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem,
 403                                FeatureSlowSHLD]>;
 404 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 405                                FeatureSlowSHLD]>;
 406 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 407                                FeatureSlowSHLD]>;
 408 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 409                                FeatureSlowSHLD]>;
 410 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 411                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 412 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 413                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 414 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 415                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 416 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 417                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 418 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 419                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 420 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 421                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 422 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 423                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 424 def : Proc<"amdfam10",        [FeatureSSE4A,
 425                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 426                                FeaturePOPCNT, FeatureSlowBTMem,
 427                                FeatureSlowSHLD]>;
 428 def : Proc<"barcelona",       [FeatureSSE4A,
 429                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 430                                FeaturePOPCNT, FeatureSlowBTMem,
 431                                FeatureSlowSHLD]>;
 432 // Bobcat
 433 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
 434                                FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
 435                                FeatureSlowSHLD]>;
 436
 437 // Jaguar
 438 def : ProcessorModel<"btver2", BtVer2Model,
 439                      [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
 440                       FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
 441                       FeatureBMI, FeatureF16C, FeatureMOVBE,
 442                       FeatureLZCNT, FeaturePOPCNT, FeatureFastUAMem,
 443                       FeatureSlowSHLD]>;
 444
 445 // TODO: We should probably add 'FeatureFastUAMem' to all of the AMD chips.
 446
 447 // Bulldozer
 448 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 449                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 450                                FeatureAVX, FeatureSSE4A, FeatureLZCNT,
 451                                FeaturePOPCNT, FeatureSlowSHLD]>;
 452 // Piledriver
 453 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 454                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 455                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 456                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 457                                FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
 458
 459 // Steamroller
 460 def : Proc<"bdver3",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 461                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 462                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 463                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 464                                FeatureTBM, FeatureFMA, FeatureSlowSHLD,
 465                                FeatureFSGSBase]>;
 466
 467 // Excavator
 468 def : Proc<"bdver4",          [FeatureAVX2, FeatureXOP, FeatureFMA4,
 469                                FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
 470                                FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
 471                                FeaturePOPCNT, FeatureBMI, FeatureBMI2,
 472                                FeatureTBM, FeatureFMA, FeatureSSE4A,
 473                                FeatureFSGSBase]>;
 474
 475 def : Proc<"geode",           [Feature3DNowA]>;
 476
 477 def : Proc<"winchip-c6",      [FeatureMMX]>;
 478 def : Proc<"winchip2",        [Feature3DNow]>;
 479 def : Proc<"c3",              [Feature3DNow]>;
 480 def : Proc<"c3-2",            [FeatureSSE1]>;
 481
 482 // We also provide a generic 64-bit specific x86 processor model which tries to
 483 // be good for modern chips without enabling instruction set encodings past the
 484 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 485 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 486 //
 487 // We currently use the Sandy Bridge model as the default scheduling model as
 488 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 489 // covers a huge swath of x86 processors. If there are specific scheduling
 490 // knobs which need to be tuned differently for AMD chips, we might consider
 491 // forming a common base for them.
 492 def : ProcessorModel<"x86-64", SandyBridgeModel,
 493                      [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
 494                       FeatureFastUAMem]>;
 495
 496 //===----------------------------------------------------------------------===//
 497 // Register File Description
 498 //===----------------------------------------------------------------------===//
 499
 500 include "X86RegisterInfo.td"
 501
 502 //===----------------------------------------------------------------------===//
 503 // Instruction Descriptions
 504 //===----------------------------------------------------------------------===//
 505
 506 include "X86InstrInfo.td"
 507
 508 def X86InstrInfo : InstrInfo;
 509
 510 //===----------------------------------------------------------------------===//
 511 // Calling Conventions
 512 //===----------------------------------------------------------------------===//
 513
 514 include "X86CallingConv.td"
 515
 516
 517 //===----------------------------------------------------------------------===//
 518 // Assembly Parser
 519 //===----------------------------------------------------------------------===//
 520
 521 def ATTAsmParser : AsmParser {
 522   string AsmParserClassName = "AsmParser";
 523 }
 524
 525 def ATTAsmParserVariant : AsmParserVariant {
 526   int Variant = 0;
 527
 528   // Variant name.
 529   string Name = "att";
 530
 531   // Discard comments in assembly strings.
 532   string CommentDelimiter = "#";
 533
 534   // Recognize hard coded registers.
 535   string RegisterPrefix = "%";
 536 }
 537
 538 def IntelAsmParserVariant : AsmParserVariant {
 539   int Variant = 1;
 540
 541   // Variant name.
 542   string Name = "intel";
 543
 544   // Discard comments in assembly strings.
 545   string CommentDelimiter = ";";
 546
 547   // Recognize hard coded registers.
 548   string RegisterPrefix = "";
 549 }
 550
 551 //===----------------------------------------------------------------------===//
 552 // Assembly Printers
 553 //===----------------------------------------------------------------------===//
 554
 555 // The X86 target supports two different syntaxes for emitting machine code.
 556 // This is controlled by the -x86-asm-syntax={att|intel}
 557 def ATTAsmWriter : AsmWriter {
 558   string AsmWriterClassName  = "ATTInstPrinter";
 559   int Variant = 0;
 560 }
 561 def IntelAsmWriter : AsmWriter {
 562   string AsmWriterClassName  = "IntelInstPrinter";
 563   int Variant = 1;
 564 }
 565
 566 def X86 : Target {
 567   // Information about the instructions...
 568   let InstructionSet = X86InstrInfo;
 569   let AssemblyParsers = [ATTAsmParser];
 570   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 571   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 572 }