lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40
  41 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  42                                       "Enable MMX instructions">;
  43 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  44                                       "Enable SSE instructions",
  45                                       // SSE codegen depends on cmovs, and all
  46                                       // SSE1+ processors support them.
  47                                       [FeatureMMX, FeatureCMOV]>;
  48 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  49                                       "Enable SSE2 instructions",
  50                                       [FeatureSSE1]>;
  51 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  52                                       "Enable SSE3 instructions",
  53                                       [FeatureSSE2]>;
  54 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  55                                       "Enable SSSE3 instructions",
  56                                       [FeatureSSE3]>;
  57 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  58                                       "Enable SSE 4.1 instructions",
  59                                       [FeatureSSSE3]>;
  60 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  61                                       "Enable SSE 4.2 instructions",
  62                                       [FeatureSSE41]>;
  63 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  64                                       "Enable 3DNow! instructions",
  65                                       [FeatureMMX]>;
  66 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  67                                       "Enable 3DNow! Athlon instructions",
  68                                       [Feature3DNow]>;
  69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  71 // without disabling 64-bit mode.
  72 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  73                                       "Support 64-bit instructions",
  74                                       [FeatureCMOV]>;
  75 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  76                                       "64-bit with cmpxchg16b",
  77                                       [Feature64Bit]>;
  78 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  79                                        "Bit testing of memory is slow">;
  80 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  81                                        "SHLD instruction is slow">;
  82 // FIXME: This is a 16-byte (SSE/AVX) feature; we should rename it to make that
  83 // explicit. Also, it seems this would be the default state for most chips
  84 // going forward, so it would probably be better to negate the logic and
  85 // match the 32-byte "slow mem" feature below.
  86 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  87                                         "IsUAMemFast", "true",
  88                                         "Fast unaligned memory access">;
  89 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
  90                             "IsUAMem32Slow", "true",
  91                             "Slow unaligned 32-byte memory access">;
  92 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  93                                       "Support SSE 4a instructions",
  94                                       [FeatureSSE3]>;
  95
  96 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  97                                       "Enable AVX instructions",
  98                                       [FeatureSSE42]>;
  99 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 100                                       "Enable AVX2 instructions",
 101                                       [FeatureAVX]>;
 102 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 103                                       "Enable AVX-512 instructions",
 104                                       [FeatureAVX2]>;
 105 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 106                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 107                                       [FeatureAVX512]>;
 108 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 109                       "Enable AVX-512 Conflict Detection Instructions",
 110                                       [FeatureAVX512]>;
 111 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 112                       "Enable AVX-512 PreFetch Instructions",
 113                                       [FeatureAVX512]>;
 114 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 115                       "Enable AVX-512 Doubleword and Quadword Instructions",
 116                                       [FeatureAVX512]>;
 117 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 118                       "Enable AVX-512 Byte and Word Instructions",
 119                                       [FeatureAVX512]>;
 120 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 121                       "Enable AVX-512 Vector Length eXtensions",
 122                                       [FeatureAVX512]>;
 123 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 124                          "Enable packed carry-less multiplication instructions",
 125                                [FeatureSSE2]>;
 126 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 127                                       "Enable three-operand fused multiple-add",
 128                                       [FeatureAVX]>;
 129 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 130                                       "Enable four-operand fused multiple-add",
 131                                       [FeatureAVX, FeatureSSE4A]>;
 132 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 133                                       "Enable XOP instructions",
 134                                       [FeatureFMA4]>;
 135 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 136                                           "HasSSEUnalignedMem", "true",
 137                       "Allow unaligned memory operands with SSE instructions">;
 138 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 139                                       "Enable AES instructions",
 140                                       [FeatureSSE2]>;
 141 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 142                                       "Enable TBM instructions">;
 143 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 144                                       "Support MOVBE instruction">;
 145 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 146                                       "Support RDRAND instruction">;
 147 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 148                        "Support 16-bit floating point conversion instructions",
 149                        [FeatureAVX]>;
 150 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 151                                        "Support FS/GS Base instructions">;
 152 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 153                                       "Support LZCNT instruction">;
 154 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 155                                       "Support BMI instructions">;
 156 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 157                                       "Support BMI2 instructions">;
 158 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 159                                       "Support RTM instructions">;
 160 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 161                                       "Support HLE">;
 162 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 163                                       "Support ADX instructions">;
 164 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 165                                       "Enable SHA instructions",
 166                                       [FeatureSSE2]>;
 167 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 168                                       "Support PRFCHW instructions">;
 169 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 170                                       "Support RDSEED instruction">;
 171 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 172                                       "Support MPX instructions">;
 173 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 174                                      "Use LEA for adjusting the stack pointer">;
 175 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 176                                      "HasSlowDivide32", "true",
 177                                      "Use 8-bit divide for positive values less than 256">;
 178 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 179                                      "HasSlowDivide64", "true",
 180                                      "Use 16-bit divide for positive values less than 65536">;
 181 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 182                                      "PadShortFunctions", "true",
 183                                      "Pad short functions">;
 184 // TODO: This feature ought to be renamed.
 185 // What it really refers to are CPUs for which certain instructions
 186 // (which ones besides the example below?) are microcoded.
 187 // The best examples of this are the memory forms of CALL and PUSH
 188 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
 189 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 190                                      "CallRegIndirect", "true",
 191                                      "Call register indirect">;
 192 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 193                                    "LEA instruction needs inputs at AG stage">;
 194 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 195                                    "LEA instruction with certain arguments is slow">;
 196 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 197                                    "INC and DEC instructions are slower than ADD and SUB">;
 198 def FeatureSoftFloat
 199     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 200                        "Use software floating point features.">;
 201
 202 //===----------------------------------------------------------------------===//
 203 // X86 processors supported.
 204 //===----------------------------------------------------------------------===//
 205
 206 include "X86Schedule.td"
 207
 208 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 209                     "Intel Atom processors">;
 210 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 211                     "Intel Silvermont processors">;
 212
 213 class Proc<string Name, list<SubtargetFeature> Features>
 214  : ProcessorModel<Name, GenericModel, Features>;
 215
 216 def : Proc<"generic",         []>;
 217 def : Proc<"i386",            []>;
 218 def : Proc<"i486",            []>;
 219 def : Proc<"i586",            []>;
 220 def : Proc<"pentium",         []>;
 221 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 222 def : Proc<"i686",            []>;
 223 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 224 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 225 def : Proc<"pentium3",        [FeatureSSE1]>;
 226 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 227 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 228 def : Proc<"pentium4",        [FeatureSSE2]>;
 229 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 230
 231 // Intel Core Duo.
 232 def : ProcessorModel<"yonah", SandyBridgeModel,
 233                      [FeatureSSE3, FeatureSlowBTMem]>;
 234
 235 // NetBurst.
 236 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
 237 def : Proc<"nocona",   [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 238
 239 // Intel Core 2 Solo/Duo.
 240 def : ProcessorModel<"core2", SandyBridgeModel,
 241                      [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 242 def : ProcessorModel<"penryn", SandyBridgeModel,
 243                      [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 244
 245 // Atom CPUs.
 246 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 247                                    ProcIntelAtom,
 248                                    FeatureSSSE3,
 249                                    FeatureCMPXCHG16B,
 250                                    FeatureMOVBE,
 251                                    FeatureSlowBTMem,
 252                                    FeatureLeaForSP,
 253                                    FeatureSlowDivide32,
 254                                    FeatureSlowDivide64,
 255                                    FeatureCallRegIndirect,
 256                                    FeatureLEAUsesAG,
 257                                    FeaturePadShortFunctions
 258                                  ]>;
 259 def : BonnellProc<"bonnell">;
 260 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 261
 262 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 263                                       ProcIntelSLM,
 264                                       FeatureSSE42,
 265                                       FeatureCMPXCHG16B,
 266                                       FeatureMOVBE,
 267                                       FeaturePOPCNT,
 268                                       FeaturePCLMUL,
 269                                       FeatureAES,
 270                                       FeatureSlowDivide64,
 271                                       FeatureCallRegIndirect,
 272                                       FeaturePRFCHW,
 273                                       FeatureSlowLEA,
 274                                       FeatureSlowIncDec,
 275                                       FeatureSlowBTMem,
 276                                       FeatureFastUAMem
 277                                     ]>;
 278 def : SilvermontProc<"silvermont">;
 279 def : SilvermontProc<"slm">; // Legacy alias.
 280
 281 // "Arrandale" along with corei3 and corei5
 282 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 283                                    FeatureSSE42,
 284                                    FeatureCMPXCHG16B,
 285                                    FeatureSlowBTMem,
 286                                    FeatureFastUAMem,
 287                                    FeaturePOPCNT
 288                                  ]>;
 289 def : NehalemProc<"nehalem">;
 290 def : NehalemProc<"corei7">;
 291
 292 // Westmere is a similar machine to nehalem with some additional features.
 293 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 294 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 295                                     FeatureSSE42,
 296                                     FeatureCMPXCHG16B,
 297                                     FeatureSlowBTMem,
 298                                     FeatureFastUAMem,
 299                                     FeaturePOPCNT,
 300                                     FeatureAES,
 301                                     FeaturePCLMUL
 302                                   ]>;
 303 def : WestmereProc<"westmere">;
 304
 305 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 306 // rather than a superset.
 307 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 308                                        FeatureAVX,
 309                                        FeatureCMPXCHG16B,
 310                                        FeatureSlowBTMem,
 311                                        FeatureFastUAMem,
 312                                        FeatureSlowUAMem32,
 313                                        FeaturePOPCNT,
 314                                        FeatureAES,
 315                                        FeaturePCLMUL
 316                                      ]>;
 317 def : SandyBridgeProc<"sandybridge">;
 318 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 319
 320 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 321                                      FeatureAVX,
 322                                      FeatureCMPXCHG16B,
 323                                      FeatureSlowBTMem,
 324                                      FeatureFastUAMem,
 325                                      FeatureSlowUAMem32,
 326                                      FeaturePOPCNT,
 327                                      FeatureAES,
 328                                      FeaturePCLMUL,
 329                                      FeatureRDRAND,
 330                                      FeatureF16C,
 331                                      FeatureFSGSBase
 332                                    ]>;
 333 def : IvyBridgeProc<"ivybridge">;
 334 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 335
 336 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 337                                    FeatureAVX2,
 338                                    FeatureCMPXCHG16B,
 339                                    FeatureSlowBTMem,
 340                                    FeatureFastUAMem,
 341                                    FeaturePOPCNT,
 342                                    FeatureAES,
 343                                    FeaturePCLMUL,
 344                                    FeatureRDRAND,
 345                                    FeatureF16C,
 346                                    FeatureFSGSBase,
 347                                    FeatureMOVBE,
 348                                    FeatureLZCNT,
 349                                    FeatureBMI,
 350                                    FeatureBMI2,
 351                                    FeatureFMA,
 352                                    FeatureRTM,
 353                                    FeatureHLE,
 354                                    FeatureSlowIncDec
 355                                  ]>;
 356 def : HaswellProc<"haswell">;
 357 def : HaswellProc<"core-avx2">; // Legacy alias.
 358
 359 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 360                                      FeatureAVX2,
 361                                      FeatureCMPXCHG16B,
 362                                      FeatureSlowBTMem,
 363                                      FeatureFastUAMem,
 364                                      FeaturePOPCNT,
 365                                      FeatureAES,
 366                                      FeaturePCLMUL,
 367                                      FeatureRDRAND,
 368                                      FeatureF16C,
 369                                      FeatureFSGSBase,
 370                                      FeatureMOVBE,
 371                                      FeatureLZCNT,
 372                                      FeatureBMI,
 373                                      FeatureBMI2,
 374                                      FeatureFMA,
 375                                      FeatureRTM,
 376                                      FeatureHLE,
 377                                      FeatureADX,
 378                                      FeatureRDSEED,
 379                                      FeatureSlowIncDec
 380                                    ]>;
 381 def : BroadwellProc<"broadwell">;
 382
 383 // FIXME: define KNL model
 384 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel,
 385                      [FeatureAVX512, FeatureERI, FeatureCDI, FeaturePFI,
 386                       FeatureCMPXCHG16B, FeatureFastUAMem, FeaturePOPCNT,
 387                       FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
 388                       FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 389                       FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
 390                       FeatureSlowIncDec, FeatureMPX]>;
 391 def : KnightsLandingProc<"knl">;
 392
 393 // FIXME: define SKX model
 394 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel,
 395                      [FeatureAVX512, FeatureCDI,
 396                       FeatureDQI, FeatureBWI, FeatureVLX,
 397                       FeatureCMPXCHG16B, FeatureSlowBTMem, FeatureFastUAMem,
 398                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
 399                       FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
 400                       FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
 401                       FeatureHLE, FeatureADX, FeatureRDSEED, FeatureSlowIncDec,
 402                       FeatureMPX]>;
 403 def : SkylakeProc<"skylake">;
 404 def : SkylakeProc<"skx">; // Legacy alias.
 405
 406
 407 // AMD CPUs.
 408
 409 def : Proc<"k6",              [FeatureMMX]>;
 410 def : Proc<"k6-2",            [Feature3DNow]>;
 411 def : Proc<"k6-3",            [Feature3DNow]>;
 412 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem,
 413                                FeatureSlowSHLD]>;
 414 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem,
 415                                FeatureSlowSHLD]>;
 416 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 417                                FeatureSlowSHLD]>;
 418 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 419                                FeatureSlowSHLD]>;
 420 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem,
 421                                FeatureSlowSHLD]>;
 422 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 423                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 424 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 425                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 426 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 427                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 428 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 429                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 430 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 431                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 432 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 433                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 434 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 435                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 436 def : Proc<"amdfam10",        [FeatureSSE4A,
 437                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 438                                FeaturePOPCNT, FeatureSlowBTMem,
 439                                FeatureSlowSHLD]>;
 440 def : Proc<"barcelona",       [FeatureSSE4A,
 441                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 442                                FeaturePOPCNT, FeatureSlowBTMem,
 443                                FeatureSlowSHLD]>;
 444 // Bobcat
 445 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
 446                                FeaturePRFCHW, FeatureLZCNT, FeaturePOPCNT,
 447                                FeatureSlowSHLD]>;
 448
 449 // Jaguar
 450 def : ProcessorModel<"btver2", BtVer2Model,
 451                      [FeatureAVX, FeatureSSE4A, FeatureCMPXCHG16B,
 452                       FeaturePRFCHW, FeatureAES, FeaturePCLMUL,
 453                       FeatureBMI, FeatureF16C, FeatureMOVBE,
 454                       FeatureLZCNT, FeaturePOPCNT, FeatureFastUAMem,
 455                       FeatureSlowSHLD]>;
 456
 457 // TODO: We should probably add 'FeatureFastUAMem' to all of the AMD chips.
 458
 459 // Bulldozer
 460 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 461                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 462                                FeatureAVX, FeatureSSE4A, FeatureLZCNT,
 463                                FeaturePOPCNT, FeatureSlowSHLD]>;
 464 // Piledriver
 465 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 466                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 467                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 468                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 469                                FeatureTBM, FeatureFMA, FeatureSlowSHLD]>;
 470
 471 // Steamroller
 472 def : Proc<"bdver3",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 473                                FeatureAES, FeaturePRFCHW, FeaturePCLMUL,
 474                                FeatureAVX, FeatureSSE4A, FeatureF16C,
 475                                FeatureLZCNT, FeaturePOPCNT, FeatureBMI,
 476                                FeatureTBM, FeatureFMA, FeatureSlowSHLD,
 477                                FeatureFSGSBase]>;
 478
 479 // Excavator
 480 def : Proc<"bdver4",          [FeatureAVX2, FeatureXOP, FeatureFMA4,
 481                                FeatureCMPXCHG16B, FeatureAES, FeaturePRFCHW,
 482                                FeaturePCLMUL, FeatureF16C, FeatureLZCNT,
 483                                FeaturePOPCNT, FeatureBMI, FeatureBMI2,
 484                                FeatureTBM, FeatureFMA, FeatureSSE4A,
 485                                FeatureFSGSBase]>;
 486
 487 def : Proc<"geode",           [Feature3DNowA]>;
 488
 489 def : Proc<"winchip-c6",      [FeatureMMX]>;
 490 def : Proc<"winchip2",        [Feature3DNow]>;
 491 def : Proc<"c3",              [Feature3DNow]>;
 492 def : Proc<"c3-2",            [FeatureSSE1]>;
 493
 494 // We also provide a generic 64-bit specific x86 processor model which tries to
 495 // be good for modern chips without enabling instruction set encodings past the
 496 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 497 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 498 //
 499 // We currently use the Sandy Bridge model as the default scheduling model as
 500 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 501 // covers a huge swath of x86 processors. If there are specific scheduling
 502 // knobs which need to be tuned differently for AMD chips, we might consider
 503 // forming a common base for them.
 504 def : ProcessorModel<"x86-64", SandyBridgeModel,
 505                      [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
 506                       FeatureFastUAMem]>;
 507
 508 //===----------------------------------------------------------------------===//
 509 // Register File Description
 510 //===----------------------------------------------------------------------===//
 511
 512 include "X86RegisterInfo.td"
 513
 514 //===----------------------------------------------------------------------===//
 515 // Instruction Descriptions
 516 //===----------------------------------------------------------------------===//
 517
 518 include "X86InstrInfo.td"
 519
 520 def X86InstrInfo : InstrInfo;
 521
 522 //===----------------------------------------------------------------------===//
 523 // Calling Conventions
 524 //===----------------------------------------------------------------------===//
 525
 526 include "X86CallingConv.td"
 527
 528
 529 //===----------------------------------------------------------------------===//
 530 // Assembly Parser
 531 //===----------------------------------------------------------------------===//
 532
 533 def ATTAsmParser : AsmParser {
 534   string AsmParserClassName = "AsmParser";
 535 }
 536
 537 def ATTAsmParserVariant : AsmParserVariant {
 538   int Variant = 0;
 539
 540   // Variant name.
 541   string Name = "att";
 542
 543   // Discard comments in assembly strings.
 544   string CommentDelimiter = "#";
 545
 546   // Recognize hard coded registers.
 547   string RegisterPrefix = "%";
 548 }
 549
 550 def IntelAsmParserVariant : AsmParserVariant {
 551   int Variant = 1;
 552
 553   // Variant name.
 554   string Name = "intel";
 555
 556   // Discard comments in assembly strings.
 557   string CommentDelimiter = ";";
 558
 559   // Recognize hard coded registers.
 560   string RegisterPrefix = "";
 561 }
 562
 563 //===----------------------------------------------------------------------===//
 564 // Assembly Printers
 565 //===----------------------------------------------------------------------===//
 566
 567 // The X86 target supports two different syntaxes for emitting machine code.
 568 // This is controlled by the -x86-asm-syntax={att|intel}
 569 def ATTAsmWriter : AsmWriter {
 570   string AsmWriterClassName  = "ATTInstPrinter";
 571   int Variant = 0;
 572 }
 573 def IntelAsmWriter : AsmWriter {
 574   string AsmWriterClassName  = "IntelInstPrinter";
 575   int Variant = 1;
 576 }
 577
 578 def X86 : Target {
 579   // Information about the instructions...
 580   let InstructionSet = X86InstrInfo;
 581   let AssemblyParsers = [ATTAsmParser];
 582   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 583   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 584 }