lib/Target/X86/X86.td

   1 //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state.
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25
  26 //===----------------------------------------------------------------------===//
  27 // X86 Subtarget features.
  28 //===----------------------------------------------------------------------===//
  29
  30 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  31                                       "Enable conditional move instructions">;
  32
  33 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  34                                        "Support POPCNT instruction">;
  35
  36
  37 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  38                                       "Enable MMX instructions">;
  39 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  40                                       "Enable SSE instructions",
  41                                       // SSE codegen depends on cmovs, and all
  42                                       // SSE1+ processors support them.
  43                                       [FeatureMMX, FeatureCMOV]>;
  44 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  45                                       "Enable SSE2 instructions",
  46                                       [FeatureSSE1]>;
  47 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  48                                       "Enable SSE3 instructions",
  49                                       [FeatureSSE2]>;
  50 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  51                                       "Enable SSSE3 instructions",
  52                                       [FeatureSSE3]>;
  53 def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
  54                                       "Enable SSE 4.1 instructions",
  55                                       [FeatureSSSE3]>;
  56 def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
  57                                       "Enable SSE 4.2 instructions",
  58                                       [FeatureSSE41]>;
  59 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  60                                       "Enable 3DNow! instructions",
  61                                       [FeatureMMX]>;
  62 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  63                                       "Enable 3DNow! Athlon instructions",
  64                                       [Feature3DNow]>;
  65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  67 // without disabling 64-bit mode.
  68 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  69                                       "Support 64-bit instructions",
  70                                       [FeatureCMOV]>;
  71 def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
  72                                       "64-bit with cmpxchg16b",
  73                                       [Feature64Bit]>;
  74 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  75                                        "Bit testing of memory is slow">;
  76 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  77                                         "IsUAMemFast", "true",
  78                                         "Fast unaligned memory access">;
  79 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  80                                       "Support SSE 4a instructions",
  81                                       [FeatureSSE3]>;
  82
  83 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  84                                       "Enable AVX instructions",
  85                                       [FeatureSSE42]>;
  86 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
  87                                       "Enable AVX2 instructions",
  88                                       [FeatureAVX]>;
  89 def FeatureCLMUL   : SubtargetFeature<"clmul", "HasCLMUL", "true",
  90                                "Enable carry-less multiplication instructions">;
  91 def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
  92                                       "Enable three-operand fused multiple-add",
  93                                       [FeatureAVX]>;
  94 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
  95                                       "Enable four-operand fused multiple-add",
  96                                       [FeatureAVX]>;
  97 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
  98                                       "Enable XOP instructions">;
  99 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
 100                                           "HasVectorUAMem", "true",
 101                  "Allow unaligned memory operands on vector/SIMD instructions">;
 102 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 103                                       "Enable AES instructions">;
 104 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 105                                       "Support MOVBE instruction">;
 106 def FeatureRDRAND  : SubtargetFeature<"rdrand", "HasRDRAND", "true",
 107                                       "Support RDRAND instruction">;
 108 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 109                        "Support 16-bit floating point conversion instructions">;
 110 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 111                                        "Support FS/GS Base instructions">;
 112 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 113                                       "Support LZCNT instruction">;
 114 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 115                                       "Support BMI instructions">;
 116 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 117                                       "Support BMI2 instructions">;
 118
 119 //===----------------------------------------------------------------------===//
 120 // X86 processors supported.
 121 //===----------------------------------------------------------------------===//
 122
 123 class Proc<string Name, list<SubtargetFeature> Features>
 124  : Processor<Name, NoItineraries, Features>;
 125
 126 def : Proc<"generic",         []>;
 127 def : Proc<"i386",            []>;
 128 def : Proc<"i486",            []>;
 129 def : Proc<"i586",            []>;
 130 def : Proc<"pentium",         []>;
 131 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 132 def : Proc<"i686",            []>;
 133 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 134 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 135 def : Proc<"pentium3",        [FeatureSSE1]>;
 136 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 137 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 138 def : Proc<"pentium4",        [FeatureSSE2]>;
 139 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 140 def : Proc<"x86-64",          [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
 141 def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
 142 def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
 143 def : Proc<"nocona",          [FeatureSSE3, FeatureCMPXCHG16B,
 144                                FeatureSlowBTMem]>;
 145 def : Proc<"core2",           [FeatureSSSE3, FeatureCMPXCHG16B,
 146                                FeatureSlowBTMem]>;
 147 def : Proc<"penryn",          [FeatureSSE41, FeatureCMPXCHG16B,
 148                                FeatureSlowBTMem]>;
 149 def : Proc<"atom",            [FeatureSSE3, FeatureCMPXCHG16B, FeatureMOVBE,
 150                                FeatureSlowBTMem]>;
 151 // "Arrandale" along with corei3 and corei5
 152 def : Proc<"corei7",          [FeatureSSE42, FeatureCMPXCHG16B,
 153                                FeatureSlowBTMem, FeatureFastUAMem,
 154                                FeaturePOPCNT, FeatureAES]>;
 155 def : Proc<"nehalem",         [FeatureSSE42,  FeatureCMPXCHG16B,
 156                                FeatureSlowBTMem, FeatureFastUAMem,
 157                                FeaturePOPCNT]>;
 158 // Westmere is a similar machine to nehalem with some additional features.
 159 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 160 def : Proc<"westmere",        [FeatureSSE42, FeatureCMPXCHG16B,
 161                                FeatureSlowBTMem, FeatureFastUAMem,
 162                                FeaturePOPCNT, FeatureAES, FeatureCLMUL]>;
 163 // Sandy Bridge
 164 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 165 // rather than a superset.
 166 // FIXME: Disabling AVX for now since it's not ready.
 167 def : Proc<"corei7-avx",      [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT,
 168                                FeatureAES, FeatureCLMUL]>;
 169 // Ivy Bridge
 170 def : Proc<"core-avx-i",      [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT,
 171                                FeatureAES, FeatureCLMUL,
 172                                FeatureRDRAND, FeatureF16C, FeatureFSGSBase]>;
 173
 174 // Haswell
 175 // FIXME: Disabling AVX/AVX2/FMA3 for now since it's not ready.
 176 def : Proc<"core-avx2",       [FeatureSSE42, FeatureCMPXCHG16B, FeaturePOPCNT,
 177                                FeatureAES, FeatureCLMUL, FeatureRDRAND,
 178                                FeatureF16C, FeatureFSGSBase,
 179                                FeatureMOVBE, FeatureLZCNT, FeatureBMI,
 180                                FeatureBMI2]>;
 181
 182 def : Proc<"k6",              [FeatureMMX]>;
 183 def : Proc<"k6-2",            [Feature3DNow]>;
 184 def : Proc<"k6-3",            [Feature3DNow]>;
 185 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem]>;
 186 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem]>;
 187 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 188 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 189 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 190 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 191                                FeatureSlowBTMem]>;
 192 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 193                                FeatureSlowBTMem]>;
 194 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 195                                FeatureSlowBTMem]>;
 196 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 197                                FeatureSlowBTMem]>;
 198 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 199                                FeatureSlowBTMem]>;
 200 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 201                                FeatureSlowBTMem]>;
 202 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 203                                FeatureSlowBTMem]>;
 204 def : Proc<"amdfam10",        [FeatureSSE3,   FeatureSSE4A,
 205                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 206                                FeaturePOPCNT, FeatureSlowBTMem]>;
 207 // FIXME: Disabling AVX/FMA4 for now since it's not ready.
 208 def : Proc<"bdver1",          [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B,
 209                                FeatureAES, FeatureCLMUL,
 210                                FeatureXOP, FeatureLZCNT, FeaturePOPCNT]>;
 211 def : Proc<"bdver2",          [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B,
 212                                FeatureAES, FeatureCLMUL,
 213                                FeatureXOP, FeatureF16C, FeatureLZCNT,
 214                                FeaturePOPCNT, FeatureBMI]>;
 215
 216 def : Proc<"winchip-c6",      [FeatureMMX]>;
 217 def : Proc<"winchip2",        [Feature3DNow]>;
 218 def : Proc<"c3",              [Feature3DNow]>;
 219 def : Proc<"c3-2",            [FeatureSSE1]>;
 220
 221 //===----------------------------------------------------------------------===//
 222 // Register File Description
 223 //===----------------------------------------------------------------------===//
 224
 225 include "X86RegisterInfo.td"
 226
 227 //===----------------------------------------------------------------------===//
 228 // Instruction Descriptions
 229 //===----------------------------------------------------------------------===//
 230
 231 include "X86InstrInfo.td"
 232
 233 def X86InstrInfo : InstrInfo;
 234
 235 //===----------------------------------------------------------------------===//
 236 // Calling Conventions
 237 //===----------------------------------------------------------------------===//
 238
 239 include "X86CallingConv.td"
 240
 241
 242 //===----------------------------------------------------------------------===//
 243 // Assembly Parser
 244 //===----------------------------------------------------------------------===//
 245
 246 // Currently the X86 assembly parser only supports ATT syntax.
 247 def ATTAsmParser : AsmParser {
 248   string AsmParserClassName = "ATTAsmParser";
 249   int Variant = 0;
 250
 251   // Discard comments in assembly strings.
 252   string CommentDelimiter = "#";
 253
 254   // Recognize hard coded registers.
 255   string RegisterPrefix = "%";
 256 }
 257
 258 //===----------------------------------------------------------------------===//
 259 // Assembly Printers
 260 //===----------------------------------------------------------------------===//
 261
 262 // The X86 target supports two different syntaxes for emitting machine code.
 263 // This is controlled by the -x86-asm-syntax={att|intel}
 264 def ATTAsmWriter : AsmWriter {
 265   string AsmWriterClassName  = "ATTInstPrinter";
 266   int Variant = 0;
 267   bit isMCAsmWriter = 1;
 268 }
 269 def IntelAsmWriter : AsmWriter {
 270   string AsmWriterClassName  = "IntelInstPrinter";
 271   int Variant = 1;
 272   bit isMCAsmWriter = 1;
 273 }
 274
 275 def X86 : Target {
 276   // Information about the instructions...
 277   let InstructionSet = X86InstrInfo;
 278
 279   let AssemblyParsers = [ATTAsmParser];
 280
 281   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 282 }