lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25
  26 //===----------------------------------------------------------------------===//
  27 // X86 Subtarget features
  28 //===----------------------------------------------------------------------===//
  29
  30 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  31                                       "Enable conditional move instructions">;
  32
  33 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  34                                        "Support POPCNT instruction">;
  35
  36
  37 def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
  38                                       "Enable MMX instructions">;
  39 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  40                                       "Enable SSE instructions",
  41                                       // SSE codegen depends on cmovs, and all
  42                                       // SSE1+ processors support them.
  43                                       [FeatureMMX, FeatureCMOV]>;
  44 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  45                                       "Enable SSE2 instructions",
  46                                       [FeatureSSE1]>;
  47 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  48                                       "Enable SSE3 instructions",
  49                                       [FeatureSSE2]>;
  50 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  51                                       "Enable SSSE3 instructions",
  52                                       [FeatureSSE3]>;
  53 def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
  54                                       "Enable SSE 4.1 instructions",
  55                                       [FeatureSSSE3]>;
  56 def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
  57                                       "Enable SSE 4.2 instructions",
  58                                       [FeatureSSE41]>;
  59 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  60                                       "Enable 3DNow! instructions",
  61                                       [FeatureMMX]>;
  62 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  63                                       "Enable 3DNow! Athlon instructions",
  64                                       [Feature3DNow]>;
  65 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  66 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  67 // without disabling 64-bit mode.
  68 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  69                                       "Support 64-bit instructions",
  70                                       [FeatureCMOV]>;
  71 def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
  72                                       "64-bit with cmpxchg16b",
  73                                       [Feature64Bit]>;
  74 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  75                                        "Bit testing of memory is slow">;
  76 def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
  77                                         "IsUAMemFast", "true",
  78                                         "Fast unaligned memory access">;
  79 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
  80                                       "Support SSE 4a instructions",
  81                                       [FeatureSSE3]>;
  82
  83 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
  84                                       "Enable AVX instructions",
  85                                       [FeatureSSE42]>;
  86 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
  87                                       "Enable AVX2 instructions",
  88                                       [FeatureAVX]>;
  89 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
  90                          "Enable packed carry-less multiplication instructions",
  91                                [FeatureSSE2]>;
  92 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
  93                                       "Enable three-operand fused multiple-add",
  94                                       [FeatureAVX]>;
  95 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
  96                                       "Enable four-operand fused multiple-add",
  97                                       [FeatureAVX, FeatureSSE4A]>;
  98 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
  99                                       "Enable XOP instructions",
 100                                       [FeatureFMA4]>;
 101 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
 102                                           "HasVectorUAMem", "true",
 103                  "Allow unaligned memory operands on vector/SIMD instructions">;
 104 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 105                                       "Enable AES instructions",
 106                                       [FeatureSSE2]>;
 107 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 108                                       "Support MOVBE instruction">;
 109 def FeatureRDRAND  : SubtargetFeature<"rdrand", "HasRDRAND", "true",
 110                                       "Support RDRAND instruction">;
 111 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 112                        "Support 16-bit floating point conversion instructions">;
 113 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 114                                        "Support FS/GS Base instructions">;
 115 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 116                                       "Support LZCNT instruction">;
 117 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 118                                       "Support BMI instructions">;
 119 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 120                                       "Support BMI2 instructions">;
 121 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 122                                       "Support RTM instructions">;
 123 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 124                                       "Support HLE">;
 125 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 126                                       "Support ADX instructions">;
 127 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 128                                       "Support PRFCHW instructions">;
 129 def FeatureLeaForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 130                                      "Use LEA for adjusting the stack pointer">;
 131 def FeatureSlowDivide : SubtargetFeature<"idiv-to-divb",
 132                                      "HasSlowDivide", "true",
 133                                      "Use small divide for positive values less than 256">;
 134 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 135                                      "PadShortFunctions", "true",
 136                                      "Pad short functions">;
 137
 138 //===----------------------------------------------------------------------===//
 139 // X86 processors supported.
 140 //===----------------------------------------------------------------------===//
 141
 142 include "X86Schedule.td"
 143
 144 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 145                     "Intel Atom processors">;
 146
 147 class Proc<string Name, list<SubtargetFeature> Features>
 148  : ProcessorModel<Name, GenericModel, Features>;
 149
 150 def : Proc<"generic",         []>;
 151 def : Proc<"i386",            []>;
 152 def : Proc<"i486",            []>;
 153 def : Proc<"i586",            []>;
 154 def : Proc<"pentium",         []>;
 155 def : Proc<"pentium-mmx",     [FeatureMMX]>;
 156 def : Proc<"i686",            []>;
 157 def : Proc<"pentiumpro",      [FeatureCMOV]>;
 158 def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
 159 def : Proc<"pentium3",        [FeatureSSE1]>;
 160 def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
 161 def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
 162 def : Proc<"pentium4",        [FeatureSSE2]>;
 163 def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
 164 def : Proc<"x86-64",          [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
 165                                FeatureFastUAMem]>;
 166 // Intel Core Duo.
 167 def : ProcessorModel<"yonah", SandyBridgeModel,
 168                      [FeatureSSE3, FeatureSlowBTMem]>;
 169
 170 // NetBurst.
 171 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
 172 def : Proc<"nocona",   [FeatureSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 173
 174 // Intel Core 2 Solo/Duo.
 175 def : ProcessorModel<"core2", SandyBridgeModel,
 176                      [FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 177 def : ProcessorModel<"penryn", SandyBridgeModel,
 178                      [FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
 179
 180 // Atom.
 181 def : ProcessorModel<"atom", AtomModel,
 182                      [ProcIntelAtom, FeatureSSSE3, FeatureCMPXCHG16B,
 183                       FeatureMOVBE, FeatureSlowBTMem, FeatureLeaForSP,
 184                       FeatureSlowDivide, FeaturePadShortFunctions]>;
 185
 186 // "Arrandale" along with corei3 and corei5
 187 def : ProcessorModel<"corei7", SandyBridgeModel,
 188                      [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
 189                       FeatureFastUAMem, FeaturePOPCNT, FeatureAES]>;
 190
 191 def : ProcessorModel<"nehalem", SandyBridgeModel,
 192                      [FeatureSSE42,  FeatureCMPXCHG16B, FeatureSlowBTMem,
 193                       FeatureFastUAMem, FeaturePOPCNT]>;
 194 // Westmere is a similar machine to nehalem with some additional features.
 195 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 196 def : ProcessorModel<"westmere", SandyBridgeModel,
 197                      [FeatureSSE42, FeatureCMPXCHG16B, FeatureSlowBTMem,
 198                       FeatureFastUAMem, FeaturePOPCNT, FeatureAES,
 199                       FeaturePCLMUL]>;
 200 // Sandy Bridge
 201 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 202 // rather than a superset.
 203 def : ProcessorModel<"corei7-avx", SandyBridgeModel,
 204                      [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
 205                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL]>;
 206 // Ivy Bridge
 207 def : ProcessorModel<"core-avx-i", SandyBridgeModel,
 208                      [FeatureAVX, FeatureCMPXCHG16B, FeatureFastUAMem,
 209                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
 210                       FeatureF16C, FeatureFSGSBase]>;
 211
 212 // Haswell
 213 def : ProcessorModel<"core-avx2", SandyBridgeModel,
 214                      [FeatureAVX2, FeatureCMPXCHG16B, FeatureFastUAMem,
 215                       FeaturePOPCNT, FeatureAES, FeaturePCLMUL, FeatureRDRAND,
 216                       FeatureF16C, FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT,
 217                       FeatureBMI, FeatureBMI2, FeatureFMA, FeatureRTM,
 218                       FeatureHLE]>;
 219
 220 def : Proc<"k6",              [FeatureMMX]>;
 221 def : Proc<"k6-2",            [Feature3DNow]>;
 222 def : Proc<"k6-3",            [Feature3DNow]>;
 223 def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem]>;
 224 def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem]>;
 225 def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 226 def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 227 def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
 228 def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 229                                FeatureSlowBTMem]>;
 230 def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 231                                FeatureSlowBTMem]>;
 232 def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 233                                FeatureSlowBTMem]>;
 234 def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
 235                                FeatureSlowBTMem]>;
 236 def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 237                                FeatureSlowBTMem]>;
 238 def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 239                                FeatureSlowBTMem]>;
 240 def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 241                                FeatureSlowBTMem]>;
 242 def : Proc<"amdfam10",        [FeatureSSE4A,
 243                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
 244                                FeaturePOPCNT, FeatureSlowBTMem]>;
 245 // Bobcat
 246 def : Proc<"btver1",          [FeatureSSSE3, FeatureSSE4A, FeatureCMPXCHG16B,
 247                                FeatureLZCNT, FeaturePOPCNT]>;
 248 // Bulldozer
 249 def : Proc<"bdver1",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 250                                FeatureAES, FeaturePCLMUL,
 251                                FeatureLZCNT, FeaturePOPCNT]>;
 252 // Enhanced Bulldozer
 253 def : Proc<"bdver2",          [FeatureXOP, FeatureFMA4, FeatureCMPXCHG16B,
 254                                FeatureAES, FeaturePCLMUL,
 255                                FeatureF16C, FeatureLZCNT,
 256                                FeaturePOPCNT, FeatureBMI, FeatureFMA]>;
 257 def : Proc<"geode",           [Feature3DNowA]>;
 258
 259 def : Proc<"winchip-c6",      [FeatureMMX]>;
 260 def : Proc<"winchip2",        [Feature3DNow]>;
 261 def : Proc<"c3",              [Feature3DNow]>;
 262 def : Proc<"c3-2",            [FeatureSSE1]>;
 263
 264 //===----------------------------------------------------------------------===//
 265 // Register File Description
 266 //===----------------------------------------------------------------------===//
 267
 268 include "X86RegisterInfo.td"
 269
 270 //===----------------------------------------------------------------------===//
 271 // Instruction Descriptions
 272 //===----------------------------------------------------------------------===//
 273
 274 include "X86InstrInfo.td"
 275
 276 def X86InstrInfo : InstrInfo;
 277
 278 //===----------------------------------------------------------------------===//
 279 // Calling Conventions
 280 //===----------------------------------------------------------------------===//
 281
 282 include "X86CallingConv.td"
 283
 284
 285 //===----------------------------------------------------------------------===//
 286 // Assembly Parser
 287 //===----------------------------------------------------------------------===//
 288
 289 def ATTAsmParser : AsmParser {
 290   string AsmParserClassName = "AsmParser";
 291 }
 292
 293 def ATTAsmParserVariant : AsmParserVariant {
 294   int Variant = 0;
 295
 296   // Discard comments in assembly strings.
 297   string CommentDelimiter = "#";
 298
 299   // Recognize hard coded registers.
 300   string RegisterPrefix = "%";
 301 }
 302
 303 def IntelAsmParserVariant : AsmParserVariant {
 304   int Variant = 1;
 305
 306   // Discard comments in assembly strings.
 307   string CommentDelimiter = ";";
 308
 309   // Recognize hard coded registers.
 310   string RegisterPrefix = "";
 311 }
 312
 313 //===----------------------------------------------------------------------===//
 314 // Assembly Printers
 315 //===----------------------------------------------------------------------===//
 316
 317 // The X86 target supports two different syntaxes for emitting machine code.
 318 // This is controlled by the -x86-asm-syntax={att|intel}
 319 def ATTAsmWriter : AsmWriter {
 320   string AsmWriterClassName  = "ATTInstPrinter";
 321   int Variant = 0;
 322   bit isMCAsmWriter = 1;
 323 }
 324 def IntelAsmWriter : AsmWriter {
 325   string AsmWriterClassName  = "IntelInstPrinter";
 326   int Variant = 1;
 327   bit isMCAsmWriter = 1;
 328 }
 329
 330 def X86 : Target {
 331   // Information about the instructions...
 332   let InstructionSet = X86InstrInfo;
 333   let AssemblyParsers = [ATTAsmParser];
 334   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 335   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 336 }