lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is a target description file for the Intel i386 architecture, referred
  11 // to here as the "X86" architecture.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // Get the target-independent interfaces which we are implementing...
  16 //
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // X86 Subtarget state
  21 //
  22
  23 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  24                                   "64-bit mode (x86_64)">;
  25 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  26                                   "32-bit mode (80386)">;
  27 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  28                                   "16-bit mode (i8086)">;
  29
  30 //===----------------------------------------------------------------------===//
  31 // X86 Subtarget features
  32 //===----------------------------------------------------------------------===//
  33
  34 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  35                                       "Enable conditional move instructions">;
  36
  37 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  38                                        "Support POPCNT instruction">;
  39
  40 def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
  41                                       "Support fxsave/fxrestore instructions">;
  42
  43 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
  44                                        "Support xsave instructions">;
  45
  46 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
  47                                        "Support xsaveopt instructions">;
  48
  49 def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
  50                                        "Support xsavec instructions">;
  51
  52 def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
  53                                        "Support xsaves instructions">;
  54
  55 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  56                                       "Enable SSE instructions",
  57                                       // SSE codegen depends on cmovs, and all
  58                                       // SSE1+ processors support them.
  59                                       [FeatureCMOV]>;
  60 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  61                                       "Enable SSE2 instructions",
  62                                       [FeatureSSE1]>;
  63 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  64                                       "Enable SSE3 instructions",
  65                                       [FeatureSSE2]>;
  66 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  67                                       "Enable SSSE3 instructions",
  68                                       [FeatureSSE3]>;
  69 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  70                                       "Enable SSE 4.1 instructions",
  71                                       [FeatureSSSE3]>;
  72 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  73                                       "Enable SSE 4.2 instructions",
  74                                       [FeatureSSE41]>;
  75 // The MMX subtarget feature is separate from the rest of the SSE features
  76 // because it's important (for odd compatibility reasons) to be able to
  77 // turn it off explicitly while allowing SSE+ to be on.
  78 def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
  79                                       "Enable MMX instructions">;
  80 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  81                                       "Enable 3DNow! instructions",
  82                                       [FeatureMMX]>;
  83 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  84                                       "Enable 3DNow! Athlon instructions",
  85                                       [Feature3DNow]>;
  86 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  87 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  88 // without disabling 64-bit mode.
  89 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  90                                       "Support 64-bit instructions",
  91                                       [FeatureCMOV]>;
  92 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  93                                       "64-bit with cmpxchg16b",
  94                                       [Feature64Bit]>;
  95 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
  96                                        "Bit testing of memory is slow">;
  97 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
  98                                        "SHLD instruction is slow">;
  99 // FIXME: This should not apply to CPUs that do not have SSE.
 100 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
 101                                 "IsUAMem16Slow", "true",
 102                                 "Slow unaligned 16-byte memory access">;
 103 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
 104                                 "IsUAMem32Slow", "true",
 105                                 "Slow unaligned 32-byte memory access">;
 106 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
 107                                       "Support SSE 4a instructions",
 108                                       [FeatureSSE3]>;
 109
 110 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
 111                                       "Enable AVX instructions",
 112                                       [FeatureSSE42]>;
 113 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 114                                       "Enable AVX2 instructions",
 115                                       [FeatureAVX]>;
 116 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 117                                       "Enable AVX-512 instructions",
 118                                       [FeatureAVX2]>;
 119 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 120                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 121                                       [FeatureAVX512]>;
 122 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 123                       "Enable AVX-512 Conflict Detection Instructions",
 124                                       [FeatureAVX512]>;
 125 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 126                       "Enable AVX-512 PreFetch Instructions",
 127                                       [FeatureAVX512]>;
 128 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 129                       "Enable AVX-512 Doubleword and Quadword Instructions",
 130                                       [FeatureAVX512]>;
 131 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 132                       "Enable AVX-512 Byte and Word Instructions",
 133                                       [FeatureAVX512]>;
 134 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 135                       "Enable AVX-512 Vector Length eXtensions",
 136                                       [FeatureAVX512]>;
 137 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 138                          "Enable packed carry-less multiplication instructions",
 139                                [FeatureSSE2]>;
 140 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 141                                       "Enable three-operand fused multiple-add",
 142                                       [FeatureAVX]>;
 143 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 144                                       "Enable four-operand fused multiple-add",
 145                                       [FeatureAVX, FeatureSSE4A]>;
 146 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 147                                       "Enable XOP instructions",
 148                                       [FeatureFMA4]>;
 149 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 150                                           "HasSSEUnalignedMem", "true",
 151                       "Allow unaligned memory operands with SSE instructions">;
 152 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 153                                       "Enable AES instructions",
 154                                       [FeatureSSE2]>;
 155 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 156                                       "Enable TBM instructions">;
 157 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 158                                       "Support MOVBE instruction">;
 159 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 160                                       "Support RDRAND instruction">;
 161 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 162                        "Support 16-bit floating point conversion instructions",
 163                        [FeatureAVX]>;
 164 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 165                                        "Support FS/GS Base instructions">;
 166 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 167                                       "Support LZCNT instruction">;
 168 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 169                                       "Support BMI instructions">;
 170 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 171                                       "Support BMI2 instructions">;
 172 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 173                                       "Support RTM instructions">;
 174 def FeatureHLE     : SubtargetFeature<"hle", "HasHLE", "true",
 175                                       "Support HLE">;
 176 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 177                                       "Support ADX instructions">;
 178 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 179                                       "Enable SHA instructions",
 180                                       [FeatureSSE2]>;
 181 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 182                                       "Support PRFCHW instructions">;
 183 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 184                                       "Support RDSEED instruction">;
 185 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
 186                                       "Support MPX instructions">;
 187 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 188                                      "Use LEA for adjusting the stack pointer">;
 189 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 190                                      "HasSlowDivide32", "true",
 191                                      "Use 8-bit divide for positive values less than 256">;
 192 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divw",
 193                                      "HasSlowDivide64", "true",
 194                                      "Use 16-bit divide for positive values less than 65536">;
 195 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 196                                      "PadShortFunctions", "true",
 197                                      "Pad short functions">;
 198 // TODO: This feature ought to be renamed.
 199 // What it really refers to are CPUs for which certain instructions
 200 // (which ones besides the example below?) are microcoded.
 201 // The best examples of this are the memory forms of CALL and PUSH
 202 // instructions, which should be avoided in favor of a MOV + register CALL/PUSH.
 203 def FeatureCallRegIndirect : SubtargetFeature<"call-reg-indirect",
 204                                      "CallRegIndirect", "true",
 205                                      "Call register indirect">;
 206 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 207                                    "LEA instruction needs inputs at AG stage">;
 208 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 209                                    "LEA instruction with certain arguments is slow">;
 210 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 211                                    "INC and DEC instructions are slower than ADD and SUB">;
 212 def FeatureSoftFloat
 213     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 214                        "Use software floating point features.">;
 215
 216 //===----------------------------------------------------------------------===//
 217 // X86 processors supported.
 218 //===----------------------------------------------------------------------===//
 219
 220 include "X86Schedule.td"
 221
 222 def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
 223                     "Intel Atom processors">;
 224 def ProcIntelSLM  : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM",
 225                     "Intel Silvermont processors">;
 226
 227 class Proc<string Name, list<SubtargetFeature> Features>
 228  : ProcessorModel<Name, GenericModel, Features>;
 229
 230 def : Proc<"generic",         [FeatureSlowUAMem16]>;
 231 def : Proc<"i386",            [FeatureSlowUAMem16]>;
 232 def : Proc<"i486",            [FeatureSlowUAMem16]>;
 233 def : Proc<"i586",            [FeatureSlowUAMem16]>;
 234 def : Proc<"pentium",         [FeatureSlowUAMem16]>;
 235 def : Proc<"pentium-mmx",     [FeatureSlowUAMem16, FeatureMMX]>;
 236 def : Proc<"i686",            [FeatureSlowUAMem16]>;
 237 def : Proc<"pentiumpro",      [FeatureSlowUAMem16, FeatureCMOV]>;
 238 def : Proc<"pentium2",        [FeatureSlowUAMem16, FeatureMMX, FeatureCMOV,
 239                                FeatureFXSR]>;
 240 def : Proc<"pentium3",        [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
 241                                FeatureFXSR]>;
 242 def : Proc<"pentium3m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1,
 243                                FeatureFXSR, FeatureSlowBTMem]>;
 244 def : Proc<"pentium-m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
 245                                FeatureFXSR, FeatureSlowBTMem]>;
 246 def : Proc<"pentium4",        [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
 247                                FeatureFXSR]>;
 248 def : Proc<"pentium4m",       [FeatureSlowUAMem16, FeatureMMX, FeatureSSE2,
 249                                FeatureFXSR, FeatureSlowBTMem]>;
 250
 251 // Intel Core Duo.
 252 def : ProcessorModel<"yonah", SandyBridgeModel,
 253                      [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
 254                       FeatureSlowBTMem]>;
 255
 256 // NetBurst.
 257 def : Proc<"prescott",
 258            [FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR,
 259             FeatureSlowBTMem]>;
 260 def : Proc<"nocona", [
 261   FeatureSlowUAMem16,
 262   FeatureMMX,
 263   FeatureSSE3,
 264   FeatureFXSR,
 265   FeatureCMPXCHG16B,
 266   FeatureSlowBTMem
 267 ]>;
 268
 269 // Intel Core 2 Solo/Duo.
 270 def : ProcessorModel<"core2", SandyBridgeModel, [
 271   FeatureSlowUAMem16,
 272   FeatureMMX,
 273   FeatureSSSE3,
 274   FeatureFXSR,
 275   FeatureCMPXCHG16B,
 276   FeatureSlowBTMem
 277 ]>;
 278 def : ProcessorModel<"penryn", SandyBridgeModel, [
 279   FeatureSlowUAMem16,
 280   FeatureMMX,
 281   FeatureSSE41,
 282   FeatureFXSR,
 283   FeatureCMPXCHG16B,
 284   FeatureSlowBTMem
 285 ]>;
 286
 287 // Atom CPUs.
 288 class BonnellProc<string Name> : ProcessorModel<Name, AtomModel, [
 289   ProcIntelAtom,
 290   FeatureSlowUAMem16,
 291   FeatureMMX,
 292   FeatureSSSE3,
 293   FeatureFXSR,
 294   FeatureCMPXCHG16B,
 295   FeatureMOVBE,
 296   FeatureSlowBTMem,
 297   FeatureLEAForSP,
 298   FeatureSlowDivide32,
 299   FeatureSlowDivide64,
 300   FeatureCallRegIndirect,
 301   FeatureLEAUsesAG,
 302   FeaturePadShortFunctions
 303 ]>;
 304 def : BonnellProc<"bonnell">;
 305 def : BonnellProc<"atom">; // Pin the generic name to the baseline.
 306
 307 class SilvermontProc<string Name> : ProcessorModel<Name, SLMModel, [
 308   ProcIntelSLM,
 309   FeatureMMX,
 310   FeatureSSE42,
 311   FeatureFXSR,
 312   FeatureCMPXCHG16B,
 313   FeatureMOVBE,
 314   FeaturePOPCNT,
 315   FeaturePCLMUL,
 316   FeatureAES,
 317   FeatureSlowDivide64,
 318   FeatureCallRegIndirect,
 319   FeaturePRFCHW,
 320   FeatureSlowLEA,
 321   FeatureSlowIncDec,
 322   FeatureSlowBTMem
 323 ]>;
 324 def : SilvermontProc<"silvermont">;
 325 def : SilvermontProc<"slm">; // Legacy alias.
 326
 327 // "Arrandale" along with corei3 and corei5
 328 class NehalemProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 329   FeatureMMX,
 330   FeatureSSE42,
 331   FeatureFXSR,
 332   FeatureCMPXCHG16B,
 333   FeatureSlowBTMem,
 334   FeaturePOPCNT
 335 ]>;
 336 def : NehalemProc<"nehalem">;
 337 def : NehalemProc<"corei7">;
 338
 339 // Westmere is a similar machine to nehalem with some additional features.
 340 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
 341 class WestmereProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 342   FeatureMMX,
 343   FeatureSSE42,
 344   FeatureFXSR,
 345   FeatureCMPXCHG16B,
 346   FeatureSlowBTMem,
 347   FeaturePOPCNT,
 348   FeatureAES,
 349   FeaturePCLMUL
 350 ]>;
 351 def : WestmereProc<"westmere">;
 352
 353 // SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
 354 // rather than a superset.
 355 class SandyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 356   FeatureMMX,
 357   FeatureAVX,
 358   FeatureFXSR,
 359   FeatureCMPXCHG16B,
 360   FeatureSlowBTMem,
 361   FeatureSlowUAMem32,
 362   FeaturePOPCNT,
 363   FeatureAES,
 364   FeaturePCLMUL,
 365   FeatureXSAVE,
 366   FeatureXSAVEOPT
 367 ]>;
 368 def : SandyBridgeProc<"sandybridge">;
 369 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 370
 371 class IvyBridgeProc<string Name> : ProcessorModel<Name, SandyBridgeModel, [
 372   FeatureMMX,
 373   FeatureAVX,
 374   FeatureFXSR,
 375   FeatureCMPXCHG16B,
 376   FeatureSlowBTMem,
 377   FeatureSlowUAMem32,
 378   FeaturePOPCNT,
 379   FeatureAES,
 380   FeaturePCLMUL,
 381   FeatureXSAVE,
 382   FeatureXSAVEOPT,
 383   FeatureRDRAND,
 384   FeatureF16C,
 385   FeatureFSGSBase
 386 ]>;
 387 def : IvyBridgeProc<"ivybridge">;
 388 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 389
 390 class HaswellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 391   FeatureMMX,
 392   FeatureAVX2,
 393   FeatureFXSR,
 394   FeatureCMPXCHG16B,
 395   FeatureSlowBTMem,
 396   FeaturePOPCNT,
 397   FeatureAES,
 398   FeaturePCLMUL,
 399   FeatureRDRAND,
 400   FeatureXSAVE,
 401   FeatureXSAVEOPT,
 402   FeatureF16C,
 403   FeatureFSGSBase,
 404   FeatureMOVBE,
 405   FeatureLZCNT,
 406   FeatureBMI,
 407   FeatureBMI2,
 408   FeatureFMA,
 409   FeatureRTM,
 410   FeatureHLE,
 411   FeatureSlowIncDec
 412 ]>;
 413 def : HaswellProc<"haswell">;
 414 def : HaswellProc<"core-avx2">; // Legacy alias.
 415
 416 class BroadwellProc<string Name> : ProcessorModel<Name, HaswellModel, [
 417   FeatureMMX,
 418   FeatureAVX2,
 419   FeatureFXSR,
 420   FeatureCMPXCHG16B,
 421   FeatureSlowBTMem,
 422   FeaturePOPCNT,
 423   FeatureAES,
 424   FeaturePCLMUL,
 425   FeatureXSAVE,
 426   FeatureXSAVEOPT,
 427   FeatureRDRAND,
 428   FeatureF16C,
 429   FeatureFSGSBase,
 430   FeatureMOVBE,
 431   FeatureLZCNT,
 432   FeatureBMI,
 433   FeatureBMI2,
 434   FeatureFMA,
 435   FeatureRTM,
 436   FeatureHLE,
 437   FeatureADX,
 438   FeatureRDSEED,
 439   FeatureSlowIncDec
 440 ]>;
 441 def : BroadwellProc<"broadwell">;
 442
 443 // FIXME: define KNL model
 444 class KnightsLandingProc<string Name> : ProcessorModel<Name, HaswellModel, [
 445   FeatureMMX,
 446   FeatureAVX512,
 447   FeatureFXSR,
 448   FeatureERI,
 449   FeatureCDI,
 450   FeaturePFI,
 451   FeatureCMPXCHG16B,
 452   FeaturePOPCNT,
 453   FeatureAES,
 454   FeaturePCLMUL,
 455   FeatureXSAVE,
 456   FeatureXSAVEOPT,
 457   FeatureRDRAND,
 458   FeatureF16C,
 459   FeatureFSGSBase,
 460   FeatureMOVBE,
 461   FeatureLZCNT,
 462   FeatureBMI,
 463   FeatureBMI2,
 464   FeatureFMA,
 465   FeatureRTM,
 466   FeatureHLE,
 467   FeatureSlowIncDec,
 468   FeatureMPX
 469 ]>;
 470 def : KnightsLandingProc<"knl">;
 471
 472 // FIXME: define SKX model
 473 class SkylakeProc<string Name> : ProcessorModel<Name, HaswellModel, [
 474   FeatureMMX,
 475   FeatureAVX512,
 476   FeatureFXSR,
 477   FeatureCDI,
 478   FeatureDQI,
 479   FeatureBWI,
 480   FeatureVLX,
 481   FeatureCMPXCHG16B,
 482   FeatureSlowBTMem,
 483   FeaturePOPCNT,
 484   FeatureAES,
 485   FeaturePCLMUL,
 486   FeatureXSAVE,
 487   FeatureXSAVEOPT,
 488   FeatureRDRAND,
 489   FeatureF16C,
 490   FeatureFSGSBase,
 491   FeatureMOVBE,
 492   FeatureLZCNT,
 493   FeatureBMI,
 494   FeatureBMI2,
 495   FeatureFMA,
 496   FeatureRTM,
 497   FeatureHLE,
 498   FeatureADX,
 499   FeatureRDSEED,
 500   FeatureSlowIncDec,
 501   FeatureMPX,
 502   FeatureXSAVEC,
 503   FeatureXSAVES
 504 ]>;
 505 def : SkylakeProc<"skylake">;
 506 def : SkylakeProc<"skx">; // Legacy alias.
 507
 508
 509 // AMD CPUs.
 510
 511 def : Proc<"k6",              [FeatureSlowUAMem16, FeatureMMX]>;
 512 def : Proc<"k6-2",            [FeatureSlowUAMem16, Feature3DNow]>;
 513 def : Proc<"k6-3",            [FeatureSlowUAMem16, Feature3DNow]>;
 514 def : Proc<"athlon",          [FeatureSlowUAMem16, Feature3DNowA,
 515                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 516 def : Proc<"athlon-tbird",    [FeatureSlowUAMem16, Feature3DNowA,
 517                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 518 def : Proc<"athlon-4",        [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 519                                FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
 520 def : Proc<"athlon-xp",       [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 521                                FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
 522 def : Proc<"athlon-mp",       [FeatureSlowUAMem16, FeatureSSE1, Feature3DNowA,
 523                                FeatureFXSR, FeatureSlowBTMem, FeatureSlowSHLD]>;
 524 def : Proc<"k8",              [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
 525                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 526                                FeatureSlowSHLD]>;
 527 def : Proc<"opteron",         [FeatureSlowUAMem16, FeatureSSE2, Feature3DNowA,
 528                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 529                                FeatureSlowSHLD]>;
 530 def : Proc<"athlon64",        [FeatureSlowUAMem16, FeatureSSE2,   Feature3DNowA,
 531                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 532                                FeatureSlowSHLD]>;
 533 def : Proc<"athlon-fx",       [FeatureSlowUAMem16, FeatureSSE2,   Feature3DNowA,
 534                                FeatureFXSR, Feature64Bit, FeatureSlowBTMem,
 535                                FeatureSlowSHLD]>;
 536 def : Proc<"k8-sse3",         [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 537                                FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
 538                                FeatureSlowSHLD]>;
 539 def : Proc<"opteron-sse3",    [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 540                                FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
 541                                FeatureSlowSHLD]>;
 542 def : Proc<"athlon64-sse3",   [FeatureSlowUAMem16, FeatureSSE3,   Feature3DNowA,
 543                                FeatureFXSR, FeatureCMPXCHG16B, FeatureSlowBTMem,
 544                                FeatureSlowSHLD]>;
 545 def : Proc<"amdfam10",        [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
 546                                FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
 547                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 548 def : Proc<"barcelona",       [FeatureSSE4A, Feature3DNowA, FeatureFXSR,
 549                                FeatureCMPXCHG16B, FeatureLZCNT, FeaturePOPCNT,
 550                                FeatureSlowBTMem, FeatureSlowSHLD]>;
 551
 552 // Bobcat
 553 def : Proc<"btver1", [
 554   FeatureMMX,
 555   FeatureSSSE3,
 556   FeatureSSE4A,
 557   FeatureFXSR,
 558   FeatureCMPXCHG16B,
 559   FeaturePRFCHW,
 560   FeatureLZCNT,
 561   FeaturePOPCNT,
 562   FeatureXSAVE,
 563   FeatureSlowSHLD
 564 ]>;
 565
 566 // Jaguar
 567 def : ProcessorModel<"btver2", BtVer2Model, [
 568   FeatureMMX,
 569   FeatureAVX,
 570   FeatureFXSR,
 571   FeatureSSE4A,
 572   FeatureCMPXCHG16B,
 573   FeaturePRFCHW,
 574   FeatureAES,
 575   FeaturePCLMUL,
 576   FeatureBMI,
 577   FeatureF16C,
 578   FeatureMOVBE,
 579   FeatureLZCNT,
 580   FeaturePOPCNT,
 581   FeatureXSAVE,
 582   FeatureXSAVEOPT,
 583   FeatureSlowSHLD
 584 ]>;
 585
 586 // Bulldozer
 587 def : Proc<"bdver1", [
 588   FeatureXOP,
 589   FeatureFMA4,
 590   FeatureCMPXCHG16B,
 591   FeatureAES,
 592   FeaturePRFCHW,
 593   FeaturePCLMUL,
 594   FeatureMMX,
 595   FeatureAVX,
 596   FeatureFXSR,
 597   FeatureSSE4A,
 598   FeatureLZCNT,
 599   FeaturePOPCNT,
 600   FeatureXSAVE,
 601   FeatureSlowSHLD
 602 ]>;
 603 // Piledriver
 604 def : Proc<"bdver2", [
 605   FeatureXOP,
 606   FeatureFMA4,
 607   FeatureCMPXCHG16B,
 608   FeatureAES,
 609   FeaturePRFCHW,
 610   FeaturePCLMUL,
 611   FeatureMMX,
 612   FeatureAVX,
 613   FeatureFXSR,
 614   FeatureSSE4A,
 615   FeatureF16C,
 616   FeatureLZCNT,
 617   FeaturePOPCNT,
 618   FeatureXSAVE,
 619   FeatureBMI,
 620   FeatureTBM,
 621   FeatureFMA,
 622   FeatureSlowSHLD
 623 ]>;
 624
 625 // Steamroller
 626 def : Proc<"bdver3", [
 627   FeatureXOP,
 628   FeatureFMA4,
 629   FeatureCMPXCHG16B,
 630   FeatureAES,
 631   FeaturePRFCHW,
 632   FeaturePCLMUL,
 633   FeatureMMX,
 634   FeatureAVX,
 635   FeatureFXSR,
 636   FeatureSSE4A,
 637   FeatureF16C,
 638   FeatureLZCNT,
 639   FeaturePOPCNT,
 640   FeatureXSAVE,
 641   FeatureBMI,
 642   FeatureTBM,
 643   FeatureFMA,
 644   FeatureXSAVEOPT,
 645   FeatureSlowSHLD,
 646   FeatureFSGSBase
 647 ]>;
 648
 649 // Excavator
 650 def : Proc<"bdver4", [
 651   FeatureMMX,
 652   FeatureAVX2,
 653   FeatureFXSR,
 654   FeatureXOP,
 655   FeatureFMA4,
 656   FeatureCMPXCHG16B,
 657   FeatureAES,
 658   FeaturePRFCHW,
 659   FeaturePCLMUL,
 660   FeatureF16C,
 661   FeatureLZCNT,
 662   FeaturePOPCNT,
 663   FeatureXSAVE,
 664   FeatureBMI,
 665   FeatureBMI2,
 666   FeatureTBM,
 667   FeatureFMA,
 668   FeatureXSAVEOPT,
 669   FeatureFSGSBase
 670 ]>;
 671
 672 def : Proc<"geode",           [FeatureSlowUAMem16, Feature3DNowA]>;
 673
 674 def : Proc<"winchip-c6",      [FeatureSlowUAMem16, FeatureMMX]>;
 675 def : Proc<"winchip2",        [FeatureSlowUAMem16, Feature3DNow]>;
 676 def : Proc<"c3",              [FeatureSlowUAMem16, Feature3DNow]>;
 677 def : Proc<"c3-2", [FeatureSlowUAMem16, FeatureMMX, FeatureSSE1, FeatureFXSR]>;
 678
 679 // We also provide a generic 64-bit specific x86 processor model which tries to
 680 // be good for modern chips without enabling instruction set encodings past the
 681 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
 682 // modern 64-bit x86 chip, and enables features that are generally beneficial.
 683 //
 684 // We currently use the Sandy Bridge model as the default scheduling model as
 685 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
 686 // covers a huge swath of x86 processors. If there are specific scheduling
 687 // knobs which need to be tuned differently for AMD chips, we might consider
 688 // forming a common base for them.
 689 def : ProcessorModel<"x86-64", SandyBridgeModel,
 690                      [FeatureMMX, FeatureSSE2, FeatureFXSR, Feature64Bit,
 691                       FeatureSlowBTMem ]>;
 692
 693 //===----------------------------------------------------------------------===//
 694 // Register File Description
 695 //===----------------------------------------------------------------------===//
 696
 697 include "X86RegisterInfo.td"
 698
 699 //===----------------------------------------------------------------------===//
 700 // Instruction Descriptions
 701 //===----------------------------------------------------------------------===//
 702
 703 include "X86InstrInfo.td"
 704
 705 def X86InstrInfo : InstrInfo;
 706
 707 //===----------------------------------------------------------------------===//
 708 // Calling Conventions
 709 //===----------------------------------------------------------------------===//
 710
 711 include "X86CallingConv.td"
 712
 713
 714 //===----------------------------------------------------------------------===//
 715 // Assembly Parser
 716 //===----------------------------------------------------------------------===//
 717
 718 def ATTAsmParser : AsmParser {
 719   string AsmParserClassName = "AsmParser";
 720 }
 721
 722 def ATTAsmParserVariant : AsmParserVariant {
 723   int Variant = 0;
 724
 725   // Variant name.
 726   string Name = "att";
 727
 728   // Discard comments in assembly strings.
 729   string CommentDelimiter = "#";
 730
 731   // Recognize hard coded registers.
 732   string RegisterPrefix = "%";
 733 }
 734
 735 def IntelAsmParserVariant : AsmParserVariant {
 736   int Variant = 1;
 737
 738   // Variant name.
 739   string Name = "intel";
 740
 741   // Discard comments in assembly strings.
 742   string CommentDelimiter = ";";
 743
 744   // Recognize hard coded registers.
 745   string RegisterPrefix = "";
 746 }
 747
 748 //===----------------------------------------------------------------------===//
 749 // Assembly Printers
 750 //===----------------------------------------------------------------------===//
 751
 752 // The X86 target supports two different syntaxes for emitting machine code.
 753 // This is controlled by the -x86-asm-syntax={att|intel}
 754 def ATTAsmWriter : AsmWriter {
 755   string AsmWriterClassName  = "ATTInstPrinter";
 756   int Variant = 0;
 757 }
 758 def IntelAsmWriter : AsmWriter {
 759   string AsmWriterClassName  = "IntelInstPrinter";
 760   int Variant = 1;
 761 }
 762
 763 def X86 : Target {
 764   // Information about the instructions...
 765   let InstructionSet = X86InstrInfo;
 766   let AssemblyParsers = [ATTAsmParser];
 767   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
 768   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
 769 }