1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "X86MCTargetDesc.h"
15 #include "X86MCAsmInfo.h"
16 #include "InstPrinter/X86ATTInstPrinter.h"
17 #include "InstPrinter/X86IntelInstPrinter.h"
18 #include "llvm/MC/MachineLocation.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCInstrAnalysis.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/ADT/Triple.h"
26 #include "llvm/Support/Host.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/TargetRegistry.h"
30 #define GET_REGINFO_MC_DESC
31 #include "X86GenRegisterInfo.inc"
33 #define GET_INSTRINFO_MC_DESC
34 #include "X86GenInstrInfo.inc"
36 #define GET_SUBTARGETINFO_MC_DESC
37 #include "X86GenSubtargetInfo.inc"
46 std::string X86_MC::ParseX86Triple(StringRef TT) {
49 if (TheTriple.getArch() == Triple::x86_64)
56 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
57 /// specified arguments. If we can't run cpuid on the host, return true.
58 bool X86_MC::GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
59 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
60 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
62 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
63 asm ("movq\t%%rbx, %%rsi\n\t"
65 "xchgq\t%%rbx, %%rsi\n\t"
72 #elif defined(_MSC_VER)
74 __cpuid(registers, value);
83 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
85 asm ("movl\t%%ebx, %%esi\n\t"
87 "xchgl\t%%ebx, %%esi\n\t"
94 #elif defined(_MSC_VER)
99 mov dword ptr [esi],eax
101 mov dword ptr [esi],ebx
103 mov dword ptr [esi],ecx
105 mov dword ptr [esi],edx
116 /// GetCpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
117 /// 4 values in the specified arguments. If we can't run cpuid on the host,
119 bool X86_MC::GetCpuIDAndInfoEx(unsigned value, unsigned subleaf, unsigned *rEAX,
120 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
121 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
122 #if defined(__GNUC__)
123 // gcc desn't know cpuid would clobber ebx/rbx. Preseve it manually.
124 asm ("movq\t%%rbx, %%rsi\n\t"
126 "xchgq\t%%rbx, %%rsi\n\t"
134 #elif defined(_MSC_VER)
135 // __cpuidex was added in MSVC++ 9.0 SP1
136 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 && _MSC_FULL_VER >= 150030729)
138 __cpuidex(registers, value, subleaf);
139 *rEAX = registers[0];
140 *rEBX = registers[1];
141 *rECX = registers[2];
142 *rEDX = registers[3];
150 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
151 #if defined(__GNUC__)
152 asm ("movl\t%%ebx, %%esi\n\t"
154 "xchgl\t%%ebx, %%esi\n\t"
162 #elif defined(_MSC_VER)
168 mov dword ptr [esi],eax
170 mov dword ptr [esi],ebx
172 mov dword ptr [esi],ecx
174 mov dword ptr [esi],edx
185 void X86_MC::DetectFamilyModel(unsigned EAX, unsigned &Family,
187 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
188 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
189 if (Family == 6 || Family == 0xf) {
191 // Examine extended family ID if family ID is F.
192 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
193 // Examine extended model ID if family ID is 6 or F.
194 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
198 unsigned X86_MC::getDwarfRegFlavour(StringRef TT, bool isEH) {
199 Triple TheTriple(TT);
200 if (TheTriple.getArch() == Triple::x86_64)
201 return DWARFFlavour::X86_64;
203 if (TheTriple.isOSDarwin())
204 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
205 if (TheTriple.getOS() == Triple::MinGW32 ||
206 TheTriple.getOS() == Triple::Cygwin)
207 // Unsupported by now, just quick fallback
208 return DWARFFlavour::X86_32_Generic;
209 return DWARFFlavour::X86_32_Generic;
212 /// getX86RegNum - This function maps LLVM register identifiers to their X86
213 /// specific numbering, which is used in various places encoding instructions.
214 unsigned X86_MC::getX86RegNum(unsigned RegNo) {
216 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
217 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
218 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
219 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
220 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
222 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
224 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
226 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
229 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
231 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
233 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
235 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
237 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
239 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
241 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
243 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
246 case X86::ST0: return 0;
247 case X86::ST1: return 1;
248 case X86::ST2: return 2;
249 case X86::ST3: return 3;
250 case X86::ST4: return 4;
251 case X86::ST5: return 5;
252 case X86::ST6: return 6;
253 case X86::ST7: return 7;
255 case X86::XMM0: case X86::XMM8:
256 case X86::YMM0: case X86::YMM8: case X86::MM0:
258 case X86::XMM1: case X86::XMM9:
259 case X86::YMM1: case X86::YMM9: case X86::MM1:
261 case X86::XMM2: case X86::XMM10:
262 case X86::YMM2: case X86::YMM10: case X86::MM2:
264 case X86::XMM3: case X86::XMM11:
265 case X86::YMM3: case X86::YMM11: case X86::MM3:
267 case X86::XMM4: case X86::XMM12:
268 case X86::YMM4: case X86::YMM12: case X86::MM4:
270 case X86::XMM5: case X86::XMM13:
271 case X86::YMM5: case X86::YMM13: case X86::MM5:
273 case X86::XMM6: case X86::XMM14:
274 case X86::YMM6: case X86::YMM14: case X86::MM6:
276 case X86::XMM7: case X86::XMM15:
277 case X86::YMM7: case X86::YMM15: case X86::MM7:
280 case X86::ES: return 0;
281 case X86::CS: return 1;
282 case X86::SS: return 2;
283 case X86::DS: return 3;
284 case X86::FS: return 4;
285 case X86::GS: return 5;
287 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
288 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
289 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
290 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
291 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
292 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
293 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
294 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
296 // Pseudo index registers are equivalent to a "none"
297 // scaled index (See Intel Manual 2A, table 2-3)
303 assert((int(RegNo) > 0) && "Unknown physical register!");
308 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
309 // FIXME: TableGen these.
310 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
311 int SEH = X86_MC::getX86RegNum(Reg);
313 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
314 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
315 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
316 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
317 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
318 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
319 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
320 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
321 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
322 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
323 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
324 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
328 MRI->mapLLVMRegToSEHReg(Reg, SEH);
332 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(StringRef TT, StringRef CPU,
334 std::string ArchFS = X86_MC::ParseX86Triple(TT);
337 ArchFS = ArchFS + "," + FS.str();
342 std::string CPUName = CPU;
343 if (CPUName.empty()) {
344 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
345 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
346 CPUName = sys::getHostCPUName();
352 MCSubtargetInfo *X = new MCSubtargetInfo();
353 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
357 static MCInstrInfo *createX86MCInstrInfo() {
358 MCInstrInfo *X = new MCInstrInfo();
359 InitX86MCInstrInfo(X);
363 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
364 Triple TheTriple(TT);
365 unsigned RA = (TheTriple.getArch() == Triple::x86_64)
366 ? X86::RIP // Should have dwarf #16.
367 : X86::EIP; // Should have dwarf #8.
369 MCRegisterInfo *X = new MCRegisterInfo();
370 InitX86MCRegisterInfo(X, RA,
371 X86_MC::getDwarfRegFlavour(TT, false),
372 X86_MC::getDwarfRegFlavour(TT, true));
373 X86_MC::InitLLVM2SEHRegisterMapping(X);
377 static MCAsmInfo *createX86MCAsmInfo(const Target &T, StringRef TT) {
378 Triple TheTriple(TT);
379 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
382 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO) {
384 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
386 MAI = new X86MCAsmInfoDarwin(TheTriple);
387 } else if (TheTriple.getEnvironment() == Triple::ELF) {
388 // Force the use of an ELF container.
389 MAI = new X86ELFMCAsmInfo(TheTriple);
390 } else if (TheTriple.getOS() == Triple::Win32) {
391 MAI = new X86MCAsmInfoMicrosoft(TheTriple);
392 } else if (TheTriple.getOS() == Triple::MinGW32 || TheTriple.getOS() == Triple::Cygwin) {
393 MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
395 // The default is ELF.
396 MAI = new X86ELFMCAsmInfo(TheTriple);
399 // Initialize initial frame state.
400 // Calculate amount of bytes used for return address storing
401 int stackGrowth = is64Bit ? -8 : -4;
403 // Initial state of the frame pointer is esp+stackGrowth.
404 MachineLocation Dst(MachineLocation::VirtualFP);
405 MachineLocation Src(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
406 MAI->addInitialFrameState(0, Dst, Src);
408 // Add return address to move list
409 MachineLocation CSDst(is64Bit ? X86::RSP : X86::ESP, stackGrowth);
410 MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
411 MAI->addInitialFrameState(0, CSDst, CSSrc);
416 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
418 CodeGenOpt::Level OL) {
419 MCCodeGenInfo *X = new MCCodeGenInfo();
422 bool is64Bit = T.getArch() == Triple::x86_64;
424 if (RM == Reloc::Default) {
425 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
426 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
427 // use static relocation model by default.
428 if (T.isOSDarwin()) {
432 RM = Reloc::DynamicNoPIC;
433 } else if (T.isOSWindows() && is64Bit)
439 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
440 // is defined as a model for code which may be used in static or dynamic
441 // executables but not necessarily a shared library. On X86-32 we just
442 // compile in -static mode, in x86-64 we use PIC.
443 if (RM == Reloc::DynamicNoPIC) {
446 else if (!T.isOSDarwin())
450 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
451 // the Mach-O file format doesn't support it.
452 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
455 // For static codegen, if we're not already set, use Small codegen.
456 if (CM == CodeModel::Default)
457 CM = CodeModel::Small;
458 else if (CM == CodeModel::JITDefault)
459 // 64-bit JIT places everything in the same buffer except external funcs.
460 CM = is64Bit ? CodeModel::Large : CodeModel::Small;
462 X->InitMCCodeGenInfo(RM, CM, OL);
466 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
467 MCContext &Ctx, MCAsmBackend &MAB,
469 MCCodeEmitter *_Emitter,
472 Triple TheTriple(TT);
474 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
475 return createMachOStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll);
477 if (TheTriple.isOSWindows() && TheTriple.getEnvironment() != Triple::ELF)
478 return createWinCOFFStreamer(Ctx, MAB, *_Emitter, _OS, RelaxAll);
480 return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack);
483 static MCInstPrinter *createX86MCInstPrinter(const Target &T,
484 unsigned SyntaxVariant,
485 const MCAsmInfo &MAI,
486 const MCInstrInfo &MII,
487 const MCRegisterInfo &MRI,
488 const MCSubtargetInfo &STI) {
489 if (SyntaxVariant == 0)
490 return new X86ATTInstPrinter(MAI, MII, MRI);
491 if (SyntaxVariant == 1)
492 return new X86IntelInstPrinter(MAI, MII, MRI);
496 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
497 return new MCInstrAnalysis(Info);
500 // Force static initialization.
501 extern "C" void LLVMInitializeX86TargetMC() {
502 // Register the MC asm info.
503 RegisterMCAsmInfoFn A(TheX86_32Target, createX86MCAsmInfo);
504 RegisterMCAsmInfoFn B(TheX86_64Target, createX86MCAsmInfo);
506 // Register the MC codegen info.
507 RegisterMCCodeGenInfoFn C(TheX86_32Target, createX86MCCodeGenInfo);
508 RegisterMCCodeGenInfoFn D(TheX86_64Target, createX86MCCodeGenInfo);
510 // Register the MC instruction info.
511 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
512 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
514 // Register the MC register info.
515 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
516 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
518 // Register the MC subtarget info.
519 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
520 X86_MC::createX86MCSubtargetInfo);
521 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
522 X86_MC::createX86MCSubtargetInfo);
524 // Register the MC instruction analyzer.
525 TargetRegistry::RegisterMCInstrAnalysis(TheX86_32Target,
526 createX86MCInstrAnalysis);
527 TargetRegistry::RegisterMCInstrAnalysis(TheX86_64Target,
528 createX86MCInstrAnalysis);
530 // Register the code emitter.
531 TargetRegistry::RegisterMCCodeEmitter(TheX86_32Target,
532 createX86MCCodeEmitter);
533 TargetRegistry::RegisterMCCodeEmitter(TheX86_64Target,
534 createX86MCCodeEmitter);
536 // Register the asm backend.
537 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
538 createX86_32AsmBackend);
539 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
540 createX86_64AsmBackend);
542 // Register the object streamer.
543 TargetRegistry::RegisterMCObjectStreamer(TheX86_32Target,
545 TargetRegistry::RegisterMCObjectStreamer(TheX86_64Target,
548 // Register the MCInstPrinter.
549 TargetRegistry::RegisterMCInstPrinter(TheX86_32Target,
550 createX86MCInstPrinter);
551 TargetRegistry::RegisterMCInstPrinter(TheX86_64Target,
552 createX86MCInstPrinter);