1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "X86MCTargetDesc.h"
15 #include "InstPrinter/X86ATTInstPrinter.h"
16 #include "InstPrinter/X86IntelInstPrinter.h"
17 #include "X86MCAsmInfo.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCInstrAnalysis.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MachineLocation.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/Host.h"
28 #include "llvm/Support/TargetRegistry.h"
36 #define GET_REGINFO_MC_DESC
37 #include "X86GenRegisterInfo.inc"
39 #define GET_INSTRINFO_MC_DESC
40 #include "X86GenInstrInfo.inc"
42 #define GET_SUBTARGETINFO_MC_DESC
43 #include "X86GenSubtargetInfo.inc"
45 std::string X86_MC::ParseX86Triple(const Triple &TT) {
47 if (TT.getArch() == Triple::x86_64)
48 FS = "+64bit-mode,-32bit-mode,-16bit-mode";
49 else if (TT.getEnvironment() != Triple::CODE16)
50 FS = "-64bit-mode,+32bit-mode,-16bit-mode";
52 FS = "-64bit-mode,-32bit-mode,+16bit-mode";
57 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
58 if (TT.getArch() == Triple::x86_64)
59 return DWARFFlavour::X86_64;
62 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
64 // Unsupported by now, just quick fallback
65 return DWARFFlavour::X86_32_Generic;
66 return DWARFFlavour::X86_32_Generic;
69 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
70 // FIXME: TableGen these.
71 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
72 unsigned SEH = MRI->getEncodingValue(Reg);
73 MRI->mapLLVMRegToSEHReg(Reg, SEH);
77 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
78 StringRef CPU, StringRef FS) {
79 std::string ArchFS = X86_MC::ParseX86Triple(TT);
82 ArchFS = (Twine(ArchFS) + "," + FS).str();
87 std::string CPUName = CPU;
91 return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
94 static MCInstrInfo *createX86MCInstrInfo() {
95 MCInstrInfo *X = new MCInstrInfo();
96 InitX86MCInstrInfo(X);
100 static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
101 unsigned RA = (TT.getArch() == Triple::x86_64)
102 ? X86::RIP // Should have dwarf #16.
103 : X86::EIP; // Should have dwarf #8.
105 MCRegisterInfo *X = new MCRegisterInfo();
106 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
107 X86_MC::getDwarfRegFlavour(TT, true), RA);
108 X86_MC::InitLLVM2SEHRegisterMapping(X);
112 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
113 const Triple &TheTriple) {
114 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
117 if (TheTriple.isOSBinFormatMachO()) {
119 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
121 MAI = new X86MCAsmInfoDarwin(TheTriple);
122 } else if (TheTriple.isOSBinFormatELF()) {
123 // Force the use of an ELF container.
124 MAI = new X86ELFMCAsmInfo(TheTriple);
125 } else if (TheTriple.isWindowsMSVCEnvironment() ||
126 TheTriple.isWindowsCoreCLREnvironment()) {
127 MAI = new X86MCAsmInfoMicrosoft(TheTriple);
128 } else if (TheTriple.isOSCygMing() ||
129 TheTriple.isWindowsItaniumEnvironment()) {
130 MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
132 // The default is ELF.
133 MAI = new X86ELFMCAsmInfo(TheTriple);
136 // Initialize initial frame state.
137 // Calculate amount of bytes used for return address storing
138 int stackGrowth = is64Bit ? -8 : -4;
140 // Initial state of the frame pointer is esp+stackGrowth.
141 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
142 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
143 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
144 MAI->addInitialFrameState(Inst);
146 // Add return address to move list
147 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
148 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
149 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
150 MAI->addInitialFrameState(Inst2);
155 static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM,
157 CodeGenOpt::Level OL) {
158 MCCodeGenInfo *X = new MCCodeGenInfo();
160 bool is64Bit = TT.getArch() == Triple::x86_64;
162 if (RM == Reloc::Default) {
163 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
164 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
165 // use static relocation model by default.
166 if (TT.isOSDarwin()) {
170 RM = Reloc::DynamicNoPIC;
171 } else if (TT.isOSWindows() && is64Bit)
177 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
178 // is defined as a model for code which may be used in static or dynamic
179 // executables but not necessarily a shared library. On X86-32 we just
180 // compile in -static mode, in x86-64 we use PIC.
181 if (RM == Reloc::DynamicNoPIC) {
184 else if (!TT.isOSDarwin())
188 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
189 // the Mach-O file format doesn't support it.
190 if (RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
193 // For static codegen, if we're not already set, use Small codegen.
194 if (CM == CodeModel::Default)
195 CM = CodeModel::Small;
196 else if (CM == CodeModel::JITDefault)
197 // 64-bit JIT places everything in the same buffer except external funcs.
198 CM = is64Bit ? CodeModel::Large : CodeModel::Small;
200 X->initMCCodeGenInfo(RM, CM, OL);
204 static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
205 unsigned SyntaxVariant,
206 const MCAsmInfo &MAI,
207 const MCInstrInfo &MII,
208 const MCRegisterInfo &MRI) {
209 if (SyntaxVariant == 0)
210 return new X86ATTInstPrinter(MAI, MII, MRI);
211 if (SyntaxVariant == 1)
212 return new X86IntelInstPrinter(MAI, MII, MRI);
216 static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
218 if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64)
219 return createX86_64MachORelocationInfo(Ctx);
220 else if (TheTriple.isOSBinFormatELF())
221 return createX86_64ELFRelocationInfo(Ctx);
222 // Default to the stock relocation info.
223 return llvm::createMCRelocationInfo(TheTriple, Ctx);
226 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
227 return new MCInstrAnalysis(Info);
230 // Force static initialization.
231 extern "C" void LLVMInitializeX86TargetMC() {
232 for (Target *T : {&TheX86_32Target, &TheX86_64Target}) {
233 // Register the MC asm info.
234 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
236 // Register the MC codegen info.
237 RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo);
239 // Register the MC instruction info.
240 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
242 // Register the MC register info.
243 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);
245 // Register the MC subtarget info.
246 TargetRegistry::RegisterMCSubtargetInfo(*T,
247 X86_MC::createX86MCSubtargetInfo);
249 // Register the MC instruction analyzer.
250 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis);
252 // Register the code emitter.
253 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);
255 // Register the object streamer.
256 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer);
258 // Register the MCInstPrinter.
259 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter);
261 // Register the MC relocation info.
262 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
265 // Register the asm backend.
266 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
267 createX86_32AsmBackend);
268 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
269 createX86_64AsmBackend);
272 unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
279 default: return getX86SubSuperRegisterOrZero(Reg, 64);
280 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
282 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
284 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
286 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
288 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
290 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
292 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
294 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
300 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
302 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
304 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
306 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
308 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
310 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
312 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
314 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
316 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
318 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
320 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
322 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
324 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
326 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
328 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
330 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
337 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
339 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
341 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
343 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
345 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
347 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
349 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
351 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
353 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
355 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
357 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
359 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
361 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
363 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
365 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
367 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
373 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
375 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
377 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
379 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
381 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
383 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
385 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
387 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
389 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
391 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
393 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
395 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
397 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
399 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
401 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
403 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
409 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
411 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
413 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
415 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
417 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
419 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
421 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
423 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
425 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
427 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
429 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
431 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
433 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
435 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
437 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
439 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
445 unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) {
446 unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
447 assert(Res != 0 && "Unexpected register or VT");