1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides X86 specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #include "X86MCTargetDesc.h"
15 #include "InstPrinter/X86ATTInstPrinter.h"
16 #include "InstPrinter/X86IntelInstPrinter.h"
17 #include "X86MCAsmInfo.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/MC/MCCodeGenInfo.h"
20 #include "llvm/MC/MCInstrAnalysis.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCStreamer.h"
24 #include "llvm/MC/MCSubtargetInfo.h"
25 #include "llvm/MC/MachineLocation.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/Host.h"
28 #include "llvm/Support/TargetRegistry.h"
36 #define GET_REGINFO_MC_DESC
37 #include "X86GenRegisterInfo.inc"
39 #define GET_INSTRINFO_MC_DESC
40 #include "X86GenInstrInfo.inc"
42 #define GET_SUBTARGETINFO_MC_DESC
43 #include "X86GenSubtargetInfo.inc"
45 std::string X86_MC::ParseX86Triple(const Triple &TT) {
47 if (TT.getArch() == Triple::x86_64)
48 FS = "+64bit-mode,-32bit-mode,-16bit-mode";
49 else if (TT.getEnvironment() != Triple::CODE16)
50 FS = "-64bit-mode,+32bit-mode,-16bit-mode";
52 FS = "-64bit-mode,-32bit-mode,+16bit-mode";
57 unsigned X86_MC::getDwarfRegFlavour(Triple TT, bool isEH) {
58 if (TT.getArch() == Triple::x86_64)
59 return DWARFFlavour::X86_64;
62 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
64 // Unsupported by now, just quick fallback
65 return DWARFFlavour::X86_32_Generic;
66 return DWARFFlavour::X86_32_Generic;
69 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
70 // FIXME: TableGen these.
71 for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
72 unsigned SEH = MRI->getEncodingValue(Reg);
73 MRI->mapLLVMRegToSEHReg(Reg, SEH);
77 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
78 StringRef CPU, StringRef FS) {
79 std::string ArchFS = X86_MC::ParseX86Triple(TT);
82 ArchFS = (Twine(ArchFS) + "," + FS).str();
87 std::string CPUName = CPU;
91 MCSubtargetInfo *X = new MCSubtargetInfo();
92 InitX86MCSubtargetInfo(X, TT, CPUName, ArchFS);
96 static MCInstrInfo *createX86MCInstrInfo() {
97 MCInstrInfo *X = new MCInstrInfo();
98 InitX86MCInstrInfo(X);
102 static MCRegisterInfo *createX86MCRegisterInfo(StringRef TT) {
103 Triple TheTriple(TT);
104 unsigned RA = (TheTriple.getArch() == Triple::x86_64)
105 ? X86::RIP // Should have dwarf #16.
106 : X86::EIP; // Should have dwarf #8.
108 MCRegisterInfo *X = new MCRegisterInfo();
109 InitX86MCRegisterInfo(X, RA,
110 X86_MC::getDwarfRegFlavour(TheTriple, false),
111 X86_MC::getDwarfRegFlavour(TheTriple, true),
113 X86_MC::InitLLVM2SEHRegisterMapping(X);
117 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
118 const Triple &TheTriple) {
119 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
122 if (TheTriple.isOSBinFormatMachO()) {
124 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
126 MAI = new X86MCAsmInfoDarwin(TheTriple);
127 } else if (TheTriple.isOSBinFormatELF()) {
128 // Force the use of an ELF container.
129 MAI = new X86ELFMCAsmInfo(TheTriple);
130 } else if (TheTriple.isWindowsMSVCEnvironment()) {
131 MAI = new X86MCAsmInfoMicrosoft(TheTriple);
132 } else if (TheTriple.isOSCygMing() ||
133 TheTriple.isWindowsItaniumEnvironment()) {
134 MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
136 // The default is ELF.
137 MAI = new X86ELFMCAsmInfo(TheTriple);
140 // Initialize initial frame state.
141 // Calculate amount of bytes used for return address storing
142 int stackGrowth = is64Bit ? -8 : -4;
144 // Initial state of the frame pointer is esp+stackGrowth.
145 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
146 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
147 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
148 MAI->addInitialFrameState(Inst);
150 // Add return address to move list
151 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
152 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
153 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
154 MAI->addInitialFrameState(Inst2);
159 static MCCodeGenInfo *createX86MCCodeGenInfo(StringRef TT, Reloc::Model RM,
161 CodeGenOpt::Level OL) {
162 MCCodeGenInfo *X = new MCCodeGenInfo();
165 bool is64Bit = T.getArch() == Triple::x86_64;
167 if (RM == Reloc::Default) {
168 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
169 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
170 // use static relocation model by default.
171 if (T.isOSDarwin()) {
175 RM = Reloc::DynamicNoPIC;
176 } else if (T.isOSWindows() && is64Bit)
182 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
183 // is defined as a model for code which may be used in static or dynamic
184 // executables but not necessarily a shared library. On X86-32 we just
185 // compile in -static mode, in x86-64 we use PIC.
186 if (RM == Reloc::DynamicNoPIC) {
189 else if (!T.isOSDarwin())
193 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
194 // the Mach-O file format doesn't support it.
195 if (RM == Reloc::Static && T.isOSDarwin() && is64Bit)
198 // For static codegen, if we're not already set, use Small codegen.
199 if (CM == CodeModel::Default)
200 CM = CodeModel::Small;
201 else if (CM == CodeModel::JITDefault)
202 // 64-bit JIT places everything in the same buffer except external funcs.
203 CM = is64Bit ? CodeModel::Large : CodeModel::Small;
205 X->initMCCodeGenInfo(RM, CM, OL);
209 static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
210 unsigned SyntaxVariant,
211 const MCAsmInfo &MAI,
212 const MCInstrInfo &MII,
213 const MCRegisterInfo &MRI) {
214 if (SyntaxVariant == 0)
215 return new X86ATTInstPrinter(MAI, MII, MRI);
216 if (SyntaxVariant == 1)
217 return new X86IntelInstPrinter(MAI, MII, MRI);
221 static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
223 if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64)
224 return createX86_64MachORelocationInfo(Ctx);
225 else if (TheTriple.isOSBinFormatELF())
226 return createX86_64ELFRelocationInfo(Ctx);
227 // Default to the stock relocation info.
228 return llvm::createMCRelocationInfo(TheTriple, Ctx);
231 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
232 return new MCInstrAnalysis(Info);
235 // Force static initialization.
236 extern "C" void LLVMInitializeX86TargetMC() {
237 for (Target *T : {&TheX86_32Target, &TheX86_64Target}) {
238 // Register the MC asm info.
239 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
241 // Register the MC codegen info.
242 RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo);
244 // Register the MC instruction info.
245 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
247 // Register the MC register info.
248 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);
250 // Register the MC subtarget info.
251 TargetRegistry::RegisterMCSubtargetInfo(*T,
252 X86_MC::createX86MCSubtargetInfo);
254 // Register the MC instruction analyzer.
255 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis);
257 // Register the code emitter.
258 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);
260 // Register the object streamer.
261 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer);
263 // Register the MCInstPrinter.
264 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter);
266 // Register the MC relocation info.
267 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
270 // Register the asm backend.
271 TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
272 createX86_32AsmBackend);
273 TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
274 createX86_64AsmBackend);