1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains small standalone helper functions and enum definitions for
11 // the X86 target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
18 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
20 #include "X86MCTargetDesc.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/Support/DataTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
28 // Enums for memory operand decoding. Each memory operand is represented with
29 // a 5 operand sequence in the form:
30 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment]
31 // These enums help decode this.
38 /// AddrSegmentReg - The operand # of the segment in the memory operand.
41 /// AddrNumOperands - Total number of operands in a memory reference.
45 /// AVX512 static rounding constants. These need to match the values in
47 enum STATIC_ROUNDING {
54 } // end namespace X86;
56 /// X86II - This namespace holds all of the target specific flags that
57 /// instruction info tracks.
60 /// Target Operand Flag enum.
62 //===------------------------------------------------------------------===//
63 // X86 Specific MachineOperand flags.
67 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
69 /// SYMBOL_LABEL + [. - PICBASELABEL]
70 MO_GOT_ABSOLUTE_ADDRESS,
72 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
73 /// immediate should get the value of the symbol minus the PIC base label:
74 /// SYMBOL_LABEL - PICBASELABEL
77 /// MO_GOT - On a symbol operand this indicates that the immediate is the
78 /// offset to the GOT entry for the symbol name from the base of the GOT.
80 /// See the X86-64 ELF ABI supplement for more details.
84 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
85 /// the offset to the location of the symbol name from the base of the GOT.
87 /// See the X86-64 ELF ABI supplement for more details.
88 /// SYMBOL_LABEL @GOTOFF
91 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
92 /// offset to the GOT entry for the symbol name from the current code
95 /// See the X86-64 ELF ABI supplement for more details.
96 /// SYMBOL_LABEL @GOTPCREL
99 /// MO_PLT - On a symbol operand this indicates that the immediate is
100 /// offset to the PLT entry of symbol name from the current code location.
102 /// See the X86-64 ELF ABI supplement for more details.
103 /// SYMBOL_LABEL @PLT
106 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
107 /// the offset of the GOT entry with the TLS index structure that contains
108 /// the module number and variable offset for the symbol. Used in the
109 /// general dynamic TLS access model.
111 /// See 'ELF Handling for Thread-Local Storage' for more details.
112 /// SYMBOL_LABEL @TLSGD
115 /// MO_TLSLD - On a symbol operand this indicates that the immediate is
116 /// the offset of the GOT entry with the TLS index for the module that
117 /// contains the symbol. When this index is passed to a call to
118 /// __tls_get_addr, the function will return the base address of the TLS
119 /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
121 /// See 'ELF Handling for Thread-Local Storage' for more details.
122 /// SYMBOL_LABEL @TLSLD
125 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
126 /// the offset of the GOT entry with the TLS index for the module that
127 /// contains the symbol. When this index is passed to a call to
128 /// ___tls_get_addr, the function will return the base address of the TLS
129 /// block for the symbol. Used in the IA32 local dynamic TLS access model.
131 /// See 'ELF Handling for Thread-Local Storage' for more details.
132 /// SYMBOL_LABEL @TLSLDM
135 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
136 /// the offset of the GOT entry with the thread-pointer offset for the
137 /// symbol. Used in the x86-64 initial exec TLS access model.
139 /// See 'ELF Handling for Thread-Local Storage' for more details.
140 /// SYMBOL_LABEL @GOTTPOFF
143 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
144 /// the absolute address of the GOT entry with the negative thread-pointer
145 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
148 /// See 'ELF Handling for Thread-Local Storage' for more details.
149 /// SYMBOL_LABEL @INDNTPOFF
152 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
153 /// the thread-pointer offset for the symbol. Used in the x86-64 local
154 /// exec TLS access model.
156 /// See 'ELF Handling for Thread-Local Storage' for more details.
157 /// SYMBOL_LABEL @TPOFF
160 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
161 /// the offset of the GOT entry with the TLS offset of the symbol. Used
162 /// in the local dynamic TLS access model.
164 /// See 'ELF Handling for Thread-Local Storage' for more details.
165 /// SYMBOL_LABEL @DTPOFF
168 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
169 /// the negative thread-pointer offset for the symbol. Used in the IA32
170 /// local exec TLS access model.
172 /// See 'ELF Handling for Thread-Local Storage' for more details.
173 /// SYMBOL_LABEL @NTPOFF
176 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
177 /// the offset of the GOT entry with the negative thread-pointer offset for
178 /// the symbol. Used in the PIC IA32 initial exec TLS access model.
180 /// See 'ELF Handling for Thread-Local Storage' for more details.
181 /// SYMBOL_LABEL @GOTNTPOFF
184 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
185 /// reference is actually to the "__imp_FOO" symbol. This is used for
186 /// dllimport linkage on windows.
189 /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
190 /// reference is actually to the "FOO$stub" symbol. This is used for calls
191 /// and jumps to external functions on Tiger and earlier.
194 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
195 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
196 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
199 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
200 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
201 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
202 MO_DARWIN_NONLAZY_PIC_BASE,
204 /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
205 /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
206 /// which is a PIC-base-relative reference to a hidden dyld lazy pointer
208 MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE,
210 /// MO_TLVP - On a symbol operand this indicates that the immediate is
213 /// This is the TLS offset for the Darwin TLS mechanism.
216 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
217 /// is some TLS offset from the picbase.
219 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
222 /// MO_SECREL - On a symbol operand this indicates that the immediate is
223 /// the offset from beginning of section.
225 /// This is the TLS offset for the COFF/Windows TLS mechanism.
230 //===------------------------------------------------------------------===//
231 // Instruction encodings. These are the standard/most common forms for X86
235 // PseudoFrm - This represents an instruction that is a pseudo instruction
236 // or one that has not been implemented yet. It is illegal to code generate
237 // it, but tolerated for intermediate implementation stages.
240 /// Raw - This form is for instructions that don't have any operands, so
241 /// they are just a fixed opcode value, like 'leave'.
244 /// AddRegFrm - This form is used for instructions like 'push r32' that have
245 /// their one register operand added to their opcode.
248 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
249 /// to specify a destination, which in this case is a register.
253 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
254 /// to specify a destination, which in this case is memory.
258 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
259 /// to specify a source, which in this case is a register.
263 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
264 /// to specify a source, which in this case is memory.
268 /// RawFrmMemOffs - This form is for instructions that store an absolute
269 /// memory offset as an immediate with a possible segment override.
272 /// RawFrmSrc - This form is for instructions that use the source index
273 /// register SI/ESI/RSI with a possible segment override.
276 /// RawFrmDst - This form is for instructions that use the destination index
277 /// register DI/EDI/ESI.
280 /// RawFrmSrc - This form is for instructions that use the source index
281 /// register SI/ESI/ERI with a possible segment override, and also the
282 /// destination index register DI/ESI/RDI.
285 /// RawFrmImm8 - This is used for the ENTER instruction, which has two
286 /// immediates, the first of which is a 16-bit immediate (specified by
287 /// the imm encoding) and the second is a 8-bit fixed value.
290 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
291 /// immediates, the first of which is a 16 or 32-bit immediate (specified by
292 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD
293 /// manual, this operand is described as pntr16:32 and pntr16:16
296 /// MRMX[rm] - The forms are used to represent instructions that use a
297 /// Mod/RM byte, and don't use the middle field for anything.
298 MRMXr = 14, MRMXm = 15,
300 /// MRM[0-7][rm] - These forms are used to represent instructions that use
301 /// a Mod/RM byte, and use the middle field to hold extended opcode
302 /// information. In the intel manual these are represented as /0, /1, ...
305 // First, instructions that operate on a register r/m operand...
306 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
307 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
309 // Next, instructions that operate on a memory r/m operand...
310 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
311 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
313 //// MRM_XX - A mod/rm byte of exactly 0xXX.
314 MRM_C0 = 32, MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35,
315 MRM_C4 = 36, MRM_C5 = 37, MRM_C6 = 38, MRM_C7 = 39,
316 MRM_C8 = 40, MRM_C9 = 41, MRM_CA = 42, MRM_CB = 43,
317 MRM_CC = 44, MRM_CD = 45, MRM_CE = 46, MRM_CF = 47,
318 MRM_D0 = 48, MRM_D1 = 49, MRM_D2 = 50, MRM_D3 = 51,
319 MRM_D4 = 52, MRM_D5 = 53, MRM_D6 = 54, MRM_D7 = 55,
320 MRM_D8 = 56, MRM_D9 = 57, MRM_DA = 58, MRM_DB = 59,
321 MRM_DC = 60, MRM_DD = 61, MRM_DE = 62, MRM_DF = 63,
322 MRM_E0 = 64, MRM_E1 = 65, MRM_E2 = 66, MRM_E3 = 67,
323 MRM_E4 = 68, MRM_E5 = 69, MRM_E6 = 70, MRM_E7 = 71,
324 MRM_E8 = 72, MRM_E9 = 73, MRM_EA = 74, MRM_EB = 75,
325 MRM_EC = 76, MRM_ED = 77, MRM_EE = 78, MRM_EF = 79,
326 MRM_F0 = 80, MRM_F1 = 81, MRM_F2 = 82, MRM_F3 = 83,
327 MRM_F4 = 84, MRM_F5 = 85, MRM_F6 = 86, MRM_F7 = 87,
328 MRM_F8 = 88, MRM_F9 = 89, MRM_FA = 90, MRM_FB = 91,
329 MRM_FC = 92, MRM_FD = 93, MRM_FE = 94, MRM_FF = 95,
333 //===------------------------------------------------------------------===//
336 // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
337 // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
338 // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
339 // prefix in 16-bit mode.
341 OpSizeMask = 0x3 << OpSizeShift,
343 OpSizeFixed = 0 << OpSizeShift,
344 OpSize16 = 1 << OpSizeShift,
345 OpSize32 = 2 << OpSizeShift,
347 // AsSize - AdSizeX implies this instruction determines its need of 0x67
348 // prefix from a normal ModRM memory operand. The other types indicate that
349 // an operand is encoded with a specific width and a prefix is needed if
350 // it differs from the current mode.
351 AdSizeShift = OpSizeShift + 2,
352 AdSizeMask = 0x3 << AdSizeShift,
354 AdSizeX = 1 << AdSizeShift,
355 AdSize16 = 1 << AdSizeShift,
356 AdSize32 = 2 << AdSizeShift,
357 AdSize64 = 3 << AdSizeShift,
359 //===------------------------------------------------------------------===//
360 // OpPrefix - There are several prefix bytes that are used as opcode
361 // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
364 OpPrefixShift = AdSizeShift + 2,
365 OpPrefixMask = 0x7 << OpPrefixShift,
367 // PS, PD - Prefix code for packed single and double precision vector
368 // floating point operations performed in the SSE registers.
369 PS = 1 << OpPrefixShift, PD = 2 << OpPrefixShift,
371 // XS, XD - These prefix codes are for single and double precision scalar
372 // floating point operations performed in the SSE registers.
373 XS = 3 << OpPrefixShift, XD = 4 << OpPrefixShift,
375 //===------------------------------------------------------------------===//
376 // OpMap - This field determines which opcode map this instruction
377 // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
379 OpMapShift = OpPrefixShift + 3,
380 OpMapMask = 0x7 << OpMapShift,
382 // OB - OneByte - Set if this instruction has a one byte opcode.
383 OB = 0 << OpMapShift,
385 // TB - TwoByte - Set if this instruction has a two byte opcode, which
386 // starts with a 0x0F byte before the real opcode.
387 TB = 1 << OpMapShift,
389 // T8, TA - Prefix after the 0x0F prefix.
390 T8 = 2 << OpMapShift, TA = 3 << OpMapShift,
392 // XOP8 - Prefix to include use of imm byte.
393 XOP8 = 4 << OpMapShift,
395 // XOP9 - Prefix to exclude use of imm byte.
396 XOP9 = 5 << OpMapShift,
398 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
399 XOPA = 6 << OpMapShift,
401 //===------------------------------------------------------------------===//
402 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
403 // They are used to specify GPRs and SSE registers, 64-bit operand size,
404 // etc. We only cares about REX.W and REX.R bits and only the former is
405 // statically determined.
407 REXShift = OpMapShift + 3,
408 REX_W = 1 << REXShift,
410 //===------------------------------------------------------------------===//
411 // This three-bit field describes the size of an immediate operand. Zero is
412 // unused so that we can tell if we forgot to set a value.
413 ImmShift = REXShift + 1,
414 ImmMask = 15 << ImmShift,
415 Imm8 = 1 << ImmShift,
416 Imm8PCRel = 2 << ImmShift,
417 Imm16 = 3 << ImmShift,
418 Imm16PCRel = 4 << ImmShift,
419 Imm32 = 5 << ImmShift,
420 Imm32PCRel = 6 << ImmShift,
421 Imm32S = 7 << ImmShift,
422 Imm64 = 8 << ImmShift,
424 //===------------------------------------------------------------------===//
425 // FP Instruction Classification... Zero is non-fp instruction.
427 // FPTypeMask - Mask for all of the FP types...
428 FPTypeShift = ImmShift + 4,
429 FPTypeMask = 7 << FPTypeShift,
431 // NotFP - The default, set for instructions that do not use FP registers.
432 NotFP = 0 << FPTypeShift,
434 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
435 ZeroArgFP = 1 << FPTypeShift,
437 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
438 OneArgFP = 2 << FPTypeShift,
440 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
441 // result back to ST(0). For example, fcos, fsqrt, etc.
443 OneArgFPRW = 3 << FPTypeShift,
445 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
446 // explicit argument, storing the result to either ST(0) or the implicit
447 // argument. For example: fadd, fsub, fmul, etc...
448 TwoArgFP = 4 << FPTypeShift,
450 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
451 // explicit argument, but have no destination. Example: fucom, fucomi, ...
452 CompareFP = 5 << FPTypeShift,
454 // CondMovFP - "2 operand" floating point conditional move instructions.
455 CondMovFP = 6 << FPTypeShift,
457 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
458 SpecialFP = 7 << FPTypeShift,
461 LOCKShift = FPTypeShift + 3,
462 LOCK = 1 << LOCKShift,
465 REPShift = LOCKShift + 1,
468 // Execution domain for SSE instructions.
469 // 0 means normal, non-SSE instruction.
470 SSEDomainShift = REPShift + 1,
473 EncodingShift = SSEDomainShift + 2,
474 EncodingMask = 0x3 << EncodingShift,
476 // VEX - encoding using 0xC4/0xC5
477 VEX = 1 << EncodingShift,
479 /// XOP - Opcode prefix used by XOP instructions.
480 XOP = 2 << EncodingShift,
482 // VEX_EVEX - Specifies that this instruction use EVEX form which provides
483 // syntax support up to 32 512-bit register operands and up to 7 16-bit
484 // mask operands as well as source operand data swizzling/memory operand
485 // conversion, eviction hint, and rounding mode.
486 EVEX = 3 << EncodingShift,
489 OpcodeShift = EncodingShift + 2,
491 /// VEX_W - Has a opcode specific functionality, but is used in the same
492 /// way as REX_W is for regular SSE instructions.
493 VEX_WShift = OpcodeShift + 8,
494 VEX_W = 1ULL << VEX_WShift,
496 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
497 /// address instructions in SSE are represented as 3 address ones in AVX
498 /// and the additional register is encoded in VEX_VVVV prefix.
499 VEX_4VShift = VEX_WShift + 1,
500 VEX_4V = 1ULL << VEX_4VShift,
502 /// VEX_4VOp3 - Similar to VEX_4V, but used on instructions that encode
503 /// operand 3 with VEX.vvvv.
504 VEX_4VOp3Shift = VEX_4VShift + 1,
505 VEX_4VOp3 = 1ULL << VEX_4VOp3Shift,
507 /// VEX_I8IMM - Specifies that the last register used in a AVX instruction,
508 /// must be encoded in the i8 immediate field. This usually happens in
509 /// instructions with 4 operands.
510 VEX_I8IMMShift = VEX_4VOp3Shift + 1,
511 VEX_I8IMM = 1ULL << VEX_I8IMMShift,
513 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
514 /// instruction uses 256-bit wide registers. This is usually auto detected
515 /// if a VR256 register is used, but some AVX instructions also have this
516 /// field marked when using a f256 memory references.
517 VEX_LShift = VEX_I8IMMShift + 1,
518 VEX_L = 1ULL << VEX_LShift,
520 // VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX
521 // prefix. Usually used for scalar instructions. Needed by disassembler.
522 VEX_LIGShift = VEX_LShift + 1,
523 VEX_LIG = 1ULL << VEX_LIGShift,
525 // TODO: we should combine VEX_L and VEX_LIG together to form a 2-bit field
526 // with following encoding:
530 // - 11 LIG (but, in insn encoding, leave VEX.L and EVEX.L in zeros.
531 // this will save 1 tsflag bit
533 // EVEX_K - Set if this instruction requires masking
534 EVEX_KShift = VEX_LIGShift + 1,
535 EVEX_K = 1ULL << EVEX_KShift,
537 // EVEX_Z - Set if this instruction has EVEX.Z field set.
538 EVEX_ZShift = EVEX_KShift + 1,
539 EVEX_Z = 1ULL << EVEX_ZShift,
541 // EVEX_L2 - Set if this instruction has EVEX.L' field set.
542 EVEX_L2Shift = EVEX_ZShift + 1,
543 EVEX_L2 = 1ULL << EVEX_L2Shift,
545 // EVEX_B - Set if this instruction has EVEX.B field set.
546 EVEX_BShift = EVEX_L2Shift + 1,
547 EVEX_B = 1ULL << EVEX_BShift,
549 // The scaling factor for the AVX512's 8-bit compressed displacement.
550 CD8_Scale_Shift = EVEX_BShift + 1,
551 CD8_Scale_Mask = 127ULL << CD8_Scale_Shift,
553 /// Has3DNow0F0FOpcode - This flag indicates that the instruction uses the
554 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents
555 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
556 /// storing a classifier in the imm8 field. To simplify our implementation,
557 /// we handle this by storeing the classifier in the opcode field and using
558 /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
559 Has3DNow0F0FOpcodeShift = CD8_Scale_Shift + 7,
560 Has3DNow0F0FOpcode = 1ULL << Has3DNow0F0FOpcodeShift,
562 /// MemOp4 - Used to indicate swapping of operand 3 and 4 to be encoded in
563 /// ModRM or I8IMM. This is used for FMA4 and XOP instructions.
564 MemOp4Shift = Has3DNow0F0FOpcodeShift + 1,
565 MemOp4 = 1ULL << MemOp4Shift,
567 /// Explicitly specified rounding control
568 EVEX_RCShift = MemOp4Shift + 1,
569 EVEX_RC = 1ULL << EVEX_RCShift
572 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
573 // specified machine instruction.
575 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
576 return TSFlags >> X86II::OpcodeShift;
579 inline bool hasImm(uint64_t TSFlags) {
580 return (TSFlags & X86II::ImmMask) != 0;
583 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
584 /// of the specified instruction.
585 inline unsigned getSizeOfImm(uint64_t TSFlags) {
586 switch (TSFlags & X86II::ImmMask) {
587 default: llvm_unreachable("Unknown immediate size");
589 case X86II::Imm8PCRel: return 1;
591 case X86II::Imm16PCRel: return 2;
594 case X86II::Imm32PCRel: return 4;
595 case X86II::Imm64: return 8;
599 /// isImmPCRel - Return true if the immediate of the specified instruction's
600 /// TSFlags indicates that it is pc relative.
601 inline unsigned isImmPCRel(uint64_t TSFlags) {
602 switch (TSFlags & X86II::ImmMask) {
603 default: llvm_unreachable("Unknown immediate size");
604 case X86II::Imm8PCRel:
605 case X86II::Imm16PCRel:
606 case X86II::Imm32PCRel:
617 /// isImmSigned - Return true if the immediate of the specified instruction's
618 /// TSFlags indicates that it is signed.
619 inline unsigned isImmSigned(uint64_t TSFlags) {
620 switch (TSFlags & X86II::ImmMask) {
621 default: llvm_unreachable("Unknown immediate signedness");
625 case X86II::Imm8PCRel:
627 case X86II::Imm16PCRel:
629 case X86II::Imm32PCRel:
635 /// getOperandBias - compute any additional adjustment needed to
636 /// the offset to the start of the memory operand
637 /// in this instruction.
638 /// If this is a two-address instruction,skip one of the register operands.
639 /// FIXME: This should be handled during MCInst lowering.
640 inline int getOperandBias(const MCInstrDesc& Desc)
642 unsigned NumOps = Desc.getNumOperands();
644 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
646 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
647 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
648 // Special case for AVX-512 GATHER with 2 TIED_TO operands
649 // Skip the first 2 operands: dst, mask_wb
651 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
652 Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1)
653 // Special case for GATHER with 2 TIED_TO operands
654 // Skip the first 2 operands: dst, mask_wb
656 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps - 2, MCOI::TIED_TO) == 0)
662 /// getMemoryOperandNo - The function returns the MCInst operand # for the
663 /// first field of the memory operand. If the instruction doesn't have a
664 /// memory operand, this returns -1.
666 /// Note that this ignores tied operands. If there is a tied register which
667 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
668 /// counted as one operand.
670 inline int getMemoryOperandNo(uint64_t TSFlags, unsigned Opcode) {
671 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
672 bool HasMemOp4 = TSFlags & X86II::MemOp4;
673 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
675 switch (TSFlags & X86II::FormMask) {
676 default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
679 case X86II::AddRegFrm:
680 case X86II::MRMDestReg:
681 case X86II::MRMSrcReg:
682 case X86II::RawFrmImm8:
683 case X86II::RawFrmImm16:
684 case X86II::RawFrmMemOffs:
685 case X86II::RawFrmSrc:
686 case X86II::RawFrmDst:
687 case X86II::RawFrmDstSrc:
689 case X86II::MRMDestMem:
691 case X86II::MRMSrcMem:
692 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
694 return 1 + HasVEX_4V + HasMemOp4 + HasEVEX_K;
696 case X86II::MRM0r: case X86II::MRM1r:
697 case X86II::MRM2r: case X86II::MRM3r:
698 case X86II::MRM4r: case X86II::MRM5r:
699 case X86II::MRM6r: case X86II::MRM7r:
702 case X86II::MRM0m: case X86II::MRM1m:
703 case X86II::MRM2m: case X86II::MRM3m:
704 case X86II::MRM4m: case X86II::MRM5m:
705 case X86II::MRM6m: case X86II::MRM7m:
706 // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
707 return 0 + HasVEX_4V + HasEVEX_K;
708 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
709 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5:
710 case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8:
711 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
712 case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE:
713 case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
714 case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4:
715 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7:
716 case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
717 case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
718 case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
719 case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3:
720 case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6:
721 case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9:
722 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
723 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF:
724 case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2:
725 case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5:
726 case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8:
727 case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB:
728 case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE:
734 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or
735 /// higher) register? e.g. r8, xmm8, xmm13, etc.
736 inline bool isX86_64ExtendedReg(unsigned RegNo) {
737 if ((RegNo > X86::XMM7 && RegNo <= X86::XMM15) ||
738 (RegNo > X86::XMM23 && RegNo <= X86::XMM31) ||
739 (RegNo > X86::YMM7 && RegNo <= X86::YMM15) ||
740 (RegNo > X86::YMM23 && RegNo <= X86::YMM31) ||
741 (RegNo > X86::ZMM7 && RegNo <= X86::ZMM15) ||
742 (RegNo > X86::ZMM23 && RegNo <= X86::ZMM31))
747 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
748 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
749 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
750 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
751 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
752 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
753 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
754 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
755 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11:
756 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15:
762 /// is32ExtendedReg - Is the MemoryOperand a 32 extended (zmm16 or higher)
763 /// registers? e.g. zmm21, etc.
764 static inline bool is32ExtendedReg(unsigned RegNo) {
765 return ((RegNo > X86::XMM15 && RegNo <= X86::XMM31) ||
766 (RegNo > X86::YMM15 && RegNo <= X86::YMM31) ||
767 (RegNo > X86::ZMM15 && RegNo <= X86::ZMM31));
771 inline bool isX86_64NonExtLowByteReg(unsigned reg) {
772 return (reg == X86::SPL || reg == X86::BPL ||
773 reg == X86::SIL || reg == X86::DIL);
777 } // end namespace llvm;