1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCAsmBackend.h"
11 #include "MCTargetDesc/X86BaseInfo.h"
12 #include "MCTargetDesc/X86FixupKinds.h"
13 #include "llvm/ADT/Twine.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCELFObjectWriter.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCFixupKindInfo.h"
18 #include "llvm/MC/MCMachObjectWriter.h"
19 #include "llvm/MC/MCObjectWriter.h"
20 #include "llvm/MC/MCSectionCOFF.h"
21 #include "llvm/MC/MCSectionELF.h"
22 #include "llvm/MC/MCSectionMachO.h"
23 #include "llvm/Object/MachOFormat.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/ELF.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/Target/TargetRegistry.h"
31 // Option to allow disabling arithmetic relaxation to workaround PR9807, which
32 // is useful when running bitwise comparison experiments on Darwin. We should be
33 // able to remove this once PR9807 is resolved.
35 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
36 cl::desc("Disable relaxation of arithmetic instruction for X86"));
38 static unsigned getFixupKindLog2Size(unsigned Kind) {
40 default: assert(0 && "invalid fixup kind!");
42 case FK_Data_1: return 0;
44 case FK_Data_2: return 1;
46 case X86::reloc_riprel_4byte:
47 case X86::reloc_riprel_4byte_movq_load:
48 case X86::reloc_signed_4byte:
49 case X86::reloc_global_offset_table:
50 case FK_Data_4: return 2;
52 case FK_Data_8: return 3;
58 class X86ELFObjectWriter : public MCELFObjectTargetWriter {
60 X86ELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine,
61 bool HasRelocationAddend)
62 : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, HasRelocationAddend) {}
65 class X86AsmBackend : public MCAsmBackend {
67 X86AsmBackend(const Target &T)
70 unsigned getNumFixupKinds() const {
71 return X86::NumTargetFixupKinds;
74 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
75 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
76 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
77 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
78 { "reloc_signed_4byte", 0, 4 * 8, 0},
79 { "reloc_global_offset_table", 0, 4 * 8, 0}
82 if (Kind < FirstTargetFixupKind)
83 return MCAsmBackend::getFixupKindInfo(Kind);
85 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
87 return Infos[Kind - FirstTargetFixupKind];
90 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
91 uint64_t Value) const {
92 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
94 assert(Fixup.getOffset() + Size <= DataSize &&
95 "Invalid fixup offset!");
97 // Check that the upper bits are either all 0 or all 1's
100 assert((isInt<8>(Value) || isUInt<8>(Value)) &&
101 "Value does not fit in a 1Byte Reloc");
104 assert((isInt<16>(Value) || isUInt<16>(Value)) &&
105 "Value does not fit in a 2Byte Reloc");
108 assert((isInt<32>(Value) || isUInt<32>(Value)) &&
109 "Value does not fit in a 4Byte Reloc");
113 for (unsigned i = 0; i != Size; ++i)
114 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
117 bool MayNeedRelaxation(const MCInst &Inst) const;
119 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
121 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
123 } // end anonymous namespace
125 static unsigned getRelaxedOpcodeBranch(unsigned Op) {
130 case X86::JAE_1: return X86::JAE_4;
131 case X86::JA_1: return X86::JA_4;
132 case X86::JBE_1: return X86::JBE_4;
133 case X86::JB_1: return X86::JB_4;
134 case X86::JE_1: return X86::JE_4;
135 case X86::JGE_1: return X86::JGE_4;
136 case X86::JG_1: return X86::JG_4;
137 case X86::JLE_1: return X86::JLE_4;
138 case X86::JL_1: return X86::JL_4;
139 case X86::JMP_1: return X86::JMP_4;
140 case X86::JNE_1: return X86::JNE_4;
141 case X86::JNO_1: return X86::JNO_4;
142 case X86::JNP_1: return X86::JNP_4;
143 case X86::JNS_1: return X86::JNS_4;
144 case X86::JO_1: return X86::JO_4;
145 case X86::JP_1: return X86::JP_4;
146 case X86::JS_1: return X86::JS_4;
150 static unsigned getRelaxedOpcodeArith(unsigned Op) {
156 case X86::IMUL16rri8: return X86::IMUL16rri;
157 case X86::IMUL16rmi8: return X86::IMUL16rmi;
158 case X86::IMUL32rri8: return X86::IMUL32rri;
159 case X86::IMUL32rmi8: return X86::IMUL32rmi;
160 case X86::IMUL64rri8: return X86::IMUL64rri32;
161 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
164 case X86::AND16ri8: return X86::AND16ri;
165 case X86::AND16mi8: return X86::AND16mi;
166 case X86::AND32ri8: return X86::AND32ri;
167 case X86::AND32mi8: return X86::AND32mi;
168 case X86::AND64ri8: return X86::AND64ri32;
169 case X86::AND64mi8: return X86::AND64mi32;
172 case X86::OR16ri8: return X86::OR16ri;
173 case X86::OR16mi8: return X86::OR16mi;
174 case X86::OR32ri8: return X86::OR32ri;
175 case X86::OR32mi8: return X86::OR32mi;
176 case X86::OR64ri8: return X86::OR64ri32;
177 case X86::OR64mi8: return X86::OR64mi32;
180 case X86::XOR16ri8: return X86::XOR16ri;
181 case X86::XOR16mi8: return X86::XOR16mi;
182 case X86::XOR32ri8: return X86::XOR32ri;
183 case X86::XOR32mi8: return X86::XOR32mi;
184 case X86::XOR64ri8: return X86::XOR64ri32;
185 case X86::XOR64mi8: return X86::XOR64mi32;
188 case X86::ADD16ri8: return X86::ADD16ri;
189 case X86::ADD16mi8: return X86::ADD16mi;
190 case X86::ADD32ri8: return X86::ADD32ri;
191 case X86::ADD32mi8: return X86::ADD32mi;
192 case X86::ADD64ri8: return X86::ADD64ri32;
193 case X86::ADD64mi8: return X86::ADD64mi32;
196 case X86::SUB16ri8: return X86::SUB16ri;
197 case X86::SUB16mi8: return X86::SUB16mi;
198 case X86::SUB32ri8: return X86::SUB32ri;
199 case X86::SUB32mi8: return X86::SUB32mi;
200 case X86::SUB64ri8: return X86::SUB64ri32;
201 case X86::SUB64mi8: return X86::SUB64mi32;
204 case X86::CMP16ri8: return X86::CMP16ri;
205 case X86::CMP16mi8: return X86::CMP16mi;
206 case X86::CMP32ri8: return X86::CMP32ri;
207 case X86::CMP32mi8: return X86::CMP32mi;
208 case X86::CMP64ri8: return X86::CMP64ri32;
209 case X86::CMP64mi8: return X86::CMP64mi32;
212 case X86::PUSHi8: return X86::PUSHi32;
213 case X86::PUSHi16: return X86::PUSHi32;
214 case X86::PUSH64i8: return X86::PUSH64i32;
215 case X86::PUSH64i16: return X86::PUSH64i32;
219 static unsigned getRelaxedOpcode(unsigned Op) {
220 unsigned R = getRelaxedOpcodeArith(Op);
223 return getRelaxedOpcodeBranch(Op);
226 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
227 // Branches can always be relaxed.
228 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
231 if (MCDisableArithRelaxation)
234 // Check if this instruction is ever relaxable.
235 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
239 // Check if it has an expression and is not RIP relative.
242 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
243 const MCOperand &Op = Inst.getOperand(i);
247 if (Op.isReg() && Op.getReg() == X86::RIP)
251 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
252 // how we do relaxations?
253 return hasExp && !hasRIP;
256 // FIXME: Can tblgen help at all here to verify there aren't other instructions
258 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
259 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
260 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
262 if (RelaxedOp == Inst.getOpcode()) {
263 SmallString<256> Tmp;
264 raw_svector_ostream OS(Tmp);
265 Inst.dump_pretty(OS);
267 report_fatal_error("unexpected instruction to relax: " + OS.str());
271 Res.setOpcode(RelaxedOp);
274 /// WriteNopData - Write optimal nops to the output file for the \arg Count
275 /// bytes. This returns the number of bytes written. It may return 0 if
276 /// the \arg Count is more than the maximum optimal nops.
277 bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
278 static const uint8_t Nops[10][10] = {
286 {0x0f, 0x1f, 0x40, 0x00},
287 // nopl 0(%[re]ax,%[re]ax,1)
288 {0x0f, 0x1f, 0x44, 0x00, 0x00},
289 // nopw 0(%[re]ax,%[re]ax,1)
290 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
292 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
293 // nopl 0L(%[re]ax,%[re]ax,1)
294 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
295 // nopw 0L(%[re]ax,%[re]ax,1)
296 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
297 // nopw %cs:0L(%[re]ax,%[re]ax,1)
298 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
301 // Write an optimal sequence for the first 15 bytes.
302 const uint64_t OptimalCount = (Count < 16) ? Count : 15;
303 const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
304 for (uint64_t i = 0, e = Prefixes; i != e; i++)
306 const uint64_t Rest = OptimalCount - Prefixes;
307 for (uint64_t i = 0, e = Rest; i != e; i++)
308 OW->Write8(Nops[Rest - 1][i]);
310 // Finish with single byte nops.
311 for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
320 class ELFX86AsmBackend : public X86AsmBackend {
322 Triple::OSType OSType;
323 ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
324 : X86AsmBackend(T), OSType(_OSType) {
325 HasReliableSymbolDifference = true;
328 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
329 const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
330 return ES.getFlags() & ELF::SHF_MERGE;
334 class ELFX86_32AsmBackend : public ELFX86AsmBackend {
336 ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
337 : ELFX86AsmBackend(T, OSType) {}
339 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
340 return createELFObjectWriter(createELFObjectTargetWriter(),
341 OS, /*IsLittleEndian*/ true);
344 MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
345 return new X86ELFObjectWriter(false, OSType, ELF::EM_386, false);
349 class ELFX86_64AsmBackend : public ELFX86AsmBackend {
351 ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
352 : ELFX86AsmBackend(T, OSType) {}
354 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
355 return createELFObjectWriter(createELFObjectTargetWriter(),
356 OS, /*IsLittleEndian*/ true);
359 MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
360 return new X86ELFObjectWriter(true, OSType, ELF::EM_X86_64, true);
364 class WindowsX86AsmBackend : public X86AsmBackend {
368 WindowsX86AsmBackend(const Target &T, bool is64Bit)
373 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
374 return createWinCOFFObjectWriter(OS, Is64Bit);
378 class DarwinX86AsmBackend : public X86AsmBackend {
380 DarwinX86AsmBackend(const Target &T)
381 : X86AsmBackend(T) { }
384 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
386 DarwinX86_32AsmBackend(const Target &T)
387 : DarwinX86AsmBackend(T) {}
389 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
390 return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
391 object::mach::CTM_i386,
392 object::mach::CSX86_ALL);
396 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
398 DarwinX86_64AsmBackend(const Target &T)
399 : DarwinX86AsmBackend(T) {
400 HasReliableSymbolDifference = true;
403 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
404 return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
405 object::mach::CTM_x86_64,
406 object::mach::CSX86_ALL);
409 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
410 // Temporary labels in the string literals sections require symbols. The
411 // issue is that the x86_64 relocation format does not allow symbol +
412 // offset, and so the linker does not have enough information to resolve the
413 // access to the appropriate atom unless an external relocation is used. For
414 // non-cstring sections, we expect the compiler to use a non-temporary label
415 // for anything that could have an addend pointing outside the symbol.
417 // See <rdar://problem/4765733>.
418 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
419 return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
422 virtual bool isSectionAtomizable(const MCSection &Section) const {
423 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
424 // Fixed sized data sections are uniqued, they cannot be diced into atoms.
425 switch (SMO.getType()) {
429 case MCSectionMachO::S_4BYTE_LITERALS:
430 case MCSectionMachO::S_8BYTE_LITERALS:
431 case MCSectionMachO::S_16BYTE_LITERALS:
432 case MCSectionMachO::S_LITERAL_POINTERS:
433 case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
434 case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
435 case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
436 case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
437 case MCSectionMachO::S_INTERPOSING:
443 } // end anonymous namespace
445 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, StringRef TT) {
446 Triple TheTriple(TT);
448 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
449 return new DarwinX86_32AsmBackend(T);
451 if (TheTriple.isOSWindows())
452 return new WindowsX86AsmBackend(T, false);
454 return new ELFX86_32AsmBackend(T, TheTriple.getOS());
457 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, StringRef TT) {
458 Triple TheTriple(TT);
460 if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
461 return new DarwinX86_64AsmBackend(T);
463 if (TheTriple.isOSWindows())
464 return new WindowsX86AsmBackend(T, true);
466 return new ELFX86_64AsmBackend(T, TheTriple.getOS());