1 //===-- X86IntelInstPrinter.cpp - AT&T assembly instruction printing ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as AT&T-style
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "X86IntelInstPrinter.h"
17 #include "X86InstComments.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/FormattedStream.h"
23 #include "X86GenInstrNames.inc"
27 // Include the auto-generated portion of the assembly writer.
28 #define GET_INSTRUCTION_NAME
29 #include "X86GenAsmWriter1.inc"
31 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
32 printInstruction(MI, OS);
34 // If verbose assembly is enabled, we can print some informative comments.
36 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
38 StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
39 return getInstructionName(Opcode);
42 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
44 switch (MI->getOperand(Op).getImm()) {
45 default: assert(0 && "Invalid ssecc argument!");
46 case 0: O << "eq"; break;
47 case 1: O << "lt"; break;
48 case 2: O << "le"; break;
49 case 3: O << "unord"; break;
50 case 4: O << "neq"; break;
51 case 5: O << "nlt"; break;
52 case 6: O << "nle"; break;
53 case 7: O << "ord"; break;
57 /// print_pcrel_imm - This is used to print an immediate value that ends up
58 /// being encoded as a pc-relative value.
59 void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
61 const MCOperand &Op = MI->getOperand(OpNo);
65 assert(Op.isExpr() && "unknown pcrel immediate operand");
70 static void PrintRegName(raw_ostream &O, StringRef RegName) {
71 for (unsigned i = 0, e = RegName.size(); i != e; ++i)
72 O << (char)toupper(RegName[i]);
75 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
77 const MCOperand &Op = MI->getOperand(OpNo);
79 PrintRegName(O, getRegisterName(Op.getReg()));
80 } else if (Op.isImm()) {
83 assert(Op.isExpr() && "unknown operand kind in printOperand");
88 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
90 const MCOperand &BaseReg = MI->getOperand(Op);
91 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
92 const MCOperand &IndexReg = MI->getOperand(Op+2);
93 const MCOperand &DispSpec = MI->getOperand(Op+3);
94 const MCOperand &SegReg = MI->getOperand(Op+4);
96 // If this has a segment register, print it.
97 if (SegReg.getReg()) {
98 printOperand(MI, Op+4, O);
104 bool NeedPlus = false;
105 if (BaseReg.getReg()) {
106 printOperand(MI, Op, O);
110 if (IndexReg.getReg()) {
111 if (NeedPlus) O << " + ";
113 O << ScaleVal << '*';
114 printOperand(MI, Op+2, O);
119 if (!DispSpec.isImm()) {
120 if (NeedPlus) O << " + ";
121 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
122 O << *DispSpec.getExpr();
124 int64_t DispVal = DispSpec.getImm();
125 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {