1 //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as Intel-style
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "X86IntelInstPrinter.h"
17 #include "MCTargetDesc/X86BaseInfo.h"
18 #include "MCTargetDesc/X86MCTargetDesc.h"
19 #include "X86InstComments.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/FormattedStream.h"
28 #include "X86GenAsmWriter1.inc"
30 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
31 OS << getRegisterName(RegNo);
34 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
36 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
37 uint64_t TSFlags = Desc.TSFlags;
39 if (TSFlags & X86II::LOCK)
42 printInstruction(MI, OS);
44 // Next always print the annotation.
45 printAnnotation(OS, Annot);
47 // If verbose assembly is enabled, we can print some informative comments.
49 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
52 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
54 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
56 default: llvm_unreachable("Invalid ssecc argument!");
57 case 0: O << "eq"; break;
58 case 1: O << "lt"; break;
59 case 2: O << "le"; break;
60 case 3: O << "unord"; break;
61 case 4: O << "neq"; break;
62 case 5: O << "nlt"; break;
63 case 6: O << "nle"; break;
64 case 7: O << "ord"; break;
65 case 8: O << "eq_uq"; break;
66 case 9: O << "nge"; break;
67 case 0xa: O << "ngt"; break;
68 case 0xb: O << "false"; break;
69 case 0xc: O << "neq_oq"; break;
70 case 0xd: O << "ge"; break;
71 case 0xe: O << "gt"; break;
72 case 0xf: O << "true"; break;
76 void X86IntelInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
78 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
80 default: llvm_unreachable("Invalid avxcc argument!");
81 case 0: O << "eq"; break;
82 case 1: O << "lt"; break;
83 case 2: O << "le"; break;
84 case 3: O << "unord"; break;
85 case 4: O << "neq"; break;
86 case 5: O << "nlt"; break;
87 case 6: O << "nle"; break;
88 case 7: O << "ord"; break;
89 case 8: O << "eq_uq"; break;
90 case 9: O << "nge"; break;
91 case 0xa: O << "ngt"; break;
92 case 0xb: O << "false"; break;
93 case 0xc: O << "neq_oq"; break;
94 case 0xd: O << "ge"; break;
95 case 0xe: O << "gt"; break;
96 case 0xf: O << "true"; break;
97 case 0x10: O << "eq_os"; break;
98 case 0x11: O << "lt_oq"; break;
99 case 0x12: O << "le_oq"; break;
100 case 0x13: O << "unord_s"; break;
101 case 0x14: O << "neq_us"; break;
102 case 0x15: O << "nlt_uq"; break;
103 case 0x16: O << "nle_uq"; break;
104 case 0x17: O << "ord_s"; break;
105 case 0x18: O << "eq_us"; break;
106 case 0x19: O << "nge_uq"; break;
107 case 0x1a: O << "ngt_uq"; break;
108 case 0x1b: O << "false_os"; break;
109 case 0x1c: O << "neq_os"; break;
110 case 0x1d: O << "ge_oq"; break;
111 case 0x1e: O << "gt_oq"; break;
112 case 0x1f: O << "true_us"; break;
116 void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
118 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
120 case 0: O << "{rn-sae}"; break;
121 case 1: O << "{rd-sae}"; break;
122 case 2: O << "{ru-sae}"; break;
123 case 3: O << "{rz-sae}"; break;
125 default: llvm_unreachable("Invalid AVX-512 rounding control argument!");
129 /// printPCRelImm - This is used to print an immediate value that ends up
130 /// being encoded as a pc-relative value.
131 void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
133 const MCOperand &Op = MI->getOperand(OpNo);
135 O << formatImm(Op.getImm());
137 assert(Op.isExpr() && "unknown pcrel immediate operand");
138 // If a symbolic branch target was added as a constant expression then print
139 // that address in hex.
140 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
142 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
143 O << formatHex((uint64_t)Address);
146 // Otherwise, just print the expression.
152 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
154 const MCOperand &Op = MI->getOperand(OpNo);
156 printRegName(O, Op.getReg());
157 } else if (Op.isImm()) {
158 O << formatImm((int64_t)Op.getImm());
160 assert(Op.isExpr() && "unknown operand kind in printOperand");
165 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
167 const MCOperand &BaseReg = MI->getOperand(Op);
168 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
169 const MCOperand &IndexReg = MI->getOperand(Op+2);
170 const MCOperand &DispSpec = MI->getOperand(Op+3);
171 const MCOperand &SegReg = MI->getOperand(Op+4);
173 // If this has a segment register, print it.
174 if (SegReg.getReg()) {
175 printOperand(MI, Op+4, O);
181 bool NeedPlus = false;
182 if (BaseReg.getReg()) {
183 printOperand(MI, Op, O);
187 if (IndexReg.getReg()) {
188 if (NeedPlus) O << " + ";
190 O << ScaleVal << '*';
191 printOperand(MI, Op+2, O);
195 if (!DispSpec.isImm()) {
196 if (NeedPlus) O << " + ";
197 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
198 O << *DispSpec.getExpr();
200 int64_t DispVal = DispSpec.getImm();
201 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
210 O << formatImm(DispVal);
217 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
219 const MCOperand &DispSpec = MI->getOperand(Op);
223 if (DispSpec.isImm()) {
224 O << formatImm(DispSpec.getImm());
226 assert(DispSpec.isExpr() && "non-immediate displacement?");
227 O << *DispSpec.getExpr();