1 //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as Intel-style
13 //===----------------------------------------------------------------------===//
15 #include "X86IntelInstPrinter.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "MCTargetDesc/X86MCTargetDesc.h"
18 #include "X86InstComments.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/FormattedStream.h"
27 #define DEBUG_TYPE "asm-printer"
29 #include "X86GenAsmWriter1.inc"
31 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
32 OS << getRegisterName(RegNo);
35 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
37 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
38 uint64_t TSFlags = Desc.TSFlags;
40 if (TSFlags & X86II::LOCK)
43 printInstruction(MI, OS);
45 // Next always print the annotation.
46 printAnnotation(OS, Annot);
48 // If verbose assembly is enabled, we can print some informative comments.
50 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
53 static void printSSEAVXCC(int64_t Imm, raw_ostream &O) {
55 default: llvm_unreachable("Invalid avxcc argument!");
56 case 0: O << "eq"; break;
57 case 1: O << "lt"; break;
58 case 2: O << "le"; break;
59 case 3: O << "unord"; break;
60 case 4: O << "neq"; break;
61 case 5: O << "nlt"; break;
62 case 6: O << "nle"; break;
63 case 7: O << "ord"; break;
64 case 8: O << "eq_uq"; break;
65 case 9: O << "nge"; break;
66 case 0xa: O << "ngt"; break;
67 case 0xb: O << "false"; break;
68 case 0xc: O << "neq_oq"; break;
69 case 0xd: O << "ge"; break;
70 case 0xe: O << "gt"; break;
71 case 0xf: O << "true"; break;
72 case 0x10: O << "eq_os"; break;
73 case 0x11: O << "lt_oq"; break;
74 case 0x12: O << "le_oq"; break;
75 case 0x13: O << "unord_s"; break;
76 case 0x14: O << "neq_us"; break;
77 case 0x15: O << "nlt_uq"; break;
78 case 0x16: O << "nle_uq"; break;
79 case 0x17: O << "ord_s"; break;
80 case 0x18: O << "eq_us"; break;
81 case 0x19: O << "nge_uq"; break;
82 case 0x1a: O << "ngt_uq"; break;
83 case 0x1b: O << "false_os"; break;
84 case 0x1c: O << "neq_os"; break;
85 case 0x1d: O << "ge_oq"; break;
86 case 0x1e: O << "gt_oq"; break;
87 case 0x1f: O << "true_us"; break;
91 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
93 int64_t Imm = MI->getOperand(Op).getImm() & 0x7;
94 printSSEAVXCC(Imm, O);
97 void X86IntelInstPrinter::printAVXCC(const MCInst *MI, unsigned Op,
99 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
100 printSSEAVXCC(Imm, O);
103 void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
105 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
107 case 0: O << "{rn-sae}"; break;
108 case 1: O << "{rd-sae}"; break;
109 case 2: O << "{ru-sae}"; break;
110 case 3: O << "{rz-sae}"; break;
114 /// printPCRelImm - This is used to print an immediate value that ends up
115 /// being encoded as a pc-relative value.
116 void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
118 const MCOperand &Op = MI->getOperand(OpNo);
120 O << formatImm(Op.getImm());
122 assert(Op.isExpr() && "unknown pcrel immediate operand");
123 // If a symbolic branch target was added as a constant expression then print
124 // that address in hex.
125 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
127 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
128 O << formatHex((uint64_t)Address);
131 // Otherwise, just print the expression.
137 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
139 const MCOperand &Op = MI->getOperand(OpNo);
141 printRegName(O, Op.getReg());
142 } else if (Op.isImm()) {
143 O << formatImm((int64_t)Op.getImm());
145 assert(Op.isExpr() && "unknown operand kind in printOperand");
150 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
152 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
153 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
154 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
155 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
156 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
158 // If this has a segment register, print it.
159 if (SegReg.getReg()) {
160 printOperand(MI, Op+X86::AddrSegmentReg, O);
166 bool NeedPlus = false;
167 if (BaseReg.getReg()) {
168 printOperand(MI, Op+X86::AddrBaseReg, O);
172 if (IndexReg.getReg()) {
173 if (NeedPlus) O << " + ";
175 O << ScaleVal << '*';
176 printOperand(MI, Op+X86::AddrIndexReg, O);
180 if (!DispSpec.isImm()) {
181 if (NeedPlus) O << " + ";
182 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
183 O << *DispSpec.getExpr();
185 int64_t DispVal = DispSpec.getImm();
186 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
195 O << formatImm(DispVal);
202 void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
204 const MCOperand &SegReg = MI->getOperand(Op+1);
206 // If this has a segment register, print it.
207 if (SegReg.getReg()) {
208 printOperand(MI, Op+1, O);
212 printOperand(MI, Op, O);
216 void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
218 // DI accesses are always ES-based.
220 printOperand(MI, Op, O);
224 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
226 const MCOperand &DispSpec = MI->getOperand(Op);
227 const MCOperand &SegReg = MI->getOperand(Op+1);
229 // If this has a segment register, print it.
230 if (SegReg.getReg()) {
231 printOperand(MI, Op+1, O);
237 if (DispSpec.isImm()) {
238 O << formatImm(DispSpec.getImm());
240 assert(DispSpec.isExpr() && "non-immediate displacement?");
241 O << *DispSpec.getExpr();