1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as AT&T-style
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "X86ATTInstPrinter.h"
17 #include "X86InstComments.h"
18 #include "MCTargetDesc/X86MCTargetDesc.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/Format.h"
26 #include "llvm/Support/FormattedStream.h"
30 // Include the auto-generated portion of the assembly writer.
31 #define PRINT_ALIAS_INSTR
32 #include "X86GenAsmWriter.inc"
34 void X86ATTInstPrinter::printRegName(raw_ostream &OS,
35 unsigned RegNo) const {
36 OS << '%' << getRegisterName(RegNo);
39 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
41 // Try to print any aliases first.
42 if (!printAliasInstr(MI, OS))
43 printInstruction(MI, OS);
45 // Next always print the annotation.
46 printAnnotation(OS, Annot);
48 // If verbose assembly is enabled, we can print some informative comments.
50 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
53 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
55 switch (MI->getOperand(Op).getImm()) {
56 default: llvm_unreachable("Invalid ssecc argument!");
57 case 0: O << "eq"; break;
58 case 1: O << "lt"; break;
59 case 2: O << "le"; break;
60 case 3: O << "unord"; break;
61 case 4: O << "neq"; break;
62 case 5: O << "nlt"; break;
63 case 6: O << "nle"; break;
64 case 7: O << "ord"; break;
65 case 8: O << "eq_uq"; break;
66 case 9: O << "nge"; break;
67 case 0xa: O << "ngt"; break;
68 case 0xb: O << "false"; break;
69 case 0xc: O << "neq_oq"; break;
70 case 0xd: O << "ge"; break;
71 case 0xe: O << "gt"; break;
72 case 0xf: O << "true"; break;
73 case 0x10: O << "eq_os"; break;
74 case 0x11: O << "lt_oq"; break;
75 case 0x12: O << "le_oq"; break;
76 case 0x13: O << "unord_s"; break;
77 case 0x14: O << "neq_us"; break;
78 case 0x15: O << "nlt_uq"; break;
79 case 0x16: O << "nle_uq"; break;
80 case 0x17: O << "ord_s"; break;
81 case 0x18: O << "eq_us"; break;
82 case 0x19: O << "nge_uq"; break;
83 case 0x1a: O << "ngt_uq"; break;
84 case 0x1b: O << "false_os"; break;
85 case 0x1c: O << "neq_os"; break;
86 case 0x1d: O << "ge_oq"; break;
87 case 0x1e: O << "gt_oq"; break;
88 case 0x1f: O << "true_us"; break;
92 /// printPCRelImm - This is used to print an immediate value that ends up
93 /// being encoded as a pc-relative value (e.g. for jumps and calls). These
94 /// print slightly differently than normal immediates. For example, a $ is not
96 void X86ATTInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
98 const MCOperand &Op = MI->getOperand(OpNo);
102 assert(Op.isExpr() && "unknown pcrel immediate operand");
103 // If a symbolic branch target was added as a constant expression then print
104 // that address in hex.
105 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
107 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
109 O.write_hex(Address);
112 // Otherwise, just print the expression.
118 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
120 const MCOperand &Op = MI->getOperand(OpNo);
122 O << '%' << getRegisterName(Op.getReg());
123 } else if (Op.isImm()) {
124 // Print X86 immediates as signed values.
125 O << '$' << (int64_t)Op.getImm();
127 if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
128 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
131 assert(Op.isExpr() && "unknown operand kind in printOperand");
132 O << '$' << *Op.getExpr();
136 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
138 const MCOperand &BaseReg = MI->getOperand(Op);
139 const MCOperand &IndexReg = MI->getOperand(Op+2);
140 const MCOperand &DispSpec = MI->getOperand(Op+3);
141 const MCOperand &SegReg = MI->getOperand(Op+4);
143 // If this has a segment register, print it.
144 if (SegReg.getReg()) {
145 printOperand(MI, Op+4, O);
149 if (DispSpec.isImm()) {
150 int64_t DispVal = DispSpec.getImm();
151 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
154 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
155 O << *DispSpec.getExpr();
158 if (IndexReg.getReg() || BaseReg.getReg()) {
160 if (BaseReg.getReg())
161 printOperand(MI, Op, O);
163 if (IndexReg.getReg()) {
165 printOperand(MI, Op+2, O);
166 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
168 O << ',' << ScaleVal;