1 //===-- X86AsmInstrumentation.cpp - Instrument X86 inline assembly C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/X86BaseInfo.h"
11 #include "X86AsmInstrumentation.h"
12 #include "X86Operand.h"
13 #include "llvm/ADT/StringExtras.h"
14 #include "llvm/ADT/Triple.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstBuilder.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCTargetAsmParser.h"
24 #include "llvm/MC/MCTargetOptions.h"
25 #include "llvm/Support/CommandLine.h"
30 // Following comment describes how assembly instrumentation works.
31 // Currently we have only AddressSanitizer instrumentation, but we're
32 // planning to implement MemorySanitizer for inline assembly too. If
33 // you're not familiar with AddressSanitizer algorithm, please, read
34 // https://code.google.com/p/address-sanitizer/wiki/AddressSanitizerAlgorithm.
36 // When inline assembly is parsed by an instance of X86AsmParser, all
37 // instructions are emitted via EmitInstruction method. That's the
38 // place where X86AsmInstrumentation analyzes an instruction and
39 // decides, whether the instruction should be emitted as is or
40 // instrumentation is required. The latter case happens when an
41 // instruction reads from or writes to memory. Now instruction opcode
42 // is explicitly checked, and if an instruction has a memory operand
43 // (for instance, movq (%rsi, %rcx, 8), %rax) - it should be
44 // instrumented. There're also exist instructions that modify
45 // memory but don't have an explicit memory operands, for instance,
48 // Let's consider at first 8-byte memory accesses when an instruction
49 // has an explicit memory operand. In this case we need two registers -
50 // AddressReg to compute address of a memory cells which are accessed
51 // and ShadowReg to compute corresponding shadow address. So, we need
52 // to spill both registers before instrumentation code and restore them
53 // after instrumentation. Thus, in general, instrumentation code will
55 // PUSHF # Store flags, otherwise they will be overwritten
56 // PUSH AddressReg # spill AddressReg
57 // PUSH ShadowReg # spill ShadowReg
58 // LEA MemOp, AddressReg # compute address of the memory operand
59 // MOV AddressReg, ShadowReg
61 // # ShadowOffset(AddressReg >> 3) contains address of a shadow
62 // # corresponding to MemOp.
63 // CMP ShadowOffset(ShadowReg), 0 # test shadow value
64 // JZ .Done # when shadow equals to zero, everything is fine
65 // MOV AddressReg, RDI
66 // # Call __asan_report function with AddressReg as an argument
69 // POP ShadowReg # Restore ShadowReg
70 // POP AddressReg # Restore AddressReg
71 // POPF # Restore flags
73 // Memory accesses with different size (1-, 2-, 4- and 16-byte) are
74 // handled in a similar manner, but small memory accesses (less than 8
75 // byte) require an additional ScratchReg, which is used for shadow value.
77 // If, suppose, we're instrumenting an instruction like movs, only
78 // contents of RDI, RDI + AccessSize * RCX, RSI, RSI + AccessSize *
79 // RCX are checked. In this case there're no need to spill and restore
80 // AddressReg , ShadowReg or flags four times, they're saved on stack
81 // just once, before instrumentation of these four addresses, and restored
82 // at the end of the instrumentation.
84 // There exist several things which complicate this simple algorithm.
85 // * Instrumented memory operand can have RSP as a base or an index
86 // register. So we need to add a constant offset before computation
87 // of memory address, since flags, AddressReg, ShadowReg, etc. were
88 // already stored on stack and RSP was modified.
89 // * Debug info (usually, DWARF) should be adjusted, because sometimes
90 // RSP is used as a frame register. So, we need to select some
91 // register as a frame register and temprorary override current CFA
97 static cl::opt<bool> ClAsanInstrumentAssembly(
98 "asan-instrument-assembly",
99 cl::desc("instrument assembly with AddressSanitizer checks"), cl::Hidden,
102 const int64_t MinAllowedDisplacement = std::numeric_limits<int32_t>::min();
103 const int64_t MaxAllowedDisplacement = std::numeric_limits<int32_t>::max();
105 int64_t ApplyDisplacementBounds(int64_t Displacement) {
106 return std::max(std::min(MaxAllowedDisplacement, Displacement),
107 MinAllowedDisplacement);
110 void CheckDisplacementBounds(int64_t Displacement) {
111 assert(Displacement >= MinAllowedDisplacement &&
112 Displacement <= MaxAllowedDisplacement);
115 bool IsStackReg(unsigned Reg) { return Reg == X86::RSP || Reg == X86::ESP; }
117 bool IsSmallMemAccess(unsigned AccessSize) { return AccessSize < 8; }
119 class X86AddressSanitizer : public X86AsmInstrumentation {
121 struct RegisterContext {
124 REG_OFFSET_ADDRESS = 0,
130 RegisterContext(unsigned AddressReg, unsigned ShadowReg,
131 unsigned ScratchReg) {
132 BusyRegs.push_back(convReg(AddressReg, 64));
133 BusyRegs.push_back(convReg(ShadowReg, 64));
134 BusyRegs.push_back(convReg(ScratchReg, 64));
137 unsigned AddressReg(unsigned Size) const {
138 return convReg(BusyRegs[REG_OFFSET_ADDRESS], Size);
141 unsigned ShadowReg(unsigned Size) const {
142 return convReg(BusyRegs[REG_OFFSET_SHADOW], Size);
145 unsigned ScratchReg(unsigned Size) const {
146 return convReg(BusyRegs[REG_OFFSET_SCRATCH], Size);
149 void AddBusyReg(unsigned Reg) {
150 if (Reg != X86::NoRegister)
151 BusyRegs.push_back(convReg(Reg, 64));
154 void AddBusyRegs(const X86Operand &Op) {
155 AddBusyReg(Op.getMemBaseReg());
156 AddBusyReg(Op.getMemIndexReg());
159 unsigned ChooseFrameReg(unsigned Size) const {
160 static const MCPhysReg Candidates[] = { X86::RBP, X86::RAX, X86::RBX,
161 X86::RCX, X86::RDX, X86::RDI,
163 for (unsigned Reg : Candidates) {
164 if (!std::count(BusyRegs.begin(), BusyRegs.end(), Reg))
165 return convReg(Reg, Size);
167 return X86::NoRegister;
171 unsigned convReg(unsigned Reg, unsigned Size) const {
172 return Reg == X86::NoRegister ? Reg : getX86SubSuperRegister(Reg, Size);
175 std::vector<unsigned> BusyRegs;
178 X86AddressSanitizer(const MCSubtargetInfo *&STI)
179 : X86AsmInstrumentation(STI), RepPrefix(false), OrigSPOffset(0) {}
181 ~X86AddressSanitizer() override {}
183 // X86AsmInstrumentation implementation:
184 void InstrumentAndEmitInstruction(const MCInst &Inst,
185 OperandVector &Operands,
187 const MCInstrInfo &MII,
188 MCStreamer &Out) override {
189 InstrumentMOVS(Inst, Operands, Ctx, MII, Out);
191 EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
193 InstrumentMOV(Inst, Operands, Ctx, MII, Out);
195 RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX);
197 EmitInstruction(Out, Inst);
200 // Adjusts up stack and saves all registers used in instrumentation.
201 virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
203 MCStreamer &Out) = 0;
205 // Restores all registers used in instrumentation and adjusts stack.
206 virtual void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
208 MCStreamer &Out) = 0;
210 virtual void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
212 const RegisterContext &RegCtx,
213 MCContext &Ctx, MCStreamer &Out) = 0;
214 virtual void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize,
216 const RegisterContext &RegCtx,
217 MCContext &Ctx, MCStreamer &Out) = 0;
219 virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
220 MCStreamer &Out) = 0;
222 void InstrumentMemOperand(X86Operand &Op, unsigned AccessSize, bool IsWrite,
223 const RegisterContext &RegCtx, MCContext &Ctx,
225 void InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg, unsigned CntReg,
226 unsigned AccessSize, MCContext &Ctx, MCStreamer &Out);
228 void InstrumentMOVS(const MCInst &Inst, OperandVector &Operands,
229 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
230 void InstrumentMOV(const MCInst &Inst, OperandVector &Operands,
231 MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
234 void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); }
236 void EmitLEA(X86Operand &Op, unsigned Size, unsigned Reg, MCStreamer &Out) {
237 assert(Size == 32 || Size == 64);
239 Inst.setOpcode(Size == 32 ? X86::LEA32r : X86::LEA64r);
240 Inst.addOperand(MCOperand::createReg(getX86SubSuperRegister(Reg, Size)));
241 Op.addMemOperands(Inst, 5);
242 EmitInstruction(Out, Inst);
245 void ComputeMemOperandAddress(X86Operand &Op, unsigned Size,
246 unsigned Reg, MCContext &Ctx, MCStreamer &Out);
248 // Creates new memory operand with Displacement added to an original
249 // displacement. Residue will contain a residue which could happen when the
250 // total displacement exceeds 32-bit limitation.
251 std::unique_ptr<X86Operand> AddDisplacement(X86Operand &Op,
252 int64_t Displacement,
253 MCContext &Ctx, int64_t *Residue);
255 bool is64BitMode() const {
256 return STI->getFeatureBits()[X86::Mode64Bit];
258 bool is32BitMode() const {
259 return STI->getFeatureBits()[X86::Mode32Bit];
261 bool is16BitMode() const {
262 return STI->getFeatureBits()[X86::Mode16Bit];
265 unsigned getPointerWidth() {
266 if (is16BitMode()) return 16;
267 if (is32BitMode()) return 32;
268 if (is64BitMode()) return 64;
269 llvm_unreachable("invalid mode");
272 // True when previous instruction was actually REP prefix.
275 // Offset from the original SP register.
276 int64_t OrigSPOffset;
279 void X86AddressSanitizer::InstrumentMemOperand(
280 X86Operand &Op, unsigned AccessSize, bool IsWrite,
281 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
282 assert(Op.isMem() && "Op should be a memory operand.");
283 assert((AccessSize & (AccessSize - 1)) == 0 && AccessSize <= 16 &&
284 "AccessSize should be a power of two, less or equal than 16.");
285 // FIXME: take into account load/store alignment.
286 if (IsSmallMemAccess(AccessSize))
287 InstrumentMemOperandSmall(Op, AccessSize, IsWrite, RegCtx, Ctx, Out);
289 InstrumentMemOperandLarge(Op, AccessSize, IsWrite, RegCtx, Ctx, Out);
292 void X86AddressSanitizer::InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg,
295 MCContext &Ctx, MCStreamer &Out) {
296 // FIXME: check whole ranges [DstReg .. DstReg + AccessSize * (CntReg - 1)]
297 // and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)].
298 RegisterContext RegCtx(X86::RDX /* AddressReg */, X86::RAX /* ShadowReg */,
299 IsSmallMemAccess(AccessSize)
301 : X86::NoRegister /* ScratchReg */);
302 RegCtx.AddBusyReg(DstReg);
303 RegCtx.AddBusyReg(SrcReg);
304 RegCtx.AddBusyReg(CntReg);
306 InstrumentMemOperandPrologue(RegCtx, Ctx, Out);
310 const MCExpr *Disp = MCConstantExpr::create(0, Ctx);
311 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
312 getPointerWidth(), 0, Disp, SrcReg, 0, AccessSize, SMLoc(), SMLoc()));
313 InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, RegCtx, Ctx,
317 // Test -1(%SrcReg, %CntReg, AccessSize)
319 const MCExpr *Disp = MCConstantExpr::create(-1, Ctx);
320 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
321 getPointerWidth(), 0, Disp, SrcReg, CntReg, AccessSize, SMLoc(),
323 InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, RegCtx, Ctx,
329 const MCExpr *Disp = MCConstantExpr::create(0, Ctx);
330 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
331 getPointerWidth(), 0, Disp, DstReg, 0, AccessSize, SMLoc(), SMLoc()));
332 InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, RegCtx, Ctx, Out);
335 // Test -1(%DstReg, %CntReg, AccessSize)
337 const MCExpr *Disp = MCConstantExpr::create(-1, Ctx);
338 std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
339 getPointerWidth(), 0, Disp, DstReg, CntReg, AccessSize, SMLoc(),
341 InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, RegCtx, Ctx, Out);
344 InstrumentMemOperandEpilogue(RegCtx, Ctx, Out);
347 void X86AddressSanitizer::InstrumentMOVS(const MCInst &Inst,
348 OperandVector &Operands,
349 MCContext &Ctx, const MCInstrInfo &MII,
351 // Access size in bytes.
352 unsigned AccessSize = 0;
354 switch (Inst.getOpcode()) {
371 InstrumentMOVSImpl(AccessSize, Ctx, Out);
374 void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
375 OperandVector &Operands, MCContext &Ctx,
376 const MCInstrInfo &MII,
378 // Access size in bytes.
379 unsigned AccessSize = 0;
381 switch (Inst.getOpcode()) {
412 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
414 for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
415 assert(Operands[Ix]);
416 MCParsedAsmOperand &Op = *Operands[Ix];
418 X86Operand &MemOp = static_cast<X86Operand &>(Op);
419 RegisterContext RegCtx(
420 X86::RDI /* AddressReg */, X86::RAX /* ShadowReg */,
421 IsSmallMemAccess(AccessSize) ? X86::RCX
422 : X86::NoRegister /* ScratchReg */);
423 RegCtx.AddBusyRegs(MemOp);
424 InstrumentMemOperandPrologue(RegCtx, Ctx, Out);
425 InstrumentMemOperand(MemOp, AccessSize, IsWrite, RegCtx, Ctx, Out);
426 InstrumentMemOperandEpilogue(RegCtx, Ctx, Out);
431 void X86AddressSanitizer::ComputeMemOperandAddress(X86Operand &Op,
433 unsigned Reg, MCContext &Ctx,
435 int64_t Displacement = 0;
436 if (IsStackReg(Op.getMemBaseReg()))
437 Displacement -= OrigSPOffset;
438 if (IsStackReg(Op.getMemIndexReg()))
439 Displacement -= OrigSPOffset * Op.getMemScale();
441 assert(Displacement >= 0);
444 if (Displacement == 0) {
445 EmitLEA(Op, Size, Reg, Out);
450 std::unique_ptr<X86Operand> NewOp =
451 AddDisplacement(Op, Displacement, Ctx, &Residue);
452 EmitLEA(*NewOp, Size, Reg, Out);
454 while (Residue != 0) {
455 const MCConstantExpr *Disp =
456 MCConstantExpr::create(ApplyDisplacementBounds(Residue), Ctx);
457 std::unique_ptr<X86Operand> DispOp =
458 X86Operand::CreateMem(getPointerWidth(), 0, Disp, Reg, 0, 1, SMLoc(),
460 EmitLEA(*DispOp, Size, Reg, Out);
461 Residue -= Disp->getValue();
465 std::unique_ptr<X86Operand>
466 X86AddressSanitizer::AddDisplacement(X86Operand &Op, int64_t Displacement,
467 MCContext &Ctx, int64_t *Residue) {
468 assert(Displacement >= 0);
470 if (Displacement == 0 ||
471 (Op.getMemDisp() && Op.getMemDisp()->getKind() != MCExpr::Constant)) {
472 *Residue = Displacement;
473 return X86Operand::CreateMem(Op.getMemModeSize(), Op.getMemSegReg(),
474 Op.getMemDisp(), Op.getMemBaseReg(),
475 Op.getMemIndexReg(), Op.getMemScale(),
479 int64_t OrigDisplacement =
480 static_cast<const MCConstantExpr *>(Op.getMemDisp())->getValue();
481 CheckDisplacementBounds(OrigDisplacement);
482 Displacement += OrigDisplacement;
484 int64_t NewDisplacement = ApplyDisplacementBounds(Displacement);
485 CheckDisplacementBounds(NewDisplacement);
487 *Residue = Displacement - NewDisplacement;
488 const MCExpr *Disp = MCConstantExpr::create(NewDisplacement, Ctx);
489 return X86Operand::CreateMem(Op.getMemModeSize(), Op.getMemSegReg(), Disp,
490 Op.getMemBaseReg(), Op.getMemIndexReg(),
491 Op.getMemScale(), SMLoc(), SMLoc());
494 class X86AddressSanitizer32 : public X86AddressSanitizer {
496 static const long kShadowOffset = 0x20000000;
498 X86AddressSanitizer32(const MCSubtargetInfo *&STI)
499 : X86AddressSanitizer(STI) {}
501 ~X86AddressSanitizer32() override {}
503 unsigned GetFrameReg(const MCContext &Ctx, MCStreamer &Out) {
504 unsigned FrameReg = GetFrameRegGeneric(Ctx, Out);
505 if (FrameReg == X86::NoRegister)
507 return getX86SubSuperRegister(FrameReg, 32);
510 void SpillReg(MCStreamer &Out, unsigned Reg) {
511 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(Reg));
515 void RestoreReg(MCStreamer &Out, unsigned Reg) {
516 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(Reg));
520 void StoreFlags(MCStreamer &Out) {
521 EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
525 void RestoreFlags(MCStreamer &Out) {
526 EmitInstruction(Out, MCInstBuilder(X86::POPF32));
530 void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
532 MCStreamer &Out) override {
533 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(32);
534 assert(LocalFrameReg != X86::NoRegister);
536 const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
537 unsigned FrameReg = GetFrameReg(Ctx, Out);
538 if (MRI && FrameReg != X86::NoRegister) {
539 SpillReg(Out, LocalFrameReg);
540 if (FrameReg == X86::ESP) {
541 Out.EmitCFIAdjustCfaOffset(4 /* byte size of the LocalFrameReg */);
542 Out.EmitCFIRelOffset(
543 MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */), 0);
547 MCInstBuilder(X86::MOV32rr).addReg(LocalFrameReg).addReg(FrameReg));
548 Out.EmitCFIRememberState();
549 Out.EmitCFIDefCfaRegister(
550 MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */));
553 SpillReg(Out, RegCtx.AddressReg(32));
554 SpillReg(Out, RegCtx.ShadowReg(32));
555 if (RegCtx.ScratchReg(32) != X86::NoRegister)
556 SpillReg(Out, RegCtx.ScratchReg(32));
560 void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
562 MCStreamer &Out) override {
563 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(32);
564 assert(LocalFrameReg != X86::NoRegister);
567 if (RegCtx.ScratchReg(32) != X86::NoRegister)
568 RestoreReg(Out, RegCtx.ScratchReg(32));
569 RestoreReg(Out, RegCtx.ShadowReg(32));
570 RestoreReg(Out, RegCtx.AddressReg(32));
572 unsigned FrameReg = GetFrameReg(Ctx, Out);
573 if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
574 RestoreReg(Out, LocalFrameReg);
575 Out.EmitCFIRestoreState();
576 if (FrameReg == X86::ESP)
577 Out.EmitCFIAdjustCfaOffset(-4 /* byte size of the LocalFrameReg */);
581 void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
583 const RegisterContext &RegCtx,
585 MCStreamer &Out) override;
586 void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize,
588 const RegisterContext &RegCtx,
590 MCStreamer &Out) override;
591 void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
592 MCStreamer &Out) override;
595 void EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx,
596 MCStreamer &Out, const RegisterContext &RegCtx) {
597 EmitInstruction(Out, MCInstBuilder(X86::CLD));
598 EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
600 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
605 Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.AddressReg(32)));
607 MCSymbol *FnSym = Ctx.getOrCreateSymbol(llvm::Twine("__asan_report_") +
608 (IsWrite ? "store" : "load") +
609 llvm::Twine(AccessSize));
610 const MCSymbolRefExpr *FnExpr =
611 MCSymbolRefExpr::create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
612 EmitInstruction(Out, MCInstBuilder(X86::CALLpcrel32).addExpr(FnExpr));
616 void X86AddressSanitizer32::InstrumentMemOperandSmall(
617 X86Operand &Op, unsigned AccessSize, bool IsWrite,
618 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
619 unsigned AddressRegI32 = RegCtx.AddressReg(32);
620 unsigned ShadowRegI32 = RegCtx.ShadowReg(32);
621 unsigned ShadowRegI8 = RegCtx.ShadowReg(8);
623 assert(RegCtx.ScratchReg(32) != X86::NoRegister);
624 unsigned ScratchRegI32 = RegCtx.ScratchReg(32);
626 ComputeMemOperandAddress(Op, 32, AddressRegI32, Ctx, Out);
628 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
630 EmitInstruction(Out, MCInstBuilder(X86::SHR32ri)
631 .addReg(ShadowRegI32)
632 .addReg(ShadowRegI32)
637 Inst.setOpcode(X86::MOV8rm);
638 Inst.addOperand(MCOperand::createReg(ShadowRegI8));
639 const MCExpr *Disp = MCConstantExpr::create(kShadowOffset, Ctx);
640 std::unique_ptr<X86Operand> Op(
641 X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI32, 0, 1,
643 Op->addMemOperands(Inst, 5);
644 EmitInstruction(Out, Inst);
648 Out, MCInstBuilder(X86::TEST8rr).addReg(ShadowRegI8).addReg(ShadowRegI8));
649 MCSymbol *DoneSym = Ctx.createTempSymbol();
650 const MCExpr *DoneExpr = MCSymbolRefExpr::create(DoneSym, Ctx);
651 EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
653 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ScratchRegI32).addReg(
655 EmitInstruction(Out, MCInstBuilder(X86::AND32ri)
656 .addReg(ScratchRegI32)
657 .addReg(ScratchRegI32)
660 switch (AccessSize) {
661 default: llvm_unreachable("Incorrect access size");
665 const MCExpr *Disp = MCConstantExpr::create(1, Ctx);
666 std::unique_ptr<X86Operand> Op(
667 X86Operand::CreateMem(getPointerWidth(), 0, Disp, ScratchRegI32, 0, 1,
669 EmitLEA(*Op, 32, ScratchRegI32, Out);
673 EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
674 .addReg(ScratchRegI32)
675 .addReg(ScratchRegI32)
682 MCInstBuilder(X86::MOVSX32rr8).addReg(ShadowRegI32).addReg(ShadowRegI8));
683 EmitInstruction(Out, MCInstBuilder(X86::CMP32rr).addReg(ScratchRegI32).addReg(
685 EmitInstruction(Out, MCInstBuilder(X86::JL_1).addExpr(DoneExpr));
687 EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
688 EmitLabel(Out, DoneSym);
691 void X86AddressSanitizer32::InstrumentMemOperandLarge(
692 X86Operand &Op, unsigned AccessSize, bool IsWrite,
693 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
694 unsigned AddressRegI32 = RegCtx.AddressReg(32);
695 unsigned ShadowRegI32 = RegCtx.ShadowReg(32);
697 ComputeMemOperandAddress(Op, 32, AddressRegI32, Ctx, Out);
699 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
701 EmitInstruction(Out, MCInstBuilder(X86::SHR32ri)
702 .addReg(ShadowRegI32)
703 .addReg(ShadowRegI32)
707 switch (AccessSize) {
708 default: llvm_unreachable("Incorrect access size");
710 Inst.setOpcode(X86::CMP8mi);
713 Inst.setOpcode(X86::CMP16mi);
716 const MCExpr *Disp = MCConstantExpr::create(kShadowOffset, Ctx);
717 std::unique_ptr<X86Operand> Op(
718 X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI32, 0, 1,
720 Op->addMemOperands(Inst, 5);
721 Inst.addOperand(MCOperand::createImm(0));
722 EmitInstruction(Out, Inst);
724 MCSymbol *DoneSym = Ctx.createTempSymbol();
725 const MCExpr *DoneExpr = MCSymbolRefExpr::create(DoneSym, Ctx);
726 EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
728 EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
729 EmitLabel(Out, DoneSym);
732 void X86AddressSanitizer32::InstrumentMOVSImpl(unsigned AccessSize,
737 // No need to test when ECX is equals to zero.
738 MCSymbol *DoneSym = Ctx.createTempSymbol();
739 const MCExpr *DoneExpr = MCSymbolRefExpr::create(DoneSym, Ctx);
741 Out, MCInstBuilder(X86::TEST32rr).addReg(X86::ECX).addReg(X86::ECX));
742 EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
744 // Instrument first and last elements in src and dst range.
745 InstrumentMOVSBase(X86::EDI /* DstReg */, X86::ESI /* SrcReg */,
746 X86::ECX /* CntReg */, AccessSize, Ctx, Out);
748 EmitLabel(Out, DoneSym);
752 class X86AddressSanitizer64 : public X86AddressSanitizer {
754 static const long kShadowOffset = 0x7fff8000;
756 X86AddressSanitizer64(const MCSubtargetInfo *&STI)
757 : X86AddressSanitizer(STI) {}
759 ~X86AddressSanitizer64() override {}
761 unsigned GetFrameReg(const MCContext &Ctx, MCStreamer &Out) {
762 unsigned FrameReg = GetFrameRegGeneric(Ctx, Out);
763 if (FrameReg == X86::NoRegister)
765 return getX86SubSuperRegister(FrameReg, 64);
768 void SpillReg(MCStreamer &Out, unsigned Reg) {
769 EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(Reg));
773 void RestoreReg(MCStreamer &Out, unsigned Reg) {
774 EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(Reg));
778 void StoreFlags(MCStreamer &Out) {
779 EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
783 void RestoreFlags(MCStreamer &Out) {
784 EmitInstruction(Out, MCInstBuilder(X86::POPF64));
788 void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
790 MCStreamer &Out) override {
791 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(64);
792 assert(LocalFrameReg != X86::NoRegister);
794 const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
795 unsigned FrameReg = GetFrameReg(Ctx, Out);
796 if (MRI && FrameReg != X86::NoRegister) {
797 SpillReg(Out, X86::RBP);
798 if (FrameReg == X86::RSP) {
799 Out.EmitCFIAdjustCfaOffset(8 /* byte size of the LocalFrameReg */);
800 Out.EmitCFIRelOffset(
801 MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */), 0);
805 MCInstBuilder(X86::MOV64rr).addReg(LocalFrameReg).addReg(FrameReg));
806 Out.EmitCFIRememberState();
807 Out.EmitCFIDefCfaRegister(
808 MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */));
811 EmitAdjustRSP(Ctx, Out, -128);
812 SpillReg(Out, RegCtx.ShadowReg(64));
813 SpillReg(Out, RegCtx.AddressReg(64));
814 if (RegCtx.ScratchReg(64) != X86::NoRegister)
815 SpillReg(Out, RegCtx.ScratchReg(64));
819 void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
821 MCStreamer &Out) override {
822 unsigned LocalFrameReg = RegCtx.ChooseFrameReg(64);
823 assert(LocalFrameReg != X86::NoRegister);
826 if (RegCtx.ScratchReg(64) != X86::NoRegister)
827 RestoreReg(Out, RegCtx.ScratchReg(64));
828 RestoreReg(Out, RegCtx.AddressReg(64));
829 RestoreReg(Out, RegCtx.ShadowReg(64));
830 EmitAdjustRSP(Ctx, Out, 128);
832 unsigned FrameReg = GetFrameReg(Ctx, Out);
833 if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
834 RestoreReg(Out, LocalFrameReg);
835 Out.EmitCFIRestoreState();
836 if (FrameReg == X86::RSP)
837 Out.EmitCFIAdjustCfaOffset(-8 /* byte size of the LocalFrameReg */);
841 void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
843 const RegisterContext &RegCtx,
845 MCStreamer &Out) override;
846 void InstrumentMemOperandLarge(X86Operand &Op, unsigned AccessSize,
848 const RegisterContext &RegCtx,
850 MCStreamer &Out) override;
851 void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
852 MCStreamer &Out) override;
855 void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) {
856 const MCExpr *Disp = MCConstantExpr::create(Offset, Ctx);
857 std::unique_ptr<X86Operand> Op(
858 X86Operand::CreateMem(getPointerWidth(), 0, Disp, X86::RSP, 0, 1,
860 EmitLEA(*Op, 64, X86::RSP, Out);
861 OrigSPOffset += Offset;
864 void EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx,
865 MCStreamer &Out, const RegisterContext &RegCtx) {
866 EmitInstruction(Out, MCInstBuilder(X86::CLD));
867 EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
869 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
874 if (RegCtx.AddressReg(64) != X86::RDI) {
875 EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RDI).addReg(
876 RegCtx.AddressReg(64)));
878 MCSymbol *FnSym = Ctx.getOrCreateSymbol(llvm::Twine("__asan_report_") +
879 (IsWrite ? "store" : "load") +
880 llvm::Twine(AccessSize));
881 const MCSymbolRefExpr *FnExpr =
882 MCSymbolRefExpr::create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
883 EmitInstruction(Out, MCInstBuilder(X86::CALL64pcrel32).addExpr(FnExpr));
887 void X86AddressSanitizer64::InstrumentMemOperandSmall(
888 X86Operand &Op, unsigned AccessSize, bool IsWrite,
889 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
890 unsigned AddressRegI64 = RegCtx.AddressReg(64);
891 unsigned AddressRegI32 = RegCtx.AddressReg(32);
892 unsigned ShadowRegI64 = RegCtx.ShadowReg(64);
893 unsigned ShadowRegI32 = RegCtx.ShadowReg(32);
894 unsigned ShadowRegI8 = RegCtx.ShadowReg(8);
896 assert(RegCtx.ScratchReg(32) != X86::NoRegister);
897 unsigned ScratchRegI32 = RegCtx.ScratchReg(32);
899 ComputeMemOperandAddress(Op, 64, AddressRegI64, Ctx, Out);
901 EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
903 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri)
904 .addReg(ShadowRegI64)
905 .addReg(ShadowRegI64)
909 Inst.setOpcode(X86::MOV8rm);
910 Inst.addOperand(MCOperand::createReg(ShadowRegI8));
911 const MCExpr *Disp = MCConstantExpr::create(kShadowOffset, Ctx);
912 std::unique_ptr<X86Operand> Op(
913 X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI64, 0, 1,
915 Op->addMemOperands(Inst, 5);
916 EmitInstruction(Out, Inst);
920 Out, MCInstBuilder(X86::TEST8rr).addReg(ShadowRegI8).addReg(ShadowRegI8));
921 MCSymbol *DoneSym = Ctx.createTempSymbol();
922 const MCExpr *DoneExpr = MCSymbolRefExpr::create(DoneSym, Ctx);
923 EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
925 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ScratchRegI32).addReg(
927 EmitInstruction(Out, MCInstBuilder(X86::AND32ri)
928 .addReg(ScratchRegI32)
929 .addReg(ScratchRegI32)
932 switch (AccessSize) {
933 default: llvm_unreachable("Incorrect access size");
937 const MCExpr *Disp = MCConstantExpr::create(1, Ctx);
938 std::unique_ptr<X86Operand> Op(
939 X86Operand::CreateMem(getPointerWidth(), 0, Disp, ScratchRegI32, 0, 1,
941 EmitLEA(*Op, 32, ScratchRegI32, Out);
945 EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
946 .addReg(ScratchRegI32)
947 .addReg(ScratchRegI32)
954 MCInstBuilder(X86::MOVSX32rr8).addReg(ShadowRegI32).addReg(ShadowRegI8));
955 EmitInstruction(Out, MCInstBuilder(X86::CMP32rr).addReg(ScratchRegI32).addReg(
957 EmitInstruction(Out, MCInstBuilder(X86::JL_1).addExpr(DoneExpr));
959 EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
960 EmitLabel(Out, DoneSym);
963 void X86AddressSanitizer64::InstrumentMemOperandLarge(
964 X86Operand &Op, unsigned AccessSize, bool IsWrite,
965 const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
966 unsigned AddressRegI64 = RegCtx.AddressReg(64);
967 unsigned ShadowRegI64 = RegCtx.ShadowReg(64);
969 ComputeMemOperandAddress(Op, 64, AddressRegI64, Ctx, Out);
971 EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
973 EmitInstruction(Out, MCInstBuilder(X86::SHR64ri)
974 .addReg(ShadowRegI64)
975 .addReg(ShadowRegI64)
979 switch (AccessSize) {
980 default: llvm_unreachable("Incorrect access size");
982 Inst.setOpcode(X86::CMP8mi);
985 Inst.setOpcode(X86::CMP16mi);
988 const MCExpr *Disp = MCConstantExpr::create(kShadowOffset, Ctx);
989 std::unique_ptr<X86Operand> Op(
990 X86Operand::CreateMem(getPointerWidth(), 0, Disp, ShadowRegI64, 0, 1,
992 Op->addMemOperands(Inst, 5);
993 Inst.addOperand(MCOperand::createImm(0));
994 EmitInstruction(Out, Inst);
997 MCSymbol *DoneSym = Ctx.createTempSymbol();
998 const MCExpr *DoneExpr = MCSymbolRefExpr::create(DoneSym, Ctx);
999 EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
1001 EmitCallAsanReport(AccessSize, IsWrite, Ctx, Out, RegCtx);
1002 EmitLabel(Out, DoneSym);
1005 void X86AddressSanitizer64::InstrumentMOVSImpl(unsigned AccessSize,
1010 // No need to test when RCX is equals to zero.
1011 MCSymbol *DoneSym = Ctx.createTempSymbol();
1012 const MCExpr *DoneExpr = MCSymbolRefExpr::create(DoneSym, Ctx);
1014 Out, MCInstBuilder(X86::TEST64rr).addReg(X86::RCX).addReg(X86::RCX));
1015 EmitInstruction(Out, MCInstBuilder(X86::JE_1).addExpr(DoneExpr));
1017 // Instrument first and last elements in src and dst range.
1018 InstrumentMOVSBase(X86::RDI /* DstReg */, X86::RSI /* SrcReg */,
1019 X86::RCX /* CntReg */, AccessSize, Ctx, Out);
1021 EmitLabel(Out, DoneSym);
1025 } // End anonymous namespace
1027 X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo *&STI)
1028 : STI(STI), InitialFrameReg(0) {}
1030 X86AsmInstrumentation::~X86AsmInstrumentation() {}
1032 void X86AsmInstrumentation::InstrumentAndEmitInstruction(
1033 const MCInst &Inst, OperandVector &Operands, MCContext &Ctx,
1034 const MCInstrInfo &MII, MCStreamer &Out) {
1035 EmitInstruction(Out, Inst);
1038 void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out,
1039 const MCInst &Inst) {
1040 Out.EmitInstruction(Inst, *STI);
1043 unsigned X86AsmInstrumentation::GetFrameRegGeneric(const MCContext &Ctx,
1045 if (!Out.getNumFrameInfos()) // No active dwarf frame
1046 return X86::NoRegister;
1047 const MCDwarfFrameInfo &Frame = Out.getDwarfFrameInfos().back();
1048 if (Frame.End) // Active dwarf frame is closed
1049 return X86::NoRegister;
1050 const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
1051 if (!MRI) // No register info
1052 return X86::NoRegister;
1054 if (InitialFrameReg) {
1055 // FrameReg is set explicitly, we're instrumenting a MachineFunction.
1056 return InitialFrameReg;
1059 return MRI->getLLVMRegNum(Frame.CurrentCfaRegister, true /* IsEH */);
1062 X86AsmInstrumentation *
1063 CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
1064 const MCContext &Ctx, const MCSubtargetInfo *&STI) {
1065 Triple T(STI->getTargetTriple());
1066 const bool hasCompilerRTSupport = T.isOSLinux();
1067 if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
1068 MCOptions.SanitizeAddress) {
1069 if (STI->getFeatureBits()[X86::Mode32Bit] != 0)
1070 return new X86AddressSanitizer32(STI);
1071 if (STI->getFeatureBits()[X86::Mode64Bit] != 0)
1072 return new X86AddressSanitizer64(STI);
1074 return new X86AsmInstrumentation(STI);
1077 } // end llvm namespace