1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This file implements the WebAssemblyTargetLowering class.
13 //===----------------------------------------------------------------------===//
15 #include "WebAssemblyISelLowering.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssemblyMachineFunctionInfo.h"
18 #include "WebAssemblySubtarget.h"
19 #include "WebAssemblyTargetMachine.h"
20 #include "WebAssemblyTargetObjectFile.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/IR/DiagnosticInfo.h"
27 #include "llvm/IR/DiagnosticPrinter.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define DEBUG_TYPE "wasm-lower"
40 // Diagnostic information for unimplemented or unsupported feature reporting.
41 // TODO: This code is copied from BPF and AMDGPU; consider factoring it out
43 class DiagnosticInfoUnsupported final : public DiagnosticInfo {
45 // Debug location where this diagnostic is triggered.
47 const Twine &Description;
53 static int getKindID() {
55 KindID = llvm::getNextAvailablePluginDiagnosticKind();
60 DiagnosticInfoUnsupported(SDLoc DLoc, const Function &Fn, const Twine &Desc,
62 : DiagnosticInfo(getKindID(), DS_Error), DLoc(DLoc.getDebugLoc()),
63 Description(Desc), Fn(Fn), Value(Value) {}
65 void print(DiagnosticPrinter &DP) const override {
67 raw_string_ostream OS(Str);
70 auto DIL = DLoc.get();
71 StringRef Filename = DIL->getFilename();
72 unsigned Line = DIL->getLine();
73 unsigned Column = DIL->getColumn();
74 OS << Filename << ':' << Line << ':' << Column << ' ';
77 OS << "in function " << Fn.getName() << ' ' << *Fn.getFunctionType() << '\n'
86 static bool classof(const DiagnosticInfo *DI) {
87 return DI->getKind() == getKindID();
91 int DiagnosticInfoUnsupported::KindID = 0;
92 } // end anonymous namespace
94 WebAssemblyTargetLowering::WebAssemblyTargetLowering(
95 const TargetMachine &TM, const WebAssemblySubtarget &STI)
96 : TargetLowering(TM), Subtarget(&STI) {
97 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
99 // Booleans always contain 0 or 1.
100 setBooleanContents(ZeroOrOneBooleanContent);
101 // WebAssembly does not produce floating-point exceptions on normal floating
103 setHasFloatingPointExceptions(false);
104 // We don't know the microarchitecture here, so just reduce register pressure.
105 setSchedulingPreference(Sched::RegPressure);
106 // Tell ISel that we have a stack pointer.
107 setStackPointerRegisterToSaveRestore(
108 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
109 // Set up the register classes.
110 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
111 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
112 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
113 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
114 // Compute derived properties from the register classes.
115 computeRegisterProperties(Subtarget->getRegisterInfo());
117 setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
118 setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom);
119 setOperationAction(ISD::JumpTable, MVTPtr, Custom);
121 // Take the default expansion for va_arg, va_copy, and va_end. There is no
122 // default action for va_start, so we do that custom.
123 setOperationAction(ISD::VASTART, MVT::Other, Custom);
124 setOperationAction(ISD::VAARG, MVT::Other, Expand);
125 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
126 setOperationAction(ISD::VAEND, MVT::Other, Expand);
128 for (auto T : {MVT::f32, MVT::f64}) {
129 // Don't expand the floating-point types to constant pools.
130 setOperationAction(ISD::ConstantFP, T, Legal);
131 // Expand floating-point comparisons.
132 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,
133 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
134 setCondCodeAction(CC, T, Expand);
135 // Expand floating-point library function operators.
136 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW,
137 ISD::FREM, ISD::FMA})
138 setOperationAction(Op, T, Expand);
139 // Note supported floating-point library function operators that otherwise
140 // default to expand.
142 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
143 setOperationAction(Op, T, Legal);
144 // Support minnan and maxnan, which otherwise default to expand.
145 setOperationAction(ISD::FMINNAN, T, Legal);
146 setOperationAction(ISD::FMAXNAN, T, Legal);
149 for (auto T : {MVT::i32, MVT::i64}) {
150 // Expand unavailable integer operations.
152 {ISD::BSWAP, ISD::ROTL, ISD::ROTR, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
153 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS,
154 ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC,
156 setOperationAction(Op, T, Expand);
160 // As a special case, these operators use the type to mean the type to
162 for (auto T : {MVT::i1, MVT::i8, MVT::i16, MVT::i32})
163 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
165 // Dynamic stack allocation: use the default expansion.
166 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
167 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
168 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand);
170 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
172 // Expand these forms; we pattern-match the forms that we can handle in isel.
173 for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
174 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
175 setOperationAction(Op, T, Expand);
177 // We have custom switch handling.
178 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
180 // WebAssembly doesn't have:
181 // - Floating-point extending loads.
182 // - Floating-point truncating stores.
183 // - i1 extending loads.
184 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
185 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
186 for (auto T : MVT::integer_valuetypes())
187 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
188 setLoadExtAction(Ext, T, MVT::i1, Promote);
190 // Trap lowers to wasm unreachable
191 setOperationAction(ISD::TRAP, MVT::Other, Legal);
194 FastISel *WebAssemblyTargetLowering::createFastISel(
195 FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const {
196 return WebAssembly::createFastISel(FuncInfo, LibInfo);
199 bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
200 const GlobalAddressSDNode * /*GA*/) const {
201 // All offsets can be folded.
205 MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/,
207 unsigned BitWidth = NextPowerOf2(VT.getSizeInBits() - 1);
208 if (BitWidth > 1 && BitWidth < 8)
210 MVT Result = MVT::getIntegerVT(BitWidth);
211 assert(Result != MVT::INVALID_SIMPLE_VALUE_TYPE &&
212 "Unable to represent scalar shift amount type");
217 WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
218 switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
219 case WebAssemblyISD::FIRST_NUMBER:
221 #define HANDLE_NODETYPE(NODE) \
222 case WebAssemblyISD::NODE: \
223 return "WebAssemblyISD::" #NODE;
224 #include "WebAssemblyISD.def"
225 #undef HANDLE_NODETYPE
230 std::pair<unsigned, const TargetRegisterClass *>
231 WebAssemblyTargetLowering::getRegForInlineAsmConstraint(
232 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
233 // First, see if this is a constraint that directly corresponds to a
234 // WebAssembly register class.
235 if (Constraint.size() == 1) {
236 switch (Constraint[0]) {
238 assert(VT != MVT::iPTR && "Pointer MVT not expected here");
239 if (VT.isInteger() && !VT.isVector()) {
240 if (VT.getSizeInBits() <= 32)
241 return std::make_pair(0U, &WebAssembly::I32RegClass);
242 if (VT.getSizeInBits() <= 64)
243 return std::make_pair(0U, &WebAssembly::I64RegClass);
251 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
254 bool WebAssemblyTargetLowering::isCheapToSpeculateCttz() const {
255 // Assume ctz is a relatively cheap operation.
259 bool WebAssemblyTargetLowering::isCheapToSpeculateCtlz() const {
260 // Assume clz is a relatively cheap operation.
264 bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL,
268 // WebAssembly offsets are added as unsigned without wrapping. The
269 // isLegalAddressingMode gives us no way to determine if wrapping could be
270 // happening, so we approximate this by accepting only non-negative offsets.
274 // WebAssembly has no scale register operands.
278 // Everything else is legal.
282 //===----------------------------------------------------------------------===//
283 // WebAssembly Lowering private implementation.
284 //===----------------------------------------------------------------------===//
286 //===----------------------------------------------------------------------===//
288 //===----------------------------------------------------------------------===//
290 static void fail(SDLoc DL, SelectionDAG &DAG, const char *msg) {
291 MachineFunction &MF = DAG.getMachineFunction();
292 DAG.getContext()->diagnose(
293 DiagnosticInfoUnsupported(DL, *MF.getFunction(), msg, SDValue()));
296 // Test whether the given calling convention is supported.
297 static bool CallingConvSupported(CallingConv::ID CallConv) {
298 // We currently support the language-independent target-independent
299 // conventions. We don't yet have a way to annotate calls with properties like
300 // "cold", and we don't have any call-clobbered registers, so these are mostly
301 // all handled the same.
302 return CallConv == CallingConv::C || CallConv == CallingConv::Fast ||
303 CallConv == CallingConv::Cold ||
304 CallConv == CallingConv::PreserveMost ||
305 CallConv == CallingConv::PreserveAll ||
306 CallConv == CallingConv::CXX_FAST_TLS;
310 WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
311 SmallVectorImpl<SDValue> &InVals) const {
312 SelectionDAG &DAG = CLI.DAG;
314 SDValue Chain = CLI.Chain;
315 SDValue Callee = CLI.Callee;
316 MachineFunction &MF = DAG.getMachineFunction();
318 CallingConv::ID CallConv = CLI.CallConv;
319 if (!CallingConvSupported(CallConv))
321 "WebAssembly doesn't support language-specific or target-specific "
322 "calling conventions yet");
323 if (CLI.IsPatchPoint)
324 fail(DL, DAG, "WebAssembly doesn't support patch point yet");
326 // WebAssembly doesn't currently support explicit tail calls. If they are
327 // required, fail. Otherwise, just disable them.
328 if ((CallConv == CallingConv::Fast && CLI.IsTailCall &&
329 MF.getTarget().Options.GuaranteedTailCallOpt) ||
330 (CLI.CS && CLI.CS->isMustTailCall()))
331 fail(DL, DAG, "WebAssembly doesn't support tail call yet");
332 CLI.IsTailCall = false;
334 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
336 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
338 fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet");
340 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
341 for (const ISD::OutputArg &Out : Outs) {
342 if (Out.Flags.isByVal())
343 fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
344 if (Out.Flags.isNest())
345 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
346 if (Out.Flags.isInAlloca())
347 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
348 if (Out.Flags.isInConsecutiveRegs())
349 fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
350 if (Out.Flags.isInConsecutiveRegsLast())
351 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
354 bool IsVarArg = CLI.IsVarArg;
355 unsigned NumFixedArgs = CLI.NumFixedArgs;
356 auto PtrVT = getPointerTy(MF.getDataLayout());
358 // Analyze operands of the call, assigning locations to each operand.
359 SmallVector<CCValAssign, 16> ArgLocs;
360 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
363 // Outgoing non-fixed arguments are placed at the top of the stack. First
364 // compute their offsets and the total amount of argument stack space
367 make_range(OutVals.begin() + NumFixedArgs, OutVals.end())) {
368 EVT VT = Arg.getValueType();
369 assert(VT != MVT::iPTR && "Legalized args should be concrete");
370 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
372 CCInfo.AllocateStack(MF.getDataLayout().getTypeAllocSize(Ty),
373 MF.getDataLayout().getABITypeAlignment(Ty));
374 CCInfo.addLoc(CCValAssign::getMem(ArgLocs.size(), VT.getSimpleVT(),
375 Offset, VT.getSimpleVT(),
380 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
384 NB = DAG.getConstant(NumBytes, DL, PtrVT, true);
385 Chain = DAG.getCALLSEQ_START(Chain, NB, DL);
389 // For non-fixed arguments, next emit stores to store the argument values
390 // to the stack at the offsets computed above.
391 SDValue SP = DAG.getCopyFromReg(
392 Chain, DL, getStackPointerRegisterToSaveRestore(), PtrVT);
394 SmallVector<SDValue, 8> Chains;
396 make_range(OutVals.begin() + NumFixedArgs, OutVals.end())) {
397 assert(ArgLocs[ValNo].getValNo() == ValNo &&
398 "ArgLocs should remain in order and only hold varargs args");
399 unsigned Offset = ArgLocs[ValNo++].getLocMemOffset();
400 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, SP,
401 DAG.getConstant(Offset, DL, PtrVT));
402 Chains.push_back(DAG.getStore(Chain, DL, Arg, Add,
403 MachinePointerInfo::getStack(MF, Offset),
407 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
410 // Compute the operands for the CALLn node.
411 SmallVector<SDValue, 16> Ops;
412 Ops.push_back(Chain);
413 Ops.push_back(Callee);
415 // Add all fixed arguments. Note that for non-varargs calls, NumFixedArgs
417 Ops.append(OutVals.begin(),
418 IsVarArg ? OutVals.begin() + NumFixedArgs : OutVals.end());
420 SmallVector<EVT, 8> Tys;
421 for (const auto &In : Ins) {
422 assert(!In.Flags.isByVal() && "byval is not valid for return values");
423 assert(!In.Flags.isNest() && "nest is not valid for return values");
424 if (In.Flags.isInAlloca())
425 fail(DL, DAG, "WebAssembly hasn't implemented inalloca return values");
426 if (In.Flags.isInConsecutiveRegs())
427 fail(DL, DAG, "WebAssembly hasn't implemented cons regs return values");
428 if (In.Flags.isInConsecutiveRegsLast())
430 "WebAssembly hasn't implemented cons regs last return values");
431 // Ignore In.getOrigAlign() because all our arguments are passed in
433 Tys.push_back(In.VT);
435 Tys.push_back(MVT::Other);
436 SDVTList TyList = DAG.getVTList(Tys);
438 DAG.getNode(Ins.empty() ? WebAssemblyISD::CALL0 : WebAssemblyISD::CALL1,
443 InVals.push_back(Res);
444 Chain = Res.getValue(1);
448 SDValue Unused = DAG.getTargetConstant(0, DL, PtrVT);
449 Chain = DAG.getCALLSEQ_END(Chain, NB, Unused, SDValue(), DL);
455 bool WebAssemblyTargetLowering::CanLowerReturn(
456 CallingConv::ID /*CallConv*/, MachineFunction & /*MF*/, bool /*IsVarArg*/,
457 const SmallVectorImpl<ISD::OutputArg> &Outs,
458 LLVMContext & /*Context*/) const {
459 // WebAssembly can't currently handle returning tuples.
460 return Outs.size() <= 1;
463 SDValue WebAssemblyTargetLowering::LowerReturn(
464 SDValue Chain, CallingConv::ID CallConv, bool /*IsVarArg*/,
465 const SmallVectorImpl<ISD::OutputArg> &Outs,
466 const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
467 SelectionDAG &DAG) const {
468 assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
469 if (!CallingConvSupported(CallConv))
470 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
472 SmallVector<SDValue, 4> RetOps(1, Chain);
473 RetOps.append(OutVals.begin(), OutVals.end());
474 Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, RetOps);
476 // Record the number and types of the return values.
477 for (const ISD::OutputArg &Out : Outs) {
478 assert(!Out.Flags.isByVal() && "byval is not valid for return values");
479 assert(!Out.Flags.isNest() && "nest is not valid for return values");
480 assert(Out.IsFixed && "non-fixed return value is not valid");
481 if (Out.Flags.isInAlloca())
482 fail(DL, DAG, "WebAssembly hasn't implemented inalloca results");
483 if (Out.Flags.isInConsecutiveRegs())
484 fail(DL, DAG, "WebAssembly hasn't implemented cons regs results");
485 if (Out.Flags.isInConsecutiveRegsLast())
486 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last results");
492 SDValue WebAssemblyTargetLowering::LowerFormalArguments(
493 SDValue Chain, CallingConv::ID CallConv, bool /*IsVarArg*/,
494 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
495 SmallVectorImpl<SDValue> &InVals) const {
496 MachineFunction &MF = DAG.getMachineFunction();
498 if (!CallingConvSupported(CallConv))
499 fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
501 // Set up the incoming ARGUMENTS value, which serves to represent the liveness
502 // of the incoming values before they're represented by virtual registers.
503 MF.getRegInfo().addLiveIn(WebAssembly::ARGUMENTS);
505 for (const ISD::InputArg &In : Ins) {
506 if (In.Flags.isByVal())
507 fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
508 if (In.Flags.isInAlloca())
509 fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
510 if (In.Flags.isNest())
511 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
512 if (In.Flags.isInConsecutiveRegs())
513 fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
514 if (In.Flags.isInConsecutiveRegsLast())
515 fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
516 // Ignore In.getOrigAlign() because all our arguments are passed in
520 ? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
521 DAG.getTargetConstant(InVals.size(), DL, MVT::i32))
522 : DAG.getUNDEF(In.VT));
524 // Record the number and types of arguments.
525 MF.getInfo<WebAssemblyFunctionInfo>()->addParam(In.VT);
528 // Incoming varargs arguments are on the stack and will be accessed through
529 // va_arg, so we don't need to do anything for them here.
534 //===----------------------------------------------------------------------===//
535 // Custom lowering hooks.
536 //===----------------------------------------------------------------------===//
538 SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
539 SelectionDAG &DAG) const {
540 switch (Op.getOpcode()) {
542 llvm_unreachable("unimplemented operation lowering");
544 case ISD::FrameIndex:
545 return LowerFrameIndex(Op, DAG);
546 case ISD::GlobalAddress:
547 return LowerGlobalAddress(Op, DAG);
548 case ISD::ExternalSymbol:
549 return LowerExternalSymbol(Op, DAG);
551 return LowerJumpTable(Op, DAG);
553 return LowerBR_JT(Op, DAG);
555 return LowerVASTART(Op, DAG);
559 SDValue WebAssemblyTargetLowering::LowerFrameIndex(SDValue Op,
560 SelectionDAG &DAG) const {
561 int FI = cast<FrameIndexSDNode>(Op)->getIndex();
562 return DAG.getTargetFrameIndex(FI, Op.getValueType());
565 SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
566 SelectionDAG &DAG) const {
568 const auto *GA = cast<GlobalAddressSDNode>(Op);
569 EVT VT = Op.getValueType();
570 assert(GA->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
571 if (GA->getAddressSpace() != 0)
572 fail(DL, DAG, "WebAssembly only expects the 0 address space");
574 WebAssemblyISD::Wrapper, DL, VT,
575 DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT, GA->getOffset()));
579 WebAssemblyTargetLowering::LowerExternalSymbol(SDValue Op,
580 SelectionDAG &DAG) const {
582 const auto *ES = cast<ExternalSymbolSDNode>(Op);
583 EVT VT = Op.getValueType();
584 assert(ES->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
585 return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
586 DAG.getTargetExternalSymbol(ES->getSymbol(), VT));
589 SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
590 SelectionDAG &DAG) const {
591 // There's no need for a Wrapper node because we always incorporate a jump
592 // table operand into a TABLESWITCH instruction, rather than ever
593 // materializing it in a register.
594 const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
595 return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
596 JT->getTargetFlags());
599 SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
600 SelectionDAG &DAG) const {
602 SDValue Chain = Op.getOperand(0);
603 const auto *JT = cast<JumpTableSDNode>(Op.getOperand(1));
604 SDValue Index = Op.getOperand(2);
605 assert(JT->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
607 SmallVector<SDValue, 8> Ops;
608 Ops.push_back(Chain);
609 Ops.push_back(Index);
611 MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
612 const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
614 // TODO: For now, we just pick something arbitrary for a default case for now.
615 // We really want to sniff out the guard and put in the real default case (and
616 // delete the guard).
617 Ops.push_back(DAG.getBasicBlock(MBBs[0]));
619 // Add an operand for each case.
620 for (auto MBB : MBBs)
621 Ops.push_back(DAG.getBasicBlock(MBB));
623 return DAG.getNode(WebAssemblyISD::TABLESWITCH, DL, MVT::Other, Ops);
626 SDValue WebAssemblyTargetLowering::LowerVASTART(SDValue Op,
627 SelectionDAG &DAG) const {
629 EVT PtrVT = getPointerTy(DAG.getMachineFunction().getDataLayout());
631 // The incoming non-fixed arguments are placed on the top of the stack, with
632 // natural alignment, at the point of the call, so the base pointer is just
633 // the current frame pointer.
634 DAG.getMachineFunction().getFrameInfo()->setFrameAddressIsTaken(true);
636 Subtarget->getRegisterInfo()->getFrameRegister(DAG.getMachineFunction());
637 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, FP, PtrVT);
638 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
639 return DAG.getStore(Op.getOperand(0), DL, FrameAddr, Op.getOperand(1),
640 MachinePointerInfo(SV), false, false, 0);
643 //===----------------------------------------------------------------------===//
644 // WebAssembly Optimization Hooks
645 //===----------------------------------------------------------------------===//
647 MCSection *WebAssemblyTargetObjectFile::SelectSectionForGlobal(
648 const GlobalValue *GV, SectionKind /*Kind*/, Mangler & /*Mang*/,
649 const TargetMachine & /*TM*/) const {
650 // TODO: Be more sophisticated than this.
651 return isa<Function>(GV) ? getTextSection() : getDataSection();