1 //===-- TargetMachine.cpp - General Target Information ---------------------==//
3 // This file describes the general parts of a Target machine.
5 //===----------------------------------------------------------------------===//
7 #include "llvm/Target/SchedInfo.h"
8 #include "llvm/Target/Machine.h"
9 #include "llvm/DerivedTypes.h"
11 // External object describing the machine instructions
12 // Initialized only when the TargetMachine class is created
13 // and reset when that class is destroyed.
15 const MachineInstrDescriptor* TargetInstrDescriptors = NULL;
17 resourceId_t MachineResource::nextId = 0;
19 static cycles_t ComputeMinGap (const InstrRUsage& fromRU,
20 const InstrRUsage& toRU);
22 static bool RUConflict (const vector<resourceId_t>& fromRVec,
23 const vector<resourceId_t>& fromRVec);
25 //---------------------------------------------------------------------------
26 // class TargetMachine
29 // Machine description.
31 //---------------------------------------------------------------------------
34 // function TargetMachine::findOptimalStorageSize
37 // This default implementation assumes that all sub-word data items use
38 // space equal to optSizeForSubWordData, and all other primitive data
39 // items use space according to the type.
41 unsigned int TargetMachine::findOptimalStorageSize(const Type* ty) const {
42 switch(ty->getPrimitiveID()) {
46 case Type::UShortTyID:
48 return optSizeForSubWordData;
51 return DataLayout.getTypeSize(ty);
56 //---------------------------------------------------------------------------
57 // class MachineInstructionInfo
58 // Interface to description of machine instructions
59 //---------------------------------------------------------------------------
63 MachineInstrInfo::MachineInstrInfo(const MachineInstrDescriptor* _desc,
64 unsigned int _descSize,
65 unsigned int _numRealOpCodes)
66 : desc(_desc), descSize(_descSize), numRealOpCodes(_numRealOpCodes)
68 assert(TargetInstrDescriptors == NULL && desc != NULL);
69 TargetInstrDescriptors = desc; // initialize global variable
74 MachineInstrInfo::~MachineInstrInfo()
76 TargetInstrDescriptors = NULL; // reset global variable
81 MachineInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
82 int64_t intValue) const
84 // First, check if opCode has an immed field.
86 uint64_t maxImmedValue = this->maxImmedConstant(opCode, isSignExtended);
87 if (maxImmedValue != 0)
89 // Now check if the constant fits
90 if (intValue <= (int64_t) maxImmedValue &&
91 intValue >= -((int64_t) maxImmedValue+1))
99 //---------------------------------------------------------------------------
100 // class MachineSchedInfo
101 // Interface to machine description for instruction scheduling
102 //---------------------------------------------------------------------------
105 MachineSchedInfo::MachineSchedInfo(int _numSchedClasses,
106 const MachineInstrInfo* _mii,
107 const InstrClassRUsage* _classRUsages,
108 const InstrRUsageDelta* _usageDeltas,
109 const InstrIssueDelta* _issueDeltas,
110 unsigned int _numUsageDeltas,
111 unsigned int _numIssueDeltas)
112 : numSchedClasses(_numSchedClasses),
114 classRUsages(_classRUsages),
115 usageDeltas(_usageDeltas),
116 issueDeltas(_issueDeltas),
117 numUsageDeltas(_numUsageDeltas),
118 numIssueDeltas(_numIssueDeltas)
123 MachineSchedInfo::initializeResources()
125 assert(MAX_NUM_SLOTS >= (int) getMaxNumIssueTotal()
126 && "Insufficient slots for static data! Increase MAX_NUM_SLOTS");
128 // First, compute common resource usage info for each class because
129 // most instructions will probably behave the same as their class.
130 // Cannot allocate a vector of InstrRUsage so new each one.
132 vector<InstrRUsage> instrRUForClasses;
133 instrRUForClasses.resize(numSchedClasses);
134 for (InstrSchedClass sc=0; sc < numSchedClasses; sc++)
136 // instrRUForClasses.push_back(new InstrRUsage);
137 instrRUForClasses[sc].setMaxSlots(getMaxNumIssueTotal());
138 instrRUForClasses[sc] = classRUsages[sc];
141 computeInstrResources(instrRUForClasses);
143 computeIssueGaps(instrRUForClasses);
148 MachineSchedInfo::computeInstrResources(const vector<InstrRUsage>& instrRUForClasses)
150 int numOpCodes = mii->getNumRealOpCodes();
151 instrRUsages.resize(numOpCodes);
153 // First get the resource usage information from the class resource usages.
154 for (MachineOpCode op=0; op < numOpCodes; op++)
156 InstrSchedClass sc = getSchedClass(op);
157 assert(sc >= 0 && sc < numSchedClasses);
158 instrRUsages[op] = instrRUForClasses[sc];
161 // Now, modify the resource usages as specified in the deltas.
162 for (unsigned i=0; i < numUsageDeltas; i++)
164 MachineOpCode op = usageDeltas[i].opCode;
165 assert(op < numOpCodes);
166 instrRUsages[op].addUsageDelta(usageDeltas[i]);
169 // Then modify the issue restrictions as specified in the deltas.
170 for (unsigned i=0; i < numIssueDeltas; i++)
172 MachineOpCode op = issueDeltas[i].opCode;
173 assert(op < numOpCodes);
174 instrRUsages[issueDeltas[i].opCode].addIssueDelta(issueDeltas[i]);
180 MachineSchedInfo::computeIssueGaps(const vector<InstrRUsage>& instrRUForClasses)
182 int numOpCodes = mii->getNumRealOpCodes();
183 instrRUsages.resize(numOpCodes);
185 assert(numOpCodes < (1 << MAX_OPCODE_SIZE) - 1
186 && "numOpCodes invalid for implementation of class OpCodePair!");
188 // First, compute issue gaps between pairs of classes based on common
189 // resources usages for each class, because most instruction pairs will
190 // usually behave the same as their class.
192 int classPairGaps[numSchedClasses][numSchedClasses];
193 for (InstrSchedClass fromSC=0; fromSC < numSchedClasses; fromSC++)
194 for (InstrSchedClass toSC=0; toSC < numSchedClasses; toSC++)
196 int classPairGap = ComputeMinGap(instrRUForClasses[fromSC],
197 instrRUForClasses[toSC]);
198 classPairGaps[fromSC][toSC] = classPairGap;
201 // Now, for each pair of instructions, use the class pair gap if both
202 // instructions have identical resource usage as their respective classes.
203 // If not, recompute the gap for the pair from scratch.
205 longestIssueConflict = 0;
207 for (MachineOpCode fromOp=0; fromOp < numOpCodes; fromOp++)
208 for (MachineOpCode toOp=0; toOp < numOpCodes; toOp++)
211 (instrRUsages[fromOp].sameAsClass && instrRUsages[toOp].sameAsClass)
212 ? classPairGaps[getSchedClass(fromOp)][getSchedClass(toOp)]
213 : ComputeMinGap(instrRUsages[fromOp], instrRUsages[toOp]);
215 if (instrPairGap > 0)
217 issueGaps[OpCodePair(fromOp,toOp)] = instrPairGap;
218 conflictLists[fromOp].push_back(toOp);
219 longestIssueConflict = max(longestIssueConflict, instrPairGap);
225 // Check if fromRVec and toRVec have *any* common entries.
226 // Assume the vectors are sorted in increasing order.
227 // Algorithm copied from function set_intersection() for sorted ranges (stl_algo.h).
229 RUConflict(const vector<resourceId_t>& fromRVec,
230 const vector<resourceId_t>& toRVec)
232 bool commonElementFound = false;
234 unsigned fN = fromRVec.size(), tN = toRVec.size();
235 unsigned fi = 0, ti = 0;
236 while (fi < fN && ti < tN)
237 if (fromRVec[fi] < toRVec[ti])
239 else if (toRVec[ti] < fromRVec[fi])
243 commonElementFound = true;
247 return commonElementFound;
252 ComputeMinGap(const InstrRUsage& fromRU, const InstrRUsage& toRU)
256 if (fromRU.numBubbles > 0)
257 minGap = fromRU.numBubbles;
259 if (minGap < fromRU.numCycles)
261 // only need to check from cycle `minGap' onwards
262 for (cycles_t gap=minGap; gap <= fromRU.numCycles-1; gap++)
264 // check if instr. #2 can start executing `gap' cycles after #1
265 // by checking for resource conflicts in each overlapping cycle
266 cycles_t numOverlap = min(fromRU.numCycles - gap, toRU.numCycles);
267 for (cycles_t c = 0; c <= numOverlap-1; c++)
268 if (RUConflict(fromRU.resourcesByCycle[gap + c],
269 toRU.resourcesByCycle[c]))
270 {// conflict found so minGap must be more than `gap'
280 //---------------------------------------------------------------------------