1 //===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15 [(callseq_start timm:$amt)]>;
16 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17 [(callseq_end timm:$amt1, timm:$amt2)]>;
19 let neverHasSideEffects = 1 in {
20 // Takes as input the value of the stack pointer after a dynamic allocation
21 // has been made. Sets the output to the address of the dynamically-
22 // allocated area itself, skipping the outgoing arguments.
24 // This expands to an LA or LAY instruction. We restrict the offset
25 // to the range of LA and keep the LAY range in reserve for when
26 // the size of the outgoing arguments is added.
27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28 [(set GR64:$dst, dynalloc12only:$src)]>;
31 //===----------------------------------------------------------------------===//
32 // Control flow instructions
33 //===----------------------------------------------------------------------===//
35 // A return instruction. R1 is the condition-code mask (all 1s)
36 // and R2 is the target address, which is always stored in %r14.
37 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1,
38 R1 = 15, R2 = 14, isCodeGenOnly = 1 in {
39 def RET : InstRR<0x07, (outs), (ins), "br\t%r14", [(z_retflag)]>;
42 // Unconditional branches. R1 is the condition-code mask (all 1s).
43 let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
44 let isIndirectBranch = 1 in
45 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
46 "br\t$R2", [(brind ADDR64:$R2)]>;
48 // An assembler extended mnemonic for BRC.
49 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
52 // An assembler extended mnemonic for BRCL. (The extension is "G"
53 // rather than "L" because "JL" is "Jump if Less".)
54 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
57 // Conditional branches. It's easier for LLVM to handle these branches
58 // in their raw BRC/BRCL form, with the 4-bit condition-code mask being
59 // the first operand. It seems friendlier to use mnemonic forms like
60 // JE and JLH when writing out the assembly though.
61 let isBranch = 1, isTerminator = 1, Uses = [CC] in {
62 let isCodeGenOnly = 1, CCMaskFirst = 1 in {
63 def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1,
64 brtarget16:$I2), "j$R1\t$I2",
65 [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
66 def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
67 brtarget32:$I2), "jg$R1\t$I2", []>;
69 def AsmBRC : InstRI<0xA74, (outs), (ins uimm8zx4:$R1, brtarget16:$I2),
71 def AsmBRCL : InstRIL<0xC04, (outs), (ins uimm8zx4:$R1, brtarget32:$I2),
72 "brcl\t$R1, $I2", []>;
75 // Fused compare-and-branch instructions. As for normal branches,
76 // we handle these instructions internally in their raw CRJ-like form,
77 // but use assembly macros like CRJE when writing them out.
79 // These instructions do not use or clobber the condition codes.
80 // We nevertheless pretend that they clobber CC, so that we can lower
81 // them to separate comparisons and BRCLs if the branch ends up being
83 multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
84 let isBranch = 1, isTerminator = 1, Defs = [CC] in {
85 def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
87 "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
88 def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
90 "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
91 def IJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
93 "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
94 def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
96 "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
99 let isCodeGenOnly = 1 in
100 defm C : CompareBranches<cond4, "$M3", "">;
101 defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">;
103 // Define AsmParser mnemonics for each general condition-code mask
104 // (integer or floating-point)
105 multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
107 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
108 "j"##name##"\t$I2", []>;
109 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
110 "jg"##name##"\t$I2", []>;
112 def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>;
113 def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
114 def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>;
115 def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>;
116 def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>;
117 def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
119 defm AsmO : CondExtendedMnemonic<1, "o">;
120 defm AsmH : CondExtendedMnemonic<2, "h">;
121 defm AsmNLE : CondExtendedMnemonic<3, "nle">;
122 defm AsmL : CondExtendedMnemonic<4, "l">;
123 defm AsmNHE : CondExtendedMnemonic<5, "nhe">;
124 defm AsmLH : CondExtendedMnemonic<6, "lh">;
125 defm AsmNE : CondExtendedMnemonic<7, "ne">;
126 defm AsmE : CondExtendedMnemonic<8, "e">;
127 defm AsmNLH : CondExtendedMnemonic<9, "nlh">;
128 defm AsmHE : CondExtendedMnemonic<10, "he">;
129 defm AsmNL : CondExtendedMnemonic<11, "nl">;
130 defm AsmLE : CondExtendedMnemonic<12, "le">;
131 defm AsmNH : CondExtendedMnemonic<13, "nh">;
132 defm AsmNO : CondExtendedMnemonic<14, "no">;
134 // Define AsmParser mnemonics for each integer condition-code mask.
135 // This is like the list above, except that condition 3 is not possible
136 // and that the low bit of the mask is therefore always 0. This means
137 // that each condition has two names. Conditions "o" and "no" are not used.
139 // We don't make one of the two names an alias of the other because
140 // we need the custom parsing routines to select the correct register class.
141 multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
143 def CR : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
145 "crj"##name##"\t$R1, $R2, $RI4", []>;
146 def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
148 "cgrj"##name##"\t$R1, $R2, $RI4", []>;
149 def CI : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
151 "cij"##name##"\t$R1, $I2, $RI4", []>;
152 def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
154 "cgij"##name##"\t$R1, $I2, $RI4", []>;
157 multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
158 : IntCondExtendedMnemonicA<ccmask, name1> {
159 let isAsmParserOnly = 1 in
160 defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
162 defm AsmJH : IntCondExtendedMnemonic<2, "h", "nle">;
163 defm AsmJL : IntCondExtendedMnemonic<4, "l", "nhe">;
164 defm AsmJLH : IntCondExtendedMnemonic<6, "lh", "ne">;
165 defm AsmJE : IntCondExtendedMnemonic<8, "e", "nlh">;
166 defm AsmJHE : IntCondExtendedMnemonic<10, "he", "nl">;
167 defm AsmJLE : IntCondExtendedMnemonic<12, "le", "nh">;
169 //===----------------------------------------------------------------------===//
170 // Select instructions
171 //===----------------------------------------------------------------------===//
173 def Select32 : SelectWrapper<GR32>;
174 def Select64 : SelectWrapper<GR64>;
176 defm CondStore8_32 : CondStores<GR32, nonvolatile_truncstorei8,
177 nonvolatile_anyextloadi8, bdxaddr20only>;
178 defm CondStore16_32 : CondStores<GR32, nonvolatile_truncstorei16,
179 nonvolatile_anyextloadi16, bdxaddr20only>;
180 defm CondStore32_32 : CondStores<GR32, nonvolatile_store,
181 nonvolatile_load, bdxaddr20only>;
183 defm CondStore8 : CondStores<GR64, nonvolatile_truncstorei8,
184 nonvolatile_anyextloadi8, bdxaddr20only>;
185 defm CondStore16 : CondStores<GR64, nonvolatile_truncstorei16,
186 nonvolatile_anyextloadi16, bdxaddr20only>;
187 defm CondStore32 : CondStores<GR64, nonvolatile_truncstorei32,
188 nonvolatile_anyextloadi32, bdxaddr20only>;
189 defm CondStore64 : CondStores<GR64, nonvolatile_store,
190 nonvolatile_load, bdxaddr20only>;
192 //===----------------------------------------------------------------------===//
194 //===----------------------------------------------------------------------===//
196 // The definitions here are for the call-clobbered registers.
197 let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
198 F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D, CC],
199 R1 = 14, isCodeGenOnly = 1 in {
200 def BRAS : InstRI<0xA75, (outs), (ins pcrel16call:$I2, variable_ops),
201 "bras\t%r14, $I2", []>;
202 def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$I2, variable_ops),
203 "brasl\t%r14, $I2", [(z_call pcrel32call:$I2)]>;
204 def BASR : InstRR<0x0D, (outs), (ins ADDR64:$R2, variable_ops),
205 "basr\t%r14, $R2", [(z_call ADDR64:$R2)]>;
208 // Define the general form of the call instructions for the asm parser.
209 // These instructions don't hard-code %r14 as the return address register.
210 def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
211 "bras\t$R1, $I2", []>;
212 def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2),
213 "brasl\t$R1, $I2", []>;
214 def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
215 "basr\t$R1, $R2", []>;
217 //===----------------------------------------------------------------------===//
219 //===----------------------------------------------------------------------===//
222 let neverHasSideEffects = 1 in {
223 def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>;
224 def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
227 // Move on condition.
228 let isCodeGenOnly = 1, Uses = [CC] in {
229 def LOCR : CondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
230 def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
233 def AsmLOCR : AsmCondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
234 def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
238 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
239 isReMaterializable = 1 in {
240 // 16-bit sign-extended immediates.
241 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>;
242 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
244 // Other 16-bit immediates.
245 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
246 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
247 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
248 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
250 // 32-bit immediates.
251 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>;
252 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
253 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
257 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
258 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
259 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
261 // These instructions are split after register allocation, so we don't
262 // want a custom inserter.
263 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
264 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
265 [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
268 let canFoldAsLoad = 1 in {
269 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
270 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
273 // Load on condition.
274 let isCodeGenOnly = 1, Uses = [CC] in {
275 def LOC : CondUnaryRSY<"loc", 0xEBF2, nonvolatile_load, GR32, 4>;
276 def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>;
279 def AsmLOC : AsmCondUnaryRSY<"loc", 0xEBF2, GR32, 4>;
280 def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
284 let SimpleBDXStore = 1 in {
285 let isCodeGenOnly = 1 in
286 defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
287 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
289 // These instructions are split after register allocation, so we don't
290 // want a custom inserter.
291 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
292 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
293 [(store GR128:$src, bdxaddr20only128:$dst)]>;
296 let isCodeGenOnly = 1 in
297 def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
298 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
300 // Store on condition.
301 let isCodeGenOnly = 1, Uses = [CC] in {
302 def STOC32 : CondStoreRSY<"stoc", 0xEBF3, GR32, 4>;
303 def STOC : CondStoreRSY<"stoc", 0xEBF3, GR64, 4>;
304 def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
307 def AsmSTOC : AsmCondStoreRSY<"stoc", 0xEBF3, GR32, 4>;
308 def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
311 // 8-bit immediate stores to 8-bit fields.
312 defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
314 // 16-bit immediate stores to 16-, 32- or 64-bit fields.
315 def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
316 def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>;
317 def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;
319 // Memory-to-memory moves.
320 let mayLoad = 1, mayStore = 1 in
321 def MVC : InstSS<0xD2, (outs), (ins bdladdr12onlylen8:$BDL1,
323 "mvc\t$BDL1, $BD2", []>;
325 let mayLoad = 1, mayStore = 1, usesCustomInserter = 1 in
326 def MVCWrapper : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
328 [(z_mvc bdaddr12only:$dest, bdaddr12only:$src,
329 imm32len8:$length)]>;
331 defm LoadStore8_32 : MVCLoadStore<anyextloadi8, truncstorei8, i32,
333 defm LoadStore16_32 : MVCLoadStore<anyextloadi16, truncstorei16, i32,
335 defm LoadStore32_32 : MVCLoadStore<load, store, i32, MVCWrapper, 4>;
337 defm LoadStore8 : MVCLoadStore<anyextloadi8, truncstorei8, i64,
339 defm LoadStore16 : MVCLoadStore<anyextloadi16, truncstorei16, i64,
341 defm LoadStore32 : MVCLoadStore<anyextloadi32, truncstorei32, i64,
343 defm LoadStore64 : MVCLoadStore<load, store, i64, MVCWrapper, 8>;
345 //===----------------------------------------------------------------------===//
347 //===----------------------------------------------------------------------===//
349 // 32-bit extensions from registers.
350 let neverHasSideEffects = 1 in {
351 def LBR : UnaryRRE<"lb", 0xB926, sext8, GR32, GR32>;
352 def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
355 // 64-bit extensions from registers.
356 let neverHasSideEffects = 1 in {
357 def LGBR : UnaryRRE<"lgb", 0xB906, sext8, GR64, GR64>;
358 def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
359 def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
362 // Match 32-to-64-bit sign extensions in which the source is already
363 // in a 64-bit register.
364 def : Pat<(sext_inreg GR64:$src, i32),
365 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
367 // 32-bit extensions from memory.
368 def LB : UnaryRXY<"lb", 0xE376, sextloadi8, GR32, 1>;
369 defm LH : UnaryRXPair<"lh", 0x48, 0xE378, sextloadi16, GR32, 2>;
370 def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_sextloadi16, GR32>;
372 // 64-bit extensions from memory.
373 def LGB : UnaryRXY<"lgb", 0xE377, sextloadi8, GR64, 1>;
374 def LGH : UnaryRXY<"lgh", 0xE315, sextloadi16, GR64, 2>;
375 def LGF : UnaryRXY<"lgf", 0xE314, sextloadi32, GR64, 4>;
376 def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_sextloadi16, GR64>;
377 def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_sextloadi32, GR64>;
379 // If the sign of a load-extend operation doesn't matter, use the signed ones.
380 // There's not really much to choose between the sign and zero extensions,
381 // but LH is more compact than LLH for small offsets.
382 def : Pat<(i32 (extloadi8 bdxaddr20only:$src)), (LB bdxaddr20only:$src)>;
383 def : Pat<(i32 (extloadi16 bdxaddr12pair:$src)), (LH bdxaddr12pair:$src)>;
384 def : Pat<(i32 (extloadi16 bdxaddr20pair:$src)), (LHY bdxaddr20pair:$src)>;
386 def : Pat<(i64 (extloadi8 bdxaddr20only:$src)), (LGB bdxaddr20only:$src)>;
387 def : Pat<(i64 (extloadi16 bdxaddr20only:$src)), (LGH bdxaddr20only:$src)>;
388 def : Pat<(i64 (extloadi32 bdxaddr20only:$src)), (LGF bdxaddr20only:$src)>;
390 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
391 // However, BDXs have two extra operands and are therefore 6 units more
393 let AddedComplexity = 7 in {
394 def : Pat<(i32 (extloadi16 pcrel32:$src)), (LHRL pcrel32:$src)>;
395 def : Pat<(i64 (extloadi16 pcrel32:$src)), (LGHRL pcrel32:$src)>;
398 //===----------------------------------------------------------------------===//
400 //===----------------------------------------------------------------------===//
402 // 32-bit extensions from registers.
403 let neverHasSideEffects = 1 in {
404 def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>;
405 def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
408 // 64-bit extensions from registers.
409 let neverHasSideEffects = 1 in {
410 def LLGCR : UnaryRRE<"llgc", 0xB984, zext8, GR64, GR64>;
411 def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
412 def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
415 // Match 32-to-64-bit zero extensions in which the source is already
416 // in a 64-bit register.
417 def : Pat<(and GR64:$src, 0xffffffff),
418 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
420 // 32-bit extensions from memory.
421 def LLC : UnaryRXY<"llc", 0xE394, zextloadi8, GR32, 1>;
422 def LLH : UnaryRXY<"llh", 0xE395, zextloadi16, GR32, 2>;
423 def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_zextloadi16, GR32>;
425 // 64-bit extensions from memory.
426 def LLGC : UnaryRXY<"llgc", 0xE390, zextloadi8, GR64, 1>;
427 def LLGH : UnaryRXY<"llgh", 0xE391, zextloadi16, GR64, 2>;
428 def LLGF : UnaryRXY<"llgf", 0xE316, zextloadi32, GR64, 4>;
429 def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_zextloadi16, GR64>;
430 def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_zextloadi32, GR64>;
432 //===----------------------------------------------------------------------===//
434 //===----------------------------------------------------------------------===//
436 // Truncations of 64-bit registers to 32-bit registers.
437 def : Pat<(i32 (trunc GR64:$src)),
438 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
440 // Truncations of 32-bit registers to memory.
441 let isCodeGenOnly = 1 in {
442 defm STC32 : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
443 defm STH32 : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
444 def STHRL32 : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
447 // Truncations of 64-bit registers to memory.
448 defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR64, 1>;
449 defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR64, 2>;
450 def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR64>;
451 defm ST : StoreRXPair<"st", 0x50, 0xE350, truncstorei32, GR64, 4>;
452 def STRL : StoreRILPC<"strl", 0xC4F, aligned_truncstorei32, GR64>;
454 //===----------------------------------------------------------------------===//
455 // Multi-register moves
456 //===----------------------------------------------------------------------===//
458 // Multi-register loads.
459 def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
461 // Multi-register stores.
462 def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
464 //===----------------------------------------------------------------------===//
466 //===----------------------------------------------------------------------===//
468 // Byte-swapping register moves.
469 let neverHasSideEffects = 1 in {
470 def LRVR : UnaryRRE<"lrv", 0xB91F, bswap, GR32, GR32>;
471 def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
474 // Byte-swapping loads. Unlike normal loads, these instructions are
475 // allowed to access storage more than once.
476 def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>;
477 def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>;
479 // Likewise byte-swapping stores.
480 def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>;
481 def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>,
484 //===----------------------------------------------------------------------===//
485 // Load address instructions
486 //===----------------------------------------------------------------------===//
488 // Load BDX-style addresses.
489 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
491 let DispSize = "12" in
492 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
494 [(set GR64:$R1, laaddr12pair:$XBD2)]>;
495 let DispSize = "20" in
496 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
498 [(set GR64:$R1, laaddr20pair:$XBD2)]>;
501 // Load a PC-relative address. There's no version of this instruction
502 // with a 16-bit offset, so there's no relaxation.
503 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
504 isReMaterializable = 1 in {
505 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
507 [(set GR64:$R1, pcrel32:$I2)]>;
510 //===----------------------------------------------------------------------===//
512 //===----------------------------------------------------------------------===//
515 let CCValues = 0xF, CCHasZero = 1 in {
516 def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>;
517 def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
519 let CCValues = 0xE, CCHasZero = 1, CCHasOrder = 1 in
520 def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
522 defm : SXU<ineg, LCGFR>;
524 //===----------------------------------------------------------------------===//
526 //===----------------------------------------------------------------------===//
528 let isCodeGenOnly = 1 in
529 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, zextloadi8, 1>;
530 defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, zextloadi8, 1>;
532 defm : InsertMem<"inserti8", IC32, GR32, zextloadi8, bdxaddr12pair>;
533 defm : InsertMem<"inserti8", IC32Y, GR32, zextloadi8, bdxaddr20pair>;
535 defm : InsertMem<"inserti8", IC, GR64, zextloadi8, bdxaddr12pair>;
536 defm : InsertMem<"inserti8", ICY, GR64, zextloadi8, bdxaddr20pair>;
538 // Insertions of a 16-bit immediate, leaving other bits unaffected.
539 // We don't have or_as_insert equivalents of these operations because
540 // OI is available instead.
541 let isCodeGenOnly = 1 in {
542 def IILL32 : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
543 def IILH32 : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
545 def IILL : BinaryRI<"iill", 0xA53, insertll, GR64, imm64ll16>;
546 def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR64, imm64lh16>;
547 def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>;
548 def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>;
550 // ...likewise for 32-bit immediates. For GR32s this is a general
551 // full-width move. (We use IILF rather than something like LLILF
552 // for 32-bit moves because IILF leaves the upper 32 bits of the
554 let isCodeGenOnly = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
555 isReMaterializable = 1 in {
556 def IILF32 : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
558 def IILF : BinaryRIL<"iilf", 0xC09, insertlf, GR64, imm64lf32>;
559 def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>;
561 // An alternative model of inserthf, with the first operand being
562 // a zero-extended value.
563 def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
564 (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit),
567 //===----------------------------------------------------------------------===//
569 //===----------------------------------------------------------------------===//
572 let Defs = [CC], CCValues = 0xF, CCHasZero = 1 in {
573 // Addition of a register.
574 let isCommutable = 1 in {
575 defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
576 defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
578 def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
580 // Addition of signed 16-bit immediates.
581 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>;
582 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
584 // Addition of signed 32-bit immediates.
585 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>;
586 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
588 // Addition of memory.
589 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, sextloadi16, 2>;
590 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>;
591 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, sextloadi32, 4>;
592 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>;
594 // Addition to memory.
595 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>;
596 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
598 defm : SXB<add, GR64, AGFR>;
600 // Addition producing a carry.
602 // Addition of a register.
603 let isCommutable = 1 in {
604 defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
605 defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
607 def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
609 // Addition of signed 16-bit immediates.
610 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>,
611 Requires<[FeatureDistinctOps]>;
612 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>,
613 Requires<[FeatureDistinctOps]>;
615 // Addition of unsigned 32-bit immediates.
616 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>;
617 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
619 // Addition of memory.
620 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>;
621 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, zextloadi32, 4>;
622 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>;
624 defm : ZXB<addc, GR64, ALGFR>;
626 // Addition producing and using a carry.
627 let Defs = [CC], Uses = [CC] in {
628 // Addition of a register.
629 def ALCR : BinaryRRE<"alc", 0xB998, adde, GR32, GR32>;
630 def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
632 // Addition of memory.
633 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>;
634 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>;
637 //===----------------------------------------------------------------------===//
639 //===----------------------------------------------------------------------===//
641 // Plain substraction. Although immediate forms exist, we use the
642 // add-immediate instruction instead.
643 let Defs = [CC], CCValues = 0xF, CCHasZero = 1 in {
644 // Subtraction of a register.
645 defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
646 def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
647 defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
649 // Subtraction of memory.
650 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, sextloadi16, 2>;
651 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>;
652 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, sextloadi32, 4>;
653 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>;
655 defm : SXB<sub, GR64, SGFR>;
657 // Subtraction producing a carry.
659 // Subtraction of a register.
660 defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
661 def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
662 defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
664 // Subtraction of unsigned 32-bit immediates. These don't match
665 // subc because we prefer addc for constants.
666 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>;
667 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
669 // Subtraction of memory.
670 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
671 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, zextloadi32, 4>;
672 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>;
674 defm : ZXB<subc, GR64, SLGFR>;
676 // Subtraction producing and using a carry.
677 let Defs = [CC], Uses = [CC] in {
678 // Subtraction of a register.
679 def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>;
680 def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
682 // Subtraction of memory.
683 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>;
684 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
687 //===----------------------------------------------------------------------===//
689 //===----------------------------------------------------------------------===//
692 // ANDs of a register.
693 let isCommutable = 1, CCValues = 0xC, CCHasZero = 1 in {
694 defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
695 defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
698 let isConvertibleToThreeAddress = 1 in {
699 // ANDs of a 16-bit immediate, leaving other bits unaffected.
700 // The CC result only reflects the 16-bit field, not the full register.
701 let isCodeGenOnly = 1 in {
702 def NILL32 : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
703 def NILH32 : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
705 def NILL : BinaryRI<"nill", 0xA57, and, GR64, imm64ll16c>;
706 def NILH : BinaryRI<"nilh", 0xA56, and, GR64, imm64lh16c>;
707 def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>;
708 def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>;
710 // ANDs of a 32-bit immediate, leaving other bits unaffected.
711 // The CC result only reflects the 32-bit field, which means we can
712 // use it as a zero indicator for i32 operations but not otherwise.
713 let isCodeGenOnly = 1, CCValues = 0xC, CCHasZero = 1 in
714 def NILF32 : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
715 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR64, imm64lf32c>;
716 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>;
720 let CCValues = 0xC, CCHasZero = 1 in {
721 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>;
722 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>;
726 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>;
728 defm : RMWIByte<and, bdaddr12pair, NI>;
729 defm : RMWIByte<and, bdaddr20pair, NIY>;
731 //===----------------------------------------------------------------------===//
733 //===----------------------------------------------------------------------===//
736 // ORs of a register.
737 let isCommutable = 1, CCValues = 0xC, CCHasZero = 1 in {
738 defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
739 defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
742 // ORs of a 16-bit immediate, leaving other bits unaffected.
743 // The CC result only reflects the 16-bit field, not the full register.
744 let isCodeGenOnly = 1 in {
745 def OILL32 : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
746 def OILH32 : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
748 def OILL : BinaryRI<"oill", 0xA5B, or, GR64, imm64ll16>;
749 def OILH : BinaryRI<"oilh", 0xA5A, or, GR64, imm64lh16>;
750 def OIHL : BinaryRI<"oihl", 0xA59, or, GR64, imm64hl16>;
751 def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>;
753 // ORs of a 32-bit immediate, leaving other bits unaffected.
754 // The CC result only reflects the 32-bit field, which means we can
755 // use it as a zero indicator for i32 operations but not otherwise.
756 let isCodeGenOnly = 1, CCValues = 0xC, CCHasZero = 1 in
757 def OILF32 : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
758 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR64, imm64lf32>;
759 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>;
762 let CCValues = 0xC, CCHasZero = 1 in {
763 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>;
764 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>;
768 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>;
770 defm : RMWIByte<or, bdaddr12pair, OI>;
771 defm : RMWIByte<or, bdaddr20pair, OIY>;
773 //===----------------------------------------------------------------------===//
775 //===----------------------------------------------------------------------===//
778 // XORs of a register.
779 let isCommutable = 1, CCValues = 0xC, CCHasZero = 1 in {
780 defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
781 defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
784 // XORs of a 32-bit immediate, leaving other bits unaffected.
785 // The CC result only reflects the 32-bit field, which means we can
786 // use it as a zero indicator for i32 operations but not otherwise.
787 let isCodeGenOnly = 1, CCValues = 0xC, CCHasZero = 1 in
788 def XILF32 : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
789 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR64, imm64lf32>;
790 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>;
793 let CCValues = 0xC, CCHasZero = 1 in {
794 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>;
795 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>;
799 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>;
801 defm : RMWIByte<xor, bdaddr12pair, XI>;
802 defm : RMWIByte<xor, bdaddr20pair, XIY>;
804 //===----------------------------------------------------------------------===//
806 //===----------------------------------------------------------------------===//
808 // Multiplication of a register.
809 let isCommutable = 1 in {
810 def MSR : BinaryRRE<"ms", 0xB252, mul, GR32, GR32>;
811 def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
813 def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
814 defm : SXB<mul, GR64, MSGFR>;
816 // Multiplication of a signed 16-bit immediate.
817 def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>;
818 def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
820 // Multiplication of a signed 32-bit immediate.
821 def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>;
822 def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
824 // Multiplication of memory.
825 defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, sextloadi16, 2>;
826 defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
827 def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, sextloadi32, 4>;
828 def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>;
830 // Multiplication of a register, producing two results.
831 def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
833 // Multiplication of memory, producing two results.
834 def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
836 //===----------------------------------------------------------------------===//
837 // Division and remainder
838 //===----------------------------------------------------------------------===//
840 // Division and remainder, from registers.
841 def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
842 def DSGR : BinaryRRE<"dsg", 0xB90D, z_sdivrem64, GR128, GR64>;
843 def DLR : BinaryRRE<"dl", 0xB997, z_udivrem32, GR128, GR32>;
844 def DLGR : BinaryRRE<"dlg", 0xB987, z_udivrem64, GR128, GR64>;
846 // Division and remainder, from memory.
847 def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
848 def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>;
849 def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>;
850 def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>;
852 //===----------------------------------------------------------------------===//
854 //===----------------------------------------------------------------------===//
857 let neverHasSideEffects = 1 in {
858 defm SLL : ShiftRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
859 def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64>;
862 // Logical shift right.
863 let neverHasSideEffects = 1 in {
864 defm SRL : ShiftRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
865 def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64>;
868 // Arithmetic shift right.
869 let Defs = [CC], CCValues = 0xE, CCHasZero = 1, CCHasOrder = 1 in {
870 defm SRA : ShiftRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
871 def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64>;
875 let neverHasSideEffects = 1 in {
876 def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32>;
877 def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64>;
880 // Rotate second operand left and inserted selected bits into first operand.
881 // These can act like 32-bit operands provided that the constant start and
882 // end bits (operands 2 and 3) are in the range [32, 64).
884 let isCodeGenOnly = 1 in
885 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
886 let CCValues = 0xE, CCHasZero = 1, CCHasOrder = 1 in
887 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
890 // Forms of RISBG that only affect one word of the destination register.
891 // They do not set CC.
892 let isCodeGenOnly = 1 in
893 def RISBLG32 : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR32>,
894 Requires<[FeatureHighWord]>;
895 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GR64, GR64>,
896 Requires<[FeatureHighWord]>;
897 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR64, GR64>,
898 Requires<[FeatureHighWord]>;
900 // Rotate second operand left and perform a logical operation with selected
901 // bits of the first operand. The CC result only describes the selected bits,
902 // so isn't useful for a full comparison against zero.
904 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
905 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
906 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
909 //===----------------------------------------------------------------------===//
911 //===----------------------------------------------------------------------===//
913 // Signed comparisons.
914 let Defs = [CC], CCValues = 0xE in {
915 // Comparison with a register.
916 def CR : CompareRR <"c", 0x19, z_cmp, GR32, GR32>;
917 def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
918 def CGR : CompareRRE<"cg", 0xB920, z_cmp, GR64, GR64>;
920 // Comparison with a signed 16-bit immediate.
921 def CHI : CompareRI<"chi", 0xA7E, z_cmp, GR32, imm32sx16>;
922 def CGHI : CompareRI<"cghi", 0xA7F, z_cmp, GR64, imm64sx16>;
924 // Comparison with a signed 32-bit immediate.
925 def CFI : CompareRIL<"cfi", 0xC2D, z_cmp, GR32, simm32>;
926 def CGFI : CompareRIL<"cgfi", 0xC2C, z_cmp, GR64, imm64sx32>;
928 // Comparison with memory.
929 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_cmp, GR32, sextloadi16, 2>;
930 defm C : CompareRXPair<"c", 0x59, 0xE359, z_cmp, GR32, load, 4>;
931 def CGH : CompareRXY<"cgh", 0xE334, z_cmp, GR64, sextloadi16, 2>;
932 def CGF : CompareRXY<"cgf", 0xE330, z_cmp, GR64, sextloadi32, 4>;
933 def CG : CompareRXY<"cg", 0xE320, z_cmp, GR64, load, 8>;
934 def CHRL : CompareRILPC<"chrl", 0xC65, z_cmp, GR32, aligned_sextloadi16>;
935 def CRL : CompareRILPC<"crl", 0xC6D, z_cmp, GR32, aligned_load>;
936 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_cmp, GR64, aligned_sextloadi16>;
937 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_cmp, GR64, aligned_sextloadi32>;
938 def CGRL : CompareRILPC<"cgrl", 0xC68, z_cmp, GR64, aligned_load>;
940 // Comparison between memory and a signed 16-bit immediate.
941 def CHHSI : CompareSIL<"chhsi", 0xE554, z_cmp, sextloadi16, imm32sx16>;
942 def CHSI : CompareSIL<"chsi", 0xE55C, z_cmp, load, imm32sx16>;
943 def CGHSI : CompareSIL<"cghsi", 0xE558, z_cmp, load, imm64sx16>;
945 defm : SXB<z_cmp, GR64, CGFR>;
947 // Unsigned comparisons.
948 let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
949 // Comparison with a register.
950 def CLR : CompareRR <"cl", 0x15, z_ucmp, GR32, GR32>;
951 def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
952 def CLGR : CompareRRE<"clg", 0xB921, z_ucmp, GR64, GR64>;
954 // Comparison with a signed 32-bit immediate.
955 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>;
956 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
958 // Comparison with memory.
959 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
960 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, zextloadi32, 4>;
961 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>;
962 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32,
963 aligned_zextloadi16>;
964 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32,
966 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
967 aligned_zextloadi16>;
968 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
969 aligned_zextloadi32>;
970 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64,
973 // Comparison between memory and an unsigned 8-bit immediate.
974 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, zextloadi8, imm32zx8>;
976 // Comparison between memory and an unsigned 16-bit immediate.
977 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, zextloadi16, imm32zx16>;
978 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
979 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
981 defm : ZXB<z_ucmp, GR64, CLGFR>;
983 //===----------------------------------------------------------------------===//
985 //===----------------------------------------------------------------------===//
987 def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>;
988 def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>;
989 def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>;
991 def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
992 def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
993 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>;
994 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
995 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
996 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>;
997 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
998 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
1000 def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
1001 def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>;
1002 def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>;
1004 def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
1005 def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
1006 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>;
1007 def ATOMIC_LOAD_NILL32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>;
1008 def ATOMIC_LOAD_NILH32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>;
1009 def ATOMIC_LOAD_NILF32 : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
1010 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>;
1011 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>;
1012 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>;
1013 def ATOMIC_LOAD_NIHL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>;
1014 def ATOMIC_LOAD_NIHH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>;
1015 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>;
1016 def ATOMIC_LOAD_NIHF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>;
1018 def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
1019 def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
1020 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>;
1021 def ATOMIC_LOAD_OILL32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
1022 def ATOMIC_LOAD_OILH32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
1023 def ATOMIC_LOAD_OILF32 : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
1024 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>;
1025 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
1026 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
1027 def ATOMIC_LOAD_OIHL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
1028 def ATOMIC_LOAD_OIHH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
1029 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
1030 def ATOMIC_LOAD_OIHF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
1032 def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
1033 def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
1034 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>;
1035 def ATOMIC_LOAD_XILF32 : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
1036 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>;
1037 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
1038 def ATOMIC_LOAD_XIHF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
1040 def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
1041 def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
1043 def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>;
1044 def ATOMIC_LOAD_NILL32i : AtomicLoadBinaryImm32<atomic_load_nand_32,
1046 def ATOMIC_LOAD_NILH32i : AtomicLoadBinaryImm32<atomic_load_nand_32,
1048 def ATOMIC_LOAD_NILF32i : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
1049 def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>;
1050 def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm64<atomic_load_nand_64,
1052 def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm64<atomic_load_nand_64,
1054 def ATOMIC_LOAD_NIHLi : AtomicLoadBinaryImm64<atomic_load_nand_64,
1056 def ATOMIC_LOAD_NIHHi : AtomicLoadBinaryImm64<atomic_load_nand_64,
1058 def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm64<atomic_load_nand_64,
1060 def ATOMIC_LOAD_NIHFi : AtomicLoadBinaryImm64<atomic_load_nand_64,
1063 def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
1064 def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>;
1065 def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>;
1067 def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
1068 def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>;
1069 def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>;
1071 def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
1072 def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
1073 def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
1075 def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
1076 def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
1077 def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
1079 def ATOMIC_CMP_SWAPW
1080 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1081 ADDR32:$bitshift, ADDR32:$negbitshift,
1084 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1085 ADDR32:$bitshift, ADDR32:$negbitshift,
1086 uimm32:$bitsize))]> {
1090 let usesCustomInserter = 1;
1093 let Defs = [CC] in {
1094 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
1095 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
1098 //===----------------------------------------------------------------------===//
1099 // Miscellaneous Instructions.
1100 //===----------------------------------------------------------------------===//
1102 // Read a 32-bit access register into a GR32. As with all GR32 operations,
1103 // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
1104 // when a 64-bit address is stored in a pair of access registers.
1105 def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
1107 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
1109 // Find leftmost one, AKA count leading zeros. The instruction actually
1110 // returns a pair of GR64s, the first giving the number of leading zeros
1111 // and the second giving a copy of the source with the leftmost one bit
1112 // cleared. We only use the first result here.
1113 let Defs = [CC] in {
1114 def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
1116 def : Pat<(ctlz GR64:$src),
1117 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_high)>;
1119 // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
1120 def : Pat<(i64 (anyext GR32:$src)),
1121 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
1123 // There are no 32-bit equivalents of LLILL and LLILH, so use a full
1124 // 64-bit move followed by a subreg. This preserves the invariant that
1125 // all GR32 operations only modify the low 32 bits.
1126 def : Pat<(i32 imm32ll16:$src),
1127 (EXTRACT_SUBREG (LLILL (LL16 imm:$src)), subreg_32bit)>;
1128 def : Pat<(i32 imm32lh16:$src),
1129 (EXTRACT_SUBREG (LLILH (LH16 imm:$src)), subreg_32bit)>;
1131 // Extend GR32s and GR64s to GR128s.
1132 let usesCustomInserter = 1 in {
1133 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1134 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
1135 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1138 //===----------------------------------------------------------------------===//
1140 //===----------------------------------------------------------------------===//
1142 // Use AL* for GR64 additions of unsigned 32-bit values.
1143 defm : ZXB<add, GR64, ALGFR>;
1144 def : Pat<(add GR64:$src1, imm64zx32:$src2),
1145 (ALGFI GR64:$src1, imm64zx32:$src2)>;
1146 def : Pat<(add GR64:$src1, (zextloadi32 bdxaddr20only:$addr)),
1147 (ALGF GR64:$src1, bdxaddr20only:$addr)>;
1149 // Use SL* for GR64 subtractions of unsigned 32-bit values.
1150 defm : ZXB<sub, GR64, SLGFR>;
1151 def : Pat<(add GR64:$src1, imm64zx32n:$src2),
1152 (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1153 def : Pat<(sub GR64:$src1, (zextloadi32 bdxaddr20only:$addr)),
1154 (SLGF GR64:$src1, bdxaddr20only:$addr)>;
1156 // Optimize sign-extended 1/0 selects to -1/0 selects. This is important
1157 // for vector legalization.
1158 def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid, uimm8zx4:$cc)),
1161 (Select32 (LHI -1), (LHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
1162 def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid,
1166 (Select64 (LGHI -1), (LGHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;