1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZInstrInfo.h"
15 #include "SystemZTargetMachine.h"
16 #include "SystemZInstrBuilder.h"
17 #include "llvm/CodeGen/LiveVariables.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #define GET_INSTRINFO_CTOR
21 #define GET_INSTRMAP_INFO
22 #include "SystemZGenInstrInfo.inc"
26 // Return a mask with Count low bits set.
27 static uint64_t allOnes(unsigned int Count) {
28 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
31 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
32 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
36 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
37 // each having the opcode given by NewOpcode.
38 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
39 unsigned NewOpcode) const {
40 MachineBasicBlock *MBB = MI->getParent();
41 MachineFunction &MF = *MBB->getParent();
43 // Get two load or store instructions. Use the original instruction for one
44 // of them (arbitarily the second here) and create a clone for the other.
45 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
46 MBB->insert(MI, EarlierMI);
48 // Set up the two 64-bit registers.
49 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
50 MachineOperand &LowRegOp = MI->getOperand(0);
51 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_high));
52 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_low));
54 // The address in the first (high) instruction is already correct.
55 // Adjust the offset in the second (low) instruction.
56 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
57 MachineOperand &LowOffsetOp = MI->getOperand(2);
58 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
61 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
62 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
63 assert(HighOpcode && LowOpcode && "Both offsets should be in range");
65 EarlierMI->setDesc(get(HighOpcode));
66 MI->setDesc(get(LowOpcode));
69 // Split ADJDYNALLOC instruction MI.
70 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
71 MachineBasicBlock *MBB = MI->getParent();
72 MachineFunction &MF = *MBB->getParent();
73 MachineFrameInfo *MFFrame = MF.getFrameInfo();
74 MachineOperand &OffsetMO = MI->getOperand(2);
76 uint64_t Offset = (MFFrame->getMaxCallFrameSize() +
77 SystemZMC::CallFrameSize +
79 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
80 assert(NewOpcode && "No support for huge argument lists yet");
81 MI->setDesc(get(NewOpcode));
82 OffsetMO.setImm(Offset);
85 // If MI is a simple load or store for a frame object, return the register
86 // it loads or stores and set FrameIndex to the index of the frame object.
87 // Return 0 otherwise.
89 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
90 static int isSimpleMove(const MachineInstr *MI, int &FrameIndex,
92 const MCInstrDesc &MCID = MI->getDesc();
93 if ((MCID.TSFlags & Flag) &&
94 MI->getOperand(1).isFI() &&
95 MI->getOperand(2).getImm() == 0 &&
96 MI->getOperand(3).getReg() == 0) {
97 FrameIndex = MI->getOperand(1).getIndex();
98 return MI->getOperand(0).getReg();
103 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
104 int &FrameIndex) const {
105 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
108 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
109 int &FrameIndex) const {
110 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
113 bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr *MI,
115 int &SrcFrameIndex) const {
116 // Check for MVC 0(Length,FI1),0(FI2)
117 const MachineFrameInfo *MFI = MI->getParent()->getParent()->getFrameInfo();
118 if (MI->getOpcode() != SystemZ::MVC ||
119 !MI->getOperand(0).isFI() ||
120 MI->getOperand(1).getImm() != 0 ||
121 !MI->getOperand(3).isFI() ||
122 MI->getOperand(4).getImm() != 0)
125 // Check that Length covers the full slots.
126 int64_t Length = MI->getOperand(2).getImm();
127 unsigned FI1 = MI->getOperand(0).getIndex();
128 unsigned FI2 = MI->getOperand(3).getIndex();
129 if (MFI->getObjectSize(FI1) != Length ||
130 MFI->getObjectSize(FI2) != Length)
133 DestFrameIndex = FI1;
138 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
139 MachineBasicBlock *&TBB,
140 MachineBasicBlock *&FBB,
141 SmallVectorImpl<MachineOperand> &Cond,
142 bool AllowModify) const {
143 // Most of the code and comments here are boilerplate.
145 // Start from the bottom of the block and work up, examining the
146 // terminator instructions.
147 MachineBasicBlock::iterator I = MBB.end();
148 while (I != MBB.begin()) {
150 if (I->isDebugValue())
153 // Working from the bottom, when we see a non-terminator instruction, we're
155 if (!isUnpredicatedTerminator(I))
158 // A terminator that isn't a branch can't easily be handled by this
163 // Can't handle indirect branches.
164 SystemZII::Branch Branch(getBranchInfo(I));
165 if (!Branch.Target->isMBB())
168 // Punt on compound branches.
169 if (Branch.Type != SystemZII::BranchNormal)
172 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
173 // Handle unconditional branches.
175 TBB = Branch.Target->getMBB();
179 // If the block has any instructions after a JMP, delete them.
180 while (llvm::next(I) != MBB.end())
181 llvm::next(I)->eraseFromParent();
186 // Delete the JMP if it's equivalent to a fall-through.
187 if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
189 I->eraseFromParent();
194 // TBB is used to indicate the unconditinal destination.
195 TBB = Branch.Target->getMBB();
199 // Working from the bottom, handle the first conditional branch.
201 // FIXME: add X86-style branch swap
203 TBB = Branch.Target->getMBB();
204 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
205 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
209 // Handle subsequent conditional branches.
210 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
212 // Only handle the case where all conditional branches branch to the same
214 if (TBB != Branch.Target->getMBB())
217 // If the conditions are the same, we can leave them alone.
218 unsigned OldCCValid = Cond[0].getImm();
219 unsigned OldCCMask = Cond[1].getImm();
220 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
223 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
230 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
231 // Most of the code and comments here are boilerplate.
232 MachineBasicBlock::iterator I = MBB.end();
235 while (I != MBB.begin()) {
237 if (I->isDebugValue())
241 if (!getBranchInfo(I).Target->isMBB())
243 // Remove the branch.
244 I->eraseFromParent();
252 bool SystemZInstrInfo::
253 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
254 assert(Cond.size() == 2 && "Invalid condition");
255 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
260 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
261 MachineBasicBlock *FBB,
262 const SmallVectorImpl<MachineOperand> &Cond,
264 // In this function we output 32-bit branches, which should always
265 // have enough range. They can be shortened and relaxed by later code
266 // in the pipeline, if desired.
268 // Shouldn't be a fall through.
269 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
270 assert((Cond.size() == 2 || Cond.size() == 0) &&
271 "SystemZ branch conditions have one component!");
274 // Unconditional branch?
275 assert(!FBB && "Unconditional branch with multiple successors!");
276 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
280 // Conditional branch.
282 unsigned CCValid = Cond[0].getImm();
283 unsigned CCMask = Cond[1].getImm();
284 BuildMI(&MBB, DL, get(SystemZ::BRC))
285 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
289 // Two-way Conditional branch. Insert the second branch.
290 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
296 bool SystemZInstrInfo::analyzeCompare(const MachineInstr *MI,
297 unsigned &SrcReg, unsigned &SrcReg2,
298 int &Mask, int &Value) const {
299 assert(MI->isCompare() && "Caller should have checked for a comparison");
301 if (MI->getNumExplicitOperands() == 2 &&
302 MI->getOperand(0).isReg() &&
303 MI->getOperand(1).isImm()) {
304 SrcReg = MI->getOperand(0).getReg();
306 Value = MI->getOperand(1).getImm();
314 // If Reg is a virtual register that is used by only a single non-debug
315 // instruction, return the defining instruction, otherwise return null.
316 static MachineInstr *getDefSingleUse(const MachineRegisterInfo *MRI,
318 if (TargetRegisterInfo::isPhysicalRegister(Reg))
321 MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg);
322 MachineRegisterInfo::use_nodbg_iterator E = MRI->use_nodbg_end();
323 if (I == E || llvm::next(I) != E)
326 return MRI->getUniqueVRegDef(Reg);
329 // Return true if MI is a shift of type Opcode by Imm bits.
330 static bool isShift(MachineInstr *MI, int Opcode, int64_t Imm) {
331 return (MI->getOpcode() == Opcode &&
332 !MI->getOperand(2).getReg() &&
333 MI->getOperand(3).getImm() == Imm);
336 // Compare compares SrcReg against zero. Check whether SrcReg contains
337 // the result of an IPM sequence that is only used by Compare. Try to
338 // delete both of them if so and return true if a change was made.
339 static bool removeIPM(MachineInstr *Compare, unsigned SrcReg,
340 const MachineRegisterInfo *MRI,
341 const TargetRegisterInfo *TRI) {
342 MachineInstr *SRA = getDefSingleUse(MRI, SrcReg);
343 if (!SRA || !isShift(SRA, SystemZ::SRA, 30))
346 MachineInstr *SLL = getDefSingleUse(MRI, SRA->getOperand(1).getReg());
347 if (!SLL || !isShift(SLL, SystemZ::SLL, 2))
350 MachineInstr *IPM = getDefSingleUse(MRI, SLL->getOperand(1).getReg());
351 if (!IPM || IPM->getOpcode() != SystemZ::IPM)
354 // Check that there are no assignments to CC between the IPM and Compare,
355 // except for the SRA that we'd like to delete. We can ignore SLL because
356 // it does not assign to CC. We can also ignore uses of the SRA CC result,
357 // since it is effectively restoring CC to the value it had before IPM
358 // (for all current use cases).
359 if (IPM->getParent() != Compare->getParent())
361 MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare;
362 for (++MBBI; MBBI != MBBE; ++MBBI) {
363 MachineInstr *MI = MBBI;
364 if (MI != SRA && MI->modifiesRegister(SystemZ::CC, TRI))
368 IPM->eraseFromParent();
369 SLL->eraseFromParent();
370 SRA->eraseFromParent();
371 Compare->eraseFromParent();
376 SystemZInstrInfo::optimizeCompareInstr(MachineInstr *Compare,
377 unsigned SrcReg, unsigned SrcReg2,
379 const MachineRegisterInfo *MRI) const {
380 assert(!SrcReg2 && "Only optimizing constant comparisons so far");
381 bool IsLogical = (Compare->getDesc().TSFlags & SystemZII::IsLogical) != 0;
384 removeIPM(Compare, SrcReg, MRI, TM.getRegisterInfo()))
389 // If Opcode is a move that has a conditional variant, return that variant,
390 // otherwise return 0.
391 static unsigned getConditionalMove(unsigned Opcode) {
393 case SystemZ::LR: return SystemZ::LOCR;
394 case SystemZ::LGR: return SystemZ::LOCGR;
399 bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const {
400 unsigned Opcode = MI->getOpcode();
401 if (TM.getSubtargetImpl()->hasLoadStoreOnCond() &&
402 getConditionalMove(Opcode))
407 bool SystemZInstrInfo::
408 isProfitableToIfCvt(MachineBasicBlock &MBB,
409 unsigned NumCycles, unsigned ExtraPredCycles,
410 const BranchProbability &Probability) const {
411 // For now only convert single instructions.
412 return NumCycles == 1;
415 bool SystemZInstrInfo::
416 isProfitableToIfCvt(MachineBasicBlock &TMBB,
417 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
418 MachineBasicBlock &FMBB,
419 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
420 const BranchProbability &Probability) const {
421 // For now avoid converting mutually-exclusive cases.
425 bool SystemZInstrInfo::
426 PredicateInstruction(MachineInstr *MI,
427 const SmallVectorImpl<MachineOperand> &Pred) const {
428 assert(Pred.size() == 2 && "Invalid condition");
429 unsigned CCValid = Pred[0].getImm();
430 unsigned CCMask = Pred[1].getImm();
431 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
432 unsigned Opcode = MI->getOpcode();
433 if (TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
434 if (unsigned CondOpcode = getConditionalMove(Opcode)) {
435 MI->setDesc(get(CondOpcode));
436 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
437 .addImm(CCValid).addImm(CCMask)
438 .addReg(SystemZ::CC, RegState::Implicit);;
446 SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
447 MachineBasicBlock::iterator MBBI, DebugLoc DL,
448 unsigned DestReg, unsigned SrcReg,
449 bool KillSrc) const {
450 // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too.
451 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
452 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_high),
453 RI.getSubReg(SrcReg, SystemZ::subreg_high), KillSrc);
454 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_low),
455 RI.getSubReg(SrcReg, SystemZ::subreg_low), KillSrc);
459 // Everything else needs only one instruction.
461 if (SystemZ::GR32BitRegClass.contains(DestReg, SrcReg))
462 Opcode = SystemZ::LR;
463 else if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
464 Opcode = SystemZ::LGR;
465 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
466 Opcode = SystemZ::LER;
467 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
468 Opcode = SystemZ::LDR;
469 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
470 Opcode = SystemZ::LXR;
472 llvm_unreachable("Impossible reg-to-reg copy");
474 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
475 .addReg(SrcReg, getKillRegState(KillSrc));
479 SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
480 MachineBasicBlock::iterator MBBI,
481 unsigned SrcReg, bool isKill,
483 const TargetRegisterClass *RC,
484 const TargetRegisterInfo *TRI) const {
485 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
487 // Callers may expect a single instruction, so keep 128-bit moves
488 // together for now and lower them after register allocation.
489 unsigned LoadOpcode, StoreOpcode;
490 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
491 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
492 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
496 SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
497 MachineBasicBlock::iterator MBBI,
498 unsigned DestReg, int FrameIdx,
499 const TargetRegisterClass *RC,
500 const TargetRegisterInfo *TRI) const {
501 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
503 // Callers may expect a single instruction, so keep 128-bit moves
504 // together for now and lower them after register allocation.
505 unsigned LoadOpcode, StoreOpcode;
506 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
507 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
511 // Return true if MI is a simple load or store with a 12-bit displacement
512 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
513 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
514 const MCInstrDesc &MCID = MI->getDesc();
515 return ((MCID.TSFlags & Flag) &&
516 isUInt<12>(MI->getOperand(2).getImm()) &&
517 MI->getOperand(3).getReg() == 0);
522 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
523 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
524 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
526 operator bool() const { return RegSize; }
528 unsigned RegSize, ImmLSB, ImmSize;
532 static LogicOp interpretAndImmediate(unsigned Opcode) {
534 case SystemZ::NILL32: return LogicOp(32, 0, 16);
535 case SystemZ::NILH32: return LogicOp(32, 16, 16);
536 case SystemZ::NILL: return LogicOp(64, 0, 16);
537 case SystemZ::NILH: return LogicOp(64, 16, 16);
538 case SystemZ::NIHL: return LogicOp(64, 32, 16);
539 case SystemZ::NIHH: return LogicOp(64, 48, 16);
540 case SystemZ::NILF32: return LogicOp(32, 0, 32);
541 case SystemZ::NILF: return LogicOp(64, 0, 32);
542 case SystemZ::NIHF: return LogicOp(64, 32, 32);
543 default: return LogicOp();
547 // Used to return from convertToThreeAddress after replacing two-address
548 // instruction OldMI with three-address instruction NewMI.
549 static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
553 unsigned NumOps = OldMI->getNumOperands();
554 for (unsigned I = 1; I < NumOps; ++I) {
555 MachineOperand &Op = OldMI->getOperand(I);
556 if (Op.isReg() && Op.isKill())
557 LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI);
564 SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
565 MachineBasicBlock::iterator &MBBI,
566 LiveVariables *LV) const {
567 MachineInstr *MI = MBBI;
568 MachineBasicBlock *MBB = MI->getParent();
570 unsigned Opcode = MI->getOpcode();
571 unsigned NumOps = MI->getNumOperands();
573 // Try to convert something like SLL into SLLK, if supported.
574 // We prefer to keep the two-operand form where possible both
575 // because it tends to be shorter and because some instructions
576 // have memory forms that can be used during spilling.
577 if (TM.getSubtargetImpl()->hasDistinctOps()) {
578 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
579 if (ThreeOperandOpcode >= 0) {
580 MachineOperand &Dest = MI->getOperand(0);
581 MachineOperand &Src = MI->getOperand(1);
582 MachineInstrBuilder MIB =
583 BuildMI(*MBB, MBBI, MI->getDebugLoc(), get(ThreeOperandOpcode))
585 // Keep the kill state, but drop the tied flag.
586 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
587 // Keep the remaining operands as-is.
588 for (unsigned I = 2; I < NumOps; ++I)
589 MIB.addOperand(MI->getOperand(I));
590 return finishConvertToThreeAddress(MI, MIB, LV);
594 // Try to convert an AND into an RISBG-type instruction.
595 if (LogicOp And = interpretAndImmediate(Opcode)) {
597 if (And.RegSize == 64)
598 NewOpcode = SystemZ::RISBG;
599 else if (TM.getSubtargetImpl()->hasHighWord())
600 NewOpcode = SystemZ::RISBLG32;
602 // We can't use RISBG for 32-bit operations because it clobbers the
603 // high word of the destination too.
606 uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB;
607 // AND IMMEDIATE leaves the other bits of the register unchanged.
608 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
610 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
611 if (NewOpcode == SystemZ::RISBLG32) {
615 MachineOperand &Dest = MI->getOperand(0);
616 MachineOperand &Src = MI->getOperand(1);
617 MachineInstrBuilder MIB =
618 BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode))
619 .addOperand(Dest).addReg(0)
620 .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
621 .addImm(Start).addImm(End + 128).addImm(0);
622 return finishConvertToThreeAddress(MI, MIB, LV);
630 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
632 const SmallVectorImpl<unsigned> &Ops,
633 int FrameIndex) const {
634 const MachineFrameInfo *MFI = MF.getFrameInfo();
635 unsigned Size = MFI->getObjectSize(FrameIndex);
637 // Eary exit for cases we don't care about
641 unsigned OpNum = Ops[0];
642 assert(Size == MF.getRegInfo()
643 .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
644 "Invalid size combination");
646 unsigned Opcode = MI->getOpcode();
647 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
648 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
649 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
650 // If we're spilling the destination of an LDGR or LGDR, store the
651 // source register instead.
653 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
654 return BuildMI(MF, MI->getDebugLoc(), get(StoreOpcode))
655 .addOperand(MI->getOperand(1)).addFrameIndex(FrameIndex)
656 .addImm(0).addReg(0);
658 // If we're spilling the source of an LDGR or LGDR, load the
659 // destination register instead.
661 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
662 unsigned Dest = MI->getOperand(0).getReg();
663 return BuildMI(MF, MI->getDebugLoc(), get(LoadOpcode), Dest)
664 .addFrameIndex(FrameIndex).addImm(0).addReg(0);
668 // Look for cases where the source of a simple store or the destination
669 // of a simple load is being spilled. Try to use MVC instead.
671 // Although MVC is in practice a fast choice in these cases, it is still
672 // logically a bytewise copy. This means that we cannot use it if the
673 // load or store is volatile. It also means that the transformation is
674 // not valid in cases where the two memories partially overlap; however,
675 // that is not a problem here, because we know that one of the memories
676 // is a full frame index.
677 if (OpNum == 0 && MI->hasOneMemOperand()) {
678 MachineMemOperand *MMO = *MI->memoperands_begin();
679 if (MMO->getSize() == Size && !MMO->isVolatile()) {
680 // Handle conversion of loads.
681 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad)) {
682 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
683 .addFrameIndex(FrameIndex).addImm(0).addImm(Size)
684 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
687 // Handle conversion of stores.
688 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore)) {
689 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
690 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
691 .addImm(Size).addFrameIndex(FrameIndex).addImm(0)
697 // If the spilled operand is the final one, try to change <INSN>R
699 int MemOpcode = SystemZ::getMemOpcode(Opcode);
700 if (MemOpcode >= 0) {
701 unsigned NumOps = MI->getNumExplicitOperands();
702 if (OpNum == NumOps - 1) {
703 const MCInstrDesc &MemDesc = get(MemOpcode);
704 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
705 assert(AccessBytes != 0 && "Size of access should be known");
706 assert(AccessBytes <= Size && "Access outside the frame index");
707 uint64_t Offset = Size - AccessBytes;
708 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(MemOpcode));
709 for (unsigned I = 0; I < OpNum; ++I)
710 MIB.addOperand(MI->getOperand(I));
711 MIB.addFrameIndex(FrameIndex).addImm(Offset);
712 if (MemDesc.TSFlags & SystemZII::HasIndex)
722 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
723 const SmallVectorImpl<unsigned> &Ops,
724 MachineInstr* LoadMI) const {
729 SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
730 switch (MI->getOpcode()) {
732 splitMove(MI, SystemZ::LG);
736 splitMove(MI, SystemZ::STG);
740 splitMove(MI, SystemZ::LD);
744 splitMove(MI, SystemZ::STD);
747 case SystemZ::ADJDYNALLOC:
748 splitAdjDynAlloc(MI);
756 uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
757 if (MI->getOpcode() == TargetOpcode::INLINEASM) {
758 const MachineFunction *MF = MI->getParent()->getParent();
759 const char *AsmStr = MI->getOperand(0).getSymbolName();
760 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
762 return MI->getDesc().getSize();
766 SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const {
767 switch (MI->getOpcode()) {
771 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
772 SystemZ::CCMASK_ANY, &MI->getOperand(0));
776 return SystemZII::Branch(SystemZII::BranchNormal,
777 MI->getOperand(0).getImm(),
778 MI->getOperand(1).getImm(), &MI->getOperand(2));
781 return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
782 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
785 return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
786 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
790 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
791 MI->getOperand(2).getImm(), &MI->getOperand(3));
795 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
796 MI->getOperand(2).getImm(), &MI->getOperand(3));
799 llvm_unreachable("Unrecognized branch opcode");
803 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
804 unsigned &LoadOpcode,
805 unsigned &StoreOpcode) const {
806 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
807 LoadOpcode = SystemZ::L;
808 StoreOpcode = SystemZ::ST32;
809 } else if (RC == &SystemZ::GR64BitRegClass ||
810 RC == &SystemZ::ADDR64BitRegClass) {
811 LoadOpcode = SystemZ::LG;
812 StoreOpcode = SystemZ::STG;
813 } else if (RC == &SystemZ::GR128BitRegClass ||
814 RC == &SystemZ::ADDR128BitRegClass) {
815 LoadOpcode = SystemZ::L128;
816 StoreOpcode = SystemZ::ST128;
817 } else if (RC == &SystemZ::FP32BitRegClass) {
818 LoadOpcode = SystemZ::LE;
819 StoreOpcode = SystemZ::STE;
820 } else if (RC == &SystemZ::FP64BitRegClass) {
821 LoadOpcode = SystemZ::LD;
822 StoreOpcode = SystemZ::STD;
823 } else if (RC == &SystemZ::FP128BitRegClass) {
824 LoadOpcode = SystemZ::LX;
825 StoreOpcode = SystemZ::STX;
827 llvm_unreachable("Unsupported regclass to load or store");
830 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
831 int64_t Offset) const {
832 const MCInstrDesc &MCID = get(Opcode);
833 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
834 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
835 // Get the instruction to use for unsigned 12-bit displacements.
836 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
837 if (Disp12Opcode >= 0)
840 // All address-related instructions can use unsigned 12-bit
844 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
845 // Get the instruction to use for signed 20-bit displacements.
846 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
847 if (Disp20Opcode >= 0)
850 // Check whether Opcode allows signed 20-bit displacements.
851 if (MCID.TSFlags & SystemZII::Has20BitOffset)
857 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
859 case SystemZ::L: return SystemZ::LT;
860 case SystemZ::LY: return SystemZ::LT;
861 case SystemZ::LG: return SystemZ::LTG;
862 case SystemZ::LGF: return SystemZ::LTGF;
863 case SystemZ::LR: return SystemZ::LTR;
864 case SystemZ::LGFR: return SystemZ::LTGFR;
865 case SystemZ::LGR: return SystemZ::LTGR;
866 case SystemZ::LER: return SystemZ::LTEBR;
867 case SystemZ::LDR: return SystemZ::LTDBR;
868 case SystemZ::LXR: return SystemZ::LTXBR;
873 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
874 // have already been filtered out. Store the first set bit in LSB and
875 // the number of set bits in Length if so.
876 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
877 unsigned First = findFirstSet(Mask);
878 uint64_t Top = (Mask >> First) + 1;
879 if ((Top & -Top) == Top) {
881 Length = findFirstSet(Top);
887 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
888 unsigned &Start, unsigned &End) const {
889 // Reject trivial all-zero masks.
893 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
894 // the msb and End specifies the index of the lsb.
895 unsigned LSB, Length;
896 if (isStringOfOnes(Mask, LSB, Length)) {
897 Start = 63 - (LSB + Length - 1);
902 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
903 // of the low 1s and End specifies the lsb of the high 1s.
904 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
905 assert(LSB > 0 && "Bottom bit must be set");
906 assert(LSB + Length < BitSize && "Top bit must be set");
907 Start = 63 - (LSB - 1);
908 End = 63 - (LSB + Length);
915 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
916 const MachineInstr *MI) const {
921 return SystemZ::CGRJ;
923 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
925 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
931 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
932 MachineBasicBlock::iterator MBBI,
933 unsigned Reg, uint64_t Value) const {
934 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
936 if (isInt<16>(Value))
937 Opcode = SystemZ::LGHI;
938 else if (SystemZ::isImmLL(Value))
939 Opcode = SystemZ::LLILL;
940 else if (SystemZ::isImmLH(Value)) {
941 Opcode = SystemZ::LLILH;
944 assert(isInt<32>(Value) && "Huge values not handled yet");
945 Opcode = SystemZ::LGFI;
947 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);