1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
37 // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38 // (The call target is implicitly __tls_get_offset.)
42 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43 // accesses (LARL). Operand 0 is the address.
46 // Used in cases where an offset is applied to a TargetGlobalAddress.
47 // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48 // PCREL_WRAPPER for an anchor point. This is used so that we can
49 // cheaply refer to either the full address or the anchor point
50 // as a register base.
56 // Integer comparisons. There are three operands: the two values
57 // to compare, and an integer of type SystemZICMP.
60 // Floating-point comparisons. The two operands are the values to compare.
63 // Test under mask. The first operand is ANDed with the second operand
64 // and the condition codes are set on the result. The third operand is
65 // a boolean that is true if the condition codes need to distinguish
66 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
67 // register forms do but the memory forms don't).
70 // Branches if a condition is true. Operand 0 is the chain operand;
71 // operand 1 is the 4-bit condition-code mask, with bit N in
72 // big-endian order meaning "branch if CC=N"; operand 2 is the
73 // target block and operand 3 is the flag operand.
76 // Selects between operand 0 and operand 1. Operand 2 is the
77 // mask of condition-code values for which operand 0 should be
78 // chosen over operand 1; it has the same form as BR_CCMASK.
79 // Operand 3 is the flag operand.
82 // Evaluates to the gap between the stack pointer and the
83 // base of the dynamically-allocatable area.
86 // Extracts the value of a 32-bit access register. Operand 0 is
87 // the number of the register.
90 // Count number of bits set in operand 0 per byte.
93 // Wrappers around the ISD opcodes of the same name. The output and
94 // first input operands are GR128s. The trailing numbers are the
95 // widths of the second operand in bits.
102 // Use a series of MVCs to copy bytes from one memory location to another.
104 // - the target address
105 // - the source address
106 // - the constant length
108 // This isn't a memory opcode because we'd need to attach two
109 // MachineMemOperands rather than one.
112 // Like MVC, but implemented as a loop that handles X*256 bytes
113 // followed by straight-line code to handle the rest (if any).
114 // The value of X is passed as an additional operand.
117 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
125 // Use CLC to compare two blocks of memory, with the same comments
126 // as for MVC and MVC_LOOP.
130 // Use an MVST-based sequence to implement stpcpy().
133 // Use a CLST-based sequence to implement strcmp(). The two input operands
134 // are the addresses of the strings to compare.
137 // Use an SRST-based sequence to search a block of memory. The first
138 // operand is the end address, the second is the start, and the third
139 // is the character to search for. CC is set to 1 on success and 2
143 // Store the CC value in bits 29 and 28 of an integer.
146 // Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
149 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
152 // Operand 0: the address of the containing 32-bit-aligned field
153 // Operand 1: the second operand of <op>, in the high bits of an i32
154 // for everything except ATOMIC_SWAPW
155 // Operand 2: how many bits to rotate the i32 left to bring the first
156 // operand into the high bits
157 // Operand 3: the negative of operand 2, for rotating the other way
158 // Operand 4: the width of the field in bits (8 or 16)
159 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
171 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
173 // Operand 0: the address of the containing 32-bit-aligned field
174 // Operand 1: the compare value, in the low bits of an i32
175 // Operand 2: the swap value, in the low bits of an i32
176 // Operand 3: how many bits to rotate the i32 left to bring the first
177 // operand into the high bits
178 // Operand 4: the negative of operand 2, for rotating the other way
179 // Operand 5: the width of the field in bits (8 or 16)
182 // Prefetch from the second operand using the 4-bit control code in
183 // the first operand. The code is 1 for a load prefetch and 2 for
188 // Return true if OPCODE is some kind of PC-relative address.
189 inline bool isPCREL(unsigned Opcode) {
190 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
192 } // end namespace SystemZISD
194 namespace SystemZICMP {
195 // Describes whether an integer comparison needs to be signed or unsigned,
196 // or whether either type is OK.
202 } // end namespace SystemZICMP
204 class SystemZSubtarget;
205 class SystemZTargetMachine;
207 class SystemZTargetLowering : public TargetLowering {
209 explicit SystemZTargetLowering(const TargetMachine &TM,
210 const SystemZSubtarget &STI);
212 // Override TargetLowering.
213 MVT getScalarShiftAmountTy(EVT LHSTy) const override {
216 EVT getSetCCResultType(LLVMContext &, EVT) const override;
217 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
218 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
219 bool isLegalICmpImmediate(int64_t Imm) const override;
220 bool isLegalAddImmediate(int64_t Imm) const override;
221 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
222 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
224 bool *Fast) const override;
225 bool isTruncateFree(Type *, Type *) const override;
226 bool isTruncateFree(EVT, EVT) const override;
227 const char *getTargetNodeName(unsigned Opcode) const override;
228 std::pair<unsigned, const TargetRegisterClass *>
229 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
230 const std::string &Constraint,
231 MVT VT) const override;
232 TargetLowering::ConstraintType
233 getConstraintType(const std::string &Constraint) const override;
234 TargetLowering::ConstraintWeight
235 getSingleConstraintMatchWeight(AsmOperandInfo &info,
236 const char *constraint) const override;
237 void LowerAsmOperandForConstraint(SDValue Op,
238 std::string &Constraint,
239 std::vector<SDValue> &Ops,
240 SelectionDAG &DAG) const override;
242 unsigned getInlineAsmMemConstraint(
243 const std::string &ConstraintCode) const override {
244 if (ConstraintCode.size() == 1) {
245 switch(ConstraintCode[0]) {
249 return InlineAsm::Constraint_Q;
251 return InlineAsm::Constraint_R;
253 return InlineAsm::Constraint_S;
255 return InlineAsm::Constraint_T;
258 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
261 MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
262 MachineBasicBlock *BB) const
264 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
265 bool allowTruncateForTailCall(Type *, Type *) const override;
266 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
267 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
269 const SmallVectorImpl<ISD::InputArg> &Ins,
270 SDLoc DL, SelectionDAG &DAG,
271 SmallVectorImpl<SDValue> &InVals) const override;
272 SDValue LowerCall(CallLoweringInfo &CLI,
273 SmallVectorImpl<SDValue> &InVals) const override;
275 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
276 const SmallVectorImpl<ISD::OutputArg> &Outs,
277 const SmallVectorImpl<SDValue> &OutVals,
278 SDLoc DL, SelectionDAG &DAG) const override;
279 SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
280 SelectionDAG &DAG) const override;
281 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
284 const SystemZSubtarget &Subtarget;
286 // Implement LowerOperation for individual opcodes.
287 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
288 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
289 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
290 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
291 SelectionDAG &DAG) const;
292 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
293 SelectionDAG &DAG, unsigned Opcode,
294 SDValue GOTOffset) const;
295 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
296 SelectionDAG &DAG) const;
297 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
298 SelectionDAG &DAG) const;
299 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
300 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
301 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
302 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
303 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
304 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
305 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
306 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
307 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
308 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
309 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
310 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
311 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
312 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
313 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
314 unsigned Opcode) const;
315 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
316 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
317 SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const;
318 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
319 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
320 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
322 // If the last instruction before MBBI in MBB was some form of COMPARE,
323 // try to replace it with a COMPARE AND BRANCH just before MBBI.
324 // CCMask and Target are the BRC-like operands for the branch.
325 // Return true if the change was made.
326 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
327 MachineBasicBlock::iterator MBBI,
329 MachineBasicBlock *Target) const;
331 // Implement EmitInstrWithCustomInserter for individual operation types.
332 MachineBasicBlock *emitSelect(MachineInstr *MI,
333 MachineBasicBlock *BB) const;
334 MachineBasicBlock *emitCondStore(MachineInstr *MI,
335 MachineBasicBlock *BB,
336 unsigned StoreOpcode, unsigned STOCOpcode,
338 MachineBasicBlock *emitExt128(MachineInstr *MI,
339 MachineBasicBlock *MBB,
340 bool ClearEven, unsigned SubReg) const;
341 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
342 MachineBasicBlock *BB,
343 unsigned BinOpcode, unsigned BitSize,
344 bool Invert = false) const;
345 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
346 MachineBasicBlock *MBB,
347 unsigned CompareOpcode,
348 unsigned KeepOldMask,
349 unsigned BitSize) const;
350 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
351 MachineBasicBlock *BB) const;
352 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
353 MachineBasicBlock *BB,
354 unsigned Opcode) const;
355 MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
356 MachineBasicBlock *BB,
357 unsigned Opcode) const;
359 } // end namespace llvm