1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
37 // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38 // (The call target is implicitly __tls_get_offset.)
42 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43 // accesses (LARL). Operand 0 is the address.
46 // Used in cases where an offset is applied to a TargetGlobalAddress.
47 // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48 // PCREL_WRAPPER for an anchor point. This is used so that we can
49 // cheaply refer to either the full address or the anchor point
50 // as a register base.
56 // Integer comparisons. There are three operands: the two values
57 // to compare, and an integer of type SystemZICMP.
60 // Floating-point comparisons. The two operands are the values to compare.
63 // Test under mask. The first operand is ANDed with the second operand
64 // and the condition codes are set on the result. The third operand is
65 // a boolean that is true if the condition codes need to distinguish
66 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
67 // register forms do but the memory forms don't).
70 // Branches if a condition is true. Operand 0 is the chain operand;
71 // operand 1 is the 4-bit condition-code mask, with bit N in
72 // big-endian order meaning "branch if CC=N"; operand 2 is the
73 // target block and operand 3 is the flag operand.
76 // Selects between operand 0 and operand 1. Operand 2 is the
77 // mask of condition-code values for which operand 0 should be
78 // chosen over operand 1; it has the same form as BR_CCMASK.
79 // Operand 3 is the flag operand.
82 // Evaluates to the gap between the stack pointer and the
83 // base of the dynamically-allocatable area.
86 // Extracts the value of a 32-bit access register. Operand 0 is
87 // the number of the register.
90 // Count number of bits set in operand 0 per byte.
93 // Wrappers around the ISD opcodes of the same name. The output and
94 // first input operands are GR128s. The trailing numbers are the
95 // widths of the second operand in bits.
102 // Use a series of MVCs to copy bytes from one memory location to another.
104 // - the target address
105 // - the source address
106 // - the constant length
108 // This isn't a memory opcode because we'd need to attach two
109 // MachineMemOperands rather than one.
112 // Like MVC, but implemented as a loop that handles X*256 bytes
113 // followed by straight-line code to handle the rest (if any).
114 // The value of X is passed as an additional operand.
117 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
125 // Use CLC to compare two blocks of memory, with the same comments
126 // as for MVC and MVC_LOOP.
130 // Use an MVST-based sequence to implement stpcpy().
133 // Use a CLST-based sequence to implement strcmp(). The two input operands
134 // are the addresses of the strings to compare.
137 // Use an SRST-based sequence to search a block of memory. The first
138 // operand is the end address, the second is the start, and the third
139 // is the character to search for. CC is set to 1 on success and 2
143 // Store the CC value in bits 29 and 28 of an integer.
146 // Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
149 // Transaction begin. The first operand is the chain, the second
150 // the TDB pointer, and the third the immediate control field.
151 // Returns chain and glue.
155 // Transaction end. Just the chain operand. Returns chain and glue.
158 // Create a vector constant by filling byte N of the result with bit
159 // 15-N of the single operand.
162 // Create a vector constant by replicating an element-sized RISBG-style mask.
163 // The first operand specifies the starting set bit and the second operand
164 // specifies the ending set bit. Both operands count from the MSB of the
168 // Replicate a GPR scalar value into all elements of a vector.
171 // Create a vector from two i64 GPRs.
174 // Replicate one element of a vector into all elements. The first operand
175 // is the vector and the second is the index of the element to replicate.
178 // Interleave elements from the high half of operand 0 and the high half
182 // Likewise for the low halves.
185 // Concatenate the vectors in the first two operands, shift them left
186 // by the third operand, and take the first half of the result.
189 // Take one element of the first v2i64 operand and the one element of
190 // the second v2i64 operand and concatenate them to form a v2i64 result.
191 // The third operand is a 4-bit value of the form 0A0B, where A and B
192 // are the element selectors for the first operand and second operands
196 // Perform a general vector permute on vector operands 0 and 1.
197 // Each byte of operand 2 controls the corresponding byte of the result,
198 // in the same way as a byte-level VECTOR_SHUFFLE mask.
201 // Pack vector operands 0 and 1 into a single vector with half-sized elements.
204 // Shift each element of vector operand 0 by the number of bits specified
205 // by scalar operand 1.
210 // For each element of the output type, sum across all sub-elements of
211 // operand 0 belonging to the corresponding element, and add in the
212 // rightmost sub-element of the corresponding element of operand 1.
215 // Compare integer vector operands 0 and 1 to produce the usual 0/-1
216 // vector result. VICMPE is for equality, VICMPH for "signed greater than"
217 // and VICMPHL for "unsigned greater than".
222 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
225 // Operand 0: the address of the containing 32-bit-aligned field
226 // Operand 1: the second operand of <op>, in the high bits of an i32
227 // for everything except ATOMIC_SWAPW
228 // Operand 2: how many bits to rotate the i32 left to bring the first
229 // operand into the high bits
230 // Operand 3: the negative of operand 2, for rotating the other way
231 // Operand 4: the width of the field in bits (8 or 16)
232 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
244 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
246 // Operand 0: the address of the containing 32-bit-aligned field
247 // Operand 1: the compare value, in the low bits of an i32
248 // Operand 2: the swap value, in the low bits of an i32
249 // Operand 3: how many bits to rotate the i32 left to bring the first
250 // operand into the high bits
251 // Operand 4: the negative of operand 2, for rotating the other way
252 // Operand 5: the width of the field in bits (8 or 16)
255 // Prefetch from the second operand using the 4-bit control code in
256 // the first operand. The code is 1 for a load prefetch and 2 for
261 // Return true if OPCODE is some kind of PC-relative address.
262 inline bool isPCREL(unsigned Opcode) {
263 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
265 } // end namespace SystemZISD
267 namespace SystemZICMP {
268 // Describes whether an integer comparison needs to be signed or unsigned,
269 // or whether either type is OK.
275 } // end namespace SystemZICMP
277 class SystemZSubtarget;
278 class SystemZTargetMachine;
280 class SystemZTargetLowering : public TargetLowering {
282 explicit SystemZTargetLowering(const TargetMachine &TM,
283 const SystemZSubtarget &STI);
285 // Override TargetLowering.
286 MVT getScalarShiftAmountTy(EVT LHSTy) const override {
289 MVT getVectorIdxTy() const override {
290 // Only the lower 12 bits of an element index are used, so we don't
291 // want to clobber the upper 32 bits of a GPR unnecessarily.
294 EVT getSetCCResultType(LLVMContext &, EVT) const override;
295 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
296 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
297 bool isLegalICmpImmediate(int64_t Imm) const override;
298 bool isLegalAddImmediate(int64_t Imm) const override;
299 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
300 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
302 bool *Fast) const override;
303 bool isTruncateFree(Type *, Type *) const override;
304 bool isTruncateFree(EVT, EVT) const override;
305 const char *getTargetNodeName(unsigned Opcode) const override;
306 std::pair<unsigned, const TargetRegisterClass *>
307 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
308 const std::string &Constraint,
309 MVT VT) const override;
310 TargetLowering::ConstraintType
311 getConstraintType(const std::string &Constraint) const override;
312 TargetLowering::ConstraintWeight
313 getSingleConstraintMatchWeight(AsmOperandInfo &info,
314 const char *constraint) const override;
315 void LowerAsmOperandForConstraint(SDValue Op,
316 std::string &Constraint,
317 std::vector<SDValue> &Ops,
318 SelectionDAG &DAG) const override;
320 unsigned getInlineAsmMemConstraint(
321 const std::string &ConstraintCode) const override {
322 if (ConstraintCode.size() == 1) {
323 switch(ConstraintCode[0]) {
327 return InlineAsm::Constraint_Q;
329 return InlineAsm::Constraint_R;
331 return InlineAsm::Constraint_S;
333 return InlineAsm::Constraint_T;
336 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
339 MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
340 MachineBasicBlock *BB) const
342 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
343 bool allowTruncateForTailCall(Type *, Type *) const override;
344 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
345 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
347 const SmallVectorImpl<ISD::InputArg> &Ins,
348 SDLoc DL, SelectionDAG &DAG,
349 SmallVectorImpl<SDValue> &InVals) const override;
350 SDValue LowerCall(CallLoweringInfo &CLI,
351 SmallVectorImpl<SDValue> &InVals) const override;
353 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
354 const SmallVectorImpl<ISD::OutputArg> &Outs,
355 const SmallVectorImpl<SDValue> &OutVals,
356 SDLoc DL, SelectionDAG &DAG) const override;
357 SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
358 SelectionDAG &DAG) const override;
359 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
362 const SystemZSubtarget &Subtarget;
364 // Implement LowerOperation for individual opcodes.
365 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
366 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
367 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
368 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
369 SelectionDAG &DAG) const;
370 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
371 SelectionDAG &DAG, unsigned Opcode,
372 SDValue GOTOffset) const;
373 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
374 SelectionDAG &DAG) const;
375 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
376 SelectionDAG &DAG) const;
377 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
378 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
379 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
380 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
381 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
382 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
383 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
384 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
385 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
386 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
387 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
388 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
389 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
390 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
391 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
392 unsigned Opcode) const;
393 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
394 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
395 SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const;
396 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
397 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
398 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
399 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
400 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
401 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
402 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
403 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
405 SDValue combineExtract(SDLoc DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
406 unsigned Index, DAGCombinerInfo &DCI,
408 SDValue combineTruncateExtract(SDLoc DL, EVT TruncVT, SDValue Op,
409 DAGCombinerInfo &DCI) const;
411 // If the last instruction before MBBI in MBB was some form of COMPARE,
412 // try to replace it with a COMPARE AND BRANCH just before MBBI.
413 // CCMask and Target are the BRC-like operands for the branch.
414 // Return true if the change was made.
415 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
416 MachineBasicBlock::iterator MBBI,
418 MachineBasicBlock *Target) const;
420 // Implement EmitInstrWithCustomInserter for individual operation types.
421 MachineBasicBlock *emitSelect(MachineInstr *MI,
422 MachineBasicBlock *BB) const;
423 MachineBasicBlock *emitCondStore(MachineInstr *MI,
424 MachineBasicBlock *BB,
425 unsigned StoreOpcode, unsigned STOCOpcode,
427 MachineBasicBlock *emitExt128(MachineInstr *MI,
428 MachineBasicBlock *MBB,
429 bool ClearEven, unsigned SubReg) const;
430 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
431 MachineBasicBlock *BB,
432 unsigned BinOpcode, unsigned BitSize,
433 bool Invert = false) const;
434 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
435 MachineBasicBlock *MBB,
436 unsigned CompareOpcode,
437 unsigned KeepOldMask,
438 unsigned BitSize) const;
439 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
440 MachineBasicBlock *BB) const;
441 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
442 MachineBasicBlock *BB,
443 unsigned Opcode) const;
444 MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
445 MachineBasicBlock *BB,
446 unsigned Opcode) const;
447 MachineBasicBlock *emitTransactionBegin(MachineInstr *MI,
448 MachineBasicBlock *MBB,
452 } // end namespace llvm