1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
36 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
37 // accesses (LARL). Operand 0 is the address.
40 // Signed integer and floating-point comparisons. The operands are the
41 // two values to compare.
44 // Likewise unsigned integer comparison.
47 // Branches if a condition is true. Operand 0 is the chain operand;
48 // operand 1 is the 4-bit condition-code mask, with bit N in
49 // big-endian order meaning "branch if CC=N"; operand 2 is the
50 // target block and operand 3 is the flag operand.
53 // Selects between operand 0 and operand 1. Operand 2 is the
54 // mask of condition-code values for which operand 0 should be
55 // chosen over operand 1; it has the same form as BR_CCMASK.
56 // Operand 3 is the flag operand.
59 // Evaluates to the gap between the stack pointer and the
60 // base of the dynamically-allocatable area.
63 // Extracts the value of a 32-bit access register. Operand 0 is
64 // the number of the register.
67 // Wrappers around the ISD opcodes of the same name. The output and
68 // first input operands are GR128s. The trailing numbers are the
69 // widths of the second operand in bits.
76 // Use MVC to copy bytes from one memory location to another.
77 // The first operand is the target address, the second operand is the
78 // source address, and the third operand is the constant length.
79 // This isn't a memory opcode because we'd need to attach two
80 // MachineMemOperands rather than one.
83 // Use CLC to compare two blocks of memory, with the same comments
87 // Use an MVST-based sequence to implement stpcpy().
90 // Use a CLST-based sequence to implement strcmp(). The two input operands
91 // are the addresses of the strings to compare.
94 // Store the CC value in bits 29 and 28 of an integer.
97 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
100 // Operand 0: the address of the containing 32-bit-aligned field
101 // Operand 1: the second operand of <op>, in the high bits of an i32
102 // for everything except ATOMIC_SWAPW
103 // Operand 2: how many bits to rotate the i32 left to bring the first
104 // operand into the high bits
105 // Operand 3: the negative of operand 2, for rotating the other way
106 // Operand 4: the width of the field in bits (8 or 16)
107 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
119 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
121 // Operand 0: the address of the containing 32-bit-aligned field
122 // Operand 1: the compare value, in the low bits of an i32
123 // Operand 2: the swap value, in the low bits of an i32
124 // Operand 3: how many bits to rotate the i32 left to bring the first
125 // operand into the high bits
126 // Operand 4: the negative of operand 2, for rotating the other way
127 // Operand 5: the width of the field in bits (8 or 16)
132 class SystemZSubtarget;
133 class SystemZTargetMachine;
135 class SystemZTargetLowering : public TargetLowering {
137 explicit SystemZTargetLowering(SystemZTargetMachine &TM);
139 // Override TargetLowering.
140 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
143 virtual EVT getSetCCResultType(LLVMContext &, EVT) const LLVM_OVERRIDE {
146 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE;
147 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const LLVM_OVERRIDE;
148 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
150 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const
152 virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
153 virtual std::pair<unsigned, const TargetRegisterClass *>
154 getRegForInlineAsmConstraint(const std::string &Constraint,
155 MVT VT) const LLVM_OVERRIDE;
156 virtual TargetLowering::ConstraintType
157 getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
158 virtual TargetLowering::ConstraintWeight
159 getSingleConstraintMatchWeight(AsmOperandInfo &info,
160 const char *constraint) const LLVM_OVERRIDE;
162 LowerAsmOperandForConstraint(SDValue Op,
163 std::string &Constraint,
164 std::vector<SDValue> &Ops,
165 SelectionDAG &DAG) const LLVM_OVERRIDE;
166 virtual MachineBasicBlock *
167 EmitInstrWithCustomInserter(MachineInstr *MI,
168 MachineBasicBlock *BB) const LLVM_OVERRIDE;
169 virtual SDValue LowerOperation(SDValue Op,
170 SelectionDAG &DAG) const LLVM_OVERRIDE;
172 LowerFormalArguments(SDValue Chain,
173 CallingConv::ID CallConv, bool isVarArg,
174 const SmallVectorImpl<ISD::InputArg> &Ins,
175 SDLoc DL, SelectionDAG &DAG,
176 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
178 LowerCall(CallLoweringInfo &CLI,
179 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
182 LowerReturn(SDValue Chain,
183 CallingConv::ID CallConv, bool IsVarArg,
184 const SmallVectorImpl<ISD::OutputArg> &Outs,
185 const SmallVectorImpl<SDValue> &OutVals,
186 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
189 const SystemZSubtarget &Subtarget;
190 const SystemZTargetMachine &TM;
192 // Implement LowerOperation for individual opcodes.
193 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
194 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
195 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
196 SelectionDAG &DAG) const;
197 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
198 SelectionDAG &DAG) const;
199 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
200 SelectionDAG &DAG) const;
201 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
202 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
203 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
204 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
205 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
206 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
207 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
208 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
209 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
210 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
211 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG,
212 unsigned Opcode) const;
213 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
214 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
215 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
217 // If the last instruction before MBBI in MBB was some form of COMPARE,
218 // try to replace it with a COMPARE AND BRANCH just before MBBI.
219 // CCMask and Target are the BRC-like operands for the branch.
220 // Return true if the change was made.
221 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
222 MachineBasicBlock::iterator MBBI,
224 MachineBasicBlock *Target) const;
226 // Implement EmitInstrWithCustomInserter for individual operation types.
227 MachineBasicBlock *emitSelect(MachineInstr *MI,
228 MachineBasicBlock *BB) const;
229 MachineBasicBlock *emitCondStore(MachineInstr *MI,
230 MachineBasicBlock *BB,
231 unsigned StoreOpcode, unsigned STOCOpcode,
233 MachineBasicBlock *emitExt128(MachineInstr *MI,
234 MachineBasicBlock *MBB,
235 bool ClearEven, unsigned SubReg) const;
236 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
237 MachineBasicBlock *BB,
238 unsigned BinOpcode, unsigned BitSize,
239 bool Invert = false) const;
240 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
241 MachineBasicBlock *MBB,
242 unsigned CompareOpcode,
243 unsigned KeepOldMask,
244 unsigned BitSize) const;
245 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
246 MachineBasicBlock *BB) const;
247 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
248 MachineBasicBlock *BB,
249 unsigned Opcode) const;
250 MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
251 MachineBasicBlock *BB,
252 unsigned Opcode) const;
254 } // end namespace llvm
256 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H