1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
36 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
37 // accesses (LARL). Operand 0 is the address.
40 // Signed integer and floating-point comparisons. The operands are the
41 // two values to compare.
44 // Likewise unsigned integer comparison.
47 // Branches if a condition is true. Operand 0 is the chain operand;
48 // operand 1 is the 4-bit condition-code mask, with bit N in
49 // big-endian order meaning "branch if CC=N"; operand 2 is the
50 // target block and operand 3 is the flag operand.
53 // Selects between operand 0 and operand 1. Operand 2 is the
54 // mask of condition-code values for which operand 0 should be
55 // chosen over operand 1; it has the same form as BR_CCMASK.
56 // Operand 3 is the flag operand.
59 // Evaluates to the gap between the stack pointer and the
60 // base of the dynamically-allocatable area.
63 // Extracts the value of a 32-bit access register. Operand 0 is
64 // the number of the register.
67 // Wrappers around the ISD opcodes of the same name. The output and
68 // first input operands are GR128s. The trailing numbers are the
69 // widths of the second operand in bits.
76 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
79 // Operand 0: the address of the containing 32-bit-aligned field
80 // Operand 1: the second operand of <op>, in the high bits of an i32
81 // for everything except ATOMIC_SWAPW
82 // Operand 2: how many bits to rotate the i32 left to bring the first
83 // operand into the high bits
84 // Operand 3: the negative of operand 2, for rotating the other way
85 // Operand 4: the width of the field in bits (8 or 16)
86 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
98 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
100 // Operand 0: the address of the containing 32-bit-aligned field
101 // Operand 1: the compare value, in the low bits of an i32
102 // Operand 2: the swap value, in the low bits of an i32
103 // Operand 3: how many bits to rotate the i32 left to bring the first
104 // operand into the high bits
105 // Operand 4: the negative of operand 2, for rotating the other way
106 // Operand 5: the width of the field in bits (8 or 16)
111 class SystemZSubtarget;
112 class SystemZTargetMachine;
114 class SystemZTargetLowering : public TargetLowering {
116 explicit SystemZTargetLowering(SystemZTargetMachine &TM);
118 // Override TargetLowering.
119 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
122 virtual EVT getSetCCResultType(LLVMContext &, EVT) const {
125 virtual bool isFMAFasterThanMulAndAdd(EVT) const LLVM_OVERRIDE {
128 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
129 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
130 virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
131 virtual std::pair<unsigned, const TargetRegisterClass *>
132 getRegForInlineAsmConstraint(const std::string &Constraint,
133 MVT VT) const LLVM_OVERRIDE;
134 virtual TargetLowering::ConstraintType
135 getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
136 virtual TargetLowering::ConstraintWeight
137 getSingleConstraintMatchWeight(AsmOperandInfo &info,
138 const char *constraint) const LLVM_OVERRIDE;
140 LowerAsmOperandForConstraint(SDValue Op,
141 std::string &Constraint,
142 std::vector<SDValue> &Ops,
143 SelectionDAG &DAG) const LLVM_OVERRIDE;
144 virtual MachineBasicBlock *
145 EmitInstrWithCustomInserter(MachineInstr *MI,
146 MachineBasicBlock *BB) const LLVM_OVERRIDE;
147 virtual SDValue LowerOperation(SDValue Op,
148 SelectionDAG &DAG) const LLVM_OVERRIDE;
150 LowerFormalArguments(SDValue Chain,
151 CallingConv::ID CallConv, bool isVarArg,
152 const SmallVectorImpl<ISD::InputArg> &Ins,
153 SDLoc DL, SelectionDAG &DAG,
154 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
156 LowerCall(CallLoweringInfo &CLI,
157 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
160 LowerReturn(SDValue Chain,
161 CallingConv::ID CallConv, bool IsVarArg,
162 const SmallVectorImpl<ISD::OutputArg> &Outs,
163 const SmallVectorImpl<SDValue> &OutVals,
164 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
167 const SystemZSubtarget &Subtarget;
168 const SystemZTargetMachine &TM;
170 // Implement LowerOperation for individual opcodes.
171 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
172 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
173 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
174 SelectionDAG &DAG) const;
175 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
176 SelectionDAG &DAG) const;
177 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
178 SelectionDAG &DAG) const;
179 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
180 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
181 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
182 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
183 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
184 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
185 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
186 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
187 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
188 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
189 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG,
190 unsigned Opcode) const;
191 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
192 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
193 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
195 // If the last instruction before MBBI in MBB was some form of COMPARE,
196 // try to replace it with a COMPARE AND BRANCH just before MBBI.
197 // CCMask and Target are the BRC-like operands for the branch.
198 // Return true if the change was made.
199 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
200 MachineBasicBlock::iterator MBBI,
202 MachineBasicBlock *Target) const;
204 // Implement EmitInstrWithCustomInserter for individual operation types.
205 MachineBasicBlock *emitSelect(MachineInstr *MI,
206 MachineBasicBlock *BB) const;
207 MachineBasicBlock *emitCondStore(MachineInstr *MI,
208 MachineBasicBlock *BB,
209 unsigned StoreOpcode, bool Invert) const;
210 MachineBasicBlock *emitExt128(MachineInstr *MI,
211 MachineBasicBlock *MBB,
212 bool ClearEven, unsigned SubReg) const;
213 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
214 MachineBasicBlock *BB,
215 unsigned BinOpcode, unsigned BitSize,
216 bool Invert = false) const;
217 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
218 MachineBasicBlock *MBB,
219 unsigned CompareOpcode,
220 unsigned KeepOldMask,
221 unsigned BitSize) const;
222 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
223 MachineBasicBlock *BB) const;
225 } // end namespace llvm
227 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H