1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
37 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
38 // accesses (LARL). Operand 0 is the address.
41 // Integer comparisons. There are three operands: the two values
42 // to compare, and an integer of type SystemZICMP.
45 // Floating-point comparisons. The two operands are the values to compare.
48 // Test under mask. The first operand is ANDed with the second operand
49 // and the condition codes are set on the result. The third operand is
50 // a boolean that is true if the condition codes need to distinguish
51 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
52 // register forms do but the memory forms don't).
55 // Branches if a condition is true. Operand 0 is the chain operand;
56 // operand 1 is the 4-bit condition-code mask, with bit N in
57 // big-endian order meaning "branch if CC=N"; operand 2 is the
58 // target block and operand 3 is the flag operand.
61 // Selects between operand 0 and operand 1. Operand 2 is the
62 // mask of condition-code values for which operand 0 should be
63 // chosen over operand 1; it has the same form as BR_CCMASK.
64 // Operand 3 is the flag operand.
67 // Evaluates to the gap between the stack pointer and the
68 // base of the dynamically-allocatable area.
71 // Extracts the value of a 32-bit access register. Operand 0 is
72 // the number of the register.
75 // Wrappers around the ISD opcodes of the same name. The output and
76 // first input operands are GR128s. The trailing numbers are the
77 // widths of the second operand in bits.
84 // Use a series of MVCs to copy bytes from one memory location to another.
86 // - the target address
87 // - the source address
88 // - the constant length
90 // This isn't a memory opcode because we'd need to attach two
91 // MachineMemOperands rather than one.
94 // Like MVC, but implemented as a loop that handles X*256 bytes
95 // followed by straight-line code to handle the rest (if any).
96 // The value of X is passed as an additional operand.
99 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
107 // Use CLC to compare two blocks of memory, with the same comments
108 // as for MVC and MVC_LOOP.
112 // Use an MVST-based sequence to implement stpcpy().
115 // Use a CLST-based sequence to implement strcmp(). The two input operands
116 // are the addresses of the strings to compare.
119 // Use an SRST-based sequence to search a block of memory. The first
120 // operand is the end address, the second is the start, and the third
121 // is the character to search for. CC is set to 1 on success and 2
125 // Store the CC value in bits 29 and 28 of an integer.
128 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
131 // Operand 0: the address of the containing 32-bit-aligned field
132 // Operand 1: the second operand of <op>, in the high bits of an i32
133 // for everything except ATOMIC_SWAPW
134 // Operand 2: how many bits to rotate the i32 left to bring the first
135 // operand into the high bits
136 // Operand 3: the negative of operand 2, for rotating the other way
137 // Operand 4: the width of the field in bits (8 or 16)
138 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
150 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
152 // Operand 0: the address of the containing 32-bit-aligned field
153 // Operand 1: the compare value, in the low bits of an i32
154 // Operand 2: the swap value, in the low bits of an i32
155 // Operand 3: how many bits to rotate the i32 left to bring the first
156 // operand into the high bits
157 // Operand 4: the negative of operand 2, for rotating the other way
158 // Operand 5: the width of the field in bits (8 or 16)
161 // Prefetch from the second operand using the 4-bit control code in
162 // the first operand. The code is 1 for a load prefetch and 2 for
168 namespace SystemZICMP {
169 // Describes whether an integer comparison needs to be signed or unsigned,
170 // or whether either type is OK.
178 class SystemZSubtarget;
179 class SystemZTargetMachine;
181 class SystemZTargetLowering : public TargetLowering {
183 explicit SystemZTargetLowering(SystemZTargetMachine &TM);
185 // Override TargetLowering.
186 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
189 virtual EVT getSetCCResultType(LLVMContext &, EVT) const LLVM_OVERRIDE {
192 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE;
193 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const LLVM_OVERRIDE;
194 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
196 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const
198 virtual bool isTruncateFree(Type *, Type *) const LLVM_OVERRIDE;
199 virtual bool isTruncateFree(EVT, EVT) const LLVM_OVERRIDE;
200 virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
201 virtual std::pair<unsigned, const TargetRegisterClass *>
202 getRegForInlineAsmConstraint(const std::string &Constraint,
203 MVT VT) const LLVM_OVERRIDE;
204 virtual TargetLowering::ConstraintType
205 getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
206 virtual TargetLowering::ConstraintWeight
207 getSingleConstraintMatchWeight(AsmOperandInfo &info,
208 const char *constraint) const LLVM_OVERRIDE;
210 LowerAsmOperandForConstraint(SDValue Op,
211 std::string &Constraint,
212 std::vector<SDValue> &Ops,
213 SelectionDAG &DAG) const LLVM_OVERRIDE;
214 virtual MachineBasicBlock *
215 EmitInstrWithCustomInserter(MachineInstr *MI,
216 MachineBasicBlock *BB) const LLVM_OVERRIDE;
217 virtual SDValue LowerOperation(SDValue Op,
218 SelectionDAG &DAG) const LLVM_OVERRIDE;
219 virtual bool allowTruncateForTailCall(Type *, Type *) const LLVM_OVERRIDE;
220 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const LLVM_OVERRIDE;
222 LowerFormalArguments(SDValue Chain,
223 CallingConv::ID CallConv, bool isVarArg,
224 const SmallVectorImpl<ISD::InputArg> &Ins,
225 SDLoc DL, SelectionDAG &DAG,
226 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
228 LowerCall(CallLoweringInfo &CLI,
229 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
232 LowerReturn(SDValue Chain,
233 CallingConv::ID CallConv, bool IsVarArg,
234 const SmallVectorImpl<ISD::OutputArg> &Outs,
235 const SmallVectorImpl<SDValue> &OutVals,
236 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
239 const SystemZSubtarget &Subtarget;
240 const SystemZTargetMachine &TM;
242 // Implement LowerOperation for individual opcodes.
243 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
244 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
245 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
246 SelectionDAG &DAG) const;
247 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
248 SelectionDAG &DAG) const;
249 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
250 SelectionDAG &DAG) const;
251 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
252 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
253 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
254 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
255 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
256 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
257 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
258 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
259 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
260 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
261 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
262 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG,
263 unsigned Opcode) const;
264 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
265 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
266 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
267 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
269 // If the last instruction before MBBI in MBB was some form of COMPARE,
270 // try to replace it with a COMPARE AND BRANCH just before MBBI.
271 // CCMask and Target are the BRC-like operands for the branch.
272 // Return true if the change was made.
273 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
274 MachineBasicBlock::iterator MBBI,
276 MachineBasicBlock *Target) const;
278 // Implement EmitInstrWithCustomInserter for individual operation types.
279 MachineBasicBlock *emitSelect(MachineInstr *MI,
280 MachineBasicBlock *BB) const;
281 MachineBasicBlock *emitCondStore(MachineInstr *MI,
282 MachineBasicBlock *BB,
283 unsigned StoreOpcode, unsigned STOCOpcode,
285 MachineBasicBlock *emitExt128(MachineInstr *MI,
286 MachineBasicBlock *MBB,
287 bool ClearEven, unsigned SubReg) const;
288 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
289 MachineBasicBlock *BB,
290 unsigned BinOpcode, unsigned BitSize,
291 bool Invert = false) const;
292 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
293 MachineBasicBlock *MBB,
294 unsigned CompareOpcode,
295 unsigned KeepOldMask,
296 unsigned BitSize) const;
297 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
298 MachineBasicBlock *BB) const;
299 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
300 MachineBasicBlock *BB,
301 unsigned Opcode) const;
302 MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
303 MachineBasicBlock *BB,
304 unsigned Opcode) const;
306 } // end namespace llvm
308 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H