1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
37 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
38 // accesses (LARL). Operand 0 is the address.
41 // Signed integer and floating-point comparisons. The operands are the
42 // two values to compare.
45 // Likewise unsigned integer comparison.
48 // Test under mask. The first operand is ANDed with the second operand
49 // and the condition codes are set on the result.
52 // Branches if a condition is true. Operand 0 is the chain operand;
53 // operand 1 is the 4-bit condition-code mask, with bit N in
54 // big-endian order meaning "branch if CC=N"; operand 2 is the
55 // target block and operand 3 is the flag operand.
58 // Selects between operand 0 and operand 1. Operand 2 is the
59 // mask of condition-code values for which operand 0 should be
60 // chosen over operand 1; it has the same form as BR_CCMASK.
61 // Operand 3 is the flag operand.
64 // Evaluates to the gap between the stack pointer and the
65 // base of the dynamically-allocatable area.
68 // Extracts the value of a 32-bit access register. Operand 0 is
69 // the number of the register.
72 // Wrappers around the ISD opcodes of the same name. The output and
73 // first input operands are GR128s. The trailing numbers are the
74 // widths of the second operand in bits.
81 // Use a series of MVCs to copy bytes from one memory location to another.
83 // - the target address
84 // - the source address
85 // - the constant length
87 // This isn't a memory opcode because we'd need to attach two
88 // MachineMemOperands rather than one.
91 // Like MVC, but implemented as a loop that handles X*256 bytes
92 // followed by straight-line code to handle the rest (if any).
93 // The value of X is passed as an additional operand.
96 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
104 // Use CLC to compare two blocks of memory, with the same comments
105 // as for MVC and MVC_LOOP.
109 // Use an MVST-based sequence to implement stpcpy().
112 // Use a CLST-based sequence to implement strcmp(). The two input operands
113 // are the addresses of the strings to compare.
116 // Use an SRST-based sequence to search a block of memory. The first
117 // operand is the end address, the second is the start, and the third
118 // is the character to search for. CC is set to 1 on success and 2
122 // Store the CC value in bits 29 and 28 of an integer.
125 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
128 // Operand 0: the address of the containing 32-bit-aligned field
129 // Operand 1: the second operand of <op>, in the high bits of an i32
130 // for everything except ATOMIC_SWAPW
131 // Operand 2: how many bits to rotate the i32 left to bring the first
132 // operand into the high bits
133 // Operand 3: the negative of operand 2, for rotating the other way
134 // Operand 4: the width of the field in bits (8 or 16)
135 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
147 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
149 // Operand 0: the address of the containing 32-bit-aligned field
150 // Operand 1: the compare value, in the low bits of an i32
151 // Operand 2: the swap value, in the low bits of an i32
152 // Operand 3: how many bits to rotate the i32 left to bring the first
153 // operand into the high bits
154 // Operand 4: the negative of operand 2, for rotating the other way
155 // Operand 5: the width of the field in bits (8 or 16)
158 // Prefetch from the second operand using the 4-bit control code in
159 // the first operand. The code is 1 for a load prefetch and 2 for
165 class SystemZSubtarget;
166 class SystemZTargetMachine;
168 class SystemZTargetLowering : public TargetLowering {
170 explicit SystemZTargetLowering(SystemZTargetMachine &TM);
172 // Override TargetLowering.
173 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
176 virtual EVT getSetCCResultType(LLVMContext &, EVT) const LLVM_OVERRIDE {
179 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE;
180 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const LLVM_OVERRIDE;
181 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
183 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const
185 virtual bool isTruncateFree(Type *, Type *) const LLVM_OVERRIDE;
186 virtual bool isTruncateFree(EVT, EVT) const LLVM_OVERRIDE;
187 virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
188 virtual std::pair<unsigned, const TargetRegisterClass *>
189 getRegForInlineAsmConstraint(const std::string &Constraint,
190 MVT VT) const LLVM_OVERRIDE;
191 virtual TargetLowering::ConstraintType
192 getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
193 virtual TargetLowering::ConstraintWeight
194 getSingleConstraintMatchWeight(AsmOperandInfo &info,
195 const char *constraint) const LLVM_OVERRIDE;
197 LowerAsmOperandForConstraint(SDValue Op,
198 std::string &Constraint,
199 std::vector<SDValue> &Ops,
200 SelectionDAG &DAG) const LLVM_OVERRIDE;
201 virtual MachineBasicBlock *
202 EmitInstrWithCustomInserter(MachineInstr *MI,
203 MachineBasicBlock *BB) const LLVM_OVERRIDE;
204 virtual SDValue LowerOperation(SDValue Op,
205 SelectionDAG &DAG) const LLVM_OVERRIDE;
206 virtual bool allowTruncateForTailCall(Type *, Type *) const LLVM_OVERRIDE;
207 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const LLVM_OVERRIDE;
209 LowerFormalArguments(SDValue Chain,
210 CallingConv::ID CallConv, bool isVarArg,
211 const SmallVectorImpl<ISD::InputArg> &Ins,
212 SDLoc DL, SelectionDAG &DAG,
213 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
215 LowerCall(CallLoweringInfo &CLI,
216 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
219 LowerReturn(SDValue Chain,
220 CallingConv::ID CallConv, bool IsVarArg,
221 const SmallVectorImpl<ISD::OutputArg> &Outs,
222 const SmallVectorImpl<SDValue> &OutVals,
223 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
226 const SystemZSubtarget &Subtarget;
227 const SystemZTargetMachine &TM;
229 // Implement LowerOperation for individual opcodes.
230 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
231 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
232 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
233 SelectionDAG &DAG) const;
234 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
235 SelectionDAG &DAG) const;
236 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
237 SelectionDAG &DAG) const;
238 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
239 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
240 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
241 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
242 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
243 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
244 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
245 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
246 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
247 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
248 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
249 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG,
250 unsigned Opcode) const;
251 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
252 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
253 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
254 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
256 // If the last instruction before MBBI in MBB was some form of COMPARE,
257 // try to replace it with a COMPARE AND BRANCH just before MBBI.
258 // CCMask and Target are the BRC-like operands for the branch.
259 // Return true if the change was made.
260 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
261 MachineBasicBlock::iterator MBBI,
263 MachineBasicBlock *Target) const;
265 // Implement EmitInstrWithCustomInserter for individual operation types.
266 MachineBasicBlock *emitSelect(MachineInstr *MI,
267 MachineBasicBlock *BB) const;
268 MachineBasicBlock *emitCondStore(MachineInstr *MI,
269 MachineBasicBlock *BB,
270 unsigned StoreOpcode, unsigned STOCOpcode,
272 MachineBasicBlock *emitExt128(MachineInstr *MI,
273 MachineBasicBlock *MBB,
274 bool ClearEven, unsigned SubReg) const;
275 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
276 MachineBasicBlock *BB,
277 unsigned BinOpcode, unsigned BitSize,
278 bool Invert = false) const;
279 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
280 MachineBasicBlock *MBB,
281 unsigned CompareOpcode,
282 unsigned KeepOldMask,
283 unsigned BitSize) const;
284 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
285 MachineBasicBlock *BB) const;
286 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
287 MachineBasicBlock *BB,
288 unsigned Opcode) const;
289 MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
290 MachineBasicBlock *BB,
291 unsigned Opcode) const;
293 } // end namespace llvm
295 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H