1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZISelLowering.h"
15 #include "SystemZCallingConv.h"
16 #include "SystemZConstantPoolValue.h"
17 #include "SystemZMachineFunctionInfo.h"
18 #include "SystemZTargetMachine.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
23 #include "llvm/IR/Intrinsics.h"
28 #define DEBUG_TYPE "systemz-lower"
31 // Represents a sequence for extracting a 0/1 value from an IPM result:
32 // (((X ^ XORValue) + AddValue) >> Bit)
33 struct IPMConversion {
34 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
35 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
42 // Represents information about a comparison.
44 Comparison(SDValue Op0In, SDValue Op1In)
45 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
47 // The operands to the comparison.
50 // The opcode that should be used to compare Op0 and Op1.
53 // A SystemZICMP value. Only used for integer comparisons.
56 // The mask of CC values that Opcode can produce.
59 // The mask of CC values for which the original condition is true.
62 } // end anonymous namespace
64 // Classify VT as either 32 or 64 bit.
65 static bool is32Bit(EVT VT) {
66 switch (VT.getSimpleVT().SimpleTy) {
72 llvm_unreachable("Unsupported type");
76 // Return a version of MachineOperand that can be safely used before the
78 static MachineOperand earlyUseOperand(MachineOperand Op) {
84 SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
85 const SystemZSubtarget &STI)
86 : TargetLowering(TM), Subtarget(STI) {
87 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
89 // Set up the register classes.
90 if (Subtarget.hasHighWord())
91 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
93 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
94 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
95 if (Subtarget.hasVector()) {
96 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
97 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass);
99 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
100 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
102 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
104 if (Subtarget.hasVector()) {
105 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass);
106 addRegisterClass(MVT::v8i16, &SystemZ::VR128BitRegClass);
107 addRegisterClass(MVT::v4i32, &SystemZ::VR128BitRegClass);
108 addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
109 addRegisterClass(MVT::v4f32, &SystemZ::VR128BitRegClass);
110 addRegisterClass(MVT::v2f64, &SystemZ::VR128BitRegClass);
113 // Compute derived properties from the register classes
114 computeRegisterProperties(Subtarget.getRegisterInfo());
116 // Set up special registers.
117 setExceptionPointerRegister(SystemZ::R6D);
118 setExceptionSelectorRegister(SystemZ::R7D);
119 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
121 // TODO: It may be better to default to latency-oriented scheduling, however
122 // LLVM's current latency-oriented scheduler can't handle physreg definitions
123 // such as SystemZ has with CC, so set this to the register-pressure
124 // scheduler, because it can.
125 setSchedulingPreference(Sched::RegPressure);
127 setBooleanContents(ZeroOrOneBooleanContent);
128 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
130 // Instructions are strings of 2-byte aligned 2-byte values.
131 setMinFunctionAlignment(2);
133 // Handle operations that are handled in a similar way for all types.
134 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
135 I <= MVT::LAST_FP_VALUETYPE;
137 MVT VT = MVT::SimpleValueType(I);
138 if (isTypeLegal(VT)) {
139 // Lower SET_CC into an IPM-based sequence.
140 setOperationAction(ISD::SETCC, VT, Custom);
142 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
143 setOperationAction(ISD::SELECT, VT, Expand);
145 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
146 setOperationAction(ISD::SELECT_CC, VT, Custom);
147 setOperationAction(ISD::BR_CC, VT, Custom);
151 // Expand jump table branches as address arithmetic followed by an
153 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
155 // Expand BRCOND into a BR_CC (see above).
156 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
158 // Handle integer types.
159 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
160 I <= MVT::LAST_INTEGER_VALUETYPE;
162 MVT VT = MVT::SimpleValueType(I);
163 if (isTypeLegal(VT)) {
164 // Expand individual DIV and REMs into DIVREMs.
165 setOperationAction(ISD::SDIV, VT, Expand);
166 setOperationAction(ISD::UDIV, VT, Expand);
167 setOperationAction(ISD::SREM, VT, Expand);
168 setOperationAction(ISD::UREM, VT, Expand);
169 setOperationAction(ISD::SDIVREM, VT, Custom);
170 setOperationAction(ISD::UDIVREM, VT, Custom);
172 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
173 // stores, putting a serialization instruction after the stores.
174 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
175 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
177 // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
178 // available, or if the operand is constant.
179 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
181 // Use POPCNT on z196 and above.
182 if (Subtarget.hasPopulationCount())
183 setOperationAction(ISD::CTPOP, VT, Custom);
185 setOperationAction(ISD::CTPOP, VT, Expand);
187 // No special instructions for these.
188 setOperationAction(ISD::CTTZ, VT, Expand);
189 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
190 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
191 setOperationAction(ISD::ROTR, VT, Expand);
193 // Use *MUL_LOHI where possible instead of MULH*.
194 setOperationAction(ISD::MULHS, VT, Expand);
195 setOperationAction(ISD::MULHU, VT, Expand);
196 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
197 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
199 // Only z196 and above have native support for conversions to unsigned.
200 if (!Subtarget.hasFPExtension())
201 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
205 // Type legalization will convert 8- and 16-bit atomic operations into
206 // forms that operate on i32s (but still keeping the original memory VT).
207 // Lower them into full i32 operations.
208 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
209 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
210 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
211 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
212 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
213 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
214 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
215 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
216 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
217 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
218 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
219 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
221 // z10 has instructions for signed but not unsigned FP conversion.
222 // Handle unsigned 32-bit types as signed 64-bit types.
223 if (!Subtarget.hasFPExtension()) {
224 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
225 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
228 // We have native support for a 64-bit CTLZ, via FLOGR.
229 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
230 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
232 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
233 setOperationAction(ISD::OR, MVT::i64, Custom);
235 // FIXME: Can we support these natively?
236 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
237 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
238 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
240 // We have native instructions for i8, i16 and i32 extensions, but not i1.
241 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
242 for (MVT VT : MVT::integer_valuetypes()) {
243 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
244 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
245 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
248 // Handle the various types of symbolic address.
249 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
250 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
251 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
252 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
253 setOperationAction(ISD::JumpTable, PtrVT, Custom);
255 // We need to handle dynamic allocations specially because of the
256 // 160-byte area at the bottom of the stack.
257 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
259 // Use custom expanders so that we can force the function to use
261 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
262 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
264 // Handle prefetches with PFD or PFDRL.
265 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
267 for (MVT VT : MVT::vector_valuetypes()) {
268 // Assume by default that all vector operations need to be expanded.
269 for (unsigned Opcode = 0; Opcode < ISD::BUILTIN_OP_END; ++Opcode)
270 if (getOperationAction(Opcode, VT) == Legal)
271 setOperationAction(Opcode, VT, Expand);
273 // Likewise all truncating stores and extending loads.
274 for (MVT InnerVT : MVT::vector_valuetypes()) {
275 setTruncStoreAction(VT, InnerVT, Expand);
276 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
277 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
278 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
281 if (isTypeLegal(VT)) {
282 // These operations are legal for anything that can be stored in a
283 // vector register, even if there is no native support for the format
284 // as such. In particular, we can do these for v4f32 even though there
285 // are no specific instructions for that format.
286 setOperationAction(ISD::LOAD, VT, Legal);
287 setOperationAction(ISD::STORE, VT, Legal);
288 setOperationAction(ISD::VSELECT, VT, Legal);
289 setOperationAction(ISD::BITCAST, VT, Legal);
290 setOperationAction(ISD::UNDEF, VT, Legal);
292 // Likewise, except that we need to replace the nodes with something
294 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
295 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
299 // Handle integer vector types.
300 for (MVT VT : MVT::integer_vector_valuetypes()) {
301 if (isTypeLegal(VT)) {
302 // These operations have direct equivalents.
303 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal);
304 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal);
305 setOperationAction(ISD::ADD, VT, Legal);
306 setOperationAction(ISD::SUB, VT, Legal);
307 if (VT != MVT::v2i64)
308 setOperationAction(ISD::MUL, VT, Legal);
309 setOperationAction(ISD::AND, VT, Legal);
310 setOperationAction(ISD::OR, VT, Legal);
311 setOperationAction(ISD::XOR, VT, Legal);
312 setOperationAction(ISD::CTPOP, VT, Custom);
313 setOperationAction(ISD::CTTZ, VT, Legal);
314 setOperationAction(ISD::CTLZ, VT, Legal);
315 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Custom);
316 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Custom);
318 // Convert a GPR scalar to a vector by inserting it into element 0.
319 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
321 // Use a series of unpacks for extensions.
322 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
323 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
325 // Detect shifts by a scalar amount and convert them into
327 setOperationAction(ISD::SHL, VT, Custom);
328 setOperationAction(ISD::SRA, VT, Custom);
329 setOperationAction(ISD::SRL, VT, Custom);
331 // At present ROTL isn't matched by DAGCombiner. ROTR should be
332 // converted into ROTL.
333 setOperationAction(ISD::ROTL, VT, Expand);
334 setOperationAction(ISD::ROTR, VT, Expand);
336 // Map SETCCs onto one of VCE, VCH or VCHL, swapping the operands
337 // and inverting the result as necessary.
338 setOperationAction(ISD::SETCC, VT, Custom);
342 if (Subtarget.hasVector()) {
343 // There should be no need to check for float types other than v2f64
344 // since <2 x f32> isn't a legal type.
345 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
346 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
347 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
348 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
351 // Handle floating-point types.
352 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
353 I <= MVT::LAST_FP_VALUETYPE;
355 MVT VT = MVT::SimpleValueType(I);
356 if (isTypeLegal(VT)) {
357 // We can use FI for FRINT.
358 setOperationAction(ISD::FRINT, VT, Legal);
360 // We can use the extended form of FI for other rounding operations.
361 if (Subtarget.hasFPExtension()) {
362 setOperationAction(ISD::FNEARBYINT, VT, Legal);
363 setOperationAction(ISD::FFLOOR, VT, Legal);
364 setOperationAction(ISD::FCEIL, VT, Legal);
365 setOperationAction(ISD::FTRUNC, VT, Legal);
366 setOperationAction(ISD::FROUND, VT, Legal);
369 // No special instructions for these.
370 setOperationAction(ISD::FSIN, VT, Expand);
371 setOperationAction(ISD::FCOS, VT, Expand);
372 setOperationAction(ISD::FREM, VT, Expand);
376 // Handle floating-point vector types.
377 if (Subtarget.hasVector()) {
378 // Scalar-to-vector conversion is just a subreg.
379 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
380 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
382 // Some insertions and extractions can be done directly but others
383 // need to go via integers.
384 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
385 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
386 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
387 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
389 // These operations have direct equivalents.
390 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
391 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
392 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
393 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
394 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
395 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
396 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
397 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
398 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
399 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
400 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
401 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
402 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
403 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
406 // We have fused multiply-addition for f32 and f64 but not f128.
407 setOperationAction(ISD::FMA, MVT::f32, Legal);
408 setOperationAction(ISD::FMA, MVT::f64, Legal);
409 setOperationAction(ISD::FMA, MVT::f128, Expand);
411 // Needed so that we don't try to implement f128 constant loads using
412 // a load-and-extend of a f80 constant (in cases where the constant
413 // would fit in an f80).
414 for (MVT VT : MVT::fp_valuetypes())
415 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
417 // Floating-point truncation and stores need to be done separately.
418 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
419 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
420 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
422 // We have 64-bit FPR<->GPR moves, but need special handling for
424 if (!Subtarget.hasVector()) {
425 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
426 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
429 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
430 // structure, but VAEND is a no-op.
431 setOperationAction(ISD::VASTART, MVT::Other, Custom);
432 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
433 setOperationAction(ISD::VAEND, MVT::Other, Expand);
435 // Codes for which we want to perform some z-specific combinations.
436 setTargetDAGCombine(ISD::SIGN_EXTEND);
437 setTargetDAGCombine(ISD::STORE);
438 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
439 setTargetDAGCombine(ISD::FP_ROUND);
441 // Handle intrinsics.
442 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
443 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
445 // We want to use MVC in preference to even a single load/store pair.
446 MaxStoresPerMemcpy = 0;
447 MaxStoresPerMemcpyOptSize = 0;
449 // The main memset sequence is a byte store followed by an MVC.
450 // Two STC or MV..I stores win over that, but the kind of fused stores
451 // generated by target-independent code don't when the byte value is
452 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
453 // than "STC;MVC". Handle the choice in target-specific code instead.
454 MaxStoresPerMemset = 0;
455 MaxStoresPerMemsetOptSize = 0;
458 EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL,
459 LLVMContext &, EVT VT) const {
462 return VT.changeVectorElementTypeToInteger();
465 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
466 VT = VT.getScalarType();
471 switch (VT.getSimpleVT().SimpleTy) {
484 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
485 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
486 return Imm.isZero() || Imm.isNegZero();
489 bool SystemZTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
490 // We can use CGFI or CLGFI.
491 return isInt<32>(Imm) || isUInt<32>(Imm);
494 bool SystemZTargetLowering::isLegalAddImmediate(int64_t Imm) const {
495 // We can use ALGFI or SLGFI.
496 return isUInt<32>(Imm) || isUInt<32>(-Imm);
499 bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
503 // Unaligned accesses should never be slower than the expanded version.
504 // We check specifically for aligned accesses in the few cases where
505 // they are required.
511 bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL,
512 const AddrMode &AM, Type *Ty,
514 // Punt on globals for now, although they can be used in limited
515 // RELATIVE LONG cases.
519 // Require a 20-bit signed offset.
520 if (!isInt<20>(AM.BaseOffs))
523 // Indexing is OK but no scale factor can be applied.
524 return AM.Scale == 0 || AM.Scale == 1;
527 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
528 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
530 unsigned FromBits = FromType->getPrimitiveSizeInBits();
531 unsigned ToBits = ToType->getPrimitiveSizeInBits();
532 return FromBits > ToBits;
535 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
536 if (!FromVT.isInteger() || !ToVT.isInteger())
538 unsigned FromBits = FromVT.getSizeInBits();
539 unsigned ToBits = ToVT.getSizeInBits();
540 return FromBits > ToBits;
543 //===----------------------------------------------------------------------===//
544 // Inline asm support
545 //===----------------------------------------------------------------------===//
547 TargetLowering::ConstraintType
548 SystemZTargetLowering::getConstraintType(StringRef Constraint) const {
549 if (Constraint.size() == 1) {
550 switch (Constraint[0]) {
551 case 'a': // Address register
552 case 'd': // Data register (equivalent to 'r')
553 case 'f': // Floating-point register
554 case 'h': // High-part register
555 case 'r': // General-purpose register
556 return C_RegisterClass;
558 case 'Q': // Memory with base and unsigned 12-bit displacement
559 case 'R': // Likewise, plus an index
560 case 'S': // Memory with base and signed 20-bit displacement
561 case 'T': // Likewise, plus an index
562 case 'm': // Equivalent to 'T'.
565 case 'I': // Unsigned 8-bit constant
566 case 'J': // Unsigned 12-bit constant
567 case 'K': // Signed 16-bit constant
568 case 'L': // Signed 20-bit displacement (on all targets we support)
569 case 'M': // 0x7fffffff
576 return TargetLowering::getConstraintType(Constraint);
579 TargetLowering::ConstraintWeight SystemZTargetLowering::
580 getSingleConstraintMatchWeight(AsmOperandInfo &info,
581 const char *constraint) const {
582 ConstraintWeight weight = CW_Invalid;
583 Value *CallOperandVal = info.CallOperandVal;
584 // If we don't have a value, we can't do a match,
585 // but allow it at the lowest weight.
588 Type *type = CallOperandVal->getType();
589 // Look at the constraint type.
590 switch (*constraint) {
592 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
595 case 'a': // Address register
596 case 'd': // Data register (equivalent to 'r')
597 case 'h': // High-part register
598 case 'r': // General-purpose register
599 if (CallOperandVal->getType()->isIntegerTy())
600 weight = CW_Register;
603 case 'f': // Floating-point register
604 if (type->isFloatingPointTy())
605 weight = CW_Register;
608 case 'I': // Unsigned 8-bit constant
609 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
610 if (isUInt<8>(C->getZExtValue()))
611 weight = CW_Constant;
614 case 'J': // Unsigned 12-bit constant
615 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
616 if (isUInt<12>(C->getZExtValue()))
617 weight = CW_Constant;
620 case 'K': // Signed 16-bit constant
621 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
622 if (isInt<16>(C->getSExtValue()))
623 weight = CW_Constant;
626 case 'L': // Signed 20-bit displacement (on all targets we support)
627 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
628 if (isInt<20>(C->getSExtValue()))
629 weight = CW_Constant;
632 case 'M': // 0x7fffffff
633 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
634 if (C->getZExtValue() == 0x7fffffff)
635 weight = CW_Constant;
641 // Parse a "{tNNN}" register constraint for which the register type "t"
642 // has already been verified. MC is the class associated with "t" and
643 // Map maps 0-based register numbers to LLVM register numbers.
644 static std::pair<unsigned, const TargetRegisterClass *>
645 parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC,
646 const unsigned *Map) {
647 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
648 if (isdigit(Constraint[2])) {
651 Constraint.slice(2, Constraint.size() - 1).getAsInteger(10, Index);
652 if (!Failed && Index < 16 && Map[Index])
653 return std::make_pair(Map[Index], RC);
655 return std::make_pair(0U, nullptr);
658 std::pair<unsigned, const TargetRegisterClass *>
659 SystemZTargetLowering::getRegForInlineAsmConstraint(
660 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
661 if (Constraint.size() == 1) {
662 // GCC Constraint Letters
663 switch (Constraint[0]) {
665 case 'd': // Data register (equivalent to 'r')
666 case 'r': // General-purpose register
668 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
669 else if (VT == MVT::i128)
670 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
671 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
673 case 'a': // Address register
675 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
676 else if (VT == MVT::i128)
677 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
678 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
680 case 'h': // High-part register (an LLVM extension)
681 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
683 case 'f': // Floating-point register
685 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
686 else if (VT == MVT::f128)
687 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
688 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
691 if (Constraint.size() > 0 && Constraint[0] == '{') {
692 // We need to override the default register parsing for GPRs and FPRs
693 // because the interpretation depends on VT. The internal names of
694 // the registers are also different from the external names
695 // (F0D and F0S instead of F0, etc.).
696 if (Constraint[1] == 'r') {
698 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
699 SystemZMC::GR32Regs);
701 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
702 SystemZMC::GR128Regs);
703 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
704 SystemZMC::GR64Regs);
706 if (Constraint[1] == 'f') {
708 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
709 SystemZMC::FP32Regs);
711 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
712 SystemZMC::FP128Regs);
713 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
714 SystemZMC::FP64Regs);
717 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
720 void SystemZTargetLowering::
721 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
722 std::vector<SDValue> &Ops,
723 SelectionDAG &DAG) const {
724 // Only support length 1 constraints for now.
725 if (Constraint.length() == 1) {
726 switch (Constraint[0]) {
727 case 'I': // Unsigned 8-bit constant
728 if (auto *C = dyn_cast<ConstantSDNode>(Op))
729 if (isUInt<8>(C->getZExtValue()))
730 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
734 case 'J': // Unsigned 12-bit constant
735 if (auto *C = dyn_cast<ConstantSDNode>(Op))
736 if (isUInt<12>(C->getZExtValue()))
737 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
741 case 'K': // Signed 16-bit constant
742 if (auto *C = dyn_cast<ConstantSDNode>(Op))
743 if (isInt<16>(C->getSExtValue()))
744 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
748 case 'L': // Signed 20-bit displacement (on all targets we support)
749 if (auto *C = dyn_cast<ConstantSDNode>(Op))
750 if (isInt<20>(C->getSExtValue()))
751 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
755 case 'M': // 0x7fffffff
756 if (auto *C = dyn_cast<ConstantSDNode>(Op))
757 if (C->getZExtValue() == 0x7fffffff)
758 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
763 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
766 //===----------------------------------------------------------------------===//
767 // Calling conventions
768 //===----------------------------------------------------------------------===//
770 #include "SystemZGenCallingConv.inc"
772 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
773 Type *ToType) const {
774 return isTruncateFree(FromType, ToType);
777 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
778 if (!CI->isTailCall())
783 // We do not yet support 128-bit single-element vector types. If the user
784 // attempts to use such types as function argument or return type, prefer
785 // to error out instead of emitting code violating the ABI.
786 static void VerifyVectorType(MVT VT, EVT ArgVT) {
787 if (ArgVT.isVector() && !VT.isVector())
788 report_fatal_error("Unsupported vector argument or return type");
791 static void VerifyVectorTypes(const SmallVectorImpl<ISD::InputArg> &Ins) {
792 for (unsigned i = 0; i < Ins.size(); ++i)
793 VerifyVectorType(Ins[i].VT, Ins[i].ArgVT);
796 static void VerifyVectorTypes(const SmallVectorImpl<ISD::OutputArg> &Outs) {
797 for (unsigned i = 0; i < Outs.size(); ++i)
798 VerifyVectorType(Outs[i].VT, Outs[i].ArgVT);
801 // Value is a value that has been passed to us in the location described by VA
802 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
803 // any loads onto Chain.
804 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
805 CCValAssign &VA, SDValue Chain,
807 // If the argument has been promoted from a smaller type, insert an
808 // assertion to capture this.
809 if (VA.getLocInfo() == CCValAssign::SExt)
810 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
811 DAG.getValueType(VA.getValVT()));
812 else if (VA.getLocInfo() == CCValAssign::ZExt)
813 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
814 DAG.getValueType(VA.getValVT()));
817 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
818 else if (VA.getLocInfo() == CCValAssign::Indirect)
819 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
820 MachinePointerInfo(), false, false, false, 0);
821 else if (VA.getLocInfo() == CCValAssign::BCvt) {
822 // If this is a short vector argument loaded from the stack,
823 // extend from i64 to full vector size and then bitcast.
824 assert(VA.getLocVT() == MVT::i64);
825 assert(VA.getValVT().isVector());
826 Value = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i64,
827 Value, DAG.getUNDEF(MVT::i64));
828 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value);
830 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
834 // Value is a value of type VA.getValVT() that we need to copy into
835 // the location described by VA. Return a copy of Value converted to
836 // VA.getValVT(). The caller is responsible for handling indirect values.
837 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
838 CCValAssign &VA, SDValue Value) {
839 switch (VA.getLocInfo()) {
840 case CCValAssign::SExt:
841 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
842 case CCValAssign::ZExt:
843 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
844 case CCValAssign::AExt:
845 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
846 case CCValAssign::BCvt:
847 // If this is a short vector argument to be stored to the stack,
848 // bitcast to v2i64 and then extract first element.
849 assert(VA.getLocVT() == MVT::i64);
850 assert(VA.getValVT().isVector());
851 Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value);
852 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value,
853 DAG.getConstant(0, DL, MVT::i32));
854 case CCValAssign::Full:
857 llvm_unreachable("Unhandled getLocInfo()");
861 SDValue SystemZTargetLowering::
862 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
863 const SmallVectorImpl<ISD::InputArg> &Ins,
864 SDLoc DL, SelectionDAG &DAG,
865 SmallVectorImpl<SDValue> &InVals) const {
866 MachineFunction &MF = DAG.getMachineFunction();
867 MachineFrameInfo *MFI = MF.getFrameInfo();
868 MachineRegisterInfo &MRI = MF.getRegInfo();
869 SystemZMachineFunctionInfo *FuncInfo =
870 MF.getInfo<SystemZMachineFunctionInfo>();
872 static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
874 // Detect unsupported vector argument types.
875 if (Subtarget.hasVector())
876 VerifyVectorTypes(Ins);
878 // Assign locations to all of the incoming arguments.
879 SmallVector<CCValAssign, 16> ArgLocs;
880 SystemZCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
881 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
883 unsigned NumFixedGPRs = 0;
884 unsigned NumFixedFPRs = 0;
885 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
887 CCValAssign &VA = ArgLocs[I];
888 EVT LocVT = VA.getLocVT();
890 // Arguments passed in registers
891 const TargetRegisterClass *RC;
892 switch (LocVT.getSimpleVT().SimpleTy) {
894 // Integers smaller than i64 should be promoted to i64.
895 llvm_unreachable("Unexpected argument type");
898 RC = &SystemZ::GR32BitRegClass;
902 RC = &SystemZ::GR64BitRegClass;
906 RC = &SystemZ::FP32BitRegClass;
910 RC = &SystemZ::FP64BitRegClass;
918 RC = &SystemZ::VR128BitRegClass;
922 unsigned VReg = MRI.createVirtualRegister(RC);
923 MRI.addLiveIn(VA.getLocReg(), VReg);
924 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
926 assert(VA.isMemLoc() && "Argument not register or memory");
928 // Create the frame index object for this incoming parameter.
929 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
930 VA.getLocMemOffset(), true);
932 // Create the SelectionDAG nodes corresponding to a load
933 // from this parameter. Unpromoted ints and floats are
934 // passed as right-justified 8-byte values.
935 EVT PtrVT = getPointerTy(DAG.getDataLayout());
936 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
937 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
938 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
939 DAG.getIntPtrConstant(4, DL));
940 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
941 MachinePointerInfo::getFixedStack(MF, FI), false,
945 // Convert the value of the argument register into the value that's
947 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
951 // Save the number of non-varargs registers for later use by va_start, etc.
952 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
953 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
955 // Likewise the address (in the form of a frame index) of where the
956 // first stack vararg would be. The 1-byte size here is arbitrary.
957 int64_t StackSize = CCInfo.getNextStackOffset();
958 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
960 // ...and a similar frame index for the caller-allocated save area
961 // that will be used to store the incoming registers.
962 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
963 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
964 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
966 // Store the FPR varargs in the reserved frame slots. (We store the
967 // GPRs as part of the prologue.)
968 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
969 SDValue MemOps[SystemZ::NumArgFPRs];
970 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
971 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
972 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
973 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
974 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
975 &SystemZ::FP64BitRegClass);
976 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
977 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
978 MachinePointerInfo::getFixedStack(MF, FI),
981 // Join the stores, which are independent of one another.
982 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
983 makeArrayRef(&MemOps[NumFixedFPRs],
984 SystemZ::NumArgFPRs-NumFixedFPRs));
991 static bool canUseSiblingCall(const CCState &ArgCCInfo,
992 SmallVectorImpl<CCValAssign> &ArgLocs) {
993 // Punt if there are any indirect or stack arguments, or if the call
994 // needs the call-saved argument register R6.
995 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
996 CCValAssign &VA = ArgLocs[I];
997 if (VA.getLocInfo() == CCValAssign::Indirect)
1001 unsigned Reg = VA.getLocReg();
1002 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
1009 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
1010 SmallVectorImpl<SDValue> &InVals) const {
1011 SelectionDAG &DAG = CLI.DAG;
1013 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1014 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1015 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1016 SDValue Chain = CLI.Chain;
1017 SDValue Callee = CLI.Callee;
1018 bool &IsTailCall = CLI.IsTailCall;
1019 CallingConv::ID CallConv = CLI.CallConv;
1020 bool IsVarArg = CLI.IsVarArg;
1021 MachineFunction &MF = DAG.getMachineFunction();
1022 EVT PtrVT = getPointerTy(MF.getDataLayout());
1024 // Detect unsupported vector argument and return types.
1025 if (Subtarget.hasVector()) {
1026 VerifyVectorTypes(Outs);
1027 VerifyVectorTypes(Ins);
1030 // Analyze the operands of the call, assigning locations to each operand.
1031 SmallVector<CCValAssign, 16> ArgLocs;
1032 SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1033 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
1035 // We don't support GuaranteedTailCallOpt, only automatically-detected
1037 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
1040 // Get a count of how many bytes are to be pushed on the stack.
1041 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
1043 // Mark the start of the call.
1045 Chain = DAG.getCALLSEQ_START(Chain,
1046 DAG.getConstant(NumBytes, DL, PtrVT, true),
1049 // Copy argument values to their designated locations.
1050 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
1051 SmallVector<SDValue, 8> MemOpChains;
1053 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1054 CCValAssign &VA = ArgLocs[I];
1055 SDValue ArgValue = OutVals[I];
1057 if (VA.getLocInfo() == CCValAssign::Indirect) {
1058 // Store the argument in a stack slot and pass its address.
1059 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1060 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1061 MemOpChains.push_back(DAG.getStore(
1062 Chain, DL, ArgValue, SpillSlot,
1063 MachinePointerInfo::getFixedStack(MF, FI), false, false, 0));
1064 ArgValue = SpillSlot;
1066 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
1069 // Queue up the argument copies and emit them at the end.
1070 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
1072 assert(VA.isMemLoc() && "Argument not register or memory");
1074 // Work out the address of the stack slot. Unpromoted ints and
1075 // floats are passed as right-justified 8-byte values.
1076 if (!StackPtr.getNode())
1077 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
1078 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
1079 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1081 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
1082 DAG.getIntPtrConstant(Offset, DL));
1085 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
1086 MachinePointerInfo(),
1091 // Join the stores, which are independent of one another.
1092 if (!MemOpChains.empty())
1093 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1095 // Accept direct calls by converting symbolic call addresses to the
1096 // associated Target* opcodes. Force %r1 to be used for indirect
1099 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1100 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
1101 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1102 } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1103 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
1104 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1105 } else if (IsTailCall) {
1106 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
1107 Glue = Chain.getValue(1);
1108 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
1111 // Build a sequence of copy-to-reg nodes, chained and glued together.
1112 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
1113 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
1114 RegsToPass[I].second, Glue);
1115 Glue = Chain.getValue(1);
1118 // The first call operand is the chain and the second is the target address.
1119 SmallVector<SDValue, 8> Ops;
1120 Ops.push_back(Chain);
1121 Ops.push_back(Callee);
1123 // Add argument registers to the end of the list so that they are
1124 // known live into the call.
1125 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
1126 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
1127 RegsToPass[I].second.getValueType()));
1129 // Add a register mask operand representing the call-preserved registers.
1130 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1131 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
1132 assert(Mask && "Missing call preserved mask for calling convention");
1133 Ops.push_back(DAG.getRegisterMask(Mask));
1135 // Glue the call to the argument copies, if any.
1137 Ops.push_back(Glue);
1140 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1142 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
1143 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
1144 Glue = Chain.getValue(1);
1146 // Mark the end of the call, which is glued to the call itself.
1147 Chain = DAG.getCALLSEQ_END(Chain,
1148 DAG.getConstant(NumBytes, DL, PtrVT, true),
1149 DAG.getConstant(0, DL, PtrVT, true),
1151 Glue = Chain.getValue(1);
1153 // Assign locations to each value returned by this call.
1154 SmallVector<CCValAssign, 16> RetLocs;
1155 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1156 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
1158 // Copy all of the result registers out of their specified physreg.
1159 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1160 CCValAssign &VA = RetLocs[I];
1162 // Copy the value out, gluing the copy to the end of the call sequence.
1163 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
1164 VA.getLocVT(), Glue);
1165 Chain = RetValue.getValue(1);
1166 Glue = RetValue.getValue(2);
1168 // Convert the value of the return register into the value that's
1170 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
1177 SystemZTargetLowering::LowerReturn(SDValue Chain,
1178 CallingConv::ID CallConv, bool IsVarArg,
1179 const SmallVectorImpl<ISD::OutputArg> &Outs,
1180 const SmallVectorImpl<SDValue> &OutVals,
1181 SDLoc DL, SelectionDAG &DAG) const {
1182 MachineFunction &MF = DAG.getMachineFunction();
1184 // Detect unsupported vector return types.
1185 if (Subtarget.hasVector())
1186 VerifyVectorTypes(Outs);
1188 // Assign locations to each returned value.
1189 SmallVector<CCValAssign, 16> RetLocs;
1190 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1191 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
1193 // Quick exit for void returns
1194 if (RetLocs.empty())
1195 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
1197 // Copy the result values into the output registers.
1199 SmallVector<SDValue, 4> RetOps;
1200 RetOps.push_back(Chain);
1201 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1202 CCValAssign &VA = RetLocs[I];
1203 SDValue RetValue = OutVals[I];
1205 // Make the return register live on exit.
1206 assert(VA.isRegLoc() && "Can only return in registers!");
1208 // Promote the value as required.
1209 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
1211 // Chain and glue the copies together.
1212 unsigned Reg = VA.getLocReg();
1213 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
1214 Glue = Chain.getValue(1);
1215 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
1218 // Update chain and glue.
1221 RetOps.push_back(Glue);
1223 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
1226 SDValue SystemZTargetLowering::
1227 prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const {
1228 return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
1231 // Return true if Op is an intrinsic node with chain that returns the CC value
1232 // as its only (other) argument. Provide the associated SystemZISD opcode and
1233 // the mask of valid CC values if so.
1234 static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
1235 unsigned &CCValid) {
1236 unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1238 case Intrinsic::s390_tbegin:
1239 Opcode = SystemZISD::TBEGIN;
1240 CCValid = SystemZ::CCMASK_TBEGIN;
1243 case Intrinsic::s390_tbegin_nofloat:
1244 Opcode = SystemZISD::TBEGIN_NOFLOAT;
1245 CCValid = SystemZ::CCMASK_TBEGIN;
1248 case Intrinsic::s390_tend:
1249 Opcode = SystemZISD::TEND;
1250 CCValid = SystemZ::CCMASK_TEND;
1258 // Return true if Op is an intrinsic node without chain that returns the
1259 // CC value as its final argument. Provide the associated SystemZISD
1260 // opcode and the mask of valid CC values if so.
1261 static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
1262 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1264 case Intrinsic::s390_vpkshs:
1265 case Intrinsic::s390_vpksfs:
1266 case Intrinsic::s390_vpksgs:
1267 Opcode = SystemZISD::PACKS_CC;
1268 CCValid = SystemZ::CCMASK_VCMP;
1271 case Intrinsic::s390_vpklshs:
1272 case Intrinsic::s390_vpklsfs:
1273 case Intrinsic::s390_vpklsgs:
1274 Opcode = SystemZISD::PACKLS_CC;
1275 CCValid = SystemZ::CCMASK_VCMP;
1278 case Intrinsic::s390_vceqbs:
1279 case Intrinsic::s390_vceqhs:
1280 case Intrinsic::s390_vceqfs:
1281 case Intrinsic::s390_vceqgs:
1282 Opcode = SystemZISD::VICMPES;
1283 CCValid = SystemZ::CCMASK_VCMP;
1286 case Intrinsic::s390_vchbs:
1287 case Intrinsic::s390_vchhs:
1288 case Intrinsic::s390_vchfs:
1289 case Intrinsic::s390_vchgs:
1290 Opcode = SystemZISD::VICMPHS;
1291 CCValid = SystemZ::CCMASK_VCMP;
1294 case Intrinsic::s390_vchlbs:
1295 case Intrinsic::s390_vchlhs:
1296 case Intrinsic::s390_vchlfs:
1297 case Intrinsic::s390_vchlgs:
1298 Opcode = SystemZISD::VICMPHLS;
1299 CCValid = SystemZ::CCMASK_VCMP;
1302 case Intrinsic::s390_vtm:
1303 Opcode = SystemZISD::VTM;
1304 CCValid = SystemZ::CCMASK_VCMP;
1307 case Intrinsic::s390_vfaebs:
1308 case Intrinsic::s390_vfaehs:
1309 case Intrinsic::s390_vfaefs:
1310 Opcode = SystemZISD::VFAE_CC;
1311 CCValid = SystemZ::CCMASK_ANY;
1314 case Intrinsic::s390_vfaezbs:
1315 case Intrinsic::s390_vfaezhs:
1316 case Intrinsic::s390_vfaezfs:
1317 Opcode = SystemZISD::VFAEZ_CC;
1318 CCValid = SystemZ::CCMASK_ANY;
1321 case Intrinsic::s390_vfeebs:
1322 case Intrinsic::s390_vfeehs:
1323 case Intrinsic::s390_vfeefs:
1324 Opcode = SystemZISD::VFEE_CC;
1325 CCValid = SystemZ::CCMASK_ANY;
1328 case Intrinsic::s390_vfeezbs:
1329 case Intrinsic::s390_vfeezhs:
1330 case Intrinsic::s390_vfeezfs:
1331 Opcode = SystemZISD::VFEEZ_CC;
1332 CCValid = SystemZ::CCMASK_ANY;
1335 case Intrinsic::s390_vfenebs:
1336 case Intrinsic::s390_vfenehs:
1337 case Intrinsic::s390_vfenefs:
1338 Opcode = SystemZISD::VFENE_CC;
1339 CCValid = SystemZ::CCMASK_ANY;
1342 case Intrinsic::s390_vfenezbs:
1343 case Intrinsic::s390_vfenezhs:
1344 case Intrinsic::s390_vfenezfs:
1345 Opcode = SystemZISD::VFENEZ_CC;
1346 CCValid = SystemZ::CCMASK_ANY;
1349 case Intrinsic::s390_vistrbs:
1350 case Intrinsic::s390_vistrhs:
1351 case Intrinsic::s390_vistrfs:
1352 Opcode = SystemZISD::VISTR_CC;
1353 CCValid = SystemZ::CCMASK_0 | SystemZ::CCMASK_3;
1356 case Intrinsic::s390_vstrcbs:
1357 case Intrinsic::s390_vstrchs:
1358 case Intrinsic::s390_vstrcfs:
1359 Opcode = SystemZISD::VSTRC_CC;
1360 CCValid = SystemZ::CCMASK_ANY;
1363 case Intrinsic::s390_vstrczbs:
1364 case Intrinsic::s390_vstrczhs:
1365 case Intrinsic::s390_vstrczfs:
1366 Opcode = SystemZISD::VSTRCZ_CC;
1367 CCValid = SystemZ::CCMASK_ANY;
1370 case Intrinsic::s390_vfcedbs:
1371 Opcode = SystemZISD::VFCMPES;
1372 CCValid = SystemZ::CCMASK_VCMP;
1375 case Intrinsic::s390_vfchdbs:
1376 Opcode = SystemZISD::VFCMPHS;
1377 CCValid = SystemZ::CCMASK_VCMP;
1380 case Intrinsic::s390_vfchedbs:
1381 Opcode = SystemZISD::VFCMPHES;
1382 CCValid = SystemZ::CCMASK_VCMP;
1385 case Intrinsic::s390_vftcidb:
1386 Opcode = SystemZISD::VFTCI;
1387 CCValid = SystemZ::CCMASK_VCMP;
1395 // Emit an intrinsic with chain with a glued value instead of its CC result.
1396 static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op,
1398 // Copy all operands except the intrinsic ID.
1399 unsigned NumOps = Op.getNumOperands();
1400 SmallVector<SDValue, 6> Ops;
1401 Ops.reserve(NumOps - 1);
1402 Ops.push_back(Op.getOperand(0));
1403 for (unsigned I = 2; I < NumOps; ++I)
1404 Ops.push_back(Op.getOperand(I));
1406 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
1407 SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1408 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1409 SDValue OldChain = SDValue(Op.getNode(), 1);
1410 SDValue NewChain = SDValue(Intr.getNode(), 0);
1411 DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
1415 // Emit an intrinsic with a glued value instead of its CC result.
1416 static SDValue emitIntrinsicWithGlue(SelectionDAG &DAG, SDValue Op,
1418 // Copy all operands except the intrinsic ID.
1419 unsigned NumOps = Op.getNumOperands();
1420 SmallVector<SDValue, 6> Ops;
1421 Ops.reserve(NumOps - 1);
1422 for (unsigned I = 1; I < NumOps; ++I)
1423 Ops.push_back(Op.getOperand(I));
1425 if (Op->getNumValues() == 1)
1426 return DAG.getNode(Opcode, SDLoc(Op), MVT::Glue, Ops);
1427 assert(Op->getNumValues() == 2 && "Expected exactly one non-CC result");
1428 SDVTList RawVTs = DAG.getVTList(Op->getValueType(0), MVT::Glue);
1429 return DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1432 // CC is a comparison that will be implemented using an integer or
1433 // floating-point comparison. Return the condition code mask for
1434 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
1435 // unsigned comparisons and clear for signed ones. In the floating-point
1436 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
1437 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
1439 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
1440 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
1441 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
1445 llvm_unreachable("Invalid integer condition!");
1454 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
1455 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
1460 // Return a sequence for getting a 1 from an IPM result when CC has a
1461 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
1462 // The handling of CC values outside CCValid doesn't matter.
1463 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
1464 // Deal with cases where the result can be taken directly from a bit
1465 // of the IPM result.
1466 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
1467 return IPMConversion(0, 0, SystemZ::IPM_CC);
1468 if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
1469 return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
1471 // Deal with cases where we can add a value to force the sign bit
1472 // to contain the right value. Putting the bit in 31 means we can
1473 // use SRL rather than RISBG(L), and also makes it easier to get a
1474 // 0/-1 value, so it has priority over the other tests below.
1476 // These sequences rely on the fact that the upper two bits of the
1477 // IPM result are zero.
1478 uint64_t TopBit = uint64_t(1) << 31;
1479 if (CCMask == (CCValid & SystemZ::CCMASK_0))
1480 return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
1481 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
1482 return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
1483 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1485 | SystemZ::CCMASK_2)))
1486 return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
1487 if (CCMask == (CCValid & SystemZ::CCMASK_3))
1488 return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
1489 if (CCMask == (CCValid & (SystemZ::CCMASK_1
1491 | SystemZ::CCMASK_3)))
1492 return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
1494 // Next try inverting the value and testing a bit. 0/1 could be
1495 // handled this way too, but we dealt with that case above.
1496 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
1497 return IPMConversion(-1, 0, SystemZ::IPM_CC);
1499 // Handle cases where adding a value forces a non-sign bit to contain
1501 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
1502 return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
1503 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
1504 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
1506 // The remaining cases are 1, 2, 0/1/3 and 0/2/3. All these are
1507 // can be done by inverting the low CC bit and applying one of the
1508 // sign-based extractions above.
1509 if (CCMask == (CCValid & SystemZ::CCMASK_1))
1510 return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
1511 if (CCMask == (CCValid & SystemZ::CCMASK_2))
1512 return IPMConversion(1 << SystemZ::IPM_CC,
1513 TopBit - (3 << SystemZ::IPM_CC), 31);
1514 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1516 | SystemZ::CCMASK_3)))
1517 return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
1518 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1520 | SystemZ::CCMASK_3)))
1521 return IPMConversion(1 << SystemZ::IPM_CC,
1522 TopBit - (1 << SystemZ::IPM_CC), 31);
1524 llvm_unreachable("Unexpected CC combination");
1527 // If C can be converted to a comparison against zero, adjust the operands
1529 static void adjustZeroCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1530 if (C.ICmpType == SystemZICMP::UnsignedOnly)
1533 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
1537 int64_t Value = ConstOp1->getSExtValue();
1538 if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
1539 (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
1540 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
1541 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
1542 C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1543 C.Op1 = DAG.getConstant(0, DL, C.Op1.getValueType());
1547 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
1548 // adjust the operands as necessary.
1549 static void adjustSubwordCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1550 // For us to make any changes, it must a comparison between a single-use
1551 // load and a constant.
1552 if (!C.Op0.hasOneUse() ||
1553 C.Op0.getOpcode() != ISD::LOAD ||
1554 C.Op1.getOpcode() != ISD::Constant)
1557 // We must have an 8- or 16-bit load.
1558 auto *Load = cast<LoadSDNode>(C.Op0);
1559 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1560 if (NumBits != 8 && NumBits != 16)
1563 // The load must be an extending one and the constant must be within the
1564 // range of the unextended value.
1565 auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
1566 uint64_t Value = ConstOp1->getZExtValue();
1567 uint64_t Mask = (1 << NumBits) - 1;
1568 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1569 // Make sure that ConstOp1 is in range of C.Op0.
1570 int64_t SignedValue = ConstOp1->getSExtValue();
1571 if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
1573 if (C.ICmpType != SystemZICMP::SignedOnly) {
1574 // Unsigned comparison between two sign-extended values is equivalent
1575 // to unsigned comparison between two zero-extended values.
1577 } else if (NumBits == 8) {
1578 // Try to treat the comparison as unsigned, so that we can use CLI.
1579 // Adjust CCMask and Value as necessary.
1580 if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
1581 // Test whether the high bit of the byte is set.
1582 Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
1583 else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
1584 // Test whether the high bit of the byte is clear.
1585 Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
1587 // No instruction exists for this combination.
1589 C.ICmpType = SystemZICMP::UnsignedOnly;
1591 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1594 assert(C.ICmpType == SystemZICMP::Any &&
1595 "Signedness shouldn't matter here.");
1599 // Make sure that the first operand is an i32 of the right extension type.
1600 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
1603 if (C.Op0.getValueType() != MVT::i32 ||
1604 Load->getExtensionType() != ExtType)
1605 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1606 Load->getChain(), Load->getBasePtr(),
1607 Load->getPointerInfo(), Load->getMemoryVT(),
1608 Load->isVolatile(), Load->isNonTemporal(),
1609 Load->isInvariant(), Load->getAlignment());
1611 // Make sure that the second operand is an i32 with the right value.
1612 if (C.Op1.getValueType() != MVT::i32 ||
1613 Value != ConstOp1->getZExtValue())
1614 C.Op1 = DAG.getConstant(Value, DL, MVT::i32);
1617 // Return true if Op is either an unextended load, or a load suitable
1618 // for integer register-memory comparisons of type ICmpType.
1619 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1620 auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
1622 // There are no instructions to compare a register with a memory byte.
1623 if (Load->getMemoryVT() == MVT::i8)
1625 // Otherwise decide on extension type.
1626 switch (Load->getExtensionType()) {
1627 case ISD::NON_EXTLOAD:
1630 return ICmpType != SystemZICMP::UnsignedOnly;
1632 return ICmpType != SystemZICMP::SignedOnly;
1640 // Return true if it is better to swap the operands of C.
1641 static bool shouldSwapCmpOperands(const Comparison &C) {
1642 // Leave f128 comparisons alone, since they have no memory forms.
1643 if (C.Op0.getValueType() == MVT::f128)
1646 // Always keep a floating-point constant second, since comparisons with
1647 // zero can use LOAD TEST and comparisons with other constants make a
1648 // natural memory operand.
1649 if (isa<ConstantFPSDNode>(C.Op1))
1652 // Never swap comparisons with zero since there are many ways to optimize
1654 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1655 if (ConstOp1 && ConstOp1->getZExtValue() == 0)
1658 // Also keep natural memory operands second if the loaded value is
1659 // only used here. Several comparisons have memory forms.
1660 if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
1663 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1664 // In that case we generally prefer the memory to be second.
1665 if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
1666 // The only exceptions are when the second operand is a constant and
1667 // we can use things like CHHSI.
1670 // The unsigned memory-immediate instructions can handle 16-bit
1671 // unsigned integers.
1672 if (C.ICmpType != SystemZICMP::SignedOnly &&
1673 isUInt<16>(ConstOp1->getZExtValue()))
1675 // The signed memory-immediate instructions can handle 16-bit
1677 if (C.ICmpType != SystemZICMP::UnsignedOnly &&
1678 isInt<16>(ConstOp1->getSExtValue()))
1683 // Try to promote the use of CGFR and CLGFR.
1684 unsigned Opcode0 = C.Op0.getOpcode();
1685 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
1687 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
1689 if (C.ICmpType != SystemZICMP::SignedOnly &&
1690 Opcode0 == ISD::AND &&
1691 C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
1692 cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1698 // Return a version of comparison CC mask CCMask in which the LT and GT
1699 // actions are swapped.
1700 static unsigned reverseCCMask(unsigned CCMask) {
1701 return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1702 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1703 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1704 (CCMask & SystemZ::CCMASK_CMP_UO));
1707 // Check whether C tests for equality between X and Y and whether X - Y
1708 // or Y - X is also computed. In that case it's better to compare the
1709 // result of the subtraction against zero.
1710 static void adjustForSubtraction(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1711 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1712 C.CCMask == SystemZ::CCMASK_CMP_NE) {
1713 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1715 if (N->getOpcode() == ISD::SUB &&
1716 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
1717 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
1718 C.Op0 = SDValue(N, 0);
1719 C.Op1 = DAG.getConstant(0, DL, N->getValueType(0));
1726 // Check whether C compares a floating-point value with zero and if that
1727 // floating-point value is also negated. In this case we can use the
1728 // negation to set CC, so avoiding separate LOAD AND TEST and
1729 // LOAD (NEGATIVE/COMPLEMENT) instructions.
1730 static void adjustForFNeg(Comparison &C) {
1731 auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
1732 if (C1 && C1->isZero()) {
1733 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1735 if (N->getOpcode() == ISD::FNEG) {
1736 C.Op0 = SDValue(N, 0);
1737 C.CCMask = reverseCCMask(C.CCMask);
1744 // Check whether C compares (shl X, 32) with 0 and whether X is
1745 // also sign-extended. In that case it is better to test the result
1746 // of the sign extension using LTGFR.
1748 // This case is important because InstCombine transforms a comparison
1749 // with (sext (trunc X)) into a comparison with (shl X, 32).
1750 static void adjustForLTGFR(Comparison &C) {
1751 // Check for a comparison between (shl X, 32) and 0.
1752 if (C.Op0.getOpcode() == ISD::SHL &&
1753 C.Op0.getValueType() == MVT::i64 &&
1754 C.Op1.getOpcode() == ISD::Constant &&
1755 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1756 auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
1757 if (C1 && C1->getZExtValue() == 32) {
1758 SDValue ShlOp0 = C.Op0.getOperand(0);
1759 // See whether X has any SIGN_EXTEND_INREG uses.
1760 for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
1762 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
1763 cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
1764 C.Op0 = SDValue(N, 0);
1772 // If C compares the truncation of an extending load, try to compare
1773 // the untruncated value instead. This exposes more opportunities to
1775 static void adjustICmpTruncate(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1776 if (C.Op0.getOpcode() == ISD::TRUNCATE &&
1777 C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
1778 C.Op1.getOpcode() == ISD::Constant &&
1779 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1780 auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
1781 if (L->getMemoryVT().getStoreSizeInBits()
1782 <= C.Op0.getValueType().getSizeInBits()) {
1783 unsigned Type = L->getExtensionType();
1784 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
1785 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
1786 C.Op0 = C.Op0.getOperand(0);
1787 C.Op1 = DAG.getConstant(0, DL, C.Op0.getValueType());
1793 // Return true if shift operation N has an in-range constant shift value.
1794 // Store it in ShiftVal if so.
1795 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
1796 auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
1800 uint64_t Amount = Shift->getZExtValue();
1801 if (Amount >= N.getValueType().getSizeInBits())
1808 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
1809 // instruction and whether the CC value is descriptive enough to handle
1810 // a comparison of type Opcode between the AND result and CmpVal.
1811 // CCMask says which comparison result is being tested and BitSize is
1812 // the number of bits in the operands. If TEST UNDER MASK can be used,
1813 // return the corresponding CC mask, otherwise return 0.
1814 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
1815 uint64_t Mask, uint64_t CmpVal,
1816 unsigned ICmpType) {
1817 assert(Mask != 0 && "ANDs with zero should have been removed by now");
1819 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
1820 if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
1821 !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
1824 // Work out the masks for the lowest and highest bits.
1825 unsigned HighShift = 63 - countLeadingZeros(Mask);
1826 uint64_t High = uint64_t(1) << HighShift;
1827 uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
1829 // Signed ordered comparisons are effectively unsigned if the sign
1831 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
1833 // Check for equality comparisons with 0, or the equivalent.
1835 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1836 return SystemZ::CCMASK_TM_ALL_0;
1837 if (CCMask == SystemZ::CCMASK_CMP_NE)
1838 return SystemZ::CCMASK_TM_SOME_1;
1840 if (EffectivelyUnsigned && CmpVal <= Low) {
1841 if (CCMask == SystemZ::CCMASK_CMP_LT)
1842 return SystemZ::CCMASK_TM_ALL_0;
1843 if (CCMask == SystemZ::CCMASK_CMP_GE)
1844 return SystemZ::CCMASK_TM_SOME_1;
1846 if (EffectivelyUnsigned && CmpVal < Low) {
1847 if (CCMask == SystemZ::CCMASK_CMP_LE)
1848 return SystemZ::CCMASK_TM_ALL_0;
1849 if (CCMask == SystemZ::CCMASK_CMP_GT)
1850 return SystemZ::CCMASK_TM_SOME_1;
1853 // Check for equality comparisons with the mask, or the equivalent.
1854 if (CmpVal == Mask) {
1855 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1856 return SystemZ::CCMASK_TM_ALL_1;
1857 if (CCMask == SystemZ::CCMASK_CMP_NE)
1858 return SystemZ::CCMASK_TM_SOME_0;
1860 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
1861 if (CCMask == SystemZ::CCMASK_CMP_GT)
1862 return SystemZ::CCMASK_TM_ALL_1;
1863 if (CCMask == SystemZ::CCMASK_CMP_LE)
1864 return SystemZ::CCMASK_TM_SOME_0;
1866 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
1867 if (CCMask == SystemZ::CCMASK_CMP_GE)
1868 return SystemZ::CCMASK_TM_ALL_1;
1869 if (CCMask == SystemZ::CCMASK_CMP_LT)
1870 return SystemZ::CCMASK_TM_SOME_0;
1873 // Check for ordered comparisons with the top bit.
1874 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
1875 if (CCMask == SystemZ::CCMASK_CMP_LE)
1876 return SystemZ::CCMASK_TM_MSB_0;
1877 if (CCMask == SystemZ::CCMASK_CMP_GT)
1878 return SystemZ::CCMASK_TM_MSB_1;
1880 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
1881 if (CCMask == SystemZ::CCMASK_CMP_LT)
1882 return SystemZ::CCMASK_TM_MSB_0;
1883 if (CCMask == SystemZ::CCMASK_CMP_GE)
1884 return SystemZ::CCMASK_TM_MSB_1;
1887 // If there are just two bits, we can do equality checks for Low and High
1889 if (Mask == Low + High) {
1890 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
1891 return SystemZ::CCMASK_TM_MIXED_MSB_0;
1892 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
1893 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
1894 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
1895 return SystemZ::CCMASK_TM_MIXED_MSB_1;
1896 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
1897 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
1900 // Looks like we've exhausted our options.
1904 // See whether C can be implemented as a TEST UNDER MASK instruction.
1905 // Update the arguments with the TM version if so.
1906 static void adjustForTestUnderMask(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1907 // Check that we have a comparison with a constant.
1908 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1911 uint64_t CmpVal = ConstOp1->getZExtValue();
1913 // Check whether the nonconstant input is an AND with a constant mask.
1916 ConstantSDNode *Mask = nullptr;
1917 if (C.Op0.getOpcode() == ISD::AND) {
1918 NewC.Op0 = C.Op0.getOperand(0);
1919 NewC.Op1 = C.Op0.getOperand(1);
1920 Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
1923 MaskVal = Mask->getZExtValue();
1925 // There is no instruction to compare with a 64-bit immediate
1926 // so use TMHH instead if possible. We need an unsigned ordered
1927 // comparison with an i64 immediate.
1928 if (NewC.Op0.getValueType() != MVT::i64 ||
1929 NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
1930 NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
1931 NewC.ICmpType == SystemZICMP::SignedOnly)
1933 // Convert LE and GT comparisons into LT and GE.
1934 if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
1935 NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
1936 if (CmpVal == uint64_t(-1))
1939 NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1941 // If the low N bits of Op1 are zero than the low N bits of Op0 can
1942 // be masked off without changing the result.
1943 MaskVal = -(CmpVal & -CmpVal);
1944 NewC.ICmpType = SystemZICMP::UnsignedOnly;
1949 // Check whether the combination of mask, comparison value and comparison
1950 // type are suitable.
1951 unsigned BitSize = NewC.Op0.getValueType().getSizeInBits();
1952 unsigned NewCCMask, ShiftVal;
1953 if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1954 NewC.Op0.getOpcode() == ISD::SHL &&
1955 isSimpleShift(NewC.Op0, ShiftVal) &&
1956 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1957 MaskVal >> ShiftVal,
1959 SystemZICMP::Any))) {
1960 NewC.Op0 = NewC.Op0.getOperand(0);
1961 MaskVal >>= ShiftVal;
1962 } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1963 NewC.Op0.getOpcode() == ISD::SRL &&
1964 isSimpleShift(NewC.Op0, ShiftVal) &&
1965 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1966 MaskVal << ShiftVal,
1968 SystemZICMP::UnsignedOnly))) {
1969 NewC.Op0 = NewC.Op0.getOperand(0);
1970 MaskVal <<= ShiftVal;
1972 NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
1978 // Go ahead and make the change.
1979 C.Opcode = SystemZISD::TM;
1981 if (Mask && Mask->getZExtValue() == MaskVal)
1982 C.Op1 = SDValue(Mask, 0);
1984 C.Op1 = DAG.getConstant(MaskVal, DL, C.Op0.getValueType());
1985 C.CCValid = SystemZ::CCMASK_TM;
1986 C.CCMask = NewCCMask;
1989 // Return a Comparison that tests the condition-code result of intrinsic
1990 // node Call against constant integer CC using comparison code Cond.
1991 // Opcode is the opcode of the SystemZISD operation for the intrinsic
1992 // and CCValid is the set of possible condition-code results.
1993 static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
1994 SDValue Call, unsigned CCValid, uint64_t CC,
1995 ISD::CondCode Cond) {
1996 Comparison C(Call, SDValue());
1998 C.CCValid = CCValid;
1999 if (Cond == ISD::SETEQ)
2000 // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
2001 C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
2002 else if (Cond == ISD::SETNE)
2003 // ...and the inverse of that.
2004 C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
2005 else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
2006 // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
2007 // always true for CC>3.
2008 C.CCMask = CC < 4 ? ~0U << (4 - CC) : -1;
2009 else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
2010 // ...and the inverse of that.
2011 C.CCMask = CC < 4 ? ~(~0U << (4 - CC)) : 0;
2012 else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
2013 // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
2014 // always true for CC>3.
2015 C.CCMask = CC < 4 ? ~0U << (3 - CC) : -1;
2016 else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
2017 // ...and the inverse of that.
2018 C.CCMask = CC < 4 ? ~(~0U << (3 - CC)) : 0;
2020 llvm_unreachable("Unexpected integer comparison type");
2021 C.CCMask &= CCValid;
2025 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
2026 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
2027 ISD::CondCode Cond, SDLoc DL) {
2028 if (CmpOp1.getOpcode() == ISD::Constant) {
2029 uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
2030 unsigned Opcode, CCValid;
2031 if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
2032 CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
2033 isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
2034 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2035 if (CmpOp0.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2036 CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 &&
2037 isIntrinsicWithCC(CmpOp0, Opcode, CCValid))
2038 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2040 Comparison C(CmpOp0, CmpOp1);
2041 C.CCMask = CCMaskForCondCode(Cond);
2042 if (C.Op0.getValueType().isFloatingPoint()) {
2043 C.CCValid = SystemZ::CCMASK_FCMP;
2044 C.Opcode = SystemZISD::FCMP;
2047 C.CCValid = SystemZ::CCMASK_ICMP;
2048 C.Opcode = SystemZISD::ICMP;
2049 // Choose the type of comparison. Equality and inequality tests can
2050 // use either signed or unsigned comparisons. The choice also doesn't
2051 // matter if both sign bits are known to be clear. In those cases we
2052 // want to give the main isel code the freedom to choose whichever
2054 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
2055 C.CCMask == SystemZ::CCMASK_CMP_NE ||
2056 (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
2057 C.ICmpType = SystemZICMP::Any;
2058 else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
2059 C.ICmpType = SystemZICMP::UnsignedOnly;
2061 C.ICmpType = SystemZICMP::SignedOnly;
2062 C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
2063 adjustZeroCmp(DAG, DL, C);
2064 adjustSubwordCmp(DAG, DL, C);
2065 adjustForSubtraction(DAG, DL, C);
2067 adjustICmpTruncate(DAG, DL, C);
2070 if (shouldSwapCmpOperands(C)) {
2071 std::swap(C.Op0, C.Op1);
2072 C.CCMask = reverseCCMask(C.CCMask);
2075 adjustForTestUnderMask(DAG, DL, C);
2079 // Emit the comparison instruction described by C.
2080 static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
2081 if (!C.Op1.getNode()) {
2083 switch (C.Op0.getOpcode()) {
2084 case ISD::INTRINSIC_W_CHAIN:
2085 Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
2087 case ISD::INTRINSIC_WO_CHAIN:
2088 Op = emitIntrinsicWithGlue(DAG, C.Op0, C.Opcode);
2091 llvm_unreachable("Invalid comparison operands");
2093 return SDValue(Op.getNode(), Op->getNumValues() - 1);
2095 if (C.Opcode == SystemZISD::ICMP)
2096 return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
2097 DAG.getConstant(C.ICmpType, DL, MVT::i32));
2098 if (C.Opcode == SystemZISD::TM) {
2099 bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
2100 bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
2101 return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
2102 DAG.getConstant(RegisterOnly, DL, MVT::i32));
2104 return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
2107 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
2108 // 64 bits. Extend is the extension type to use. Store the high part
2109 // in Hi and the low part in Lo.
2110 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
2111 unsigned Extend, SDValue Op0, SDValue Op1,
2112 SDValue &Hi, SDValue &Lo) {
2113 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
2114 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
2115 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
2116 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
2117 DAG.getConstant(32, DL, MVT::i64));
2118 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
2119 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
2122 // Lower a binary operation that produces two VT results, one in each
2123 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
2124 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
2125 // on the extended Op0 and (unextended) Op1. Store the even register result
2126 // in Even and the odd register result in Odd.
2127 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
2128 unsigned Extend, unsigned Opcode,
2129 SDValue Op0, SDValue Op1,
2130 SDValue &Even, SDValue &Odd) {
2131 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
2132 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
2133 SDValue(In128, 0), Op1);
2134 bool Is32Bit = is32Bit(VT);
2135 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
2136 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
2139 // Return an i32 value that is 1 if the CC value produced by Glue is
2140 // in the mask CCMask and 0 otherwise. CC is known to have a value
2141 // in CCValid, so other values can be ignored.
2142 static SDValue emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue,
2143 unsigned CCValid, unsigned CCMask) {
2144 IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
2145 SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
2147 if (Conversion.XORValue)
2148 Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
2149 DAG.getConstant(Conversion.XORValue, DL, MVT::i32));
2151 if (Conversion.AddValue)
2152 Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
2153 DAG.getConstant(Conversion.AddValue, DL, MVT::i32));
2155 // The SHR/AND sequence should get optimized to an RISBG.
2156 Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
2157 DAG.getConstant(Conversion.Bit, DL, MVT::i32));
2158 if (Conversion.Bit != 31)
2159 Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
2160 DAG.getConstant(1, DL, MVT::i32));
2164 // Return the SystemISD vector comparison operation for CC, or 0 if it cannot
2165 // be done directly. IsFP is true if CC is for a floating-point rather than
2166 // integer comparison.
2167 static unsigned getVectorComparison(ISD::CondCode CC, bool IsFP) {
2171 return IsFP ? SystemZISD::VFCMPE : SystemZISD::VICMPE;
2175 return IsFP ? SystemZISD::VFCMPHE : static_cast<SystemZISD::NodeType>(0);
2179 return IsFP ? SystemZISD::VFCMPH : SystemZISD::VICMPH;
2182 return IsFP ? static_cast<SystemZISD::NodeType>(0) : SystemZISD::VICMPHL;
2189 // Return the SystemZISD vector comparison operation for CC or its inverse,
2190 // or 0 if neither can be done directly. Indicate in Invert whether the
2191 // result is for the inverse of CC. IsFP is true if CC is for a
2192 // floating-point rather than integer comparison.
2193 static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, bool IsFP,
2195 if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2200 CC = ISD::getSetCCInverse(CC, !IsFP);
2201 if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2209 // Return a v2f64 that contains the extended form of elements Start and Start+1
2210 // of v4f32 value Op.
2211 static SDValue expandV4F32ToV2F64(SelectionDAG &DAG, int Start, SDLoc DL,
2213 int Mask[] = { Start, -1, Start + 1, -1 };
2214 Op = DAG.getVectorShuffle(MVT::v4f32, DL, Op, DAG.getUNDEF(MVT::v4f32), Mask);
2215 return DAG.getNode(SystemZISD::VEXTEND, DL, MVT::v2f64, Op);
2218 // Build a comparison of vectors CmpOp0 and CmpOp1 using opcode Opcode,
2219 // producing a result of type VT.
2220 static SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode, SDLoc DL,
2221 EVT VT, SDValue CmpOp0, SDValue CmpOp1) {
2222 // There is no hardware support for v4f32, so extend the vector into
2223 // two v2f64s and compare those.
2224 if (CmpOp0.getValueType() == MVT::v4f32) {
2225 SDValue H0 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp0);
2226 SDValue L0 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp0);
2227 SDValue H1 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp1);
2228 SDValue L1 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp1);
2229 SDValue HRes = DAG.getNode(Opcode, DL, MVT::v2i64, H0, H1);
2230 SDValue LRes = DAG.getNode(Opcode, DL, MVT::v2i64, L0, L1);
2231 return DAG.getNode(SystemZISD::PACK, DL, VT, HRes, LRes);
2233 return DAG.getNode(Opcode, DL, VT, CmpOp0, CmpOp1);
2236 // Lower a vector comparison of type CC between CmpOp0 and CmpOp1, producing
2237 // an integer mask of type VT.
2238 static SDValue lowerVectorSETCC(SelectionDAG &DAG, SDLoc DL, EVT VT,
2239 ISD::CondCode CC, SDValue CmpOp0,
2241 bool IsFP = CmpOp0.getValueType().isFloatingPoint();
2242 bool Invert = false;
2245 // Handle tests for order using (or (ogt y x) (oge x y)).
2249 assert(IsFP && "Unexpected integer comparison");
2250 SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0);
2251 SDValue GE = getVectorCmp(DAG, SystemZISD::VFCMPHE, DL, VT, CmpOp0, CmpOp1);
2252 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GE);
2256 // Handle <> tests using (or (ogt y x) (ogt x y)).
2260 assert(IsFP && "Unexpected integer comparison");
2261 SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0);
2262 SDValue GT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp0, CmpOp1);
2263 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GT);
2267 // Otherwise a single comparison is enough. It doesn't really
2268 // matter whether we try the inversion or the swap first, since
2269 // there are no cases where both work.
2271 if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2272 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1);
2274 CC = ISD::getSetCCSwappedOperands(CC);
2275 if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2276 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp1, CmpOp0);
2278 llvm_unreachable("Unhandled comparison");
2283 SDValue Mask = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
2284 DAG.getConstant(65535, DL, MVT::i32));
2285 Mask = DAG.getNode(ISD::BITCAST, DL, VT, Mask);
2286 Cmp = DAG.getNode(ISD::XOR, DL, VT, Cmp, Mask);
2291 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
2292 SelectionDAG &DAG) const {
2293 SDValue CmpOp0 = Op.getOperand(0);
2294 SDValue CmpOp1 = Op.getOperand(1);
2295 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2297 EVT VT = Op.getValueType();
2299 return lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1);
2301 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2302 SDValue Glue = emitCmp(DAG, DL, C);
2303 return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
2306 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2307 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2308 SDValue CmpOp0 = Op.getOperand(2);
2309 SDValue CmpOp1 = Op.getOperand(3);
2310 SDValue Dest = Op.getOperand(4);
2313 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2314 SDValue Glue = emitCmp(DAG, DL, C);
2315 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
2316 Op.getOperand(0), DAG.getConstant(C.CCValid, DL, MVT::i32),
2317 DAG.getConstant(C.CCMask, DL, MVT::i32), Dest, Glue);
2320 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
2321 // allowing Pos and Neg to be wider than CmpOp.
2322 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
2323 return (Neg.getOpcode() == ISD::SUB &&
2324 Neg.getOperand(0).getOpcode() == ISD::Constant &&
2325 cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
2326 Neg.getOperand(1) == Pos &&
2328 (Pos.getOpcode() == ISD::SIGN_EXTEND &&
2329 Pos.getOperand(0) == CmpOp)));
2332 // Return the absolute or negative absolute of Op; IsNegative decides which.
2333 static SDValue getAbsolute(SelectionDAG &DAG, SDLoc DL, SDValue Op,
2335 Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
2337 Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
2338 DAG.getConstant(0, DL, Op.getValueType()), Op);
2342 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
2343 SelectionDAG &DAG) const {
2344 SDValue CmpOp0 = Op.getOperand(0);
2345 SDValue CmpOp1 = Op.getOperand(1);
2346 SDValue TrueOp = Op.getOperand(2);
2347 SDValue FalseOp = Op.getOperand(3);
2348 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2351 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2353 // Check for absolute and negative-absolute selections, including those
2354 // where the comparison value is sign-extended (for LPGFR and LNGFR).
2355 // This check supplements the one in DAGCombiner.
2356 if (C.Opcode == SystemZISD::ICMP &&
2357 C.CCMask != SystemZ::CCMASK_CMP_EQ &&
2358 C.CCMask != SystemZ::CCMASK_CMP_NE &&
2359 C.Op1.getOpcode() == ISD::Constant &&
2360 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
2361 if (isAbsolute(C.Op0, TrueOp, FalseOp))
2362 return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
2363 if (isAbsolute(C.Op0, FalseOp, TrueOp))
2364 return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
2367 SDValue Glue = emitCmp(DAG, DL, C);
2369 // Special case for handling -1/0 results. The shifts we use here
2370 // should get optimized with the IPM conversion sequence.
2371 auto *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
2372 auto *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
2373 if (TrueC && FalseC) {
2374 int64_t TrueVal = TrueC->getSExtValue();
2375 int64_t FalseVal = FalseC->getSExtValue();
2376 if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
2377 // Invert the condition if we want -1 on false.
2379 C.CCMask ^= C.CCValid;
2380 SDValue Result = emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
2381 EVT VT = Op.getValueType();
2382 // Extend the result to VT. Upper bits are ignored.
2384 Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
2385 // Sign-extend from the low bit.
2386 SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32);
2387 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
2388 return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
2392 SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, DL, MVT::i32),
2393 DAG.getConstant(C.CCMask, DL, MVT::i32), Glue};
2395 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
2396 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
2399 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
2400 SelectionDAG &DAG) const {
2402 const GlobalValue *GV = Node->getGlobal();
2403 int64_t Offset = Node->getOffset();
2404 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2405 Reloc::Model RM = DAG.getTarget().getRelocationModel();
2406 CodeModel::Model CM = DAG.getTarget().getCodeModel();
2409 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
2410 // Assign anchors at 1<<12 byte boundaries.
2411 uint64_t Anchor = Offset & ~uint64_t(0xfff);
2412 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
2413 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2415 // The offset can be folded into the address if it is aligned to a halfword.
2417 if (Offset != 0 && (Offset & 1) == 0) {
2418 SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
2419 Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
2423 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
2424 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2425 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2426 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2427 false, false, false, 0);
2430 // If there was a non-zero offset that we didn't fold, create an explicit
2433 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
2434 DAG.getConstant(Offset, DL, PtrVT));
2439 SDValue SystemZTargetLowering::lowerTLSGetOffset(GlobalAddressSDNode *Node,
2442 SDValue GOTOffset) const {
2444 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2445 SDValue Chain = DAG.getEntryNode();
2448 // __tls_get_offset takes the GOT offset in %r2 and the GOT in %r12.
2449 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2450 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R12D, GOT, Glue);
2451 Glue = Chain.getValue(1);
2452 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R2D, GOTOffset, Glue);
2453 Glue = Chain.getValue(1);
2455 // The first call operand is the chain and the second is the TLS symbol.
2456 SmallVector<SDValue, 8> Ops;
2457 Ops.push_back(Chain);
2458 Ops.push_back(DAG.getTargetGlobalAddress(Node->getGlobal(), DL,
2459 Node->getValueType(0),
2462 // Add argument registers to the end of the list so that they are
2463 // known live into the call.
2464 Ops.push_back(DAG.getRegister(SystemZ::R2D, PtrVT));
2465 Ops.push_back(DAG.getRegister(SystemZ::R12D, PtrVT));
2467 // Add a register mask operand representing the call-preserved registers.
2468 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2469 const uint32_t *Mask =
2470 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
2471 assert(Mask && "Missing call preserved mask for calling convention");
2472 Ops.push_back(DAG.getRegisterMask(Mask));
2474 // Glue the call to the argument copies.
2475 Ops.push_back(Glue);
2478 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2479 Chain = DAG.getNode(Opcode, DL, NodeTys, Ops);
2480 Glue = Chain.getValue(1);
2482 // Copy the return value from %r2.
2483 return DAG.getCopyFromReg(Chain, DL, SystemZ::R2D, PtrVT, Glue);
2486 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
2487 SelectionDAG &DAG) const {
2488 if (DAG.getTarget().Options.EmulatedTLS)
2489 return LowerToTLSEmulatedModel(Node, DAG);
2491 const GlobalValue *GV = Node->getGlobal();
2492 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2493 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
2495 // The high part of the thread pointer is in access register 0.
2496 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
2497 DAG.getConstant(0, DL, MVT::i32));
2498 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
2500 // The low part of the thread pointer is in access register 1.
2501 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
2502 DAG.getConstant(1, DL, MVT::i32));
2503 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
2505 // Merge them into a single 64-bit address.
2506 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
2507 DAG.getConstant(32, DL, PtrVT));
2508 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
2510 // Get the offset of GA from the thread pointer, based on the TLS model.
2513 case TLSModel::GeneralDynamic: {
2514 // Load the GOT offset of the tls_index (module ID / per-symbol offset).
2515 SystemZConstantPoolValue *CPV =
2516 SystemZConstantPoolValue::Create(GV, SystemZCP::TLSGD);
2518 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2519 Offset = DAG.getLoad(
2520 PtrVT, DL, DAG.getEntryNode(), Offset,
2521 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2524 // Call __tls_get_offset to retrieve the offset.
2525 Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_GDCALL, Offset);
2529 case TLSModel::LocalDynamic: {
2530 // Load the GOT offset of the module ID.
2531 SystemZConstantPoolValue *CPV =
2532 SystemZConstantPoolValue::Create(GV, SystemZCP::TLSLDM);
2534 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2535 Offset = DAG.getLoad(
2536 PtrVT, DL, DAG.getEntryNode(), Offset,
2537 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2540 // Call __tls_get_offset to retrieve the module base offset.
2541 Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_LDCALL, Offset);
2543 // Note: The SystemZLDCleanupPass will remove redundant computations
2544 // of the module base offset. Count total number of local-dynamic
2545 // accesses to trigger execution of that pass.
2546 SystemZMachineFunctionInfo* MFI =
2547 DAG.getMachineFunction().getInfo<SystemZMachineFunctionInfo>();
2548 MFI->incNumLocalDynamicTLSAccesses();
2550 // Add the per-symbol offset.
2551 CPV = SystemZConstantPoolValue::Create(GV, SystemZCP::DTPOFF);
2553 SDValue DTPOffset = DAG.getConstantPool(CPV, PtrVT, 8);
2554 DTPOffset = DAG.getLoad(
2555 PtrVT, DL, DAG.getEntryNode(), DTPOffset,
2556 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2559 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Offset, DTPOffset);
2563 case TLSModel::InitialExec: {
2564 // Load the offset from the GOT.
2565 Offset = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2566 SystemZII::MO_INDNTPOFF);
2567 Offset = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Offset);
2568 Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Offset,
2569 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2570 false, false, false, 0);
2574 case TLSModel::LocalExec: {
2575 // Force the offset into the constant pool and load it from there.
2576 SystemZConstantPoolValue *CPV =
2577 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
2579 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2580 Offset = DAG.getLoad(
2581 PtrVT, DL, DAG.getEntryNode(), Offset,
2582 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2588 // Add the base and offset together.
2589 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
2592 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
2593 SelectionDAG &DAG) const {
2595 const BlockAddress *BA = Node->getBlockAddress();
2596 int64_t Offset = Node->getOffset();
2597 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2599 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
2600 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2604 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
2605 SelectionDAG &DAG) const {
2607 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2608 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2610 // Use LARL to load the address of the table.
2611 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2614 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
2615 SelectionDAG &DAG) const {
2617 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2620 if (CP->isMachineConstantPoolEntry())
2621 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2622 CP->getAlignment());
2624 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2625 CP->getAlignment(), CP->getOffset());
2627 // Use LARL to load the address of the constant pool entry.
2628 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2631 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
2632 SelectionDAG &DAG) const {
2634 SDValue In = Op.getOperand(0);
2635 EVT InVT = In.getValueType();
2636 EVT ResVT = Op.getValueType();
2638 // Convert loads directly. This is normally done by DAGCombiner,
2639 // but we need this case for bitcasts that are created during lowering
2640 // and which are then lowered themselves.
2641 if (auto *LoadN = dyn_cast<LoadSDNode>(In))
2642 return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(),
2643 LoadN->getMemOperand());
2645 if (InVT == MVT::i32 && ResVT == MVT::f32) {
2647 if (Subtarget.hasHighWord()) {
2648 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
2650 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
2651 MVT::i64, SDValue(U64, 0), In);
2653 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
2654 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
2655 DAG.getConstant(32, DL, MVT::i64));
2657 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
2658 return DAG.getTargetExtractSubreg(SystemZ::subreg_r32,
2659 DL, MVT::f32, Out64);
2661 if (InVT == MVT::f32 && ResVT == MVT::i32) {
2662 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
2663 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_r32, DL,
2664 MVT::f64, SDValue(U64, 0), In);
2665 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
2666 if (Subtarget.hasHighWord())
2667 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
2669 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
2670 DAG.getConstant(32, DL, MVT::i64));
2671 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
2673 llvm_unreachable("Unexpected bitcast combination");
2676 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
2677 SelectionDAG &DAG) const {
2678 MachineFunction &MF = DAG.getMachineFunction();
2679 SystemZMachineFunctionInfo *FuncInfo =
2680 MF.getInfo<SystemZMachineFunctionInfo>();
2681 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2683 SDValue Chain = Op.getOperand(0);
2684 SDValue Addr = Op.getOperand(1);
2685 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2688 // The initial values of each field.
2689 const unsigned NumFields = 4;
2690 SDValue Fields[NumFields] = {
2691 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), DL, PtrVT),
2692 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), DL, PtrVT),
2693 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
2694 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
2697 // Store each field into its respective slot.
2698 SDValue MemOps[NumFields];
2699 unsigned Offset = 0;
2700 for (unsigned I = 0; I < NumFields; ++I) {
2701 SDValue FieldAddr = Addr;
2703 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
2704 DAG.getIntPtrConstant(Offset, DL));
2705 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
2706 MachinePointerInfo(SV, Offset),
2710 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2713 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
2714 SelectionDAG &DAG) const {
2715 SDValue Chain = Op.getOperand(0);
2716 SDValue DstPtr = Op.getOperand(1);
2717 SDValue SrcPtr = Op.getOperand(2);
2718 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2719 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
2722 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32, DL),
2723 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
2724 /*isTailCall*/false,
2725 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
2728 SDValue SystemZTargetLowering::
2729 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
2730 SDValue Chain = Op.getOperand(0);
2731 SDValue Size = Op.getOperand(1);
2734 unsigned SPReg = getStackPointerRegisterToSaveRestore();
2736 // Get a reference to the stack pointer.
2737 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
2739 // Get the new stack pointer value.
2740 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
2742 // Copy the new stack pointer back.
2743 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
2745 // The allocated data lives above the 160 bytes allocated for the standard
2746 // frame, plus any outgoing stack arguments. We don't know how much that
2747 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
2748 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
2749 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
2751 SDValue Ops[2] = { Result, Chain };
2752 return DAG.getMergeValues(Ops, DL);
2755 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
2756 SelectionDAG &DAG) const {
2757 EVT VT = Op.getValueType();
2761 // Just do a normal 64-bit multiplication and extract the results.
2762 // We define this so that it can be used for constant division.
2763 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
2764 Op.getOperand(1), Ops[1], Ops[0]);
2766 // Do a full 128-bit multiplication based on UMUL_LOHI64:
2768 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
2770 // but using the fact that the upper halves are either all zeros
2773 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
2775 // and grouping the right terms together since they are quicker than the
2778 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
2779 SDValue C63 = DAG.getConstant(63, DL, MVT::i64);
2780 SDValue LL = Op.getOperand(0);
2781 SDValue RL = Op.getOperand(1);
2782 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
2783 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
2784 // UMUL_LOHI64 returns the low result in the odd register and the high
2785 // result in the even register. SMUL_LOHI is defined to return the
2786 // low half first, so the results are in reverse order.
2787 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2788 LL, RL, Ops[1], Ops[0]);
2789 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
2790 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
2791 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
2792 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
2794 return DAG.getMergeValues(Ops, DL);
2797 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
2798 SelectionDAG &DAG) const {
2799 EVT VT = Op.getValueType();
2803 // Just do a normal 64-bit multiplication and extract the results.
2804 // We define this so that it can be used for constant division.
2805 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
2806 Op.getOperand(1), Ops[1], Ops[0]);
2808 // UMUL_LOHI64 returns the low result in the odd register and the high
2809 // result in the even register. UMUL_LOHI is defined to return the
2810 // low half first, so the results are in reverse order.
2811 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2812 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2813 return DAG.getMergeValues(Ops, DL);
2816 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
2817 SelectionDAG &DAG) const {
2818 SDValue Op0 = Op.getOperand(0);
2819 SDValue Op1 = Op.getOperand(1);
2820 EVT VT = Op.getValueType();
2824 // We use DSGF for 32-bit division.
2826 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
2827 Opcode = SystemZISD::SDIVREM32;
2828 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
2829 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
2830 Opcode = SystemZISD::SDIVREM32;
2832 Opcode = SystemZISD::SDIVREM64;
2834 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
2835 // input is "don't care". The instruction returns the remainder in
2836 // the even register and the quotient in the odd register.
2838 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
2839 Op0, Op1, Ops[1], Ops[0]);
2840 return DAG.getMergeValues(Ops, DL);
2843 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
2844 SelectionDAG &DAG) const {
2845 EVT VT = Op.getValueType();
2848 // DL(G) uses a double-width dividend, so we need to clear the even
2849 // register in the GR128 input. The instruction returns the remainder
2850 // in the even register and the quotient in the odd register.
2853 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
2854 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2856 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
2857 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2858 return DAG.getMergeValues(Ops, DL);
2861 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
2862 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
2864 // Get the known-zero masks for each operand.
2865 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
2866 APInt KnownZero[2], KnownOne[2];
2867 DAG.computeKnownBits(Ops[0], KnownZero[0], KnownOne[0]);
2868 DAG.computeKnownBits(Ops[1], KnownZero[1], KnownOne[1]);
2870 // See if the upper 32 bits of one operand and the lower 32 bits of the
2871 // other are known zero. They are the low and high operands respectively.
2872 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
2873 KnownZero[1].getZExtValue() };
2875 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
2877 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
2882 SDValue LowOp = Ops[Low];
2883 SDValue HighOp = Ops[High];
2885 // If the high part is a constant, we're better off using IILH.
2886 if (HighOp.getOpcode() == ISD::Constant)
2889 // If the low part is a constant that is outside the range of LHI,
2890 // then we're better off using IILF.
2891 if (LowOp.getOpcode() == ISD::Constant) {
2892 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
2893 if (!isInt<16>(Value))
2897 // Check whether the high part is an AND that doesn't change the
2898 // high 32 bits and just masks out low bits. We can skip it if so.
2899 if (HighOp.getOpcode() == ISD::AND &&
2900 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
2901 SDValue HighOp0 = HighOp.getOperand(0);
2902 uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
2903 if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
2907 // Take advantage of the fact that all GR32 operations only change the
2908 // low 32 bits by truncating Low to an i32 and inserting it directly
2909 // using a subreg. The interesting cases are those where the truncation
2912 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
2913 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
2914 MVT::i64, HighOp, Low32);
2917 SDValue SystemZTargetLowering::lowerCTPOP(SDValue Op,
2918 SelectionDAG &DAG) const {
2919 EVT VT = Op.getValueType();
2921 Op = Op.getOperand(0);
2923 // Handle vector types via VPOPCT.
2924 if (VT.isVector()) {
2925 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Op);
2926 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::v16i8, Op);
2927 switch (VT.getVectorElementType().getSizeInBits()) {
2931 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
2932 SDValue Shift = DAG.getConstant(8, DL, MVT::i32);
2933 SDValue Tmp = DAG.getNode(SystemZISD::VSHL_BY_SCALAR, DL, VT, Op, Shift);
2934 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
2935 Op = DAG.getNode(SystemZISD::VSRL_BY_SCALAR, DL, VT, Op, Shift);
2939 SDValue Tmp = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
2940 DAG.getConstant(0, DL, MVT::i32));
2941 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
2945 SDValue Tmp = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
2946 DAG.getConstant(0, DL, MVT::i32));
2947 Op = DAG.getNode(SystemZISD::VSUM, DL, MVT::v4i32, Op, Tmp);
2948 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
2952 llvm_unreachable("Unexpected type");
2957 // Get the known-zero mask for the operand.
2958 APInt KnownZero, KnownOne;
2959 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2960 unsigned NumSignificantBits = (~KnownZero).getActiveBits();
2961 if (NumSignificantBits == 0)
2962 return DAG.getConstant(0, DL, VT);
2964 // Skip known-zero high parts of the operand.
2965 int64_t OrigBitSize = VT.getSizeInBits();
2966 int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits);
2967 BitSize = std::min(BitSize, OrigBitSize);
2969 // The POPCNT instruction counts the number of bits in each byte.
2970 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op);
2971 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::i64, Op);
2972 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
2974 // Add up per-byte counts in a binary tree. All bits of Op at
2975 // position larger than BitSize remain zero throughout.
2976 for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
2977 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));
2978 if (BitSize != OrigBitSize)
2979 Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,
2980 DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT));
2981 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
2984 // Extract overall result from high byte.
2986 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
2987 DAG.getConstant(BitSize - 8, DL, VT));
2992 // Op is an atomic load. Lower it into a normal volatile load.
2993 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
2994 SelectionDAG &DAG) const {
2995 auto *Node = cast<AtomicSDNode>(Op.getNode());
2996 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
2997 Node->getChain(), Node->getBasePtr(),
2998 Node->getMemoryVT(), Node->getMemOperand());
3001 // Op is an atomic store. Lower it into a normal volatile store followed
3002 // by a serialization.
3003 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
3004 SelectionDAG &DAG) const {
3005 auto *Node = cast<AtomicSDNode>(Op.getNode());
3006 SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
3007 Node->getBasePtr(), Node->getMemoryVT(),
3008 Node->getMemOperand());
3009 return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
3013 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
3014 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
3015 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
3017 unsigned Opcode) const {
3018 auto *Node = cast<AtomicSDNode>(Op.getNode());
3020 // 32-bit operations need no code outside the main loop.
3021 EVT NarrowVT = Node->getMemoryVT();
3022 EVT WideVT = MVT::i32;
3023 if (NarrowVT == WideVT)
3026 int64_t BitSize = NarrowVT.getSizeInBits();
3027 SDValue ChainIn = Node->getChain();
3028 SDValue Addr = Node->getBasePtr();
3029 SDValue Src2 = Node->getVal();
3030 MachineMemOperand *MMO = Node->getMemOperand();
3032 EVT PtrVT = Addr.getValueType();
3034 // Convert atomic subtracts of constants into additions.
3035 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
3036 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
3037 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
3038 Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType());
3041 // Get the address of the containing word.
3042 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3043 DAG.getConstant(-4, DL, PtrVT));
3045 // Get the number of bits that the word must be rotated left in order
3046 // to bring the field to the top bits of a GR32.
3047 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3048 DAG.getConstant(3, DL, PtrVT));
3049 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3051 // Get the complementing shift amount, for rotating a field in the top
3052 // bits back to its proper position.
3053 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3054 DAG.getConstant(0, DL, WideVT), BitShift);
3056 // Extend the source operand to 32 bits and prepare it for the inner loop.
3057 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
3058 // operations require the source to be shifted in advance. (This shift
3059 // can be folded if the source is constant.) For AND and NAND, the lower
3060 // bits must be set, while for other opcodes they should be left clear.
3061 if (Opcode != SystemZISD::ATOMIC_SWAPW)
3062 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
3063 DAG.getConstant(32 - BitSize, DL, WideVT));
3064 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
3065 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
3066 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
3067 DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT));
3069 // Construct the ATOMIC_LOADW_* node.
3070 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
3071 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
3072 DAG.getConstant(BitSize, DL, WideVT) };
3073 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
3076 // Rotate the result of the final CS so that the field is in the lower
3077 // bits of a GR32, then truncate it.
3078 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
3079 DAG.getConstant(BitSize, DL, WideVT));
3080 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
3082 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
3083 return DAG.getMergeValues(RetOps, DL);
3086 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
3087 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
3088 // operations into additions.
3089 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
3090 SelectionDAG &DAG) const {
3091 auto *Node = cast<AtomicSDNode>(Op.getNode());
3092 EVT MemVT = Node->getMemoryVT();
3093 if (MemVT == MVT::i32 || MemVT == MVT::i64) {
3094 // A full-width operation.
3095 assert(Op.getValueType() == MemVT && "Mismatched VTs");
3096 SDValue Src2 = Node->getVal();
3100 if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
3101 // Use an addition if the operand is constant and either LAA(G) is
3102 // available or the negative value is in the range of A(G)FHI.
3103 int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
3104 if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
3105 NegSrc2 = DAG.getConstant(Value, DL, MemVT);
3106 } else if (Subtarget.hasInterlockedAccess1())
3107 // Use LAA(G) if available.
3108 NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL, MemVT),
3111 if (NegSrc2.getNode())
3112 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
3113 Node->getChain(), Node->getBasePtr(), NegSrc2,
3114 Node->getMemOperand(), Node->getOrdering(),
3115 Node->getSynchScope());
3117 // Use the node as-is.
3121 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
3124 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
3125 // into a fullword ATOMIC_CMP_SWAPW operation.
3126 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
3127 SelectionDAG &DAG) const {
3128 auto *Node = cast<AtomicSDNode>(Op.getNode());
3130 // We have native support for 32-bit compare and swap.
3131 EVT NarrowVT = Node->getMemoryVT();
3132 EVT WideVT = MVT::i32;
3133 if (NarrowVT == WideVT)
3136 int64_t BitSize = NarrowVT.getSizeInBits();
3137 SDValue ChainIn = Node->getOperand(0);
3138 SDValue Addr = Node->getOperand(1);
3139 SDValue CmpVal = Node->getOperand(2);
3140 SDValue SwapVal = Node->getOperand(3);
3141 MachineMemOperand *MMO = Node->getMemOperand();
3143 EVT PtrVT = Addr.getValueType();
3145 // Get the address of the containing word.
3146 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3147 DAG.getConstant(-4, DL, PtrVT));
3149 // Get the number of bits that the word must be rotated left in order
3150 // to bring the field to the top bits of a GR32.
3151 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3152 DAG.getConstant(3, DL, PtrVT));
3153 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3155 // Get the complementing shift amount, for rotating a field in the top
3156 // bits back to its proper position.
3157 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3158 DAG.getConstant(0, DL, WideVT), BitShift);
3160 // Construct the ATOMIC_CMP_SWAPW node.
3161 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
3162 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
3163 NegBitShift, DAG.getConstant(BitSize, DL, WideVT) };
3164 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
3165 VTList, Ops, NarrowVT, MMO);
3169 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
3170 SelectionDAG &DAG) const {
3171 MachineFunction &MF = DAG.getMachineFunction();
3172 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
3173 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
3174 SystemZ::R15D, Op.getValueType());
3177 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
3178 SelectionDAG &DAG) const {
3179 MachineFunction &MF = DAG.getMachineFunction();
3180 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
3181 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
3182 SystemZ::R15D, Op.getOperand(1));
3185 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
3186 SelectionDAG &DAG) const {
3187 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3189 // Just preserve the chain.
3190 return Op.getOperand(0);
3193 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3194 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
3195 auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
3198 DAG.getConstant(Code, DL, MVT::i32),
3201 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, DL,
3202 Node->getVTList(), Ops,
3203 Node->getMemoryVT(), Node->getMemOperand());
3206 // Return an i32 that contains the value of CC immediately after After,
3207 // whose final operand must be MVT::Glue.
3208 static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {
3210 SDValue Glue = SDValue(After, After->getNumValues() - 1);
3211 SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
3212 return DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
3213 DAG.getConstant(SystemZ::IPM_CC, DL, MVT::i32));
3217 SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
3218 SelectionDAG &DAG) const {
3219 unsigned Opcode, CCValid;
3220 if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
3221 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
3222 SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
3223 SDValue CC = getCCResult(DAG, Glued.getNode());
3224 DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
3232 SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
3233 SelectionDAG &DAG) const {
3234 unsigned Opcode, CCValid;
3235 if (isIntrinsicWithCC(Op, Opcode, CCValid)) {
3236 SDValue Glued = emitIntrinsicWithGlue(DAG, Op, Opcode);
3237 SDValue CC = getCCResult(DAG, Glued.getNode());
3238 if (Op->getNumValues() == 1)
3240 assert(Op->getNumValues() == 2 && "Expected a CC and non-CC result");
3241 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(),
3245 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3247 case Intrinsic::s390_vpdi:
3248 return DAG.getNode(SystemZISD::PERMUTE_DWORDS, SDLoc(Op), Op.getValueType(),
3249 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3251 case Intrinsic::s390_vperm:
3252 return DAG.getNode(SystemZISD::PERMUTE, SDLoc(Op), Op.getValueType(),
3253 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3255 case Intrinsic::s390_vuphb:
3256 case Intrinsic::s390_vuphh:
3257 case Intrinsic::s390_vuphf:
3258 return DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(Op), Op.getValueType(),
3261 case Intrinsic::s390_vuplhb:
3262 case Intrinsic::s390_vuplhh:
3263 case Intrinsic::s390_vuplhf:
3264 return DAG.getNode(SystemZISD::UNPACKL_HIGH, SDLoc(Op), Op.getValueType(),
3267 case Intrinsic::s390_vuplb:
3268 case Intrinsic::s390_vuplhw:
3269 case Intrinsic::s390_vuplf:
3270 return DAG.getNode(SystemZISD::UNPACK_LOW, SDLoc(Op), Op.getValueType(),
3273 case Intrinsic::s390_vupllb:
3274 case Intrinsic::s390_vupllh:
3275 case Intrinsic::s390_vupllf:
3276 return DAG.getNode(SystemZISD::UNPACKL_LOW, SDLoc(Op), Op.getValueType(),
3279 case Intrinsic::s390_vsumb:
3280 case Intrinsic::s390_vsumh:
3281 case Intrinsic::s390_vsumgh:
3282 case Intrinsic::s390_vsumgf:
3283 case Intrinsic::s390_vsumqf:
3284 case Intrinsic::s390_vsumqg:
3285 return DAG.getNode(SystemZISD::VSUM, SDLoc(Op), Op.getValueType(),
3286 Op.getOperand(1), Op.getOperand(2));
3293 // Says that SystemZISD operation Opcode can be used to perform the equivalent
3294 // of a VPERM with permute vector Bytes. If Opcode takes three operands,
3295 // Operand is the constant third operand, otherwise it is the number of
3296 // bytes in each element of the result.
3300 unsigned char Bytes[SystemZ::VectorBytes];
3304 static const Permute PermuteForms[] = {
3306 { SystemZISD::MERGE_HIGH, 8,
3307 { 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 } },
3309 { SystemZISD::MERGE_HIGH, 4,
3310 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
3312 { SystemZISD::MERGE_HIGH, 2,
3313 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
3315 { SystemZISD::MERGE_HIGH, 1,
3316 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
3318 { SystemZISD::MERGE_LOW, 8,
3319 { 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31 } },
3321 { SystemZISD::MERGE_LOW, 4,
3322 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
3324 { SystemZISD::MERGE_LOW, 2,
3325 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
3327 { SystemZISD::MERGE_LOW, 1,
3328 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
3330 { SystemZISD::PACK, 4,
3331 { 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31 } },
3333 { SystemZISD::PACK, 2,
3334 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
3336 { SystemZISD::PACK, 1,
3337 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
3338 // VPDI V1, V2, 4 (low half of V1, high half of V2)
3339 { SystemZISD::PERMUTE_DWORDS, 4,
3340 { 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 } },
3341 // VPDI V1, V2, 1 (high half of V1, low half of V2)
3342 { SystemZISD::PERMUTE_DWORDS, 1,
3343 { 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31 } }
3346 // Called after matching a vector shuffle against a particular pattern.
3347 // Both the original shuffle and the pattern have two vector operands.
3348 // OpNos[0] is the operand of the original shuffle that should be used for
3349 // operand 0 of the pattern, or -1 if operand 0 of the pattern can be anything.
3350 // OpNos[1] is the same for operand 1 of the pattern. Resolve these -1s and
3351 // set OpNo0 and OpNo1 to the shuffle operands that should actually be used
3352 // for operands 0 and 1 of the pattern.
3353 static bool chooseShuffleOpNos(int *OpNos, unsigned &OpNo0, unsigned &OpNo1) {
3357 OpNo0 = OpNo1 = OpNos[1];
3358 } else if (OpNos[1] < 0) {
3359 OpNo0 = OpNo1 = OpNos[0];
3367 // Bytes is a VPERM-like permute vector, except that -1 is used for
3368 // undefined bytes. Return true if the VPERM can be implemented using P.
3369 // When returning true set OpNo0 to the VPERM operand that should be
3370 // used for operand 0 of P and likewise OpNo1 for operand 1 of P.
3372 // For example, if swapping the VPERM operands allows P to match, OpNo0
3373 // will be 1 and OpNo1 will be 0. If instead Bytes only refers to one
3374 // operand, but rewriting it to use two duplicated operands allows it to
3375 // match P, then OpNo0 and OpNo1 will be the same.
3376 static bool matchPermute(const SmallVectorImpl<int> &Bytes, const Permute &P,
3377 unsigned &OpNo0, unsigned &OpNo1) {
3378 int OpNos[] = { -1, -1 };
3379 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
3382 // Make sure that the two permute vectors use the same suboperand
3383 // byte number. Only the operand numbers (the high bits) are
3384 // allowed to differ.
3385 if ((Elt ^ P.Bytes[I]) & (SystemZ::VectorBytes - 1))
3387 int ModelOpNo = P.Bytes[I] / SystemZ::VectorBytes;
3388 int RealOpNo = unsigned(Elt) / SystemZ::VectorBytes;
3389 // Make sure that the operand mappings are consistent with previous
3391 if (OpNos[ModelOpNo] == 1 - RealOpNo)
3393 OpNos[ModelOpNo] = RealOpNo;
3396 return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
3399 // As above, but search for a matching permute.
3400 static const Permute *matchPermute(const SmallVectorImpl<int> &Bytes,
3401 unsigned &OpNo0, unsigned &OpNo1) {
3402 for (auto &P : PermuteForms)
3403 if (matchPermute(Bytes, P, OpNo0, OpNo1))
3408 // Bytes is a VPERM-like permute vector, except that -1 is used for
3409 // undefined bytes. This permute is an operand of an outer permute.
3410 // See whether redistributing the -1 bytes gives a shuffle that can be
3411 // implemented using P. If so, set Transform to a VPERM-like permute vector
3412 // that, when applied to the result of P, gives the original permute in Bytes.
3413 static bool matchDoublePermute(const SmallVectorImpl<int> &Bytes,
3415 SmallVectorImpl<int> &Transform) {
3417 for (unsigned From = 0; From < SystemZ::VectorBytes; ++From) {
3418 int Elt = Bytes[From];
3420 // Byte number From of the result is undefined.
3421 Transform[From] = -1;
3423 while (P.Bytes[To] != Elt) {
3425 if (To == SystemZ::VectorBytes)
3428 Transform[From] = To;
3434 // As above, but search for a matching permute.
3435 static const Permute *matchDoublePermute(const SmallVectorImpl<int> &Bytes,
3436 SmallVectorImpl<int> &Transform) {
3437 for (auto &P : PermuteForms)
3438 if (matchDoublePermute(Bytes, P, Transform))
3443 // Convert the mask of the given VECTOR_SHUFFLE into a byte-level mask,
3444 // as if it had type vNi8.
3445 static void getVPermMask(ShuffleVectorSDNode *VSN,
3446 SmallVectorImpl<int> &Bytes) {
3447 EVT VT = VSN->getValueType(0);
3448 unsigned NumElements = VT.getVectorNumElements();
3449 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3450 Bytes.resize(NumElements * BytesPerElement, -1);
3451 for (unsigned I = 0; I < NumElements; ++I) {
3452 int Index = VSN->getMaskElt(I);
3454 for (unsigned J = 0; J < BytesPerElement; ++J)
3455 Bytes[I * BytesPerElement + J] = Index * BytesPerElement + J;
3459 // Bytes is a VPERM-like permute vector, except that -1 is used for
3460 // undefined bytes. See whether bytes [Start, Start + BytesPerElement) of
3461 // the result come from a contiguous sequence of bytes from one input.
3462 // Set Base to the selector for the first byte if so.
3463 static bool getShuffleInput(const SmallVectorImpl<int> &Bytes, unsigned Start,
3464 unsigned BytesPerElement, int &Base) {
3466 for (unsigned I = 0; I < BytesPerElement; ++I) {
3467 if (Bytes[Start + I] >= 0) {
3468 unsigned Elem = Bytes[Start + I];
3471 // Make sure the bytes would come from one input operand.
3472 if (unsigned(Base) % Bytes.size() + BytesPerElement > Bytes.size())
3474 } else if (unsigned(Base) != Elem - I)
3481 // Bytes is a VPERM-like permute vector, except that -1 is used for
3482 // undefined bytes. Return true if it can be performed using VSLDI.
3483 // When returning true, set StartIndex to the shift amount and OpNo0
3484 // and OpNo1 to the VPERM operands that should be used as the first
3485 // and second shift operand respectively.
3486 static bool isShlDoublePermute(const SmallVectorImpl<int> &Bytes,
3487 unsigned &StartIndex, unsigned &OpNo0,
3489 int OpNos[] = { -1, -1 };
3491 for (unsigned I = 0; I < 16; ++I) {
3492 int Index = Bytes[I];
3494 int ExpectedShift = (Index - I) % SystemZ::VectorBytes;
3495 int ModelOpNo = unsigned(ExpectedShift + I) / SystemZ::VectorBytes;
3496 int RealOpNo = unsigned(Index) / SystemZ::VectorBytes;
3498 Shift = ExpectedShift;
3499 else if (Shift != ExpectedShift)
3501 // Make sure that the operand mappings are consistent with previous
3503 if (OpNos[ModelOpNo] == 1 - RealOpNo)
3505 OpNos[ModelOpNo] = RealOpNo;
3509 return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
3512 // Create a node that performs P on operands Op0 and Op1, casting the
3513 // operands to the appropriate type. The type of the result is determined by P.
3514 static SDValue getPermuteNode(SelectionDAG &DAG, SDLoc DL,
3515 const Permute &P, SDValue Op0, SDValue Op1) {
3516 // VPDI (PERMUTE_DWORDS) always operates on v2i64s. The input
3517 // elements of a PACK are twice as wide as the outputs.
3518 unsigned InBytes = (P.Opcode == SystemZISD::PERMUTE_DWORDS ? 8 :
3519 P.Opcode == SystemZISD::PACK ? P.Operand * 2 :
3521 // Cast both operands to the appropriate type.
3522 MVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBytes * 8),
3523 SystemZ::VectorBytes / InBytes);
3524 Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0);
3525 Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1);
3527 if (P.Opcode == SystemZISD::PERMUTE_DWORDS) {
3528 SDValue Op2 = DAG.getConstant(P.Operand, DL, MVT::i32);
3529 Op = DAG.getNode(SystemZISD::PERMUTE_DWORDS, DL, InVT, Op0, Op1, Op2);
3530 } else if (P.Opcode == SystemZISD::PACK) {
3531 MVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(P.Operand * 8),
3532 SystemZ::VectorBytes / P.Operand);
3533 Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1);
3535 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1);
3540 // Bytes is a VPERM-like permute vector, except that -1 is used for
3541 // undefined bytes. Implement it on operands Ops[0] and Ops[1] using
3543 static SDValue getGeneralPermuteNode(SelectionDAG &DAG, SDLoc DL, SDValue *Ops,
3544 const SmallVectorImpl<int> &Bytes) {
3545 for (unsigned I = 0; I < 2; ++I)
3546 Ops[I] = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Ops[I]);
3548 // First see whether VSLDI can be used.
3549 unsigned StartIndex, OpNo0, OpNo1;
3550 if (isShlDoublePermute(Bytes, StartIndex, OpNo0, OpNo1))
3551 return DAG.getNode(SystemZISD::SHL_DOUBLE, DL, MVT::v16i8, Ops[OpNo0],
3552 Ops[OpNo1], DAG.getConstant(StartIndex, DL, MVT::i32));
3554 // Fall back on VPERM. Construct an SDNode for the permute vector.
3555 SDValue IndexNodes[SystemZ::VectorBytes];
3556 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
3558 IndexNodes[I] = DAG.getConstant(Bytes[I], DL, MVT::i32);
3560 IndexNodes[I] = DAG.getUNDEF(MVT::i32);
3561 SDValue Op2 = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, IndexNodes);
3562 return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Ops[0], Ops[1], Op2);
3566 // Describes a general N-operand vector shuffle.
3567 struct GeneralShuffle {
3568 GeneralShuffle(EVT vt) : VT(vt) {}
3570 void add(SDValue, unsigned);
3571 SDValue getNode(SelectionDAG &, SDLoc);
3573 // The operands of the shuffle.
3574 SmallVector<SDValue, SystemZ::VectorBytes> Ops;
3576 // Index I is -1 if byte I of the result is undefined. Otherwise the
3577 // result comes from byte Bytes[I] % SystemZ::VectorBytes of operand
3578 // Bytes[I] / SystemZ::VectorBytes.
3579 SmallVector<int, SystemZ::VectorBytes> Bytes;
3581 // The type of the shuffle result.
3586 // Add an extra undefined element to the shuffle.
3587 void GeneralShuffle::addUndef() {
3588 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3589 for (unsigned I = 0; I < BytesPerElement; ++I)
3590 Bytes.push_back(-1);
3593 // Add an extra element to the shuffle, taking it from element Elem of Op.
3594 // A null Op indicates a vector input whose value will be calculated later;
3595 // there is at most one such input per shuffle and it always has the same
3596 // type as the result.
3597 void GeneralShuffle::add(SDValue Op, unsigned Elem) {
3598 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3600 // The source vector can have wider elements than the result,
3601 // either through an explicit TRUNCATE or because of type legalization.
3602 // We want the least significant part.
3603 EVT FromVT = Op.getNode() ? Op.getValueType() : VT;
3604 unsigned FromBytesPerElement = FromVT.getVectorElementType().getStoreSize();
3605 assert(FromBytesPerElement >= BytesPerElement &&
3606 "Invalid EXTRACT_VECTOR_ELT");
3607 unsigned Byte = ((Elem * FromBytesPerElement) % SystemZ::VectorBytes +
3608 (FromBytesPerElement - BytesPerElement));
3610 // Look through things like shuffles and bitcasts.
3611 while (Op.getNode()) {
3612 if (Op.getOpcode() == ISD::BITCAST)
3613 Op = Op.getOperand(0);
3614 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) {
3615 // See whether the bytes we need come from a contiguous part of one
3617 SmallVector<int, SystemZ::VectorBytes> OpBytes;
3618 getVPermMask(cast<ShuffleVectorSDNode>(Op), OpBytes);
3620 if (!getShuffleInput(OpBytes, Byte, BytesPerElement, NewByte))
3626 Op = Op.getOperand(unsigned(NewByte) / SystemZ::VectorBytes);
3627 Byte = unsigned(NewByte) % SystemZ::VectorBytes;
3628 } else if (Op.getOpcode() == ISD::UNDEF) {
3635 // Make sure that the source of the extraction is in Ops.
3637 for (; OpNo < Ops.size(); ++OpNo)
3638 if (Ops[OpNo] == Op)
3640 if (OpNo == Ops.size())
3643 // Add the element to Bytes.
3644 unsigned Base = OpNo * SystemZ::VectorBytes + Byte;
3645 for (unsigned I = 0; I < BytesPerElement; ++I)
3646 Bytes.push_back(Base + I);
3649 // Return SDNodes for the completed shuffle.
3650 SDValue GeneralShuffle::getNode(SelectionDAG &DAG, SDLoc DL) {
3651 assert(Bytes.size() == SystemZ::VectorBytes && "Incomplete vector");
3653 if (Ops.size() == 0)
3654 return DAG.getUNDEF(VT);
3656 // Make sure that there are at least two shuffle operands.
3657 if (Ops.size() == 1)
3658 Ops.push_back(DAG.getUNDEF(MVT::v16i8));
3660 // Create a tree of shuffles, deferring root node until after the loop.
3661 // Try to redistribute the undefined elements of non-root nodes so that
3662 // the non-root shuffles match something like a pack or merge, then adjust
3663 // the parent node's permute vector to compensate for the new order.
3664 // Among other things, this copes with vectors like <2 x i16> that were
3665 // padded with undefined elements during type legalization.
3667 // In the best case this redistribution will lead to the whole tree
3668 // using packs and merges. It should rarely be a loss in other cases.
3669 unsigned Stride = 1;
3670 for (; Stride * 2 < Ops.size(); Stride *= 2) {
3671 for (unsigned I = 0; I < Ops.size() - Stride; I += Stride * 2) {
3672 SDValue SubOps[] = { Ops[I], Ops[I + Stride] };
3674 // Create a mask for just these two operands.
3675 SmallVector<int, SystemZ::VectorBytes> NewBytes(SystemZ::VectorBytes);
3676 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
3677 unsigned OpNo = unsigned(Bytes[J]) / SystemZ::VectorBytes;
3678 unsigned Byte = unsigned(Bytes[J]) % SystemZ::VectorBytes;
3681 else if (OpNo == I + Stride)
3682 NewBytes[J] = SystemZ::VectorBytes + Byte;
3686 // See if it would be better to reorganize NewMask to avoid using VPERM.
3687 SmallVector<int, SystemZ::VectorBytes> NewBytesMap(SystemZ::VectorBytes);
3688 if (const Permute *P = matchDoublePermute(NewBytes, NewBytesMap)) {
3689 Ops[I] = getPermuteNode(DAG, DL, *P, SubOps[0], SubOps[1]);
3690 // Applying NewBytesMap to Ops[I] gets back to NewBytes.
3691 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
3692 if (NewBytes[J] >= 0) {
3693 assert(unsigned(NewBytesMap[J]) < SystemZ::VectorBytes &&
3694 "Invalid double permute");
3695 Bytes[J] = I * SystemZ::VectorBytes + NewBytesMap[J];
3697 assert(NewBytesMap[J] < 0 && "Invalid double permute");
3700 // Just use NewBytes on the operands.
3701 Ops[I] = getGeneralPermuteNode(DAG, DL, SubOps, NewBytes);
3702 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J)
3703 if (NewBytes[J] >= 0)
3704 Bytes[J] = I * SystemZ::VectorBytes + J;
3709 // Now we just have 2 inputs. Put the second operand in Ops[1].
3711 Ops[1] = Ops[Stride];
3712 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
3713 if (Bytes[I] >= int(SystemZ::VectorBytes))
3714 Bytes[I] -= (Stride - 1) * SystemZ::VectorBytes;
3717 // Look for an instruction that can do the permute without resorting
3719 unsigned OpNo0, OpNo1;
3721 if (const Permute *P = matchPermute(Bytes, OpNo0, OpNo1))
3722 Op = getPermuteNode(DAG, DL, *P, Ops[OpNo0], Ops[OpNo1]);
3724 Op = getGeneralPermuteNode(DAG, DL, &Ops[0], Bytes);
3725 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3728 // Return true if the given BUILD_VECTOR is a scalar-to-vector conversion.
3729 static bool isScalarToVector(SDValue Op) {
3730 for (unsigned I = 1, E = Op.getNumOperands(); I != E; ++I)
3731 if (Op.getOperand(I).getOpcode() != ISD::UNDEF)
3736 // Return a vector of type VT that contains Value in the first element.
3737 // The other elements don't matter.
3738 static SDValue buildScalarToVector(SelectionDAG &DAG, SDLoc DL, EVT VT,
3740 // If we have a constant, replicate it to all elements and let the
3741 // BUILD_VECTOR lowering take care of it.
3742 if (Value.getOpcode() == ISD::Constant ||
3743 Value.getOpcode() == ISD::ConstantFP) {
3744 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Value);
3745 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
3747 if (Value.getOpcode() == ISD::UNDEF)
3748 return DAG.getUNDEF(VT);
3749 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
3752 // Return a vector of type VT in which Op0 is in element 0 and Op1 is in
3753 // element 1. Used for cases in which replication is cheap.
3754 static SDValue buildMergeScalars(SelectionDAG &DAG, SDLoc DL, EVT VT,
3755 SDValue Op0, SDValue Op1) {
3756 if (Op0.getOpcode() == ISD::UNDEF) {
3757 if (Op1.getOpcode() == ISD::UNDEF)
3758 return DAG.getUNDEF(VT);
3759 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op1);
3761 if (Op1.getOpcode() == ISD::UNDEF)
3762 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0);
3763 return DAG.getNode(SystemZISD::MERGE_HIGH, DL, VT,
3764 buildScalarToVector(DAG, DL, VT, Op0),
3765 buildScalarToVector(DAG, DL, VT, Op1));
3768 // Extend GPR scalars Op0 and Op1 to doublewords and return a v2i64
3770 static SDValue joinDwords(SelectionDAG &DAG, SDLoc DL, SDValue Op0,
3772 if (Op0.getOpcode() == ISD::UNDEF && Op1.getOpcode() == ISD::UNDEF)
3773 return DAG.getUNDEF(MVT::v2i64);
3774 // If one of the two inputs is undefined then replicate the other one,
3775 // in order to avoid using another register unnecessarily.
3776 if (Op0.getOpcode() == ISD::UNDEF)
3777 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
3778 else if (Op1.getOpcode() == ISD::UNDEF)
3779 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
3781 Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
3782 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
3784 return DAG.getNode(SystemZISD::JOIN_DWORDS, DL, MVT::v2i64, Op0, Op1);
3787 // Try to represent constant BUILD_VECTOR node BVN using a
3788 // SystemZISD::BYTE_MASK-style mask. Store the mask value in Mask
3790 static bool tryBuildVectorByteMask(BuildVectorSDNode *BVN, uint64_t &Mask) {
3791 EVT ElemVT = BVN->getValueType(0).getVectorElementType();
3792 unsigned BytesPerElement = ElemVT.getStoreSize();
3793 for (unsigned I = 0, E = BVN->getNumOperands(); I != E; ++I) {
3794 SDValue Op = BVN->getOperand(I);
3795 if (Op.getOpcode() != ISD::UNDEF) {
3797 if (Op.getOpcode() == ISD::Constant)
3798 Value = dyn_cast<ConstantSDNode>(Op)->getZExtValue();
3799 else if (Op.getOpcode() == ISD::ConstantFP)
3800 Value = (dyn_cast<ConstantFPSDNode>(Op)->getValueAPF().bitcastToAPInt()
3804 for (unsigned J = 0; J < BytesPerElement; ++J) {
3805 uint64_t Byte = (Value >> (J * 8)) & 0xff;
3807 Mask |= 1ULL << ((E - I - 1) * BytesPerElement + J);
3816 // Try to load a vector constant in which BitsPerElement-bit value Value
3817 // is replicated to fill the vector. VT is the type of the resulting
3818 // constant, which may have elements of a different size from BitsPerElement.
3819 // Return the SDValue of the constant on success, otherwise return
3821 static SDValue tryBuildVectorReplicate(SelectionDAG &DAG,
3822 const SystemZInstrInfo *TII,
3823 SDLoc DL, EVT VT, uint64_t Value,
3824 unsigned BitsPerElement) {
3825 // Signed 16-bit values can be replicated using VREPI.
3826 int64_t SignedValue = SignExtend64(Value, BitsPerElement);
3827 if (isInt<16>(SignedValue)) {
3828 MVT VecVT = MVT::getVectorVT(MVT::getIntegerVT(BitsPerElement),
3829 SystemZ::VectorBits / BitsPerElement);
3830 SDValue Op = DAG.getNode(SystemZISD::REPLICATE, DL, VecVT,
3831 DAG.getConstant(SignedValue, DL, MVT::i32));
3832 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3834 // See whether rotating the constant left some N places gives a value that
3835 // is one less than a power of 2 (i.e. all zeros followed by all ones).
3836 // If so we can use VGM.
3837 unsigned Start, End;
3838 if (TII->isRxSBGMask(Value, BitsPerElement, Start, End)) {
3839 // isRxSBGMask returns the bit numbers for a full 64-bit value,
3840 // with 0 denoting 1 << 63 and 63 denoting 1. Convert them to
3841 // bit numbers for an BitsPerElement value, so that 0 denotes
3842 // 1 << (BitsPerElement-1).
3843 Start -= 64 - BitsPerElement;
3844 End -= 64 - BitsPerElement;
3845 MVT VecVT = MVT::getVectorVT(MVT::getIntegerVT(BitsPerElement),
3846 SystemZ::VectorBits / BitsPerElement);
3847 SDValue Op = DAG.getNode(SystemZISD::ROTATE_MASK, DL, VecVT,
3848 DAG.getConstant(Start, DL, MVT::i32),
3849 DAG.getConstant(End, DL, MVT::i32));
3850 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3855 // If a BUILD_VECTOR contains some EXTRACT_VECTOR_ELTs, it's usually
3856 // better to use VECTOR_SHUFFLEs on them, only using BUILD_VECTOR for
3857 // the non-EXTRACT_VECTOR_ELT elements. See if the given BUILD_VECTOR
3858 // would benefit from this representation and return it if so.
3859 static SDValue tryBuildVectorShuffle(SelectionDAG &DAG,
3860 BuildVectorSDNode *BVN) {
3861 EVT VT = BVN->getValueType(0);
3862 unsigned NumElements = VT.getVectorNumElements();
3864 // Represent the BUILD_VECTOR as an N-operand VECTOR_SHUFFLE-like operation
3865 // on byte vectors. If there are non-EXTRACT_VECTOR_ELT elements that still
3866 // need a BUILD_VECTOR, add an additional placeholder operand for that
3867 // BUILD_VECTOR and store its operands in ResidueOps.
3868 GeneralShuffle GS(VT);
3869 SmallVector<SDValue, SystemZ::VectorBytes> ResidueOps;
3870 bool FoundOne = false;
3871 for (unsigned I = 0; I < NumElements; ++I) {
3872 SDValue Op = BVN->getOperand(I);
3873 if (Op.getOpcode() == ISD::TRUNCATE)
3874 Op = Op.getOperand(0);
3875 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
3876 Op.getOperand(1).getOpcode() == ISD::Constant) {
3877 unsigned Elem = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
3878 GS.add(Op.getOperand(0), Elem);
3880 } else if (Op.getOpcode() == ISD::UNDEF) {
3883 GS.add(SDValue(), ResidueOps.size());
3884 ResidueOps.push_back(Op);
3888 // Nothing to do if there are no EXTRACT_VECTOR_ELTs.
3892 // Create the BUILD_VECTOR for the remaining elements, if any.
3893 if (!ResidueOps.empty()) {
3894 while (ResidueOps.size() < NumElements)
3895 ResidueOps.push_back(DAG.getUNDEF(VT.getVectorElementType()));
3896 for (auto &Op : GS.Ops) {
3897 if (!Op.getNode()) {
3898 Op = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BVN), VT, ResidueOps);
3903 return GS.getNode(DAG, SDLoc(BVN));
3906 // Combine GPR scalar values Elems into a vector of type VT.
3907 static SDValue buildVector(SelectionDAG &DAG, SDLoc DL, EVT VT,
3908 SmallVectorImpl<SDValue> &Elems) {
3909 // See whether there is a single replicated value.
3911 unsigned int NumElements = Elems.size();
3912 unsigned int Count = 0;
3913 for (auto Elem : Elems) {
3914 if (Elem.getOpcode() != ISD::UNDEF) {
3915 if (!Single.getNode())
3917 else if (Elem != Single) {
3924 // There are three cases here:
3926 // - if the only defined element is a loaded one, the best sequence
3927 // is a replicating load.
3929 // - otherwise, if the only defined element is an i64 value, we will
3930 // end up with the same VLVGP sequence regardless of whether we short-cut
3931 // for replication or fall through to the later code.
3933 // - otherwise, if the only defined element is an i32 or smaller value,
3934 // we would need 2 instructions to replicate it: VLVGP followed by VREPx.
3935 // This is only a win if the single defined element is used more than once.
3936 // In other cases we're better off using a single VLVGx.
3937 if (Single.getNode() && (Count > 1 || Single.getOpcode() == ISD::LOAD))
3938 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Single);
3940 // The best way of building a v2i64 from two i64s is to use VLVGP.
3941 if (VT == MVT::v2i64)
3942 return joinDwords(DAG, DL, Elems[0], Elems[1]);
3944 // Use a 64-bit merge high to combine two doubles.
3945 if (VT == MVT::v2f64)
3946 return buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
3948 // Build v4f32 values directly from the FPRs:
3950 // <Axxx> <Bxxx> <Cxxxx> <Dxxx>
3955 if (VT == MVT::v4f32) {
3956 SDValue Op01 = buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
3957 SDValue Op23 = buildMergeScalars(DAG, DL, VT, Elems[2], Elems[3]);
3958 // Avoid unnecessary undefs by reusing the other operand.
3959 if (Op01.getOpcode() == ISD::UNDEF)
3961 else if (Op23.getOpcode() == ISD::UNDEF)
3963 // Merging identical replications is a no-op.
3964 if (Op01.getOpcode() == SystemZISD::REPLICATE && Op01 == Op23)
3966 Op01 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op01);
3967 Op23 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op23);
3968 SDValue Op = DAG.getNode(SystemZISD::MERGE_HIGH,
3969 DL, MVT::v2i64, Op01, Op23);
3970 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3973 // Collect the constant terms.
3974 SmallVector<SDValue, SystemZ::VectorBytes> Constants(NumElements, SDValue());
3975 SmallVector<bool, SystemZ::VectorBytes> Done(NumElements, false);
3977 unsigned NumConstants = 0;
3978 for (unsigned I = 0; I < NumElements; ++I) {
3979 SDValue Elem = Elems[I];
3980 if (Elem.getOpcode() == ISD::Constant ||
3981 Elem.getOpcode() == ISD::ConstantFP) {
3983 Constants[I] = Elem;
3987 // If there was at least one constant, fill in the other elements of
3988 // Constants with undefs to get a full vector constant and use that
3989 // as the starting point.
3991 if (NumConstants > 0) {
3992 for (unsigned I = 0; I < NumElements; ++I)
3993 if (!Constants[I].getNode())
3994 Constants[I] = DAG.getUNDEF(Elems[I].getValueType());
3995 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Constants);
3997 // Otherwise try to use VLVGP to start the sequence in order to
3998 // avoid a false dependency on any previous contents of the vector
3999 // register. This only makes sense if one of the associated elements
4001 unsigned I1 = NumElements / 2 - 1;
4002 unsigned I2 = NumElements - 1;
4003 bool Def1 = (Elems[I1].getOpcode() != ISD::UNDEF);
4004 bool Def2 = (Elems[I2].getOpcode() != ISD::UNDEF);
4006 SDValue Elem1 = Elems[Def1 ? I1 : I2];
4007 SDValue Elem2 = Elems[Def2 ? I2 : I1];
4008 Result = DAG.getNode(ISD::BITCAST, DL, VT,
4009 joinDwords(DAG, DL, Elem1, Elem2));
4013 Result = DAG.getUNDEF(VT);
4016 // Use VLVGx to insert the other elements.
4017 for (unsigned I = 0; I < NumElements; ++I)
4018 if (!Done[I] && Elems[I].getOpcode() != ISD::UNDEF)
4019 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I],
4020 DAG.getConstant(I, DL, MVT::i32));
4024 SDValue SystemZTargetLowering::lowerBUILD_VECTOR(SDValue Op,
4025 SelectionDAG &DAG) const {
4026 const SystemZInstrInfo *TII =
4027 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4028 auto *BVN = cast<BuildVectorSDNode>(Op.getNode());
4030 EVT VT = Op.getValueType();
4032 if (BVN->isConstant()) {
4033 // Try using VECTOR GENERATE BYTE MASK. This is the architecturally-
4034 // preferred way of creating all-zero and all-one vectors so give it
4035 // priority over other methods below.
4037 if (tryBuildVectorByteMask(BVN, Mask)) {
4038 SDValue Op = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
4039 DAG.getConstant(Mask, DL, MVT::i32));
4040 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4043 // Try using some form of replication.
4044 APInt SplatBits, SplatUndef;
4045 unsigned SplatBitSize;
4047 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4049 SplatBitSize <= 64) {
4050 // First try assuming that any undefined bits above the highest set bit
4051 // and below the lowest set bit are 1s. This increases the likelihood of
4052 // being able to use a sign-extended element value in VECTOR REPLICATE
4053 // IMMEDIATE or a wraparound mask in VECTOR GENERATE MASK.
4054 uint64_t SplatBitsZ = SplatBits.getZExtValue();
4055 uint64_t SplatUndefZ = SplatUndef.getZExtValue();
4056 uint64_t Lower = (SplatUndefZ
4057 & ((uint64_t(1) << findFirstSet(SplatBitsZ)) - 1));
4058 uint64_t Upper = (SplatUndefZ
4059 & ~((uint64_t(1) << findLastSet(SplatBitsZ)) - 1));
4060 uint64_t Value = SplatBitsZ | Upper | Lower;
4061 SDValue Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value,
4066 // Now try assuming that any undefined bits between the first and
4067 // last defined set bits are set. This increases the chances of
4068 // using a non-wraparound mask.
4069 uint64_t Middle = SplatUndefZ & ~Upper & ~Lower;
4070 Value = SplatBitsZ | Middle;
4071 Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value, SplatBitSize);
4076 // Fall back to loading it from memory.
4080 // See if we should use shuffles to construct the vector from other vectors.
4081 SDValue Res = tryBuildVectorShuffle(DAG, BVN);
4085 // Detect SCALAR_TO_VECTOR conversions.
4086 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op))
4087 return buildScalarToVector(DAG, DL, VT, Op.getOperand(0));
4089 // Otherwise use buildVector to build the vector up from GPRs.
4090 unsigned NumElements = Op.getNumOperands();
4091 SmallVector<SDValue, SystemZ::VectorBytes> Ops(NumElements);
4092 for (unsigned I = 0; I < NumElements; ++I)
4093 Ops[I] = Op.getOperand(I);
4094 return buildVector(DAG, DL, VT, Ops);
4097 SDValue SystemZTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
4098 SelectionDAG &DAG) const {
4099 auto *VSN = cast<ShuffleVectorSDNode>(Op.getNode());
4101 EVT VT = Op.getValueType();
4102 unsigned NumElements = VT.getVectorNumElements();
4104 if (VSN->isSplat()) {
4105 SDValue Op0 = Op.getOperand(0);
4106 unsigned Index = VSN->getSplatIndex();
4107 assert(Index < VT.getVectorNumElements() &&
4108 "Splat index should be defined and in first operand");
4109 // See whether the value we're splatting is directly available as a scalar.
4110 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4111 Op0.getOpcode() == ISD::BUILD_VECTOR)
4112 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0.getOperand(Index));
4113 // Otherwise keep it as a vector-to-vector operation.
4114 return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0),
4115 DAG.getConstant(Index, DL, MVT::i32));
4118 GeneralShuffle GS(VT);
4119 for (unsigned I = 0; I < NumElements; ++I) {
4120 int Elt = VSN->getMaskElt(I);
4124 GS.add(Op.getOperand(unsigned(Elt) / NumElements),
4125 unsigned(Elt) % NumElements);
4127 return GS.getNode(DAG, SDLoc(VSN));
4130 SDValue SystemZTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
4131 SelectionDAG &DAG) const {
4133 // Just insert the scalar into element 0 of an undefined vector.
4134 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL,
4135 Op.getValueType(), DAG.getUNDEF(Op.getValueType()),
4136 Op.getOperand(0), DAG.getConstant(0, DL, MVT::i32));
4139 SDValue SystemZTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
4140 SelectionDAG &DAG) const {
4141 // Handle insertions of floating-point values.
4143 SDValue Op0 = Op.getOperand(0);
4144 SDValue Op1 = Op.getOperand(1);
4145 SDValue Op2 = Op.getOperand(2);
4146 EVT VT = Op.getValueType();
4148 // Insertions into constant indices of a v2f64 can be done using VPDI.
4149 // However, if the inserted value is a bitcast or a constant then it's
4150 // better to use GPRs, as below.
4151 if (VT == MVT::v2f64 &&
4152 Op1.getOpcode() != ISD::BITCAST &&
4153 Op1.getOpcode() != ISD::ConstantFP &&
4154 Op2.getOpcode() == ISD::Constant) {
4155 uint64_t Index = dyn_cast<ConstantSDNode>(Op2)->getZExtValue();
4156 unsigned Mask = VT.getVectorNumElements() - 1;
4161 // Otherwise bitcast to the equivalent integer form and insert via a GPR.
4162 MVT IntVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
4163 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements());
4164 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT,
4165 DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0),
4166 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2);
4167 return DAG.getNode(ISD::BITCAST, DL, VT, Res);
4171 SystemZTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
4172 SelectionDAG &DAG) const {
4173 // Handle extractions of floating-point values.
4175 SDValue Op0 = Op.getOperand(0);
4176 SDValue Op1 = Op.getOperand(1);
4177 EVT VT = Op.getValueType();
4178 EVT VecVT = Op0.getValueType();
4180 // Extractions of constant indices can be done directly.
4181 if (auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {
4182 uint64_t Index = CIndexN->getZExtValue();
4183 unsigned Mask = VecVT.getVectorNumElements() - 1;
4188 // Otherwise bitcast to the equivalent integer form and extract via a GPR.
4189 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
4190 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements());
4191 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT,
4192 DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0), Op1);
4193 return DAG.getNode(ISD::BITCAST, DL, VT, Res);
4197 SystemZTargetLowering::lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
4198 unsigned UnpackHigh) const {
4199 SDValue PackedOp = Op.getOperand(0);
4200 EVT OutVT = Op.getValueType();
4201 EVT InVT = PackedOp.getValueType();
4202 unsigned ToBits = OutVT.getVectorElementType().getSizeInBits();
4203 unsigned FromBits = InVT.getVectorElementType().getSizeInBits();
4206 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits),
4207 SystemZ::VectorBits / FromBits);
4208 PackedOp = DAG.getNode(UnpackHigh, SDLoc(PackedOp), OutVT, PackedOp);
4209 } while (FromBits != ToBits);
4213 SDValue SystemZTargetLowering::lowerShift(SDValue Op, SelectionDAG &DAG,
4214 unsigned ByScalar) const {
4215 // Look for cases where a vector shift can use the *_BY_SCALAR form.
4216 SDValue Op0 = Op.getOperand(0);
4217 SDValue Op1 = Op.getOperand(1);
4219 EVT VT = Op.getValueType();
4220 unsigned ElemBitSize = VT.getVectorElementType().getSizeInBits();
4222 // See whether the shift vector is a splat represented as BUILD_VECTOR.
4223 if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op1)) {
4224 APInt SplatBits, SplatUndef;
4225 unsigned SplatBitSize;
4227 // Check for constant splats. Use ElemBitSize as the minimum element
4228 // width and reject splats that need wider elements.
4229 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4230 ElemBitSize, true) &&
4231 SplatBitSize == ElemBitSize) {
4232 SDValue Shift = DAG.getConstant(SplatBits.getZExtValue() & 0xfff,
4234 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4236 // Check for variable splats.
4237 BitVector UndefElements;
4238 SDValue Splat = BVN->getSplatValue(&UndefElements);
4240 // Since i32 is the smallest legal type, we either need a no-op
4242 SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Splat);
4243 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4247 // See whether the shift vector is a splat represented as SHUFFLE_VECTOR,
4248 // and the shift amount is directly available in a GPR.
4249 if (auto *VSN = dyn_cast<ShuffleVectorSDNode>(Op1)) {
4250 if (VSN->isSplat()) {
4251 SDValue VSNOp0 = VSN->getOperand(0);
4252 unsigned Index = VSN->getSplatIndex();
4253 assert(Index < VT.getVectorNumElements() &&
4254 "Splat index should be defined and in first operand");
4255 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4256 VSNOp0.getOpcode() == ISD::BUILD_VECTOR) {
4257 // Since i32 is the smallest legal type, we either need a no-op
4259 SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32,
4260 VSNOp0.getOperand(Index));
4261 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4266 // Otherwise just treat the current form as legal.
4270 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
4271 SelectionDAG &DAG) const {
4272 switch (Op.getOpcode()) {
4274 return lowerBR_CC(Op, DAG);
4275 case ISD::SELECT_CC:
4276 return lowerSELECT_CC(Op, DAG);
4278 return lowerSETCC(Op, DAG);
4279 case ISD::GlobalAddress:
4280 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
4281 case ISD::GlobalTLSAddress:
4282 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
4283 case ISD::BlockAddress:
4284 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
4285 case ISD::JumpTable:
4286 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
4287 case ISD::ConstantPool:
4288 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
4290 return lowerBITCAST(Op, DAG);
4292 return lowerVASTART(Op, DAG);
4294 return lowerVACOPY(Op, DAG);
4295 case ISD::DYNAMIC_STACKALLOC:
4296 return lowerDYNAMIC_STACKALLOC(Op, DAG);
4297 case ISD::SMUL_LOHI:
4298 return lowerSMUL_LOHI(Op, DAG);
4299 case ISD::UMUL_LOHI:
4300 return lowerUMUL_LOHI(Op, DAG);
4302 return lowerSDIVREM(Op, DAG);
4304 return lowerUDIVREM(Op, DAG);
4306 return lowerOR(Op, DAG);
4308 return lowerCTPOP(Op, DAG);
4309 case ISD::CTLZ_ZERO_UNDEF:
4310 return DAG.getNode(ISD::CTLZ, SDLoc(Op),
4311 Op.getValueType(), Op.getOperand(0));
4312 case ISD::CTTZ_ZERO_UNDEF:
4313 return DAG.getNode(ISD::CTTZ, SDLoc(Op),
4314 Op.getValueType(), Op.getOperand(0));
4315 case ISD::ATOMIC_SWAP:
4316 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
4317 case ISD::ATOMIC_STORE:
4318 return lowerATOMIC_STORE(Op, DAG);
4319 case ISD::ATOMIC_LOAD:
4320 return lowerATOMIC_LOAD(Op, DAG);
4321 case ISD::ATOMIC_LOAD_ADD:
4322 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
4323 case ISD::ATOMIC_LOAD_SUB:
4324 return lowerATOMIC_LOAD_SUB(Op, DAG);
4325 case ISD::ATOMIC_LOAD_AND:
4326 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
4327 case ISD::ATOMIC_LOAD_OR:
4328 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
4329 case ISD::ATOMIC_LOAD_XOR:
4330 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
4331 case ISD::ATOMIC_LOAD_NAND:
4332 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
4333 case ISD::ATOMIC_LOAD_MIN:
4334 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
4335 case ISD::ATOMIC_LOAD_MAX:
4336 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
4337 case ISD::ATOMIC_LOAD_UMIN:
4338 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
4339 case ISD::ATOMIC_LOAD_UMAX:
4340 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
4341 case ISD::ATOMIC_CMP_SWAP:
4342 return lowerATOMIC_CMP_SWAP(Op, DAG);
4343 case ISD::STACKSAVE:
4344 return lowerSTACKSAVE(Op, DAG);
4345 case ISD::STACKRESTORE:
4346 return lowerSTACKRESTORE(Op, DAG);
4348 return lowerPREFETCH(Op, DAG);
4349 case ISD::INTRINSIC_W_CHAIN:
4350 return lowerINTRINSIC_W_CHAIN(Op, DAG);
4351 case ISD::INTRINSIC_WO_CHAIN:
4352 return lowerINTRINSIC_WO_CHAIN(Op, DAG);
4353 case ISD::BUILD_VECTOR:
4354 return lowerBUILD_VECTOR(Op, DAG);
4355 case ISD::VECTOR_SHUFFLE:
4356 return lowerVECTOR_SHUFFLE(Op, DAG);
4357 case ISD::SCALAR_TO_VECTOR:
4358 return lowerSCALAR_TO_VECTOR(Op, DAG);
4359 case ISD::INSERT_VECTOR_ELT:
4360 return lowerINSERT_VECTOR_ELT(Op, DAG);
4361 case ISD::EXTRACT_VECTOR_ELT:
4362 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
4363 case ISD::SIGN_EXTEND_VECTOR_INREG:
4364 return lowerExtendVectorInreg(Op, DAG, SystemZISD::UNPACK_HIGH);
4365 case ISD::ZERO_EXTEND_VECTOR_INREG:
4366 return lowerExtendVectorInreg(Op, DAG, SystemZISD::UNPACKL_HIGH);
4368 return lowerShift(Op, DAG, SystemZISD::VSHL_BY_SCALAR);
4370 return lowerShift(Op, DAG, SystemZISD::VSRL_BY_SCALAR);
4372 return lowerShift(Op, DAG, SystemZISD::VSRA_BY_SCALAR);
4374 llvm_unreachable("Unexpected node to lower");
4378 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
4379 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
4380 switch ((SystemZISD::NodeType)Opcode) {
4381 case SystemZISD::FIRST_NUMBER: break;
4387 OPCODE(PCREL_WRAPPER);
4388 OPCODE(PCREL_OFFSET);
4394 OPCODE(SELECT_CCMASK);
4395 OPCODE(ADJDYNALLOC);
4396 OPCODE(EXTRACT_ACCESS);
4398 OPCODE(UMUL_LOHI64);
4415 OPCODE(SEARCH_STRING);
4419 OPCODE(TBEGIN_NOFLOAT);
4422 OPCODE(ROTATE_MASK);
4424 OPCODE(JOIN_DWORDS);
4429 OPCODE(PERMUTE_DWORDS);
4434 OPCODE(UNPACK_HIGH);
4435 OPCODE(UNPACKL_HIGH);
4437 OPCODE(UNPACKL_LOW);
4438 OPCODE(VSHL_BY_SCALAR);
4439 OPCODE(VSRL_BY_SCALAR);
4440 OPCODE(VSRA_BY_SCALAR);
4467 OPCODE(ATOMIC_SWAPW);
4468 OPCODE(ATOMIC_LOADW_ADD);
4469 OPCODE(ATOMIC_LOADW_SUB);
4470 OPCODE(ATOMIC_LOADW_AND);
4471 OPCODE(ATOMIC_LOADW_OR);
4472 OPCODE(ATOMIC_LOADW_XOR);
4473 OPCODE(ATOMIC_LOADW_NAND);
4474 OPCODE(ATOMIC_LOADW_MIN);
4475 OPCODE(ATOMIC_LOADW_MAX);
4476 OPCODE(ATOMIC_LOADW_UMIN);
4477 OPCODE(ATOMIC_LOADW_UMAX);
4478 OPCODE(ATOMIC_CMP_SWAPW);
4485 // Return true if VT is a vector whose elements are a whole number of bytes
4487 static bool canTreatAsByteVector(EVT VT) {
4488 return VT.isVector() && VT.getVectorElementType().getSizeInBits() % 8 == 0;
4491 // Try to simplify an EXTRACT_VECTOR_ELT from a vector of type VecVT
4492 // producing a result of type ResVT. Op is a possibly bitcast version
4493 // of the input vector and Index is the index (based on type VecVT) that
4494 // should be extracted. Return the new extraction if a simplification
4495 // was possible or if Force is true.
4496 SDValue SystemZTargetLowering::combineExtract(SDLoc DL, EVT ResVT, EVT VecVT,
4497 SDValue Op, unsigned Index,
4498 DAGCombinerInfo &DCI,
4500 SelectionDAG &DAG = DCI.DAG;
4502 // The number of bytes being extracted.
4503 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
4506 unsigned Opcode = Op.getOpcode();
4507 if (Opcode == ISD::BITCAST)
4508 // Look through bitcasts.
4509 Op = Op.getOperand(0);
4510 else if (Opcode == ISD::VECTOR_SHUFFLE &&
4511 canTreatAsByteVector(Op.getValueType())) {
4512 // Get a VPERM-like permute mask and see whether the bytes covered
4513 // by the extracted element are a contiguous sequence from one
4515 SmallVector<int, SystemZ::VectorBytes> Bytes;
4516 getVPermMask(cast<ShuffleVectorSDNode>(Op), Bytes);
4518 if (!getShuffleInput(Bytes, Index * BytesPerElement,
4519 BytesPerElement, First))
4522 return DAG.getUNDEF(ResVT);
4523 // Make sure the contiguous sequence starts at a multiple of the
4524 // original element size.
4525 unsigned Byte = unsigned(First) % Bytes.size();
4526 if (Byte % BytesPerElement != 0)
4528 // We can get the extracted value directly from an input.
4529 Index = Byte / BytesPerElement;
4530 Op = Op.getOperand(unsigned(First) / Bytes.size());
4532 } else if (Opcode == ISD::BUILD_VECTOR &&
4533 canTreatAsByteVector(Op.getValueType())) {
4534 // We can only optimize this case if the BUILD_VECTOR elements are
4535 // at least as wide as the extracted value.
4536 EVT OpVT = Op.getValueType();
4537 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
4538 if (OpBytesPerElement < BytesPerElement)
4540 // Make sure that the least-significant bit of the extracted value
4541 // is the least significant bit of an input.
4542 unsigned End = (Index + 1) * BytesPerElement;
4543 if (End % OpBytesPerElement != 0)
4545 // We're extracting the low part of one operand of the BUILD_VECTOR.
4546 Op = Op.getOperand(End / OpBytesPerElement - 1);
4547 if (!Op.getValueType().isInteger()) {
4548 EVT VT = MVT::getIntegerVT(Op.getValueType().getSizeInBits());
4549 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
4550 DCI.AddToWorklist(Op.getNode());
4552 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits());
4553 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
4555 DCI.AddToWorklist(Op.getNode());
4556 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op);
4559 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
4560 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
4561 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&
4562 canTreatAsByteVector(Op.getValueType()) &&
4563 canTreatAsByteVector(Op.getOperand(0).getValueType())) {
4564 // Make sure that only the unextended bits are significant.
4565 EVT ExtVT = Op.getValueType();
4566 EVT OpVT = Op.getOperand(0).getValueType();
4567 unsigned ExtBytesPerElement = ExtVT.getVectorElementType().getStoreSize();
4568 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
4569 unsigned Byte = Index * BytesPerElement;
4570 unsigned SubByte = Byte % ExtBytesPerElement;
4571 unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement;
4572 if (SubByte < MinSubByte ||
4573 SubByte + BytesPerElement > ExtBytesPerElement)
4575 // Get the byte offset of the unextended element
4576 Byte = Byte / ExtBytesPerElement * OpBytesPerElement;
4577 // ...then add the byte offset relative to that element.
4578 Byte += SubByte - MinSubByte;
4579 if (Byte % BytesPerElement != 0)
4581 Op = Op.getOperand(0);
4582 Index = Byte / BytesPerElement;
4588 if (Op.getValueType() != VecVT) {
4589 Op = DAG.getNode(ISD::BITCAST, DL, VecVT, Op);
4590 DCI.AddToWorklist(Op.getNode());
4592 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op,
4593 DAG.getConstant(Index, DL, MVT::i32));
4598 // Optimize vector operations in scalar value Op on the basis that Op
4599 // is truncated to TruncVT.
4601 SystemZTargetLowering::combineTruncateExtract(SDLoc DL, EVT TruncVT, SDValue Op,
4602 DAGCombinerInfo &DCI) const {
4603 // If we have (trunc (extract_vector_elt X, Y)), try to turn it into
4604 // (extract_vector_elt (bitcast X), Y'), where (bitcast X) has elements
4606 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4607 TruncVT.getSizeInBits() % 8 == 0) {
4608 SDValue Vec = Op.getOperand(0);
4609 EVT VecVT = Vec.getValueType();
4610 if (canTreatAsByteVector(VecVT)) {
4611 if (auto *IndexN = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
4612 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
4613 unsigned TruncBytes = TruncVT.getStoreSize();
4614 if (BytesPerElement % TruncBytes == 0) {
4615 // Calculate the value of Y' in the above description. We are
4616 // splitting the original elements into Scale equal-sized pieces
4617 // and for truncation purposes want the last (least-significant)
4618 // of these pieces for IndexN. This is easiest to do by calculating
4619 // the start index of the following element and then subtracting 1.
4620 unsigned Scale = BytesPerElement / TruncBytes;
4621 unsigned NewIndex = (IndexN->getZExtValue() + 1) * Scale - 1;
4623 // Defer the creation of the bitcast from X to combineExtract,
4624 // which might be able to optimize the extraction.
4625 VecVT = MVT::getVectorVT(MVT::getIntegerVT(TruncBytes * 8),
4626 VecVT.getStoreSize() / TruncBytes);
4627 EVT ResVT = (TruncBytes < 4 ? MVT::i32 : TruncVT);
4628 return combineExtract(DL, ResVT, VecVT, Vec, NewIndex, DCI, true);
4636 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
4637 DAGCombinerInfo &DCI) const {
4638 SelectionDAG &DAG = DCI.DAG;
4639 unsigned Opcode = N->getOpcode();
4640 if (Opcode == ISD::SIGN_EXTEND) {
4641 // Convert (sext (ashr (shl X, C1), C2)) to
4642 // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
4643 // cheap as narrower ones.
4644 SDValue N0 = N->getOperand(0);
4645 EVT VT = N->getValueType(0);
4646 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
4647 auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4648 SDValue Inner = N0.getOperand(0);
4649 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
4650 if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
4651 unsigned Extra = (VT.getSizeInBits() -
4652 N0.getValueType().getSizeInBits());
4653 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
4654 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
4655 EVT ShiftVT = N0.getOperand(1).getValueType();
4656 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
4657 Inner.getOperand(0));
4658 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
4659 DAG.getConstant(NewShlAmt, SDLoc(Inner),
4661 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
4662 DAG.getConstant(NewSraAmt, SDLoc(N0), ShiftVT));
4667 if (Opcode == SystemZISD::MERGE_HIGH ||
4668 Opcode == SystemZISD::MERGE_LOW) {
4669 SDValue Op0 = N->getOperand(0);
4670 SDValue Op1 = N->getOperand(1);
4671 if (Op0.getOpcode() == ISD::BITCAST)
4672 Op0 = Op0.getOperand(0);
4673 if (Op0.getOpcode() == SystemZISD::BYTE_MASK &&
4674 cast<ConstantSDNode>(Op0.getOperand(0))->getZExtValue() == 0) {
4675 // (z_merge_* 0, 0) -> 0. This is mostly useful for using VLLEZF
4677 if (Op1 == N->getOperand(0))
4679 // (z_merge_? 0, X) -> (z_unpackl_? 0, X).
4680 EVT VT = Op1.getValueType();
4681 unsigned ElemBytes = VT.getVectorElementType().getStoreSize();
4682 if (ElemBytes <= 4) {
4683 Opcode = (Opcode == SystemZISD::MERGE_HIGH ?
4684 SystemZISD::UNPACKL_HIGH : SystemZISD::UNPACKL_LOW);
4685 EVT InVT = VT.changeVectorElementTypeToInteger();
4686 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(ElemBytes * 16),
4687 SystemZ::VectorBytes / ElemBytes / 2);
4689 Op1 = DAG.getNode(ISD::BITCAST, SDLoc(N), InVT, Op1);
4690 DCI.AddToWorklist(Op1.getNode());
4692 SDValue Op = DAG.getNode(Opcode, SDLoc(N), OutVT, Op1);
4693 DCI.AddToWorklist(Op.getNode());
4694 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
4698 // If we have (truncstoreiN (extract_vector_elt X, Y), Z) then it is better
4699 // for the extraction to be done on a vMiN value, so that we can use VSTE.
4700 // If X has wider elements then convert it to:
4701 // (truncstoreiN (extract_vector_elt (bitcast X), Y2), Z).
4702 if (Opcode == ISD::STORE) {
4703 auto *SN = cast<StoreSDNode>(N);
4704 EVT MemVT = SN->getMemoryVT();
4705 if (MemVT.isInteger()) {
4706 SDValue Value = combineTruncateExtract(SDLoc(N), MemVT,
4707 SN->getValue(), DCI);
4708 if (Value.getNode()) {
4709 DCI.AddToWorklist(Value.getNode());
4711 // Rewrite the store with the new form of stored value.
4712 return DAG.getTruncStore(SN->getChain(), SDLoc(SN), Value,
4713 SN->getBasePtr(), SN->getMemoryVT(),
4714 SN->getMemOperand());
4718 // Try to simplify a vector extraction.
4719 if (Opcode == ISD::EXTRACT_VECTOR_ELT) {
4720 if (auto *IndexN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
4721 SDValue Op0 = N->getOperand(0);
4722 EVT VecVT = Op0.getValueType();
4723 return combineExtract(SDLoc(N), N->getValueType(0), VecVT, Op0,
4724 IndexN->getZExtValue(), DCI, false);
4727 // (join_dwords X, X) == (replicate X)
4728 if (Opcode == SystemZISD::JOIN_DWORDS &&
4729 N->getOperand(0) == N->getOperand(1))
4730 return DAG.getNode(SystemZISD::REPLICATE, SDLoc(N), N->getValueType(0),
4732 // (fround (extract_vector_elt X 0))
4733 // (fround (extract_vector_elt X 1)) ->
4734 // (extract_vector_elt (VROUND X) 0)
4735 // (extract_vector_elt (VROUND X) 1)
4737 // This is a special case since the target doesn't really support v2f32s.
4738 if (Opcode == ISD::FP_ROUND) {
4739 SDValue Op0 = N->getOperand(0);
4740 if (N->getValueType(0) == MVT::f32 &&
4742 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4743 Op0.getOperand(0).getValueType() == MVT::v2f64 &&
4744 Op0.getOperand(1).getOpcode() == ISD::Constant &&
4745 cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue() == 0) {
4746 SDValue Vec = Op0.getOperand(0);
4747 for (auto *U : Vec->uses()) {
4748 if (U != Op0.getNode() &&
4750 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4751 U->getOperand(0) == Vec &&
4752 U->getOperand(1).getOpcode() == ISD::Constant &&
4753 cast<ConstantSDNode>(U->getOperand(1))->getZExtValue() == 1) {
4754 SDValue OtherRound = SDValue(*U->use_begin(), 0);
4755 if (OtherRound.getOpcode() == ISD::FP_ROUND &&
4756 OtherRound.getOperand(0) == SDValue(U, 0) &&
4757 OtherRound.getValueType() == MVT::f32) {
4758 SDValue VRound = DAG.getNode(SystemZISD::VROUND, SDLoc(N),
4760 DCI.AddToWorklist(VRound.getNode());
4762 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(U), MVT::f32,
4763 VRound, DAG.getConstant(2, SDLoc(U), MVT::i32));
4764 DCI.AddToWorklist(Extract1.getNode());
4765 DAG.ReplaceAllUsesOfValueWith(OtherRound, Extract1);
4767 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op0), MVT::f32,
4768 VRound, DAG.getConstant(0, SDLoc(Op0), MVT::i32));
4778 //===----------------------------------------------------------------------===//
4780 //===----------------------------------------------------------------------===//
4782 // Create a new basic block after MBB.
4783 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
4784 MachineFunction &MF = *MBB->getParent();
4785 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
4786 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
4790 // Split MBB after MI and return the new block (the one that contains
4791 // instructions after MI).
4792 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
4793 MachineBasicBlock *MBB) {
4794 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
4795 NewMBB->splice(NewMBB->begin(), MBB,
4796 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
4797 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
4801 // Split MBB before MI and return the new block (the one that contains MI).
4802 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI,
4803 MachineBasicBlock *MBB) {
4804 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
4805 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
4806 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
4810 // Force base value Base into a register before MI. Return the register.
4811 static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
4812 const SystemZInstrInfo *TII) {
4814 return Base.getReg();
4816 MachineBasicBlock *MBB = MI->getParent();
4817 MachineFunction &MF = *MBB->getParent();
4818 MachineRegisterInfo &MRI = MF.getRegInfo();
4820 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
4821 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
4822 .addOperand(Base).addImm(0).addReg(0);
4826 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
4828 SystemZTargetLowering::emitSelect(MachineInstr *MI,
4829 MachineBasicBlock *MBB) const {
4830 const SystemZInstrInfo *TII =
4831 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4833 unsigned DestReg = MI->getOperand(0).getReg();
4834 unsigned TrueReg = MI->getOperand(1).getReg();
4835 unsigned FalseReg = MI->getOperand(2).getReg();
4836 unsigned CCValid = MI->getOperand(3).getImm();
4837 unsigned CCMask = MI->getOperand(4).getImm();
4838 DebugLoc DL = MI->getDebugLoc();
4840 MachineBasicBlock *StartMBB = MBB;
4841 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
4842 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
4845 // BRC CCMask, JoinMBB
4846 // # fallthrough to FalseMBB
4848 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
4849 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
4850 MBB->addSuccessor(JoinMBB);
4851 MBB->addSuccessor(FalseMBB);
4854 // # fallthrough to JoinMBB
4856 MBB->addSuccessor(JoinMBB);
4859 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
4862 BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
4863 .addReg(TrueReg).addMBB(StartMBB)
4864 .addReg(FalseReg).addMBB(FalseMBB);
4866 MI->eraseFromParent();
4870 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
4871 // StoreOpcode is the store to use and Invert says whether the store should
4872 // happen when the condition is false rather than true. If a STORE ON
4873 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
4875 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
4876 MachineBasicBlock *MBB,
4877 unsigned StoreOpcode, unsigned STOCOpcode,
4878 bool Invert) const {
4879 const SystemZInstrInfo *TII =
4880 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4882 unsigned SrcReg = MI->getOperand(0).getReg();
4883 MachineOperand Base = MI->getOperand(1);
4884 int64_t Disp = MI->getOperand(2).getImm();
4885 unsigned IndexReg = MI->getOperand(3).getReg();
4886 unsigned CCValid = MI->getOperand(4).getImm();
4887 unsigned CCMask = MI->getOperand(5).getImm();
4888 DebugLoc DL = MI->getDebugLoc();
4890 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
4892 // Use STOCOpcode if possible. We could use different store patterns in
4893 // order to avoid matching the index register, but the performance trade-offs
4894 // might be more complicated in that case.
4895 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
4898 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
4899 .addReg(SrcReg).addOperand(Base).addImm(Disp)
4900 .addImm(CCValid).addImm(CCMask);
4901 MI->eraseFromParent();
4905 // Get the condition needed to branch around the store.
4909 MachineBasicBlock *StartMBB = MBB;
4910 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
4911 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
4914 // BRC CCMask, JoinMBB
4915 // # fallthrough to FalseMBB
4917 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
4918 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
4919 MBB->addSuccessor(JoinMBB);
4920 MBB->addSuccessor(FalseMBB);
4923 // store %SrcReg, %Disp(%Index,%Base)
4924 // # fallthrough to JoinMBB
4926 BuildMI(MBB, DL, TII->get(StoreOpcode))
4927 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
4928 MBB->addSuccessor(JoinMBB);
4930 MI->eraseFromParent();
4934 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
4935 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
4936 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
4937 // BitSize is the width of the field in bits, or 0 if this is a partword
4938 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
4939 // is one of the operands. Invert says whether the field should be
4940 // inverted after performing BinOpcode (e.g. for NAND).
4942 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
4943 MachineBasicBlock *MBB,
4946 bool Invert) const {
4947 MachineFunction &MF = *MBB->getParent();
4948 const SystemZInstrInfo *TII =
4949 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4950 MachineRegisterInfo &MRI = MF.getRegInfo();
4951 bool IsSubWord = (BitSize < 32);
4953 // Extract the operands. Base can be a register or a frame index.
4954 // Src2 can be a register or immediate.
4955 unsigned Dest = MI->getOperand(0).getReg();
4956 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
4957 int64_t Disp = MI->getOperand(2).getImm();
4958 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
4959 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
4960 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
4961 DebugLoc DL = MI->getDebugLoc();
4963 BitSize = MI->getOperand(6).getImm();
4965 // Subword operations use 32-bit registers.
4966 const TargetRegisterClass *RC = (BitSize <= 32 ?
4967 &SystemZ::GR32BitRegClass :
4968 &SystemZ::GR64BitRegClass);
4969 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
4970 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
4972 // Get the right opcodes for the displacement.
4973 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
4974 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
4975 assert(LOpcode && CSOpcode && "Displacement out of range");
4977 // Create virtual registers for temporary results.
4978 unsigned OrigVal = MRI.createVirtualRegister(RC);
4979 unsigned OldVal = MRI.createVirtualRegister(RC);
4980 unsigned NewVal = (BinOpcode || IsSubWord ?
4981 MRI.createVirtualRegister(RC) : Src2.getReg());
4982 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
4983 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
4985 // Insert a basic block for the main loop.
4986 MachineBasicBlock *StartMBB = MBB;
4987 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
4988 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
4992 // %OrigVal = L Disp(%Base)
4993 // # fall through to LoopMMB
4995 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
4996 .addOperand(Base).addImm(Disp).addReg(0);
4997 MBB->addSuccessor(LoopMBB);
5000 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
5001 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
5002 // %RotatedNewVal = OP %RotatedOldVal, %Src2
5003 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
5004 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
5006 // # fall through to DoneMMB
5008 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5009 .addReg(OrigVal).addMBB(StartMBB)
5010 .addReg(Dest).addMBB(LoopMBB);
5012 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
5013 .addReg(OldVal).addReg(BitShift).addImm(0);
5015 // Perform the operation normally and then invert every bit of the field.
5016 unsigned Tmp = MRI.createVirtualRegister(RC);
5017 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
5018 .addReg(RotatedOldVal).addOperand(Src2);
5020 // XILF with the upper BitSize bits set.
5021 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
5022 .addReg(Tmp).addImm(-1U << (32 - BitSize));
5024 // Use LCGR and add -1 to the result, which is more compact than
5025 // an XILF, XILH pair.
5026 unsigned Tmp2 = MRI.createVirtualRegister(RC);
5027 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
5028 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
5029 .addReg(Tmp2).addImm(-1);
5031 } else if (BinOpcode)
5032 // A simply binary operation.
5033 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
5034 .addReg(RotatedOldVal).addOperand(Src2);
5036 // Use RISBG to rotate Src2 into position and use it to replace the
5037 // field in RotatedOldVal.
5038 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
5039 .addReg(RotatedOldVal).addReg(Src2.getReg())
5040 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
5042 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
5043 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
5044 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
5045 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
5046 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5047 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5048 MBB->addSuccessor(LoopMBB);
5049 MBB->addSuccessor(DoneMBB);
5051 MI->eraseFromParent();
5055 // Implement EmitInstrWithCustomInserter for pseudo
5056 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
5057 // instruction that should be used to compare the current field with the
5058 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
5059 // for when the current field should be kept. BitSize is the width of
5060 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
5062 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
5063 MachineBasicBlock *MBB,
5064 unsigned CompareOpcode,
5065 unsigned KeepOldMask,
5066 unsigned BitSize) const {
5067 MachineFunction &MF = *MBB->getParent();
5068 const SystemZInstrInfo *TII =
5069 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5070 MachineRegisterInfo &MRI = MF.getRegInfo();
5071 bool IsSubWord = (BitSize < 32);
5073 // Extract the operands. Base can be a register or a frame index.
5074 unsigned Dest = MI->getOperand(0).getReg();
5075 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
5076 int64_t Disp = MI->getOperand(2).getImm();
5077 unsigned Src2 = MI->getOperand(3).getReg();
5078 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
5079 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
5080 DebugLoc DL = MI->getDebugLoc();
5082 BitSize = MI->getOperand(6).getImm();
5084 // Subword operations use 32-bit registers.
5085 const TargetRegisterClass *RC = (BitSize <= 32 ?
5086 &SystemZ::GR32BitRegClass :
5087 &SystemZ::GR64BitRegClass);
5088 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
5089 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
5091 // Get the right opcodes for the displacement.
5092 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
5093 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
5094 assert(LOpcode && CSOpcode && "Displacement out of range");
5096 // Create virtual registers for temporary results.
5097 unsigned OrigVal = MRI.createVirtualRegister(RC);
5098 unsigned OldVal = MRI.createVirtualRegister(RC);
5099 unsigned NewVal = MRI.createVirtualRegister(RC);
5100 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
5101 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
5102 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
5104 // Insert 3 basic blocks for the loop.
5105 MachineBasicBlock *StartMBB = MBB;
5106 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5107 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5108 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
5109 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
5113 // %OrigVal = L Disp(%Base)
5114 // # fall through to LoopMMB
5116 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
5117 .addOperand(Base).addImm(Disp).addReg(0);
5118 MBB->addSuccessor(LoopMBB);
5121 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
5122 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
5123 // CompareOpcode %RotatedOldVal, %Src2
5124 // BRC KeepOldMask, UpdateMBB
5126 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5127 .addReg(OrigVal).addMBB(StartMBB)
5128 .addReg(Dest).addMBB(UpdateMBB);
5130 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
5131 .addReg(OldVal).addReg(BitShift).addImm(0);
5132 BuildMI(MBB, DL, TII->get(CompareOpcode))
5133 .addReg(RotatedOldVal).addReg(Src2);
5134 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5135 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
5136 MBB->addSuccessor(UpdateMBB);
5137 MBB->addSuccessor(UseAltMBB);
5140 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
5141 // # fall through to UpdateMMB
5144 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
5145 .addReg(RotatedOldVal).addReg(Src2)
5146 .addImm(32).addImm(31 + BitSize).addImm(0);
5147 MBB->addSuccessor(UpdateMBB);
5150 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
5151 // [ %RotatedAltVal, UseAltMBB ]
5152 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
5153 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
5155 // # fall through to DoneMMB
5157 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
5158 .addReg(RotatedOldVal).addMBB(LoopMBB)
5159 .addReg(RotatedAltVal).addMBB(UseAltMBB);
5161 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
5162 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
5163 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
5164 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
5165 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5166 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5167 MBB->addSuccessor(LoopMBB);
5168 MBB->addSuccessor(DoneMBB);
5170 MI->eraseFromParent();
5174 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
5177 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
5178 MachineBasicBlock *MBB) const {
5179 MachineFunction &MF = *MBB->getParent();
5180 const SystemZInstrInfo *TII =
5181 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5182 MachineRegisterInfo &MRI = MF.getRegInfo();
5184 // Extract the operands. Base can be a register or a frame index.
5185 unsigned Dest = MI->getOperand(0).getReg();
5186 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
5187 int64_t Disp = MI->getOperand(2).getImm();
5188 unsigned OrigCmpVal = MI->getOperand(3).getReg();
5189 unsigned OrigSwapVal = MI->getOperand(4).getReg();
5190 unsigned BitShift = MI->getOperand(5).getReg();
5191 unsigned NegBitShift = MI->getOperand(6).getReg();
5192 int64_t BitSize = MI->getOperand(7).getImm();
5193 DebugLoc DL = MI->getDebugLoc();
5195 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
5197 // Get the right opcodes for the displacement.
5198 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
5199 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
5200 assert(LOpcode && CSOpcode && "Displacement out of range");
5202 // Create virtual registers for temporary results.
5203 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
5204 unsigned OldVal = MRI.createVirtualRegister(RC);
5205 unsigned CmpVal = MRI.createVirtualRegister(RC);
5206 unsigned SwapVal = MRI.createVirtualRegister(RC);
5207 unsigned StoreVal = MRI.createVirtualRegister(RC);
5208 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
5209 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
5210 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
5212 // Insert 2 basic blocks for the loop.
5213 MachineBasicBlock *StartMBB = MBB;
5214 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5215 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5216 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
5220 // %OrigOldVal = L Disp(%Base)
5221 // # fall through to LoopMMB
5223 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
5224 .addOperand(Base).addImm(Disp).addReg(0);
5225 MBB->addSuccessor(LoopMBB);
5228 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
5229 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
5230 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
5231 // %Dest = RLL %OldVal, BitSize(%BitShift)
5232 // ^^ The low BitSize bits contain the field
5234 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
5235 // ^^ Replace the upper 32-BitSize bits of the
5236 // comparison value with those that we loaded,
5237 // so that we can use a full word comparison.
5238 // CR %Dest, %RetryCmpVal
5240 // # Fall through to SetMBB
5242 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5243 .addReg(OrigOldVal).addMBB(StartMBB)
5244 .addReg(RetryOldVal).addMBB(SetMBB);
5245 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
5246 .addReg(OrigCmpVal).addMBB(StartMBB)
5247 .addReg(RetryCmpVal).addMBB(SetMBB);
5248 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
5249 .addReg(OrigSwapVal).addMBB(StartMBB)
5250 .addReg(RetrySwapVal).addMBB(SetMBB);
5251 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
5252 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
5253 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
5254 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
5255 BuildMI(MBB, DL, TII->get(SystemZ::CR))
5256 .addReg(Dest).addReg(RetryCmpVal);
5257 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5258 .addImm(SystemZ::CCMASK_ICMP)
5259 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
5260 MBB->addSuccessor(DoneMBB);
5261 MBB->addSuccessor(SetMBB);
5264 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
5265 // ^^ Replace the upper 32-BitSize bits of the new
5266 // value with those that we loaded.
5267 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
5268 // ^^ Rotate the new field to its proper position.
5269 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
5271 // # fall through to ExitMMB
5273 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
5274 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
5275 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
5276 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
5277 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
5278 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
5279 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5280 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5281 MBB->addSuccessor(LoopMBB);
5282 MBB->addSuccessor(DoneMBB);
5284 MI->eraseFromParent();
5288 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
5289 // if the high register of the GR128 value must be cleared or false if
5290 // it's "don't care". SubReg is subreg_l32 when extending a GR32
5291 // and subreg_l64 when extending a GR64.
5293 SystemZTargetLowering::emitExt128(MachineInstr *MI,
5294 MachineBasicBlock *MBB,
5295 bool ClearEven, unsigned SubReg) const {
5296 MachineFunction &MF = *MBB->getParent();
5297 const SystemZInstrInfo *TII =
5298 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5299 MachineRegisterInfo &MRI = MF.getRegInfo();
5300 DebugLoc DL = MI->getDebugLoc();
5302 unsigned Dest = MI->getOperand(0).getReg();
5303 unsigned Src = MI->getOperand(1).getReg();
5304 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
5306 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
5308 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
5309 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
5311 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
5313 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
5314 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
5317 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
5318 .addReg(In128).addReg(Src).addImm(SubReg);
5320 MI->eraseFromParent();
5325 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
5326 MachineBasicBlock *MBB,
5327 unsigned Opcode) const {
5328 MachineFunction &MF = *MBB->getParent();
5329 const SystemZInstrInfo *TII =
5330 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5331 MachineRegisterInfo &MRI = MF.getRegInfo();
5332 DebugLoc DL = MI->getDebugLoc();
5334 MachineOperand DestBase = earlyUseOperand(MI->getOperand(0));
5335 uint64_t DestDisp = MI->getOperand(1).getImm();
5336 MachineOperand SrcBase = earlyUseOperand(MI->getOperand(2));
5337 uint64_t SrcDisp = MI->getOperand(3).getImm();
5338 uint64_t Length = MI->getOperand(4).getImm();
5340 // When generating more than one CLC, all but the last will need to
5341 // branch to the end when a difference is found.
5342 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
5343 splitBlockAfter(MI, MBB) : nullptr);
5345 // Check for the loop form, in which operand 5 is the trip count.
5346 if (MI->getNumExplicitOperands() > 5) {
5347 bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
5349 uint64_t StartCountReg = MI->getOperand(5).getReg();
5350 uint64_t StartSrcReg = forceReg(MI, SrcBase, TII);
5351 uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
5352 forceReg(MI, DestBase, TII));
5354 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
5355 uint64_t ThisSrcReg = MRI.createVirtualRegister(RC);
5356 uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
5357 MRI.createVirtualRegister(RC));
5358 uint64_t NextSrcReg = MRI.createVirtualRegister(RC);
5359 uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
5360 MRI.createVirtualRegister(RC));
5362 RC = &SystemZ::GR64BitRegClass;
5363 uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
5364 uint64_t NextCountReg = MRI.createVirtualRegister(RC);
5366 MachineBasicBlock *StartMBB = MBB;
5367 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5368 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5369 MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
5372 // # fall through to LoopMMB
5373 MBB->addSuccessor(LoopMBB);
5376 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
5377 // [ %NextDestReg, NextMBB ]
5378 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
5379 // [ %NextSrcReg, NextMBB ]
5380 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
5381 // [ %NextCountReg, NextMBB ]
5382 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
5383 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
5386 // The prefetch is used only for MVC. The JLH is used only for CLC.
5389 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
5390 .addReg(StartDestReg).addMBB(StartMBB)
5391 .addReg(NextDestReg).addMBB(NextMBB);
5392 if (!HaveSingleBase)
5393 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
5394 .addReg(StartSrcReg).addMBB(StartMBB)
5395 .addReg(NextSrcReg).addMBB(NextMBB);
5396 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
5397 .addReg(StartCountReg).addMBB(StartMBB)
5398 .addReg(NextCountReg).addMBB(NextMBB);
5399 if (Opcode == SystemZ::MVC)
5400 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
5401 .addImm(SystemZ::PFD_WRITE)
5402 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
5403 BuildMI(MBB, DL, TII->get(Opcode))
5404 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
5405 .addReg(ThisSrcReg).addImm(SrcDisp);
5407 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5408 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5410 MBB->addSuccessor(EndMBB);
5411 MBB->addSuccessor(NextMBB);
5415 // %NextDestReg = LA 256(%ThisDestReg)
5416 // %NextSrcReg = LA 256(%ThisSrcReg)
5417 // %NextCountReg = AGHI %ThisCountReg, -1
5418 // CGHI %NextCountReg, 0
5420 // # fall through to DoneMMB
5422 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
5425 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
5426 .addReg(ThisDestReg).addImm(256).addReg(0);
5427 if (!HaveSingleBase)
5428 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
5429 .addReg(ThisSrcReg).addImm(256).addReg(0);
5430 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
5431 .addReg(ThisCountReg).addImm(-1);
5432 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
5433 .addReg(NextCountReg).addImm(0);
5434 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5435 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5437 MBB->addSuccessor(LoopMBB);
5438 MBB->addSuccessor(DoneMBB);
5440 DestBase = MachineOperand::CreateReg(NextDestReg, false);
5441 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
5445 // Handle any remaining bytes with straight-line code.
5446 while (Length > 0) {
5447 uint64_t ThisLength = std::min(Length, uint64_t(256));
5448 // The previous iteration might have created out-of-range displacements.
5449 // Apply them using LAY if so.
5450 if (!isUInt<12>(DestDisp)) {
5451 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
5452 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
5453 .addOperand(DestBase).addImm(DestDisp).addReg(0);
5454 DestBase = MachineOperand::CreateReg(Reg, false);
5457 if (!isUInt<12>(SrcDisp)) {
5458 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
5459 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
5460 .addOperand(SrcBase).addImm(SrcDisp).addReg(0);
5461 SrcBase = MachineOperand::CreateReg(Reg, false);
5464 BuildMI(*MBB, MI, DL, TII->get(Opcode))
5465 .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
5466 .addOperand(SrcBase).addImm(SrcDisp);
5467 DestDisp += ThisLength;
5468 SrcDisp += ThisLength;
5469 Length -= ThisLength;
5470 // If there's another CLC to go, branch to the end if a difference
5472 if (EndMBB && Length > 0) {
5473 MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
5474 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5475 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5477 MBB->addSuccessor(EndMBB);
5478 MBB->addSuccessor(NextMBB);
5483 MBB->addSuccessor(EndMBB);
5485 MBB->addLiveIn(SystemZ::CC);
5488 MI->eraseFromParent();
5492 // Decompose string pseudo-instruction MI into a loop that continually performs
5493 // Opcode until CC != 3.
5495 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
5496 MachineBasicBlock *MBB,
5497 unsigned Opcode) const {
5498 MachineFunction &MF = *MBB->getParent();
5499 const SystemZInstrInfo *TII =
5500 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5501 MachineRegisterInfo &MRI = MF.getRegInfo();
5502 DebugLoc DL = MI->getDebugLoc();
5504 uint64_t End1Reg = MI->getOperand(0).getReg();
5505 uint64_t Start1Reg = MI->getOperand(1).getReg();
5506 uint64_t Start2Reg = MI->getOperand(2).getReg();
5507 uint64_t CharReg = MI->getOperand(3).getReg();
5509 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
5510 uint64_t This1Reg = MRI.createVirtualRegister(RC);
5511 uint64_t This2Reg = MRI.createVirtualRegister(RC);
5512 uint64_t End2Reg = MRI.createVirtualRegister(RC);
5514 MachineBasicBlock *StartMBB = MBB;
5515 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5516 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5519 // # fall through to LoopMMB
5520 MBB->addSuccessor(LoopMBB);
5523 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
5524 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
5526 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
5528 // # fall through to DoneMMB
5530 // The load of R0L can be hoisted by post-RA LICM.
5533 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
5534 .addReg(Start1Reg).addMBB(StartMBB)
5535 .addReg(End1Reg).addMBB(LoopMBB);
5536 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
5537 .addReg(Start2Reg).addMBB(StartMBB)
5538 .addReg(End2Reg).addMBB(LoopMBB);
5539 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
5540 BuildMI(MBB, DL, TII->get(Opcode))
5541 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
5542 .addReg(This1Reg).addReg(This2Reg);
5543 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5544 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
5545 MBB->addSuccessor(LoopMBB);
5546 MBB->addSuccessor(DoneMBB);
5548 DoneMBB->addLiveIn(SystemZ::CC);
5550 MI->eraseFromParent();
5554 // Update TBEGIN instruction with final opcode and register clobbers.
5556 SystemZTargetLowering::emitTransactionBegin(MachineInstr *MI,
5557 MachineBasicBlock *MBB,
5559 bool NoFloat) const {
5560 MachineFunction &MF = *MBB->getParent();
5561 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
5562 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
5565 MI->setDesc(TII->get(Opcode));
5567 // We cannot handle a TBEGIN that clobbers the stack or frame pointer.
5568 // Make sure to add the corresponding GRSM bits if they are missing.
5569 uint64_t Control = MI->getOperand(2).getImm();
5570 static const unsigned GPRControlBit[16] = {
5571 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
5572 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
5574 Control |= GPRControlBit[15];
5576 Control |= GPRControlBit[11];
5577 MI->getOperand(2).setImm(Control);
5579 // Add GPR clobbers.
5580 for (int I = 0; I < 16; I++) {
5581 if ((Control & GPRControlBit[I]) == 0) {
5582 unsigned Reg = SystemZMC::GR64Regs[I];
5583 MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
5587 // Add FPR/VR clobbers.
5588 if (!NoFloat && (Control & 4) != 0) {
5589 if (Subtarget.hasVector()) {
5590 for (int I = 0; I < 32; I++) {
5591 unsigned Reg = SystemZMC::VR128Regs[I];
5592 MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
5595 for (int I = 0; I < 16; I++) {
5596 unsigned Reg = SystemZMC::FP64Regs[I];
5597 MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
5605 MachineBasicBlock *SystemZTargetLowering::
5606 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
5607 switch (MI->getOpcode()) {
5608 case SystemZ::Select32Mux:
5609 case SystemZ::Select32:
5610 case SystemZ::SelectF32:
5611 case SystemZ::Select64:
5612 case SystemZ::SelectF64:
5613 case SystemZ::SelectF128:
5614 return emitSelect(MI, MBB);
5616 case SystemZ::CondStore8Mux:
5617 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
5618 case SystemZ::CondStore8MuxInv:
5619 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
5620 case SystemZ::CondStore16Mux:
5621 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
5622 case SystemZ::CondStore16MuxInv:
5623 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
5624 case SystemZ::CondStore8:
5625 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
5626 case SystemZ::CondStore8Inv:
5627 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
5628 case SystemZ::CondStore16:
5629 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
5630 case SystemZ::CondStore16Inv:
5631 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
5632 case SystemZ::CondStore32:
5633 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
5634 case SystemZ::CondStore32Inv:
5635 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
5636 case SystemZ::CondStore64:
5637 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
5638 case SystemZ::CondStore64Inv:
5639 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
5640 case SystemZ::CondStoreF32:
5641 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
5642 case SystemZ::CondStoreF32Inv:
5643 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
5644 case SystemZ::CondStoreF64:
5645 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
5646 case SystemZ::CondStoreF64Inv:
5647 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
5649 case SystemZ::AEXT128_64:
5650 return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
5651 case SystemZ::ZEXT128_32:
5652 return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
5653 case SystemZ::ZEXT128_64:
5654 return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
5656 case SystemZ::ATOMIC_SWAPW:
5657 return emitAtomicLoadBinary(MI, MBB, 0, 0);
5658 case SystemZ::ATOMIC_SWAP_32:
5659 return emitAtomicLoadBinary(MI, MBB, 0, 32);
5660 case SystemZ::ATOMIC_SWAP_64:
5661 return emitAtomicLoadBinary(MI, MBB, 0, 64);
5663 case SystemZ::ATOMIC_LOADW_AR:
5664 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
5665 case SystemZ::ATOMIC_LOADW_AFI:
5666 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
5667 case SystemZ::ATOMIC_LOAD_AR:
5668 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
5669 case SystemZ::ATOMIC_LOAD_AHI:
5670 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
5671 case SystemZ::ATOMIC_LOAD_AFI:
5672 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
5673 case SystemZ::ATOMIC_LOAD_AGR:
5674 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
5675 case SystemZ::ATOMIC_LOAD_AGHI:
5676 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
5677 case SystemZ::ATOMIC_LOAD_AGFI:
5678 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
5680 case SystemZ::ATOMIC_LOADW_SR:
5681 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
5682 case SystemZ::ATOMIC_LOAD_SR:
5683 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
5684 case SystemZ::ATOMIC_LOAD_SGR:
5685 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
5687 case SystemZ::ATOMIC_LOADW_NR:
5688 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
5689 case SystemZ::ATOMIC_LOADW_NILH:
5690 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
5691 case SystemZ::ATOMIC_LOAD_NR:
5692 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
5693 case SystemZ::ATOMIC_LOAD_NILL:
5694 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
5695 case SystemZ::ATOMIC_LOAD_NILH:
5696 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
5697 case SystemZ::ATOMIC_LOAD_NILF:
5698 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
5699 case SystemZ::ATOMIC_LOAD_NGR:
5700 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
5701 case SystemZ::ATOMIC_LOAD_NILL64:
5702 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
5703 case SystemZ::ATOMIC_LOAD_NILH64:
5704 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
5705 case SystemZ::ATOMIC_LOAD_NIHL64:
5706 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
5707 case SystemZ::ATOMIC_LOAD_NIHH64:
5708 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
5709 case SystemZ::ATOMIC_LOAD_NILF64:
5710 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
5711 case SystemZ::ATOMIC_LOAD_NIHF64:
5712 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
5714 case SystemZ::ATOMIC_LOADW_OR:
5715 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
5716 case SystemZ::ATOMIC_LOADW_OILH:
5717 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
5718 case SystemZ::ATOMIC_LOAD_OR:
5719 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
5720 case SystemZ::ATOMIC_LOAD_OILL:
5721 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
5722 case SystemZ::ATOMIC_LOAD_OILH:
5723 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
5724 case SystemZ::ATOMIC_LOAD_OILF:
5725 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
5726 case SystemZ::ATOMIC_LOAD_OGR:
5727 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
5728 case SystemZ::ATOMIC_LOAD_OILL64:
5729 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
5730 case SystemZ::ATOMIC_LOAD_OILH64:
5731 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
5732 case SystemZ::ATOMIC_LOAD_OIHL64:
5733 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
5734 case SystemZ::ATOMIC_LOAD_OIHH64:
5735 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
5736 case SystemZ::ATOMIC_LOAD_OILF64:
5737 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
5738 case SystemZ::ATOMIC_LOAD_OIHF64:
5739 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
5741 case SystemZ::ATOMIC_LOADW_XR:
5742 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
5743 case SystemZ::ATOMIC_LOADW_XILF:
5744 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
5745 case SystemZ::ATOMIC_LOAD_XR:
5746 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
5747 case SystemZ::ATOMIC_LOAD_XILF:
5748 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
5749 case SystemZ::ATOMIC_LOAD_XGR:
5750 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
5751 case SystemZ::ATOMIC_LOAD_XILF64:
5752 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
5753 case SystemZ::ATOMIC_LOAD_XIHF64:
5754 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
5756 case SystemZ::ATOMIC_LOADW_NRi:
5757 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
5758 case SystemZ::ATOMIC_LOADW_NILHi:
5759 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
5760 case SystemZ::ATOMIC_LOAD_NRi:
5761 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
5762 case SystemZ::ATOMIC_LOAD_NILLi:
5763 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
5764 case SystemZ::ATOMIC_LOAD_NILHi:
5765 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
5766 case SystemZ::ATOMIC_LOAD_NILFi:
5767 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
5768 case SystemZ::ATOMIC_LOAD_NGRi:
5769 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
5770 case SystemZ::ATOMIC_LOAD_NILL64i:
5771 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
5772 case SystemZ::ATOMIC_LOAD_NILH64i:
5773 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
5774 case SystemZ::ATOMIC_LOAD_NIHL64i:
5775 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
5776 case SystemZ::ATOMIC_LOAD_NIHH64i:
5777 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
5778 case SystemZ::ATOMIC_LOAD_NILF64i:
5779 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
5780 case SystemZ::ATOMIC_LOAD_NIHF64i:
5781 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
5783 case SystemZ::ATOMIC_LOADW_MIN:
5784 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5785 SystemZ::CCMASK_CMP_LE, 0);
5786 case SystemZ::ATOMIC_LOAD_MIN_32:
5787 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5788 SystemZ::CCMASK_CMP_LE, 32);
5789 case SystemZ::ATOMIC_LOAD_MIN_64:
5790 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
5791 SystemZ::CCMASK_CMP_LE, 64);
5793 case SystemZ::ATOMIC_LOADW_MAX:
5794 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5795 SystemZ::CCMASK_CMP_GE, 0);
5796 case SystemZ::ATOMIC_LOAD_MAX_32:
5797 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5798 SystemZ::CCMASK_CMP_GE, 32);
5799 case SystemZ::ATOMIC_LOAD_MAX_64:
5800 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
5801 SystemZ::CCMASK_CMP_GE, 64);
5803 case SystemZ::ATOMIC_LOADW_UMIN:
5804 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5805 SystemZ::CCMASK_CMP_LE, 0);
5806 case SystemZ::ATOMIC_LOAD_UMIN_32:
5807 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5808 SystemZ::CCMASK_CMP_LE, 32);
5809 case SystemZ::ATOMIC_LOAD_UMIN_64:
5810 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
5811 SystemZ::CCMASK_CMP_LE, 64);
5813 case SystemZ::ATOMIC_LOADW_UMAX:
5814 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5815 SystemZ::CCMASK_CMP_GE, 0);
5816 case SystemZ::ATOMIC_LOAD_UMAX_32:
5817 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5818 SystemZ::CCMASK_CMP_GE, 32);
5819 case SystemZ::ATOMIC_LOAD_UMAX_64:
5820 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
5821 SystemZ::CCMASK_CMP_GE, 64);
5823 case SystemZ::ATOMIC_CMP_SWAPW:
5824 return emitAtomicCmpSwapW(MI, MBB);
5825 case SystemZ::MVCSequence:
5826 case SystemZ::MVCLoop:
5827 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
5828 case SystemZ::NCSequence:
5829 case SystemZ::NCLoop:
5830 return emitMemMemWrapper(MI, MBB, SystemZ::NC);
5831 case SystemZ::OCSequence:
5832 case SystemZ::OCLoop:
5833 return emitMemMemWrapper(MI, MBB, SystemZ::OC);
5834 case SystemZ::XCSequence:
5835 case SystemZ::XCLoop:
5836 return emitMemMemWrapper(MI, MBB, SystemZ::XC);
5837 case SystemZ::CLCSequence:
5838 case SystemZ::CLCLoop:
5839 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
5840 case SystemZ::CLSTLoop:
5841 return emitStringWrapper(MI, MBB, SystemZ::CLST);
5842 case SystemZ::MVSTLoop:
5843 return emitStringWrapper(MI, MBB, SystemZ::MVST);
5844 case SystemZ::SRSTLoop:
5845 return emitStringWrapper(MI, MBB, SystemZ::SRST);
5846 case SystemZ::TBEGIN:
5847 return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false);
5848 case SystemZ::TBEGIN_nofloat:
5849 return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true);
5850 case SystemZ::TBEGINC:
5851 return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true);
5853 llvm_unreachable("Unexpected instr type to insert");