1 //===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "SystemZFrameLowering.h"
11 #include "SystemZCallingConv.h"
12 #include "SystemZInstrBuilder.h"
13 #include "SystemZInstrInfo.h"
14 #include "SystemZMachineFunctionInfo.h"
15 #include "SystemZRegisterInfo.h"
16 #include "SystemZSubtarget.h"
17 #include "llvm/CodeGen/MachineModuleInfo.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/RegisterScavenging.h"
20 #include "llvm/IR/Function.h"
25 // The ABI-defined register save slots, relative to the incoming stack
27 static const TargetFrameLowering::SpillSlot SpillOffsetTable[] = {
28 { SystemZ::R2D, 0x10 },
29 { SystemZ::R3D, 0x18 },
30 { SystemZ::R4D, 0x20 },
31 { SystemZ::R5D, 0x28 },
32 { SystemZ::R6D, 0x30 },
33 { SystemZ::R7D, 0x38 },
34 { SystemZ::R8D, 0x40 },
35 { SystemZ::R9D, 0x48 },
36 { SystemZ::R10D, 0x50 },
37 { SystemZ::R11D, 0x58 },
38 { SystemZ::R12D, 0x60 },
39 { SystemZ::R13D, 0x68 },
40 { SystemZ::R14D, 0x70 },
41 { SystemZ::R15D, 0x78 },
42 { SystemZ::F0D, 0x80 },
43 { SystemZ::F2D, 0x88 },
44 { SystemZ::F4D, 0x90 },
45 { SystemZ::F6D, 0x98 }
47 } // end anonymous namespace
49 SystemZFrameLowering::SystemZFrameLowering()
50 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8,
51 -SystemZMC::CallFrameSize, 8) {
52 // Create a mapping from register number to save slot offset.
53 RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
54 for (unsigned I = 0, E = array_lengthof(SpillOffsetTable); I != E; ++I)
55 RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset;
58 const TargetFrameLowering::SpillSlot *
59 SystemZFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {
60 NumEntries = array_lengthof(SpillOffsetTable);
61 return SpillOffsetTable;
64 void SystemZFrameLowering::determineCalleeSaves(MachineFunction &MF,
66 RegScavenger *RS) const {
67 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
69 MachineFrameInfo *MFFrame = MF.getFrameInfo();
70 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
71 bool HasFP = hasFP(MF);
72 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
73 bool IsVarArg = MF.getFunction()->isVarArg();
75 // va_start stores incoming FPR varargs in the normal way, but delegates
76 // the saving of incoming GPR varargs to spillCalleeSavedRegisters().
77 // Record these pending uses, which typically include the call-saved
78 // argument register R6D.
80 for (unsigned I = MFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
81 SavedRegs.set(SystemZ::ArgGPRs[I]);
83 // If the function requires a frame pointer, record that the hard
84 // frame pointer will be clobbered.
86 SavedRegs.set(SystemZ::R11D);
88 // If the function calls other functions, record that the return
89 // address register will be clobbered.
90 if (MFFrame->hasCalls())
91 SavedRegs.set(SystemZ::R14D);
93 // If we are saving GPRs other than the stack pointer, we might as well
94 // save and restore the stack pointer at the same time, via STMG and LMG.
95 // This allows the deallocation to be done by the LMG, rather than needing
96 // a separate %r15 addition.
97 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
98 for (unsigned I = 0; CSRegs[I]; ++I) {
99 unsigned Reg = CSRegs[I];
100 if (SystemZ::GR64BitRegClass.contains(Reg) && SavedRegs.test(Reg)) {
101 SavedRegs.set(SystemZ::R15D);
107 // Add GPR64 to the save instruction being built by MIB, which is in basic
108 // block MBB. IsImplicit says whether this is an explicit operand to the
109 // instruction, or an implicit one that comes between the explicit start
110 // and end registers.
111 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
112 unsigned GPR64, bool IsImplicit) {
113 const TargetRegisterInfo *RI =
114 MBB.getParent()->getSubtarget().getRegisterInfo();
115 unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
116 bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32);
117 if (!IsLive || !IsImplicit) {
118 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
120 MBB.addLiveIn(GPR64);
124 bool SystemZFrameLowering::
125 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
126 MachineBasicBlock::iterator MBBI,
127 const std::vector<CalleeSavedInfo> &CSI,
128 const TargetRegisterInfo *TRI) const {
132 MachineFunction &MF = *MBB.getParent();
133 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
134 SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
135 bool IsVarArg = MF.getFunction()->isVarArg();
136 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
138 // Scan the call-saved GPRs and find the bounds of the register spill area.
140 unsigned HighGPR = SystemZ::R15D;
141 unsigned StartOffset = -1U;
142 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
143 unsigned Reg = CSI[I].getReg();
144 if (SystemZ::GR64BitRegClass.contains(Reg)) {
145 unsigned Offset = RegSpillOffsets[Reg];
146 assert(Offset && "Unexpected GPR save");
147 if (StartOffset > Offset) {
149 StartOffset = Offset;
154 // Save the range of call-saved registers, for use by the epilogue inserter.
155 ZFI->setLowSavedGPR(LowGPR);
156 ZFI->setHighSavedGPR(HighGPR);
158 // Include the GPR varargs, if any. R6D is call-saved, so would
159 // be included by the loop above, but we also need to handle the
160 // call-clobbered argument registers.
162 unsigned FirstGPR = ZFI->getVarArgsFirstGPR();
163 if (FirstGPR < SystemZ::NumArgGPRs) {
164 unsigned Reg = SystemZ::ArgGPRs[FirstGPR];
165 unsigned Offset = RegSpillOffsets[Reg];
166 if (StartOffset > Offset) {
167 LowGPR = Reg; StartOffset = Offset;
174 assert(LowGPR != HighGPR && "Should be saving %r15 and something else");
176 // Build an STMG instruction.
177 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
179 // Add the explicit register operands.
180 addSavedGPR(MBB, MIB, LowGPR, false);
181 addSavedGPR(MBB, MIB, HighGPR, false);
184 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
186 // Make sure all call-saved GPRs are included as operands and are
187 // marked as live on entry.
188 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
189 unsigned Reg = CSI[I].getReg();
190 if (SystemZ::GR64BitRegClass.contains(Reg))
191 addSavedGPR(MBB, MIB, Reg, true);
194 // ...likewise GPR varargs.
196 for (unsigned I = ZFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
197 addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
200 // Save FPRs in the normal TargetInstrInfo way.
201 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
202 unsigned Reg = CSI[I].getReg();
203 if (SystemZ::FP64BitRegClass.contains(Reg)) {
205 TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
206 &SystemZ::FP64BitRegClass, TRI);
213 bool SystemZFrameLowering::
214 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
215 MachineBasicBlock::iterator MBBI,
216 const std::vector<CalleeSavedInfo> &CSI,
217 const TargetRegisterInfo *TRI) const {
221 MachineFunction &MF = *MBB.getParent();
222 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
223 SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
224 bool HasFP = hasFP(MF);
225 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
227 // Restore FPRs in the normal TargetInstrInfo way.
228 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
229 unsigned Reg = CSI[I].getReg();
230 if (SystemZ::FP64BitRegClass.contains(Reg))
231 TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
232 &SystemZ::FP64BitRegClass, TRI);
235 // Restore call-saved GPRs (but not call-clobbered varargs, which at
236 // this point might hold return values).
237 unsigned LowGPR = ZFI->getLowSavedGPR();
238 unsigned HighGPR = ZFI->getHighSavedGPR();
239 unsigned StartOffset = RegSpillOffsets[LowGPR];
241 // If we saved any of %r2-%r5 as varargs, we should also be saving
242 // and restoring %r6. If we're saving %r6 or above, we should be
244 assert(LowGPR != HighGPR && "Should be loading %r15 and something else");
246 // Build an LMG instruction.
247 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
249 // Add the explicit register operands.
250 MIB.addReg(LowGPR, RegState::Define);
251 MIB.addReg(HighGPR, RegState::Define);
254 MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D);
255 MIB.addImm(StartOffset);
257 // Do a second scan adding regs as being defined by instruction
258 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
259 unsigned Reg = CSI[I].getReg();
260 if (Reg != LowGPR && Reg != HighGPR)
261 MIB.addReg(Reg, RegState::ImplicitDefine);
268 void SystemZFrameLowering::
269 processFunctionBeforeFrameFinalized(MachineFunction &MF,
270 RegScavenger *RS) const {
271 MachineFrameInfo *MFFrame = MF.getFrameInfo();
272 uint64_t MaxReach = (MFFrame->estimateStackSize(MF) +
273 SystemZMC::CallFrameSize * 2);
274 if (!isUInt<12>(MaxReach)) {
275 // We may need register scavenging slots if some parts of the frame
276 // are outside the reach of an unsigned 12-bit displacement.
277 // Create 2 for the case where both addresses in an MVC are
279 RS->addScavengingFrameIndex(MFFrame->CreateStackObject(8, 8, false));
280 RS->addScavengingFrameIndex(MFFrame->CreateStackObject(8, 8, false));
284 // Emit instructions before MBBI (in MBB) to add NumBytes to Reg.
285 static void emitIncrement(MachineBasicBlock &MBB,
286 MachineBasicBlock::iterator &MBBI,
288 unsigned Reg, int64_t NumBytes,
289 const TargetInstrInfo *TII) {
292 int64_t ThisVal = NumBytes;
293 if (isInt<16>(NumBytes))
294 Opcode = SystemZ::AGHI;
296 Opcode = SystemZ::AGFI;
297 // Make sure we maintain 8-byte stack alignment.
298 int64_t MinVal = -uint64_t(1) << 31;
299 int64_t MaxVal = (int64_t(1) << 31) - 8;
300 if (ThisVal < MinVal)
302 else if (ThisVal > MaxVal)
305 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
306 .addReg(Reg).addImm(ThisVal);
307 // The CC implicit def is dead.
308 MI->getOperand(3).setIsDead();
313 void SystemZFrameLowering::emitPrologue(MachineFunction &MF,
314 MachineBasicBlock &MBB) const {
315 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
316 MachineFrameInfo *MFFrame = MF.getFrameInfo();
318 static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
319 SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
320 MachineBasicBlock::iterator MBBI = MBB.begin();
321 MachineModuleInfo &MMI = MF.getMMI();
322 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
323 const std::vector<CalleeSavedInfo> &CSI = MFFrame->getCalleeSavedInfo();
324 bool HasFP = hasFP(MF);
325 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
327 // The current offset of the stack pointer from the CFA.
328 int64_t SPOffsetFromCFA = -SystemZMC::CFAOffsetFromInitialSP;
330 if (ZFI->getLowSavedGPR()) {
331 // Skip over the GPR saves.
332 if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
335 llvm_unreachable("Couldn't skip over GPR saves");
337 // Add CFI for the GPR saves.
338 for (auto &Save : CSI) {
339 unsigned Reg = Save.getReg();
340 if (SystemZ::GR64BitRegClass.contains(Reg)) {
341 int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
342 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
343 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
344 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
345 .addCFIIndex(CFIIndex);
350 uint64_t StackSize = getAllocatedStackSize(MF);
352 // Allocate StackSize bytes.
353 int64_t Delta = -int64_t(StackSize);
354 emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
356 // Add CFI for the allocation.
357 unsigned CFIIndex = MMI.addFrameInst(
358 MCCFIInstruction::createDefCfaOffset(nullptr, SPOffsetFromCFA + Delta));
359 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
360 .addCFIIndex(CFIIndex);
361 SPOffsetFromCFA += Delta;
365 // Copy the base of the frame to R11.
366 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
367 .addReg(SystemZ::R15D);
369 // Add CFI for the new frame location.
370 unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
371 unsigned CFIIndex = MMI.addFrameInst(
372 MCCFIInstruction::createDefCfaRegister(nullptr, HardFP));
373 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
374 .addCFIIndex(CFIIndex);
376 // Mark the FramePtr as live at the beginning of every block except
377 // the entry block. (We'll have marked R11 as live on entry when
379 for (auto I = std::next(MF.begin()), E = MF.end(); I != E; ++I)
380 I->addLiveIn(SystemZ::R11D);
383 // Skip over the FPR saves.
384 SmallVector<unsigned, 8> CFIIndexes;
385 for (auto &Save : CSI) {
386 unsigned Reg = Save.getReg();
387 if (SystemZ::FP64BitRegClass.contains(Reg)) {
388 if (MBBI != MBB.end() &&
389 (MBBI->getOpcode() == SystemZ::STD ||
390 MBBI->getOpcode() == SystemZ::STDY))
393 llvm_unreachable("Couldn't skip over FPR save");
395 // Add CFI for the this save.
396 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
397 unsigned IgnoredFrameReg;
399 getFrameIndexReference(MF, Save.getFrameIdx(), IgnoredFrameReg);
401 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
402 nullptr, DwarfReg, SPOffsetFromCFA + Offset));
403 CFIIndexes.push_back(CFIIndex);
406 // Complete the CFI for the FPR saves, modelling them as taking effect
407 // after the last save.
408 for (auto CFIIndex : CFIIndexes) {
409 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
410 .addCFIIndex(CFIIndex);
414 void SystemZFrameLowering::emitEpilogue(MachineFunction &MF,
415 MachineBasicBlock &MBB) const {
416 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
418 static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
419 SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
421 // Skip the return instruction.
422 assert(MBBI->isReturn() && "Can only insert epilogue into returning blocks");
424 uint64_t StackSize = getAllocatedStackSize(MF);
425 if (ZFI->getLowSavedGPR()) {
427 unsigned Opcode = MBBI->getOpcode();
428 if (Opcode != SystemZ::LMG)
429 llvm_unreachable("Expected to see callee-save register restore code");
431 unsigned AddrOpNo = 2;
432 DebugLoc DL = MBBI->getDebugLoc();
433 uint64_t Offset = StackSize + MBBI->getOperand(AddrOpNo + 1).getImm();
434 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
436 // If the offset is too large, use the largest stack-aligned offset
437 // and add the rest to the base register (the stack or frame pointer).
439 uint64_t NumBytes = Offset - 0x7fff8;
440 emitIncrement(MBB, MBBI, DL, MBBI->getOperand(AddrOpNo).getReg(),
443 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
444 assert(NewOpcode && "No restore instruction available");
447 MBBI->setDesc(ZII->get(NewOpcode));
448 MBBI->getOperand(AddrOpNo + 1).ChangeToImmediate(Offset);
449 } else if (StackSize) {
450 DebugLoc DL = MBBI->getDebugLoc();
451 emitIncrement(MBB, MBBI, DL, SystemZ::R15D, StackSize, ZII);
455 bool SystemZFrameLowering::hasFP(const MachineFunction &MF) const {
456 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
457 MF.getFrameInfo()->hasVarSizedObjects() ||
458 MF.getInfo<SystemZMachineFunctionInfo>()->getManipulatesSP());
461 int SystemZFrameLowering::getFrameIndexReference(const MachineFunction &MF,
463 unsigned &FrameReg) const {
464 const MachineFrameInfo *MFFrame = MF.getFrameInfo();
465 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
467 // Fill in FrameReg output argument.
468 FrameReg = RI->getFrameRegister(MF);
470 // Start with the offset of FI from the top of the caller-allocated frame
471 // (i.e. the top of the 160 bytes allocated by the caller). This initial
472 // offset is therefore negative.
473 int64_t Offset = (MFFrame->getObjectOffset(FI) +
474 MFFrame->getOffsetAdjustment());
476 // Make the offset relative to the incoming stack pointer.
477 Offset -= getOffsetOfLocalArea();
479 // Make the offset relative to the bottom of the frame.
480 Offset += getAllocatedStackSize(MF);
485 uint64_t SystemZFrameLowering::
486 getAllocatedStackSize(const MachineFunction &MF) const {
487 const MachineFrameInfo *MFFrame = MF.getFrameInfo();
489 // Start with the size of the local variables and spill slots.
490 uint64_t StackSize = MFFrame->getStackSize();
492 // We need to allocate the ABI-defined 160-byte base area whenever
493 // we allocate stack space for our own use and whenever we call another
495 if (StackSize || MFFrame->hasVarSizedObjects() || MFFrame->hasCalls())
496 StackSize += SystemZMC::CallFrameSize;
502 SystemZFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
503 // The ABI requires us to allocate 160 bytes of stack space for the callee,
504 // with any outgoing stack arguments being placed above that. It seems
505 // better to make that area a permanent feature of the frame even if
506 // we're using a frame pointer.
510 void SystemZFrameLowering::
511 eliminateCallFramePseudoInstr(MachineFunction &MF,
512 MachineBasicBlock &MBB,
513 MachineBasicBlock::iterator MI) const {
514 switch (MI->getOpcode()) {
515 case SystemZ::ADJCALLSTACKDOWN:
516 case SystemZ::ADJCALLSTACKUP:
517 assert(hasReservedCallFrame(MF) &&
518 "ADJSTACKDOWN and ADJSTACKUP should be no-ops");
523 llvm_unreachable("Unexpected call frame instruction");