1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SPARC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Type.h"
23 #include "llvm/ADT/BitVector.h"
24 #include "llvm/ADT/STLExtras.h"
27 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
28 const TargetInstrInfo &tii)
29 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
30 Subtarget(st), TII(tii) {
33 void SparcRegisterInfo::
34 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
35 unsigned SrcReg, bool isKill, int FI,
36 const TargetRegisterClass *RC) const {
37 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
38 if (RC == SP::IntRegsRegisterClass)
39 BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
40 .addReg(SrcReg, false, false, isKill);
41 else if (RC == SP::FPRegsRegisterClass)
42 BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
43 .addReg(SrcReg, false, false, isKill);
44 else if (RC == SP::DFPRegsRegisterClass)
45 BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
46 .addReg(SrcReg, false, false, isKill);
48 assert(0 && "Can't store this register to stack slot");
51 void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
53 SmallVectorImpl<MachineOperand> &Addr,
54 const TargetRegisterClass *RC,
55 SmallVectorImpl<MachineInstr*> &NewMIs) const {
57 if (RC == SP::IntRegsRegisterClass)
59 else if (RC == SP::FPRegsRegisterClass)
61 else if (RC == SP::DFPRegsRegisterClass)
64 assert(0 && "Can't load this register");
65 MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
66 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
67 MachineOperand &MO = Addr[i];
69 MIB.addReg(MO.getReg());
70 else if (MO.isImmediate())
71 MIB.addImm(MO.getImmedValue());
73 MIB.addFrameIndex(MO.getFrameIndex());
75 MIB.addReg(SrcReg, false, false, isKill);
76 NewMIs.push_back(MIB);
80 void SparcRegisterInfo::
81 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
82 unsigned DestReg, int FI,
83 const TargetRegisterClass *RC) const {
84 if (RC == SP::IntRegsRegisterClass)
85 BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
86 else if (RC == SP::FPRegsRegisterClass)
87 BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
88 else if (RC == SP::DFPRegsRegisterClass)
89 BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
91 assert(0 && "Can't load this register from stack slot");
94 void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
95 SmallVectorImpl<MachineOperand> &Addr,
96 const TargetRegisterClass *RC,
97 SmallVectorImpl<MachineInstr*> &NewMIs) const {
99 if (RC == SP::IntRegsRegisterClass)
101 else if (RC == SP::FPRegsRegisterClass)
103 else if (RC == SP::DFPRegsRegisterClass)
106 assert(0 && "Can't load this register");
107 MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
108 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
109 MachineOperand &MO = Addr[i];
111 MIB.addReg(MO.getReg());
112 else if (MO.isImmediate())
113 MIB.addImm(MO.getImmedValue());
115 MIB.addFrameIndex(MO.getFrameIndex());
117 NewMIs.push_back(MIB);
121 void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
122 MachineBasicBlock::iterator I,
123 unsigned DestReg, unsigned SrcReg,
124 const TargetRegisterClass *DestRC,
125 const TargetRegisterClass *SrcRC) const {
126 if (DestRC != SrcRC) {
127 cerr << "Not yet supported!";
131 if (DestRC == SP::IntRegsRegisterClass)
132 BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
133 else if (DestRC == SP::FPRegsRegisterClass)
134 BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg);
135 else if (DestRC == SP::DFPRegsRegisterClass)
136 BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
139 assert (0 && "Can't copy this register");
142 void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
143 MachineBasicBlock::iterator I,
145 const MachineInstr *Orig) const {
146 MachineInstr *MI = Orig->clone();
147 MI->getOperand(0).setReg(DestReg);
151 MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
152 SmallVectorImpl<unsigned> &Ops,
154 if (Ops.size() != 1) return NULL;
156 unsigned OpNum = Ops[0];
157 bool isFloat = false;
158 MachineInstr *NewMI = NULL;
159 switch (MI->getOpcode()) {
161 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
162 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
163 if (OpNum == 0) // COPY -> STORE
164 NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
165 .addReg(MI->getOperand(2).getReg());
167 NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
168 .addFrameIndex(FI).addImm(0);
175 if (OpNum == 0) // COPY -> STORE
176 NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
177 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
179 NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
180 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
185 NewMI->copyKillDeadInfo(MI);
189 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
191 static const unsigned CalleeSavedRegs[] = { 0 };
192 return CalleeSavedRegs;
195 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
196 BitVector Reserved(getNumRegs());
197 Reserved.set(SP::G2);
198 Reserved.set(SP::G3);
199 Reserved.set(SP::G4);
200 Reserved.set(SP::O6);
201 Reserved.set(SP::I6);
202 Reserved.set(SP::I7);
203 Reserved.set(SP::G0);
204 Reserved.set(SP::G5);
205 Reserved.set(SP::G6);
206 Reserved.set(SP::G7);
211 const TargetRegisterClass* const*
212 SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
213 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
214 return CalleeSavedRegClasses;
217 bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
221 void SparcRegisterInfo::
222 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
223 MachineBasicBlock::iterator I) const {
224 MachineInstr &MI = *I;
225 int Size = MI.getOperand(0).getImmedValue();
226 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
229 BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
233 void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
234 int SPAdj, RegScavenger *RS) const {
235 assert(SPAdj == 0 && "Unexpected");
238 MachineInstr &MI = *II;
239 while (!MI.getOperand(i).isFrameIndex()) {
241 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
244 int FrameIndex = MI.getOperand(i).getFrameIndex();
246 // Addressable stack objects are accessed using neg. offsets from %fp
247 MachineFunction &MF = *MI.getParent()->getParent();
248 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
249 MI.getOperand(i+1).getImmedValue();
251 // Replace frame index with a frame pointer reference.
252 if (Offset >= -4096 && Offset <= 4095) {
253 // If the offset is small enough to fit in the immediate field, directly
255 MI.getOperand(i).ChangeToRegister(SP::I6, false);
256 MI.getOperand(i+1).ChangeToImmediate(Offset);
258 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
259 // scavenge a register here instead of reserving G1 all of the time.
260 unsigned OffHi = (unsigned)Offset >> 10U;
261 BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
263 BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
265 // Insert: G1+%lo(offset) into the user.
266 MI.getOperand(i).ChangeToRegister(SP::G1, false);
267 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
271 void SparcRegisterInfo::
272 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
274 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
275 MachineBasicBlock &MBB = MF.front();
276 MachineFrameInfo *MFI = MF.getFrameInfo();
278 // Get the number of bytes to allocate from the FrameInfo
279 int NumBytes = (int) MFI->getStackSize();
281 // Emit the correct save instruction based on the number of bytes in
282 // the frame. Minimum stack frame size according to V8 ABI is:
283 // 16 words for register window spill
284 // 1 word for address of returned aggregate-value
285 // + 6 words for passing parameters on the stack
287 // 23 words * 4 bytes per word = 92 bytes
289 // Round up to next doubleword boundary -- a double-word boundary
290 // is required by the ABI.
291 NumBytes = (NumBytes + 7) & ~7;
292 NumBytes = -NumBytes;
294 if (NumBytes >= -4096) {
295 BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
296 SP::O6).addImm(NumBytes).addReg(SP::O6);
298 MachineBasicBlock::iterator InsertPt = MBB.begin();
299 // Emit this the hard way. This clobbers G1 which we always know is
301 unsigned OffHi = (unsigned)NumBytes >> 10U;
302 BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
304 BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
305 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
306 BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
307 .addReg(SP::O6).addReg(SP::G1);
311 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
312 MachineBasicBlock &MBB) const {
313 MachineBasicBlock::iterator MBBI = prior(MBB.end());
314 assert(MBBI->getOpcode() == SP::RETL &&
315 "Can only put epilog before 'retl' instruction!");
316 BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
320 unsigned SparcRegisterInfo::getRARegister() const {
321 assert(0 && "What is the return address register");
325 unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
326 assert(0 && "What is the frame register");
330 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
331 assert(0 && "What is the exception register");
335 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
336 assert(0 && "What is the exception handler register");
340 int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
341 assert(0 && "What is the dwarf register number");
345 #include "SparcGenRegisterInfo.inc"